Si5338 Data Sheet

Si5338 Data Sheet

S i 5 3 3 8

I

2

C - P

R O G R A M M A B L E

A

N Y

- R

A T E

, A

N Y

- O

U T P U T

Q

U A D

C

L O C K

G

E N E R A T O R

Features

Low power MultiSynth technology enables independent, any-rate

 frequency synthesis on four differential  output drivers

Highly-configurable output drivers support up to four differential outputs or eight single-ended clock outputs or a combination of both

Low phase jitter of 0.7 ps RMS typ

High precision synthesis allows true zero ppm frequency accuracy on all outputs

Flexible input reference:



External crystal: 8 to 30 MHz



CMOS input: 5 to 200 MHz



SSTL/HSTL input: 5 to 350 MHz



Differential input: 5 to 710 MHz

Independently configurable outputs support any frequency or format:



LVPECL/LVDS: 0.16 to 710 MHz



HCSL: 0.16 to 250 MHz



CMOS: 0.16 to 200 MHz



SSTL/HSTL: 0.16 to 350 MHz

Independent output voltage per driver:

1.5, 1.8, 2.5, or 3.3 V

Independent core supply voltage:

1.8, 2.5, 3.3 V

Independent Frequency increment/ decrement feature enables glitchless frequency adjustments in

1 ppm steps

Independent phase adjustment on each of the output drivers with an accuracy of <20 ps steps

Highly configurable spread spectrum on any output:



Any frequency from 5 to 350 MHz



Any spread from 0.5 to 5.0%



Any modulation rate from 33 to

63 kHz

External feedback mode allows zero-delay buffer implementation

Loss of lock and loss of signal alarms

I

2

C/SMBus compatible interface

Easy to use programming software

Small size: 4 x 4 mm, 24-QFN

Low power: 45 mA core supply typ

Wide temperature range: –40 to

+85 °C

IN1

IN2

IN3

IN4

IN5

IN6

Ordering Information:

See page 32.

Pin Assignments

Top View

CLK1A

CLK1B

VDDO1

VDDO2

CLK2A

CLK2B

Applications

Gigabit Ethernet

PCI Express 2.0

OC-3/12, SFI-5

Processor, memory clocking

Broadcast video xDSL

PON

T1/E1

Description

The Si5338 is a high performance, low jitter clock generator capable of synthesizing any frequency on each of the device's four output drivers. The device is capable of operating in asynchronous mode for replacing free-running crystal oscillators (XO), or in a synchronous mode for translating any frequency to any other frequency within its supported frequency range. Using its patented

MultiSynth technology, the Si5338 allows generation of four independent clocks with 0 ppm precision. Each output clock is independently configurable to support any of the supported signal format and supply voltages. The Si5338 provides low jitter frequency synthesis with outstanding frequency flexibility in a space-saving

4 x 4 mm QFN package. The device is programmable via an I

2

C/SMBuscompatible serial interface and supports operation from a 1.8, 2.5, or 3.3 V core supply.

Rev. 0.5 10/09 Copyright © 2009 by Silicon Laboratories Si5338

S i 5 3 3 8

Functional Block Diagram

Osc

IN1

IN2

IN3

IN4

IN5

IN6

CLKIN

CLKINB

CLKIN

FDBK

FDBK

FDBKB

SCL

SDA

INTR

÷P1

Input

Selector

÷P2

Analog Phase-Locked Loop

ref fb

Phase

Frequency

Detector

Loop

Filter

VCO

MultiSynth

÷N

OEB/PINC/FINC

I2C_LSB/PDEC/FDEC

Control

NVM

(OTP)

RAM

MultiSynth

÷M0

Output

Selectors

÷

R0

MultiSynth

÷M1

÷

R1

MultiSynth

÷M2

MultiSynth

÷M3

÷

÷

R2

R3

VDDO0

CLK0A

CLK0B

VDDO1

CLK1A

CLK1B

VDDO2

CLK2A

CLK2B

VDDO3

CLK3A

CLK3B

2 Rev. 0.5

Si5338

T

A B L E O F

C

O N T E N TS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8. Useful Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5. I

2

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Rev. 0.5

3

4

S i 5 3 3 8

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85°C)

Parameter

Ambient Temperature

Core Supply Voltage

Symbol

V

T

A

DD

Test Condition Min

–40

2.97

2.25

1.71

Typ

25

3.3

2.5

1.8

Max

85

3.63

2.75

1.98

Unit

°C

V

V

V

Output Buffer Supply

Voltage

V

DDOn

1.4

— 3.63

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. Absolute Maximum Ratings

Parameter Symbol Test Condition Value Unit

DC Supply Voltage

Storage Temperature Range

ESD Tolerance

V

DD

T

STG

HBM

(100 pF, 1.5 k

)

CDM

–0.5 to 3.8

–55 to 150

2.5

V

°C kV

ESD Tolerance

ESD Tolerance

Latch-up Tolerance

MM

550

175

V

V

JESD78 Compliant

Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 3. Thermal Characteristics

Parameter

Thermal Resistance

Junction to Ambient

Symbol

Theta JA

Test Condition

Still Air

Value

37

Unit

°C/W

Rev. 0.5

Si5338

Table 4. DC Characteristics

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85°C)

Parameter

Core Supply Current*

Symbol

I

DD

Test Condition

100 MHz on all outputs,

25 MHz refclk

LVPECL, 710 MHz

Output Buffer Supply Current I

DDOx

LVDS, 710 MHz

HCSL, 250 MHz

2 pF load capacitance

SSTL, 350 MHz

CMOS, 50 MHz

15 pF load capacitance

CMOS, 200 MHz

2 pF load capacitance

HSTL, 350 MHz

Min

Typ

45

*Note: Output Supply Voltage = 3.63 V. The supply current is considerably lower for lower supply voltage.

Max

60

19

28

28

19

30

8

20

Unit

mA mA mA mA mA mA mA mA

Rev. 0.5

5

6

S i 5 3 3 8

Table 5. Performance Characteristics

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85°C)

Parameter

Symbol Test Condition Min

APLL Acquisition Time

APLL Lock Range

APLL Loop Bandwidth t

ACQ f

LOCK f

BW f

RES

5000

MultiSynth Frequency

Synthesis Resolution

CLKIN Loss of Signal Detect

Time

CLKIN Loss of Signal Release

Time

APLL Loss of Lock Detect Time t t

LOS

LOSRLS

Output frequency < Fvco/8 0

0.01

t

LOL

Clock multiplication ratio off by 1000 ppm

Reset Time t

RST

POR to Output Clock Valid

(Pre-programmed Devices)

Input-to-Output Propagation

Delay

Output-Output Skew t t t

RDY

PROP

DSKEW

Buffer Mode

(APLL Bypass)

Outputs at same frequency, signal format

Programmable Initial

Phase Offset

Phase Increment/Decrement

Accuracy

Phase Increment/Decrement

Range

P

P

P

OFFSET

STEP

RANGE

Frequency range for phase increment/decrement

Phase Increment/Decrement

Update Rate f

P

PRANGE

UPDATE

Pin control

2,3

Frequency Increment/

Decrement Step Size f

STEP

R divider not used

Notes:

1. Keep MultiSynth output frequency between 5 MHz to Fvco/8.

2. Maximum frequency is Fvco/8.

3. Update rate via I

2

C is limited by the time it takes to perform a write operation.

4. Default value is.5% down spread.

5. Default value is ~31.5 kHz

–45

–45

1

Typ

1.6

0

2.6

0.2

5

2.5

5

1

10

100

+45

20

1500

See

Note

1

Max

25

1

2

2

+45

350

1

Unit

ms ppm

MHz ppb

µs

µs ms ms ms ns ps ns ps ns

MHz kHz ppm

Rev. 0.5

Si5338

Table 5. Performance Characteristics (Continued)

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85°C)

Parameter

Frequency Increment/

Decrement Range

Frequency Increment/

Decrement Update Rate

Spread Spectrum PP

Frequency Deviation

Symbol

f f

RANGE

UPDATE

SS

DEV

Test Condition

R divider not used

Pin control

1,2

MultiSynth Output < ~Fvco/8

Min

5

0.1

Spread Spectrum Modulation

Rate

SS

DEV

MultiSynth Output < ~Fvco/8

Notes:

1. Keep MultiSynth output frequency between 5 MHz to Fvco/8.

2. Maximum frequency is Fvco/8.

3. Update rate via I

2

C is limited by the time it takes to perform a write operation.

4. Default value is.5% down spread.

5. Default value is ~31.5 kHz

30

Typ

Max

350

1

1500

5.0

4

63

5

Unit

MHz kHz

% kHz

Table 6. Input and Output Clock Characteristics

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter Symbol Test Condition Min

Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)

Frequency f

IN

5

Differential Voltage

Swing

V

PP

710 MHz input 0.4

Rise/Fall Time

Duty Cycle t

R

/t

F

DC

20%–80%

< 1 ns tr/tf

40

Input Impedance

Input Capacitance

R

IN

C

IN

Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)

10

Frequency f

IN

V

I

CMOS

SSTL/HSTL

5

5

–0.1

Input Voltage

Input Voltage Swing

(CMOS Standard)

Rise/Fall Time

Duty Cycle

Input Capacitance t

R

DC

C

/t

F

IN

200 MHz, Tr/Tf = 1.3 ns

20%–80%

< 4 ns tr/tf

0.8

40

Typ

2

3.5

Max Units

200

350

3.63

3.73

4

60

710

2.4

1.0

60

MHz

MHz

Vpp

V ns

% pF

MHz

V

PP ns

% k

 pF

Rev. 0.5

7

8

S i 5 3 3 8

Table 6. Input and Output Clock Characteristics (Continued)

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter Symbol

Output Clocks (Differential)

Test Condition Min

Frequency f

OUT

LVPECL, LVDS

HCSL

0.16

367

550

0.16

V

OC common mode —

LVPECL Output Voltage

LVDS Output Voltage

(2.5/3.3 V)

LVDS Output Voltage

(1.8 V)

HCSL Output Voltage

Rise/Fall Time

Duty Cycle

V

SEPP

V

OC

V

SEPP

V

OC

V

SEPP

V

OC

V

SEPP t

R

/t

F

DC peak-to-peak singleended swing common mode peak-to-peak singleended swing common mode peak-to-peak singleended swing common mode peak-to-peak singleended swing

20%–80%

CKn < 350 MHz

350 MHz < CLKn <

710 MHz

0.55

1.125

0.25

0.8

0.25

0.35

0.575

45

40

Output Clocks (Single-Ended)

Frequency f

OUT t

R

/t

F

CMOS

SSTL, HSTL

2 pF load

0.16

0.16

CMOS 20%-80% Rise/

Fall Time

CMOS 20%-80% Rise/

Fall Time

CMOS Output Resistance

SSTL Output Resistance

HSTL Output Resistance t

R

/t

F

15 pF load —

VDDO–.3

CMOS Output Voltage

V

OH

V

OL

4 mA load

4 mA load

0.45

50

50

50

Typ

V

DDO

1.4 V

0.8

1.2

0.35

0.875

0.35

0.375

0.725

Max Units

V

PP

V

V

PP ps

%

%

V

PP

V

V

PP

V

MHz

MHz

MHz

MHz

V

0.96

1.275

0.45

0.95

0.45

0.400

0.85

450

55

60

350

466

710

250

200

350

0.85

1.7

.3

MHz

MHz ns ns

V

V

Rev. 0.5

Si5338

Table 6. Input and Output Clock Characteristics (Continued)

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter Symbol

V

OH

V

OL

Test Condition Min

SSTL-3 VDDOx = 2.97 to 3.63 V

.45xVDDO+.41

SSTL Output Voltage

SSTL-2 VDDOx = 2.25 to 2.75 V

0.5xVDDO+.41

HSTL Output Voltage

Duty Cycle

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

DC

SSTL-18 VDDOx = 1.71 to 1.98 V

0.5xVDDO+.34

VDDO = 1.4 to 1.6 V

0.5xVDDO +.3

45

Typ

Max

.45xVDDO

–.41

Units

V

V

0.5xVDDO

–.41

V

V

V

0.5xVDDO

–.34

.5xVDDO

–.3

55

V

V

V

%

Rev. 0.5

9

S i 5 3 3 8

Table 7. Control Pins

Parameter

Input Control Pins (IN3, IN4)

Input Voltage Low

Input Voltage High

Input Capacitance

Input Resistance

Output Control Pins (INTR)

Output Voltage Low

Rise/Fall Time

20–80%

Symbol

V

IL

V

IH

C

IN

R

IN

V

OL t

R

/t

F

Condition

I

SINK

= 3 mA

C

L

< 10 pf, pull up

1 k

Table 8. Crystal Specifications for 8 to 11 MHz

Parameter

Crystal Frequency

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level Spec

Symbol

f

XTAL c

L c

O r

ESR d

L

Table 9. Crystal Specifications for 11 to 19 MHz

Parameter

Crystal Frequency

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level Spec

Symbol

f

XTAL c

L c

O r

ESR d

L

Min

8

11

100

Min

11

11

100

Typ

–0.1

0.9

20

0

Typ

12

Typ

12

Max

0.4

10

Max

11

13

6

300

Max

19

13

5

200

0.3

3.63

4

Unit

Unit

MHz pF pF

µW

Unit

MHz pF pF

µW

V

V pF k

V ns

10 Rev. 0.5

Si5338

Table 10. Crystal Specifications for 19 to 26 MHz

Parameter

Crystal Frequency

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level Spec

Symbol

f

XTAL c

L c

O r

ESR d

L

Table 11. Crystal Specifications for 26 to 30 MHz

Parameter

Crystal Frequency

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level Spec

Symbol

f

XTAL c

L c

O r

ESR d

L

Min

19

11

100

Typ

12

Max

26

13

4

100

Unit

MHz pF pF

µW

Min

26

11

100

Typ

12

Max

30

13

4

75

Unit

MHz pF pF

µW

Rev. 0.5

11

S i 5 3 3 8

Table 12. Jitter Specifications

1

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter Symbol

GbE Random Jitter

(12 kHz–20 MHz)

2

J

GBE

Test Condition

CLKIN = 25 MHz

All CLKn at 125 MHz

3

Min

Typ

0.7

Max

1

Unit

ps RMS

OC-12 Random Jitter

(12 kHz–5 MHz)

J

OC12

CLKIN = 19.44 MHz

All CLKn at

155.52 MHz

3

— 0.7

1 ps RMS

PCI Express 3.0

Random Jitter

(1.5 MHz—50 MHz)

2

PCI Express 3.0

Random Jitter

(12 kHz—20 MHz)

2

PCI Express 3.0

Period Jitter

PCI Express 3.0

Cycle-Cycle Jitter

J

J

PCIERJ1

PCIERJ2

CLKIN = 25 MHz

All CLKn at 100 MHz

Spread Spectrum not

enabled

3

CLKIN = 25 MHz

All CLKn at 100 MHz

Spread Spectrum not

enabled

3

CLKIN = 25 MHz

All CLKn at 100 MHz

Spread Spectrum not

enabled

3

CLKIN = 25 MHz

All CLKn at 100 MHz

Spread Spectrum not

enabled

3

0.6

0.7

8

13

1

1

15

30 ps RMS ps RMS ps pk-pk ps pk-pk

Period Jitter

J

PER

N = 10,000 cycles

4

— 10 30 ps pk-pk

Cycle-Cycle Jitter

Random Jitter

(12 kHz–20 MHz)

J

CC

R

J

N = 10,000 cycles

Output MultiSynth operated in Integer or

Fractional mode.

4

Output and feedback

MultiSynth in Integer or

fractional mode

4

17

0.7

50

1.5

ps pk-pk ps RMS

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. D

J

for PCI and GBE is < 5 ps pp

3. Output MultiSynth in Integer mode.

4. Input frequency > 25 Mhz and any output frequency > 5 MHz.

5. Rj is multiplied by 14; estimate the pp jitter from Rj over 2

12

rising edges.

12 Rev. 0.5

Si5338

Table 12. Jitter Specifications

1

(Continued)

(V

DD

= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Output MultiSynth operated in fractional

mode

4

— 3 15 ps pk-pk

Deterministic Jitter

D

J

Output MultiSynth operated in integer

mode

4

Output MultiSynth operated in fractional

mode

4

2

13

10

36 ps pk-pk ps pk-pk

Total Jitter

(12 kHz–20 MHz)

T

J

= D

J

+14xR

(See Note

5

)

J

Output MultiSynth operated in integer

mode

4

— 12 20 ps pk-pk

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. D

J

for PCI and GBE is < 5 ps pp

3. Output MultiSynth in Integer mode.

4. Input frequency > 25 Mhz and any output frequency > 5 MHz.

5. Rj is multiplied by 14; estimate the pp jitter from Rj over 2

12

rising edges.

Rev. 0.5

13

S i 5 3 3 8

Table 13. I

2

C Specifications (SCL,SDA)

2

Parameter Symbol Test Condition Standard Mode

Fast Mode

3

Unit

LOW level input voltage:

HIGH level input voltage:

V

V

ILI2C

IHI2C

Min

0.7 x V

DDI2C

Max Min

3.63 0.7 x V

DDI2C

1

Max

DDI2C

1

3.63

V

V

Hysteresis of

Schmitt trigger inputs

LOW Level Output Voltage (open drain or open collector) at 3 mA

Sink Current

Input Current

V

V

HYS

OLI2C

1

V

DDI2C

1

V

DDI2C

= 2.5/3.3 V

1

= 1.8 V

N/A

N/A

N/A

N/A

0.1

0

0 0.4 0 0.4

0.2 x V

DDI2C

V

V

V

Capacitance for

Each I/O Pin

I

2

C Bus Timeout

I

II2C

C

II2C

V

IN

= –0.1 to V

DDI2C

Timeout Enabled

–10 10 –10 10

25

4

35

25

4

35

µA pF ms

Notes:

1. Only I

2

C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I

2

C bus voltage is less than 2.5 V to maintain compatibility with the I

2

C bus standard.

2. Refer to NXP’s UM10204 I

2

C-bus specification and user manual, revision 03, for further details: www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.

3. Compliant with Fast Mode+ pending characterization.

14 Rev. 0.5

Si5338

2. Typical Application Circuits

0.1 uF Power Supply

Decoupling Capacitors

(1 per VDD or VDDOx pin)

Optional XTAL for

Free-run Applications

27 MHz

XTAL

Single-ended or

Differential Inputs for Synchronous

Applications

27MHz

74.25MHz

74.25/1.001 MHz

148.5MHz

148.5/1.001MHz

100

+3.3V

1k 1k 1k

I

2

C Bus

I

2

C Address = 0x70 or 0x71

+3.3 V

7 24 20 16 15 11

1

IN1

2

IN2

3

IN3

5

IN5

6

IN6

CLK0

CLK1

Si5338C

CLK2

CLK3

18

17

22

21 x

CLK4

CLK5

14 x

13 x

8

19

12

INTR

SDA

SCL

4

I2C_LSB

CLK6

CLK7

10

9 x

23

PAD

SD/HD/3G

SDI IN

SD/HD/3G-SDI

Video/Audio

Format Converter

SDI

Deserializer

Video

Processor

SDI

Serializer

SD/HD/3G

SDI OUT

100 MHz

74.25MHz, 74.25/1.001MHz

148.5MHz, 148.5/1.001MHz

100

Audio

Processor

24.576MHz / 6.144 MHz

Audio Out

IN3

Storage Area

Network

0.1 uF Power Supply

Decoupling Capacitors

(1 per VDD or VDDOx pin)

25 MHz

XTAL

+3.3V

1k 1k 1k

I

2

C Bus

I

2

C Address = 0x70 or 0x71

+3.3 V disk

SAS2

4/8 Port

Controller disk

7 24 20 16 15 11 disk

1

IN1

2

IN2

3

IN3 x

5

IN5

6

IN6

8

19

12

INTR

SDA

SCL

4

I2C_LSB

CLK0

CLK1

22

21

Si5338C

CLK2

CLK3

18

17 x

CLK4

CLK5

14

13 x

CLK6

CLK7

10

9 x disk

37.5/75/120/150MHz

SAS2

4/8 Port

Controller

100MHz

66MHz

PCIe

Switch

Network

Processor

Ethernet

Fiber

Channel

106.25MHz

Rev. 0.5

15

S i 5 3 3 8

3. Functional Description

Osc

Input

Stage

IN1

IN2

IN3

CLKIN

CLKINB

CLKIN

IN4

IN5

IN6

SCL

SDA

INTR

÷P1 ref

FDBK

FDBK

FDBKB

÷P2

Control & Memory

OEB/PINC/FINC

I2C_LSB/PDEC/FDEC

Control

NVM

(OTP)

RAM fb

VDD

Synthesis

Stage 1

(APLL)

Phase

Frequency

Detector

Loop

Filter

VCO

MultiSynth

÷N

Synthesis

Stage 2

MultiSynth

÷M0

MultiSynth

÷M1

MultiSynth

÷M2

MultiSynth

÷M3

Output

Stage

÷

R0

÷

R1

÷ R2

÷

R3

Figure 1. Si5338 Block Diagram

3.1. Overview

The Si5338 is a high performance, low jitter clock generator capable of synthesizing four independent user-programmable clock frequencies up to 350 MHz and select frequencies up to 710 MHz. The device supports free-run operation using an external crystal, or it can lock to an external clock for generating synchronous clocks. The output drivers support four differential clocks, or eight single-ended clocks, or a combination of both. The output drivers are configurable to support common signal formats such as LVPECL,

LVDS, HCSL, CMOS, HSTL, and SSTL. Separate output supply pins are available for generating 3.3, 2.5,

1.8, and 1.5 V signal levels. The core voltage supply accepts 3.3, 2.5, or 1.8 V and is independent from the output supplies.

Using its two stage synthesis architecture and patented high-resolution MultiSynth technology, the Si5338 can generate four independent frequencies from a single input frequency. In addition to clock generation, the inputs can bypass the synthesis stage enabling its use as a high-performance clock buffer, or as a combination of a buffer and generator.

For applications that need fine frequency adjustments

(i.e. clock margining), each of the synthesized frequencies can be incremented or decremented in user defined steps as low as 1 ppm per step. Output-tooutput phase delays are also adjustable in user defined steps as low as 20 ps per step to compensate for PCB trace delays or for fine tuning of set-up and hold margins. A zero-delay buffer mode is also available to help minimize input-to-output delay. Spread spectrum is available on each of the clock outputs for EMI sensitive applications such as PCI Express.

Configuration and control of the Si5338 is mainly handled through the I

2

C/SMBus interface. Some features such as output enable, frequency or phase adjustments can optionally be pin controlled. The device has a maskable interrupt pin which can be monitored for loss of lock or loss of input signal conditions.

The device also provides the option of storing a user definable clock configuration in its non-volatile memory

(NVM) which becomes the default clock configuration at power-up. Changes to the default configuration can always be made through the I

2

C interface.

The Si5338 brings unprecedented flexibility and easy of use to high performance clock generation and distribution applications.

VDDO0

CLK0A

CLK0B

VDDO1

CLK1A

CLK1B

VDDO2

CLK2A

CLK2B

VDDO3

CLK3A

CLK3B

16 Rev. 0.5

Si5338

3.2. Input Stage

The input stage supports four inputs. Two are used as the clock inputs to the synthesis stage and the other two are used as feedback inputs for zero delay or external feedback mode. In cases where external feedback is not required, all four input are available to the synthesis stage. The reference selector selects one of the inputs as the reference to the synthesis stage. The input configuration is selectable through the I

C interface.

common single-ended signals such as CMOS, HSTL,

and SSTL. Refer to Table 6 for signal voltage limits. A

typical single-ended connection is shown in Figure 3.

Refer to application note AN408 for additional termination options.

For free-run operation, the internal oscillator can operate from a low frequency fundamental mode crystal

(XTAL) with a resonant frequency between 8 and

30 MHz. A crystal can easily be connected to pins IN1 and IN2 without external components as shown in

Figure 4.

IN1

IN2

IN3

Clock

Inputs

CLKIN

CLKINB

CLKIN

Osc

Input

Stage

osc ref

÷P1 refdiv

Reference

Selector

ref

XTAL

IN1

IN2

Osc

To synthesis stage or output selectors

IN4

IN5

IN6

FDBK

FDBK

FDBKB fb

÷P2 fbdiv fb

Feedback

Inputs

Figure 2. Input Stage

IN1/IN2 and IN5/IN6 are differential inputs which are capable of accepting clock rates ranging from 5 MHz to

710 MHz. The differential inputs are capable of interfacing to multiple signals such as LVPECL, LVDS,

HSCL, and CML. Differential signals must be AC

coupled as shown in Figure 3. A termination resistor of

100 Ohms placed close to the input pins is also

required. Refer to Table 6 for signal voltage limits.

Figure 4. Connecting an XTAL to the Si5338

Refer to application note AN360 for recommended

XTAL components.

3.3. Synthesis Stages

Synthesis of the output clocks is performed in two

stages as shown in Figure 5. The first stage is a high

frequency analog phase-locked loop (APLL) which multiplies the input stage clock to a frequency within the range of 2.2 GHz to 2.8 GHz. Multiplication of the input frequency is accomplished using a proprietary and highly precise MultiSynth feedback divider (N) which allows the APLL to generate any frequency within its

VCO range with less jitter than typical fractional N dividers.

Rs

50

50

100

0.1 uF

0.1 uF

IN1 / IN5

IN2 / IN6

50 IN3 / IN4

Figure 3. Interfacing Differential and Single-

Ended Signals to the Si5338

IN3 and IN4 accept single-ended signals from 5 MHz to

200 MHz (CMOS) or 350 MHz (SSTL, HSTL). The single-ended inputs are internally AC coupled so they can accept a wide variety of signals without requiring a specific DC level. The input signal only needs to meet a minimum voltage swing which makes it compatible with ref fb

Phase

Frequency

Detector

Synthesis

Stage 1

(APLL)

2.2-2.8

GHz

Loop

Filter

VCO

MultiSynth

÷N

Synthesis

Stage 2

MultiSynth

÷M0

MultiSynth

÷M1

MultiSynth

÷M2

MultiSynth

÷M3

Figure 5. Synthesis Stages

Rev. 0.5

17

S i 5 3 3 8

The second stage of synthesis consist of four additional highly precise MultiSynth output dividers (M0, M1, M2,

M3) which ultimately determines the output clock frequencies. Using this two stage technique, the Si5338 can generate four independent output clocks with any frequency between the range of 5 to 350 MHz and select ranges up to 710 MHz with 0 ppm accuracy.

3.4. Output Stage

The output stage consists of output selectors, output dividers, and programmable output drivers as shown in

Figure 6.

configured to stop high, low, or tri-state when the APLL has lost lock. Each of the outputs can also be enabled or disabled through the I

2

C port.

3.5. Configuring the Si5338

The Si5338 is a highly flexible clock generator which is entirely configurable through its I

2

C interface. The device’s default configuration is stored in non-volatile

memory (NVM) as shown in Figure 7. The NVM is a one

time programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for applications that need a clock present at power-up (e.g. for providing a clock to a processor).

Output

Stage

Power-Up/POR

÷

R0

VDDO0

CLK0A

CLK0B

÷

R1

÷ R2

VDDO1

CLK1A

CLK1B

VDDO2

CLK2A

CLK2B

NVM

(OTP)

Default

Config

RAM

÷

R3

VDDO3

CLK3A

CLK3B

Figure 6. Output Stage

The output selectors select the clock source for the output drivers. By default, each output driver is connected to its own MultiSynth block (e.g. M0 to CLK0,

M1 to CLK1, etc), but other combinations are possible by reconfiguring the device. Any of the output drivers can also connect to any of the clocks in the input stage

(osc, ref, refdiv, fb, or fbdiv) effectively bypassing the synthesis stages. Each of the output drivers can also connect to the first MultiSynth block (M0) enabling a fan-out function. This allows the Si5338 to act as a clock generator, a fanout buffer, or a combination of both in the same package.

The output dividers (R0, R1, R2, R3) allow another stage of clock division.These dividers are configurable as divide by 1 (default), 2, 4, 8, 16, or 32.

The output drivers are configurable to support common signal formats such as LVPECL, LVDS, HCSL,

CMOS, HSTL, and SSTL. Separate output supply pins

(VDDO n

) are available for generating 3.3, 2.5, 1.8, and

1.5 V signal levels. Additionally, the outputs can be

I

2

C

Figure 7. Si5338 Memory Configuration

During a power cycle or a power-on reset (POR) the contents of the NVM are copied into random access memory (RAM) which is where the device operates from. Any changes to the device’s configuration after power up is made by reading and writing to registers in the RAM space through the I

2

C interface.

3.5.1. Configuring the Si5338 by Writing to RAM

The Any Rate Clock Generator Software available from the Silicon Labs web site (www.silabs.com) provides an easy to use Graphical User Interface (GUI) to help set the input configuration, the APLL and MultiSynth parameters, output configuration, and other miscellaneous features and functions. The GUI generates a new register map file which can be written to RAM through the I

2

C port. Writing the new configuration to RAM must be done after every power cycle or a manual power-on reset (POR) cycle.

18 Rev. 0.5

Si5338

3.5.2. Configuring the Si5338 by Writing to NVM

An alternative to writing the device configuration to RAM after every power cycle is to write directly to the NVM.

Writing to NVM only has to be done once and becomes the default configuration after every power cycle or

POR. Writing to NVM is easily done using the Si5338 field programmer (Si5338-PROG-EVB). NVM is an OTP memory, so it can only be written once. Alternatively, parts can be pre-ordered with a custom NVM default configuration.

3.5.3. Changing the Default Configuration

Once the configuration is stored in RAM it is always modifiable by directly writing to individual registers. An example could be selecting a new reference input, configuring a new output frequency, etc. A full Si5338 software register map is available from the Silicon Labs web site. The register map of the Si5338 is addressable as two memory pages each containing 256 8-bit

registers as shown in Figure 8. For more information on

configuring the Si5338, please refer to application note

AN411.

Page 0

0

255

(256)

(347)

Input

Configuration

PLL

Configuration

MultiSynth

Configuration

Output

Configuration

Frequency Inc/Dec

Configuration

Device Control and Status

Page Select

Spread Spectrum

Configuration

3.6. Status Indicators

An interrupt pin (INTR) is available to indicate a loss of signal (LOS) condition, a APLL loss of lock (LOL) condition, or that the APLL is in process of acquiring

lock (SYS_CAL). As shown in Figure 9, a status register

at address 218 is available to help identify the exact event that caused the interrupt pin to become active.

218

7 6 5 4

LOL

3 2

LOS

Fdbk

LOS

Clk

1 0

Sys

Cal

System Calibration

(Lock Acquisition)

Loss Of Signal

Clock Input

Loss Of Signal

Feedback Input

Loss Of Lock

Figure 9. Status Register

The INTR pin provides a useful status indicator for systems that have access to the I

2

C interface, and for

systems that do not. Figure 10 shows a typical

connection with the required pull-up resistor to VDD.

3.6.1. Using the INTR pin in Systems with I

2

C

For systems that use the I

2

C interface for system monitoring, the INTR pin provides a convenient fault indicator for a processor. Once the interrupt pin becomes active, the processor can identify its trigger by reading the status register. Each of the status bits can be individually masked to prevent them from causing an interrupt. The status mask register is located at address

6.

3.6.2. Using the INTR pin in Systems without I

2

C

The INTR pin also provides a useful function in systems that require a pin controlled fault indicator. Pre-setting the interrupt mask register allows the INTR pin to become an indicator for a specific event such as LOS and/or LOL. Therefore the INTR pin can be used to indicate a single fault event, or even multiple events.

Page 1

Reserved

1k

V

DD

INTR

Control & Memory

Control

NVM

(OTP)

RAM

(512)

Figure 8. Si5338 Memory Map (RAM) Figure 10. INTR pin with required pull-up

Rev. 0.5

19

S i 5 3 3 8

3.7. Output Enable

There two methods of enabling and disabling the output drivers: Pin control, and I

2

C control.

3.7.1. Enabling Outputs Using Pin Control

The Si5338K/L/M devices provide an Output Enable pin

(OEB) as shown in Figure 11. Pulling this pin high will

tri-state all four output drivers.

0 = Enabled

1 = Disabled

OEB

Figure 11. Output Enable Pin (Si5338K/L/M)

3.7.2. Enabling Outputs Through the I2C Interface

Output enable can be controlled through the I

2

C

interface. As shown in Figure 12, register 230[3:0]

allows control of each individual output driver. Register

230[4] controls all drivers at once. Registers 110[7:6],

114[7:6], 118[7:6], 112[7:6] control the output disabled state as tri-state, low, high, or always on.

230

110

114

118

122

7 6

0 = enable

1 = disable

7 6

CLK0 OEB

State

5

7 6

CLK1 OEB

State

5

7 6

CLK2 OEB

State

5

7 6

CLK3 OEB

State

5

5 4 3 2 1 0

OEB

All

OEB

3

OEB

2

OEB

1

OEB

0

00 = disabled tri-state

01 = disabled low

10 = disabled high

11 = always enabled

4

4

4

4

Control

NVM

(OTP)

RAM

Bits reserved

3

3

3

3

2

2

2

2

1

1

1

1

0

0

0

0

Bits used by other functions

3.8. Useful Features of the Si5338

The Si5338 offers several features and functions which are useful in many timing applications. The following paragraphs describes the main features in detail and typical applications.

3.8.1. Frequency Increment/Decrement

Each of the output clock frequencies can be independently stepped up or down in pre-defined steps as low as 1 ppm per step. Setting of the step size and control of the frequency increment or decrement is accomplished through the I

2

C interface. Alternatively, the Si5338 can be ordered with optional frequency increment (FINC) and frequency decrement (FDEC)

pins for pin controlled applications. See Table 15 for

ordering information of pin controlled devices.

The frequency increment and decrement feature is useful in applications that require a variable clock frequency (e.g. CPU speed control, FIFO overflow management, etc...) or in applications where frequency margining (e.g. f out

+/-5%) is necessary for design verification and manufacturing test. Frequency steps are seamless and glitchless.

3.8.2. Output Phase Increment/Decrement

The Si5338 has a digitally-controlled glitchless phase increment and decrement feature that allows adjusting the phase of each output clock in relation to the other output clocks. The phase of each output clock can be adjusted with an accuracy of 20 ps over a range of +/-

45 ns. Setting of the step size and control of the phase

I increment or decrement is accomplished through the

2

C interface. Alternatively, the Si5338 can be ordered with optional phase increment (PINC) and frequency decrement (PDEC) pins for pin controlled applications.

See Table 15 for ordering information of pin controlled

devices.

The phase increment and decrement feature provides a useful method for fine tuning set-up and hold timing margins or adjusting for mismatched PCB trace lengths.

3.8.3. Zero-Delay Buffer/Clock Generator Mode

The Si5338 supports an optional zero delay mode of operation for applications that require minimal input-tooutput delay. In this mode, one of the device output clocks is fed back to the feedback input pin (IN4 or IN5/

IN6) to implement an external feedback path essentially nullifying the delay between the reference input and the

output clocks. Figure 13 shows the Si5338 in a typical

zero delay buffer configuration. The zero-delay mode combined with the phase increment/decrement feature allows unprecedented flexibility in generating clocks with precise edge alignment.

Figure 12. Output Enable Control Registers

20 Rev. 0.5

Si5338

4. Applications of the Si5338

Si5338

XTAL

F in

Osc

P2 ref

PLL

M0

M1

R0

R1

R2

R3

F

0

F

1

F

2

F

3

Figure 13. Si5338 as a Zero-Delay Buffer/Clock

Generator

3.8.4. Spread Spectrum

To help reduce Electro Magnetic Interference (EMI), the

Si5338 supports spread spectrum modulation. The output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system EMI. The Si5338 implements spread spectrum using its patented MultiSynth technology to achieve previously unattainable precision in both modulation

rate and spreading magnitude as shown in Figure 14.

Spread spectrum can be applied to any output clock, any clock frequency, and any spread amount. The device supports center spread (+/- 0.1% to +/- 5%) and down spread (- 0.1% to - 5%). In addition, the device has extensive on-chip voltage regulation such that power supply variations do not influence the device’s spread spectrum clock waveforms.

Because of its flexible architecture, the Si5338 can be configured to serve several functions in the timing path.

The following sections describe some common applications.

4.1. Free-Running Clock Generator

Using the internal oscillator (Osc) and an inexpensive external crystal (XTAL), the Si5338 can be configured as a free-running clock generator for replacing high-end and long lead time crystal oscillators found on many printed circuit boards (PCB). Replacing several crystal oscillators with a single IC solution helps to consolidate the Bill Of Materials (BOM), reduces the number of suppliers, and reduces the number of long lead time components on the PCB. In addition, since crystal oscillators tend to be the least reliable aspect of many systems, the overall FIT rate improves with the elimination of each oscillator.

Up to four independent clock frequencies can be generated at any rate within its supported frequency range and with any of supported output types. Features like frequency increment and decrement, and phase adjustments on a per output basis provides

unprecedented flexibility for PCB designs. Figure 15

shows the Si5338 configured as a free-running clock generator.

XTAL

Osc ref

PLL M0 R0

F

0

M1 R1

F

1

20

M2 R2

F

2

10

+/- 0%

+/- 1%

M3 R3

F

3 0

Si5338

-10

-20

-30

-40

-50

-60

-70

-80

-10% -8% -6% -4% -2% 0% 2%

Relative Frequency

4% 6% 8% 10%

Figure 14. Configurable Spread Spectrum

Figure 15. Si5338 as a Free-Running Clock

Generator

4.2. Synchronous Frequency Translation

In other cases it is useful to generate an output frequency which is synchronous (or phase locked) to another clock frequency. The Si5338 is the ideal choice for generating up to four clocks with different frequencies with a fixed phase relationship to an input reference. Because of its highly precise frequency synthesis, the Si5338 can generate all four output frequencies with 0 ppm error to the input reference. The

Si5338 is an ideal choice for applications that traditionally required multiple stages of frequency

Rev. 0.5

21

S i 5 3 3 8

synthesis to achieve complex frequency translations.

Examples are in broadcast video (e.g. 148.5 MHz to

148.351648351648 MHz), WAN/LAN applications (e.g.

155.52 MHz to 156.25 MHz), and Forward Error

Correction (FEC) applications (e.g. 156.25 MHz to

161.1328125 MHz). Using the input reference selectors, the Si5338 can select from one of four inputs (IN1/IN2,

IN3, IN4, IN5/IN6). Figure 16 shows the Si5338

configured as a synchronous clock generator.

4.3.1. Combination Free-Running and Synchronous

Clock Generator

Another application of the Si5338 is in generating both free-running and synchronous clocks in one device.

This is accomplished by configuring the input and output selectors for the desired split configuration. An

example of such an application is shown in Figure 18.

Si5338

Si5338

XTAL

Osc

R0

F

0

M0 R0

F

0

R1

F

1

P1 M1 R1

F

1

F in ref

PLL

F in

M0 R2 F

2

P2

M2 R2

F

2

P2 ref

PLL

M1 R3

F

3

M3 R3

F

3

Figure 18. Si5338 In a Free-Running and

Synchronous Clock Generator Application

Figure 16. Si5338 as a Synchronous Clock

Generator or Frequency Translator

4.3. Configurable Buffer and Level

Translator

Using the output selectors, the synthesis stage can be entirely bypassed allowing the Si5338 to act as a configurable clock buffer/divider with level translation and selectable inputs. Because of its highly selectable configuration, virtually any combination is possible. The configurable output drivers allow four differential outputs, eight single-ended outputs, or a combination of

both. Figure 17 shows the Si5338 configured as a

flexible clock buffer.

F in

Si5338

R0

R1

R2

R3

1

F in

*

R0

1

F in

*

R1

1

F in

*

R2

1

F in

*

R3

Figure 17. Si5338 as a Configurable Clock

Buffer/Divider with Level Translation

22 Rev. 0.5

Si5338

5. I

2

C Interface

Configuration an operation of the Si5338 is controlled by reading and writing to the RAM space using the I

2

C interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode

(100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.

The I

2

C bus consists of a bidirectional serial data line

(SDA) and a serial clock input (SCL) as shown in

Figure 19. Both the SDA and SCL pins must be

connected to the VDD supply via an external pull-up as recommended by the I

2

C specification.

I

2

C Bus

V

DD

0/1

I2C_LSB

SCL

SDA

OEB/PINC/FINC

I2C_LSB/PDEC/FDEC

Control

Write Operation – Single Byte

S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P

Write Operation - Burst (Auto Address Increment)

S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P

Reg Addr +1

From slave to master

From master to slave

1 – Read

0 – Write

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH)

S – START condition

P – STOP condition

Figure 21. I

2

C Write Operation

A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This

is shown in Figure 22.

Figure 19. I

2

C and Control Signals

The 7-bit device (slave) address of the Si5338 consist of a 6-bit fixed address plus a user selectable LSB bit as

shown in Figure 20. The LSB bit is selectable using the

optional I2C_LSB pin which is available as an ordering option for applications that require more than one

Si5338 on a single I

2

C bus. Devices without the

I2C_LSB pin option have a fixed 7-bit address of 70h as

shown in Figure 20. Other custom I

2

C addresses are

also possible. See Table 15 for details on device

ordering information with the optional I2C_LSB pin.

Read Operation – Single Byte

S Slv Addr [6:0] 0 A Reg Addr [7:0] A P

S Slv Addr [6:0] 1 A Data [7:0] N P

Read Operation - Burst (Auto Address Increment)

S Slv Addr [6:0] 0 A Reg Addr [7:0] A P

S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P

Reg Addr +1

Slave Address

(with I2C_LSB Option)

6 5 4 3 2 1 0

1 1 1 0 0 0 0/1

I2C_LSB pin

From slave to master

From master to slave

1 – Read

0 – Write

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH)

S – START condition

P – STOP condition

Slave Address

(without I2C_LSB Option)

6 5 4 3 2 1 0

1 1 1 0 0 0 0

Figure 20. Si5338 I

2

C Slave Address

Data is transferred MSB first in 8-bit words as specified by the I

2

C specification. A write command consists of a

7-bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in

Figure 21. A write burst operation is also shown where

every additional data word is written using to an autoincremented address.

Figure 22. I

2

C Read Operation

AC and DC electrical specifications for the SCL and

SDA pins are shown in Table 13. The timing

specifications and timing diagram for the I

2

C bus is compatible with the I

2

C-Bus Standard. SDA timeout is supported for compatibility with SMBus interfaces.

The I

2

C bus can be operated at a bus voltage of 1.71 to

3.63 V and is 3.3 V tolerant.

Rev. 0.5

23

S i 5 3 3 8

6. Pin Descriptions

Top View

IN1

IN2

IN3

IN4

IN5

IN6

CLK1A

CLK1B

VDDO1

VDDO2

CLK2A

CLK2B

Note: Center pad must be tied to GND for normal operation.

Pin #

1

Pin Name I/O

Table 14. Si5338 Pin Descriptions

Signal Type Description

CLKIN/CLKINB

2

IN1/IN2 I Multi

These pins are used as the main differential clock input

or as the XTAL input. See section 3.2, Figure 3 and

Figure 4 for connection details.

When not in use, leave IN1 unconnected and IN2 connected to GND.

24 Rev. 0.5

Pin #

3

Pin Name

IN3

Si5338

Table 14. Si5338 Pin Descriptions (Continued)

I/O Signal Type Description

This pin can have one of the following functions depending on the part number.

I Multi

CLKIN (for Si5338A/B/C & Si5338N/P/Q devices only)

Provides a high-impedance clock input for single ended clock signals such as CMOS, SSTL or HSTL. This input

should be dc-coupled as shown in section 3.2 Figure 3.

If this pin is not used, it should be connected to ground.

PINC (for Si5338D/E/F devices only)

Used as the phase increment pin. See section 3.8.2 for

more details. Minimum pulse width of 100 ns is required for proper operation. If this pin is not used, it should be connected to ground.

FINC (for Si5338G/H/J devices only)

Used as the frequency increment pin. See section 3.8.1

for more details. Minimum pulse width of 100 ns is required for proper operation. If this pin is not used, it should be connected to ground.

OEB (for Si5338K/L/M devices only)

Used as an output enable pin. 0= All outputs enabled,

1= All outputs disabled. By default outputs are tri-stated when disabled.

Rev. 0.5

25

S i 5 3 3 8

Pin #

4

5

6

7

8

9

Pin Name

IN4

IN5/IN6

VDD

INTR

CLK3B

Table 14. Si5338 Pin Descriptions (Continued)

I/O Signal Type Description

This pin can have one of the following functions depending on the part number

I

I

VDD

O

O

Multi

I2C_LSB (for Si5338A/B/C & Si5338K/L/M devices only)

This is the LSB of the Si5338 I

2

C address. 0 = I2C address 70h, 1 = I2C address 71h.

FDBK (for Si5338N/P/Q devices only)

Provides a high-impedance feedback input for single ended clock signals such as CMOS, SSTL or HSTL.

This input should be dc-coupled as shown in section 3.2

Figure 3. If this pin is not used, it should be connected to

ground.

PDEC (for Si5338D/E/F) devices only)

Used as the phase decrement pin. See section 3.8.2 for

more details. Minimum pulse width of 100 ns is required for proper operation. If this pin is not used, it should be connected to ground.

Multi

FDEC (for Si5338G/H/J devices only)

Used as the frequency decrement pin. See section 3.8.1

for more details. Minimum pulse width of 100 ns is required for proper operation. If this pin is not used, it should be connected to ground.

FDBK/FDBKB

These pins can be used as a differential feedback input in zero delay buffer mode, or as a secondary clock input.

See section 3.2 Figure 3 for termination details. See

section 3.8.3 for zero delay buffer mode set-up.

Supply

Open Drain

Multi

When not in use, leave IN5 unconnected and IN6 connected to GND.

Core Supply Voltage

This is the core supply voltage which can operate from a

1.8, 2.5, or 3.3 V supply. A 0.1 µF bypass capacitor should be located very close to this pin.

Interrupt

This pin functions as a maskable interrupt output.

0 = No interrupt.

1 = Interrupt present.

This pin requires a pull-up resistor of at least 1 k

.

Output Clock B for Channel 3

May be a single-ended output or half of a differential output with CLK3A being the other differential half.

26 Rev. 0.5

Pin #

10

11

12

13

14

15

16

17

18

19

20

21

Pin Name

CLK3A

VDDO3

SCL

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

SDA

VDDO0

CLK0B

Si5338

Table 14. Si5338 Pin Descriptions (Continued)

I/O

O

VDD

I

O

O

VDD

VDD

O

O

I/O

VDD

O

Signal Type

Multi

Supply

LVCMOS

Multi

Multi

Supply

Supply

Multi

Multi

LVCMOS

Supply

Multi

Description

Output Clock A for Channel 3

May be a single-ended output or half of a differential output with CLK3B being the other differential half.

Output Clock Supply Voltage

Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK3A,B.

A 0.1 µF capacitor must be located very close to this pin.

If CLK3 is not used, this pin must be tied to VDD (pin 7,

24).

I

2

C Serial Clock Input

This is the serial clock input for the I

2

C bus. This pin

must be pulled-up using a pull-up resistor of at least

1 k

.

Output Clock B for Channel 2

May be a single-ended output or half of a differential output with CLK2A being the other differential half.

Output Clock A for Channel 2

May be a single-ended output or half of a differential output with CLK2B being the other differential half.

Output Clock Supply Voltage

Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK2A,B.

A 0.1 µF capacitor must be located very close to this pin.

If CLK2 is not used, this pin must be tied to VDD (pin 7,

24).

Output Clock Supply Voltage

Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK1A,B.

A 0.1 µF capacitor must be located very close to this pin.

If CLK1 is not used, this pin must be tied to VDD (pin 7,

24).

Output Clock B for Channel 1

May be a single-ended output or half of a differential output with CLK1A being the other differential half.

Output Clock A for Channel 1

May be a single-ended output or half of a differential output with CLK1B being the other differential half.

I

2

C Serial Data

This is the serial data for the I

2

C bus. This pin must be

pulled-up using a pull-up resistor of at least 1 k

.

Output Clock Supply Voltage

Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK0A,B.

A 0.1 µF capacitor must be located very close to this pin.

If CLK0 is not used, this pin must be tied to VDD (pin 7,

24).

Output Clock B for Channel 0

May be a single-ended output or half of a differential output with CLK0A being the other differential half.

Rev. 0.5

27

S i 5 3 3 8

Pin #

22

23

24

GND

PAD

Pin Name

CLK0A

GND

VDD

GND

Table 14. Si5338 Pin Descriptions (Continued)

I/O

O

GND

VDD

GND

Signal Type

Multi

GND

Supply

GND

Description

Output Clock A for Channel 0

May be a single-ended output or half of a differential output with CLK0B being the other differential half.

Ground.

Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device.

Core Supply Voltage.

The device operates from a 1.8, 2.5, or 3.3 V supply. A

0.1 µF bypass capacitor should be located very close to this pin.

Ground Pad.

This is the large pad in the center of the package. Use as many vias as possible to connect this pad to a ground plane. Device specifications cannot be guaranteed unless the ground pad is properly connected to a ground plane on the PCB.

28 Rev. 0.5

Si5338

7. Device Pinout by Part Number

The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/

M/Q have a maximum output clock frequency of 200 MHz.

Devices are also orderable according to the pin control functions available on pins 3 and 4. CLKIN - single-ended clock input, I2C_LSB - determines the LSB bit of the 7-bit I

2

C address, FINC - frequency increment pin, FDEC frequency decrement pin, PINC - phase increment pin, PDEC - phase decrement pin, FDBK - single-ended feedback input, OEB - Output Enable.

Table 15. Pin Function by Part Number

Pin # Si5338A - 710 MHz

Si5338B - 350 MHz

Si5338C - 200 MHz

1

2

3

CLKIN

1

CLKINB

1

CLKIN

2

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I2C_LSB

FDBK

4

FDBKB

4

VDD

INTR

CLK3B

CLK3A

VDDO3

SCL

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

SDA

VDDO0

CLK0B

CLK0A

GND

VDD

Si5338D - 710 MHz

Si5338E - 350 MHz

Si5338F - 200 MHz

CLKIN

1

CLKINB

1

PINC

PDEC

FDBK

4

FDBKB

4

VDD

INTR

CLK3B

CLK3A

VDDO3

SCL

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

SDA

VDDO0

CLK0B

CLK0A

GND

VDD

Notes:

1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.

2. CLKIN on pin 3 is a single-ended clock input

3. FDBK on pin 4 is a single-ended feedback input

4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs

Si5338G - 710 MHz

Si5338H - 350 MHz

Si5338J - 200 MHz

CLKIN

1

CLKINB

1

FINC

FDEC

FDBK

4

FDBKB

4

VDD

INTR

CLK3B

CLK3A

VDDO3

SCL

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

SDA

VDDO0

CLK0B

CLK0A

GND

VDD

Si5338K - 710 MHz

Si5338L - 350 MHz

Si5338M - 200 MHz

CLKIN

1

CLKINB

1

OEB

I2C_LSB

FDBK

4

FDBKB

4

VDD

INTR

CLK3B

CLK3A

VDDO3

SCL

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

SDA

VDDO0

CLK0B

CLK0A

GND

VDD

Si5338N - 710 MHz

Si5338P - 350 MHz

Si5338Q - 200 MHz

CLKIN

1

CLKINB

1

CLKIN

2

FDBK

3

FDBK

4

FDBKB

4

VDD

INTR

CLK3B

CLK3A

VDDO3

SCL

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

SDA

VDDO0

CLK0B

CLK0A

GND

VDD

Rev. 0.5

29

S i 5 3 3 8

8. Package Outline: 24-Lead QFN

Figure 23. 24-Lead Quad Flat No-lead (QFN)

Table 16. Package Dimensions

Dimension Min Nom Max

A

A1 b

D

D2 e

E

0.80

0.00

0.18

2.35

0.85

0.02

0.25

4.00 BSC.

2.50

0.50 BSC.

4.00 BSC.

0.90

0.05

0.30

2.65

E2

L aaa bbb

2.35

0.30

2.50

0.40

0.10

0.10

2.65

0.50

ccc ddd

0.08

0.10

eee 0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body

Components.

30 Rev. 0.5

Si5338

9. Recommended PCB Layout

Table 17. PCB Land Pattern

Dimension

P1

P2

X1

Y1

C1

C2

E

Min

2.50

2.50

0.20

0.75

Nom

2.55

2.55

0.25

0.80

3.90

3.90

0.50

Max

2.60

2.60

0.30

0.85

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

8. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.

Rev. 0.5

31

S i 5 3 3 8

10. Ordering Information

Si5338X AXXXXX

GMR

Si5338 µP-Controlled Clock

Generator Product Family

Operating Temp Range: -40 to +85 °C

Package: 4 x 4 mm QFN, ROHS6, Pb-free

R = Tape & Reel

(blank) = Tubes

A = Product Revision A

XXXXX = Leave blank for standard factory default configuration. Custom configurations will be assigned a

5-digit ordering code by the factory .

H

J

K

L

D

E

F

G

M

N

P

Q

1 st

Option Code: Clock Output Frequency Range

A

B

C

0.16 MHz to 700 MHz I2C_LSB

0.16 MHz to 350 MHz I2C_LSB

0.16 MHz to 200 MHz I2C_LSB

0.16 MHz to 700 MHz Phase Inc/Dec Pin Control

0.16 MHz to 350 MHz Phase Inc/Dec Pin Control

0.16 MHz to 200 MHz Phase Inc/Dec Pin Control

0.16 MHz to 700 MHz Freq Inc/Dec Pin Control

0.16 MHz to 350 MHz Freq Inc/Dec Pin Control

0.16 MHz to 200 MHz Freq Inc/Dec Pin Control

0.16 MHz to 700 MHz OEB Pin Control + I2C_LSB

0.16 MHz to 350 MHz OEB Pin Control + I2C_LSB

0.16 MHz to 200 MHz OEB Pin Control + I2C_LSB

0.16 MHz to 700 MHz Four Inputs (2 Differential, 2 Single-ended)

0.16 MHz to 350 MHz Four Inputs (2 Differential, 2 Single-ended)

0.16 MHz to 200 MHz Four Inputs (2 Differential, 2 Single-ended)

32 Rev. 0.5

D

OCUMENT

C

HANGE

L

IST

Revision 0.1 to 0.2

 Updated block diagram to show Rn output divider and APLL bypass mode

Updated pin description to include FDBK±

Updated Table 4. DC Characteristics

Updated Table 12. Jitter Specifications

Added Supply Current vs. Output Frequency

Updated package outline specification

Clarified input clock configuration register settings

Updated DRV_INVERTn[1:0] settings

Added APLL bypass mode

Added LOS_FDBK description

Added additional detail to phase increment/ decrement and frequency increment/decrement descriptions

Clarified output driver powerdown options

Clarified entry to self-calibration mode

Updated ordering guide

Revision 0.2 to 0.3

Changed minimum output clock frequency from

5 MHz to 1 MHz.

Updated slew rates.

Updated " Features" on page 1.

Updated Table 6, “Input and Output Clock

Characteristics,” on page 7.

Deleted Table 12, “Output Driver Slew Rate Control”.

Revision 0.3 to 0.5

Major editorial changes to all sections to improve clarity

Completed electrical specification tables with final characterization results

Revised the maximum input and output frequencies from 700 MHz to 710 MHz

Improved jitter specifications to reflect updated characterization results

Added new Si5338N/P/Q ordering codes

Added typical application diagrams

Added an application section to highlight the flexibility of the Si5338 in various timing functions

Added a configuration section to clarify configuration options

Rev. 0.5

Si5338

33

S i 5 3 3 8

C

ONTACT

I

NFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

34 Rev. 0.5

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