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UM10429
LPC1102 User manual
Rev. 1 — 20 October 2010
Document information
Info
Content
Keywords
ARM Cortex-M0, LPC1102, LPC1102UK
Abstract
LPC1102 User manual
User manual
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LPC1102 UM
Revision history
Rev
Date
Description
1
20101020
LPC1102 User manual
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Chapter 1: LPC1102 Introductory information
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1.1 Introduction
The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit
microcontroller applications, offering performance, low power, simple instruction set and
memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC1102 operates at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data
memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general
purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.
1.2 Features
• System:
– ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
– ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
– Serial Wire Debug.
– System tick timer.
• Memory:
– 32 kB on-chip flash programming memory.
– 8 kB SRAM.
– In-Application Programming (IAP) and In-System Programming (ISP) support via
on-chip bootloader software.
• Digital peripherals:
– 11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
– GPIO pins can be used as edge and level sensitive interrupt sources.
– Four general purpose counter/timers with a total of one capture input and nine
match outputs.
– Programmable WatchDog Timer (WDT).
• Analog peripherals:
– 10-bit ADC with input multiplexing among five pins.
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Chapter 1: LPC1102 Introductory information
• Serial interfaces:
– UART with fractional baud rate generation, internal FIFO, and RS-485 support.
– One SPI controller with SSP features and with FIFO and multi-protocol capabilities.
• Clock generation:
– 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used
as a system clock.
– Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
– PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from an external clock or the internal RC
oscillator.
– Clock output function with divider that can reflect the external clock, IRC clock,
CPU clock, and the Watchdog clock.
• Power control:
– Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep and Deep-sleep modes.
– Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
– Two reduced power modes: Sleep and Deep-sleep modes.
– Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
six of the functional pins.
– Power-On Reset (POR).
– Brownout detect with four separate thresholds for interrupt and forced reset.
• Unique device serial number for identification.
• Single 3.3 V power supply (1.8 V to 3.6 V).
• Available as WLCSP16 package.
1.3 Ordering information
Table 1.
Ordering information
Type number
LPC1102UK
Package
Name
Description
Version
WLCSP16
wafer level chip-size package; 16 bumps; 2.17 × 2.32 × 0.6 mm
-
Table 2.
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Ordering options
Type number
Flash
Total
SRAM
UART
I2C/
Fm+
SPI
ADC
channels
Package
LPC1102UK
32 kB
8 kB
1
-
1
5
WLCSP16
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Chapter 1: LPC1102 Introductory information
1.4 Block diagram
XTALIN
SWD
RESET
LPC1102
IRC
TEST/DEBUG
INTERFACE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
POR
ARM
CORTEX-M0
clocks and
controls
FLASH
32 kB
system bus
slave
GPIO port
PIO0/1
HIGH-SPEED
GPIO
SRAM
8 kB
slave
ROM
slave
slave
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
RXD
TXD
UART
AD[4:0]
10-bit ADC
SCK, MISO,
MOSI
SPI
CT32B0_MAT[3,1,0]
CT32B1_MAT[2:0]
CT32B1_CAP0
CT16B0_MAT[2:0]
32-bit COUNTER/TIMER 0
WDT
32-bit COUNTER/TIMER 1
IOCONFIG
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
SYSTEM CONTROL
PMU
002aaf524
Fig 1.
LPC1102 Block diagram
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Chapter 1: LPC1102 Introductory information
1.5 ARM Cortex-M0 processor
The ARM Cortex-M0 processor is described in detail in Section 19.2 “About the
Cortex-M0 processor and core peripherals”. For the LPC1102, the ARM Cortex-M0
processor core is configured as follows:
• System options:
– The Nested Vectored Interrupt Controller (NVIC) is included and supports up to 32
interrupts.
– The system tick timer is included.
• Debug options: Serial Wire Debug is included with two watchpoints and four
breakpoints.
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Chapter 2: LPC1102 Memory mapping
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2.1 How to read this chapter
Table 3 shows the memory configuration for the LPC1102 part.
Table 3.
Part
LPC1102 memory configuration
Flash
SRAM
32 kB
8 kB
Suffix
LPC1102
2.2 Memory map
Figure 2 shows the memory and peripheral address space of the LPC1102.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC1102, the GPIO ports are the only AHB peripherals. The APB peripheral area
is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This allows simplifying the address decoding for each
peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
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Chapter 2: LPC1102 Memory mapping
4 GB
AHB peripherals
LPC1102
0x5020 0000
0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
127 - 16 reserved
0xE000 0000
0x5004 0000
reserved
AHB peripherals
15-12
reserved
0x5020 0000
11-8
reserved
0x5000 0000
7-4
GPIO PIO1
3-0
GPIO PIO0
reserved
APB peripherals
0x5003 0000
0x5002 0000
0x5001 0000
0x5000 0000
0x4008 0000
31 - 23 reserved
0x4005 C000
0x4008 0000
1 GB
APB peripherals
reserved
22
0x4000 0000
0x4005 8000
21 - 19 reserved
0x4004 C000
reserved
0x2000 0000
0.5 GB
18
system control
17
IOCONFIG
16
15
SPI
flash controller
14
PMU
reserved
0x1000 2000
0x1000 0000
reserved
0x0000 8000
32 kB on-chip flash
0 GB
0x4004 0000
0x4003 C000
0x4003 8000
0x4002 8000
0x1FFF 0000
reserved
8 kB SRAM
0x4004 4000
13 - 10 reserved
0x1FFF 4000
16 kB boot ROM
0x4004 8000
9
reserved
8
reserved
0x4002 0000
7
ADC
0x4001 C000
6
32-bit counter/timer 1
0x4001 8000
5
32-bit counter/timer 0
0x4001 4000
4
16-bit counter/timer 1
0x4001 0000
3
16-bit counter/timer 0
0x4000 C000
2
UART
0x4000 8000
1
0
WDT
0x4000 4000
reserved
0x4000 0000
0x4002 4000
0x0000 00C0
active interrupt vectors
0x0000 0000
0x0000 0000
002aaf526
Fig 2.
LPC1102 memory map
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Chapter 3: LPC1102 System configuration
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3.1 How to read this chapter
This chapter applies to part LPC1102.
3.2 Introduction
The system configuration block controls oscillators, start logic, and clock generation of the
LPC1102. Also included in this block are registers for setting the priority for AHB access
and a register for remapping flash, SRAM, and ROM memory areas.
3.3 Pin description
Table 4 shows pins that are associated with system control block functions.
Table 4.
Pin summary
Pin name
Pin direction
Pin description
PIO0_0; PIO0_8 to PIO0_11
I
Start logic wake-up pins port 0
PIO1_0
I
Start logic wake-up pin port 1
3.4 Clocking and power control
See Figure 3 for an overview of the LPC1102 Clock Generation Unit (CGU).
The LPC1102 include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC1102 will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. UART, the WDT, and SPI0 have individual clock dividers to derive peripheral
clocks from the main clock.
For details on power control see Section 3.8.
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Chapter 3: LPC1102 System configuration
SYSTEM CLOCK
DIVIDER
AHB clock 0
(system)
system clock
AHB clocks
1 to 18
(memories
and peripherals)
18
AHBCLKCTRL[1:18]
IRC oscillator
SPI0 PERIPHERAL
CLOCK DIVIDER
SPI0_PCLK
UART PERIPHERAL
CLOCK DIVIDER
UART_PCLK
WDT CLOCK
DIVIDER
WDT_PCLK
main clock
watchdog oscillator
MAINCLKSEL
(main clock select)
sys_pllclkout
IRC oscillator
IRC oscillator
sys_pllclkin
system oscillator
SYSTEM PLL
watchdog oscillator
SYSPLLCLKSEL
(system PLL clock select)
Fig 3.
WDTUEN
(WDT clock update enable)
LPC1102 CGU block diagram
3.5 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See Section 3.11 for the flash access timing register, which can be re-configured as part
the system setup. This register is not part of the system configuration block.
Table 5.
Register overview: system control block (base address 0x4004 8000)
Name
Access
Address offset Description
Reset
value
Reference
SYSMEMREMAP
R/W
0x000
System memory remap
0x002
Table 6
PRESETCTRL
R/W
0x004
Peripheral reset control
0x000
Table 7
SYSPLLCTRL
R/W
0x008
System PLL control
0x000
Table 8
SYSPLLSTAT
R
0x00C
System PLL status
0x000
Table 9
-
-
0x010 - 0x01C
Reserved
-
-
SYSOSCCTRL
R/W
0x020
System oscillator control
0x000
Table 10
WDTOSCCTRL
R/W
0x024
Watchdog oscillator control
0x000
Table 11
IRCCTRL
R/W
0x028
IRC control
0x080
Table 12
-
-
0x02C
Reserved
-
-
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Chapter 3: LPC1102 System configuration
Table 5.
Register overview: system control block (base address 0x4004 8000) …continued
Name
Access
Address offset Description
Reset
value
Reference
SYSRSTSTAT
R
0x030
System reset status register
0x000
Table 13
-
-
0x034 - 0x03C
Reserved
-
-
SYSPLLCLKSEL
R/W
0x040
System PLL clock source select
0x000
Table 14
SYSPLLCLKUEN
R/W
0x044
System PLL clock source update enable
0x000
Table 15
-
-
0x048 - 0x06C
Reserved
-
-
MAINCLKSEL
R/W
0x070
Main clock source select
0x000
Table 16
MAINCLKUEN
R/W
0x074
Main clock source update enable
0x000
Table 17
SYSAHBCLKDIV
R/W
0x078
System AHB clock divider
0x001
Table 18
-
-
0x07C
Reserved
-
-
SYSAHBCLKCTRL
R/W
0x080
System AHB clock control
0x85F
Table 19
-
-
0x084 - 0x090
Reserved
-
-
SSP0CLKDIV
R/W
0x094
SPI0 clock divder
0x000
Table 20
UARTCLKDIV
R/W
0x098
UART clock divder
0x000
Table 21
-
-
0x09C
Reserved
-
-
-
-
0x0A0-0x0CC
Reserved
-
-
WDTCLKSEL
R/W
0x0D0
WDT clock source select
0x000
Table 22
WDTCLKUEN
R/W
0x0D4
WDT clock source update enable
0x000
Table 23
WDTCLKDIV
R/W
0x0D8
WDT clock divider
0x000
Table 24
-
-
0x0DC
Reserved
-
-
-
-
0x0E0
Reserved
-
-
-
-
0x0E4
Reserved
-
-
-
-
0x0E8
Reserved
-
-
-
-
0x0EC - 0x0FC Reserved
-
-
PIOPORCAP0
R
0x100
POR captured PIO status 0
user
dependent
Table 25
-
-
0x104
Reserved
-
-
-
R
0x108 - 0x14C
Reserved
-
-
BODCTRL
R/W
0x150
BOD control
0x000
Table 26
SYSTCKCAL
R/W
0x154
System tick counter calibration
0x004
Table 27
-
-
0x158 - 0x1FC
Reserved
-
-
STARTAPRP0
R/W
0x200
Start logic edge control register 0
Table 28
STARTERP0
R/W
0x204
Start logic signal enable register 0
Table 29
STARTRSRP0CLR
W
0x208
Start logic reset register 0
STARTSRP0
R
0x20C
Start logic status register 0
n/a
Table 31
-
-
0x210 - 0x22C
Reserved
-
-
PDSLEEPCFG
R/W
0x230
Power-down states in Deep-sleep mode
0x0000
0000
Table 33
PDAWAKECFG
R/W
0x234
Power-down states after wake-up from
Deep-sleep mode
0x0000
EDF0
Table 34
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Table 30
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Chapter 3: LPC1102 System configuration
Table 5.
Register overview: system control block (base address 0x4004 8000) …continued
Name
Access
Address offset Description
Reset
value
Reference
PDRUNCFG
R/W
0x238
Power-down configuration register
0x0000
EDF0
Table 35
-
-
0x23C - 0x3F0
Reserved
-
-
DEVICE_ID
R
0x3F4
Device ID
part
dependent
Table 36
3.5.1 System memory remap register
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM.
Table 6.
System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Bit
Symbol
1:0
MAP
31:2
-
Value
Description
Reset
value
System memory remap
10
0x0
Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
0x1
User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
0x2
User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
0x3
User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
-
Reserved
0x00
3.5.2 Peripheral reset control register
This register allows software to reset the SPI peripheral. Writing a 0 to the SSP0_RST_N
bit resets the SPI0 peripheral. Writing a 1 de-asserts the reset.
Remark: Before accessing the SPI peripheral, write a 1 to this register to ensure that the
reset signal to the SPI is de-asserted.
Table 7.
Bit
Symbol
0
SSP0_RST_N
31:1
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Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
-
Value
Description
Reset
value
SPI0 reset control
0
0
Resets the SPI0 peripheral.
1
SPI0 reset de-asserted.
-
Reserved
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Chapter 3: LPC1102 System configuration
3.5.3 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and memories. The PLL can
produce a clock up to the maximum allowed for the CPU.
Table 8.
System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Bit
Symbol
4:0
6:5
31:7
Value
Description
Reset
value
MSEL
Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ration M = 32
0x000
PSEL
Post divider ratio P. The division ratio is 2 × P.
0x00
-
0x0
P=1
0x1
P=2
0x2
P=4
0x3
P=8
-
Reserved. Do not write ones to reserved bits.
0x0
3.5.4 System PLL status register
This register is a Read-only register and supplies the PLL lock status (see
Section 3.10.1).
Table 9.
System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
Bit
Symbol
0
LOCK
31:1
Value
-
Description
Reset
value
PLL lock status
0x0
0
PLL not locked
1
PLL locked
-
Reserved
0x00
3.5.5 System oscillator control register
This register configures the frequency range for the system oscillator.
Table 10.
UM10429
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System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit
Symbol
Value
0
BYPASS
Description
Reset
value
Bypass system oscillator
0x0
0
Oscillator is not bypassed.
1
Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN pin.
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Chapter 3: LPC1102 System configuration
Table 10.
System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit
Symbol
1
FREQRANGE
31:2
Value
-
Description
Reset
value
Determines frequency range for Low-power
oscillator.
0x0
0
1 - 20 MHz frequency range.
1
15 - 25 MHz frequency range
-
Reserved
0x00
3.5.6 Watchdog oscillator control register
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk = Fclkana⁄(2 × (1 + DIVSEL)) = 7.8 kHz to 1.7 MHz (nominal values).
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ±40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system oscillator.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 11.
UM10429
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Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit
Symbol
4:0
DIVSEL
Value
Description
Reset
value
Select divider for Fclkana.
wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
00000: 2 × (1 + DIVSEL) = 2
00001: 2 × (1 + DIVSEL) = 4
to
11111: 2 × (1 + DIVSEL) = 64
0x00
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Chapter 3: LPC1102 System configuration
Table 11.
Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description …continued
Bit
Symbol
8:5
FREQSEL
31:9
-
Value
Description
Reset
value
Select watchdog oscillator analog output frequency
(Fclkana).
0x00
0x1
0.5 MHz
0x2
0.8 MHz
0x3
1.1 MHz
0x4
1.4 MHz
0x5
1.6 MHz
0x6
1.8 MHz
0x7
2.0 MHz
0x8
2.2 MHz
0x9
2.4 MHz
0xA
2.6 MHz
0xB
2.7 MHz
0xC
2.9 MHz
0xD
3.1 MHz
0xE
3.2 MHz
0xF
3.4 MHz
-
Reserved
0x00
3.5.7 Internal resonant crystal control register
This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
and written by the boot code on start-up.
Table 12.
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Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit
description
Bit
Symbol
7:0
TRIM
31:9
-
Value
-
Description
Reset value
Trim value
0x1000 0000,
then flash will
reprogram
Reserved
0x00
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Chapter 3: LPC1102 System configuration
3.5.8 System reset status register
if another reset signal - for example EXTRST - remains asserted after the POR signal is
negated, then its bit is set to detected.
Table 13.
System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description
Bit
Symbol
0
POR
1
2
3
4
31:5
Value
Description
Reset
value
POR reset status
0x0
0
no POR detected
1
POR detected
EXTRST
0x0
0
no RESET event detected
1
RESET detected
0
no WDT reset detected
1
WDT reset detected
WDT
Status of the Watchdog reset
BOD
Status of the Brown-out detect reset
0
no BOD reset detected
1
BOD reset detected
SYSRST
Status of the software system reset
-
0
no System reset detected
1
System reset detected
-
Reserved
0x0
0x0
0x0
0x00
3.5.9 System PLL clock source select register
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
(see Section 3.5.10) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
Table 14.
Bit
Symbol
1:0
SEL
31:2
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System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)
bit description
-
Value
Description
Reset
value
System PLL clock source
0x00
0x0
IRC oscillator
0x1
System oscillator
0x2
Reserved
0x3
Reserved
-
Reserved
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3.5.10 System PLL clock source update enable register
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 15.
System PLL clock source update enable register (SYSPLLUEN, address 0x4004
8044) bit description
Bit
Symbol
0
ENA
31:1
Value
-
Description
Reset value
Enable system PLL clock source update
0x0
0
No change
1
Update clock source
-
Reserved
0x00
3.5.11 Main clock source select register
This register selects the main system clock which can be either any input to the system
PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators
directly. The main system clock clocks the core, the peripherals, and the memories.
The MAINCLKUEN register (see Section 3.5.12) must be toggled from LOW to HIGH for
the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
Table 16.
Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit
description
Bit
Symbol
1:0
SEL
31:2
-
Value
Description
Reset value
Clock source for main clock
0x00
0x0
IRC oscillator
0x1
Input clock to system PLL
0x2
WDT oscillator
0x3
System PLL clock out
-
Reserved
0x00
3.5.12 Main clock source update enable register
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
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Table 17.
Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
Bit
Symbol
0
ENA
31:1
-
Value
Description
Reset value
Enable main clock source update
0x0
0
No change
1
Update clock source
-
Reserved
0x00
3.5.13 System AHB clock divider register
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
Table 18.
System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
Bit
Symbol
Description
Reset
value
7:0
DIV
System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0x01
31:8
-
Reserved
0x00
3.5.14 System AHB clock control register
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and
the PMU. This clock cannot be disabled.
Table 19.
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
Bit
Symbol
0
SYS
1
Value
User manual
Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
1
Reserved
1
Enable
ROM
Enables clock for ROM.
1
UM10429
Reset
value
0
0
2
Description
RAM
1
Disable
Enable
Enables clock for RAM.
0
Disable
1
Enable
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Table 19.
Bit
Symbol
3
FLASHREG
4
Description
Reset
value
Enables clock for flash register interface.
1
0
Disabled
1
Enabled
FLASHARRAY
Enables clock for flash array access.
0
Disabled
1
Enabled
1
-
Reserved.
0
6
GPIO
Enables clock for GPIO.
1
8
9
10
11
12
13
User manual
Value
5
7
UM10429
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description …continued
0
Disable
1
Enable
CT16B0
Enables clock for 16-bit counter/timer 0.
0
Disable
1
Enable
CT16B1
0
Enables clock for 16-bit counter/timer 1.
0
Disable
1
Enable
0
Disable
1
Enable
CT32B0
0
Enables clock for 32-bit counter/timer 0.
CT32B1
0
Enables clock for 32-bit counter/timer 1.
0
Disable
1
Enable
SSP0
0
Enables clock for SPI0.
0
Disable
1
Enable
UART
1
Enables clock for UART. Note that the UART pins
must be configured in the IOCON block before the
UART clock can be enabled.
0
Disable
1
Enable
ADC
Enables clock for ADC.
0
Disable
1
Enable
0
0
14
-
Reserved
0
15
WDT
Enables clock for WDT.
0
0
Disable
1
Enable
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Table 19.
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description …continued
Bit
Symbol
16
IOCON
31:17
-
Value
Description
Reset
value
Enables clock for I/O configuration block.
0
0
Disable
1
Enable
-
Reserved
0x00
3.5.15 SPI0 clock divider register
This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be
shut down by setting the DIV bits to 0x0.
Table 20.
SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
SPI0_PCLK clock divider values
0: Disable SPI0_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8
-
Reserved
0x00
3.5.16 UART clock divider register
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART pins must be configured in the IOCON block before the
UART clock can be enabled.
Table 21.
UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
UART_PCLK clock divider values
0: Disable UART_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8
-
Reserved
0x00
3.5.17 WDT clock source select register
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
(see Section 3.5.18) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
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Table 22.
WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit
description
Bit
Symbol
1:0
SEL
31:2
-
Value
Description
Reset
value
WDT clock source
0x00
0x0
IRC oscillator
0x1
Main clock
0x2
Watchdog oscillator
0x3
Reserved
-
Reserved
0x00
3.5.18 WDT clock source update enable register
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 23.
WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)
bit description
Bit
Symbol
0
ENA
31:1
-
Value
Description
Reset value
Enable WDT clock source update
0x0
0
No change
1
Update clock source
-
Reserved
0x00
3.5.19 WDT clock divider register
This register determines the divider values for the watchdog clock wdt_clk.
Table 24.
WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
WDT clock divider values
0: Disable WDT_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8
-
Reserved
0x00
3.5.20 POR captured PIO status register 0
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
one GPIO pin. This register is a read-only status register.
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Chapter 3: LPC1102 System configuration
Table 25.
POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit
description
Bit
Symbol
Description
Reset value
0
CAPPIO0_0
Raw reset status input PIO0_0
User implementation dependent
7:1
-
Reserved.
-
8
CAPPIO0_8
Raw reset status input PIO0_8
User implementation dependent
9
CAPPIO0_9
Raw reset status input PIO0_9
User implementation dependent
10
CAPPIO0_10
Raw reset status input PIO0_10
User implementation dependent
11
CAPPIO0_11
Raw reset status input PIO0_11
User implementation dependent
12
CAPPIO1_0
Raw reset status input PIO1_0
User implementation dependent
13
CAPPIO1_1
Raw reset status input PIO1_1
User implementation dependent
14
CAPPIO1_2
Raw reset status input PIO1_2
User implementation dependent
15
CAPPIO1_3
Raw reset status input PIO1_3
User implementation dependent
17:16
-
Reserved.
-
18
CAPPIO1_6
Raw reset status input PIO1_6
User implementation dependent
19
CAPPIO1_7
Raw reset status input PIO1_7
User implementation dependent
31:20
-
Reserved.
-
3.5.21 BOD control register
The BOD control register selects four separate threshold values for sending a BOD
interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in
Table 26 are typical values.
Table 26.
Symbol
1:0
BODRSTLEV
3:2
UM10429
User manual
BOD control register (BODCTRL, address 0x4004 8150) bit description
Bit
Value Description
Reset
value
BOD reset level
00
0x0
Level 0: The reset assertion threshold voltage is 1.46 V; the
reset de-assertion threshold voltage is 1.63 V.
0x1
Level 1: The reset assertion threshold voltage is 2.06 V; the
reset de-assertion threshold voltage is 2.15 V.
0x2
Level 2: The reset assertion threshold voltage is 2.35 V; the
reset de-assertion threshold voltage is 2.43 V.
0x3
Level 3: The reset assertion threshold voltage is 2.63 V; the
reset de-assertion threshold voltage is 2.71 V.
BODINTVAL
BOD interrupt level
00
0x0
Level 0: The interrupt assertion threshold voltage is 1.65 V;
the interrupt de-assertion threshold voltage is 1.80 V.
0x1
Level 1:The interrupt assertion threshold voltage is 2.22 V;
the interrupt de-assertion threshold voltage is 2.35 V.
0x2
Level 2: The interrupt assertion threshold voltage is 2.52 V;
the interrupt de-assertion threshold voltage is 2.66 V.
0x3
Level 3: The interrupt assertion threshold voltage is 2.80 V;
the interrupt de-assertion threshold voltage is 2.90 V.
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Table 26.
BOD control register (BODCTRL, address 0x4004 8150) bit description
Bit
Symbol
Value Description
4
BODRSTENA
31:5 -
Reset
value
BOD reset enable
0
Disable reset function.
1
Enable reset function.
-
Reserved
0
0x00
3.5.22 System tick counter calibration register
This register determines the value of the SYST_CALIB register (see Table 138).
Table 27.
System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit
description
Bit
Symbol
25:0
CAL
31:26
-
Value
-
Description
Reset
value
System tick timer calibration value
0x04
Reserved
0x00
3.5.23 Start logic edge control register 0
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO
input to produce a falling or rising clock edge, respectively, for the start logic (see
Section 3.9.2).
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see Table 44), up to a total of 13 interrupts.
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
Table 28.
Bit
Symbol
0
APRPIO0_0
7:1
-
8
APRPIO0_8
9
UM10429
User manual
Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description
Value
Description
Reset
value
Edge select for start logic input PIO0_0
0x0
0
Falling edge
1
Rising edge
-
Reserved
0x0
Edge select for start logic input PIO0_8
0x0
0
Falling edge
1
Rising edge
APRPIO0_9
Edge select for start logic input PIO0_9
0
Falling edge
1
Rising edge
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Table 28.
Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description …continued
Bit
Symbol
10
APRPIO0_10
11
Value
Edge select for start logic input PIO0_10
0x0
Falling edge
1
Rising edge
Edge select for start logic input PIO0_11
0
Falling edge
1
Rising edge
APRPIO1_0
31:13 -
Reset
value
0
APRPIO0_11
12
Description
0x0
Edge select for start logic input PIO1_0.
0
Falling edge
1
Rising edge
-
Reserved
0x0
0x0
3.5.24 Start logic signal enable register 0
This STARTERP0 register enables or disables the start signal bits in the start logic. The bit
assignment is identical to Table 28.
Table 29.
Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit
description
Bit
Symbol
Value
0
ERPIO0_0
7:1
-
8
ERPIO0_8
9
10
UM10429
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0x0
1
Enabled
Reserved
0x0
Enable start signal for start logic input PIO0_8
0x0
0
Disabled
1
Enabled
ERPIO0_9
Enable start signal for start logic input PIO0_9
0
Disabled
1
Enabled
ERPIO0_10
0x0
Enable start signal for start logic input PIO0_10
ERPIO0_11
0x0
Disabled
Enabled
Enable start signal for start logic input PIO0_11
0
Disabled
1
Enabled
ERPIO1_0
31:13 -
Enable start signal for start logic input PIO0_0
Disabled
1
12
Reset
value
0
0
11
Description
Enable start signal for start logic input PIO1_0
0
Disabled
1
Enabled
Reserved
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0x0
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3.5.25 Start logic reset register 0
Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit
assignment is identical to Table 28. The start-up logic uses the input signals to generate a
clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt
for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared
before being used.
Table 30.
Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit
description
Bit
Symbol
Value
0
RSRPIO0_0
7:1
-
8
RSRPIO0_8
9
10
11
12
31:13
Reset
value
Start signal reset for start logic input PIO0_0
n/a
0
-
1
Write: reset start signal
-
Reserved
n/a
Start signal reset for start logic input PIO0_8
n/a
0
-
1
Write: reset start signal
0
-
1
Write: reset start signal
RSRPIO0_9
Start signal reset for start logic input PIO0_9
RSRPIO0_10
n/a
Start signal reset for start logic input PIO0_10
0
-
1
Write: reset start signal
RSRPIO0_11
Start signal reset for start logic input PIO0_11
0
-
1
Write: reset start signal
RSRPIO1_0
-
Description
Start signal reset for start logic input PIO1_0
0
-
1
Write: reset start signal
-
Reserved
n/a
n/a
n/a
n/a
3.5.26 Start logic status register 0
This register reflects the status of the enabled start signal bits. The bit assignment is
identical to Table 28. Each bit (if enabled) reflects the state of the start logic, i.e. whether
or not a wake-up signal has been received for a given pin.
Table 31.
Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description
Bit
Symbol
Value
0
SRPIO0_0
0
7:1
UM10429
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-
Description
Reset
value
Start signal status for start logic input 0PIO0_0
n/a
No start signal received
1
Start signal pending
-
Reserved
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Table 31.
Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description
Bit
Symbol
8
SRPIO0_8
9
Value
Start signal pending
Start signal status for start logic input PIO0_9
0
No start signal received
1
Start signal pending
-
n/a
Start signal status for start logic input PIO0_10
0
No start signal received
1
Start signal pending
Start signal status for start logic input PIO0_11
0
No start signal received
1
Start signal pending
SRPIO1_0
31:13
n/a
No start signal received
SRPIO0_11
12
Start signal status for start logic input PIO0_8
1
SRPIO0_10
11
Reset
value
0
SRPIO0_9
10
Description
Start signal status for start logic input PIO1_0
0
No start signal received
1
Start signal pending
-
Reserved
n/a
n/a
n/a
n/a
3.5.27 Deep-sleep mode configuration register
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode.
This register must be initialized at least once before entering Deep-sleep mode with
one of the four values shown in Table 32:
Table 32.
Allowed values for PDSLEEPCFG register
Configuration
WD oscillator on
BOD on
PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7
WD oscillator off
BOD off
PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in Table 32 are the only values allowed
for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
• BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
additional current drain in Deep-sleep mode.
• WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer or a general purpose timer if they are needed
for timing a wake-up event (see Section 3.9.3 for details). In this case, the watchdog
oscillator analog output frequency must be set to its lowest value (bits FREQSEL in
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the WDTOSCCTRL = 0001, see Table 11) and all peripheral clocks other than the
timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 19) before
entering Deep-sleep mode.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Table 33.
Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
description
Bit
Symbol
2:0
3
Value
Description
Reset
value
-
Reserved. Always write these bits as 111.
0
BOD_PD
BOD power-down control in Deep-sleep mode, see
Table 32.
0
0
Powered
1
Powered down
5:4
-
Reserved. Always write these bits as 11.
0
6
WDTOSC_PD
Watchdog oscillator power control in Deep-sleep
mode, see Table 32.
0
0
Powered
1
Powered down
7
-
Reserved. Always write this bit as 1.
0
10:8
-
Reserved. Always write these bits as 000.
0
12:11
-
Reserved. Always write these bits as 11.
0
31:13
-
Reserved
0
3.5.28 Wake-up configuration register
The bits in this register determine the state the chip enters when it is waking up from
Deep-sleep mode.
By default, the IRC and flash memory are powered and running and the BOD circuit is
enabled when the chip wakes up from Deep-sleep mode.
Remark: Reserved bits must be always written as indicated.
Table 34.
Bit
Symbol
0
IRCOUT_PD
1
UM10429
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Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
Value
Description
Reset
value
IRC oscillator output wake-up configuration
0
0
Powered
1
Powered down
IRC_PD
IRC oscillator power-down wake-up configuration
0
Powered
1
Powered down
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Chapter 3: LPC1102 System configuration
Table 34.
Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description …continued
Bit
Symbol
2
FLASH_PD
3
4
5
6
7
Value
Description
Reset
value
Flash wake-up configuration
0
0
Powered
1
Powered down
BOD_PD
BOD wake-up configuration
0
Powered
1
Powered down
ADC_PD
0
ADC wake-up configuration
0
Powered
1
Powered down
SYSOSC_PD
1
System oscillator wake-up configuration
0
Powered
1
Powered down
WDTOSC_PD
1
Watchdog oscillator wake-up configuration
0
Powered
1
Powered down
SYSPLL_PD
System PLL wake-up configuration
0
Powered
1
Powered down
1
1
8
-
Reserved. Always write this bit as 1.
1
9
-
Reserved. Always write this bit as 0.
0
10
-
Reserved. Always write this bit as 1.
1
11
-
Reserved. Always write this bit as 1.
1
12
-
Reserved. Always write this bit as 0.
0
15:13
-
Reserved. Always write these bits as 111.
111
31:16
-
Reserved
-
-
3.5.29 Power-down configuration register
The bits in the PDRUNCFG register control the power to the various analog blocks. This
register can be written to at any time while the chip is running, and a write will take effect
immediately with the exception of the power-down signal to the IRC.
To avoid glitches when powering down the IRC, the IRC clock is automatically switched off
at a clean point. Therefore, for the IRC a delay is possible before the power-down state
takes effect.
By default, the IRC and flash memory are powered and running and the BOD circuit is
enabled.
Remark: Reserved bits must be always written as indicated.
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Table 35.
Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit
description
Bit
Symbol
Value
0
IRCOUT_PD
0
1
1
2
3
4
5
6
7
IRC_PD
Description
Reset
value
IRC oscillator output power-down
0
Powered
Powered down
IRC oscillator power-down
0
Powered
1
Powered down
0
Powered
1
Powered down
FLASH_PD
0
Flash power-down
BOD_PD
0
BOD power-down
0
Powered
1
Powered down
ADC_PD
0
ADC power-down
0
Powered
1
Powered down
SYSOSC_PD
1
System oscillator power-down
0
Powered
1
Powered down
WDTOSC_PD
1
Watchdog oscillator power-down
0
Powered
1
Powered down
SYSPLL_PD
1
System PLL power-down
0
Powered
1
Powered down
1
8
-
Reserved. Always write this bit as 1.
1
9
-
Reserved. Always write this bit as 0.
0
10
-
Reserved. Always write this bit as 1.
1
11
-
Reserved. Always write this bit as 1.
1
12
-
Reserved. Always write this bit as 0.
0
15:13
-
Reserved. Always write these bits as 111.
111
31:16
-
Reserved
-
-
3.5.30 Device ID register
This device ID register is a read-only register and contains the part ID for each LPC1102
part. This register is also read by the ISP/IAP commands (Section 19.5.11).
Table 36.
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Device ID register (DEVICE_ID, address 0x4004 83F4) bit description
Bit
Symbol
Description
Reset value
31:0
DEVICEID
Part ID numbers for LPC1102 parts
LPC1102 = 0x2500 102B
part-dependent
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3.6 Reset
Reset has four sources on the LPC1102: the RESET pin, Watchdog Reset, Power-On
Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset.
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the IRC causing reset to remain
asserted until the external Reset is de-asserted, the oscillator is running, and the flash
controller has completed its initialization.
On the assertion of a reset source external to the Cortex-M0 CPU (POR, BOD reset,
External reset, and Watchdog reset), the following processes are initiated:
1. The IRC starts up. After the IRC-start-up time (maximum of 6 μs on power-up), the
IRC provides a stable clock output.
2. The boot code in the ROM starts. The boot code performs the boot tasks and may
jump to the flash.
3. The flash is powered up. This takes approximately 100 μs. Then the flash initialization
sequence is started, which takes about 250 cycles.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
3.7 Brown-out detection
The LPC1102 includes four levels for monitoring the voltage on the VDD pin. If this voltage
falls below one of the four selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
in order to cause a CPU interrupt; if not, software can monitor the signal by reading the
NVIC status register (see Table 44). An additional four threshold levels can be selected to
cause a forced reset of the chip (see Table 26).
3.8 Power management
The LPC1102 support a variety of power control features. In Active mode, when the chip
is running, power and clocks to selected peripherals can be optimized for power
consumption. In addition, there are three special modes of processor power reduction:
Sleep mode and Deep-sleep mode mode.
Remark: The Debug mode is not supported in Sleep or Deep-sleep mode.
3.8.1 Active mode
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
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3.8.1.1 Power configuration in Active mode
Power consumption in Active mode is determined by the following configuration choices:
• The SYSAHBCLKCTRL register controls which memories and peripherals are
running (Table 19).
• The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and
the flash block) can be controlled at any time individually through the PDRUNCFG
register (Table 35).
• The clock source for the system clock can be selected from the IRC (default), the
system oscillator, or the watchdog oscillator (see Figure 3 and related registers).
• The system clock frequency can be selected by the SYSPLLCTRL (Table 8) and the
SYSAHBCLKDIV register (Table 18).
• Selected peripherals (UART, SPI0, WDT) use individual peripheral clocks with their
own clock dividers. The peripheral clocks can be shut down through the
corresponding clock divider registers.
3.8.2 Sleep mode
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of
instructions is suspended until either a reset or an enabled interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue
operation during Sleep mode and may generate interrupts to cause the processor to
resume execution. Sleep mode eliminates dynamic power used by the processor itself,
memory systems and their related controllers, and internal buses. The processor state
and registers, peripheral registers, and internal SRAM values are maintained, and the
logic levels of the pins remain static.
3.8.2.1 Power configuration in Sleep mode
Power consumption in Sleep mode is configured by the same settings as in Active mode:
• The clock remains running.
• The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
• Analog and digital peripherals are selected as in Active mode.
3.8.2.2 Programming Sleep mode
The following steps must be performed to enter Sleep mode:
1. The DPDEN bit in the PCON register must be set to zero (Table 41).
2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see
(Table 225).
3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.
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3.8.2.3 Wake-up from Sleep mode
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
3.8.3 Deep-sleep mode
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register.
Deep-sleep mode eliminates all power used by the flash and analog peripherals and all
dynamic power used by the processor itself, memory systems and their related
controllers, and internal buses. The processor state and registers, peripheral registers,
and internal SRAM values are maintained, and the logic levels of the pins remain static.
3.8.3.1 Power configuration in Deep-sleep mode
Power consumption in Deep-sleep mode is determined by the Deep-sleep power
configuration setting in the PDSLEEPCFG (Table 33) register:
• The only clock source available in Deep-sleep mode is the watchdog oscillator. The
watchdog oscillator can be left running in Deep-sleep mode if required for
timer-controlled wake-up (see Section 3.9.3). All other clock sources (the IRC and
system oscillator) and the system PLL are shut down. The watchdog oscillator analog
output frequency must be set to the lowest value of its analog clock output (bits
FREQSEL in the WDTOSCCTRL = 0001, see Table 11).
• The BOD circuit can be left running in Deep-sleep mode if required by the application.
• If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or
one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register
to minimize power consumption.
3.8.3.2 Programming Deep-sleep mode
The following steps must be performed to enter Deep-sleep mode:
1. The DPDEN bit in the PCON register must be set to zero (Table 41).
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table 33)
register.
a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is
powered in the PDRUNCFG register and switch the clock source to WD oscillator
in the MAINCLKSEL register (Table 16).
b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down,
ensure that the IRC is powered in the PDRUNCFG register and switch the clock
source to IRC in the MAINCLKSEL register (Table 16). This ensures that the
system clock is shut down glitch-free.
3. Select the power configuration after wake-up in the PDAWAKECFG (Table 34)
register.
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4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start
logic registers (Table 28 to Table 31), and enable the start logic interrupt in the NVIC.
5. In the SYSAHBCLKCTRL register (Table 19), disable all peripherals except
counter/timer or WDT if needed.
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 225).
7. Use the ARM WFI instruction.
3.8.3.3 Wake-up from Deep-sleep mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
• Signal on an external pin. For this purpose, pins PIO0_0, PIO0_8 to PIO0_11, and
PIO1_0 can be enabled as inputs to the start logic. The start logic does not require
any clocks and generates the interrupt if enabled in the NVIC to wake up from
Deep-sleep mode.
• Input signal to the start logic created by a match event on one of the general purpose
timer external match outputs. The pin holding the timer match function must be
enabled as start logic input in the NVIC, the corresponding timer must be enabled in
the SYSAHBCLKCTRL register, and the watchdog oscillator must be running in
Deep-sleep mode (for details see Section 3.9.3).
• Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register (Table 26).
• Reset from the watchdog timer. In this case, the watchdog oscillator must be running
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in
the SYSAHBCLKCTRL register.
• A reset signal from the external RESET pin.
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency
determines the wake-up time causing the wake-up time to be longer than waking up with
the IRC.
3.9 Deep-sleep mode details
3.9.1 IRC oscillator
The IRC is the only oscillator on the LPC1102 that can always shut down glitch-free.
Therefore it is recommended that the user switches the clock source to IRC before the
chip enters Deep-sleep mode.
3.9.2 Start logic
The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM
core. The port pins PIO0_0 to PIO0_11 and PIO1_1 are connected to the start logic and
serve as wake-up pins. The user must program the start logic registers for each input to
set the appropriate edge polarity for the corresponding wake-up event. Furthermore, the
interrupts corresponding to each input must be enabled in the NVIC (see Section 3.5.23).
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The start logic does not require a clock to run because it uses the input signals on the
enabled pins to generate a clock edge when enabled. Therefore, the start logic signals
should be cleared (see Table 30) before use.
The start logic can also be used in Active mode to provide a vectored interrupt using the
LPC1102’s input pins.
3.9.3 Using the general purpose counter/timers to create a self-wake-up
event
If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers
can count clock cycles of the watchdog oscillator and create a match event when the
number of cycles equals a preset match value. The match event causes the
corresponding match output pin to go HIGH, LOW, or toggle. The state of the match
output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin
is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic
edge control register (see Table 28).
The following steps must be performed to configure the counter/timer and create a timed
Deep-sleep self-wake-up event:
1. Configure the port pin as match output in the IOCONFIG block. Select from pins
PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a match output
function.
2. In the corresponding counter/timer, set the match value, and configure the match
output for the selected pin.
3. Select the watchdog oscillator to run in Deep-sleep mode in the PDSLEEPCFG
register.
4. Switch the clock source to the watchdog oscillator in the MAINCLKSEL register
(Table 16) and ensure the watchdog oscillator is powered in the PDRUNCFG register.
5. Enable the pin, configure its edge detect function, and reset the start logic in the start
logic registers (Table 28 to Table 31), and enable the interrupt in the NVIC.
6. Disable all other peripherals in the SYSAHBCLKCTRL register.
7. Ensure that the DPDEN bit in the PCON register is set to zero (Table 41).
8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 225).
9. Start the counter/timer.
10. Use the ARM WFI instruction to enter Deep-sleep mode.
3.10 System PLL functional description
The LPC1102 uses the system PLL to create the clocks for the core and peripherals.
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Chapter 3: LPC1102 System configuration
irc_osc_clk
FCLKIN
sys_osc_clk
pd
FCCO
PSEL<1:0>
PFD
2
SYSPLLCLKSEL
pd
LOCK
DETECT
LOCK
cd
/2P
FCLKOUT
analog section
pd
cd
/M
5
MSEL<4:0>
Fig 4.
System PLL block diagram
The block diagram of this PLL is shown in Figure 4. The input frequency range is 10 MHz
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock and
optionally two additional phases. The CCO frequency range is 156 MHz to
320 MHz.These clocks are either divided by 2×P by the programmable post divider to
create the output clock(s), or are sent directly to the output(s). The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the phase-frequency detector is also monitored by the lock detector,
to signal when the PLL has locked on to the input clock.
Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.
3.10.1 Lock detector
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.
3.10.2 Power-down control
To reduce the power consumption when the PLL clock is not needed, a Power-down
mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bits to one
in the Power-down configuration register (Table 35). In this mode, the internal current
reference will be turned off, the oscillator and the phase-frequency detector will be
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stopped and the dividers will enter a reset state. While in Power-down mode, the lock
output will be low to indicate that the PLL is not in lock. When the Power-down mode is
terminated by setting the SYSPLL_PD bits to zero, the PLL will resume its normal
operation and will make the lock signal high once it has regained lock on the input clock.
3.10.3 Divider ratio programming
Post divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits as shown in Table 8. This guarantees an
output clock with a 50% duty cycle.
Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one, as specified in Table 8.
Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the MSEL and PSEL values with the dividers, the risk
exists that the counter will read in an undefined value, which could lead to unwanted
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
3.10.4 Frequency selection
The PLL frequency equations use the following parameters (also see Figure 3):
Table 37.
PLL frequency parameters
Parameter
System PLL
FCLKIN
Frequency of sys_pllclkin (input clock to the system PLL) from the
SYSPLLCLKSEL multiplexer (see Section 3.5.9).
FCCO
Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.
FCLKOUT
Frequency of sys_pllclkout
P
System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see Section 3.5.3).
M
System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see
Section 3.5.3).
3.10.4.1 Normal mode
In normal mode the post divider is enabled, giving a 50% duty cycle clock with the
following frequency relations:
(1)
FCLKOUT = M × FCLKIN = ( FCCO ) ⁄ ( 2 × P )
To select the appropriate values for M and P, it is recommended to follow these steps:
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1. Specify the input clock frequency FCLKIN.
2. Calculate M to obtain the desired output frequency FCLKOUT with
M = FCLKOUT / FCLKIN.
3. Find a value so that FCCO = 2 × P × FCLKOUT.
4. Verify that all frequencies and divider values conform to the limits specified in Table 8.
5. Ensure that FCLKOUT < 100 MHz.
Table 38 shows how to configure the PLL for a 12 MHz crystal oscillator using the
SYSPLLCTRL register (Table 8). The main clock is equivalent to the system clock if the
system clock divider SYSAHBCLKDIV is set to one (see Table 18).
Table 38.
PLL configuration examples
PLL input
clock
sys_pllclkin
(FCLKIN)
Main clock
(FCLKOUT)
MSEL bits M divider PSEL bits
Table 8
value
Table 8
P divider
value
FCCO
frequency
12 MHz
48 MHz
00011
4
01
2
192 MHz
12 MHz
36 MHz
00010
3
10
4
288 MHz
12 MHz
24 MHz
00001
2
10
4
192 MHz
3.10.4.2 Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When
the Power-down mode is terminated by setting the SYSPLL_PD bit to zero in the
Power-down configuration register (Table 35), the PLL will resume its normal operation
and will make the lock signal HIGH once it has regained lock on the input clock.
3.11 Flash memory access
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x4003 C010.
This register is part of the flash configuration block (see Figure 2).
Remark: Improper setting of this register may result in incorrect operation of the LPC1102
flash memory.
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Chapter 3: LPC1102 System configuration
Table 39.
Bit
Symbol
1:0
FLASHTIM
31:2 -
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Flash configuration register (FLASHCFG, address 0x4003 C010) bit description
Value Description
Reset
value
Flash memory access time. FLASHTIM +1 is equal to the
number of system clocks used for flash access.
10
0x0
1 system clock flash access time (for system clock
frequencies of up to 20 MHz).
0x1
2 system clocks flash access time (for system clock
frequencies of up to 40 MHz).
0x2
3 system clocks flash access time (for system clock
frequencies of up to 50 MHz).
0x3
Reserved.
-
Reserved. User software must not change the value of
<tbd>
these bits. Bits 31:2 must be written back exactly as read.
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4.1 Introduction
The PMU allows access to the power mode status.
4.2 Register description
Table 40.
Register overview: PMU (base address 0x4003 8000)
Name
Access
Address
offset
Description
Reset
value
PCON
R/W
0x000
Power control register
0x0
4.2.1 Power control register
The power control register provides the flags for active or Sleep/Deep-sleep modes.
Table 41.
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Power control register (PCON, address 0x4003 8000) bit description
Bit
Symbol
0
1
Value
Description
Reset
value
-
Reserved. This bit must always be written as 0.
0x0
-
Reserved. This bit must always be written as 0.
0
7:2
-
Reserved. These bits must always be written as 0.
0x0
8
SLEEPFLAG
Sleep mode flag
0
0
Read: No power-down mode entered. LPC1102 is in
Active mode.
Write: No effect.
1
Read: Sleep/Deep-sleepmode entered.
Write: Writing a 1 clears the SLEEPFLAG bit to 0.
11:9
-
Reserved. These bits must always be written as 0.
0x0
11
-
Reserved. This bit must always be written as 0.
0x0
31:12
-
Reserved. Do not write ones to this bit.
0x0
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Chapter 5: LPC1102 Power profiles
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5.1 Features
• Includes ROM-based application services
• Power Management services
• Clocking services
5.2 Description
This chapter describes calls that applications can make to code that is included in on-chip
ROM to facilitate power management and clocking setup.
5.3 Definitions
The following elements have to be defined in an application that uses the power profiles:
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
const PWRD * pWRD;
} ROM;
ROM ** rom = (ROM **) 0x1FFF1FF8;
unsigned int command[4], result[2];
5.4 Clocking routine
5.4.1 set_pll
This routine sets up the system PLL according to the calling arguments. If the expected
clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL
to lower system power consumption.
IMPORTANT: Before this routine is invoked, the PLL clock source (IRC/system oscillator)
must be selected (Table 15), the main clock source must be set to the input clock to the
system PLL (Table 17) and the system/AHB clock divider must be set to 1 (Table 19).
set_pll attempts to find a PLL setup that matches the calling parameters. Once a
combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio
(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll
applies the selected values and switches the main clock source selection to the system
PLL clock out (if necessary).
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The routine returns a result code that indicates if the system PLL was successfully set
(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).
The current system frequency value is also returned. The application should use this
information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or
clockout).
Table 42.
set_pll routine
Routine
set_pll
Input
Param0: system PLL input frequency (in kHz)
Param1: expected system clock (in kHz)
Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,
CPU_FREQ_APPROX)
Param3: system PLL lock timeout
Result
Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |
PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED
Result1: system clock (in kHz)
The following definitions are needed when making set_pll power routine calls:
/* set_pll
#define
#define
#define
#define
/* set_pll
#define
#define
#define
#define
#define
mode options */
CPU_FREQ_EQU
CPU_FREQ_LTE
CPU_FREQ_GTE
CPU_FREQ_APPROX
result0 options */
PLL_CMD_SUCCESS
PLL_INVALID_FREQ
PLL_INVALID_MODE
PLL_FREQ_NOT_FOUND
PLL_NOT_LOCKED
0
1
2
3
0
1
2
3
4
5.4.1.1 System PLL input frequency and expected system clock
set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily
finds a solution when the ratio between the expected system clock and the system PLL
input frequency is an integer value, but it can also find solutions in other cases.
The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10
MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and
50000 kHz inclusive. If either of these requirements is not met, set_pll returns
PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.
5.4.1.2 Mode
The first priority of set_pll is to find a setup that generates the system clock at exactly the
rate specified in Param1. If it is unlikely that an exact match can be found, input parameter
mode (Param2) should be used to specify if the actual system clock can be less than or
equal, greater than or equal or approximately the value specified as the expected system
clock (Param1).
A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the
frequency requested in Param1.
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Chapter 5: LPC1102 Power profiles
CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such
as overall current consumption and/or power budget reasons).
CPU_FREQ_GTE helps applications that need a minimum level of CPU processing
capabilities.
CPU_FREQ_APPROX results in a system clock that is as close as possible to the
requested value (it may be greater than or less than the requested value).
If an illegal mode is specified, set_pll returns PLL_INVALID_MODE. If the expected
system clock is out of the range supported by this routine, set_pll returns
PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and
Param0 is returned as Result1.
5.4.1.3 System PLL lock timeout
It should take no more than 100 μs for the system PLL to lock if a valid configuration is
selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. If a non-zero
value is provided, that is how many times the code will check for a successful PLL lock
event before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged
and Param0 is returned as Result1.
Hint: setting Param3 equal to the system PLL frequency [Hz] divided by 10000 will
provide more than enough PLL lock-polling cycles.
5.4.1.4 Code examples
The following examples illustrate some of the features of set_pll discussed above.
5.4.1.4.1
Invalid frequency (device maximum clock rate exceeded)
command[0] = 12000;
command[1] = 60000;
command[2] = CPU_FREQ_EQU;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock and a system clock of exactly
60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected
system clock of 60 MHz exceeds the maximum of 50 MHz. Therefore set_pll returns
PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings.
5.4.1.4.2
Invalid frequency selection (system clock divider restrictions)
command[0] = 12000;
command[1] = 40;
command[2] = CPU_FREQ_LTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40
kHz and no timeout while waiting for the PLL to lock. Since the maximum divider value for
the system clock is 255 and running at 40 kHz would need a divide by value of 300, set_pll
returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL
settings.
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Chapter 5: LPC1102 Power profiles
5.4.1.4.3
Exact solution cannot be found (PLL)
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_EQU;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock and a system clock of exactly
25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no
valid PLL setup within earlier mentioned restrictions, set_pll returns
PLL_FREQ_NOT_FOUND in result[0] and 12000 in result[1] without changing the PLL
settings.
5.4.1.4.4
System clock less than or equal to the expected value
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_LTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of no more than
25 MHz and no locking timeout. set_pll returns PLL_CMD_SUCCESS in result[0] and
24000 in result[1]. The new system clock is 24 MHz.
5.4.1.4.5
System clock greater than or equal to the expected value
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_GTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz
and no locking timeout. set_pll returns PLL_CMD_SUCCESS in result[0] and 36000 in
result[1]. The new system clock is 36 MHz.
5.4.1.4.6
System clock approximately equal to the expected value
command[0] = 12000;
command[1] = 16500;
command[2] = CPU_FREQ_APPROX;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of approximately
16.5 MHz and no locking timeout. set_pll returns PLL_CMD_SUCCESS in result[0] and
16000 in result[1]. The new system clock is 16 MHz.
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Chapter 5: LPC1102 Power profiles
5.5 Power routine
5.5.1 set_power
This routine configures the device’s internal power control settings according to the calling
arguments. The goal is to reduce active power consumption while maintaining the feature
of interest to the application close to its optimum.
set_power returns a result code that reports if the power setting was successfully changed
or not.
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Chapter 5: LPC1102 Power profiles
using power profiles
and changing
system clock
current_clock, current_mode
new_clock, new_mode
True
current_clock = new_clock?
use power routine call
to change mode from
current_mode to new_mode
False
current_mode = DEFAULT?
and
current_mode = new_mode?
False
True
use either clocking routine
call or custom code to change
system clock from
current_clock to new_clock
True
current_clock < new_clock?
False
use power routine call
to change mode from
current_mode to new_mode
wait 50 μs
use either clocking routine
call or custom code to change
system clock from
current_clock to new_clock
use power routine call
to change mode from
current_mode to new_mode
use either clocking routine
call or custom code to change
system clock from
current_clock to new_clock
End
Fig 5.
Power profiles usage
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Chapter 5: LPC1102 Power profiles
Table 43.
set_power routine
Routine
set_power
Input
Param0: new system clock (in MHz)
Param1: mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_
EFFICIENCY, PWR_LOW_CURRENT)
Param2: current system clock (in MHz)
Result
Result0: PWR_CMD_SUCCESS | PWR_INVALID_FREQ |
PWR_INVALID_MODE
The following definitions are needed for set_power routine calls:
/* set_power mode options */
#define
PWR_DEFAULT
#define
PWR_CPU_PERFORMANCE
#define
PWR_EFFICIENCY
#define
PWR_LOW_CURRENT
/* set_power result0 options */
#define
PWR_CMD_SUCCESS
#define
PWR_INVALID_FREQ
#define
PWR_INVALID_MODE
0
1
2
3
0
1
2
5.5.1.1 New system clock
The new system clock is the clock rate at which the microcontroller will be running after
either a successful execution of a clocking routine call or a similar code provided by the
user. This operand must be an integer between 1 to 50 MHz inclusive. If a value out of this
range is supplied, set_power returns PWR_INVALID_FREQ and does not change the
power control system.
5.5.1.2 Mode
The input parameter mode (Param1) specifies one of four available power settings. If an
illegal selection is provided, set_power returns PWR_INVALID_MODE and does not
change the power control system.
PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state.
PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more
processing capability to the application. CPU performance is 30% better than the default
option.
PWR_EFFICIENCY setting was designed to find a balance between active current and
the CPU’s ability to execute code and process data. In this mode the device outperforms
the default mode both in terms of providing higher CPU performance and lowering active
current.
PWR_LOW_CURRENT is intended for those solutions that focus on lowering power
consumption rather than CPU performance.
5.5.1.3 Current system clock
The current system clock is the clock rate at which the microcontroller is running when
set_power is called. This parameter is an integer between from 1 and 50 MHz inclusive.
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Chapter 5: LPC1102 Power profiles
5.5.1.4 Code examples
The following examples illustrate some of the set_power features discussed above.
5.5.1.4.1
Invalid frequency (device maximum clock rate exceeded)
command[0] = 55;
command[1] = PWR_CPU_PERFORMANCE;
command[2] = 12;
(*rom)->pWRD->set_power(command, result);
The above setup would be used in a system running at 12 MHz attempting to switch to
55 MHz system clock, with a need for maximum CPU processing power. Since the
specified 55 MHz clock is above the 50 MHz maximum, set_power returns
PWR_INVALID_FREQ in result[0] without changing anything in the existing power setup.
5.5.1.4.2
An applicable power setup
command[0] = 24;
command[1] = PWR_CPU_EFFICIENCY;
command[2] = 12;
(*rom)->pWRD->set_power(command, result);
The above code specifies that an application running at a system clock of 12 MHz will
switch to 24 MHz with emphasis on efficiency. set_power returns PWR_CMD_SUCCESS
in result[0] after configuring the microcontroller’s internal power control features.
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Chapter 6: LPC1102 Interrupt controller
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6.1 How to read this chapter
This chapter applies to the LPC1102 part.
6.2 Introduction
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
6.3 Features
•
•
•
•
•
•
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
The NVIC supports 32 vectored interrupts
4 programmable interrupt priority levels with hardware priority level masking
Software interrupt generation
6.4 Interrupt sources
Table 44 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
See Section 19.5.2 for the NVIC register bit descriptions.
Interrupts 0 to 12 are connected to a PIO input pin serving as wake-up pin from
Deep-sleep mode; Interrupt 0 to 11 correspond to PIO0_0 to PIO0_11 and interrupt 12
corresponds to PIO1_0; see Section 3.5.28.
Table 44.
Exception
Number
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Connection of interrupt sources to the Vectored Interrupt Controller
Vector
Offset
Function
Flag(s)
0
start logic wake-up
interrupt
start logic input PIO0_0.
7:1
-
Reserved
11:8
start logic wake-up
interrupt
start logic input PIO0_11 to PIO0_8
12
start logic wake-up
interrupt
start logic input PIO1_0
13
-
Reserved
14
-
Reserved
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Chapter 6: LPC1102 Interrupt controller
Table 44.
Exception
Number
Connection of interrupt sources to the Vectored Interrupt Controller
Vector
Offset
Function
Flag(s)
15
-
Reserved
16
CT16B0
Match 0 - 2
17
CT16B1
Match 0 - 1
18
CT32B0
Match 0 - 3
19
CT32B1
Match 0 - 3
Capture 0
20
SPI/SSP0
Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
21
UART
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
UM10429
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22
-
Reserved
23
-
Reserved
24
ADC
A/D Converter end of conversion
25
WDT
Watchdog interrupt (WDINT)
26
BOD
Brown-out detect
27
-
Reserved
28
-
Reserved
29
-
Reserved
30
PIO_1
GPIO interrupt status of port 1
31
PIO_0
GPIO interrupt status of port 0
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Chapter 7: LPC1102 I/O Configuration
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7.1 How to read this chapter
This chapter applies to part LPC1102.
7.2 Introduction
The I/O configuration registers control the electrical characteristics of the pads. The
following features are programmable:
•
•
•
•
pin function
internal pull-up/pull-down resistor or bus keeper function
hysteresis
analog input or digital mode for pads hosting the ADC inputs
7.3 General description
The IOCON registers control the function (GPIO or peripheral function), the input mode,
and the hysteresis of all PIOn_m pins. If a pin is used as input pin for the ADC, an analog
input mode can be selected.
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Chapter 7: LPC1102 I/O Configuration
VDD
ESD
output enable
pin configured
as digital output
driver
output
PIN
ESD
VDD
VSS
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pin configured
as digital input
pull-down enable
data input
select analog input
pin configured
as analog input
Fig 6.
analog input
002aaf304
Standard I/O pin configuration
7.3.1 Pin function
The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a
peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether
the pin is configured as an input or output (see Section 9.3.2). For any peripheral function,
the pin direction is controlled automatically depending on the pin’s functionality. The
GPIOnDIR registers have no effect for peripheral functions.
7.3.2 Pin mode
The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down
resistors for each pin or select the repeater mode.
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
pull-up/pull-down. The default value is pull-up enabled.
The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
known state if it is configured as an input and is not driven externally. Repeater mode may
typically be used to prevent a pin from floating (and potentially using significant power if it
floats to an indeterminate state) if it is temporarily not driven.
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Chapter 7: LPC1102 I/O Configuration
7.3.3 Hysteresis
The input buffer for digital functions can be configured with hysteresis or as plain buffer
through the IOCON registers (see the LPC1102 data sheet for details).
If the external pad supply voltage VDD is between 2.5 V and 3.6 V, the hysteresis buffer
can be enabled or disabled. If VDD is below 2.5 V, the hysteresis buffer must be disabled
to use the pin in input mode.
7.3.4 A/D-mode
In A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for
analog-to-digital conversions. This mode can be selected in those IOCON registers that
control pins with an analog function. If A/D mode is selected, Hysteresis and Pin mode
settings have no effect.
For pins without analog functions, the A/D-mode setting has no effect.
7.4 Register description
The I/O configuration registers control the PIO port pins, the inputs and outputs of all
peripherals and functional blocks and the ADC input pins.
Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and
electrical characteristics.
Table 45.
Register overview: I/O configuration (base address 0x4004 4000)
Name
Access
Address
offset
Description
Reset
value
Reference
-
-
0x000 0x008
Reserved
-
-
IOCON_RESET_PIO0_0
R/W
0x00C
I/O configuration for pin RESET/PIO0_0 0xD0
Table 47
-
-
0x010 0x05C
Reserved
-
-
IOCON_PIO0_8
R/W
0x060
I/O configuration for pin
PIO0_8/MISO0/CT16B0_MAT0
0xD0
Table 48
IOCON_PIO0_9
R/W
0x064
I/O configuration for pin
PIO0_9/MOSI0/CT16B0_MAT1
0xD0
Table 49
IOCON_SWCLK_PIO0_10
R/W
0x068
Reserved
-
-
-
-
0x06C 0x070
Reserved
-
-
IOCON_R_PIO0_11
R/W
0x074
I/O configuration for pin
R/PIO0_11/AD0/CT32B0_MAT3
0xD0
Table 51
IOCON_R_PIO1_0
R/W
0x078
I/O configuration for pin
R/PIO1_0/AD1/CT32B1_CAP0
0xD0
Table 52
IOCON_R_PIO1_1
R/W
0x07C
I/O configuration for pin
R/PIO1_1/AD2/CT32B1_MAT0
0xD0
Table 53
IOCON_R_PIO1_2
R/W
0x080
I/O configuration for pin
R/PIO1_2/AD3/CT32B1_MAT1
0xD0
Table 54
-
-
0x084 0x08C
Reserved
-
-
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Chapter 7: LPC1102 I/O Configuration
Table 45.
Register overview: I/O configuration (base address 0x4004 4000)
Name
Access
Address
offset
Description
Reset
value
Reference
IOCON_SWDIO_PIO1_3
R/W
0x090
I/O configuration for pin
SWDIO/PIO1_3/AD4/CT32B1_MAT2
0xD0
Table 55
-
-
0x094 0x0A0
Reserved
-
-
IOCON_PIO1_6
R/W
0x0A4
I/O configuration for pin
PIO1_6/RXD/CT32B0_MAT0
0xD0
Table 56
IOCON_PIO1_7
R/W
0x0A8
I/O configuration for pin
PIO1_7/TXD/CT32B0_MAT1
0xD0
Table 57
Table 46.
I/O configuration registers ordered by port number
Port pin
Register name
Reference
PIO0_0
IOCON_RESET_PIO0_0
Table 47
PIO0_8
IOCON_PIO0_8
Table 48
PIO0_9
IOCON_PIO0_9
Table 49
PIO0_10
IOCON_SWCLK_PIO0_10
Table 50
PIO0_11
IOCON_R_PIO0_11
Table 51
PIO1_0
IOCON_R_PIO1_0
Table 52
PIO1_1
IOCON_R_PIO1_1
Table 53
PIO1_2
IOCON_R_PIO1_2
Table 54
PIO1_3
IOCON_SWDIO_PIO1_3
Table 55
PIO1_6
IOCON_PIO1_6
Table 56
PIO1_7
IOCON_PIO1_7
Table 57
7.4.1 I/O configuration registers IOCON_PIOn
For details on the I/O configuration settings, see Section 7.3.
Table 47.
Bit
Symbol
2:0
FUNC
4:3
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IOCON_nRESET_PIO0_0 register (IOCON_nRESET_PIO0_0, address 0x4004
400C) bit description
Value
Description
Reset
value
Selects pin function.
Values 0x2 to 0x7 are reserved.
000
000
Selects function RESET.
001
Selects function PIO0_0.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
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Chapter 7: LPC1102 I/O Configuration
Table 47.
Bit
Symbol
5
HYS
Description
Reset
value
Hysteresis.
0
0
Disable.
1
Enable.
-
-
Reserved.
11
31:8
-
-
Reserved.
0
IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description
Bit
Symbol
2:0
FUNC
4:3
5
Value
Description
Reset
value
Selects pin function.
Values 0x3 to 0x7 are reserved.
000
0x0
Selects function PIO0_8.
0x1
Selects function MISO0.
0x2
Selects function CT16B0_MAT0.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
Hysteresis.
0
Disable.
1
Enable.
10
0
7:6
-
-
Reserved.
11
31:8
-
-
Reserved.
0
Table 49.
IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description
Bit
Symbol
2:0
FUNC
4:3
User manual
Value
7:6
Table 48.
UM10429
IOCON_nRESET_PIO0_0 register (IOCON_nRESET_PIO0_0, address 0x4004
400C) bit description
Value
Description
Reset
value
Selects pin function.
Values 0x3 to 0x7 are reserved.
000
0x0
Selects function PIO0_9.
0x1
Selects function MOSI0.
0x2
Selects function CT16B0_MAT1.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
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Chapter 7: LPC1102 I/O Configuration
Table 49.
Symbol
5
HYS
Description
Reset
value
Hysteresis.
0
0
Disable.
1
Enable.
-
-
Reserved.
11
31:8
-
-
Reserved.
0
IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004
4068) bit description
Bit
Symbol Value
Description
Reset
value
2:0
FUNC
Selects pin function.
Values 0x4 to 0x7 are reserved.
000
4:3
5
0x0
Selects function SWCLK.
0x1
Selects function PIO0_10.
0x2
Selects function SCK0
0x3
Selects function CT16B0_MAT2.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
10
Hysteresis.
0
0
Disable.
1
Enable.
-
-
Reserved.
11
31:8 -
-
Reserved.
0
7:6
Table 51.
User manual
Value
7:6
Table 50.
UM10429
IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description
Bit
IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit
description
Bit
Symbol
2:0
FUNC
Value
Description
Reset
value
Selects pin function.
Values 0x4 to 0x7 are reserved.
000
0x0
Selects function R. This function is reserved. Select one of
the alternate functions below.
0x1
Selects function PIO0_11.
0x2
Selects function AD0.
0x3
Selects function CT32B0_MAT3.
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Chapter 7: LPC1102 I/O Configuration
Table 51.
IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit
description …continued
Bit
Symbol
4:3
MODE
5
Value
-
7
ADMODE
-
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
Symbol
2:0
FUNC
UM10429
User manual
1
Enable.
-
Reserved.
1
Selects Analog/Digital mode.
1
0
Analog input mode.
1
Digital functional mode.
-
Reserved.
-
Description
Reset
value
Selects pin function.
Values 0x4 to 0x7 are reserved.
000
0x0
Selects function R. This function is reserved. Select one of
the alternate functions below.
0x1
Selects function PIO1_0.
0x2
Selects function AD1.
0x3
Selects function CT32B1_CAP0.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
Hysteresis.
-
7
ADMODE
-
Disable.
Value
6
31:8
0
IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit
description
Bit
5
10
Hysteresis.
6
4:3
Selects function mode (on-chip pull-up/pull-down resistor
control).
Inactive (no pull-down/pull-up resistor enabled).
HYS
Table 52.
Reset
value
0x0
0
31:8
Description
10
0
0
Disable.
1
Enable.
-
Reserved.
1
Selects Analog/Digital mode.
1
0
Analog input mode.
1
Digital functional mode.
-
Reserved.
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Chapter 7: LPC1102 I/O Configuration
Table 53.
IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit
description
Bit
Symbol
2:0
FUNC
4:3
Value
UM10429
User manual
000
0x1
Selects function PIO1_1.
0x2
Selects function AD2.
0x3
Selects function CT32B1_MAT0.
Selects function mode (on-chip pull-up/pull-down resistor
control).
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
Hysteresis.
-
7
ADMODE
10
Inactive (no pull-down/pull-up resistor enabled).
0x1
HYS
-
Selects pin function.
Values 0x4 to 0x7 are reserved.
Selects function R. This function is reserved. Select one of
the alternate functions below.
MODE
6
31:8
Reset
value
0x0
0x0
5
Description
0
0
Disable.
1
Enable.
-
Reserved.
1
Selects Analog/Digital mode.
1
0
Analog input mode.
1
Digital functional mode.
-
Reserved.
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Chapter 7: LPC1102 I/O Configuration
Table 54.
IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit
description
Bit
Symbol
2:0
FUNC
4:3
Value
Selects function PIO1_2.
0x2
Selects function AD3.
0x3
Selects function CT32B1_MAT1.
Selects function mode (on-chip pull-up/pull-down resistor
control).
7
ADMODE
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
Symbol
2:0
FUNC
0
Disable.
1
Enable.
-
Reserved.
1
Selects Analog/Digital mode.
1
0
Analog input mode.
1
Digital functional mode.
-
Reserved.
Value
UM10429
User manual
-
Description
Reset
value
Selects pin function.
Values 0x4 to 0x7 are reserved.
000
0x0
Selects function SWDIO.
0x1
Selects function PIO1_3.
0x2
Selects function AD4.
0x3
Selects function CT32B1_MAT2.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
5
0
IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description
Bit
4:3
10
Inactive (no pull-down/pull-up resistor enabled).
Hysteresis.
-
Table 55.
000
0x1
HYS
-
Selects pin function.
Values 0x4 to 0x7 are reserved.
Selects function R. This function is reserved. Select one of
the alternate functions below.
MODE
6
31:8
Reset
value
0x0
0x0
5
Description
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
10
Hysteresis.
0
Disable.
1
Enable.
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Chapter 7: LPC1102 I/O Configuration
Table 55.
Bit
Symbol
Value
Description
Reset
value
6
-
-
Reserved.
1
7
ADMODE
Select Analog/Digital mode.
1
31:8
-
Table 56.
Symbol
2:0
FUNC
5
Analog input mode.
1
Digital functional mode.
-
Reserved.
Value
-
Description
Reset
value
Selects pin function.
Values 0x3 to 0x7 are reserved.
000
0x0
Selects function PIO1_6.
0x1
Selects function RXD.
0x2
Selects function CT32B0_MAT0.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
HYS
Hysteresis.
0
Disable.
1
Enable.
10
0
7:6
-
-
Reserved.
11
31:8
-
-
Reserved.
0
Table 57.
IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description
Bit
Symbol
2:0
FUNC
4:3
User manual
0
IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description
Bit
4:3
UM10429
IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description …continued
Value
Description
Reset
value
Selects pin function.
Values 0x3 to 0x7 are reserved.
000
0x0
Selects function PIO1_7.
0x1
Selects function TXD.
0x2
Selects function CT32B0_MAT1.
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
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Chapter 7: LPC1102 I/O Configuration
Table 57.
UM10429
User manual
IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description
Bit
Symbol
5
HYS
Value
Description
Reset
value
Hysteresis.
0
0
Disable.
1
Enable.
7:6
-
-
Reserved.
11
31:8
-
-
Reserved.
0
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Chapter 8: LPC1102 Pin configuration
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User manual
8.1 How to read this chapter
The LPC1102 is available in a WLCSP16 package.
8.2 Pin configuration
D
C
B
A
1
2
3
4
ball A1
index area
Fig 7.
Table 58.
Pin configuration WLCSP16 package
Pin description table
Symbol
Pin
Start
logic
input
Type
Reset Description
state[1]
RESET/PIO0_0
C1[2]
yes
I
I; PU
RESET — External reset input: A LOW on this pin resets the
device, causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
I/O
-
PIO0_0 — General purpose digital input/output pin.
I/O
I; PU
PIO0_8 — General purpose digital input/output pin.
I/O
-
MISO0 — Master In Slave Out for SPI.
PIO0_8/MISO/
CT16B0_MAT0
A2[3]
PIO0_9/MOSI/
CT16B0_MAT1
A3[3]
SWCLK/
PIO0_10/
SCK/CT16B0_MAT2
A4[3]
UM10429
User manual
yes
yes
yes
O
-
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
I/O
I; PU
PIO0_9 — General purpose digital input/output pin.
I/O
-
MOSI0 — Master Out Slave In for SPI.
O
-
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
I
I; PU
SWCLK — Serial wire clock.
I/O
-
PIO0_10 — General purpose digital input/output pin.
I/O
-
SCK — Serial clock for SPI.
O
-
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
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Chapter 8: LPC1102 Pin configuration
Table 58.
Pin description table …continued
Symbol
Pin
Start
logic
input
Type
Reset Description
state[1]
R/PIO0_11/
AD0/CT32B0_MAT3
B4[4]
yes
-
I; PU
R — Reserved.
I/O
-
PIO0_11 — General purpose digital input/output pin.
I
-
AD0 — A/D converter, input 0.
I
-
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
-
I; PU
R — Reserved.
I/O
-
PIO1_0 — General purpose digital input/output pin.
I
-
AD1 — A/D converter, input 1.
I
-
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
-
I; PU
R — Reserved.
I/O
-
PIO1_1 — General purpose digital input/output pin.
I
-
AD2 — A/D converter, input 2.
O
-
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
-
I; PU
R — Reserved.
I/O
-
PIO1_2 — General purpose digital input/output pin.
I
-
AD3 — A/D converter, input 3.
O
-
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
I/O
I; PU
SWDIO — Serial wire debug input/output.
I/O
-
PIO1_3 — General purpose digital input/output pin.
I
-
AD4 — A/D converter, input 4.
O
-
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
I/O
I; PU
PIO1_6 — General purpose digital input/output pin.
I
-
RXD — Receiver input for UART.
O
-
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I/O
I; PU
PIO1_7 — General purpose digital input/output pin.
O
-
TXD — Transmitter output for UART.
O
-
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
R/PIO1_0/
AD1/CT32B1_CAP0
R/PIO1_1/
AD2/CT32B1_MAT0
R/PIO1_2/
AD3/CT32B1_MAT1
SWDIO/PIO1_3/AD4/
CT32B1_MAT2
B3[4]
C4[4]
C3[4]
D4[4]
PIO1_6/RXD/
CT32B0_MAT0
C2[3]
PIO1_7/TXD/
CT32B0_MAT1
D1[3]
yes
no
no
no
no
no
VDD
D2; A1 -
I
-
3.3 V supply voltage to the internal regulator, the external rail,
and the ADC. Also used as the ADC reference voltage.
XTALIN
B2[5]
-
I
-
External clock input and input to internal clock generator circuits.
Input voltage must not exceed 1.8 V.
VSS
D3; B1 -
I
-
Ground.
[1]
Pin state at reset for default function: I = Input; PU = internal pull-up enabled.
[2]
This pin includes a 20 ns glitch filter. The pulse-width must be at least 50 ns to reset or wake up the chip.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 6).
[4]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 6).
[5]
When the external clock is not used, connect XTALIN as follows: XTALIN can be left floating or can be grounded (grounding is preferred
to reduce susceptibility to noise).
UM10429
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Chapter 9: LPC1102 General Purpose I/O (GPIO)
Rev. 1 — 20 October 2010
User manual
9.1 How to read this chapter
See Table 59 for available GPIO pins:
Table 59.
GPIO configuration
Part
Package
GPIO port 0
GPIO port 1
LPC1102
WLCSP16 PIO0_0; PIO0_8 to PIO0_11
GPIO
port 2
PIO1_0 to PIO1_3; PIO1_6 to PIO1_7
GPIO
port 3
Total GPIO
pins
-
11
Register bits corresponding to PIOn_m pins which are not available are reserved.
9.2 Introduction
9.2.1 Features
•
•
•
•
•
•
GPIO pins can be configured as input or output by software.
Each individual port pin can serve as an edge or level-sensitive interrupt request.
Interrupts can be configured on single falling or rising edges and on both edges.
Level-sensitive interrupt pins can be HIGH or LOW-active.
All GPIO pins are inputs by default.
Reading and writing of data registers are masked by address bits 13:2.
9.3 Register description
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
Table 60.
Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000)
Name
Access
Address offset
Description
Reset
value
GPIOnDATA
R/W
0x0000 to 0x3FF8
Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
Section 9.4.1).
n/a
GPIOnDATA
R/W
0x3FFC
Port n data register for pins PIOn_0 to
PIOn_11
n/a
-
-
0x4000 to 0x7FFC
reserved
-
GPIOnDIR
R/W
0x8000
Data direction register for port n
0x00
GPIOnIS
R/W
0x8004
Interrupt sense register for port n
0x00
GPIOnIBE
R/W
0x8008
Interrupt both edges register for port n
0x00
GPIOnIEV
R/W
0x800C
Interrupt event register for port n
0x00
GPIOnIE
R/W
0x8010
Interrupt mask register for port n
0x00
GPIOnRIS
R
0x8014
Raw interrupt status register for port n
0x00
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Chapter 9: LPC1102 General Purpose I/O (GPIO)
Table 60.
Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000)
Name
Access
Address offset
Description
Reset
value
GPIOnMIS
R
0x8018
Masked interrupt status register for port n
0x00
GPIOnIC
W
0x801C
Interrupt clear register for port n
0x00
-
-
0x8020 - 0xFFFF
reserved
0x00
9.3.1 GPIO data register
The GPIOnDATA register holds the current logic state of the pin (HIGH or LOW),
independently of whether the pin is configured as an GPIO input or output or as another
digital function. If the pin is configured as GPIO output, the current value of the
GPIOnDATA register is driven to the pin.
Table 61.
GPIOnDATA register (GPIO0DATA, address 0x5000 0000 to 0x5000 3FFC;
GPIO1DATA, address 0x5001 0000 to 0x5001 3FFC; GPIO2DATA, address 0x5002
0000 to 0x5002 3FFC; GPIO3DATA, address 0x5003 0000 to 0x5003 3FFC) bit
description
Bit
Symbol
Description
Reset Access
value
11:0
DATA
Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = n/a
0.
R/W
31:12
-
Reserved
-
-
A read of the GPIOnDATA register always returns the current logic level (state) of the pin
independently of its configuration. Because there is a single data register for both the
value of the output driver and the state of the pin’s input, write operations have different
effects depending on the pin’s configuration:
• If a pin is configured as GPIO input, a write to the GPIOnDATA register has no effect
on the pin level. A read returns the current state of the pin.
• If a pin is configured as GPIO output, the current value of GPIOnDATA register is
driven to the pin. This value can be a result of writing to the GPIOnDATA register, or it
can reflect the previous state of the pin if the pin is switched to GPIO output from
GPIO input or another digital function. A read returns the current state of the pin.
• If a pin is configured as another digital function (input or output), a write to the
GPIOnDATA register has no effect on the pin level. A read returns the current state of
the pin even if it is configured as an output. This means that by reading the
GPIOnDATA register, the digital output or input value of a function other than GPIO on
that pin can be observed.
The following rules apply when the pins are switched from input to output:
• Pin is configured as input with a HIGH level applied:
– Change pin to output: pin drives HIGH level.
• Pin is configured as input with a LOW level applied:
– Change pin to output: pin drives LOW level.
The rules show that the pins mirror the current logic level. Therefore floating pins may
drive an unpredictable level when switched from input to output.
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Chapter 9: LPC1102 General Purpose I/O (GPIO)
9.3.2 GPIO data direction register
Table 62.
GPIOnDIR register (GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address
0x5003 8000) bit description
Bit
Symbol
Description
Reset
value
Access
11:0
IO
Selects pin x as input or output (x = 0 to 11).
0 = Pin PIOn_x is configured as input.
1 = Pin PIOn_x is configured as output.
0x00
R/W
31:12
-
Reserved
-
-
9.3.3 GPIO interrupt sense register
Table 63.
GPIOnIS register (GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003
8004) bit description
Bit
Symbol
Description
Reset Access
value
11:0
ISENSE
Selects interrupt on pin x as level or edge sensitive (x = 0 to 0x00
11).
0 = Interrupt on pin PIOn_x is configured as edge sensitive.
1 = Interrupt on pin PIOn_x is configured as level sensitive.
R/W
31:12
-
Reserved
-
-
9.3.4 GPIO interrupt both edges sense register
Table 64.
GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003
8008) bit description
Bit
Symbol Description
Reset Access
value
11:0
IBE
Selects interrupt on pin x to be triggered on both edges (x = 0 0x00
to 11).
0 = Interrupt on pin PIOn_x is controlled through register
GPIOnIEV.
1 = Both edges on pin PIOn_x trigger an interrupt.
R/W
31:12
-
Reserved
-
-
9.3.5 GPIO interrupt event register
Table 65.
UM10429
User manual
GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003
800C) bit description
Bit
Symbol
Description
Reset Access
value
11:0
IEV
Selects interrupt on pin x to be triggered rising or falling
edges (x = 0 to 11).
0 = Depending on setting in register GPIOnIS (see
Table 63), falling edges or LOW level on pin PIOn_x
trigger an interrupt.
1 = Depending on setting in register GPIOnIS (see
Table 63), rising edges or HIGH level on pin PIOn_x
trigger an interrupt.
0x00
R/W
31:12
-
Reserved
-
-
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Chapter 9: LPC1102 General Purpose I/O (GPIO)
9.3.6 GPIO interrupt mask register
Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their
individual interrupts and the combined GPIOnINTR line. Clearing a bit disables interrupt
triggering on that pin.
Table 66.
GPIOnIE register (GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003
8010) bit description
Bit
Symbol Description
Reset Access
value
11:0
MASK
Selects interrupt on pin x to be masked (x = 0 to 11).
0 = Interrupt on pin PIOn_x is masked.
1 = Interrupt on pin PIOn_x is not masked.
0x00
R/W
31:12
-
Reserved
-
-
9.3.7 GPIO raw interrupt status register
Bits read HIGH in the GPIOnIRS register reflect the raw (prior to masking) interrupt status
of the corresponding pins indicating that all the requirements have been met before they
are allowed to trigger the GPIOIE. Bits read as zero indicate that the corresponding input
pins have not initiated an interrupt. The register is read-only.
Table 67.
GPIOnIRS register (GPIO0IRS, address 0x5000 8014 to GPIO3IRS, address 0x5003
8014) bit description
Bit
Symbol
Description
Reset Access
value
11:0
RAWST
Raw interrupt status (x = 0 to 11).
0 = No interrupt on pin PIOn_x.
1 = Interrupt requirements met on PIOn_x.
0x00
R
31:12
-
Reserved
-
-
9.3.8 GPIO masked interrupt status register
Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an
interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input
pins has been generated or that the interrupt is masked. GPIOMIS is the state of the
interrupt after masking. The register is read-only.
Table 68.
GPIOnMIS register (GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address
0x5003 8018) bit description
Bit
Symbol Description
Reset Access
value
11:0
MASK
Selects interrupt on pin x to be masked (x = 0 to 11).
0 = No interrupt or interrupt masked on pin PIOn_x.
1 = Interrupt on PIOn_x.
0x00
R
31:12
-
Reserved
-
-
9.3.9 GPIO interrupt clear register
This register allows software to clear edge detection for port bits that are identified as
edge-sensitive in the Interrupt Sense register. This register has no effect on port bits
identified as level-sensitive.
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Chapter 9: LPC1102 General Purpose I/O (GPIO)
Table 69.
GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003
801C) bit description
Bit
Symbol
Description
Reset Access
value
11:0
CLR
Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00
the interrupt edge detection logic. This register is write-only.
W
Remark: The synchronizer between the GPIO and the
NVIC blocks causes a delay of 2 clocks. It is recommended
to add two NOPs after the clear of the interrupt edge
detection logic before the exit of the interrupt service
routine.
0 = No effect.
1 = Clears edge detection logic for pin PIOn_x.
31:12
-
Reserved
-
-
9.4 Functional description
9.4.1 Write/read data operation
In order for software to be able to set GPIO bits without affecting any other pins in a single
write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide
mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA
bits masked by 1 are affected by read and write operations. The masked GPIOnDATA
register can be located anywhere between address offsets 0x0000 to 0x3FFC in the
GPIOn address space. Reading and writing to the GPIOnDATA register at address
0x3FFC sets all masking bits to 1.
Write operation
If the address bit (i+2) associated with the GPIO port bit i (i = 0 to 11) to be written is
HIGH, the value of the GPIODATA register bit i is updated. If the address bit (i+2) is LOW,
the corresponding GPIODATA register bit i is left unchanged.
ADDRESS[13:2]
13
12
11
10
9
8
7
6
5
4
3
2
address 0x098
0
0
0
0
0
0
1
0
0
1
1
0
data 0xFE4
1
1
1
1
1
1
1
0
0
1
0
0
GPIODATA register
at address + 0x098
u
u
u
u
u
u
1
u
u
1
0
u
0
0
u = unchanged
Fig 8.
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Masked write operation to the GPIODATA register
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Chapter 9: LPC1102 General Purpose I/O (GPIO)
Read operation
If the address bit associated with the GPIO data bit is HIGH, the value is read. If the
address bit is LOW, the GPIO data bit is read as 0. Reading a port DATA register yields
the state of port pins 11:0 ANDed with address bits 13:2.
Fig 9.
UM10429
User manual
ADDRESS[13:2]
13
12
11
10
9
8
7
6
5
4
3
2
address 0x0C4
0
0
0
0
0
0
1
1
0
0
0
1
port pin settings
1
1
1
1
1
1
1
0
0
1
0
0
data read
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Masked read operation
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Chapter 10: LPC1102 Universal Asynchronous Transmitter
(UART)
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User manual
10.1 How to read this chapter
The UART block is implemented on the LPC1101 without modem control.
10.2 Basic configuration
The UART is configured using the following registers:
1. Pins: The UART pins must be configured in the IOCONFIG register block
(Section 7.4.1) before the UART clocks can be enabled.
2. Power: In the SYSAHBCLKCTRL register, set bit 12 (Table 19).
3. Peripheral clock: Enable the UART peripheral clock by writing to the UARTCLKDIV
register (Table 21).
10.3 Features
•
•
•
•
•
•
16-byte receive and transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Built-in baud rate generator.
UART allows for implementation of either software or hardware flow control.
RS-485/EIA-485 9-bit mode support with output enable.
10.4 Pin description
Table 70.
UART pin description
Pin
Type
Description
RXD
Input
Serial Input. Serial receive data.
TXD
Output Serial Output. Serial transmit data.
10.5 Register description
The UART contains registers organized as shown in Table 71. The Divisor Latch Access
Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 71.
Register overview: UART (base address: 0x4000 8000)
Name
Access Address Description
offset
Reset
value
U0RBR
RO
0x000
Receiver Buffer Register. Contains the next received character to be read.
(DLAB=0)
NA
U0THR
WO
0x000
Transmit Holding Register. The next character to be transmitted is written
here. (DLAB=0)
NA
U0DLL
R/W
0x000
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The 0x01
full divisor is used to generate a baud rate from the fractional rate divider.
(DLAB=1)
U0DLM
R/W
0x004
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The 0x00
full divisor is used to generate a baud rate from the fractional rate divider.
(DLAB=1)
U0IER
R/W
0x004
Interrupt Enable Register. Contains individual interrupt enable bits for the 7
potential UART interrupts. (DLAB=0)
0x00
U0IIR
RO
0x008
Interrupt ID Register. Identifies which interrupt(s) are pending.
0x01
U0FCR
WO
0x008
FIFO Control Register. Controls UART FIFO usage and modes.
0x00
U0LCR
R/W
0x00C
Line Control Register. Contains controls for frame formatting and break
generation.
0x00
-
-
0x010
Reserved
-
U0LSR
RO
0x014
Line Status Register. Contains flags for transmit and receive status,
including line errors.
0x60
-
-
0x018
Reserved
-
U0SCR
R/W
0x01C
Scratch Pad Register. Eight-bit temporary storage for software.
0x00
U0ACR
R/W
0x020
Auto-baud Control Register. Contains controls for the auto-baud feature.
0x00
-
-
0x024
Reserved
-
U0FDR
R/W
0x028
Fractional Divider Register. Generates a clock input for the baud rate
divider.
0x10
-
-
0x02C
Reserved
-
U0TER
R/W
0x030
Transmit Enable Register. Turns off UART transmitter for use with software 0x80
flow control.
-
-
0x034 0x048
Reserved
-
U0RS485CTRL R/W
0x04C
RS-485/EIA-485 Control. Contains controls to configure various aspects of
RS-485/EIA-485 modes.
0x00
U0ADRMATCH R/W
0x050
RS-485/EIA-485 address match. Contains the address match value for
RS-485/EIA-485 mode.
0x00
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
10.5.1 UART Receiver Buffer Register ( DLAB = 0, Read Only)
The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0RBR. The U0RBR is always Read Only.
Since PE, FE and BI bits (see Table 81) correspond to the byte sitting on the top of the
RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach
for fetching the valid pair of received byte and its status bits is first to read the content of
the U0LSR register, and then to read a byte from the U0RBR.
Table 72.
UART Receiver Buffer Register (U0RBR - address 0x4000 8000 when DLAB = 0,
Read Only) bit description
Bit
Symbol
Description
7:0
RBR
The UART Receiver Buffer Register contains the oldest received undefined
byte in the UART RX FIFO.
31:8 -
Reset Value
Reserved
-
10.5.2 UART Transmitter Holding Register (DLAB = 0, Write Only)
The U0THR is the top byte of the UART TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0THR. The U0THR is always Write Only.
Table 73.
UART Transmitter Holding Register (U0THR - address 0x4000 8000 when
DLAB = 0, Write Only) bit description
Bit
Symbol
Description
Reset Value
7:0
THR
Writing to the UART Transmit Holding Register causes the data
to be stored in the UART transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
NA
Reserved
-
31:8 -
10.5.3 UART Divisor Latch LSB and MSB Registers (DLAB = 1)
The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the UART_PCLK clock in order to
produce the baud rate clock, which must be 16x the desired baud rate. The U0DLL and
U0DLM registers together form a 16-bit divisor where U0DLL contains the lower 8 bits of
the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated
like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit
(DLAB) in U0LCR must be one in order to access the UART Divisor Latches. Details on
how to select the right value for U0DLL and U0DLM can be found in Section 10.5.13.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 74.
UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1)
bit description
Bit
Symbol
Description
Reset value
7:0
DLLSB
The UART Divisor Latch LSB Register, along with the U0DLM
register, determines the baud rate of the UART.
0x01
Reserved
-
31:8 Table 75.
UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when
DLAB = 1) bit description
Bit
Symbol
Description
Reset value
7:0
DLMSB
The UART Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UART.
0x00
Reserved
-
31:8 -
10.5.4 UART Interrupt Enable Register ( DLAB = 0)
The U0IER is used to enable the four UART interrupt sources.
Table 76.
UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit
description
Bit
Symbol
0
RBRIE
Value
0
1
1
2
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THREIE
Description
Reset
value
RBR Interrupt Enable
Enables the Receive Data Available interrupt for UART. It
also controls the Character Receive Time-out interrupt.
0
Disable the RDA interrupt.
Enable the RDA interrupt.
THRE Interrupt Enable
Enables the THRE interrupt for UART. The status of this
interrupt can be read from U0LSR[5].
0
Disable the THRE interrupt.
1
Enable the THRE interrupt.
RXLIE
RX Line Interrupt Enable
Enables the UART RX line status interrupts. The status of
this interrupt can be read from U0LSR[4:1].
3
-
6:4
-
7
-
8
ABEOIntEn
0
Disable the RX line status interrupts.
1
Enable the RX line status interrupts.
-
Reserved
0
0
-
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
-
Reserved
0
Enables the end of auto-baud interrupt.
0
0
Disable end of auto-baud Interrupt.
1
Enable end of auto-baud Interrupt.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 76.
UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit
description …continued
Bit
Symbol
Value
9
ABTOIntEn
Description
Reset
value
Enables the auto-baud time-out interrupt.
0
0
Disable auto-baud time-out Interrupt.
1
Enable auto-baud time-out Interrupt.
31:10 -
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
10.5.5 UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read
Only)
U0IIR provides a status code that denotes the priority and source of a pending interrupt.
The interrupts are frozen during a U0IIR access. If an interrupt occurs during a U0IIR
access, the interrupt is recorded for the next U0IIR access.
Table 77.
UART Interrupt Identification Register (U0IIR - address 0x4004 8008, Read Only)
bit description
Bit
Symbol
0
IntStatus
Value Description
Interrupt status. Note that U0IIR[0] is active low. The
pending interrupt can be determined by evaluating
U0IIR[3:1].
0
1
3:1
Reset
value
IntId
1
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. U0IER[3:1] identifies an interrupt
0
corresponding to the UART Rx FIFO. All other combinations
of U0IER[3:1] not listed below are reserved (000,
100,101,111).
0x3
1 - Receive Line Status (RLS).
0x2
2a - Receive Data Available (RDA).
0x6
2b - Character Time-out Indicator (CTI).
0x1
3 - THRE Interrupt.
5:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
7:6
FIFOEnable
These bits are equivalent to U0FCR[0].
0
8
ABEOInt
End of auto-baud interrupt. True if auto-baud has finished
successfully and interrupt is enabled.
0
9
ABTOInt
Auto-baud time-out interrupt. True if auto-baud has timed
out and interrupt is enabled.
0
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
31:10 -
Bits U0IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the
IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the
type of interrupt and handling as described in Table 78. Given the status of U0IIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U0IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon a U0LSR read.
The UART RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the
trigger level defined in U0FCR7:6 and is reset when the UART Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U0IIR[3:1] = 110) is a second level interrupt and is set when the UART
Rx FIFO contains at least one character and no UART Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART Rx FIFO activity (read or write of UART RSR) will
clear the interrupt. This interrupt is intended to flush the UART RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 78.
Interrupt source
0001
None
0110
UM10429
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UART Interrupt Handling
U0IIR[3:0] Priority Interrupt
value[1]
type
-
None
Highest RX Line
Status /
Error
OE[2]
Interrupt
reset
-
or
PE[2]
or
FE[2]
or
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BI[2]
U0LSR
Read[2]
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 78.
UART Interrupt Handling
U0IIR[3:0] Priority Interrupt
value[1]
type
Interrupt source
Interrupt
reset
0100
Second RX Data
Available
Rx data available or trigger level reached in FIFO
(U0FCR0=1)
U0RBR
Read[3] or
UART FIFO
drops below
trigger level
1100
Second Character Minimum of one character in the RX FIFO and no
Time-out character input or removed during a time period
indication depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
U0RBR
Read[3]
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number
of characters) × 8 + 1] RCLKs
0010
Third
THRE
THRE[2]
U0IIR
Read[4] (if
source of
interrupt) or
THR write
[1]
Values “0000”, “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2]
For details see Section 10.5.8 “UART Line Status Register”
[3]
For details see Section 10.5.1 “UART Receiver Buffer Register ( DLAB = 0, Read Only)”
[4]
For details see Section 10.5.5 “UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only)”
and Section 10.5.2 “UART Transmitter Holding Register (DLAB = 0, Write Only)”
The UART THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated
when the UART THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U0THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
10.5.6 UART FIFO Control Register (Write Only)
The U0FCR controls the operation of the UART RX and TX FIFOs.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 79.
UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit
description
Bit
Symbol
Value Description
0
FIFOEN
FIFO Enable
1
2
RXFIFO
RES
TXFIFO
RES
Reset
value
0
0
UART FIFOs are disabled. Must not be used in the application.
1
Active high enable for both UART Rx and TX FIFOs and
U0FCR[7:1] access. This bit must be set for proper UART
operation. Any transition on this bit will automatically clear the
UART FIFOs.
RX FIFO Reset
0
0
No impact on either of UART FIFOs.
1
Writing a logic 1 to U0FCR[1] will clear all bytes in UART Rx FIFO,
reset the pointer logic. This bit is self-clearing.
TX FIFO Reset
0
0
No impact on either of UART FIFOs.
1
Writing a logic 1 to U0FCR[2] will clear all bytes in UART TX
FIFO, reset the pointer logic. This bit is self-clearing.
3
-
Reserved
0
5:4
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
7:6
RXTL
RX Trigger Level
These two bits determine how many receiver UART FIFO
characters must be written before an interrupt is activated.
0
31:8 -
-
0x0
Trigger level 0 (1 character or 0x01).
0x1
Trigger level 1 (4 characters or 0x04).
0x2
Trigger level 2 (8 characters or 0x08).
0x3
Trigger level 3 (14 characters or 0x0E).
-
Reserved
-
10.5.7 UART Line Control Register
The U0LCR determines the format of the data character that is to be transmitted or
received.
Table 80.
Bit
Symbol Value Description
Reset
Value
1:0
WLS
0
2
UM10429
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UART Line Control Register (U0LCR - address 0x4000 800C) bit description
Word Length Select
0x0
5-bit character length.
0x1
6-bit character length.
0x2
7-bit character length.
0x3
8-bit character length.
SBS
Stop Bit Select
0
1 stop bit.
1
2 stop bits (1.5 if U0LCR[1:0]=00).
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 80.
UART Line Control Register (U0LCR - address 0x4000 800C) bit description
Bit
Symbol Value Description
Reset
Value
3
PE
0
5:4
Parity Enable
0
Disable parity generation and checking.
1
Enable parity generation and checking.
PS
Parity Select
0x0
Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
0x1
Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
0x2
Forced 1 stick parity.
0x3
6
7
31:
8
0
Forced 0 stick parity.
BC
Break Control
0
0
Disable break transmission.
1
Enable break transmission. Output pin UART TXD is forced to logic
0 when U0LCR[6] is active high.
DLAB
Divisor Latch Access Bit (DLAB)
-
0
Disable access to Divisor Latches.
1
Enable access to Divisor Latches.
-
Reserved
0
-
10.5.8 UART Line Status Register
The U0LSR is a Read Only register that provides status information on the UART TX and
RX blocks.
Table 81.
UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
description
Bit Symbol
0
1
UM10429
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Value Description
RDR
Reset
Value
Receiver Data Ready:U0LSR[0] is set when the U0RBR holds
an unread character and is cleared when the UART RBR FIFO
is empty.
0
U0RBR is empty.
1
U0RBR contains valid data.
OE
0
Overrun Error
0
The overrun error condition is set as soon as it occurs. A
U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART
RSR has a new character assembled and the UART RBR FIFO
is full. In this case, the UART RBR FIFO will not be overwritten
and the character in the UART RSR will be lost.
0
Overrun error status is inactive.
1
Overrun error status is active.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 81.
UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
description …continued
Bit Symbol
2
Value Description
PE
Reset
Value
Parity Error
0
When the parity bit of a received character is in the wrong state,
a parity error occurs. A U0LSR read clears U0LSR[2]. Time of
parity error detection is dependent on U0FCR[0].
Note: A parity error is associated with the character at the top of
the UART RBR FIFO.
3
0
Parity error status is inactive.
1
Parity error status is active.
FE
Framing Error
0
When the stop bit of a received character is a logic 0, a framing
error occurs. A U0LSR read clears U0LSR[3]. The time of the
framing error detection is dependent on U0FCR0. Upon
detection of a framing error, the RX will attempt to
re-synchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no Framing
Error.
Note: A framing error is associated with the character at the top
of the UART RBR FIFO.
4
0
Framing error status is inactive.
1
Framing error status is active.
BI
Break Interrupt
When RXD1 is held in the spacing state (all zeros) for one full
character transmission (start, data, parity, stop), a break
interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXD1 goes to marking state (all
ones). A U0LSR read clears this status bit. The time of break
detection is dependent on U0FCR[0].
0
Note: The break interrupt is associated with the character at the
top of the UART RBR FIFO.
5
6
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0
Break interrupt status is inactive.
1
Break interrupt status is active.
THRE
Transmitter Holding Register Empty
THRE is set immediately upon detection of an empty UART
THR and is cleared on a U0THR write.
0
U0THR contains valid data.
1
U0THR is empty.
1
1
Transmitter Empty
TEMT is set when both U0THR and U0TSR are empty; TEMT is
cleared when either the U0TSR or the U0THR contain valid
data.
TEMT
0
U0THR and/or the U0TSR contains valid data.
1
U0THR and the U0TSR are empty.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 81.
UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
description …continued
Bit Symbol
7
Value Description
RXFE
Reset
Value
Error in RX FIFO
U0LSR[7] is set when a character with a RX error such as
framing error, parity error or break interrupt, is loaded into the
U0RBR. This bit is cleared when the U0LSR register is read
and there are no subsequent errors in the UART FIFO.
31: 8
0
U0RBR contains no UART RX errors or U0FCR[0]=0.
1
UART RBR contains at least one UART RX error.
-
Reserved
0
-
10.5.9 UART Scratch Pad Register
The U0SCR has no effect on the UART operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the U0SCR has occurred.
Table 82.
UART Scratch Pad Register (U0SCR - address 0x4000 8014) bit description
Bit Symbol Description
Reset Value
7:0 Pad
A readable, writable byte.
0x00
31: 8
Reserved
-
10.5.10 UART Auto-baud Control Register
The UART Auto-baud Control Register (U0ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Table 83.
Bit
Symbol
0
Start
1
2
7:3
UM10429
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Auto-baud Control Register (U0ACR - address 0x4000 8020) bit description
Value Description
This bit is automatically cleared after auto-baud
completion.
0
0
Auto-baud stop (auto-baud is not running).
1
Auto-baud start (auto-baud is running). Auto-baud run
bit. This bit is automatically cleared after auto-baud
completion.
Mode
Auto-baud mode select bit.
0
0
Mode 0.
1
Mode 1.
0
No restart
1
Restart in case of time-out (counter restarts at next
UART Rx falling edge)
NA
Reserved, user software should not write ones to
0
reserved bits. The value read from a reserved bit is not
defined.
AutoRestart
-
Reset value
Restart select.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 83.
Auto-baud Control Register (U0ACR - address 0x4000 8020) bit description
Bit
Symbol
8
ABEOIntClr
9
Value Description
End of auto-baud interrupt clear bit (write only
accessible).
0
0
Writing a 0 has no impact.
1
Writing a 1 will clear the corresponding interrupt in the
U0IIR.
ABTOIntClr
31:10 -
Reset value
Auto-baud time-out interrupt clear bit (write only
accessible).
0
0
Writing a 0 has no impact.
1
Writing a 1 will clear the corresponding interrupt in the
U0IIR.
NA
Reserved, user software should not write ones to
0
reserved bits. The value read from a reserved bit is not
defined.
10.5.11 Auto-baud
The UART auto-baud function can be used to measure the incoming baud rate based on
the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit
time of the receive data stream and set the divisor latch registers U0DLM and U0DLL
accordingly.
Auto-baud is started by setting the U0ACR Start bit. Auto-baud can be stopped by clearing
the U0ACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the U0ACR
Mode bit. In Mode 0 the baud rate is measured on two subsequent falling edges of the
UART Rx pin (the falling edge of the start bit and the falling edge of the least significant
bit). In Mode 1 the baud rate is measured between the falling edge and the subsequent
rising edge of the UART Rx pin (the length of the start bit).
The U0ACR AutoRestart bit can be used to automatically restart baud rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set, the rate
measurement will restart at the next falling edge of the UART Rx pin.
The auto-baud function can generate two interrupts.
• The U0IIR ABTOInt interrupt will get set if the interrupt is enabled (U0IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
• The U0IIR ABEOInt interrupt will get set if the interrupt is enabled (U0IER ABEOIntEn
is set and the auto-baud has completed successfully).
The auto-baud interrupts have to be cleared by setting the corresponding U0ACR
ABTOIntClr and ABEOIntEn bits.
The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud.
Also, when auto-baud is used, any write to U0DLM and U0DLL registers should be done
before U0ACR register write. The minimum and the maximum baud rates supported by
UART are function of UART_PCLK, number of data bits, stop bits and parity bits.
(2)
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
2 × P CLK
PCLK
ratemin = ------------------------- ≤ UART baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax
16 × ( 2 + databits + paritybits + stopbits )
16 × 2 15
10.5.12 Auto-baud modes
When the software is expecting an ”AT" command, it configures the UART with the
expected character format and sets the U0ACR Start bit. The initial values in the divisor
latches U0DLM and U0DLM don‘t care. Because of the ”A" or ”a" ASCII coding
(”A" = 0x41, ”a" = 0x61), the UART Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the U0ACR Start bit is set, the
auto-baud protocol will execute the following phases:
1. On U0ACR Start bit setting, the baud rate measurement counter is reset and the
UART U0RSR is reset. The U0RSR baud rate is switched to the highest rate.
2. A falling edge on UART Rx pin triggers the beginning of the start bit. The rate
measuring counter will start counting UART_PCLK cycles.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the UART input clock, guaranteeing the start bit is stored in the
U0RSR.
4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate
counter will continue incrementing with the pre-scaled UART input clock
(UART_PCLK).
5. If Mode = 0, the rate counter will stop on next falling edge of the UART Rx pin. If
Mode = 1, the rate counter will stop on the next rising edge of the UART Rx pin.
6. The rate counter is loaded into U0DLM/U0DLL and the baud rate will be switched to
normal operation. After setting the U0DLM/U0DLL, the end of auto-baud interrupt
U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the
remaining bits of the ”A/a" character.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
'A' (0x41) or 'a' (0x61)
start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity stop
UARTn RX
start bit
LSB of 'A' or 'a'
U0ACR start
rate counter
16xbaud_rate
16 cycles
16 cycles
a. Mode 0 (start bit and LSB are used for auto-baud)
'A' (0x41) or 'a' (0x61)
start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity stop
UARTn RX
start bit
LSB of 'A' or 'a'
U1ACR start
rate counter
16xbaud_rate
16 cycles
b. Mode 1 (only start bit is used for auto-baud)
Fig 10. Auto-baud a) mode 0 and b) mode 1 waveform
10.5.13 UART Fractional Divider Register (U0FDR - 0x4000 8028)
The UART Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 84.
UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description
Bit
Function
Description
Reset
value
3:0
DIVADDVAL
Baud rate generation pre-scaler divisor value. If this field is 0,
0
fractional baud rate generator will not impact the UART baud rate.
7:4
MULVAL
Baud rate pre-scaler multiplier value. This field must be greater or 1
equal 1 for UART to operate properly, regardless of whether the
fractional baud rate generator is used or not.
31:8
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
0
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baud rate can be calculated as:
(3)
PCLK
UART baudrate = ---------------------------------------------------------------------------------------------------------------------------------DivAddVal
16 × ( 256 × U0DLM + U0DLL ) × ⎛ 1 + -----------------------------⎞
⎝
MulVal ⎠
Where UART_PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART
baud rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL< MULVAL
The value of the U0FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U0FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
10.5.13.1 Baud rate calculation
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baud rate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Calculating UART
baudrate (BR)
PCLK,
BR
DL est = PCLK/(16 x BR)
DL est is an
integer?
True
False
DIVADDVAL = 0
MULVAL = 1
FR est = 1.5
Pick another FR est from
the range [1.1, 1.9]
DL est = Int(PCLK/(16 x BR x FR est))
FR est = PCLK/(16 x BR x DL est)
False
1.1 < FR est < 1.9?
True
DIVADDVAL = table(FR est )
MULVAL = table(FR est )
DLM = DL est [15:8]
DLL = DLest [7:0]
End
Fig 11. Algorithm for setting UART dividers
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Table 85.
10.5.13.1.1
Fractional Divider setting look-up table
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
1.000
0/1
1.250
1/4
1.500
1/2
1.750
3/4
1.067
1/15
1.267
4/15
1.533
8/15
1.769
10/13
1.071
1/14
1.273
3/11
1.538
7/13
1.778
7/9
1.077
1/13
1.286
2/7
1.545
6/11
1.786
11/14
1.083
1/12
1.300
3/10
1.556
5/9
1.800
4/5
1.091
1/11
1.308
4/13
1.571
4/7
1.818
9/11
1.100
1/10
1.333
1/3
1.583
7/12
1.833
5/6
1.111
1/9
1.357
5/14
1.600
3/5
1.846
11/13
1.125
1/8
1.364
4/11
1.615
8/13
1.857
6/7
1.133
2/15
1.375
3/8
1.625
5/8
1.867
13/15
1.143
1/7
1.385
5/13
1.636
7/11
1.875
7/8
1.154
2/13
1.400
2/5
1.643
9/14
1.889
8/9
1.167
1/6
1.417
5/12
1.667
2/3
1.900
9/10
1.182
2/11
1.429
3/7
1.692
9/13
1.909
10/11
1.200
1/5
1.444
4/9
1.700
7/10
1.917
11/12
1.214
3/14
1.455
5/11
1.714
5/7
1.923
12/13
1.222
2/9
1.462
6/13
1.727
8/11
1.929
13/14
1.231
3/13
1.467
7/15
1.733
11/15
1.933
14/15
Example 1: UART_PCLK = 14.7456 MHz, BR = 9600
According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)
= 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and
DLL = 96.
10.5.13.1.2
Example 2: UART_PCLK = 12 MHz, BR = 115200
According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) =
6.51. This DLest is not an integer number and the next step is to estimate the FR
parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest
is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1
and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up
table.
The closest value for FRest = 1.628 in the look-up Table 85 is FR = 1.625. It is equivalent
to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equation 3, the UART’s baud rate is
115384. This rate has a relative error of 0.16% from the originally specified 115200.
10.5.14 UART Transmit Enable Register
In addition to being equipped with full hardware flow control (auto-cts and auto-rts
mechanisms described above), U0TER enables implementation of software flow control.
When TxEn = 1, UART transmitter will keep sending data as long as they are available. As
soon as TxEn becomes 0, UART transmission will stop.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
Although Table 86 describes how to use TxEn bit in order to achieve hardware flow
control, it is strongly suggested to let UART hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
Table 86 describes how to use TXEn bit in order to achieve software flow control.
Table 86.
UART Transmit Enable Register (U0TER - address 0x4000 8030) bit description
Bit
Symbol
Description
6:0
-
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
7
TXEN
When this bit is 1, as it is after a Reset, data written to the THR 1
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it detects that the a hardware-handshaking TX-permit
signal (CTS) has gone false, or with software handshaking,
when it receives an XOFF character (DC3). Software can set
this bit again when it detects that the TX-permit signal has gone
true, or when it receives an XON (DC1) character.
31:8 -
Reset Value
Reserved
-
10.5.15 UART RS485 Control register
The U0RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 87.
Bit
Symbol
0
NMMEN
1
2
User manual
Value
Description
Reset
value
RS-485/EIA-485 mode
0
0
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is disabled.
1
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is enabled. In this mode, an address is detected
when a received byte causes the UART to set the
parity error and generate an interrupt.
RXDIS
Receiver enable/disable
0
The receiver is enabled.
1
The receiver is disabled.
AADEN
31:3 -
UM10429
UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit
description
0
Auto Address Detect (AAD) enable/disable
0
0
Auto Address Detect (AAD) is disabled.
1
Auto Address Detect (AAD) is enabled.
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
10.5.16 UART RS-485 Address Match register (U0RS485ADRMATCH - 0x4000
8050)
The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
Table 88.
UART RS-485 Address Match register (U0RS485ADRMATCH - address
0x4000 8050) bit description
Bit
Symbol
Description
Reset value
7:0
ADRMATCH
Contains the address match value.
0x00
31:8
-
Reserved
-
10.5.17 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored
and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it
will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The
processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted
and stored in the RXFIFO regardless of whether they are data or address. When an
address character is received a parity error interrupt will be generated and the processor
can decide whether or not to disable the receiver.
RS-485/EIA-485 Auto Address Detection (AAD) mode
When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are
set, the UART is in auto address detect mode.
In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit
value programmed into the RS485ADRMATCH register.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if it
is either a data byte OR an address byte which fails to match the RS485ADRMATCH
value.
When a matching address character is detected it will be pushed onto the RXFIFO along
with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be
cleared by hardware). The receiver will also generate an Rx Data Ready Interrupt.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted
and stored in the RXFIFO until an address byte which does not match the
RS485ADRMATCH value is received. When this occurs, the receiver will be automatically
disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address
character will not be stored in the RXFIFO.
10.6 Architecture
The architecture of the UART is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART.
The UART receiver block, U0RX, monitors the serial input line, RXD, for valid input. The
UART RX Shift Register (U0RSR) accepts valid characters via RXD. After a valid
character is assembled in the U0RSR, it is passed to the UART RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART transmitter block, U0TX, accepts data written by the CPU or host and buffers
the data in the UART TX Holding Register FIFO (U0THR). The UART TX Shift Register
(U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the
serial output pin, TXD1.
The UART Baud Rate Generator block, U0BRG, generates the timing enables used by the
UART TX block. The U0BRG clock input source is UART_PCLK. The main clock is
divided down per the divisor specified in the U0DLL and U0DLM registers. This divided
down clock is a 16x oversample clock, NBAUDOUT.
The interrupt interface contains registers U0IER and U0IIR. The interrupt interface
receives several one clock wide enables from the U0TX and U0RX blocks.
Status information from the U0TX and U0RX is stored in the U0LSR. Control information
for the U0TX and U0RX is stored in the U0LCR.
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
U0TX
U0THR
NTXRDY
U0TSR
TXD
U0BRG
U0DLL
NBAUDOUT
U0DLM
RCLK
U0RX
NRXRDY
INTERRUPT
U0RBR
U0RSR
RXD
U0IER
U0INTR
U0IIR
U0FCR
U0LSR
U0SCR
U0LCR
PA[2:0]
PSEL
PSTB
PWRITE
APB
INTERFACE
PD[7:0]
DDIS
AR
MR
PCLK
Fig 12. UART block diagram
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Chapter 11: LPC1102 SPI0 with SSP
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11.1 How to read this chapter
The LPC1102 includes one SPI interface.
Remark: The SPI block includes the full SSP feature set, and all register names use the
SSP prefix.
11.2 Basic configuration
The SPI0 is configured using the following registers:
1. Pins: The SPI pins must be configured in the IOCONFIG register block.
2. Power: In the SYSAHBCLKCTRL register, set bit 11 (Table 19).
3. Peripheral clock: Enable the SPI0 peripheral clock by writing to the SSP0CLKDIV
register (Section 3.5.15 ).
4. Reset: Before accessing the SPI block, ensure that the SSP_RST_N bits (bit 0) in the
PRESETCTRL register (Table 7) is set to 1. This de-asserts the reset signal to the SPI
blocks.
Remark: Care must be taken when using the SPI because the SPI clock SCK and the
serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the
SPI is enabled, the serial wire debugger is no longer available.
11.3 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
•
•
•
•
Synchronous Serial Communication.
Supports master or slave operation.
Eight-frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.
11.4 General description
The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
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11.5 Pin description
Table 89.
SPI pin descriptions
Pin
name
Interface pin
Type name/function
Pin description
SPI
SSI
Microwire
SCK0/1
I/O
SCK
SSEL0
I/O
SSEL FS
CLK
SK
Serial Clock. SCK/CLK/SK is a clock signal used
to synchronize the transfer of data. It is driven by
the master and received by the slave. When
SPI/SSP interface is used, the clock is
programmable to be active-high or active-low,
otherwise it is always active-high. SCK only
switches during a data transfer. Any other time, the
SPI/SSP interface either holds it in its inactive state
or does not drive it (leaves it in high-impedance
state).
CS
Frame Sync/Slave Select. When the SPI/SSP
interface is a bus master, it drives this signal to an
active state before the start of serial data and then
releases it to an inactive state after the data has
been sent.The active state of this signal can be
high or low depending upon the selected bus and
mode. When the SPI/SSP interface is a bus slave,
this signal qualifies the presence of data from the
Master according to the protocol in use.
When there is just one bus master and one bus
slave, the Frame Sync or Slave Select signal from
the Master can be connected directly to the slave’s
corresponding input. When there is more than one
slave on the bus, further qualification of their Frame
Select/Slave Select inputs will typically be
necessary to prevent more than one slave from
responding to a transfer.
MISO0
I/O
MISO DR(M) SI(M)
DX(S) SO(S)
Master In Slave Out. The MISO signal transfers
serial data from the slave to the master. When the
SPI/SSP is a slave, serial data is output on this
signal. When the SPI/SSP is a master, it clocks in
serial data from this signal. When the SPI/SSP is a
slave and is not selected by FS/SSEL, it does not
drive this signal (leaves it in high-impedance state).
MOSI0
I/O
MOSI DX(M) SO(M)
DR(S) SI(S)
Master Out Slave In. The MOSI signal transfers
serial data from the master to the slave. When the
SPI/SSP is a master, it outputs serial data on this
signal. When the SPI/SSP is a slave, it clocks in
serial data from this signal.
Remark: Care must be taken when using the SPI because the SPI clock SCK and the
serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the
SPI is enabled, the serial wire debugger is no longer available.
11.6 Register description
The register addresses of the SPI controllers are shown in Table 90.
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Remark: Register names use the SSP prefix to indicate that the SPI controllers have full
SSP capabilities.
Table 90.
Register overview: SPI0 (base address 0x4004 0000)
Name
Access Address
offset
Description
Reset
Value[1]
SSP0CR0
R/W
0x000
Control Register 0. Selects the serial clock rate, bus type, and data size.
0
SSP0CR1
R/W
0x004
Control Register 1. Selects master/slave and other modes.
0
SSP0DR
R/W
0x008
Data Register. Writes fill the transmit FIFO, and reads empty the receive
FIFO.
0
SSP0SR
RO
0x00C
Status Register
0x0000
0003
SSP0CPSR
R/W
0x010
Clock Prescale Register
0
SSP0IMSC
R/W
0x014
Interrupt Mask Set and Clear Register
0
SSP0RIS
RO
0x018
Raw Interrupt Status Register
0x0000
0008
SSP0MIS
RO
0x01C
Masked Interrupt Status Register
0
SSP0ICR
WO
0x020
SSPICR Interrupt Clear Register
NA
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
11.6.1 SPI/SSP Control Register 0
This register controls the basic operation of the SPI/SSP controller.
Table 91:
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SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000) bit description
Bit
Symbol
3:0
DSS
Value
Description
Reset
Value
Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000 to 0010 are not
supported and should not be used.
0000
0x3
4-bit transfer
0x4
5-bit transfer
0x5
6-bit transfer
0x6
7-bit transfer
0x7
8-bit transfer
0x8
9-bit transfer
0x9
10-bit transfer
0xA
11-bit transfer
0xB
12-bit transfer
0xC
13-bit transfer
0xD
14-bit transfer
0xE
15-bit transfer
0xF
16-bit transfer
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Table 91:
SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000) bit description
Bit
Symbol
5:4
FRF
6
7
15:8
Value
Reset
Value
Frame Format.
00
0x0
SPI
0x1
TI
0x2
Microwire
0x3
This combination is not supported and should not be used.
CPOL
Clock Out Polarity. This bit is only used in SPI mode.
0
SPI controller maintains the bus clock low between frames.
1
SPI controller maintains the bus clock high between frames.
CPHA
0
Clock Out Phase. This bit is only used in SPI mode.
0
SPI controller captures serial data on the first clock transition
of the frame, that is, the transition away from the inter-frame
state of the clock line.
1
SPI controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
0
Serial Clock Rate. The number of prescaler-output clocks per 0x00
bit on the bus, minus one. Given that CPSDVSR is the
prescale divider, and the APB clock PCLK clocks the
prescaler, the bit frequency is PCLK / (CPSDVSR × [SCR+1]).
SCR
31:16 -
Description
-
Reserved
-
11.6.2 SPI/SSP0 Control Register 1
This register controls certain aspects of the operation of the SPI/SSP controller.
Table 92:
Bit
Symbol
0
LBM
1
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SPI/SSP Control Register 1 (SSP0CR1 - address 0x4004 0004) bit description
Value
Description
Reset
Value
Loop Back Mode.
0
0
During normal operation.
1
Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).
SSE
SPI Enable.
0
0
The SPI controller is disabled.
1
The SPI controller will interact with other devices on the
serial bus. Software should write the appropriate control
information to the other SPI/SSP registers and interrupt
controller registers, before setting this bit.
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Table 92:
SPI/SSP Control Register 1 (SSP0CR1 - address 0x4004 0004) bit description
Bit
Symbol
2
MS
Value
Description
Reset
Value
Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
0
0
The SPI controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
1
The SPI controller acts as a slave on the bus, driving MISO
line and receiving SCLK, MOSI, and SSEL lines.
3
SOD
Slave Output Disable. This bit is relevant only in slave
0
mode (MS = 1). If it is 1, this blocks this SPI controller from
driving the transmit data line (MISO).
31:4
-
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
11.6.3 SPI/SSP Data Register
Software can write data to be transmitted to this register and read data that has been
received.
Table 93:
SPI/SSP Data Register (SSP0DR - address 0x4004 0008) bit description
Bit
Symbol
Description
Reset Value
15:0
DATA
Write: software can write data to be sent in a future frame to this 0x0000
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SPI controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bit, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SPI controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bit, the data is right-justified in this
field with higher order bits filled with 0s.
31:16 -
Reserved.
-
11.6.4 SPI/SSP Status Register
This read-only register reflects the current status of the SPI controller.
Table 94:
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SPI/SSP Status Register (SSP0SR - address 0x4004 000C) bit description
Bit
Symbol
Description
Reset Value
0
TFE
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
1
1
TNF
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
2
RNE
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
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Table 94:
SPI/SSP Status Register (SSP0SR - address 0x4004 000C) bit description
Bit
Symbol
Description
Reset Value
3
RFF
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
0
4
BSY
Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.
0
31:5
-
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
11.6.5 SPI/SSP Clock Prescale Register
This register controls the factor by which the Prescaler divides the SPI peripheral clock
SPI_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in the
SSPCR0 registers, to determine the bit clock.
Table 95:
SPI/SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010) bit
description
Bit
Symbol
7:0
CPSDVSR This even value between 2 and 254, by which SPI_PCLK is
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Description
0
31:8
-
-
Reserved.
Reset Value
Important: the SSPnCPSR value must be properly initialized, or the SPI controller will not
be able to transmit data correctly.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI
peripheral clock selected in Section 3.5.15. The content of the SSPnCPSR register is not
relevant.
In master mode, CPSDVSRmin = 2 or larger (even numbers only).
11.6.6 SPI/SSP Interrupt Mask Set/Clear Register
This register controls whether each of the four possible interrupt conditions in the SPI
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
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Table 96:
SPI/SSP Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014) bit
description
Bit
Symbol
Description
Reset
Value
0
RORIM
0
Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
1
RTIM
Software should set this bit to enable interrupt when a Receive
Time-out condition occurs. A Receive Time-out occurs when the Rx
FIFO is not empty, and no has not been read for a “time-out period".
The time-out period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR ×
[SCR+1]).
2
RXIM
Software should set this bit to enable interrupt when the Rx FIFO is at 0
least half full.
3
TXIM
Software should set this bit to enable interrupt when the Tx FIFO is at 0
least half empty.
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0
NA
11.6.7 SPI/SSP Raw Interrupt Status Register
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPIMSC registers.
Table 97:
SPI/SSP Raw Interrupt Status register (SSP0RIS - address 0x4004 0018) bit
description
Bit
Symbol
Description
Reset Value
0
RORRIS
This bit is 1 if another frame was completely received while the 0
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
1
RTRIS
This bit is 1 if the Rx FIFO is not empty, and has not been read 0
for a “time-out period". The time-out period is the same for
master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
2
RXRIS
This bit is 1 if the Rx FIFO is at least half full.
3
TXRIS
This bit is 1 if the Tx FIFO is at least half empty.
1
31:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
0
11.6.8 SPI/SSP Masked Interrupt Status Register
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPIMSC registers. When an SPI interrupt occurs, the interrupt service
routine should read this register to determine the cause(s) of the interrupt.
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Table 98:
SPI/SSP Masked Interrupt Status register (SSP0MIS - address 0x4004 001C) bit
description
Bit
Symbol
Description
0
RORMIS
This bit is 1 if another frame was completely received while the 0
RxFIFO was full, and this interrupt is enabled.
Reset Value
1
RTMIS
This bit is 1 if the Rx FIFO is not empty, has not been read for
a “time-out period", and this interrupt is enabled. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
2
RXMIS
This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0
is enabled.
3
TXMIS
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
0
31:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
0
11.6.9 SPI/SSP Interrupt Clear Register
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SPI controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO or disabled by
clearing the corresponding bit in SSPIMSC registers.
Table 99:
SPI/SSP interrupt Clear Register (SSP0ICR - address 0x4004 0020) bit description
Bit
Symbol
Description
Reset Value
0
RORIC
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
NA
1
RTIC
Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read for a timeout period interrupt. The timeout
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
NA
31:2
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
11.7 Functional description
11.7.1 Texas Instruments synchronous serial frame format
Figure 13 shows the 4-wire Texas Instruments synchronous serial frame format supported
by the SPI module.
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CLK
FS
DX/DR
MSB
LSB
4 to 16 bits
a. Single frame transfer
CLK
FS
DX/DR
MSB
LSB
MSB
4 to 16 bits
LSB
4 to 16 bits
b. Continuous/back-to-back frames transfer
Fig 13. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
Frames Transfer
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is in 3-state mode whenever the SSP is idle. Once the bottom entry
of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to
be transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.
11.7.2 SPI frame format
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.
11.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
When the CPOL clock polarity control bit is LOW, it produces a steady state low value on
the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is
placed on the CLK pin when data is not being transferred.
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The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is
LOW, data is captured on the first clock edge transition. If the CPHA clock phase control
bit is HIGH, data is captured on the second clock edge transition.
11.7.2.2 SPI format with CPOL=0,CPHA=0
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in Figure 14.
SCK
SSEL
MSB
MOSI
MISO
LSB
MSB
LSB
Q
4 to 16 bits
a. Single transfer with CPOL=0 and CPHA=0
SCK
SSEL
MOSI
MISO
MSB
LSB
MSB
LSB
MSB
Q
LSB
MSB
LSB
Q
4 to 16 bits
4 to 16 bits
b. Continuous transfer with CPOL=0 and CPHA=0
Fig 14. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)
In this configuration, during idle periods:
• The CLK signal is forced LOW.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is captured on the rising and propagated on the falling edges of the SCK signal.
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In the case of a single word transmission, after all bits of the data word have been
transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
11.7.2.3 SPI format with CPOL=0,CPHA=1
The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in
Figure 15, which covers both single and continuous transfers.
SCK
SSEL
MOSI
MISO
Q
MSB
LSB
MSB
LSB
Q
4 to 16 bits
Fig 15. SPI frame format with CPOL=0 and CPHA=1
In this configuration, during idle periods:
• The CLK signal is forced LOW.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin
is enabled. After a further one half SCK period, both master and slave valid data is
enabled onto their respective transmission lines. At the same time, the SCK is enabled
with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line is
returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
11.7.2.4 SPI format with CPOL = 1,CPHA = 0
Single and continuous transmission signal sequences for SPI format with CPOL=1,
CPHA=0 are shown in Figure 16.
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SCK
SSEL
MSB
MOSI
MISO
LSB
MSB
LSB
Q
4 to 16 bits
a. Single transfer with CPOL=1 and CPHA=0
SCK
SSEL
MOSI
MISO
MSB
LSB
MSB
LSB
MSB
Q
LSB
MSB
LSB
Q
4 to 16 bits
4 to 16 bits
b. Continuous transfer with CPOL=1 and CPHA=0
Fig 16. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)
In this configuration, during idle periods:
• The CLK signal is forced HIGH.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW, which causes
slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI
pin is enabled.
One half period later, valid master data is transferred to the MOSI line. Now that both the
master and slave data have been set, the SCK master clock pin becomes LOW after one
further half SCK period. This means that data is captured on the falling edges and be
propagated on the rising edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSEL line is returned to its idle HIGH state one SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
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11.7.2.5 SPI format with CPOL = 1,CPHA = 1
The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in
Figure 17, which covers both single and continuous transfers.
SCK
SSEL
MOSI
MISO
Q
MSB
LSB
MSB
LSB
Q
4 to 16 bits
Fig 17. SPI Frame Format with CPOL = 1 and CPHA = 1
In this configuration, during idle periods:
• The CLK signal is forced HIGH.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is
enabled. After a further one half SCK period, both master and slave data are enabled onto
their respective transmission lines. At the same time, the SCK is enabled with a falling
edge transition. Data is then captured on the rising edges and propagated on the falling
edges of the SCK signal.
After all bits have been transferred, in the case of a single word transmission, the SSEL
line is returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSEL pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state
as described above. In general, for continuous back-to-back transfers the SSEL pin is
held LOW between successive data words and termination is the same as that of the
single word transfer.
11.7.3 Semiconductor Microwire frame format
Figure 18 shows the Microwire frame format for a single frame. Figure 19 shows the same
format when back-to-back frames are transmitted.
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Chapter 11: LPC1102 SPI0 with SSP
SK
CS
SO
MSB
LSB
8-bit control
SI
0 MSB
LSB
4 to 16 bits
of output data
Fig 18. Microwire frame format (single transfer)
SK
CS
SO
LSB
MSB
LSB
8-bit control
SI
0 MSB
LSB
4 to 16 bits
of output data
MSB
LSB
4 to 16 bits
of output data
Fig 19. Microwire frame format (continuos transfers)
Microwire format is very similar to SPI format, except that transmission is half-duplex
instead of full-duplex, using a master-slave message passing technique. Each serial
transmission begins with an 8-bit control word that is transmitted from the SPI/SSP to the
off-chip slave device. During this transmission, no incoming data is received by the
SPI/SSP. After the message has been sent, the off-chip slave decodes it and, after waiting
one serial clock after the last bit of the 8-bit control message has been sent, responds with
the required data. The returned data is 4 to 16 bit in length, making the total frame length
anywhere from 13 to 25 bits.
In this configuration, during idle periods:
• The SK signal is forced LOW.
• CS is forced HIGH.
• The transmit data line SO is arbitrarily forced LOW.
A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge
of CS causes the value contained in the bottom entry of the transmit FIFO to be
transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control
frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame
transmission. The SI pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising
edge of each SK. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state, and the slave responds by transmitting data back
to the SPI/SSP. Each bit is driven onto SI line on the falling edge of SK. The SPI/SSP in
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Chapter 11: LPC1102 SPI0 with SSP
turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers,
the CS signal is pulled HIGH one clock period after the last bit has been latched in the
receive serial shifter, that causes the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of
SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as a
single transfer. However, the CS line is continuously asserted (held LOW) and
transmission of data occurs back to back. The control byte of the next frame follows
directly after the LSB of the received data from the current frame. Each of the received
values is transferred from the receive shifter on the falling edge SK, after the LSB of the
frame has been latched into the SPI/SSP.
11.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire
mode
In the Microwire mode, the SPI/SSP slave samples the first bit of receive data on the
rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must
ensure that the CS signal has sufficient setup and hold margins with respect to the rising
edge of SK.
Figure 20 illustrates these setup and hold time requirements. With respect to the SK rising
edge on which the first bit of receive data is to be sampled by the SPI/SSP slave, CS must
have a setup of at least two times the period of SK on which the SPI/SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.
t HOLD= tSK
tSETUP=2*tSK
SK
CS
SI
Fig 20. Microwire frame format setup and hold details
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12.1 How to read this chapter
The 16-bit timer blocks do not contain capture inputs and operate in timer mode only.
12.2 Basic configuration
The CT16B0/1 are configured using the following registers:
1. Pins: The CT16B0/1 pins must be configured in the IOCONFIG register block
(Section 7.4.1).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 7 and bit 8
(Table 19).
12.3 Features
• Two 16-bit counter/timers with a programmable 16-bit prescaler.
• Timer operation only.
• Four 16-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to three (CT16B0) or two (CT16B1) external outputs corresponding to match
registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
12.4 Applications
• Interval timer for counting internal events
• Free-running timer
• Pulse Width Modulator via match outputs
12.5 Description
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) and can
optionally generate interrupts or perform other actions at specified timer values based on
four match registers.
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
In PWM mode, three match registers on CT16B0 can be used to provide a single-edge
controlled PWM output on the match output pins. It is recommended to use the match
registers that are not pinned out to control the PWM cycle length.
Remark: The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are
functionally identical except for the peripheral base address and their external pins.
12.6 Pin description
Table 100 gives a brief summary of each of the counter/timer related pins.
Table 100. Counter/timer pin description
Pin
Peripheral
Type
Description
CT16B0_MAT[2:0]
CT16B0
Output
External Match Outputs of CT16B0:
When a match register of CT16B0 (MR3:0) equals the timer counter (TC),
this output can either toggle, go LOW, go HIGH, or do nothing. The
External Match Register (EMR) and the PWM Control Register
(PWMCON) control the functionality of this output.
n/a
CT16B1
Output
no outputs available
12.7 Register description
The 16-bit counter/timer0 contains the registers shown in Table 101 and the 16-bit
counter/timer1 contains the registers shown in Table 102. More detailed descriptions
follow.
Table 101. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000)
Name
Access
Address Description
offset
Reset
value[1]
TMR16B0IR
R/W
0x000
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
0
TMR16B0TCR
R/W
0x004
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
0
TMR16B0TC
R/W
0x008
Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of 0
PCLK. The TC is controlled through the TCR.
TMR16B0PR
R/W
0x00C
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
TMR16B0PC
R/W
0x010
Prescale Counter (PC). The 16-bit PC is a counter which is incremented 0
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
TMR16B0MCR
R/W
0x014
Match Control Register (MCR). The MCR is used to control if an interrupt 0
is generated and if the TC is reset when a Match occurs.
TMR16B0MR0
R/W
0x018
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset 0
the TC, stop both the TC and PC, and/or generate an interrupt every time
MR0 matches the TC.
TMR16B0MR1
R/W
0x01C
Match Register 1 (MR1). See MR0 description.
0
TMR16B0MR2
R/W
0x020
Match Register 2 (MR2). See MR0 description.
0
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 101. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000) …continued
Name
Access
Address Description
offset
Reset
value[1]
TMR16B0MR3
R/W
0x024
Match Register 3 (MR3). See MR0 description.
0
-
-
0x028
Reserved
-
-
-
0x02C
Reserved
-
TMR16B0EMR
R/W
0x03C
External Match Register (EMR). The EMR controls the match function
and the external match pins CT16B0_MAT[2:0].
0
-
-
0x040 0x06C
Reserved
-
-
-
0x070
Reserved
-
0x074
PWM Control Register (PWMCON). The PWMCON enables PWM mode 0
for the external match pins CT16B0_MAT[2:0].
TMR16B0PWMC R/W
[1]
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 102. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000)
Name
Access
Address Description
offset
Reset
value[1]
TMR16B1IR
R/W
0x000
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
0
TMR16B1TCR
R/W
0x004
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
0
TMR16B1TC
R/W
0x008
Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of 0
PCLK. The TC is controlled through the TCR.
TMR16B1PR
R/W
0x00C
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
TMR16B1PC
R/W
0x010
Prescale Counter (PC). The 16-bit PC is a counter which is incremented 0
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
TMR16B1MCR
R/W
0x014
Match Control Register (MCR). The MCR is used to control if an interrupt 0
is generated and if the TC is reset when a Match occurs.
TMR16B1MR0
R/W
0x018
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset 0
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
TMR16B1MR1
R/W
0x01C
Match Register 1 (MR1). See MR0 description.
0
TMR16B1MR2
R/W
0x020
Match Register 2 (MR2). See MR0 description.
0
TMR16B1MR3
R/W
0x024
Match Register 3 (MR3). See MR0 description.
0
-
-
0x028
Reserved
-
-
-
0x02C
Reserved
-
TMR16B1EMR
R/W
0x03C
External Match Register (EMR). The EMR controls the match function
and the external match pins CT16B1_MAT[1:0].
0
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 102. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000) …continued
Name
Access
Address Description
offset
Reset
value[1]
-
-
0x040 0x06C
Reserved
-
-
-
0x070
Reserved
-
0x074
PWM Control Register (PWMCON). The PWMCON enables PWM mode 0
for the external match pins CT16B1_MAT[1:0].
TMR16B1PWMC R/W
[1]
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
12.7.1 Interrupt Register (TMR16B0IR and TMR16B1IR)
The Interrupt Register (IR) consists of four bits for the match interrupts and one bit for the
capture interrupt. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
Table 103. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit
description
Bit
Symbol
Description
Reset value
0
MR0 Interrupt
Interrupt flag for match channel 0.
0
1
MR1 Interrupt
Interrupt flag for match channel 1.
0
2
MR2 Interrupt
Interrupt flag for match channel 2.
0
3
MR3 Interrupt
Interrupt flag for match channel 3.
0
31:4
-
Reserved
-
12.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 104. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR address 0x4001 0004) bit description
Bit
Symbol
Description
Reset value
0
Counter Enable When one, the Timer Counter and Prescale Counter are 0
enabled for counting. When zero, the counters are
disabled.
1
Counter Reset
When one, the Timer Counter and the Prescale Counter 0
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
31:2
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
12.7.3 Timer Counter register
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 105. Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC
0x4001 0008) bit description
Bit
Symbol
Description
Reset
value
15:0
TC
Timer counter value.
0
31:16
-
Reserved.
-
12.7.4 Prescale Register
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 106. Prescale registers (TMR16B0PR, address 0x4000 C00C and TMR16B1PR
0x4001 000C) bit description
Bit
Symbol
Description
Reset
value
15:0
PR
Prescale counter max value.
0
31:16
-
Reserved.
-
12.7.5 Prescale Counter register
The 16-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Table 107: Prescale counter registers (TMR16B0PC, address 0x4001 C010 and TMR16B1PC
0x4000 0010) bit description
Bit
Symbol
Description
Reset
value
15:0
PC
Timer prescale counter value.
0
31:16
-
Reserved.
-
12.7.6 Match Control Register
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in Table 108.
Table 108. Match Control Register (TMR16B0MCR - address 0x4000 C014 and
TMR16B1MCR - address 0x4001 0014) bit description
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Bit
Symbol
0
MR0I
Value Description
Reset
value
Interrupt on MR0: an interrupt is generated when MR0
matches the value in the TC.
1
Enabled
0
Disabled
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 108. Match Control Register (TMR16B0MCR - address 0x4000 C014 and
TMR16B1MCR - address 0x4001 0014) bit description …continued
Bit
Symbol
1
MR0R
2
3
4
5
6
7
8
9
10
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Value Description
Reset
value
Reset on MR0: the TC will be reset if MR0 matches it.
1
Enabled
0
Disabled
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR0 matches the TC.
1
Enabled
0
Disabled
MR1I
Interrupt on MR1: an interrupt is generated when MR1
matches the value in the TC.
1
Enabled
0
Disabled
MR1R
Reset on MR1: the TC will be reset if MR1 matches it.
1
Enabled
0
Disabled
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR1 matches the TC.
1
Enabled
0
Disabled
MR2I
Interrupt on MR2: an interrupt is generated when MR2
matches the value in the TC.
1
Enabled
0
Disabled
MR2R
Reset on MR2: the TC will be reset if MR2 matches it.
1
Enabled
0
Disabled
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR2 matches the TC.
1
Enabled
0
Disabled
MR3I
Interrupt on MR3: an interrupt is generated when MR3
matches the value in the TC.
1
Enabled
0
Disabled
MR3R
Reset on MR3: the TC will be reset if MR3 matches it.
1
Enabled
0
Disabled
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0
0
0
0
0
0
0
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 108. Match Control Register (TMR16B0MCR - address 0x4000 C014 and
TMR16B1MCR - address 0x4001 0014) bit description …continued
Bit
Symbol
11
MR3S
31:12
Value Description
Reset
value
Stop on MR3: the TC and PC will be stopped and TCR[0] will
be set to 0 if MR3 matches the TC.
-
1
Enabled
0
Disabled
0
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
12.7.7 Match Registers 0 to 3
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 109: Match registers (TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and
TMR16B1MR0 to 3, addresses 0x4001 0018 to 24) bit description
Bit
Symbol
Description
Reset
value
15:0
MATCH
Timer counter match value.
0
31:16
-
Reserved.
-
12.7.8 External Match Register
The External Match Register provides both control and status of the external match
channels and external match pins CT16B0_MAT[2:0] and CT16B1_MAT[1:0].
If the match outputs are configured as PWM output in the PWMCON registers
(Section 12.7.9), the function of the external match registers is determined by the PWM
rules (Section 12.7.10 “Rules for single edge controlled PWM outputs” on page 114).
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 110. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address
0x4001 003C) bit description
Bit
Symbol
0
EM0
External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0,
0
whether or not this output is connected to its pin. When a match occurs between the TC
and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
1
EM1
External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1,
0
whether or not this output is connected to its pin. When a match occurs between the TC
and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6]
control the functionality of this output. This bit is driven to the
CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
2
EM2
External Match 2. This bit reflects the state of output match channel 2, whether or not
0
this output is connected to its pin. When a match occurs between the TC and MR2, this
bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output. Note that on counter/timer 0 this match channel is not pinned
out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the
IOCON registers (0 = LOW, 1 = HIGH).
3
EM3
External Match 3. This bit reflects the state of output of match channel 3. When a match 0
occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do
nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin
available for this channel on either of the 16-bit timers.
5:4
EMC0
7:6
9:8
Value
External Match Control 0. Determines the functionality of External Match 0.
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
External Match Control 1. Determines the functionality of External Match 1.
00
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
EMC2
User manual
Reset
value
00
EMC1
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Description
External Match Control 2. Determines the functionality of External Match 2.
00
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 110. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address
0x4001 003C) bit description
Bit
Symbol
11:10
EMC3
31:12
Value
Description
Reset
value
External Match Control 3. Determines the functionality of External Match 3.
00
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 111. External match control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Function
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
12.7.9 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For timer 0, three single-edge controlled PWM outputs can be selected on the
CT16B0_MAT[2:0] outputs. For timer 1, two single-edged PWM outputs can be selected
on the CT16B1_Mat[1:0] outputs. One additional match register determines the PWM
cycle length. When a match occurs in any of the other match registers, the PWM output is
set to HIGH. The timer is reset by the match register that is configured to set the PWM
cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.
Table 112. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
TMR16B1PWMC- address 0x4001 0074) bit description
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Bit
Symbol
Description
Reset value
0
PWM enable
When one, PWM mode is enabled for CT16Bn_MAT0.
When zero, CT16Bn_MAT0 is controlled by EM0.
0
1
PWM enable
When one, PWM mode is enabled for CT16Bn_MAT1.
When zero, CT16Bn_MAT1 is controlled by EM1.
0
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
Table 112. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
TMR16B1PWMC- address 0x4001 0074) bit description
Bit
Symbol
Description
Reset value
2
PWM enable
When one, PWM mode is enabled for match channel 2 0
or pin CT16B0_MAT2. When zero, match channel 2 or
pin CT16B0_MAT2 is controlled by EM2. Match channel
2 is not pinned out on timer 1.
3
PWM enable
When one, PWM mode is enabled for match channel 3.
When zero, match channel 3 is controlled by EM3.
0
Note: It is recommended to use to set the PWM cycle
because it is not pinned out.
31:4
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
12.7.10 Rules for single edge controlled PWM outputs
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
(timer is set to zero) unless their match value is equal to zero.
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
3. If a match value larger than the PWM cycle length is written to the match register, and
the PWM signal is HIGH already, then the PWM signal will be cleared on the next start
of the next PWM cycle.
4. If a match register contains the same value as the timer reset value (the PWM cycle
length), then the PWM output will be reset to LOW on the next clock tick. Therefore,
the PWM output will always consist of a one clock tick wide positive pulse with a
period determined by the PWM cycle length (i.e. the timer reload value).
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
timer goes back to zero and will stay HIGH continuously.
Note: When the match outputs are selected to serve as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
PWM2/MAT2
MR2 = 100
PWM1/MAT1
MR1 = 41
PWM0/MAT0
MR0 = 65
0
41
65
100
(counter is reset)
Fig 21. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
MAT3:0 enabled as PWM outputs by the PWCON register.
12.8 Example timer operation
Figure 22 shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 23 shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
PCLK
prescale
counter
2
timer
counter
4
0
1
2
0
1
5
2
0
6
1
0
2
0
1
1
timer counter
reset
interrupt
Fig 22. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale counter
timer counter
TCR[0]
(counter enable)
2
4
0
1
5
1
2
0
6
0
interrupt
Fig 23. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
12.9 Architecture
The block diagram for counter/timer0 and counter/timer1 is shown in Figure 24.
MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
MATCH CONTROL REGISTER
EXTERNAL MATCH REGISTER
INTERRUPT REGISTER
CONTROL
=
MATn[2:0]
INTERRUPT
=
=
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]
=
CSN
TIMER COUNTER
CE
TCI
PCLK
PRESCALE COUNTER
reset
enable
TIMER CONTROL REGISTER
MAXVAL
PRESCALE REGISTER
Fig 24. 16-bit counter/timer block diagram
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
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User manual
13.1 How to read this chapter
The 32-bit timer 0 does not contain capture inputs and operates in timer mode only. The
32-bit timer 1 contains one capture channel corresponding to one capture input.
13.2 Basic configuration
The CT32B0/1 are configured using the following registers:
1. Pins: The CT32B0/1 pins must be configured in the IOCONFIG register block
(Section 7.4.1).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 9 and bit 10
(Table 19).
13.3 Features
• Two 32-bit counter/timers with a programmable 32-bit prescaler.
• Counter or Timer operation.
• One 32-bit capture channel that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs corresponding to match registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
13.4 Applications
•
•
•
•
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Interval timer for counting internal events
Pulse Width Demodulator via capture input
Free running timer
Pulse Width Modulator via match outputs
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
13.5 Description
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
Remark: 32-bit counter/timer0 (CT32B0) and 32-bit counter/timer1 (CT32B1) are
functionally identical except for the peripheral base address.
13.6 Pin description
Table 113 gives a brief summary of each of the counter/timer related pins.
Table 113. Counter/timer pin description
Pin
Peripheral Type
Description
CT32B1_CAP0
CT32B1
Capture Signals:
A transition on a capture pin can be configured to load one of the Capture
Registers with the value in the Timer Counter and optionally generate an
interrupt.
Input
The counter/timer block can select a capture signal as a clock source
instead of the PCLK derived clock. For more details see Section 13.7.11
“Count Control Register (TMR32B0CTCR and TMR32B1TCR)” on page
126.
n/a
CT32B0
Input
no inputs avialable
CT32B0_MAT[3, 1, 0]
CT32B1
Output
CT32B1_MAT[2:0]
CT32B0
Ouput
External Match Output of CT32B0/1:
When a match register TMR32B0/1MR3:0 equals the timer counter (TC),
this output can either toggle, go LOW, go HIGH, or do nothing. The
External Match Register (EMR) and the PWM Control register (PWMCON)
control the functionality of this output.
13.7 Register description
32-bit counter/timer0 contains the registers shown in Table 114 and 32-bit counter/timer1
contains the registers shown in Table 115. More detailed descriptions follow.
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 114. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000)
Name
Access
Address Description
offset
Reset
value[1]
TMR32B0IR
R/W
0x000
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
0
TMR32B0TCR
R/W
0x004
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
0
TMR32B0TC
R/W
0x008
Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of 0
PCLK. The TC is controlled through the TCR.
TMR32B0PR
R/W
0x00C
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
TMR32B0PC
R/W
0x010
Prescale Counter (PC). The 32-bit PC is a counter which is incremented 0
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
TMR32B0MCR
R/W
0x014
Match Control Register (MCR). The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match occurs.
TMR32B0MR0
R/W
0x018
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset 0
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
TMR32B0MR1
R/W
0x01C
Match Register 1 (MR1). See MR0 description.
0
TMR32B0MR2
R/W
0x020
Match Register 2 (MR2). See MR0 description.
0
TMR32B0MR3
R/W
0x024
Match Register 3 (MR3). See MR0 description.
0
-
-
0x028
Reserved
-
-
-
0x02C
Reserved
-
TMR32B0EMR
R/W
0x03C
External Match Register (EMR). The EMR controls the match function
and the external match pins CT32B0_MAT[3:0].
0
-
-
0x040 0x06C
Reserved
-
-
-
0x070
Reserved
-
0x074
PWM Control Register (PWMCON). The PWMCON enables PWM
mode for the external match pins CT32B0_MAT[3:0].
0
TMR32B0PWMC R/W
[1]
0
0
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 115. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000)
Name
Access
Address Description
offset
Reset
value[1]
TMR32B1IR
R/W
0x000
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
0
TMR32B1TCR
R/W
0x004
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
0
TMR32B1TC
R/W
0x008
Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of 0
PCLK. The TC is controlled through the TCR.
TMR32B1PR
R/W
0x00C
Prescale Register (PR). When the Prescale Counter (below) is equal to 0
this value, the next clock increments the TC and clears the PC.
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 115. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000) …continued
Name
Access
Address Description
offset
TMR32B1PC
R/W
0x010
Prescale Counter (PC). The 32-bit PC is a counter which is incremented 0
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
TMR32B1MCR
R/W
0x014
Match Control Register (MCR). The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match occurs.
TMR32B1MR0
R/W
0x018
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset 0
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
TMR32B1MR1
R/W
0x01C
Match Register 1 (MR1). See MR0 description.
0
TMR32B1MR2
R/W
0x020
Match Register 2 (MR2). See MR0 description.
0
TMR32B1MR3
R/W
0x024
Match Register 3 (MR3). See MR0 description.
0
TMR32B1CCR
R/W
0x028
Capture Control Register (CCR). The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether or
not an interrupt is generated when a capture takes place.
0
TMR32B1CR0
RO
0x02C
Capture Register 0 (CR0). CR0 is loaded with the value of TC when
there is an event on the CT32B1_CAP0 input.
0
TMR32B1EMR
R/W
0x03C
External Match Register (EMR). The EMR controls the match function
and the external match pins CT32B1_MAT[3:0].
0
-
-
0x040 0x06C
reserved
-
TMR32B1CTCR
R/W
0x070
Count Control Register (CTCR). The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
0
TMR32B1PWMC R/W
0x074
PWM Control Register (PWMCON). The PWMCON enables PWM
mode for the external match pins CT32B1_MAT[3:0].
0
[1]
Reset
value[1]
0
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
13.7.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
The Interrupt Register consists of four bits for the match interrupts and one bit for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
Table 116. Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
description
Bit
Symbol
Description
Reset value
0
MR0 Interrupt
Interrupt flag for match channel 0.
0
1
MR1 Interrupt
Interrupt flag for match channel 1.
0
2
MR2 Interrupt
Interrupt flag for match channel 2.
0
3
MR3 Interrupt
Interrupt flag for match channel 3.
0
4
CR0 Interrupt
Interrupt flag for capture channel 0 event.
0
31:5
-
Reserved
-
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
13.7.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR)
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 117. Timer Control Register (TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR address 0x4001 8004) bit description
Bit
Symbol
Description
Reset value
0
CEN
Counter Enable
0
When one, the Timer Counter and Prescale Counter are
enabled for counting. When zero, the counters are
disabled.
1
CRES
Counter Reset
0
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
31:2
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
13.7.3 Timer Counter (TMR32B0TC - address 0x4001 4008 and
TMR32B1TC - address 0x4001 8008)
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 118. Timer counter registers (TMR32B0TC, address 0x4001 4008 and TMR32B1TC
0x4001 8008) bit description
Bit
Symbol
Description
Reset
value
31:0
TC
Timer counter value.
0
13.7.4 Prescale Register (TMR32B0PR - address 0x4001 400C and
TMR32B1PR - address 0x4001 800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 119. Prescale registers (TMR32B0PR, address 0x4001 400C and TMR32B1PR
0x4001 800C) bit description
Bit
Symbol
Description
Reset
value
31:0
PR
Prescale counter max value.
0
13.7.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and
TMR32B1PC - address 0x4001 8010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Table 120. Prescale registers (TMR32B0PC, address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description
Bit
Symbol
Description
Reset
value
31:0
PC
Timer prescale counter value.
0
13.7.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in Table 121.
Table 121. Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
bit description
Bit
Symbol
0
MR0I
1
2
3
4
5
6
7
Value Description
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
1
Enabled
0
Disabled
MR0R
Reset on MR0: the TC will be reset if MR0 matches it.
1
Enabled
0
Disabled
MR0S
1
Enabled
0
Disabled
0
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
1
Enabled
0
Disabled
MR1R
Reset on MR1: the TC will be reset if MR1 matches it.
1
Enabled
0
Disabled
MR1S
0
0
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0
the TC.
1
Enabled
0
Disabled
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
1
Enabled
0
Disabled
MR2R
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0
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0
the TC.
MR1I
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value
Reset on MR2: the TC will be reset if MR2 matches it.
1
Enabled
0
Disabled
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 121. Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
bit description
Bit
Symbol
8
MR2S
9
10
11
31:12
Value Description
Reset
value
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0
the TC.
1
Enabled
0
Disabled
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
1
Enabled
0
Disabled
MR3R
Reset on MR3: the TC will be reset if MR3 matches it.
1
Enabled
0
Disabled
MR3S
0
0
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0
the TC.
1
Enabled
0
Disabled
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
13.7.7 Match Registers (TMR32B0MR0/1/2/3 and TMR32B1MR0/1/2/3)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 122. Match registers (TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and
TMR32B1MR0 to 3, addresses 0x4001 8018 to 24) bit description
Bit
Symbol
Description
Reset
value
31:0
MATCH
Timer counter match value.
0
13.7.8 Capture Control Register (TMR32B1CCR)
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Timer Counter when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Table 123. Capture Control Register (TMR32B1CCR - address 0x4001 8028) bit description
Bit
Symbol
0
CAP0RE
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Value Description
Reset
value
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
1
Enabled
0
Disabled
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 123. Capture Control Register (TMR32B1CCR - address 0x4001 8028) bit description
Bit
Symbol
1
CAP0FE
2
31:3
Value Description
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0
cause CR0 to be loaded with the contents of TC.
1
Enabled
0
Disabled
CAP0I
-
Reset
value
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
1
Enabled
0
Disabled
0
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
13.7.9 Capture Register (TMR32B1CR0 - address 0x4001 802C)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 124. Capture registers (TMR32B1CR0, addresses 0x4001 802C) bit description
Bit
Symbol
Description
Reset
value
31:0
CAP
Timer counter capture value.
0
13.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (Section 13.7.13 “Rules for single edge
controlled PWM outputs” on page 128).
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 125. External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
bit description
Bit
Symbol Value Description
0
EM0
External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0
output is connected to its pin. When a match occurs between the TC and MR0, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality
of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1
EM1
External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0
output is connected to its pin. When a match occurs between the TC and MR1, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality
of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
2
EM2
External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0
output is connected to its pin. When a match occurs between the TC and MR2, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality
of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
3
EM3
External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the
functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
5:4
EMC0
External Match Control 0. Determines the functionality of External Match 0.
00
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
11
7:6
9:8
EMC1
User manual
Toggle the corresponding External Match bit/output.
External Match Control 1. Determines the functionality of External Match 1.
00
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
EMC2
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Reset
value
External Match Control 2. Determines the functionality of External Match 2.
00
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 125. External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
bit description
Bit
Symbol Value Description
Reset
value
11:10
EMC3
00
31:12
External Match Control 3. Determines the functionality of External Match 3.
-
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 126. External match control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Function
00
Do Nothing.
01
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
10
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
11
Toggle the corresponding External Match bit/output.
13.7.11 Count Control Register (TMR32B0CTCR and TMR32B1TCR)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/(2 × PCLK).
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 127. Count Control Register (TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR
- address 0x4001 8070) bit description
Bit
Symbol
1:0
CTM
Value
Description
Reset
value
Counter/Timer Mode. This field selects which rising PCLK
00
edges can increment Timer’s Prescale Counter (PC), or clear
PC and increment Timer Counter (TC).
Timer Mode: every rising PCLK edge
3:2
CIS
31:4
-
0x0
Timer Mode: every rising PCLK edge
0x1
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
Count Input Select. When bits 1:0 in this register are not 00, 00
these bits select which CAP pin is sampled for clocking.
Note: If Counter mode is selected in the TnCTCR, the 3 bits
for that input in the Capture Control Register (TnCCR) must
be programmed as 000.
0x1 - 0x3 reserved.
0x0
CT32Bn_CAP0
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
13.7.12 PWM Control Register (TMR32B0PWMC and TMR32B1PWMC)
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three-single edge controlled PWM outputs can be selected
on the MATn[2:0] outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM outputs are cleared.
Table 128. PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC 0x4001 8074) bit description
UM10429
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Bit
Symbol
Description
Reset value
0
PWM enable
When one, PWM mode is enabled for CT32Bn_MAT0.
When zero, CT32Bn_MAT0 is controlled by EM0.
0
1
PWM enable
When one, PWM mode is enabled for CT32Bn_MAT1.
When zero, CT32Bn_MAT1 is controlled by EM1.
0
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
Table 128. PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC 0x4001 8074) bit description
Bit
Symbol
Description
Reset value
2
PWM enable
When one, PWM mode is enabled for CT32Bn_MAT2.
When zero, CT32Bn_MAT2 is controlled by EM2.
0
3
PWM enable
When one, PWM mode is enabled for CT32Bn_MAT3.
When zero, CT32Bn_MAT3 is controlled by EM3.
0
Note: It is recommended to use match channel 3 to set
the PWM cycle.
31:4
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
13.7.13 Rules for single edge controlled PWM outputs
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
(timer is set to zero) unless their match value is equal to zero.
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
3. If a match value larger than the PWM cycle length is written to the match register, and
the PWM signal is HIGH already, then the PWM signal will be cleared with the start of
the next PWM cycle.
4. If a match register contains the same value as the timer reset value (the PWM cycle
length), then the PWM output will be reset to LOW on the next clock tick after the
timer reaches the match value. Therefore, the PWM output will always consist of a
one clock tick wide positive pulse with a period determined by the PWM cycle length
(i.e. the timer reload value).
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
timer goes back to zero and will stay HIGH continuously.
Note: When the match outputs are selected to function as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
PWM2/MAT2
MR2 = 100
PWM1/MAT1
MR1 = 41
PWM0/MAT0
MR0 = 65
0
41
65
100
(counter is reset)
Fig 25. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
MAT3:0 enabled as PWM outputs by the PWCON register.
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
13.8 Example timer operation
Figure 26 shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 27 shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
PCLK
prescale
counter
2
timer
counter
4
0
1
2
0
1
5
2
0
6
1
0
2
0
1
1
timer counter
reset
interrupt
Fig 26. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale counter
timer counter
TCR[0]
(counter enable)
2
4
0
1
5
1
2
0
6
0
interrupt
Fig 27. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
13.9 Architecture
The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in
Figure 28.
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Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
MATCH CONTROL REGISTER
EXTERNAL MATCH REGISTER
INTERRUPT REGISTER
CONTROL
=
MAT[3:0]
INTERRUPT
=
CAP0
=
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]
=
CAPTURE CONTROL REGISTER
CSN
TIMER COUNTER
CE
CAPTURE REGISTER 0
TCI
PCLK
PRESCALE COUNTER
reset
enable
TIMER CONTROL REGISTER
MAXVAL
PRESCALE REGISTER
Fig 28. 32-bit counter/timer block diagram
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Chapter 14: LPC1102 WatchDog Timer (WDT)
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14.1 How to read this chapter
The WDT block is implemented on the LPC1102.
14.2 Basic configuration
The WDT is configured using the following registers:
1. Pins: The WDT uses no external pins.
2. Power: In the SYSAHBCLKCTRL register, set bit 15 (Table 19).
3. Peripheral clock: Select the watchdog clock source Table 23) and enable the WDT
peripheral clock by writing to the WDTCLKDIV register (Table 25).
Remark: The frequency of the watchdog oscillator is undefined after reset. The
watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL
register (see Table 11) before using the watchdog oscillator as clock source for the
WDT.
14.3 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 24 bit timer with internal pre-scaler.
Selectable time period from (TWDCLK × 256 × 4) to (TWDCLK × 224 × 4) in multiples of
TWDCLK × 4.
• The Watchdog clock (WDCLK) source is selected in the syscon block from the
Internal RC oscillator (IRC), the main clock, or the Watchdog oscillator, see Table 23.
This gives a wide range of potential timing choices for Watchdog operation under
different power reduction conditions. For increased reliability, it also provides the
ability to run the Watchdog timer from an entirely internal source that is not dependent
on an external crystal and its associated components and wiring.
14.4 Applications
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
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Chapter 14: LPC1102 WatchDog Timer (WDT)
14.5 Description
The Watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (TWDCLK × 256 × 4)
and the maximum Watchdog interval is (TWDCLK × 224 × 4) in multiples of (TWDCLK × 4).
The Watchdog should be used in the following manner:
1. Set the Watchdog timer constant reload value in WDTC register.
2. Setup the Watchdog timer operating mode in WDMOD register.
3. Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
4. The Watchdog should be fed again before the Watchdog counter underflows to
prevent reset/interrupt.
When the Watchdog is in the reset mode and the counter underflows, the CPU will be
reset, loading the stack pointer and program counter from the vector table as in the case
of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if
the Watchdog has caused the reset condition. The WDTOF flag must be cleared by
software.
14.6 WDT clocking
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see Figure 3).
The WDCLK is used for the watchdog timer counting and is derived from the wdt_clk in
Figure 3. Several clocks can be used as a clock source for wdt_clk clock: the IRC, the
watchdog oscillator, and the main clock. The clock source is selected in the syscon block
(see Table 23). The WDCLK has its own clock divider (Section 3.5.20), which can also
disable this clock.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
The watchdog oscillator can be powered down in the PDRUNCFG register
(Section 3.5.34) if it is not used. The clock to the watchdog register block (PCLK) can be
disabled in the SYSAHBCLKCTRL register (Table 19) for power savings.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register (see
Table 11) before using the watchdog oscillator for the WDT.
14.7 Register description
The Watchdog contains four registers as shown in Table 129 below.
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Chapter 14: LPC1102 WatchDog Timer (WDT)
Table 129. Register overview: Watchdog timer (base address 0x4000 4000)
Name
Access Address Description
offset
Reset
Value[1]
WDMOD
R/W
0x000
Watchdog mode register. This register contains the
basic mode and status of the Watchdog Timer.
0
WDTC
R/W
0x004
Watchdog timer constant register. This register
determines the time-out value.
0xFF
WDFEED
WO
0x008
Watchdog feed sequence register. Writing 0xAA
followed by 0x55 to this register reloads the
Watchdog timer with the value contained in WDTC.
NA
WDTV
RO
0x00C
Watchdog timer value register. This register reads
out the current value of the Watchdog timer.
0xFF
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
14.7.1 Watchdog Mode register (WDMOD - 0x4000 0000)
The WDMOD register controls the operation of the Watchdog through the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Table 130. Watchdog Mode register (WDMOD - address 0x4000 4000) bit description
Bit
Symbol
Description
Reset Value
0
WDEN
WDEN Watchdog enable bit (Set Only). When 1, the
watchdog timer is running.
0
1
WDRESET WDRESET Watchdog reset enable bit (Set Only). When 1,
a watchdog time-out will cause a chip reset.
0
2
WDTOF
WDTOF Watchdog time-out flag. Set when the watchdog
timer times out, cleared by software.
0 (Only after
POR and BOD
reset)
3
WDINT
WDINT Watchdog interrupt flag (Read Only, not clearable
by software).
0
7:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
31:8
-
reserved
-
Once the WDEN and/or WDRESET bits are set, they can not be cleared by software. Both
flags are cleared by a reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is
cleared by software or a POR or Brown-Out-Detect reset.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the NVIC or the watchdog interrupt request will be generated indefinitely. The
intent of the watchdog interrupt is to allow debugging watchdog activity without resetting
the device when the watchdog overflows.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and if a watchdog
interrupt occurs in Sleep mode, it will wake up the device.
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Chapter 14: LPC1102 WatchDog Timer (WDT)
Table 131. Watchdog operating modes selection
WDEN
WDRESET
Mode of Operation
0
X (0 or 1)
Debug/Operate without the Watchdog running.
1
0
Watchdog interrupt mode: debug with the Watchdog interrupt but no
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will set the
WDINT flag and the Watchdog interrupt request will be generated.
Remark: In interrupt mode, check the WDINT flag. If this flag is set,
the interrupt is true and can be serviced by the interrupt routine. If this
flag is not set, the interrupt should be ignored.
1
1
Watchdog reset mode: operate with the Watchdog interrupt and
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will reset
the microcontroller. Although the Watchdog interrupt is also enabled in
this case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.
14.7.2 Watchdog Timer Constant register (WDTC - 0x4000 4004)
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is TWDCLK × 256 × 4.
Table 132. Watchdog Constant register (WDTC - address 0x4000 4004) bit description
Bit
Symbol
Description
Reset Value
23:0
Count
Watchdog time-out interval.
0x0000 00FF
31:25
-
Reserved
-
14.7.3 Watchdog Feed register (WDFEED - 0x4000 4008)
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
Table 133. Watchdog Feed register (WDFEED - address 0x4000 4008) bit description
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Bit
Symbol
Description
Reset Value
7:0
Feed
Feed value should be 0xAA followed by 0x55.
NA
31:8
-
Reserved
-
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Chapter 14: LPC1102 WatchDog Timer (WDT)
14.7.4 Watchdog Timer Value register (WDTV - 0x4000 400C)
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 24-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
Table 134. Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description
Bit
Symbol
Description
Reset Value
23:0
Count
Counter timer value.
0x0000 00FF
31:24
-
Reserved
-
14.8 Block diagram
The block diagram of the Watchdog is shown below in the Figure 29. The synchronization
logic (PCLK/WDCLK) is not shown in the block diagram.
feed sequence
WDTC
feed ok
WDFEED
feed error
÷4
wdt_clk
24-BIT DOWN COUNTER
underflow
enable
count
SHADOW BIT
WMOD register
WDINT
WDTOF WDRESET
WDEN
reset
interrupt
Fig 29. Watchdog block diagram
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Chapter 15: LPC1102 System tick timer
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15.1 How to read this chapter
The system tick timer (SysTick timer) is part of the ARM Cortex-M0 core.
15.2 Basic configuration
The system tick timer is configured using the following registers:
1. Pins: The system tick timer uses no external pins.
2. Power: The system tick timer is enabled through the SysTick control register
(Section 19.5.4.1). The system tick timer clock is fixed to half the frequency of the
system clock.
15.3 Features
• Simple 24-bit timer.
• Uses dedicated exception vector.
• Clocked internally by a dedicated system tick timer clock. The system tick timer clock
is fixed to half the frequency of the system clock.
15.4 Description
The SysTick timer is an integral part of the Cortex-M0. The SysTick timer is intended to
generate a fixed 10 millisecond interrupt for use by an operating system or other system
management software.
Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by
providing a standard timer that is available on Cortex-M0 based devices. The SysTick
timer can be used for:
• An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and
invokes a SysTick routine.
• A high-speed alarm timer using the core clock.
• A simple counter. Software can use this to measure time to completion and time used.
• An internal clock source control based on missing/meeting durations. The
COUNTFLAG bit-field in the control and status register can be used to determine if an
action completed within a set duration, as part of a dynamic clock management
control loop.
Refer to the Cortex-M0 User Guide for details.
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Chapter 15: LPC1102 System tick timer
15.5 Operation
The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt.
The intent is to provide a fixed 10 millisecond time interval between interrupts. The
SysTick timer is clocked from the CPU clock. In order to generate recurring interrupts at a
specific interval, the SYST_RVR register must be initialized with the correct value for the
desired interval. A default value (<tbd>) is provided in the SYST_CALIB register and may
be changed by software. The default value gives a 10 millisecond interrupt rate if the CPU
clock is set to <tbd>.
The block diagram of the SysTick timer is shown below in the Figure 30.
SYST_CALIB
SYST_RVR
load data
SYST_CVR
24-bit down counter
clock
system clock/2
load
private
peripheral
bus
under- count
flow
enable
ENABLE
SYST_CSR
COUNTFLAG
TICKINT
System Tick
interrupt
Fig 30. System tick timer block diagram
15.6 Register description
The systick timer registers are located on the ARM Cortex-M0 private peripheral bus (see
Figure 38), and are part of the ARM Cortex-M0 core peripherals. For details, see
Section 19.5.4.
Table 135. Register overview: SysTick timer (base address 0xE000 E000)
Name
Access
Address
offset
Description
Reset value[1]
SYST_CSR
R/W
0x010
System Timer Control and status register
0x000 0000
SYST_RVR
R/W
0x014
System Timer Reload value register
0
SYST_CVR
R/W
0x018
System Timer Current value register
0
SYST_CAL
R/W
0x01C
System Timer Calibration value register
0x4
[1]
Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
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Chapter 15: LPC1102 System tick timer
15.6.1 System Timer Control and status register
The SYST_CSR register contains control information for the SysTick timer and provides a
status flag. This register is part of the ARM Cortex-M0 core system timer register block.
For a bit description of this register, see Section 19.5.4 “System timer, SysTick”.
15.6.2 System Timer Reload value register
The SYST_RVR register is set to the value that will be loaded into the SysTick timer
whenever it counts down to zero. This register is loaded by software as part of timer
initialization. The SYST_CALIB register may be read and used as the value for
SYST_RVR register if the CPU is running at the frequency intended for use with the
SYST_CALIB value.
Table 136. System Timer Reload value register (SYST_RVR - 0xE000 E014) bit description
Bit
Symbol
Description
Reset
value
23:0
RELOAD
This is the value that is loaded into the System Tick counter when it 0
counts down to 0.
31:24
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
15.6.3 System Timer Current value register
The SYST_CVR register returns the current count from the System Tick counter when it is
read by software.
Table 137. System Timer Current value register (SYST_CVR - 0xE000 E018) bit description
Bit
Symbol
Description
Reset
value
23:0
CURRENT Reading this register returns the current value of the System Tick
counter. Writing any value clears the System Tick counter and the
COUNTFLAG bit in STCTRL.
31:24
-
0
Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
15.6.4 System Timer Calibration value register (SYST_CALIB - 0xE000 E01C)
The value of the SYST_CALIB register is driven by the value of the SYSTCKCAL register
in the system configuration block (see Table 27).
Table 138. System Timer Calibration value register (SYST_CALIB - 0xE000 E01C) bit
description
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Bit
Symbol
23:0
Value
Description
Reset
value
TENMS
<tbd>
0x4
29:24
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
30
SKEW
<tbd>
0
31
NOREF
<tbd>
0
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Chapter 15: LPC1102 System tick timer
15.7 Example timer calculations
To use the system tick timer, do the following:
1. Program the SYST_RVR register with the reload value RELOAD to obtain the desired
time interval.
2. Clear the SYST_CVR register by writing to it. This ensures that the timer will count
from the SYST_RVR value rather than an arbitrary value when the timer is enabled.
3. Program the SYST_SCR register with the value 0x7 which enables the SysTick timer
and the SysTick timer interrupt.
The following example illustrates selecting the SysTick timer reload value to obtain a
10 ms time interval with the LPC1102 system clock set to 50 MHz.
Example (system clock = 50 MHz)
The system tick clock = system clock⁄2 = 25 MHz.
RELOAD = (system tick clock frequency × 10 ms) −1 = (25 MHz × 10 ms) −1 = 250000 −1
= 249999 = 0x0003D08F
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
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16.1 How to read this chapter
The ADC is uses channels 0 to 4 on the LPC1102. Channels 5 to 6 are not pinned out.
16.2 Basic configuration
The ADC is configured using the following registers:
1. Pins: The ADC pin functions are configured in the IOCONFIG register block
(Section 7.4.1).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 13 (Table 19).
Power to the ADC at run-time is controlled through the PDRUNCFG register
(Table 40).
16.3 Features
•
•
•
•
•
•
•
•
10-bit successive approximation Analog-to-Digital Converter (ADC).
Input multiplexing among 5 pins.
Power-down mode.
Measurement range 0 to 3.6 V. Do not exceed the VDD voltage level.
10-bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
16.4 Pin description
Table 139 gives a brief summary of the ADC related pins.
Table 139. ADC pin description
Pin
Type
Description
AD[7:0]
Input
Analog Inputs. The A/D converter cell can measure the voltage on any
of these input signals.
Remark: While the pins are 5 V tolerant in digital mode, the maximum
input voltage must not exceed VDD when the pins are configured as
analog inputs.
VDD
Input
VREF; Reference voltage.
The ADC function must be selected via the IOCON registers in order to get accurate
voltage readings on the monitored pin. For a pin hosting an ADC input, it is not possible to
have a have a digital function selected and yet get valid ADC readings. An inside circuit
disconnects ADC hardware from the associated pin whenever a digital function is selected
on that pin.
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
16.5 ADC clocking
Basic clocking for the A/D converters is determined by the APB clock (PCLK). A
programmable divider is included in the A/D converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
16.6 Register description
The ADC contains registers organized as shown in Table 140.
Table 140. Register overview: ADC (base address 0x4001 C000)
Name
Access Address Description
offset
Reset
Value[1]
AD0CR
R/W
0x000
A/D Control Register. The AD0CR register must be written to select the
operating mode before A/D conversion can occur.
0x0000 0000
AD0GDR
R/W
0x004
A/D Global Data Register. Contains the result of the most recent A/D
conversion.
NA
-
-
0x008
Reserved.
-
AD0INTEN R/W
0x00C
A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
0x0000 0100
AD0DR0
R/W
0x010
A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0
NA
AD0DR1
R/W
0x014
A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
NA
AD0DR2
R/W
0x018
A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
NA
AD0DR3
R/W
0x01C
A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
NA
AD0DR4
R/W
0x020
A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
NA
AD0DR5
R/W
0x024
Reserved.
NA
AD0DR6
R/W
0x028
Reserved.
NA
AD0DR7
R/W
0x02C
Reserved.
NA
AD0STAT
RO
0x030
A/D Status Register. This register contains DONE and OVERRUN flags for 0
all of the A/D channels, as well as the A/D interrupt flag.
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
16.6.1 A/D Control Register
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
Table 141. A/D Control Register (AD0CR - address 0x4001 C000) bit description
Bit
Symbol
4:0
SEL
Value Description
Reset
Value
Selects which of the AD4:0 pins is (are) to be sampled and converted. Bit 0 selects Pin
0x00
AD0, bit 1 selects pin AD1,..., and bit 4 selects pin AD4.
In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one
of these bits should be 1.
In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any
or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL =
0x01).
7:5
-
Reserved
15:8
CLKDIV
The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which 0
should be less than or equal to 4.5 MHz. Typically, software should program the smallest
value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such
as a high-impedance analog source) a slower clock may be desirable.
16
BURST
Burst mode
0
Remark: If BURST is set to 1 , the ADGINTEN bit in the AD0INTEN register (Table 144)
must be set to 0.
0
Software-controlled mode: Conversions are software-controlled and require 11 clocks.
1
Hardware scan mode: The AD converter does repeated conversions at the rate selected
by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL
field. The first conversion after the start corresponds to the least-significant bit set to 1 in
the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated
conversions can be terminated by clearing this bit, but the conversion in progress when
this bit is cleared will be completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
19:17 CLKS
23:20 -
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This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits).
0x0
11 clocks / 10 bits
0x1
10 clocks / 9 bits
0x2
9 clocks / 8 bits
0x3
8 clocks / 7 bits
0x4
7 clocks / 6 bits
0x5
6 clocks / 5 bits
0x6
5 clocks / 4 bits
0x7
4 clocks / 3 bits
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
Table 141. A/D Control Register (AD0CR - address 0x4001 C000) bit description
Bit
Symbol
Value Description
26:24 START
27
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started.
0x0
No start (this value should be used when clearing PDN to 0).
0x1
Start conversion now.
0x2
Reserved
0x3
Reserved
0x4
Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1].
0x5
Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1].
0x6
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1].
0x7
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
EDGE
0
[1]
0
This bit is significant only when the START field contains 010-111. In these cases:
1
31:28 -
Reset
Value
0
Start conversion on a falling edge on the selected CAP/MAT signal.
Start conversion on a rising edge on the selected CAP/MAT signal.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Note that this does not require that the timer match function appear on a device pin.
16.6.2 A/D Global Data Register
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
Table 142. A/D Global Data Register (AD0GDR - address 0x4001 C004) bit description
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Bit
Symbol
Description
Reset
Value
5:0
Unused
These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution A/D converters.
0
15:6
X
V_VREF When DONE is 1, this field contains a binary fraction representing the
voltage on the ADn pin selected by the SEL field, divided by the voltage
on the VDD pin. Zero in the field indicates that the voltage on the ADn
pin was less than, equal to, or close to that on VSS, while 0x3FF
indicates that the voltage on ADn was close to, equal to, or greater than
that on VREF.
23:16 Unused
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
26:24 CHN
These bits contain the channel from which the result bits V_VREF were X
converted.
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
Table 142. A/D Global Data Register (AD0GDR - address 0x4001 C004) bit description
Bit
Symbol
Description
Reset
Value
29:27 Unused
These bits always read as zeroes. They could be used for expansion of 0
the CHN field in future compatible A/D converters that can convert more
channels.
30
OVERR
UN
This bit is 1 in burst mode if the results of one or more conversions was 0
(were) lost and overwritten before the conversion that produced the
result in the V_VREF bits.
31
DONE
This bit is set to 1 when an A/D conversion completes. It is cleared
0
when this register is read and when the ADCR is written. If the ADCR is
written while a conversion is still in progress, this bit is set and a new
conversion is started.
16.6.3 A/D Status Register
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Table 143. A/D Status Register (AD0STAT - address 0x4001 C030) bit description
Bit
Symbol
Description
Reset
Value
4:0
Done4:0
These bits mirror the DONE status flags that appear in the result
register for each A/D channel.
0
7:5
-
Reserved
-
12:8
Overrun7:0 These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
0
15:13 -
Reserved
-
16
This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.
0
Unused, always 0.
0
ADINT
31:17 Unused
16.6.4 A/D Interrupt Enable Register
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
Table 144. A/D Interrupt Enable Register (AD0INTEN - address 0x4001 C00C) bit description
Bit
Symbol
Description
Reset
Value
4:0
ADINTEN 4:0
These bits allow control over which A/D channels generate
0x00
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
7:5
-
Reserved.
-
8
ADGINTEN
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 4:0 will generate interrupts.
1
Remark: This bit must be set to 0 in burst mode (BURST = 1 in the
AD0CR register).
31:9 Unused
Unused, always 0.
0
16.6.5 A/D Data Registers
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 145. A/D Data Registers (AD0DR0 to AD0DR4 - addresses 0x4001 C010 to
0x4001 C020) bit description
Bit
Symbol
Description
Reset
Value
5:0
Unused
Unused, always 0.
0
These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution ADCs.
15:6
V_VREF
29:16 Unused
When DONE is 1, this field contains a binary fraction representing the NA
voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in
the field indicates that the voltage on the ADn pin was less than, equal
to, or close to that on VREF, while 0x3FF indicates that the voltage on
AD input was close to, equal to, or greater than that on VREF.
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
0
30
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits.This bit is cleared by reading this
register.
0
31
DONE
0
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
16.7 Operation
16.7.1 Hardware-triggered conversion
If the BURST bit in the ADCR0 is 0 and the START field contains 010-111, the A/D
converter will start a conversion when a transition occurs on a selected pin or timer match
signal.
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
16.7.2 Interrupts
An interrupt is requested to the interrupt controller when the ADINT bit in the ADSTAT
register is 1. The ADINT bit is one when any of the DONE bits of A/D channels that are
enabled for interrupts (via the ADINTEN register) are one. Software can use the Interrupt
Enable bit in the interrupt controller that corresponds to the ADC to control whether this
results in an interrupt. The result register for an A/D channel that is generating an interrupt
must be read in order to clear the corresponding DONE flag.
16.7.3 Accuracy vs. digital receiver
While the A/D converter can be used to measure the voltage on any ADC input pin,
regardless of the pin’s setting in the IOCON block, selecting the ADC in the IOCON
registers function improves the conversion accuracy by disabling the pin’s digital receiver
(see also Section 7.3.4).
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Chapter 17: LPC1102 Flash memory programming firmware
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17.1 How to read this chapter
Table 146. LPC1102 flash configuration
Type number
Flash
ISP via UART
LPC1102
32 kB
yes
17.2 Features
• In-System Programming: The LPC1102 has no dedicated ISP entry pin. Therefore,
user code is required to invoke ISP functionality. Unprogrammed parts automatically
boot into ISP mode.
• In-Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.
• Flash access times can be configured through a register in the flash controller block.
• Erase time for one sector is 100 ms ± 5%. Programming time for one block of 256
bytes is 1 ms ± 5%.
Remark: In addition to the ISP and IAP commands, a register can be accessed in the
flash controller block to configure flash memory access times, see Section 17.8.
17.3 General description
17.3.1 Bootloader
The bootloader controls initial operation after reset and also provides the means to
accomplish programming of the flash memory via UART. This could be initial
programming of a blank device, erasure and re-programming of a previously programmed
device, or programming of the flash memory by the application program in a running
system.
The bootloader code is executed every time the part is powered on or reset. If a valid user
program is found then the execution control is transferred to it. If a valid user program is
not found, the auto-baud routine is invoked.
The loader can execute the ISP command handler or the user application code. However,
in order to enter ISP mode, the user code must provide for an ISP entry mechanism
because the LPC1102 does not have an ISP entry pin. Unprogrammed parts boot in ISP
mode by default.
17.3.2 Memory map after any reset
The boot block is 16 kB in size. The boot block is located in the memory region starting
from the address 0x1FFF 0000. The bootloader is designed to run from this memory area,
but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is
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Chapter 17: LPC1102 Flash memory programming firmware
described later in this chapter. The interrupt vectors residing in the boot block of the
on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the
boot block are also visible in the memory region starting from the address 0x0000 0000.
17.3.3 Criterion for Valid User Code
Criterion for valid user code: The reserved Cortex-M0 exception vector location 7 (offset
0x 0000 001C in the vector table) should contain the 2’s complement of the check-sum of
table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0. The
bootloader code checksums the first 8 locations in sector 0 of the flash. If the result is 0,
then execution control is transferred to the user code.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port
0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronization character in
terms of its own frequency and programs the baud rate generator of the serial port. It also
sends an ASCII string ("Synchronized<CR><LF>") to the host. In response to this host
should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at
the received characters to verify synchronization. If synchronization is verified then
"OK<CR><LF>" string is sent to the host. The host should respond by sending the crystal
frequency (in kHz) at which the part is running. For example, if the part is running at 10
MHz , the response from the host should be "10000<CR><LF>". "OK<CR><LF>" string is
sent to the host after receiving the crystal frequency. If synchronization is not verified then
the auto-baud routine waits again for a synchronization character. For auto-baud to work
correctly in case of user invoked ISP, the CCLK frequency should be greater than or equal
to 10 MHz.
Once the crystal frequency is received the part is initialized and the ISP command handler
is invoked. For safety reasons an "Unlock" command is required before executing the
commands resulting in flash erase/write operations and the "Go" command. The rest of
the commands can be executed without the unlock command. The Unlock command is
required to be executed once per ISP session. The Unlock command is explained in
Section 17.5 “UART ISP commands” on page 153.
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Chapter 17: LPC1102 Flash memory programming firmware
17.3.4 Boot process flowchart
RESET
INITIALIZE
CRP1/2/3
ENABLED?
no
ENABLE DEBUG
yes
WATCHDOG
FLAG SET?
A
yes
no
USER CODE
VALID?
CRP3
ENABLED?
yes
no
no
yes
EXECUTE INTERNAL
USER CODE
USER CODE
VALID?
no
no
boot from
UART
RUN AUTO-BAUD
yes
A
no
AUTO-BAUD
SUCCESSFUL?
yes
RECEIVE CRYSTAL FREQUENCY
RUN UART ISP COMMAND HANDLER
(1) For details on handling the crystal frequency, see Section 17.6.8 “Reinvoke ISP (IAP)” on page 166
Fig 31. Boot process flowchart
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17.3.5 Sector numbers
Some IAP and ISP commands operate on sectors and specify sector numbers. The
following table shows the correspondence between sector numbers and memory
addresses for LPC1102 devices.
Table 147. Flash sector configuration
Sector
number
Sector size Address range
LPC1102
32 kB flash
0
4 kB
0x0000 0000 - 0x0000 0FFF
yes
1
4 kB
0x0000 1000 - 0x0000 1FFF
yes
2
4 kB
0x0000 2000 - 0x0000 2FFF
yes
3
4 kB
0x0000 3000 - 0x0000 3FFF
yes
4
4 kB
0x0000 4000 - 0x0000 4FFF
yes
5
4 kB
0x0000 5000 - 0x0000 5FFF
yes
6
4 kB
0x0000 6000 - 0x0000 6FFF
yes
7
4 kB
0x0000 7000 - 0x0000 7FFF
yes
17.3.6 Flash content protection mechanism
The LPC1102 is equipped with the Error Correction Code (ECC) capable Flash memory.
The purpose of an error correction module is twofold. Firstly, it decodes data words read
from the memory into output data words. Secondly, it encodes data words to be written to
the memory. The error correction capability consists of single bit error correction with
Hamming code.
The operation of ECC is transparent to the running application. The ECC content itself is
stored in a flash memory not accessible by user’s code to either read from it or write into it
on its own. A byte of ECC corresponds to every consecutive 128 bits of the user
accessible Flash. Consequently, Flash bytes from 0x0000 0000 to 0x0000 000F are
protected by the first ECC byte, Flash bytes from 0x0000 0010 to 0x0000 001F are
protected by the second ECC byte, etc.
Whenever the CPU requests a read from user’s Flash, both 128 bits of raw data
containing the specified memory location and the matching ECC byte are evaluated. If the
ECC mechanism detects a single error in the fetched data, a correction will be applied
before data are provided to the CPU. When a write request into the user’s Flash is made,
write of user specified content is accompanied by a matching ECC value calculated and
stored in the ECC memory.
When a sector of Flash memory is erased, the corresponding ECC bytes are also erased.
Once an ECC byte is written, it can not be updated unless it is erased first. Therefore, for
the implemented ECC mechanism to perform properly, data must be written into the flash
memory in groups of 16 bytes (or multiples of 16), aligned as described above.
17.3.7 Code Read Protection (CRP)
Code Read Protection is a mechanism that allows the user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x0000 02FC. IAP commands are not affected by the code read protection.
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Important: any CRP change becomes effective only after the device has gone
through a power cycle.
Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all
three CRP levels, the user’s application code must provide a flash update mechanism
which reinvokes ISP by defining a user-selected PIO pin for ISP entry.
Table 148. Code Read Protection options
Name
Pattern
Description
programmed in
0x0000 02FC
CRP1
0x12345678
Access to chip via the SWD pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
•
Write to RAM command cannot access RAM below 0x1000
0300.
•
•
Copy RAM to flash command can not write to Sector 0.
•
•
Compare command is disabled.
Erase command can erase Sector 0 only when all sectors are
selected for erase.
Read Memory command is disabled.
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. Since compare command
is disabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the flash.
CRP2
0x87654321
Access to chip via the SWD pins is disabled. The following ISP
commands are disabled:
•
•
•
•
•
Read Memory
Write to RAM
Go
Copy RAM to flash
Compare
When CRP2 is enabled the ISP erase command only allows erasure
of all user sectors.
CRP3
0x43218765
Access to chip via the SWD pins is disabled. No ISP access.
Table 149. Code Read Protection hardware/software interaction
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CRP option
User Code
Valid
SWD enabled LPC1102 enters
ISP mode
partial flash
update in ISP
mode
None
No
Yes
Yes
Yes
None
Yes
Yes
No
NA
CRP1
Yes
No
No
NA
CRP2
Yes
No
No
NA
CRP3
Yes
No
No
NA
CRP1
No
No
Yes
Yes
CRP2
No
No
Yes
No
CRP3
No
No
Yes
No
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Table 150. ISP commands allowed for different CRP levels
ISP command
CRP1
CRP2
CRP3
Unlock
yes
yes
n/a
Set Baud Rate
yes
yes
n/a
Echo
yes
yes
n/a
Write to RAM
yes; above 0x1000 0300
only
no
n/a
Read Memory
no
no
n/a
Prepare sector(s) for
write operation
yes
yes
n/a
Copy RAM to flash
yes; not to sector 0
no
n/a
Go
no
no
n/a
Erase sector(s)
yes; sector 0 can only be
erased when all sectors are
erased.
yes; all sectors
only
n/a
Blank check sector(s)
no
no
n/a
Read Part ID
yes
yes
n/a
Read Boot code version yes
yes
n/a
Compare
no
no
n/a
ReadUID
yes
yes
n/a
In case a CRP mode is enabled and access to the chip is allowed via the ISP, an
unsupported or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
17.4 UART Communication protocol
All UART ISP commands should be sent as single ASCII strings. Strings should be
terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra
<CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF>
terminated ASCII strings. Data is sent and received in UU-encoded format.
17.4.1 UART ISP command format
"Command Parameter_0 Parameter_1 ... Parameter_n<CR><LF>" "Data" (Data only for
Write commands).
17.4.2 UART ISP response format
"Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> ...
Response_n<CR><LF>" "Data" (Data only for Read commands).
17.4.3 UART ISP data format
The data stream is in UU-encoded format. The UU-encode algorithm converts 3 bytes of
binary data in to 4 bytes of printable ASCII character set. It is more efficient than Hex
format which converts 1 byte of binary data in to 2 bytes of ASCII hex. The sender should
send the check-sum after transmitting 20 UU-encoded lines. The length of any
UU-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes.
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The receiver should compare it with the check-sum of the received bytes. If the
check-sum matches then the receiver should respond with "OK<CR><LF>" to continue
further transmission. If the check-sum does not match the receiver should respond with
"RESEND<CR><LF>". In response the sender should retransmit the bytes.
17.4.4 UART ISP flow control
A software XON/XOFF flow control scheme is used to prevent data loss due to buffer
overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to
stop the flow of data. Data flow is resumed by sending the ASCII control character DC1
(start). The host should also support the same flow control scheme.
17.4.5 UART SP command abort
Commands can be aborted by sending the ASCII control character "ESC". This feature is
not documented as a command under "ISP Commands" section. Once the escape code is
received the ISP command handler waits for a new command.
17.4.6 Interrupts during UART ISP
The boot block interrupt vectors located in the boot block of the flash are active after any
reset.
17.4.7 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.
17.4.8 RAM used by ISP command handler
ISP commands use on-chip RAM from 0x1000 017C to 0x1000 025B. The user could use
this area, but the contents may be lost upon reset. Flash programming commands use the
top 32 bytes of on-chip RAM. The stack is located at (RAM top − 32). The maximum stack
usage is 256 bytes and it grows downwards.
17.4.9 RAM used by IAP command handler
Flash programming commands use the top 32 bytes of on-chip RAM. The maximum stack
usage in the user allocated stack space is 128 bytes and it grows downwards.
17.5 UART ISP commands
The following commands are accepted by the ISP command handler. Detailed status
codes are supported for each command. The command handler sends the return code
INVALID_COMMAND when an undefined command is received. Commands and return
codes are in ASCII format.
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CMD_SUCCESS is sent by ISP command handler only when received ISP command has
been completely executed and the new ISP command can be given by the host.
Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"
commands.
Table 151. UART ISP command summary
ISP Command
Usage
Described in
Unlock
U <Unlock Code>
Table 152
Set Baud Rate
B <Baud Rate> <stop bit>
Table 153
Echo
A <setting>
Table 154
Write to RAM
W <start address> <number of bytes>
Table 155
Read Memory
R <address> <number of bytes>
Table 156
Prepare sector(s) for
write operation
P <start sector number> <end sector number>
Table 157
Copy RAM to flash
C <Flash address> <RAM address> <number of bytes> Table 158
Go
G <address> <Mode>
Table 159
Erase sector(s)
E <start sector number> <end sector number>
Table 160
Blank check sector(s)
I <start sector number> <end sector number>
Table 161
Read Part ID
J
Table 162
Read Boot code version
K
Table 164
Compare
M <address1> <address2> <number of bytes>
Table 165
ReadUID
N
Table 166
17.5.1 Unlock <Unlock code> (UART ISP)
Table 152. UART ISP Unlock command
Command
U
Input
Unlock code: 2313010
Return Code
CMD_SUCCESS |
INVALID_CODE |
PARAM_ERROR
Description
This command is used to unlock Flash Write, Erase, and Go commands.
Example
"U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands.
17.5.2 Set Baud Rate <Baud Rate> <stop bit> (UART ISP)
Table 153. UART ISP Set Baud Rate command
Command
B
Input
Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200
Stop bit: 1 | 2
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Table 153. UART ISP Set Baud Rate command
Command
B
Return Code
CMD_SUCCESS |
INVALID_BAUD_RATE |
INVALID_STOP_BIT |
PARAM_ERROR
Description
This command is used to change the baud rate. The new baud rate is effective
after the command handler sends the CMD_SUCCESS return code.
Example
"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.
17.5.3 Echo <setting> (UART ISP)
Table 154. UART ISP Echo command
Command
A
Input
Setting: ON = 1 | OFF = 0
Return Code
CMD_SUCCESS |
PARAM_ERROR
Description
The default setting for echo command is ON. When ON the ISP command handler
sends the received serial data back to the host.
Example
"A 0<CR><LF>" turns echo off.
17.5.4 Write to RAM <start address> <number of bytes> (UART ISP)
The host should send the data only after receiving the CMD_SUCCESS return code. The
host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is
generated by adding raw data (before UU-encoding) bytes and is reset after transmitting
20 UU-encoded lines. The length of any UU-encoded line should not exceed
61 characters (bytes) i.e. it can hold 45 data bytes. When the data fits in less then
20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.
The ISP command handler compares it with the check-sum of the received bytes. If the
check-sum matches, the ISP command handler responds with "OK<CR><LF>" to
continue further transmission. If the check-sum does not match, the ISP command
handler responds with "RESEND<CR><LF>". In response the host should retransmit the
bytes.
Table 155. UART ISP Write to RAM command
Command
W
Input
Start Address: RAM address where data bytes are to be written. This address
should be a word boundary.
Number of Bytes: Number of bytes to be written. Count should be a multiple of 4
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Table 155. UART ISP Write to RAM command
Command
W
Return Code
CMD_SUCCESS |
ADDR_ERROR (Address not on word boundary) |
ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not multiple of 4) |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
Description
This command is used to download data to RAM. Data should be in UU-encoded
format. This command is blocked when code read protection is enabled.
Example
"W 268436224 4<CR><LF>" writes 4 bytes of data to address 0x1000 0300.
17.5.5 Read Memory <address> <no. of bytes> (UART ISP)
The data stream is followed by the command success return code. The check-sum is sent
after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data
(before UU-encoding) bytes and is reset after transmitting 20 UU-encoded lines. The
length of any UU-encoded line should not exceed 61 characters (bytes) i.e. it can hold
45 data bytes. When the data fits in less then 20 UU-encoded lines then the check-sum is
of actual number of bytes sent. The host should compare it with the checksum of the
received bytes. If the check-sum matches then the host should respond with
"OK<CR><LF>" to continue further transmission. If the check-sum does not match then
the host should respond with "RESEND<CR><LF>". In response the ISP command
handler sends the data again.
Table 156. UART ISP Read Memory command
Command
R
Input
Start Address: Address from where data bytes are to be read. This address
should be a word boundary.
Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.
Return Code
CMD_SUCCESS followed by <actual data (UU-encoded)> |
ADDR_ERROR (Address not on word boundary) |
ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not a multiple of 4) |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
Description
This command is used to read data from RAM or flash memory. This command is
blocked when code read protection is enabled.
Example
"R 268435456 4<CR><LF>" reads 4 bytes of data from address 0x1000 0000.
17.5.6 Prepare sector(s) for write operation <start sector number> <end
sector number> (UART ISP)
This command makes flash write/erase operation a two step process.
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Table 157. UART ISP Prepare sector(s) for write operation command
Command
P
Input
Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.
Return Code
CMD_SUCCESS |
BUSY |
INVALID_SECTOR |
PARAM_ERROR
Description
This command must be executed before executing "Copy RAM to flash" or "Erase
Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase
Sector(s)" command causes relevant sectors to be protected again. The boot
block can not be prepared by this command. To prepare a single sector use the
same "Start" and "End" sector numbers.
Example
"P 0 0<CR><LF>" prepares the flash sector 0.
17.5.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes>
(UART ISP)
When writing to the flash, the following limitations apply:
1. The smallest amount of data that can be written to flash by the copy RAM to flash
command is 256 byte (equal to one page).
2. One page consists of 16 flash words (lines), and the smallest amount that can be
modified per flash write is one flash word (one line). This limitation follows from the
application of ECC to the flash write operation, see Section 17.3.6.
3. To avoid write disturbance (a mechanism intrinsic to flash memories), an erase should
be performed after following 16 consecutive writes inside the same page. Note that
the erase operation then erases the entire sector.
Remark: Once a page has been written to 16 times, it is still possible to write to other
pages within the same sector without performing a sector erase (assuming that those
pages have been erased previously).
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Table 158. UART ISP Copy command
Command
C
Input
Flash Address(DST): Destination flash address where data bytes are to be
written. The destination address should be a 256 byte boundary.
RAM Address(SRC): Source RAM address from where data bytes are to be read.
Number of Bytes: Number of bytes to be written. Should be 256 | 512 | 1024 |
4096.
Return Code CMD_SUCCESS |
SRC_ADDR_ERROR (Address not on word boundary) |
DST_ADDR_ERROR (Address not on correct boundary) |
SRC_ADDR_NOT_MAPPED |
DST_ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |
SECTOR_NOT_PREPARED_FOR WRITE_OPERATION |
BUSY |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
Description
This command is used to program the flash memory. The "Prepare Sector(s) for
Write Operation" command should precede this command. The affected sectors are
automatically protected again once the copy command is successfully executed.
The boot block cannot be written by this command. This command is blocked when
code read protection is enabled.
Example
"C 0 268467504 512<CR><LF>" copies 512 bytes from the RAM address
0x1000 0800 to the flash address 0.
17.5.8 Go <address> <mode> (UART ISP)
Table 159. UART ISP Go command
Command
G
Input
Address: Flash or RAM address from which the code execution is to be started.
This address should be on a word boundary.
Mode: T (Execute program in Thumb Mode) | A (Execute program in ARM mode).
Return Code CMD_SUCCESS |
ADDR_ERROR |
ADDR_NOT_MAPPED |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
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Description
This command is used to execute a program residing in RAM or flash memory. It
may not be possible to return to the ISP command handler once this command is
successfully executed. This command is blocked when code read protection is
enabled.
Example
"G 0 A<CR><LF>" branches to address 0x0000 0000 in ARM mode.
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17.5.9 Erase sector(s) <start sector number> <end sector number> (UART
ISP)
Table 160. UART ISP Erase sector command
Command
E
Input
Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.
Return Code CMD_SUCCESS |
BUSY |
INVALID_SECTOR |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
Description
This command is used to erase one or more sector(s) of on-chip flash memory. The
boot block can not be erased using this command. This command only allows
erasure of all user sectors when the code read protection is enabled.
Example
"E 2 3<CR><LF>" erases the flash sectors 2 and 3.
17.5.10 Blank check sector(s) <sector number> <end sector number> (UART
ISP)
Table 161. UART ISP Blank check sector command
Command
I
Input
Start Sector Number:
End Sector Number: Should be greater than or equal to start sector number.
Return Code CMD_SUCCESS |
SECTOR_NOT_BLANK (followed by <Offset of the first non blank word location>
<Contents of non blank word location>) |
INVALID_SECTOR |
PARAM_ERROR
Description
This command is used to blank check one or more sectors of on-chip flash memory.
Blank check on sector 0 always fails as first 64 bytes are re-mapped to flash
boot block.
Example
"I 2 3<CR><LF>" blank checks the flash sectors 2 and 3.
17.5.11 Read Part Identification number (UART ISP)
Table 162. UART ISP Read Part Identification command
Command
J
Input
None.
Return Code CMD_SUCCESS followed by part identification number in ASCII (see Table 163).
Description
This command is used to read the part identification number.
Table 163. Part identification number
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Device
Hex coding
LPC1102
0x2500 102B
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17.5.12 Read Boot code version number (UART ISP)
Table 164. UART ISP Read Boot Code version number command
Command
K
Input
None
Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.
It is to be interpreted as <byte1(Major)>.<byte0(Minor)>.
Description
This command is used to read the boot code version number.
17.5.13 Compare <address1> <address2> <no of bytes> (UART ISP)
Table 165. UART ISP Compare command
Command
M
Input
Address1 (DST): Starting flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Address2 (SRC): Starting flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Number of Bytes: Number of bytes to be compared; should be a multiple of 4.
Return Code CMD_SUCCESS | (Source and destination data are equal)
COMPARE_ERROR | (Followed by the offset of first mismatch)
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED |
PARAM_ERROR
Description
This command is used to compare the memory contents at two locations.
Compare result may not be correct when source or destination address
contains any of the first 512 bytes starting from address zero. First 512 bytes
are re-mapped to boot ROM
Example
"M 8192 268468224 4<CR><LF>" compares 4 bytes from the RAM address
0x1000 8000 to the 4 bytes from the flash address 0x2000.
17.5.14 ReadUID (UART ISP)
Table 166. UART ISP ReadUID command
Command
N
Input
None
Return Code CMD_SUCCESS followed by four 32-bit words of E-sort test information in ASCII
format. The word sent at the lowest address is sent first.
Description
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17.5.15 UART ISP Return Codes
Table 167. UART ISP Return Codes Summary
Return Mnemonic
Code
Description
0
CMD_SUCCESS
Command is executed successfully. Sent by ISP
handler only when command given by the host has
been completely and successfully executed.
1
INVALID_COMMAND
Invalid command.
2
SRC_ADDR_ERROR
Source address is not on word boundary.
3
DST_ADDR_ERROR
Destination address is not on a correct boundary.
4
SRC_ADDR_NOT_MAPPED
Source address is not mapped in the memory map.
Count value is taken in to consideration where
applicable.
5
DST_ADDR_NOT_MAPPED
Destination address is not mapped in the memory
map. Count value is taken in to consideration
where applicable.
6
COUNT_ERROR
Byte count is not multiple of 4 or is not a permitted
value.
7
INVALID_SECTOR
Sector number is invalid or end sector number is
greater than start sector number.
8
SECTOR_NOT_BLANK
Sector is not blank.
9
SECTOR_NOT_PREPARED_FOR_ Command to prepare sector for write operation
WRITE_OPERATION
was not executed.
10
COMPARE_ERROR
Source and destination data not equal.
11
BUSY
Flash programming hardware interface is busy.
12
PARAM_ERROR
Insufficient number of parameters or invalid
parameter.
13
ADDR_ERROR
Address is not on word boundary.
14
ADDR_NOT_MAPPED
Address is not mapped in the memory map. Count
value is taken in to consideration where applicable.
15
CMD_LOCKED
Command is locked.
16
INVALID_CODE
Unlock code is invalid.
17
INVALID_BAUD_RATE
Invalid baud rate setting.
18
INVALID_STOP_BIT
Invalid stop bit setting.
19
CODE_READ_PROTECTION_
ENABLED
Code read protection enabled.
17.6 IAP commands
For in application programming the IAP routine should be called with a word pointer in
register r0 pointing to memory (RAM) containing command code and parameters. Result
of the IAP command is returned in the result table pointed to by register r1. The user can
reuse the command table for result by passing the same pointer in registers r0 and r1. The
parameter table should be big enough to hold all the results in case the number of results
are more than number of parameters. Parameter passing is illustrated in the Figure 32.
The number of parameters and results vary according to the IAP command. The
maximum number of parameters is 5, passed to the "Copy RAM to FLASH" command.
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The maximum number of results is 4, returned by the "ReadUID" command. The
command handler sends the status code INVALID_COMMAND when an undefined
command is received. The IAP routine resides at 0x1FFF 1FF0 location and it is thumb
code.
The IAP function could be called in the following way using C.
Define the IAP location entry point. Since the 0th bit of the IAP location is set there will be
a change to Thumb instruction set when the program counter branches to this address.
#define IAP_LOCATION 0x1fff1ff1
Define data structure or pointers to pass IAP command table and result table to the IAP
function:
unsigned long command[5];
unsigned long result[4];
or
unsigned long * command;
unsigned long * result;
command=(unsigned long *) 0x……
result= (unsigned long *) 0x……
Define pointer to function type, which takes two parameters and returns void. Note the IAP
returns the result with the base address of the table residing in R1.
typedef void (*IAP)(unsigned int [],unsigned int[]);
IAP iap_entry;
Setting function pointer:
iap_entry=(IAP) IAP_LOCATION;
Whenever you wish to call IAP you could use the following statement.
iap_entry (command, result);
As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC
0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers
respectively. Additional parameters are passed on the stack. Up to 4 parameters can be
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands,
which results in a flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP flash
programming is permitted in the application.
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Table 168. IAP Command Summary
IAP Command
Command Code
Described in
Prepare sector(s) for write operation
5010
Table 169
Copy RAM to flash
5110
Table 170
Erase sector(s)
5210
Table 171
Blank check sector(s)
5310
Table 172
Read Part ID
5410
Table 173
Read Boot code version
5510
Table 174
Compare
5610
Table 175
Reinvoke ISP
5710
Table 176
Read UID
5810
Table 177
COMMAND CODE
PARAMETER 1
command
parameter table
PARAMETER 2
ARM REGISTER r0
PARAMETER n
ARM REGISTER r1
STATUS CODE
RESULT 1
command
result table
RESULT 2
RESULT n
Fig 32. IAP parameter passing
17.6.1 Prepare sector(s) for write operation (IAP)
This command makes flash write/erase operation a two step process.
Table 169. IAP Prepare sector(s) for write operation command
Command
Prepare sector(s) for write operation
Input
Command code: 5010
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
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Table 169. IAP Prepare sector(s) for write operation command
Command
Prepare sector(s) for write operation
Return Code
CMD_SUCCESS |
BUSY |
INVALID_SECTOR
Result
None
Description
This command must be executed before executing "Copy RAM to flash" or "Erase
Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase
Sector(s)" command causes relevant sectors to be protected again. The boot
sector can not be prepared by this command. To prepare a single sector use the
same "Start" and "End" sector numbers.
17.6.2 Copy RAM to flash (IAP)
See Section 17.5.4 for limitations on the write-to-flash process.
Table 170. IAP Copy RAM to flash command
Command
Copy RAM to flash
Input
Command code: 5110
Param0(DST): Destination flash address where data bytes are to be written. This
address should be a 256 byte boundary.
Param1(SRC): Source RAM address from which data bytes are to be read. This
address should be a word boundary.
Param2: Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
Param3: System Clock Frequency (CCLK) in kHz.
Return Code
CMD_SUCCESS |
SRC_ADDR_ERROR (Address not a word boundary) |
DST_ADDR_ERROR (Address not on correct boundary) |
SRC_ADDR_NOT_MAPPED |
DST_ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
BUSY
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Result
None
Description
This command is used to program the flash memory. The affected sectors should
be prepared first by calling "Prepare Sector for Write Operation" command. The
affected sectors are automatically protected again once the copy command is
successfully executed. The boot sector can not be written by this command.
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17.6.3 Erase Sector(s) (IAP)
Table 171. IAP Erase Sector(s) command
Command
Erase Sector(s)
Input
Command code: 5210
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
Param2: System Clock Frequency (CCLK) in kHz.
Return Code
CMD_SUCCESS |
BUSY |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
INVALID_SECTOR
Result
None
Description
This command is used to erase a sector or multiple sectors of on-chip flash
memory. The boot sector can not be erased by this command. To erase a single
sector use the same "Start" and "End" sector numbers.
17.6.4 Blank check sector(s) (IAP)
Table 172. IAP Blank check sector(s) command
Command
Blank check sector(s)
Input
Command code: 5310
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
Return Code
CMD_SUCCESS |
BUSY |
SECTOR_NOT_BLANK |
INVALID_SECTOR
Result
Result0: Offset of the first non blank word location if the Status Code is
SECTOR_NOT_BLANK.
Result1: Contents of non blank word location.
Description
This command is used to blank check a sector or multiple sectors of on-chip flash
memory. To blank check a single sector use the same "Start" and "End" sector
numbers.
17.6.5 Read Part Identification number (IAP)
Table 173. IAP Read Part Identification command
Command
Read part identification number
Input
Command code: 5410
Return Code
CMD_SUCCESS |
Result
Result0: Part Identification Number.
Description
This command is used to read the part identification number.
Parameters: None
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17.6.6 Read Boot code version number (IAP)
Table 174. IAP Read Boot Code version number command
Command
Read boot code version number
Input
Command code: 5510
Parameters: None
Return Code
CMD_SUCCESS |
Result
Result0: 2 bytes of boot code version number in ASCII format. It is to be
interpreted as <byte1(Major)>.<byte0(Minor)>
Description
This command is used to read the boot code version number.
17.6.7 Compare <address1> <address2> <no of bytes> (IAP)
Table 175. IAP Compare command
Command
Compare
Input
Command code: 5610
Param0(DST): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param1(SRC): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param2: Number of bytes to be compared; should be a multiple of 4.
Return Code
CMD_SUCCESS |
COMPARE_ERROR |
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED
Result
Description
Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.
This command is used to compare the memory contents at two locations.
The result may not be correct when the source or destination includes any
of the first 512 bytes starting from address zero. The first 512 bytes can be
re-mapped to RAM.
17.6.8 Reinvoke ISP (IAP)
Table 176. IAP Reinvoke ISP
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Command
Compare
Input
Command code: 5710
Return Code
None
Result
None.
Description
This command is used to invoke the bootloader in ISP mode. It maps boot
vectors, sets PCLK = CCLK, configures UART pins RXD and TXD, resets
counter/timer CT32B1 and resets the U0FDR (see Table 84). This command may
be used when a valid user program is present in the internal flash memory and no
pin is available to force the ISP mode.
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17.6.9 ReadUID (IAP)
Table 177. IAP ReadUID command
Command
Compare
Input
Command code: 5810
Return Code
CMD_SUCCESS
Result
Result0: The first 32-bit word (at the lowest address).
Result1: The second 32-bit word.
Result2: The third 32-bit word.
Result3: The fourth 32-bit word.
Description
This command is used to read the unique ID.
17.6.10 IAP Status Codes
Table 178. IAP Status Codes Summary
Status Mnemonic
Code
Description
0
CMD_SUCCESS
Command is executed successfully.
1
INVALID_COMMAND
Invalid command.
2
SRC_ADDR_ERROR
Source address is not on a word boundary.
3
DST_ADDR_ERROR
Destination address is not on a correct boundary.
4
SRC_ADDR_NOT_MAPPED
Source address is not mapped in the memory map.
Count value is taken in to consideration where
applicable.
5
DST_ADDR_NOT_MAPPED
Destination address is not mapped in the memory
map. Count value is taken in to consideration where
applicable.
6
COUNT_ERROR
Byte count is not multiple of 4 or is not a permitted
value.
7
INVALID_SECTOR
Sector number is invalid.
8
SECTOR_NOT_BLANK
Sector is not blank.
9
SECTOR_NOT_PREPARED_
FOR_WRITE_OPERATION
Command to prepare sector for write operation was
not executed.
10
COMPARE_ERROR
Source and destination data is not same.
11
BUSY
Flash programming hardware interface is busy.
17.7 Debug notes
17.7.1 Comparing flash images
Depending on the debugger used and the IDE debug settings, the memory that is visible
when the debugger connects might be the boot ROM, the internal SRAM, or the flash. To
help determine which memory is present in the current debug environment, check the
value contained at flash address 0x0000 0004. This address contains the entry point to
the code in the ARM Cortex-M0 vector table, which is the bottom of the boot ROM, the
internal SRAM, or the flash memory respectively.
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Table 179. Memory mapping in debug mode
Memory mapping mode
Memory start address visible at 0x0000 0004
Bootloader mode
0x1FFF 0000
User flash mode
0x0000 0000
User SRAM mode
0x1000 0000
17.7.2 Serial Wire Debug (SWD) flash programming interface
Debug tools can write parts of the flash image to RAM and then execute the IAP call
"Copy RAM to flash" repeatedly with proper offset.
17.8 Flash memory access
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x4003 C010.
Remark: Improper setting of this register may result in incorrect operation of the LPC1102
flash memory.
Table 180. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description
Bit
Symbol
1:0
FLASHTIM
31:2 -
Value Description
Reset
value
Flash memory access time. FLASHTIM +1 is equal to the
number of system clocks used for flash access.
10
00
1 system clock flash access time (for system clock
frequencies of up to 20 MHz).
01
2 system clocks flash access time (for system clock
frequencies of up to 40 MHz).
10
3 system clocks flash access time (for system clock
frequencies of up to 50 MHz).
11
Reserved.
-
Reserved. User software must not change the value of
<tbd>
these bits. Bits 31:2 must be written back exactly as read.
17.9 Flash signature generation
The flash module contains a built-in signature generator. This generator can produce a
128-bit signature from a range of flash memory. A typical usage is to verify the flashed
contents against a calculated signature (e.g. during programming).
The address range for generating a signature must be aligned on flash-word boundaries,
i.e. 128-bit boundaries. Once started, signature generation completes independently.
While signature generation is in progress, the flash memory cannot be accessed for other
purposes, and an attempted read will cause a wait state to be asserted until signature
generation is complete. Code outside of the flash (e.g. internal RAM) can be executed
during signature generation. This can include interrupt services, if the interrupt vector
table is re-mapped to memory other than the flash memory. The code that initiates
signature generation should also be placed outside of the flash memory.
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17.9.1 Register description for signature generation
Table 181. Register overview: FMC (base address 0x4003 C000)
Name
Access Address Description
offset
Reset Reference
value
FMSSTART
R/W
0x020
Signature start address register
0
Table 182
FMSSTOP
R/W
0x024
Signature stop-address register
0
Table 183
FMSW0
R
0x02C
Word 0 [31:0]
-
Table 184
FMSW1
R
0x030
Word 1 [63:32]
-
Table 185
FMSW2
R
0x034
Word 2 [95:64]
-
Table 186
FMSW3
R
0x038
Word 3 [127:96]
-
Table 187
FMSTAT
R
0xFE0
Signature generation status register
0
Section 17.
9.1.3
FMSTATCLR W
0xFE8
Signature generation status clear
register
Section 17.
9.1.4
17.9.1.1 Signature generation address and control registers
These registers control automatic signature generation. A signature can be generated for
any part of the flash memory contents. The address range to be used for generation is
defined by writing the start address to the signature start address register (FMSSTART)
and the stop address to the signature stop address register (FMSSTOP. The start and
stop addresses must be aligned to 128-bit boundaries and can be derived by dividing the
byte address by 16.
Signature generation is started by setting the SIG_START bit in the FMSSTOP register.
Setting the SIG_START bit is typically combined with the signature stop address in a
single write.
Table 182 and Table 183 show the bit assignments in the FMSSTART and FMSSTOP
registers respectively.
Table 182. Flash Module Signature Start register (FMSSTART - 0x4003 C020) bit description
Bit
Symbol
Description
Reset
value
31:17
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
16:0
START
Signature generation start address (corresponds to AHB byte
address bits[20:4]).
0
Table 183. Flash Module Signature Stop register (FMSSTOP - 0x4003 C024) bit description
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Bit
Symbol
31:18
-
Value
Description
Reset
value
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
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Table 183. Flash Module Signature Stop register (FMSSTOP - 0x4003 C024) bit description
Bit
Symbol
17
SIG_START
16:0
Value
STOP
Description
Reset
value
Start control bit for signature generation.
0
0
Signature generation is stopped
1
Initiate signature generation
BIST stop address divided by 16 (corresponds to AHB
byte address [20:4]).
0
17.9.1.2 Signature generation result registers
The signature generation result registers return the flash signature produced by the
embedded signature generator. The 128-bit signature is reflected by the four registers
FMSW0, FMSW1, FMSW2 and FMSW3.
The generated flash signature can be used to verify the flash memory contents. The
generated signature can be compared with an expected signature and thus makes saves
time and code space. The method for generating the signature is described in
Section 17.9.2.
Table 187 show bit assignment of the FMSW0 and FMSW1, FMSW2, FMSW3 registers
respectively.
Table 184. FMSW0 register bit description (FMSW0, address: 0x4003 C02C)
Bit
Symbol
Description
Reset value
31:0
SW0[31:0]
Word 0 of 128-bit signature (bits 31 to 0).
-
Table 185. FMSW1 register bit description (FMSW1, address: 0x4003 C030)
Bit
Symbol
Description
Reset value
31:0
SW1[63:32]
Word 1 of 128-bit signature (bits 63 to 32).
-
Table 186. FMSW2 register bit description (FMSW2, address: 0x4003 C034)
Bit
Symbol
Description
Reset value
31:0
SW2[95:64]
Word 2 of 128-bit signature (bits 95 to 64).
-
Table 187. FMSW3 register bit description (FMSW3, address: 0x4003 40C8)
Bit
Symbol
Description
Reset value
31:0
SW3[127:96]
Word 3 of 128-bit signature (bits 127 to 96).
-
17.9.1.3 Flash Module Status register
The read-only FMSTAT register provides a means of determining when signature
generation has completed. Completion of signature generation can be checked by polling
the SIG_DONE bit in FMSTAT. SIG_DONE should be cleared via the FMSTATCLR
register before starting a signature generation operation, otherwise the status might
indicate completion of a previous operation.
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Table 188. Flash module Status register (FMSTAT - 0x4003 CFE0) bit description
Bit
Symbol
Description
Reset
value
31:2
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
2
SIG_DONE
When 1, a previously started signature generation has
0
completed. See FMSTATCLR register description for clearing this
flag.
1:0
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
17.9.1.4 Flash Module Status Clear register
The FMSTATCLR register is used to clear the signature generation completion flag.
Table 189. Flash Module Status Clear register (FMSTATCLR - 0x0x4003 CFE8) bit description
Bit
Symbol
Description
Reset
value
31:2
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
2
SIG_DONE_CLR Writing a 1 to this bits clears the signature generation
completion flag (SIG_DONE) in the FMSTAT register.
0
1:0
-
NA
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
17.9.2 Algorithm and procedure for signature generation
Signature generation
A signature can be generated for any part of the flash contents. The address range to be
used for signature generation is defined by writing the start address to the FMSSTART
register, and the stop address to the FMSSTOP register.
The signature generation is started by writing a ‘1’ to FMSSTOP.MISR_START. Starting
the signature generation is typically combined with defining the stop address, which is
done in another field FMSSTOP.FMSSTOP of the same register.
The time that the signature generation takes is proportional to the address range for which
the signature is generated. Reading of the flash memory for signature generation uses a
self-timed read mechanism and does not depend on any configurable timing settings for
the flash. A safe estimation for the duration of the signature generation is:
Duration = int( (60 / tcy) + 3 ) x (FMSSTOP - FMSSTART + 1)
When signature generation is triggered via software, the duration is in AHB clock cycles,
and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled
by software to determine when signature generation is complete.
If signature generation is triggered via JTAG, the duration is in JTAG tck cycles, and tcy is
the time in ns for one JTAG clock. Polling the SIG_DONE bit in FMSTAT is not possible in
this case.
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After signature generation, a 128-bit signature can be read from the FMSW0 to FMSW3
registers. The 128-bit signature reflects the corrected data read from the flash. The 128-bit
signature reflects flash parity bits and check bit values.
Content verification
The signature as it is read from the FMSW0 to FMSW3 registers must be equal to the
reference signature. The algorithms to derive the reference signature is given in
Figure 33.
sign = 0
FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP
{
FOR i = 0 TO 126
nextSign[i] = f_Q[address][i] XOR sign[i+1]
nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR
sign[27] XOR sign[29]
sign = nextSign
}
signature128 = sign
Fig 33. Algorithm for generating a 128 bit signature
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Chapter 18: LPC1102 Serial Wire Debug (SWD)
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18.1 How to read this chapter
The debug functionality is implemented on the LPC1102.
18.2 Features
•
•
•
•
Supports ARM Serial Wire Debug mode.
Direct debug access to all memories, registers, and peripherals.
No target resources are required for the debugging session.
Four breakpoints. Four instruction breakpoints that can also be used to remap
instruction addresses for code patches. Two data comparators that can be used to
remap addresses for patches to literal values.
• Two data watchpoints that can also be used as triggers.
18.3 Introduction
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported. The ARM Cortex-M0 is configured to support up to four breakpoints and two
watchpoints.
18.4 Description
Debugging with the LPC1102 uses the Serial Wire Debug mode.
18.5 Pin description
The tables below indicate the various pin functions related to debug. Some of these
functions share pins with other functions which therefore may not be used at the same
time.
Table 190. Serial Wire Debug pin description
Pin Name
Type
Description
SWCLK
Input
Serial Wire Clock. This pin is the clock for debug logic when in the
Serial Wire Debug mode (SWCLK). This pin is pulled up internally.
SWDIO
Input /
Output
Serial wire debug data input/output. The SWDIO pin is used by an
external debug tool to communicate with and control the LPC1102.
This pin is pulled up internally.
Remark: Note that the SPI clock SCK and the serial wire debug clock SWCLK share the
same pin on the WLCSP16 package. Once the SPI is enabled, the serial wire debugger is
no longer available.
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18.6 Debug notes
18.6.1 Debug limitations
Important: The user should be aware of certain limitations during debugging. The most
important is that, due to limitations of the ARM Cortex-M0 integration, the LPC1102
cannot wake up in the usual manner from Deep-sleep mode. It is recommended not to
use this mode during debug.
Another issue is that debug mode changes the way in which reduced power modes work
internal to the ARM Cortex-M0 CPU, and this ripples through the entire system. These
differences mean that power measurements should not be made while debugging, the
results will be higher than during normal operation in an application.
During a debugging session, the System Tick Timer is automatically stopped whenever
the CPU is stopped. Other peripherals are not affected.
18.6.2 Debug connections
Signals from SWD connector
VDD
LPC1102
VTREF
SWDIO
SWCLK
SWDIO
SWCLK
nSRST
RESET
GND
Gnd
The VTREF pin on the SWD connector enables the debug connector to match the target voltage.
Fig 34. Connecting the SWD pins to a standard SWD connector
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19.1 Introduction
The following material is using the ARM Cortex-M0 User Guide. Minor changes have
been made regarding the specific implementation of the Cortex-M0 for the LPC1102.
The ARM Cortex-M0 documentation is also available in Ref. 1 and Ref. 2.
19.2 About the Cortex-M0 processor and core peripherals
The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers,
including:
•
•
•
•
•
a simple architecture that is easy to learn and program
ultra-low power, energy efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family.
Cortex-M0 components
Cortex-M0 processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Debug
Cortex-M0
processor
core
Breakpoint
and
watchpoint
unit
Bus matrix
Debugger
interface
AHB-Lite interface to system
Debug
Access Port
(DAP)
Serial Wire debug-port
Fig 35. Cortex-M0 implementation
The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor
core, with a 3-stage pipeline von Neumann architecture. The processor delivers
exceptional energy efficiency through a small but powerful instruction set and extensively
optimized design, providing high-end processing hardware including a single-cycle
multiplier.
The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the
16-bit Thumb instruction set and includes Thumb-2 technology. This provides the
exceptional performance expected of a modern 32-bit architecture, with a higher code
density than other 8-bit and 16-bit microcontrollers.
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
• includes a non-maskable interrupt (NMI). The NMI is not implemented on the
LPC1102.
• provides zero jitter interrupt option
• provides four interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart
load-multiple and store-multiple operations. Interrupt handlers do not require any
assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining
optimization also significantly reduces the overhead when switching from one ISR to
another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
Deep-sleep function that enables the entire device to be rapidly powered down.
19.2.1 System-level interface
The Cortex-M0 processor provides a single system-level interface using AMBA
technology to provide high speed, low latency memory accesses.
19.2.2 Integrated configurable debug
The Cortex-M0 processor implements a complete hardware debug solution, with
extensive hardware breakpoint and watchpoint options. This provides high system
visibility of the processor, memory and peripherals through a 2-pin Serial Wire Debug
(SWD) port that is ideal for microcontrollers and other small package devices.
19.2.3 Cortex-M0 processor features summary
•
•
•
•
•
•
•
high code density with 32-bit performance
tools and binary upwards compatible with Cortex-M processor family
integrated ultra low-power sleep modes
efficient code execution permits slower processor clock or increases sleep mode time
single-cycle 32-bit hardware multiplier
zero jitter interrupt handling
extensive debug capabilities.
19.2.4 Cortex-M0 core peripherals
These are:
NVIC — The NVIC is an embedded interrupt controller that supports low latency interrupt
processing.
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System Control Block — The System Control Block (SCB) is the programmers model
interface to the processor. It provides system implementation information and system
control, including configuration, control, and reporting of system exceptions.
System timer — The system timer, SysTick, is a 24-bit count-down timer. Use this as a
Real Time Operating System (RTOS) tick timer or as a simple counter.
19.3 Processor
19.3.1 Programmers model
This section describes the Cortex-M0 programmers model. In addition to the individual
core register descriptions, it contains information about the processor modes and stacks.
19.3.1.1 Processor modes
The processor modes are:
Thread mode — Used to execute application software. The processor enters Thread
mode when it comes out of reset.
Handler mode — Used to handle exceptions. The processor returns to Thread mode
when it has finished all exception processing.
19.3.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer indicates the
last stacked item on the stack memory. When the processor pushes a new item onto the
stack, it decrements the stack pointer and then writes the item to the new memory
location. The processor implements two stacks, the main stack and the process stack,
with independent copies of the stack pointer, see Section 19.3.1.3.2.
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see Section 19–19.3.1.3.7. In Handler mode, the processor
always uses the main stack. The options for processor operations are:
Table 191. Summary of processor mode and stack use options
Processor
mode
Used to
execute
Stack used
Thread
Applications
Main stack or process stack
See Section 19–19.3.1.3.7
Handler
Exception
handlers
Main stack
19.3.1.3 Core registers
The processor core registers are:
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R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
SP (R13)
LR (R14)
PC (R15)
Low registers
High registers
Stack Pointer
Link Register
Program Counter
PSR
PRIMASK
CONTROL
General purpose registers
PSP
Program Status Register
Interrupt mask register
Control Register
MSP
Special registers
Fig 36. Processor core register set
Table 192. Core register set summary
19.3.1.3.1
Name
Type [1]
Reset value
Description
R0-R12
RW
Unknown
Section 19–19.3.1.3.1
MSP
RW
See description
Section 19–19.3.1.3.2
PSP
RW
Unknown
Section 19–19.3.1.3.2
LR
RW
Unknown
Section 19–19.3.1.3.3
PC
RW
See description
Section 19–19.3.1.3.4
PSR
RW
Unknown[2]
Table 19–193
APSR
RW
Unknown
Table 19–194
IPSR
RO
0x00000000
Table 195
EPSR
RO
Unknown [2]
Table 19–196
PRIMASK
RW
0x00000000
Table 19–197
CONTROL
RW
0x00000000
Table 19–198
[1]
Describes access type during program execution in thread mode and Handler mode. Debug access can
differ.
[2]
Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
19.3.1.3.2
Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
• 0 = Main Stack Pointer (MSP). This is the reset value.
• 1 = Process Stack Pointer (PSP).
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On reset, the processor loads the MSP with the value from address 0x00000000.
19.3.1.3.3
Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions. On reset, the LR value is Unknown.
19.3.1.3.4
Program Counter
The Program Counter (PC) is register R15. It contains the current program address. On
reset, the processor loads the PC with the value of the reset vector, which is at address
0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.
19.3.1.3.5
Program Status Register
The Program Status Register (PSR) combines:
• Application Program Status Register (APSR)
• Interrupt Program Status Register (IPSR)
• Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR bit
assignments are:
31 30 29 28 27
25 24 23
6 5
APSR N Z C V
Reserved
IPSR
EPSR
0
Reserved
Reserved
T
Exception number
Reserved
Fig 37. APSR, IPSR, EPSR register bit assignments
Access these registers individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example:
• read all of the registers using PSR with the MRS instruction
• write to the APSR using APSR with the MSR instruction.
The PSR combinations and attributes are:
Table 193. PSR register combinations
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Register
Type
Combination
PSR
RW[1][2]
APSR, EPSR, and IPSR
IEPSR
RO
EPSR and IPSR
IAPSR
RW[1]
APSR and IPSR
EAPSR
RW[2]
APSR and EPSR
[1]
The processor ignores writes to the IPSR bits.
[2]
Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
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See the instruction descriptions Section 19–19.4.7.6 and Section 19–19.4.7.7 for more
information about how to access the program status registers.
Application Program Status Register: The APSR contains the current state of the
condition flags, from previous instruction executions. See the register summary in
Table 19–192 for its attributes. The bit assignments are:
Table 194. APSR bit assignments
Bits
Name
Function
[31]
N
Negative flag
[30]
Z
Zero flag
[29]
C
Carry or borrow flag
[28]
V
Overflow flag
[27:0]
-
Reserved
See Section 19.4.4.1.4 for more information about the APSR negative, zero, carry or
borrow, and overflow flags.
Interrupt Program Status Register: The IPSR contains the exception number of the
current Interrupt Service Routine (ISR). See the register summary in Table 19–192 for
its attributes. The bit assignments are:
Table 195. IPSR bit assignments
Bits
Name
Function
[31:6]
-
Reserved
[5:0]
Exception number This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = HardFault
4-10 = Reserved
11 = SVCall
12, 13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
.
.
.
47 = IRQ31
48-63 = Reserved.
see Section 19–19.3.3.2 for more information.
Execution Program Status Register: The EPSR contains the Thumb state bit.
See the register summary in Table 19–192 for the EPSR attributes. The bit assignments
are:
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Table 196. EPSR bit assignments
Bits
Name
Function
[31:25]
-
Reserved
[24]
T
Thumb state bit
[23:0]
-
Reserved
Attempts by application software to read the EPSR directly using the MRS instruction
always return zero. Attempts to write the EPSR using the MSR instruction are ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the cause of the
fault. See Section 19–19.3.3.6. The following can clear the T bit to 0:
• instructions BLX, BX and POP{PC}
• restoration from the stacked xPSR value on an exception return
• bit[0] of the vector value on an exception entry.
Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See
Section 19–19.3.4.1 for more information.
Interruptible-restartable instructions: The interruptible-restartable instructions are LDM
and STM. When an interrupt occurs during the execution of one of these instructions, the
processor abandons execution of the instruction.
After servicing the interrupt, the processor restarts execution of the instruction from the
beginning.
19.3.1.3.6
Exception mask register
The exception mask register disables the handling of exceptions by the processor.
Disable exceptions where they might impact on timing critical tasks or code sequences
requiring atomicity.
To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS instruction,
to change the value of PRIMASK. See Section 19–19.4.7.6, Section 19–19.4.7.7, and
Section 19–19.4.7.2 for more information.
Priority Mask Register: The PRIMASK register prevents activation of all exceptions with
configurable priority. See the register summary in Table 19–192 for its attributes. The bit
assignments are:
Table 197. PRIMASK register bit assignments
Bits
Name
Function
[31:1]
-
Reserved
[0]
PRIMASK
0 = no effect
1 = prevents the activation of all exceptions with
configurable priority.
19.3.1.3.7
CONTROL register
The CONTROL register controls the stack used when the processor is in Thread mode.
See the register summary in Table 19–192 for its attributes. The bit assignments are:
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Table 198. CONTROL register bit assignments
Bits
Name
Function
[31:2]
-
Reserved
[1]
Active stack
pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
[0]
-
Reserved.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry
and return mechanisms update the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode
to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see
Section 19–19.4.7.6.
Remark: When changing the stack pointer, software must use an ISB instruction
immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer. See Section 19–19.4.7.5.
19.3.1.4 Exceptions and interrupts
The Cortex-M0 processor supports interrupts and system exceptions. The processor and
the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An
interrupt or exception changes the normal flow of software control. The processor uses
handler mode to handle all exceptions except for reset. See Section 19–19.3.3.6.1 and
Section 19–19.3.3.6.2 for more information.
The NVIC registers control interrupt handling. See Section 19–19.5.2 for more
information.
19.3.1.5 Data types
The processor:
• supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
• manages all data memory accesses as little-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always little-endian. See Section 19–19.3.2.1 for
more information.
19.3.1.6 The Cortex Microcontroller Software Interface Standard
ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for
programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device
driver library.
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For a Cortex-M0 microcontroller system, CMSIS defines:
• a common way to:
– access peripheral registers
– define exception vectors
• the names of:
– the registers of the core peripherals
– the core exception vectors
• a device-independent interface for RTOS kernels.
The CMSIS includes address definitions and data structures for the core peripherals in the
Cortex-M0 processor. It also includes optional interfaces for middleware components
comprising a TCP/IP stack and a Flash file system.
The CMSIS simplifies software development by enabling the reuse of template code, and
the combination of CMSIS-compliant software components from various middleware
vendors. Software vendors can expand the CMSIS to include their peripheral definitions
and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark: This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.
The following sections give more information about the CMSIS:
•
•
•
•
Section 19.3.5.3 “Power management programming hints”
Section 19.4.2 “Intrinsic functions”
Section 19.5.2.1 “Accessing the Cortex-M0 NVIC registers using CMSIS”
Section 19.5.2.8.1 “NVIC programming hints”.
19.3.2 Memory model
This section describes the processor memory map and the behavior of memory accesses.
The processor has a fixed memory map that provides up to 4GB of addressable memory.
The memory map is:
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0xFFFFFFFF
Device
511MB
Private peripheral bus 1MB
External device
0xE0100000
0xE00FFFFF
0xE0000000
0xDFFFFFFF
1.0GB
0xA0000000
0x9FFFFFFF
External RAM
1.0GB
0x60000000
0x5FFFFFFF
Peripheral
0.5GB
0x40000000
0x3FFFFFFF
SRAM
0.5GB
0x20000000
0x1FFFFFFF
Code
0.5GB
0x00000000
See Figure 2 for the LPC1102 specific implementation of the memory map. SRAM and code
locations are different on the LPC1102.
Fig 38. Generic ARM Cortex-M0 memory map
The processor reserves regions of the Private peripheral bus (PPB) address range for
core peripheral registers, see Section 19–19.2.
19.3.2.1 Memory regions, types and attributes
The memory map is split into regions. Each region has a defined memory type, and some
regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
The memory types are:
Normal — The processor can re-order transactions for efficiency, or perform speculative
reads.
Device — The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
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Strongly-ordered — The processor preserves transaction order relative to all other
transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that
the memory system can buffer a write to Device memory, but must not buffer a write to
Strongly-ordered memory.
The additional memory attributes include.
Execute Never (XN) — Means the processor prevents instruction accesses. A HardFault
exception is generated on executing an instruction fetched from an XN region of memory.
19.3.2.2 Memory system ordering of memory accesses
For most memory accesses caused by explicit memory access instructions, the memory
system does not guarantee that the order in which the accesses complete matches the
program order of the instructions, providing any re-ordering does not affect the behavior of
the instruction sequence. Normally, if correct program execution depends on two memory
accesses completing in program order, software must insert a memory barrier instruction
between the memory access instructions, see Section 19–19.3.2.4.
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs
before A2 in program order, the ordering of the memory accesses caused by two
instructions is:
Normal
access
Non-shareable
Shareable
Stronglyordered
access
Normal access
-
-
-
-
Device access, non-shareable
-
<
-
<
Device access, shareable
-
-
<
<
Strongly-ordered access
-
<
<
<
A2
A1
Device access
Fig 39. Memory ordering restrictions
Where:
- — Means that the memory system does not guarantee the ordering of the accesses.
< — Means that accesses are observed in program order, that is, A1 is always observed
before A2.
19.3.2.3 Behavior of memory accesses
The behavior of accesses to each region in the memory map is:
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Table 199. Memory access behavior
Address
range
Memory
region
Memory
type [1]
XN [1] Description
0x000000000x1FFFFFFF
Code
Normal
-
Executable region for program
code. You can also put data here.
0x200000000x3FFFFFFF
SRAM
Normal
-
Executable region for data. You
can also put code here.
0x400000000x5FFFFFFF
Peripheral
Device
XN
External device memory.
0x600000000x9FFFFFFF
External
RAM
Normal
-
Executable region for data.
0xA00000000xDFFFFFFF
External
device
Device
XN
External device memory.
0xE00000000xE00FFFFF
Private Peripheral Strongly-ordered
Bus
XN
This region includes the NVIC,
System timer, and System Control
Block. Only word accesses can be
used in this region.
0xE01000000xFFFFFFFF
Device
XN
Vendor specific.
[1]
Device
See Section 19–19.3.2.1 for more information.
The Code, SRAM, and external RAM regions can hold programs.
19.3.2.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
• the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence
• memory or devices in the memory map might have different wait states
• some memory accesses are buffered or speculative.
Section 19–19.3.2.2 describes the cases where the memory system guarantees the order
of memory accesses. Otherwise, if the order of memory accesses is critical, software
must include memory barrier instructions to force that ordering. The processor provides
the following memory barrier instructions:
DMB — The Data Memory Barrier (DMB) instruction ensures that outstanding memory
transactions complete before subsequent memory transactions. See Section 19–19.4.7.3.
DSB — The Data Synchronization Barrier (DSB) instruction ensures that outstanding
memory transactions complete before subsequent instructions execute. See
Section 19–19.4.7.4.
ISB — The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent instructions. See
Section 19–19.4.7.5.
The following are examples of using memory barrier instructions:
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Vector table — If the program changes an entry in the vector table, and then enables the
corresponding exception, use a DMB instruction between the operations. This ensures that
if the exception is taken immediately after being enabled the processor uses the new
exception vector.
Self-modifying code — If a program contains self-modifying code, use an ISB instruction
immediately after the code modification in the program. This ensures subsequent
instruction execution uses the updated program.
Memory map switching — If the system contains a memory map switching mechanism,
use a DSB instruction after switching the memory map. This ensures subsequent
instruction execution uses the updated memory map.
Memory accesses to Strongly-ordered memory, such as the System Control Block, do not
require the use of DMB instructions.
The processor preserves transaction order relative to all other transactions.
19.3.2.5 Memory endianness
The processor views memory as a linear collection of bytes numbered in ascending order
from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the
second stored word. Section 19–19.3.2.5.1 describes how words of data are stored in
memory.
19.3.2.5.1
Little-endian format
In little-endian format, the processor stores the least significant byte (lsbyte) of a word at
the lowest-numbered byte, and the most significant byte (msbyte) at the
highest-numbered byte. For example:
Register
Memory
7
0
31
Address
A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
Fig 40. Little-endian format
19.3.3 Exception model
This section describes the exception model.
19.3.3.1 Exception states
Each exception is in one of the following states:
Inactive — The exception is not active and not pending.
Pending — The exception is waiting to be serviced by the processor.
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An interrupt request from a peripheral or from software can change the state of the
corresponding interrupt to pending.
Active — An exception that is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this
case both exceptions are in the active state.
Active and pending — The exception is being serviced by the processor and there is a
pending exception from the same source.
19.3.3.2 Exception types
The exception types are:
Remark: The NMI is not implemented on the LPC1102.
Reset — Reset is invoked on power up or a warm reset. The exception model treats reset
as a special form of exception. When reset is asserted, the operation of the processor
stops, potentially at any point in an instruction. When reset is deasserted, execution
restarts from the address provided by the reset entry in the vector table. Execution restarts
in Thread mode.
NMI — A NonMaskable Interrupt (NMI) can be signalled by a peripheral or triggered by
software. This is the highest priority exception other than reset. It is permanently enabled
and has a fixed priority of −2. NMIs cannot be:
• masked or prevented from activation by any other exception
• preempted by any exception other than Reset.
HardFault — A HardFault is an exception that occurs because of an error during normal
or exception processing. HardFaults have a fixed priority of -1, meaning they have higher
priority than any exception with configurable priority.
SVCall — A supervisor call (SVC) is an exception that is triggered by the SVC instruction.
In an OS environment, applications can use SVC instructions to access OS kernel functions
and device drivers.
PendSV — PendSV is an interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active.
SysTick — A SysTick exception is an exception the system timer generates when it
reaches zero. Software can also generate a SysTick exception. In an OS environment, the
processor can use this exception as system tick.
Interrupt (IRQ) — An interrupt, or IRQ, is an exception signalled by a peripheral, or
generated by a software request. All interrupts are asynchronous to instruction execution.
In the system, peripherals use interrupts to communicate with the processor.
Table 200. Properties of different exception types
Exception
number [1]
User manual
Exception
type
Priority
Vector
address[2]
1
-
Reset
-3, the highest
0x00000004
2
-14
NMI
-2
0x00000008
3
-13
HardFault
-1
0x0000000C
4-10
-
Reserved
-
-
SVCall
Configurable [3]
0x0000002C
11
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Table 200. Properties of different exception types
Exception
number [1]
IRQ
number [1]
Exception
type
Priority
Vector
address[2]
12-13
-
Reserved
-
0x00000038
14
-2
PendSV
Configurable [3]
15
-1
SysTick
Configurable [3]
0x0000003C
Interrupt (IRQ)
Configurable [3]
0x00000040 and
above [4]
16 and above
0 and above
[1]
To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for
exceptions other than interrupts. The IPSR returns the Exception number, see Table 19–195.
[2]
See Section 19.3.3.4 for more information.
[3]
See Section 19–19.5.2.6.
[4]
Increasing in steps of 4.
For an asynchronous exception, other than reset, the processor can execute additional
instructions between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that Table 19–200 shows as having
configurable priority, see Section 19–19.5.2.3.
For more information about HardFaults, see Section 19–19.3.4.
19.3.3.3 Exception handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs) — Interrupts IRQ0 to IRQ31 are the exceptions
handled by ISRs.
Fault handler — HardFault is the only exception handled by the fault handler.
System handlers — NMI, PendSV, SVCall SysTick, and HardFault are all system
exceptions handled by system handlers.
19.3.3.4 Vector table
The vector table contains the reset value of the stack pointer, and the start addresses,
also called exception vectors, for all exception handlers. Figure 19–41 shows the order of
the exception vectors in the vector table. The least-significant bit of each vector must be 1,
indicating that the exception handler is written in Thumb code.
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Vector
Exception number IRQ number
47
31
IRQ31
.
.
.
.
.
.
18
2
IRQ2
17
1
IRQ1
16
0
IRQ0
15
-1
SysTick
14
-2
PendSV
13
0xBC
.
.
.
0x48
0x44
0x40
0x3C
0x38
Reserved
12
11
Offset
-5
SVCall
10
0x2C
9
8
7
Reserved
6
5
4
3
-13
HardFault
2
-14
NMI
1
Reset
Initial SP value
0x10
0x0C
0x08
0x04
0x00
Fig 41. Vector table
The vector table is fixed at address 0x00000000.
19.3.3.5 Exception priorities
As Table 19–200 shows, all exceptions have an associated priority, with:
• a lower priority value indicating a higher priority
• configurable priorities for all exceptions except Reset, HardFault, and NMI.
If software does not configure any priorities, then all exceptions with a configurable priority
have a priority of 0. For information about configuring exception priorities see
• Section 19–19.5.3.7
• Section 19–19.5.2.6.
Remark: Configurable priority values are in the range 0-3. The Reset, HardFault, and NMI
exceptions, with fixed negative priority values, always have higher priority than any other
exception.
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Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that
IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is
processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the
lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are
pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is
preempted if a higher priority exception occurs. If an exception occurs with the same
priority as the exception being handled, the handler is not preempted, irrespective of the
exception number. However, the status of the new interrupt changes to pending.
19.3.3.6 Exception entry and return
Descriptions of exception handling use the following terms:
Preemption — When the processor is executing an exception handler, an exception can
preempt the exception handler if its priority is higher than the priority of the exception
being handled.
When one exception preempts another, the exceptions are called nested exceptions. See
Section 19–19.3.3.6.1 for more information.
Return — This occurs when the exception handler is completed, and:
• there is no pending exception with sufficient priority to be serviced
• the completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before
the interrupt occurred. See Section 19–19.3.3.6.2 for more information.
Tail-chaining — This mechanism speeds up exception servicing. On completion of an
exception handler, if there is a pending exception that meets the requirements for
exception entry, the stack pop is skipped and control transfers to the new exception
handler.
Late-arriving — This mechanism speeds up preemption. If a higher priority exception
occurs during state saving for a previous exception, the processor switches to handle the
higher priority exception and initiates the vector fetch for that exception. State saving is
not affected by late arrival because the state saved would be the same for both
exceptions. On return from the exception handler of the late-arriving exception, the normal
tail-chaining rules apply.
19.3.3.6.1
Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and
either:
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case
the new exception preempts the exception being handled.
When one exception preempts another, the exceptions are nested.
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Sufficient priority means the exception has greater priority than any limit set by the mask
register, see Section 19–19.3.1.3.6. An exception with less priority than this is pending but
is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a
late-arriving exception, the processor pushes information onto the current stack. This
operation is referred to as stacking and the structure of eight data words is referred as a
stack frame. The stack frame contains the following information:
Decreasing
memory
address
SP
SP
SP
SP
SP
SP
SP
SP
+
+
+
+
+
+
+
+
0x1C
0x18
0x14
0x10
0x0C
0x08
0x04
0x00
<previous>
xPSR
PC
LR
R12
R3
R2
R1
R0
SP points here before interrupt
SP points here after interrupt
Fig 42. Exception entry stack contents
Immediately after stacking, the stack pointer indicates the lowest address in the stack
frame. The stack frame is aligned to a double-word address.
The stack frame includes the return address. This is the address of the next instruction in
the interrupted program. This value is restored to the PC at exception return so that the
interrupted program resumes.
The processor performs a vector fetch that reads the exception handler start address from
the vector table. When stacking is complete, the processor starts executing the exception
handler. At the same time, the processor writes an EXC_RETURN value to the LR. This
indicates which stack pointer corresponds to the stack frame and what operation mode
the processor was in before the entry occurred.
If no higher priority exception occurs during exception entry, the processor starts
executing the exception handler and automatically changes the status of the
corresponding pending interrupt to active.
If another higher priority exception occurs during exception entry, the processor starts
executing the exception handler for this exception and does not change the pending
status of the earlier exception. This is the late arrival case.
19.3.3.6.2
Exception return
Exception return occurs when the processor is in Handler mode and execution of one of
the following instructions attempts to set the PC to an EXC_RETURN value:
• a POP instruction that loads the PC
• a BX instruction using any register.
The processor saves an EXC_RETURN value to the LR on exception entry. The
exception mechanism relies on this value to detect when the processor has completed an
exception handler. Bits[31:4] of an EXC_RETURN value are 0xFFFFFFF. When the
processor loads a value matching this pattern to the PC it detects that the operation is a
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not a normal branch operation and, instead, that the exception is complete. Therefore, it
starts the exception return sequence. Bits[3:0] of the EXC_RETURN value indicate the
required return stack and processor mode, as Table 19–201 shows.
Table 201. Exception return behavior
EXC_RETURN
Description
0xFFFFFFF1
Return to Handler mode.
Exception return gets state from the main stack.
Execution uses MSP after return.
0xFFFFFFF9
Return to Thread mode.
Exception return gets state from MSP.
Execution uses MSP after return.
0xFFFFFFFD
Return to Thread mode.
Exception return gets state from PSP.
Execution uses PSP after return.
All other values
Reserved.
19.3.4 Fault handling
Faults are a subset of exceptions, see Section 19–19.3.3. All faults result in the HardFault
exception being taken or cause lockup if they occur in the NMI or HardFault handler. The
faults are:
•
•
•
•
•
•
•
•
execution of an SVC instruction at a priority equal or higher than SVCall
execution of a BKPT instruction without a debugger attached
a system-generated bus error on a load or store
execution of an instruction from an XN memory address
execution of an instruction from a location for which the system generates a bus fault
a system-generated bus error on a vector fetch
execution of an Undefined instruction
execution of an instruction when not in Thumb-State as a result of the T-bit being
previously cleared to 0
• an attempted load or store to an unaligned address.
Remark: Only Reset and NMI can preempt the fixed priority HardFault handler. A
HardFault can preempt any exception other than Reset, NMI, or another hard fault.
19.3.4.1 Lockup
The processor enters a lockup state if a fault occurs when executing the NMI or HardFault
handlers, or if the system generates a bus error when unstacking the PSR on an
exception return using the MSP. When the processor is in lockup state it does not execute
any instructions. The processor remains in lockup state until one of the following occurs:
• it is reset
• a debugger halts it
• an NMI occurs and the current lockup is in the HardFault handler.
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Remark: If lockup state occurs in the NMI handler a subsequent NMI does not cause the
processor to leave lockup state.
19.3.5 Power management
The Cortex-M0 processor sleep modes reduce power consumption:
• a sleep mode, that stops the processor clock
• a Deep-sleep mode.
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see
Section 19–19.5.3.5.
This section describes the mechanisms for entering sleep mode and the conditions for
waking up from sleep mode.
19.3.5.1 Entering sleep mode
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wake-up events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back in
to sleep mode.
19.3.5.1.1
Wait for interrupt
The Wait For Interrupt instruction, WFI, causes immediate entry to sleep mode. When the
processor executes a WFI instruction it stops executing instructions and enters sleep
mode. See Section 19–19.4.7.12 for more information.
19.3.5.1.2
Wait for event
Remark: The WFE instruction is not implemented on the LPC1102.
The Wait For Event instruction, WFE, causes entry to sleep mode conditional on the value
of a one-bit event register. When the processor executes a WFE instruction, it checks the
value of the event register:
0 — The processor stops executing instructions and enters sleep mode
1 — The processor sets the register to zero and continues executing instructions without
entering sleep mode.
See Section 19–19.4.7.11 for more information.
If the event register is 1, this indicates that the processor must not enter sleep mode on
execution of a WFE instruction. Typically, this is because of the assertion of an external
event, or because another processor in the system has executed a SEV instruction, see
Section 19–19.4.7.9. Software cannot access this register directly.
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19.3.5.1.3
Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the
execution of an exception handler and returns to Thread mode it immediately enters sleep
mode. Use this mechanism in applications that only require the processor to run when an
interrupt occurs.
19.3.5.2 Wake-up from sleep mode
The conditions for the processor to wake-up depend on the mechanism that caused it to
enter sleep mode.
19.3.5.2.1
Wake-up from WFI or sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority
to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK
bit to 1. If an interrupt arrives that is enabled and has a higher priority than current
exception priority, the processor wakes up but does not execute the interrupt handler until
the processor sets PRIMASK to zero. For more information about PRIMASK, see
Section 19–19.3.1.3.6.
19.3.5.2.2
Wake-up from WFE
The processor wakes up if:
• it detects an exception with sufficient priority to cause exception entry
• in a multiprocessor system, another processor in the system executes a SEV
instruction.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt
triggers an event and wakes up the processor, even if the interrupt is disabled or has
insufficient priority to cause exception entry. For more information about the SCR see
Section 19–19.5.3.5.
19.3.5.3 Power management programming hints
ISO/IEC C cannot directly generate the WFI, WFE, and SEV instructions. The CMSIS
provides the following intrinsic functions for these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
void __SEV(void) // Send Event
19.4 Instruction set
19.4.1 Instruction set summary
The processor implements a version of the Thumb instruction set. Table 202 lists the
supported instructions.
Remark: In Table 202
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• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands and mnemonic parts
• the Operands column is not exhaustive.
For more information on the instructions and operands, see the instruction descriptions.
Table 202. Cortex-M0 instructions
Mnemonic
Operands
Brief description
Flags
Reference
ADCS
{Rd,} Rn, Rm
Add with Carry
N,Z,C,V
Section 19–19.4.5.1
ADD{S}
{Rd,} Rn, <Rm|#imm>
Add
N,Z,C,V
Section 19–19.4.5.1
ADR
Rd, label
PC-relative Address to Register
-
Section 19–19.4.4.1
ANDS
{Rd,} Rn, Rm
Bitwise AND
N,Z
Section 19–19.4.5.1
ASRS
{Rd,} Rm, <Rs|#imm>
Arithmetic Shift Right
N,Z,C
Section 19–19.4.5.3
B{cc}
label
Branch {conditionally}
-
Section 19–19.4.6.1
BICS
{Rd,} Rn, Rm
Bit Clear
N,Z
Section 19–19.4.5.2
BKPT
#imm
Breakpoint
-
Section 19–19.4.7.1
BL
label
Branch with Link
-
Section 19–19.4.6.1
BLX
Rm
Branch indirect with Link
-
Section 19–19.4.6.1
BX
Rm
Branch indirect
-
Section 19–19.4.6.1
CMN
Rn, Rm
Compare Negative
N,Z,C,V
Section 19–19.4.5.4
CMP
Rn, <Rm|#imm>
Compare
N,Z,C,V
Section 19–19.4.5.4
CPSID
i
Change Processor State, Disable
Interrupts
-
Section 19–19.4.7.2
CPSIE
i
Change Processor State, Enable
Interrupts
-
Section 19–19.4.7.2
DMB
-
Data Memory Barrier
-
Section 19–19.4.7.3
DSB
-
Data Synchronization Barrier
-
Section 19–19.4.7.4
EORS
{Rd,} Rn, Rm
Exclusive OR
N,Z
Section 19–19.4.5.2
ISB
-
Instruction Synchronization Barrier
-
Section 19–19.4.7.5
LDM
Rn{!}, reglist
Load Multiple registers, increment after
-
Section 19–19.4.4.5
LDR
Rt, label
Load Register from PC-relative address -
Section 19–19.4.4
LDR
Rt, [Rn, <Rm|#imm>]
Load Register with word
-
Section 19–19.4.4
LDRB
Rt, [Rn, <Rm|#imm>]
Load Register with byte
-
Section 19–19.4.4
LDRH
Rt, [Rn, <Rm|#imm>]
Load Register with halfword
-
Section 19–19.4.4
LDRSB
Rt, [Rn, <Rm|#imm>]
Load Register with signed byte
-
Section 19–19.4.4
LDRSH
Rt, [Rn, <Rm|#imm>]
Load Register with signed halfword
-
Section 19–19.4.4
LSLS
{Rd,} Rn, <Rs|#imm>
Logical Shift Left
N,Z,C
Section 19–19.4.5.3
U
{Rd,} Rn, <Rs|#imm>
Logical Shift Right
N,Z,C
Section 19–19.4.5.3
MOV{S}
Rd, Rm
Move
N,Z
Section 19–19.4.5.5
MRS
Rd, spec_reg
Move to general register from special
register
-
Section 19–19.4.7.6
MSR
spec_reg, Rm
Move to special register from general
register
N,Z,C,V
Section 19–19.4.7.7
MULS
Rd, Rn, Rm
Multiply, 32-bit result
N,Z
Section 19–19.4.5.6
MVNS
Rd, Rm
Bitwise NOT
N,Z
Section 19–19.4.5.5
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Table 202. Cortex-M0 instructions
Mnemonic
Operands
Brief description
Flags
Reference
NOP
-
No Operation
-
Section 19–19.4.7.8
ORRS
{Rd,} Rn, Rm
Logical OR
N,Z
Section 19–19.4.5.2
POP
reglist
Pop registers from stack
-
Section 19–19.4.4.6
PUSH
reglist
Push registers onto stack
-
Section 19–19.4.4.6
REV
Rd, Rm
Byte-Reverse word
-
Section 19–19.4.5.7
REV16
Rd, Rm
Byte-Reverse packed halfwords
-
Section 19–19.4.5.7
REVSH
Rd, Rm
Byte-Reverse signed halfword
-
Section 19–19.4.5.7
RORS
{Rd,} Rn, Rs
Rotate Right
N,Z,C
Section 19–19.4.5.3
RSBS
{Rd,} Rn, #0
Reverse Subtract
N,Z,C,V
Section 19–19.4.5.1
SBCS
{Rd,} Rn, Rm
Subtract with Carry
N,Z,C,V
Section 19–19.4.5.1
SEV
-
Send Event
-
Section 19–19.4.7.9
STM
Rn!, reglist
Store Multiple registers, increment after
-
Section 19–19.4.4.5
STR
Rt, [Rn, <Rm|#imm>]
Store Register as word
-
Section 19–19.4.4
STRB
Rt, [Rn, <Rm|#imm>]
Store Register as byte
-
Section 19–19.4.4
STRH
Rt, [Rn, <Rm|#imm>]
Store Register as halfword
-
Section 19–19.4.4
SUB{S}
{Rd,} Rn, <Rm|#imm>
Subtract
N,Z,C,V
Section 19–19.4.5.1
SVC
#imm
Supervisor Call
-
Section 19–19.4.7.10
SXTB
Rd, Rm
Sign extend byte
-
Section 19–19.4.5.8
SXTH
Rd, Rm
Sign extend halfword
-
Section 19–19.4.5.8
TST
Rn, Rm
Logical AND based test
N,Z
Section 19–19.4.5.9
UXTB
Rd, Rm
Zero extend a byte
-
Section 19–19.4.5.8
UXTH
Rd, Rm
Zero extend a halfword
-
Section 19–19.4.5.8
WFE
-
Wait For Event
-
Section 19–19.4.7.11
WFI
-
Wait For Interrupt
-
Section 19–19.4.7.12
19.4.2 Intrinsic functions
ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section
describes intrinsic functions that can generate these instructions, provided by the CMSIS
and that might be provided by a C compiler. If a C compiler does not support an
appropriate intrinsic function, you might have to use inline assembler to access the
relevant instruction.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC
C code cannot directly access:
Table 203. CMSIS intrinsic functions to generate some Cortex-M0 instructions
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Instruction
CMSIS intrinsic function
CPSIE i
void __enable_irq(void)
CPSID i
void __disable_irq(void)
ISB
void __ISB(void)
DSB
void __DSB(void)
DMB
void __DMB(void)
NOP
void __NOP(void)
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Table 203. CMSIS intrinsic functions to generate some Cortex-M0 instructions
Instruction
CMSIS intrinsic function
REV
uint32_t __REV(uint32_t int value)
REV16
uint32_t __REV16(uint32_t int value)
REVSH
uint32_t __REVSH(uint32_t int value)
SEV
void __SEV(void)
WFE
void __WFE(void)
WFI
void __WFI(void)
The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions:
Table 204. insic functions to access the special registers
Special register
Access
CMSIS function
PRIMASK
Read
uint32_t __get_PRIMASK (void)
Write
void __set_PRIMASK (uint32_t value)
Read
uint32_t __get_CONTROL (void)
Write
void __set_CONTROL (uint32_t value)
Read
uint32_t __get_MSP (void)
Write
void __set_MSP (uint32_t TopOfMainStack)
Read
uint32_t __get_PSP (void)
Write
void __set_PSP (uint32_t TopOfProcStack)
CONTROL
MSP
PSP
19.4.3 About the instruction descriptions
The following sections give more information about using the instructions:
•
•
•
•
•
•
Section 19.4.3.1 “Operands”
Section 19.4.3.2 “Restrictions when using PC or SP”
Section 19.4.3.3 “Shift Operations”
Section 19.4.3.4 “Address alignment”
Section 19.4.3.5 “PC-relative expressions”
Section 19.4.3.6 “Conditional execution”.
19.4.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the other operands.
19.4.3.2 Restrictions when using PC or SP
Many instructions are unable to use, or have restrictions on whether you can use, the
Program Counter (PC) or Stack Pointer (SP) for the operands or destination register.
See instruction descriptions for more information.
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Remark: When you update the PC with a BX, BLX, or POP instruction, bit[0] of any
address must be 1 for correct execution. This is because this bit indicates the destination
instruction set, and the Cortex-M0 processor only supports Thumb instructions. When a
BL or BLX instruction writes the value of bit[0] into the LR it is automatically assigned the
value 1.
19.4.3.3 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of
bits, the shift length. Register shift can be performed directly by the instructions ASR,
LSR, LSL, and ROR and the result is written to a destination register.The permitted shift
lengths depend on the shift type and the instruction, see the individual instruction
description. If the shift length is 0, no shift occurs. Register shift operations update the
carry flag except when the specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag. In these descriptions, Rm is
the register containing the value to be shifted, and n is the shift length.
19.4.3.3.1
ASR
Arithmetic shift right by n bits moves the left-hand 32 -n bits of the register Rm, to the right
by n places, into the right-hand 32 -n bits of the result, and it copies the original bit[31] of
the register into the left-hand n bits of the result. See Figure 19–43.
You can use the ASR operation to divide the signed value in the register Rm by 2n, with
the result being rounded towards negative-infinity.
When the instruction is ASRS the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm.
Remark:
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm.
Carry
Flag
31
5 4 3 2 1 0
...
Fig 43. ASR #3
19.4.3.3.2
LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by
n places, into the right-hand 32 -n bits of the result, and it sets the left-hand n bits of the
result to 0. See Figure 44.
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You can use the LSR operation to divide the value in the register Rm by 2n, if the value is
regarded as an unsigned integer.
When the instruction is LSRS, the carry flag is updated to the last bit shifted out, bit[n-1],
of the register Rm.
Remark:
• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0.
Carry
Flag
0 0 0
31
5 4
3 2 1 0
...
Fig 44. LSR #3
19.4.3.3.3
LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n
places, into the left-hand 32-n bits of the result, and it sets the right-hand n bits of the
result to 0. See Figure 45.
You can use the LSL operation to multiply the value in the register Rm by 2n, if the value is
regarded as an unsigned integer or a two’s complement signed integer. Overflow can
occur without warning.
When the instruction is LSLS the carry flag is updated to the last bit shifted out, bit[32-n],
of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
Remark:
• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0.
0 0 0
31
Carry
Flag
5 4
3 2 1 0
...
Fig 45. LSL #3
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19.4.3.3.4
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result, and it moves the right-hand n bits of the
register into the left-hand n bits of the result. See Figure 19–46.
When the instruction is RORS the carry flag is updated to the last bit rotation, bit[n-1], of
the register Rm.
Remark:
• If n is 32, then the value of the result is same as the value in Rm, and if the carry flag
is updated, it is updated to bit[31] of Rm.
• ROR
with shift length, n, greater than 32 is the same as
ROR
with shift length n-32.
Carry
Flag
31
5 4
3 2 1 0
...
Fig 46. ROR #3
19.4.3.4 Address alignment
An aligned access is an operation where a word-aligned address is used for a word, or
multiple word access, or where a halfword-aligned address is used for a halfword access.
Byte accesses are always aligned.
There is no support for unaligned accesses on the Cortex-M0 processor. Any attempt to
perform an unaligned memory access operation results in a HardFault exception.
19.4.3.5 PC-relative expressions
A PC-relative expression or label is a symbol that represents the address of an instruction
or literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
Remark:
• For most instructions, the value of the PC is the address of the current instruction plus
4 bytes.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form [PC, #imm].
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19.4.3.6 Conditional execution
Most data processing instructions update the condition flags in the Application Program
Status Register (APSR) according to the result of the operation, see Section . Some
instructions update all flags, and some only update a subset. If a flag is not updated, the
original value is preserved. See the instruction descriptions for the flags they affect.
You can execute a conditional branch instruction, based on the condition flags set in
another instruction, either:
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
On the Cortex-M0 processor, conditional execution is available by using conditional
branches.
This section describes:
• Section 19.4.3.6.1 “The condition flags”
• Section 19.4.3.6.2 “Condition code suffixes”.
19.4.3.6.1
The condition flags
The APSR contains the following condition flags:
N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z — Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C — Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V — Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR see Section 19–19.3.1.3.5.
A carry occurs:
• if the result of an addition is greater than or equal to 232
• if the result of a subtraction is positive or zero
• as the result of a shift or rotate instruction.
Overflow occurs when the sign of the result, in bit[31], does not match the sign of the
result had the operation been performed at infinite precision, for example:
•
•
•
•
if adding two negative values results in a positive value
if adding two positive values results in a negative value
if subtracting a positive value from a negative value generates a positive value
if subtracting a negative value from a positive value generates a negative value.
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except
that the result is discarded. See the instruction descriptions for more information.
19.4.3.6.2
Condition code suffixes
Conditional branch is shown in syntax descriptions as B{cond}. A branch instruction with a
condition code is only taken if the condition code flags in the APSR meet the specified
condition, otherwise the branch instruction is ignored. shows the condition codes to use.
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Table 205 also shows the relationship between condition code suffixes and the N, Z, C,
and V flags.
Table 205. Condition code suffixes
Suffix
Flags
Meaning
EQ
Z=1
Equal, last flag setting result was zero
NE
Z=0
Not equal, last flag setting result was non-zero
CS or HS
C=1
Higher or same, unsigned
CC or LO
C=0
Lower, unsigned
MI
N=1
Negative
PL
N=0
Positive or zero
VS
V=1
Overflow
VC
V=0
No overflow
HI
C = 1 and Z = 0
Higher, unsigned
LS
C = 0 or Z = 1
Lower or same, unsigned
GE
N=V
Greater than or equal, signed
LT
N != V
Less than, signed
GT
Z = 0 and N = V
Greater than, signed
LE
Z = 1 and N != V
Less than or equal, signed
AL
Can have any value
Always. This is the default when no suffix is specified.
19.4.4 Memory access instructions
Table 206 shows the memory access instructions:
Table 206. Access instructions
Mnemonic
Brief description
See
LDR{type}
Load Register using register offset
Section 19–19.4.4.
3
LDR
Load Register from PC-relative address
Section 19–19.4.4.
4
POP
Pop registers from stack
Section 19–19.4.4.
6
PUSH
Push registers onto stack
Section 19–19.4.4.
6
STM
Store Multiple registers
Section 19–19.4.4.
5
STR{type}
Store Register using immediate offset
Section 19–19.4.4.
2
STR{type}
Store Register using register offset
Section 19–19.4.4.
3
19.4.4.1 ADR
Generates a PC-relative address.
19.4.4.1.1
Syntax
ADR Rd, label
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where:
Rd is the destination register.
label is a PC-relative expression. See Section 19–19.4.3.5.
19.4.4.1.2
Operation
ADR generates an address by adding an immediate value to the PC, and writes the result
to the destination register.
ADR facilitates the generation of position-independent code, because the address is
PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure
that bit[0] of the address you generate is set to 1 for correct execution.
19.4.4.1.3
Restrictions
In this instruction Rd must specify R0-R7. The data-value addressed must be word
aligned and within 1020 bytes of the current PC.
19.4.4.1.4
Condition flags
This instruction does not change the flags.
19.4.4.1.5
Examples
ADR
R1, TextMessage
; Write address value of a location labelled as
; TextMessage to R1
ADR
R3, [PC,#996]
; Set R3 to value of PC + 996.
19.4.4.2 LDR and STR, immediate offset
Load and Store with immediate offset.
19.4.4.2.1
Syntax
LDR Rt, [<Rn | SP> {, #imm}]
LDR<B|H> Rt, [Rn {, #imm}]
STR Rt, [<Rn | SP>, {,#imm}]
STR<B|H> Rt, [Rn {,#imm}]
where:
Rt is the register to load or store.
Rn is the register on which the memory address is based.
imm is an offset from Rn. If imm is omitted, it is assumed to be zero.
19.4.4.2.2
Operation
LDR, LDRB and LDRH instructions load the register specified by Rt with either a word,
byte or halfword data value from memory. Sizes less than word are zero extended to
32-bits before being written to the register specified by Rt.
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STR, STRB and STRH instructions store the word, least-significant byte or lower halfword
contained in the single register specified by Rt in to memory. The memory address to load
from or store to is the sum of the value in the register specified by either Rn or SP and the
immediate value imm.
19.4.4.2.3
Restrictions
In these instructions:
• Rt and Rn must only specify R0-R7.
• imm must be between:
– 0 and 1020 and an integer multiple of four for LDR and STR
using SP as the base register
– 0 and 124 and an integer multiple of four for LDR and STR
using R0-R7 as the base register
– 0 and 62 and an integer multiple of two for LDRH and STRH
– 0 and 31 for LDRB and STRB.
• The computed address must be divisible by the number of bytes in the transaction,
see Section 19–19.4.3.4.
19.4.4.2.4
Condition flags
These instructions do not change the flags.
19.4.4.2.5
Examples
LDR
STR
R4, [R7
; Loads R4 from the address in R7.
R2, [R0,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-1020.
19.4.4.3 LDR and STR, register offset
Load and Store with register offset.
19.4.4.3.1
Syntax
LDR Rt, [Rn, Rm]
LDR<B|H> Rt, [Rn, Rm]
LDR<SB|SH> Rt, [Rn, Rm]
STR Rt, [Rn, Rm]
STR<B|H> Rt, [Rn, Rm]
where:
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
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19.4.4.3.2
Operation
LDR, LDRB, U, LDRSB and LDRSH load the register specified by Rt with either a word,
zero extended byte, zero extended halfword, sign extended byte or sign extended
halfword value from memory.
STR, STRB and STRH store the word, least-significant byte or lower halfword contained
in the single register specified by Rt into memory.
The memory address to load from or store to is the sum of the values in the registers
specified by Rn and Rm.
19.4.4.3.3
Restrictions
In these instructions:
• Rt, Rn, and Rm must only specify R0-R7.
• the computed memory address must be divisible by the number of bytes in the load or
store, see Section 19–19.4.3.4.
19.4.4.3.4
Condition flags
These instructions do not change the flags.
19.4.4.3.5
Examples
STR
R0, [R5, R1]
LDRSH R1, [R2, R3]
; Store value of R0 into an address equal to
; sum of R5 and R1
; Load a halfword from the memory address
; specified by (R2 + R3), sign extend to 32-bits
; and write to R1.
19.4.4.4 LDR, PC-relative
Load register (literal) from memory.
19.4.4.4.1
Syntax
LDR Rt, label
where:
Rt is the register to load.
label is a PC-relative expression. See Section 19–19.4.3.5.
19.4.4.4.2
Operation
Loads the register specified by Rt from the word in memory specified by label.
19.4.4.4.3
Restrictions
In these instructions, label must be within 1020 bytes of the current PC and word aligned.
19.4.4.4.4
Condition flags
These instructions do not change the flags.
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19.4.4.4.5
Examples
LDR
R0, LookUpTable
; Load R0 with a word of data from an address
; labelled as LookUpTable.
LDR
R3, [PC, #100]
; Load R3 with memory word at (PC + 100).
19.4.4.5 LDM and STM
Load and Store Multiple registers.
19.4.4.5.1
Syntax
LDM Rn{!}, reglist
STM Rn!, reglist
where:
Rn is the register on which the memory addresses are based.
! writeback suffix.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can
contain register ranges. It must be comma separated if it contains more than one
register or register range, see Section 19–19.4.4.5.5.
LDMIA and LDMFD are synonyms for LDM. LDMIA refers to the base register being
Incremented After each access. LDMFD refers to its use for popping data from Full
Descending stacks.
STMIA and STMEA are synonyms for STM. STMIA refers to the base register being
Incremented After each access. STMEA refers to its use for pushing data onto Empty
Ascending stacks.
19.4.4.5.2
Operation
LDM instructions load the registers in reglist with word values from memory addresses
based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses
based on Rn.
The memory addresses used for the accesses are at 4-byte intervals ranging from the
value in the register specified by Rn to the value in the register specified by Rn + 4 * (n-1),
where n is the number of registers in reglist. The accesses happens in order of increasing
register numbers, with the lowest numbered register using the lowest memory address
and the highest number register using the highest memory address. If the writeback suffix
is specified, the value in the register specified by Rn + 4 *n is written back to the register
specified by Rn.
19.4.4.5.3
Restrictions
In these instructions:
• reglist and Rn are limited to R0-R7.
• the writeback suffix must always be used unless the instruction is an LDM where
reglist also contains Rn, in which case the writeback suffix must not be used.
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• the value in the register specified by Rn must be word aligned. See
Section 19–19.4.3.4 for more information.
• for STM, if Rn appears in reglist, then it must be the first register in the list.
19.4.4.5.4
Condition flags
These instructions do not change the flags.
19.4.4.5.5
Examples
LDM
19.4.4.5.6
R0,{R0,R3,R4}
; LDMIA is a synonym for LDM
STMIA R1!,{R2-R4,R6}
Incorrect examples
STM
R5!,{R4,R5,R6} ; Value stored for R5 is unpredictable
LDM
R2,{}
; There must be at least one register in the list
19.4.4.6 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
19.4.4.6.1
Syntax
PUSH reglist
POP reglist
where:
reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges.
It must be comma separated if it contains more than one register or register range.
19.4.4.6.2
Operation
PUSH stores registers on the stack, with the lowest numbered register using the lowest
memory address and the highest numbered register using the highest memory address.
POP loads registers from the stack, with the lowest numbered register using the lowest
memory address and the highest numbered register using the highest memory address.
PUSH uses the value in the SP register minus four as the highest memory address,
POP uses the value in the SP register as the lowest memory address, implementing a
full-descending stack. On completion,
PUSH updates the SP register to point to the location of the lowest store value,
POP updates the SP register to point to the location above the highest location loaded.
If a POP instruction includes PC in its reglist, a branch to this location is performed when
the POP instruction has completed. Bit[0] of the value read for the PC is used to update
the APSR T-bit. This bit must be 1 to ensure correct operation.
19.4.4.6.3
Restrictions
In these instructions:
• reglist must use only R0-R7.
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• The exception is LR for a PUSH and PC for a POP.
19.4.4.6.4
Condition flags
These instructions do not change the flags.
19.4.4.6.5
Examples
PUSH
{R0,R4-R7}
; Push R0,R4,R5,R6,R7 onto the stack
PUSH
{R2,LR}
; Push R2 and the link-register onto the stack
POP
{R0,R6,PC}
; Pop r0,r6 and PC from the stack, then branch to
; the new PC.
19.4.5 General data processing instructions
Table 207 shows the data processing instructions:
Table 207. Data processing instructions
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Mnemonic
Brief description
See
ADCS
Add with Carry
Section 19–19.4.5.1
ADD{S}
Add
Section 19–19.4.5.1
ANDS
Logical AND
Section 19–19.4.5.2
ASRS
Arithmetic Shift Right
Section 19–19.4.5.3
BICS
Bit Clear
Section 19–19.4.5.2
CMN
Compare Negative
Section 19–19.4.5.4
CMP
Compare
Section 19–19.4.5.4
EORS
Exclusive OR
Section 19–19.4.5.2
LSLS
Logical Shift Left
Section 19–19.4.5.3
LSRS
Logical Shift Right
Section 19–19.4.5.3
MOV{S}
Move
Section 19–19.4.5.5
MULS
Multiply
Section 19–19.4.5.6
MVNS
Move NOT
Section 19–19.4.5.5
ORRS
Logical OR
Section 19–19.4.5.2
REV
Reverse byte order in a word
Section 19–19.4.5.7
REV16
Reverse byte order in each halfword
Section 19–19.4.5.7
REVSH
Reverse byte order in bottom halfword Section 19–19.4.5.7
and sign extend
RORS
Rotate Right
Section 19–19.4.5.3
RSBS
Reverse Subtract
Section 19–19.4.5.1
SBCS
Subtract with Carry
Section 19–19.4.5.1
SUBS
Subtract
Section 19–19.4.5.1
SXTB
Sign extend a byte
Section 19–19.4.5.8
SXTH
Sign extend a halfword
Section 19–19.4.5.8
UXTB
Zero extend a byte
Section 19–19.4.5.8
UXTH
Zero extend a halfword
Section 19–19.4.5.8
TST
Test
Section 19–19.4.5.9
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19.4.5.1 ADC, ADD, RSB, SBC, and SUB
Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.
19.4.5.1.1
Syntax
ADCS {Rd,} Rn, Rm
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS {Rd,} Rn, Rm, #0
SBCS {Rd,} Rn, Rm
SUB{S} {Rd,} Rn,
<Rm|#imm>
Where:
S causes an ADD or SUB instruction to update flags
Rd specifies the result register
Rn specifies the first source register
Rm specifies the second source register
imm specifies a constant immediate value.
When the optional Rd register specifier is omitted, it is assumed to take the same value as
Rn, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.
19.4.5.1.2
Operation
The ADCS instruction adds the value in Rn to the value in Rm, adding a further one if the
carry flag is set, places the result in the register specified by Rd and updates the N, Z, C,
and V flags.
The ADD instruction adds the value in Rn to the value in Rm or an immediate value
specified by imm and places the result in the register specified by Rd.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C
and V flags.
The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic
negative of the value, and places the result in the register specified by Rd and updates the
N, Z, C and V flags.
The SBCS instruction subtracts the value of Rm from the value in Rn, deducts a further
one if the carry flag is set. It places the result in the register specified by Rd and updates
the N, Z, C and V flags.
The SUB instruction subtracts the value in Rm or the immediate specified by imm. It
places the result in the register specified by Rd.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C
and V flags.
Use ADC and SBC to synthesize multiword arithmetic, see Section 19.4.5.1.4.
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
See also Section 19–19.4.4.1.
19.4.5.1.3
Restrictions
Table 208 lists the legal combinations of register specifiers and immediate values that can
be used with each instruction.
Table 208. ADC, ADD, RSB, SBC and SUB operand restrictions
Instruction Rd
Rn
Rm
imm
Restrictions
ADCS
R0-R7
R0-R7
R0-R7
-
Rd and Rn must specify the same register.
ADD
R0-R15
R0-R15
R0-PC
-
Rd and Rn must specify the same register.
R0-R7
SP or PC
-
0-1020
Immediate value must be an integer multiple of four.
SP
SP
-
0-508
Immediate value must be an integer multiple of four.
R0-R7
R0-R7
-
0-7
-
R0-R7
R0-R7
-
0-255
Rd and Rn must specify the same register.
R0-R7
R0-R7
R0-R7
-
-
RSBS
R0-R7
R0-R7
-
-
-
SBCS
R0-R7
R0-R7
R0-R7
-
Rd and Rn must specify the same register.
SUB
SP
SP
-
0-508
Immediate value must be an integer multiple of four.
Rn and Rm must not both specify PC.
ADDS
SUBS
R0-R7
R0-R7
-
0-7
-
R0-R7
R0-R7
-
0-255
Rd and Rn must specify the same register.
R0-R7
R0-R7
R0-R7
-
-
19.4.5.1.4
Examples
The following shows two instructions that add a 64-bit integer contained in R0 and R1 to
another 64-bit integer contained in R2 and R3, and place the result in R0 and R1.
64-bit addition:
ADDS
R0, R0, R2
; add the least significant words
ADCS
R1, R1, R3
; add the most significant words with carry
Multiword values do not have to use consecutive registers. The following shows
instructions that subtract a 96-bit integer contained in R1, R2, and R3 from another
contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.
96-bit subtraction:
SUBS
R4, R4, R1
; subtract the least significant words
SBCS
R5, R5, R2
; subtract the middle words with carry
SBCS
R6, R6, R3
; subtract the most significant words with carry
The following shows the RSBS instruction used to perform a 1's complement of a single
register.
Arithmetic negation:
RSBS
R7, R7, #0
; subtract R7 from zero
19.4.5.2 AND, ORR, EOR, and BIC
Logical AND, OR, Exclusive OR, and Bit Clear.
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
19.4.5.2.1
Syntax
ANDS {Rd,} Rn, Rm
ORRS {Rd,} Rn, Rm
EORS {Rd,} Rn, Rm
BICS {Rd,} Rn, Rm
where:
Rd is the destination register.
Rn is the register holding the first operand and is the same as the destination register.
Rm second register.
19.4.5.2.2
Operation
The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive
OR operations on the values in Rn and Rm.
The BIC instruction performs an AND operation on the bits in Rn with the logical negation
of the corresponding bits in the value of Rm.
The condition code flags are updated on the result of the operation, see
Section 19.4.3.6.1.
19.4.5.2.3
Restrictions
In these instructions, Rd, Rn, and Rm must only specify R0-R7.
19.4.5.2.4
Condition flags
These instructions:
• update the N and Z flags according to the result
• do not affect the C or V flag.
19.4.5.2.5
Examples
ANDS
R2, R2, R1
ORRS
R2, R2,
ANDS
R5, R5,
EORS
R7, R7,
BICS
R0, R0,
R5
R8
R6
R1
19.4.5.3 ASR, LSL, LSR, and ROR
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.
19.4.5.3.1
Syntax
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
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LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
where:
Rd is the destination register. If Rd is omitted, it is assumed to take the same value as
Rm.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm.
imm is the shift length.
The range of shift length depends on the instruction:
ASR — shift length from 1 to 32
LSL — shift length from 0 to 31
LSR — shift length from 1 to 32.
Remark: MOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.
19.4.5.3.2
Operation
ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left,
logical-shift-right or a right-rotation of the bits in the register Rm by the number of places
specified by the immediate imm or the value in the least-significant byte of the register
specified by Rs.
For details on what result is generated by the different instructions, see
Section 19–19.4.3.3.
19.4.5.3.3
Restrictions
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register.
19.4.5.3.4
Condition flags
These instructions update the N and Z flags according to the result.
The C flag is updated to the last bit shifted out, except when the shift length is 0, see
Section 19–19.4.3.3. The V flag is left unmodified.
19.4.5.3.5
Examples
ASRS
R7, R5, #9 ; Arithmetic shift right by 9 bits
LSLS
R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSRS
R4, R5, #6 ; Logical shift right by 6 bits
RORS
R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.
19.4.5.4 CMP and CMN
Compare and Compare Negative.
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
19.4.5.4.1
Syntax
CMN Rn, Rm
CMP Rn, #imm
CMP Rn, Rm
where:
Rn is the register holding the first operand.
Rm is the register to compare with.
imm is the immediate value to compare with.
19.4.5.4.2
Operation
These instructions compare the value in a register with either the value in another register
or an immediate value. They update the condition flags on the result, but do not write the
result to a register.
The CMP instruction subtracts either the value in the register specified by Rm, or the
immediate imm from the value in Rn and updates the flags. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Rm to the value in Rn and updates the flags. This
is the same as an ADDS instruction, except that the result is discarded.
19.4.5.4.3
Restrictions
For the:
• CMN
instruction Rn, and Rm must only specify R0-R7.
• CMP instruction:
– Rn and Rm can specify R0-R14
– immediate must be in the range 0-255.
19.4.5.4.4
Condition flags
These instructions update the N, Z, C and V flags according to the result.
19.4.5.4.5
Examples
CMP
R2, R9
CMN
R0, R2
19.4.5.5 MOV and MVN
Move and Move NOT.
19.4.5.5.1
Syntax
MOV{S} Rd, Rm
MOVS Rd, #imm
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
MVNS Rd, Rm
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see Section 19–19.4.3.6.
Rd is the destination register.
Rm is a register.
imm is any value in the range 0-255.
19.4.5.5.2
Operation
The MOV instruction copies the value of Rm into Rd.
The MOVS instruction performs the same operation as the MOV instruction, but also
updates the N and Z flags.
The MVNS instruction takes the value of Rm, performs a bitwise logical negate operation
on the value, and places the result into Rd.
19.4.5.5.3
Restrictions
In these instructions, Rd, and Rm must only specify R0-R7.
When Rd is the PC in a MOV instruction:
• Bit[0] of the result is discarded.
• A branch occurs to the address created by forcing bit[0] of the result to 0. The T-bit
remains unmodified.
Remark: Though it is possible to use MOV as a branch instruction, ARM strongly
recommends the use of a BX or BLX instruction to branch for software portability.
19.4.5.5.4
Condition flags
If S is specified, these instructions:
• update the N and Z flags according to the result
• do not affect the C or V flags.
19.4.5.5.5
Example
MOVS R0,
MOVS
MOV
MOVS
MOV
MVNS
#0x000B
R1, #0x0
R10, R12
R3, #23
R8, SP
R2, R0
; Write value of 0x000B to R0, flags get updated
; Write value of zero to R1, flags are updated
; Write value in R12 to R10, flags are not updated
; Write value of 23 to R3
; Write value of stack pointer to R8
; Write inverse of R0 to the R2 and update flags
19.4.5.6 MULS
Multiply using 32-bit operands, and producing a 32-bit result.
19.4.5.6.1
Syntax
MULS Rd, Rn, Rm
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
where:
Rd is the destination register.
Rn, Rm are registers holding the values to be multiplied.
19.4.5.6.2
Operation
The MUL instruction multiplies the values in the registers specified by Rn and Rm, and
places the least significant 32 bits of the result in Rd. The condition code flags are
updated on the result of the operation, see Section 19–19.4.3.6.
The results of this instruction does not depend on whether the operands are signed or
unsigned.
19.4.5.6.3
Restrictions
In this instruction:
• Rd, Rn, and Rm must only specify R0-R7
• Rd must be the same as Rm.
19.4.5.6.4
Condition flags
This instruction:
• updates the N and Z flags according to the result
• does not affect the C or V flags.
19.4.5.6.5
Examples
MULS
R0, R2, R0
; Multiply with flag update, R0 = R0 x R2
19.4.5.7 REV, REV16, and REVSH
Reverse bytes.
19.4.5.7.1
Syntax
REV Rd, Rn
REV16 Rd, Rn
REVSH Rd, Rn
where:
Rd is the destination register.
Rn is the source register.
19.4.5.7.2
Operation
Use these instructions to change endianness of data:
REV — converts 32-bit big-endian data into little-endian data or 32-bit little-endian data
into big-endian data.
REV16 — converts two packed 16-bit big-endian data into little-endian data or two packed
16-bit little-endian data into big-endian data.
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REVSH — converts 16-bit signed big-endian data into 32-bit signed little-endian data or
16-bit signed little-endian data into 32-bit signed big-endian data.
19.4.5.7.3
Restrictions
In these instructions, Rd, and Rn must only specify R0-R7.
19.4.5.7.4
Condition flags
These instructions do not change the flags.
19.4.5.7.5
Examples
REV
R3, R7 ; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5 ; Reverse signed halfword
19.4.5.8 SXT and UXT
Sign extend and Zero extend.
19.4.5.8.1
Syntax
SXTB Rd, Rm
SXTH Rd, Rm
UXTB Rd, Rm
UXTH Rd, Rm
where:
Rd is the destination register.
Rm is the register holding the value to be extended.
19.4.5.8.2
Operation
These instructions extract bits from the resulting value:
•
•
•
•
19.4.5.8.3
SXTB extracts bits[7:0] and sign extends to 32 bits
UXTB extracts bits[7:0] and zero extends to 32 bits
SXTH extracts bits[15:0] and sign extends to 32 bits
UXTH extracts bits[15:0] and zero extends to 32 bits.
Restrictions
In these instructions, Rd and Rm must only specify R0-R7.
19.4.5.8.4
Condition flags
These instructions do not affect the flags.
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
19.4.5.8.5
Examples
SXTH R4, R6
UXTB R3, R1
; Obtain the lower halfword of the
; value in R6 and then sign extend to
; 32 bits and write the result to R4.
; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3
19.4.5.9 TST
Test bits.
19.4.5.9.1
Syntax
TST Rn, Rm
where:
Rn is the register holding the first operand.
Rm the register to test against.
19.4.5.9.2
Operation
This instruction tests the value in a register against another register. It updates the
condition flags based on the result, but does not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value in
Rm. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with a register that has that bit
set to 1 and all other bits cleared to 0.
19.4.5.9.3
Restrictions
In these instructions, Rn and Rm must only specify R0-R7.
19.4.5.9.4
Condition flags
This instruction:
• updates the N and Z flags according to the result
• does not affect the C or V flags.
19.4.5.9.5
Examples
TST
R0, R1 ; Perform bitwise AND of R0 value and R1 value,
; condition code flags are updated but result is discarded
19.4.6 Branch and control instructions
Table 209 shows the branch and control instructions:
Table 209. Branch and control instructions
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Mnemonic
Brief description
See
B{cc}
Branch {conditionally}
Section 19–19.4.6.1
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
Table 209. Branch and control instructions
Mnemonic
Brief description
See
BL
Branch with Link
Section 19–19.4.6.1
BLX
Branch indirect with Link
Section 19–19.4.6.1
BX
Branch indirect
Section 19–19.4.6.1
19.4.6.1 B, BL, BX, and BLX
Branch instructions.
19.4.6.1.1
Syntax
B{cond} label
BL label
BX Rm
BLX Rm
where:
cond is an optional condition code, see Section 19–19.4.3.6.
label is a PC-relative expression. See Section 19–19.4.3.5.
Rm is a register providing the address to branch to.
19.4.6.1.2
Operation
All these instructions cause a branch to the address indicated by label or contained in the
register specified by Rm. In addition:
• The BL and BLX instructions write the address of the next instruction to LR, the link
register R14.
• The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.
BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is
suitable for use by a subsequent POP {PC} or BX instruction to perform a successful
return branch.
Table 210 shows the ranges for the various branch instructions.
Table 210. Branch ranges
Instruction
19.4.6.1.3
Branch range
B label
−2 KB to +2 KB
Bcond label
−256 bytes to +254 bytes
BL label
−16 MB to +16 MB
BX Rm
Any value in register
BLX Rm
Any value in register
Restrictions
In these instructions:
• Do not use SP or PC in the BX or BLX instruction.
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• For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update
the EPSR T-bit and is discarded from the target address.
Remark: Bcond is the only conditional instruction on the Cortex-M0 processor.
19.4.6.1.4
Condition flags
These instructions do not change the flags.
19.4.6.1.5
Examples
B
loopA ; Branch to loopA
BL
funC ; Branch with link (Call) to function funC, return address
; stored in LR
BX
LR
; Return from function call
BLX
R0
; Branch with link and exchange (Call) to a address stored
; in R0
BEQ
labelD ; Conditionally branch to labelD if last flag setting
; instruction set the Z flag, else do not branch.
19.4.7 Miscellaneous instructions
Table 211 shows the remaining Cortex-M0 instructions:
Table 211. Miscellaneous instructions
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Mnemonic
Brief description
See
BKPT
Breakpoint
Section 19–19.4.7.
1
CPSID
Change Processor State, Disable Interrupts
Section 19–19.4.7.
2
CPSIE
Change Processor State, Enable Interrupts
Section 19–19.4.7.
2
DMB
Data Memory Barrier
Section 19–19.4.7.
3
DSB
Data Synchronization Barrier
Section 19–19.4.7.
4
ISB
Instruction Synchronization Barrier
Section 19–19.4.7.
5
MRS
Move from special register to register
Section 19–19.4.7.
6
MSR
Move from register to special register
Section 19–19.4.7.
7
NOP
No Operation
Section 19–19.4.7.
8
SEV
Send Event
Section 19–19.4.7.
9
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
Table 211. Miscellaneous instructions
Mnemonic
Brief description
See
SVC
Supervisor Call
Section 19–19.4.7.
10
WFE
Wait For Event
Section 19–19.4.7.
11
WFI
Wait For Interrupt
Section 19–19.4.7.
12
19.4.7.1 BKPT
Breakpoint.
19.4.7.1.1
Syntax
BKPT #imm
where:
imm is an integer in the range 0-255.
19.4.7.1.2
Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use
this to investigate system state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional
information about the breakpoint.
The processor might also produce a HardFault or go in to lockup if a debugger is not
attached when a BKPT instruction is executed. See Section 19–19.3.4.1 for more
information.
19.4.7.1.3
Restrictions
There are no restrictions.
19.4.7.1.4
Condition flags
This instruction does not change the flags.
19.4.7.1.5
Examples
BKPT #0
; Breakpoint with immediate value set to 0x0.
19.4.7.2 CPS
Change Processor State.
19.4.7.2.1
Syntax
CPSID i
CPSIE i
19.4.7.2.2
Operation
CPS changes the PRIMASK special register values. CPSID causes interrupts to be
disabled by setting PRIMASK. CPSIE cause interrupts to be enabled by clearing
PRIMASK.See Section 19–19.3.1.3.6 for more information about these registers.
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19.4.7.2.3
Restrictions
There are no restrictions.
19.4.7.2.4
Condition flags
This instruction does not change the condition flags.
19.4.7.2.5
Examples
CPSID i ; Disable all interrupts except NMI (set PRIMASK)
CPSIE i ; Enable interrupts (clear PRIMASK)
19.4.7.3 DMB
Data Memory Barrier.
19.4.7.3.1
Syntax
DMB
19.4.7.3.2
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear in program order before the DMB instruction are observed before any explicit
memory accesses that appear in program order after the DMB instruction. DMB does not
affect the ordering of instructions that do not access memory.
19.4.7.3.3
Restrictions
There are no restrictions.
19.4.7.3.4
Condition flags
This instruction does not change the flags.
19.4.7.3.5
Examples
DMB ; Data Memory Barrier
19.4.7.4 DSB
Data Synchronization Barrier.
19.4.7.4.1
Syntax
DSB
19.4.7.4.2
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after
the DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.
19.4.7.4.3
Restrictions
There are no restrictions.
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19.4.7.4.4
Condition flags
This instruction does not change the flags.
19.4.7.4.5
Examples
DSB ; Data Synchronisation Barrier
19.4.7.5 ISB
Instruction Synchronization Barrier.
19.4.7.5.1
Syntax
ISB
19.4.7.5.2
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
19.4.7.5.3
Restrictions
There are no restrictions.
19.4.7.5.4
Condition flags
This instruction does not change the flags.
19.4.7.5.5
Examples
ISB ; Instruction Synchronisation Barrier
19.4.7.6 MRS
Move the contents of a special register to a general-purpose register.
19.4.7.6.1
Syntax
MRS Rd, spec_reg
where:
Rd is the general-purpose destination register.
spec_reg is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
19.4.7.6.2
Operation
MRS stores the contents of a special-purpose register to a general-purpose register. The
MRS instruction can be combined with the MR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See Section 19–19.4.7.7.
19.4.7.6.3
Restrictions
In this instruction, Rd must not be SP or PC.
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19.4.7.6.4
Condition flags
This instruction does not change the flags.
19.4.7.6.5
Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
19.4.7.7 MSR
Move the contents of a general-purpose register into the specified special register.
19.4.7.7.1
Syntax
MSR spec_reg, Rn
where:
Rn is the general-purpose source register.
spec_reg is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
19.4.7.7.2
Operation
MSR updates one of the special registers with the value from the register specified by Rn.
See Section 19–19.4.7.6.
19.4.7.7.3
Restrictions
In this instruction, Rn must not be SP and must not be PC.
19.4.7.7.4
Condition flags
This instruction updates the flags explicitly based on the value in Rn.
19.4.7.7.5
Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
19.4.7.8 NOP
No Operation.
19.4.7.8.1
Syntax
NOP
19.4.7.8.2
Operation
NOP performs no operation and is not guaranteed to be time consuming. The processor
might remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the subsequent instructions on a 64-bit
boundary.
19.4.7.8.3
Restrictions
There are no restrictions.
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19.4.7.8.4
Condition flags
This instruction does not change the flags.
19.4.7.8.5
Examples
NOP ; No operation
19.4.7.9 SEV
Send Event.
19.4.7.9.1
Syntax
SEV
19.4.7.9.2
Operation
SEV causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register, see Section 19–19.3.5.
See also Section 19–19.4.7.11.
19.4.7.9.3
Restrictions
There are no restrictions.
19.4.7.9.4
Condition flags
This instruction does not change the flags.
19.4.7.9.5
Examples
SEV ; Send Event
19.4.7.10 SVC
Supervisor Call.
19.4.7.10.1
Syntax
SVC #imm
where:
imm is an integer in the range 0-255.
19.4.7.10.2
Operation
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to
determine what service is being requested.
19.4.7.10.3
Restrictions
There are no restrictions.
19.4.7.10.4
Condition flags
This instruction does not change the flags.
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19.4.7.10.5
Examples
SVC #0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
19.4.7.11 WFE
Wait For Event.
Remark: The WFE instruction is not implemented on the LPC1102.
19.4.7.11.1
Syntax
WFE
19.4.7.11.2
Operation
If the event register is 0, WFE suspends execution until one of the following events
occurs:
• an exception, unless masked by the exception mask registers or the current priority
level
• an exception enters the Pending state, if SEVONPEND in the System Control
Register is set
• a Debug Entry request, if debug is enabled
• an event signaled by a peripheral or another processor in a multiprocessor system
using the SEV instruction.
If the event register is 1, WFE clears it to 0 and completes immediately.
For more information see Section 19–19.3.5.
Remark: WFE is intended for power saving only. When writing software assume that WFE
might behave as NOP.
19.4.7.11.3
Restrictions
There are no restrictions.
19.4.7.11.4
Condition flags
This instruction does not change the flags.
19.4.7.11.5
Examples
WFE ; Wait for event
19.4.7.12 WFI
Wait for Interrupt.
19.4.7.12.1
Syntax
WFI
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19.4.7.12.2
Operation
WFI
suspends execution until one of the following events occurs:
• an exception
• an interrupt becomes pending which would preempt if PRIMASK was clear
• a Debug Entry request, regardless of whether debug is enabled.
Remark: WFI is intended for power saving only. When writing software assume that WFI
might behave as a NOP operation.
19.4.7.12.3
Restrictions
There are no restrictions.
19.4.7.12.4
Condition flags
This instruction does not change the flags.
19.4.7.12.5
Examples
WFI ; Wait for interrupt
19.5 Peripherals
19.5.1 About the ARM Cortex-M0
The address map of the Private peripheral bus (PPB) is:
Table 212. Core peripheral register regions
Address
Core peripheral
Description
0xE000E008-0xE000E00F
System Control Block
Table 19–221
0xE000E010-0xE000E01F
System timer
Table 19–230
0xE000E100-0xE000E4EF
Nested Vectored Interrupt Controller
Table 19–213
0xE000ED00-0xE000ED3F
System Control Block
Table 19–221
0xE000EF00-0xE000EF03
Nested Vectored Interrupt Controller
Table 19–213
In register descriptions, the register type is described as follows:
RW — Read and write.
RO — Read-only.
WO — Write-only.
19.5.2 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the
registers it uses. The NVIC supports:
• 32 interrupts.
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• A programmable priority level of 0-3 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
• Level and pulse detection of interrupt signals.
• Interrupt tail-chaining.
• An external Non-maskable interrupt (NMI). The NMI is not implemented on the
LPC1102.
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Table 213. NVIC register summary
Address
Name
Type
Reset value
Description
0xE000E100
ISER
RW
0x00000000
Section 19–19.5.2.2
0xE000E180
ICER
RW
0x00000000
Section 19–19.5.2.3
0xE000E200
ISPR
RW
0x00000000
Section 19–19.5.2.4
0xE000E280
ICPR
RW
0x00000000
Section 19–19.5.2.5
RW
0x00000000
Section 19–19.5.2.6
0xE000E400-0x IPR0-7
E000E41C
19.5.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
CMSIS functions enable software portability between different Cortex-M profile
processors.
To access the NVIC registers when using CMSIS, use the following functions:
Table 214. CMISIS access NVIC functions
CMSIS function
Description
void NVIC_EnableIRQ(IRQn_Type IRQn)[1]
Enables an interrupt or exception.
IRQn)[1]
Disables an interrupt or exception.
void NVIC_DisableIRQ(IRQn_Type
void NVIC_SetPendingIRQ(IRQn_Type
IRQn)[1]
void NVIC_ClearPendingIRQ(IRQn_Type
Sets the pending status of interrupt or exception to 1.
IRQn)[1]
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)[1]
Clears the pending status of interrupt or exception to 0.
Reads the pending status of interrupt or exception.
This function returns non-zero value if the pending status is set
to 1.
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)[1] Sets the priority of an interrupt or exception with configurable
priority level to 1.
uint32_t NVIC_GetPriority(IRQn_Type IRQn)[1]
[1]
Reads the priority of an interrupt or exception with configurable
priority level. This function returns the current priority level.
The input parameter IRQn is the IRQ number, see Table 200 for more information.
19.5.2.2 Interrupt Set-enable Register
The ISER enables interrupts, and shows which interrupts are enabled. See the register
summary in Table 213 for the register attributes.
The bit assignments are:
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Table 215. ISER bit assignments
Bits
Name
Function
[31:0]
SETENA
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
19.5.2.3 Interrupt Clear-enable Register
The ICER disables interrupts, and show which interrupts are enabled. See the register
summary in Table 19–213 for the register attributes.
The bit assignments are:
Table 216. ICER bit assignments
Bits
Name
Function
[31:0]
CLRENA
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
19.5.2.4 Interrupt Set-pending Register
The ISPR forces interrupts into the pending state, and shows which interrupts are
pending. See the register summary in Table 19–213 for the register attributes.
The bit assignments are:
Table 217. ISPR bit assignments
Bits
Name
Function
[31:0]
SETPEND
Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Remark: Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
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• a disabled interrupt sets the state of that interrupt to pending.
19.5.2.5 Interrupt Clear-pending Register
The ICPR removes the pending state from interrupts, and shows which interrupts are
pending. See the register summary in Table 19–213 for the register attributes.
The bit assignments are:
Table 218. ICPR bit assignments
Bits
Name
Function
[31:0]
CLRPEND
Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an interrupt.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
19.5.2.6 Interrupt Priority Registers
The IPR0-IPR7 registers provide an 2-bit priority field for each interrupt. These registers
are only word-accessible. See the register summary in Table 19–213 for their attributes.
Each register holds four priority fields as shown:
31
16 15
PRI_30
PRI_(4n+3)
PRI_(4n+2)
PRI_3
PRI_2
IPR0
0
PRI_29
PRI_28
PRI_(4n+1)
PRI_(4n)
PRI_1
PRI_0
...
...
IPRn
8 7
...
PRI_31
...
IPR7
24 23
Fig 47. IPR register
Table 219. IPR bit assignments
Bits
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Name
Function
Each priority field holds a priority value, 0-3. The lower the
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:6] of each field, bits
[5:0] read as zero and ignore writes.
[31:24]
Priority, byte offset 3
[23:16]
Priority, byte offset 2
[15:8]
Priority, byte offset 1
[7:0]
Priority, byte offset 0
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See Section 19–19.5.2.1 for more information about the access to the interrupt priority
array, which provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt M as follows:
• the corresponding IPR number, N, is given by N = N DIV 4
• the byte offset of the required Priority field in this register is M MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
19.5.2.7 Level-sensitive and pulse interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see Section 19.5.2.7.1. For a level-sensitive interrupt, if the signal is not
deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
19.5.2.7.1
Hardware and software control of interrupts
The Cortex-M0 latches all interrupts. A peripheral interrupt becomes pending for one of
the following reasons:
• the NVIC detects that the interrupt signal is active and the corresponding interrupt is
not active
• the NVIC detects a rising edge on the interrupt signal
• software writes to the corresponding interrupt set-pending register bit, see
Section 19–19.5.2.4.
A pending interrupt remains pending until one of the following:
• The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
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– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this
is pulsed the state of the interrupt changes to pending and active. In this case,
when the processor returns from the ISR the state of the interrupt changes to
pending, which might cause the processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the
processor returns from the ISR the state of the interrupt changes to inactive.
• Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the
interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, state of the interrupt changes to:
– inactive, if the state was pending
– active, if the state was active and pending.
19.5.2.8 NVIC usage hints and tips
Ensure software uses correctly aligned register accesses. The processor does not
support unaligned accesses to NVIC registers.
An interrupt can enter pending state even if it is disabled. Disabling an interrupt only
prevents the processor from taking that interrupt.
19.5.2.8.1
NVIC programming hints
Software uses the CPSIE i and instructions to enable and disable interrupts. The CMSIS
provides the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 220. CMSIS functions for NVIC control
CMSIS interrupt control function
Description
void NVIC_EnableIRQ(IRQn_t IRQn)
Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn)
Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
Return true (1) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn)
Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
Clear IRQn pending status
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn)
Read priority of IRQn
void NVIC_SystemReset (void)
Reset the system
The input parameter IRQn is the IRQ number, see Table 19–200 for more information. For
more information about these functions, see the CMSIS documentation.
19.5.3 System Control Block
The System Control Block (SCB) provides system implementation information, and
system control. This includes configuration, control, and reporting of the system
exceptions. The SCB registers are:
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Table 221. Summary of the SCB registers
Address
Name
Type
Reset value
Description
0xE000ED00
0xE000ED04
CPUID
RO
0x410CC200
Section 19.5.3.2
ICSR
RW [1]
0x00000000
Section 19–19.5.3.3
0xE000ED0C
AIRCR
RW [1]
0xFA050000
Section 19–19.5.3.4
0xE000ED10
SCR
RW
0x00000000
Section 19–19.5.3.5
0xE000ED14
CCR
RO
0x00000204
Section 19–19.5.3.6
0xE000ED1C
SHPR2
RW
0x00000000
Section 19–19.5.3.7.1
0xE000ED20
SHPR3
RW
0x00000000
Section 19–19.5.3.7.2
[1]
See the register description for more information.
19.5.3.1 The CMSIS mapping of the Cortex-M0 SCB registers
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the array SHP[1] corresponds to the registers SHPR2-SHPR3.
19.5.3.2 CPUID Register
The CPUID register contains the processor part number, version, and implementation
information. See the register summary in for its attributes. The bit assignments are:
Table 222. CPUID register bit assignments
Bits
Name
Function
[31:24]
Implementer
Implementer code:
[23:20]
Variant
Variant number, the r value in the rnpn product revision
identifier:
[19:16]
Constant
Constant that defines the architecture of the processor:, reads
as
[15:4]
Partno
Part number of the processor:
0x41 = ARM
0x0 = Revision 0
0xC = ARMv6-M architecture
0xC20 = Cortex-M0
[3:0]
Revision
Revision number, the p value in the rnpn product revision
identifier:
0x0 = Patch 0
19.5.3.3 Interrupt Control and State Register
The ICSR:
• provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
• indicates:
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
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– whether any interrupts are pending.
See the register summary in Table 19–221 for the ICSR attributes. The bit assignments
are:
Table 223. ICSR bit assignments
Bits
Name
Type
[31]
NMIPENDSET[2]
RW
Function
NMI set-pending bit.
Write:
0 = no effect
1 = changes NMI exception state to pending.
Read:
0 = NMI exception is not pending
1 = NMI exception is pending.
Because NMI is the highest-priority exception, normally
the processor enters the NMI exception handler as soon
as it detects a write of 1 to this bit. Entering the handler
then clears this bit to 0. This means a read of this bit by
the NMI exception handler returns 1 only if the NMI
signal is reasserted while the processor is executing that
handler.
[30:29]
-
-
Reserved.
[28]
PENDSVSET
RW
PendSV set-pending bit.
Write:
0 = no effect
1 = changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV
exception state to pending.
[27]
PENDSVCLR
WO
PendSV clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the PendSV
exception.
[26]
PENDSTSET
RW
SysTick exception set-pending bit.
Write:
0 = no effect
1 = changes SysTick exception state to pending.
Read:
0 = SysTick exception is not pending
1 = SysTick exception is pending.
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Table 223. ICSR bit assignments
Bits
Name
Type
Function
[25]
PENDSTCLR
WO
SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick
exception.
This bit is WO. On a register read its value is Unknown.
[24:23]
-
-
Reserved.
[22]
ISRPENDING
RO
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
[21:18]
-
-
Reserved.
[17:12]
VECTPENDING
RO
Indicates the exception number of the highest priority
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
[11:6]
-
-
[5:0]
VECTACTIVE[1]
RO
Reserved.
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number[1] of the currently
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table 19–195.
[1]
This is the same value as IPSR bits[5:0], see Table 19–195.
[2]
The NMI is not implemented on the LPC1102.
When you write to the ICSR, the effect is Unpredictable if you:
• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
19.5.3.4 Application Interrupt and Reset Control Register
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in Table 19–221 and Table 19–224 for its attributes.
To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
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Table 224. AIRCR bit assignments
Bits
Name
Type
[31:16]
Read: Reserved
RW
Write: VECTKEY
Function
Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the
write is ignored.
[15]
ENDIANESS
RO
Data endianness implemented:
0 = Little-endian
1 = Big-endian.
[14:3]
-
-
[2]
SYSRESETREQ
WO
Reserved
System reset request:
0 = no effect
1 = requests a system level reset.
This bit reads as 0.
[1]
VECTCLRACTIVE
WO
Reserved for debug use. This bit reads as 0. When
writing to the register you must write 0 to this bit,
otherwise behavior is Unpredictable.
[0]
-
-
Reserved.
19.5.3.5 System Control Register
The SCR controls features of entry to and exit from low power state. See the register
summary in Table 19–221 for its attributes. The bit assignments are:
Table 225. SCR bit assignments
Bits
Name
Function
[31:5]
-
Reserved.
[4]
SEVONPEND
Send Event on Pending bit:
0 = only enabled interrupts or events can wake-up the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wake-up the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for
an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
[3]
-
Reserved.
[2]
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
[1]
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread
mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR to Thread
mode.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
[0]
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Reserved.
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19.5.3.6 Configuration and Control Register
The CCR is a read-only register and indicates some aspects of the behavior of the
Cortex-M0 processor. See the register summary in Table 19–221 for the CCR attributes.
The bit assignments are:
Table 226. CCR bit assignments
Bits
Name
Function
[31:10]
-
Reserved.
[9]
STKALIGN
Always reads as one, indicates 8-byte stack alignment on
exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR
to indicate the stack alignment. On return from the exception it
uses this stacked bit to restore the correct stack alignment.
[8:4]
-
Reserved.
[3]
UNALIGN_TRP
Always reads as one, indicates that all unaligned accesses
generate a HardFault.
[2:0]
-
Reserved.
19.5.3.7 System Handler Priority Registers
The SHPR2-SHPR3 registers set the priority level, 0 to 3, of the exception handlers that
have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in Table 19–221 for their
attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
• uint32_t NVIC_GetPriority(IRQn_Type IRQn)
• void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
The input parameter IRQn is the IRQ number, see Table 19–200 for more information.
The system fault handlers, and the priority field and register for each handler are:
Table 227. System fault handler priority fields
Handler
Field
Register description
SVCall
PRI_11
Section 19–19.5.3.7.1
PendSV
PRI_14
Section 19–19.5.3.7.2
SysTick
PRI_15
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
19.5.3.7.1
System Handler Priority Register 2
The bit assignments are:
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Table 228. SHPR2 register bit assignments
Bits
19.5.3.7.2
Name
Function
[31:24]
PRI_11
Priority of system handler 11, SVCall
[23:0]
-
Reserved
System Handler Priority Register 3
The bit assignments are:
Table 229. SHPR3 register bit assignments
Bits
Name
Function
[31:24]
PRI_15
Priority of system handler 15, SysTick exception
[23:16]
PRI_14
Priority of system handler 14, PendSV
[15:0]
-
Reserved
19.5.3.8 SCB usage hints and tips
Ensure software uses aligned 32-bit word size transactions to access all the SCB
registers.
19.5.4 System timer, SysTick
When enabled, the timer counts down from the current value (SYST_CVR) to zero,
reloads (wraps) to the value in the SysTick Reload Value Register (SYST_RVR) on the
next clock edge, then decrements on subsequent clocks. When the counter transitions to
zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.
Remark: The SYST_CVR value is UNKNOWN on reset. Software should write to the
register to clear it to zero before enabling the feature. This ensures the timer will count
from the SYST_RVR value rather than an arbitrary value when it is enabled.
Remark: If the SYST_RVR is zero, the timer will be maintained with a current value of
zero after it is reloaded with this value. This mechanism can be used to disable the feature
independently from the timer enable bit.
A write to the SYST_CVR will clear the register and the COUNTFLAG status bit. The write
causes the SYST_CVR to reload from the SYST_RVR on the next timer clock, however, it
does not trigger the SysTick exception logic. On a read, the current value is the value of
the register at the time the register is accessed.
Remark: When the processor is halted for debugging the counter does not decrement.
The system timer registers are:
Table 230. System timer registers summary
Address
Name
Type
Reset
value
Description
0xE000E010
SYST_CSR
RW
0x00000000
Section 19.5.4.1
0xE000E014
SYST_RVR
RW
Unknown
Section 19–19.5.4.2
0xE000E018
SYST_CVR
RW
Unknown
Section 19–19.5.4.3
0x00000004 [1]
Section 19–19.5.4.4
0xE000E01C
[1]
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SYST_CALIB RO
SysTick calibration value.
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19.5.4.1 SysTick Control and Status Register
The SYST_CSR enables the SysTick features. See the register summary in for its
attributes. The bit assignments are:
Table 231. SYST_CSR bit assignments
Bits
Name
Function
[31:17]
-
Reserved.
[16]
COUNTFLAG
Returns 1 if timer counted to 0 since the last read of this register.
[15:3]
-
Reserved.
[2]
CLKSOURCE
Selects the SysTick timer clock source:
0 = external reference clock.
1 = processor clock.
Remark: The external reference clock option is not implemented.
This bit reads as 1 and writes to this bit are ignored.
[1]
TICKINT
Enables SysTick exception request:
0 = counting down to zero does not assert the SysTick exception
request.
1 = counting down to zero asserts the SysTick exception request.
[0]
ENABLE
Enables the counter:
0 = counter disabled.
1 = counter enabled.
19.5.4.2 SysTick Reload Value Register
The SYST_RVR specifies the start value to load into the SYST_CVR. See the register
summary in Table 19–230 for its attributes. The bit assignments are:
Table 232. SYST_RVR bit assignments
19.5.4.2.1
Bits
Name
Function
[31:24]
-
Reserved.
[23:0]
RELOAD
Value to load into the SYST_CVR when the counter is enabled and
when it reaches 0, see Section 19.5.4.2.1.
Calculating the RELOAD value
The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. You can
program a value of 0, but this has no effect because the SysTick exception request and
COUNTFLAG are activated when counting from 1 to 0.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD
value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set
RELOAD to 99.
19.5.4.3 SysTick Current Value Register
The SYST_CVR contains the current value of the SysTick counter. See the register
summary in Table 19–230 for its attributes. The bit assignments are:
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
Table 233. SYST_CVR bit assignments
Bits
Name
Function
[31:24]
-
Reserved.
[23:0]
CURRENT
Reads return the current value of the SysTick counter.
A write of any value clears the field to 0, and also clears the
SYST_CSR.COUNTFLAG bit to 0.
19.5.4.4 SysTick Calibration Value Register
The SYST_CALIB register indicates the SysTick calibration properties. See the register
summary in Table 19–230 for its attributes. The bit assignments are:
Table 234. SYST_CALIB register bit assignments
Bits
Name
Function
[31]
NOREF
Reads as one. Indicates that no separate reference clock is provided.
[30]
SKEW
Reads as one. Calibration value for the 10ms inexact timing is not known
because TENMS is not known. This can affect the suitability of SysTick
as a software real time clock.
[29:24]
-
Reserved.
[23:0]
TENMS
Reads as zero. Indicates calibration value is not known.
If calibration information is not known, calculate the calibration value required from the
frequency of the processor clock or external clock.
19.5.4.5 SysTick usage hints and tips
The interrupt controller clock updates the SysTick counter. If this clock signal is stopped
for low power mode, the SysTick counter stops.
Ensure software uses word accesses to access the SysTick registers.
If the SysTick counter reload and current value are undefined at reset, the correct
initialization sequence for the SysTick counter is:
1. Program reload value.
2. Clear current value.
3. Program Control and Status register.
19.6 Cortex-M0 instruction summary
Table 235. Cortex M0- instruction summary
Operation
Description
Assembler
Cycles
Move
8-bit immediate
MOVS Rd, #<imm>
1
Add
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Lo to Lo
MOVS Rd, Rm
1
Any to Any
MOV Rd, Rm
1
Any to PC
MOV PC, Rm
3
3-bit immediate
ADDS Rd, Rn, #<imm>
1
All registers Lo
ADDS Rd, Rn, Rm
1
Any to Any
ADD Rd, Rd, Rm
1
Any to PC
ADD PC, PC, Rm
3
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
Table 235. Cortex M0- instruction summary
Operation
Description
Assembler
Cycles
Add
8-bit immediate
ADDS Rd, Rd, #<imm>
1
With carry
ADCS Rd, Rd, Rm
1
Immediate to SP
ADD SP, SP, #<imm>
1
Form address from SP
ADD Rd, SP, #<imm>
1
Form address from PC
ADR Rd, <label>
1
Lo and Lo
SUBS Rd, Rn, Rm
1
3-bit immediate
SUBS Rd, Rn, #<imm>
1
8-bit immediate
SUBS Rd, Rd, #<imm>
1
With carry
SBCS Rd, Rd, Rm
1
Immediate from SP
SUB SP, SP, #<imm>
1
Subtract
Negate
RSBS Rd, Rn, #0
1
Multiply
Multiply
MULS Rd, Rm, Rd
1 or 32[1]
Compare
Compare
CMP Rn, Rm
1
Negative
CMN Rn, Rm
1
Immediate
CMP Rn, #<imm>
1
AND
ANDS Rd, Rd, Rm
1
Exclusive OR
EORS Rd, Rd, Rm
1
OR
ORRS Rd, Rd, Rm
1
Bit clear
BICS Rd, Rd, Rm
1
Move NOT
MVNS Rd, Rm
1
AND test
TST Rn, Rm
1
Logical shift left by immediate
LSLS Rd, Rm, #<shift>
1
Logical
Shift
User manual
LSLS Rd, Rd, Rs
1
Logical shift right by immediate
LSRS Rd, Rm, #<shift>
1
Logical shift right by register
LSRS Rd, Rd, Rs
1
Arithmetic shift right
ASRS Rd, Rm, #<shift>
1
Arithmetic shift right by regist
ASRS Rd, Rd, Rs
1
Rotate
Rotate right by register
RORS Rd, Rd, Rs
1
Load
Word, immediate offset
LDR Rd, [Rn, #<imm>]
2
Halfword, immediate offset
LDRH Rd, [Rn, #<imm>]
2
Byte, immediate offset
LDRB Rd, [Rn, #<imm>]
2
Word, register offset
LDR Rd, [Rn, Rm]
2
Halfword, register offset
LDRH Rd, [Rn, Rm]
2
Signed halfword, register offset
LDRSH Rd, [Rn, Rm]
2
Store
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Logical shift left by register
Byte, register offset
LDRB Rd, [Rn, Rm]
2
Signed byte, register offset
LDRSB Rd, [Rn, Rm]
2
PC-relative
LDR Rd, <label>
2
SP-relative
LDR Rd, [SP, #<imm>]
2
Multiple, excluding base
LDM Rn!, {<loreglist>}
1 + N[2]
Multiple, including base
LDM Rn, {<loreglist>}
1 + N[2]
Word, immediate offset
STR Rd, [Rn, #<imm>]
2
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
Table 235. Cortex M0- instruction summary
Operation
Description
Assembler
Cycles
Store
Halfword, immediate offset
STRH Rd, [Rn, #<imm>]
2
Byte, immediate offset
STRB Rd, [Rn, #<imm>]
2
Word, register offset
STR Rd, [Rn, Rm]
2
Halfword, register offset
STRH Rd, [Rn, Rm]
2
Byte, register offset
STRB Rd, [Rn, Rm]
2
SP-relative
STR Rd, [SP, #<imm>]
2
Multiple
STM Rn!, {<loreglist>}
1 + N[2]
Push
PUSH {<loreglist>}
1 + N[2]
Push with link register
PUSH {<loreglist>, LR}
1 + N[2]
Pop
POP {<loreglist>}
1 + N[2]
Pop and return
POP {<loreglist>, PC}
4 + N[3]
Conditional
B<cc> <label>
1 or 3[4]
Unconditional
B <label>
3
With link
BL <label>
4
Push
Pop
Branch
Extend
Reverse
State change
Hint
Barriers
[1]
With exchange
BX Rm
3
With link and exchange
BLX Rm
3
Signed halfword to word
SXTH Rd, Rm
1
Signed byte to word
SXTB Rd, Rm
1
Unsigned halfword
UXTH Rd, Rm
1
Unsigned byte
UXTB Rd, Rm
1
Bytes in word
REV Rd, Rm
1
Bytes in both halfwords
REV16 Rd, Rm
1
Signed bottom half word
REVSH Rd, Rm
1
Supervisor Call
SVC <imm>
-[5]
Disable interrupts
CPSID i
1
Enable interrupts
CPSIE i
1
Read special register
MRS Rd, <specreg>
4
Write special register
MSR <specreg>, Rn
4
Send event
SEV
1
Wait for event
WFE
2[6]
Wait for interrupt
WFI
2[6]
Yield
YIELD[7]
1
No operation
NOP
1
Instruction synchronization
ISB
4
Data memory
DMB
4
Data synchronization
DSB
4
Depends on multiplier implementation.
[2]
N is the number of elements.
[3]
N is the number of elements in the stack-pop list including PC and assumes load or store
does not generate a HardFault exception.
[4]
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3 if taken, 1 if not taken.
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
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[5]
Cycle count depends on core and debug configuration.
[6]
Excludes time spend waiting for an interrupt or event.
[7]
Executes as NOP.
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20.1 Abbreviations
Table 236. Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
AMBA
Advanced Microcontroller Bus Architecture
APB
Advanced Peripheral Bus
BOD
BrownOut Detection
GPIO
General Purpose Input/Output
PLL
Phase-Locked Loop
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
TTL
Transistor-Transistor Logic
UART
Universal Asynchronous Receiver/Transmitter
20.2 References
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[1]
ARM DUI 0497A — Cortex-M0 Devices Generic User Guide
[2]
ARM DDI 0432C — Cortex-M0 Revision r0p0 Technical Reference Manual
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Chapter 20: LPC1102 Supplementary information
20.3 Legal information
20.3.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
20.3.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
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malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
20.3.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
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20.4 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . .4
LPC1102 memory configuration . . . . . . . . . . . . .7
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .10
System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .12
System PLL control register (SYSPLLCTRL,
address 0x4004 8008) bit description . . . . . . .13
System PLL status register (SYSPLLSTAT,
address 0x4004 800C) bit description . . . . . . .13
System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description. . . . . . . .13
Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Internal resonant crystal control register
(IRCCTRL, address 0x4004 8028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
System reset status register (SYSRSTSTAT,
address 0x4004 8030) bit description. . . . . . . .16
System PLL clock source select register
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
System PLL clock source update enable register
(SYSPLLUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Main clock source select register (MAINCLKSEL,
address 0x4004 8070) bit description. . . . . . . .17
Main clock source update enable register
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
System AHB clock divider register
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
System AHB clock control register
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .18
SPI0 clock divider register (SSP0CLKDIV,
address 0x4004 8094) bit description. . . . . . . .20
UART clock divider register (UARTCLKDIV,
address 0x4004 8098) bit description. . . . . . . .20
WDT clock source select register (WDTCLKSEL,
address 0x4004 80D0) bit description . . . . . . .21
WDT clock source update enable register
(WDTCLKUEN, address 0x4004 80D4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WDT clock divider register (WDTCLKDIV, address
0x4004 80D8) bit description . . . . . . . . . . . . . .21
POR captured PIO status registers 0
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
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Table 26. BOD control register (BODCTRL, address 0x4004
8150) bit description. . . . . . . . . . . . . . . . . . . . . 22
Table 27. System tick timer calibration register
(SYSTCKCAL, address 0x4004 8154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 28. Start logic edge control register 0 (STARTAPRP0,
address 0x4004 8200) bit description . . . . . . 23
Table 29. Start logic signal enable register 0 (STARTERP0,
address 0x4004 8204) bit description . . . . . . 24
Table 30. Start logic reset register 0 (STARTRSRP0CLR,
address 0x4004 8208) bit description . . . . . . 25
Table 31. Start logic status register 0 (STARTSRP0,
address 0x4004 820C) bit description . . . . . . 25
Table 32. Allowed values for PDSLEEPCFG register . . . 26
Table 33. Deep-sleep configuration register
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 34. Wake-up configuration register (PDAWAKECFG,
address 0x4004 8234) bit description . . . . . . 27
Table 35. Power-down configuration register (PDRUNCFG,
address 0x4004 8238) bit description . . . . . . 29
Table 36. Device ID register (DEVICE_ID, address 0x4004
83F4) bit description . . . . . . . . . . . . . . . . . . . . 29
Table 37. PLL frequency parameters. . . . . . . . . . . . . . . . 36
Table 38. PLL configuration examples. . . . . . . . . . . . . . . 37
Table 39. Flash configuration register (FLASHCFG, address
0x4003 C010) bit description . . . . . . . . . . . . . . 38
Table 40. Register overview: PMU (base address 0x4003
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 41. Power control register (PCON, address 0x4003
8000) bit description . . . . . . . . . . . . . . . . . . . . 39
Table 42. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 43. set_power routine . . . . . . . . . . . . . . . . . . . . . . 46
Table 44. Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . 48
Table 45. Register overview: I/O configuration (base
address 0x4004 4000) . . . . . . . . . . . . . . . . . . . 52
Table 46. I/O configuration registers ordered by port
number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 47. IOCON_nRESET_PIO0_0 register
(IOCON_nRESET_PIO0_0, address 0x4004
400C) bit description . . . . . . . . . . . . . . . . . . . . 53
Table 48. IOCON_PIO0_8 register (IOCON_PIO0_8,
address 0x4004 4060) bit description . . . . . . . 54
Table 49. IOCON_PIO0_9 register (IOCON_PIO0_9,
address 0x4004 4064) bit description . . . . . . . 54
Table 50. IOCON_SWCLK_PIO0_10 register
(IOCON_SWCLK_PIO0_10, address 0x4004
4068) bit description . . . . . . . . . . . . . . . . . . . . 55
Table 51. IOCON_R_PIO0_11 register
(IOCON_R_PIO0_11, address 0x4004 4074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 52. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0,
address 0x4004 4078) bit description . . . . . . . 56
Table 53. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1,
address 0x4004 407C) bit description . . . . . . 57
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Table 54. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2,
address 0x4004 4080) bit description . . . . . . .58
Table 55. IOCON_SWDIO_PIO1_3 register
(IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 56. IOCON_PIO1_6 register (IOCON_PIO1_6,
address 0x4004 40A4) bit description . . . . . . .59
Table 57. IOCON_PIO1_7 register (IOCON_PIO1_7,
address 0x4004 40A8) bit description . . . . . . .59
Table 58. Pin description table . . . . . . . . . . . . . . . . . . . .61
Table 59. GPIO configuration . . . . . . . . . . . . . . . . . . . . . .63
Table 60. Register overview: GPIO (base address port 0:
0x5000 0000; port 1: 0x5001 0000) . . . . . . . . .63
Table 61. GPIOnDATA register (GPIO0DATA, address
0x5000 0000 to 0x5000 3FFC; GPIO1DATA,
address 0x5001 0000 to 0x5001 3FFC;
GPIO2DATA, address 0x5002 0000 to 0x5002
3FFC; GPIO3DATA, address 0x5003 0000 to
0x5003 3FFC) bit description . . . . . . . . . . . . .64
Table 62. GPIOnDIR register (GPIO0DIR, address 0x5000
8000 to GPIO3DIR, address 0x5003 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 63. GPIOnIS register (GPIO0IS, address 0x5000
8004 to GPIO3IS, address 0x5003 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 64. GPIOnIBE register (GPIO0IBE, address 0x5000
8008 to GPIO3IBE, address 0x5003 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 65. GPIOnIEV register (GPIO0IEV, address 0x5000
800C to GPIO3IEV, address 0x5003 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 66. GPIOnIE register (GPIO0IE, address 0x5000
8010 to GPIO3IE, address 0x5003 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 67. GPIOnIRS register (GPIO0IRS, address 0x5000
8014 to GPIO3IRS, address 0x5003 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 68. GPIOnMIS register (GPIO0MIS, address 0x5000
8018 to GPIO3MIS, address 0x5003 8018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 69. GPIOnIC register (GPIO0IC, address 0x5000
801C to GPIO3IC, address 0x5003 801C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 70. UART pin description . . . . . . . . . . . . . . . . . . . .69
Table 71. Register overview: UART (base address: 0x4000
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 72. UART Receiver Buffer Register (U0RBR address 0x4000 8000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . . .71
Table 73. UART Transmitter Holding Register (U0THR address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . .71
Table 74. UART Divisor Latch LSB Register (U0DLL address 0x4000 8000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 75. UART Divisor Latch MSB Register (U0DLM address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
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Table 76. UART Interrupt Enable Register (U0IER - address
0x4000 8004 when DLAB = 0) bit description 72
Table 77. UART Interrupt Identification Register (U0IIR address 0x4004 8008, Read Only) bit description
73
Table 78. UART Interrupt Handling . . . . . . . . . . . . . . . . . 74
Table 79. UART FIFO Control Register (U0FCR - address
0x4000 8008, Write Only) bit description . . . . . 76
Table 80. UART Line Control Register (U0LCR - address
0x4000 800C) bit description . . . . . . . . . . . . . 76
Table 81. UART Line Status Register (U0LSR - address
0x4000 8014, Read Only) bit description . . . . 77
Table 82. UART Scratch Pad Register (U0SCR - address
0x4000 8014) bit description . . . . . . . . . . . . . . 79
Table 83. Auto-baud Control Register (U0ACR - address
0x4000 8020) bit description . . . . . . . . . . . . . . 79
Table 84. UART Fractional Divider Register (U0FDR address 0x4000 8028) bit description . . . . . . . 83
Table 85. Fractional Divider setting look-up table . . . . . . 85
Table 86. UART Transmit Enable Register (U0TER address 0x4000 8030) bit description . . . . . . . 86
Table 87. UART RS485 Control register (U0RS485CTRL address 0x4000 804C) bit description . . . . . . 86
Table 88. UART RS-485 Address Match register
(U0RS485ADRMATCH - address 0x4000 8050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 89. SPI pin descriptions . . . . . . . . . . . . . . . . . . . . . 91
Table 90. Register overview: SPI0 (base address 0x4004
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 91: SPI/SSP Control Register 0 (SSP0CR0 - address
0x4004 0000) bit description . . . . . . . . . . . . . . 92
Table 92: SPI/SSP Control Register 1 (SSP0CR1 - address
0x4004 0004) bit description . . . . . . . . . . . . . . 93
Table 93: SPI/SSP Data Register (SSP0DR - address
0x4004 0008) bit description . . . . . . . . . . . . . . 94
Table 94: SPI/SSP Status Register (SSP0SR - address
0x4004 000C) bit description . . . . . . . . . . . . . . 94
Table 95: SPI/SSP Clock Prescale Register (SSP0CPSR address 0x4004 0010) bit description . . . . . . . 95
Table 96: SPI/SSP Interrupt Mask Set/Clear register
(SSP0IMSC - address 0x4004 0014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 97: SPI/SSP Raw Interrupt Status register (SSP0RIS
- address 0x4004 0018) bit description . . . . . . 96
Table 98: SPI/SSP Masked Interrupt Status register
(SSP0MIS - address 0x4004 001C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 99: SPI/SSP interrupt Clear Register (SSP0ICR address 0x4004 0020) bit description . . . . . . . 97
Table 100. Counter/timer pin description . . . . . . . . . . . . 106
Table 101. Register overview: 16-bit counter/timer 0 CT16B0
(base address 0x4000 C000) . . . . . . . . . . . . 106
Table 102. Register overview: 16-bit counter/timer 1 CT16B1
(base address 0x4001 0000) . . . . . . . . . . . . 107
Table 103. Interrupt Register (TMR16B0IR - address
0x4000 C000 and TMR16B1IR - address
0x4001 0000) bit description . . . . . . . . . . . . . 108
Table 104. Timer Control Register (TMR16B0TCR - address
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0x4000 C004 and TMR16B1TCR - address
0x4001 0004) bit description . . . . . . . . . . . . .108
Table 105. Timer counter registers (TMR16B0TC, address
0x4000 C008 and TMR16B1TC 0x4001 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 106. Prescale registers (TMR16B0PR, address
0x4000 C00C and TMR16B1PR 0x4001 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 107: Prescale counter registers (TMR16B0PC,
address 0x4001 C010 and TMR16B1PC
0x4000 0010) bit description . . . . . . . . . . . . .109
Table 108. Match Control Register (TMR16B0MCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014) bit description . . . . . .109
Table 109: Match registers (TMR16B0MR0 to 3, addresses
0x4000 C018 to 24 and TMR16B1MR0 to 3,
addresses 0x4001 0018 to 24) bit description 111
Table 110. External Match Register (TMR16B0EMR address 0x4000 C03C and TMR16B1EMR address 0x4001 003C) bit description . . . . . . 112
Table 111. External match control . . . . . . . . . . . . . . . . . . 113
Table 112. PWM Control Register (TMR16B0PWMC address 0x4000 C074 and TMR16B1PWMCaddress 0x4001 0074) bit description. . . . . . . 113
Table 113. Counter/timer pin description . . . . . . . . . . . . . 118
Table 114. Register overview: 32-bit counter/timer 0 CT32B0
(base address 0x4001 4000) . . . . . . . . . . . . 119
Table 115. Register overview: 32-bit counter/timer 1 CT32B1
(base address 0x4001 8000) . . . . . . . . . . . . 119
Table 116. Interrupt Register (TMR32B0IR - address
0x4001 4000 and TMR32B1IR - address
0x4001 8000) bit description . . . . . . . . . . . . .120
Table 117. Timer Control Register (TMR32B0TCR - address
0x4001 4004 and TMR32B1TCR - address
0x4001 8004) bit description . . . . . . . . . . . . .121
Table 118. Timer counter registers (TMR32B0TC, address
0x4001 4008 and TMR32B1TC 0x4001 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Table 119. Prescale registers (TMR32B0PR, address
0x4001 400C and TMR32B1PR 0x4001 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Table 120. Prescale registers (TMR32B0PC, address
0x4001 4010 and TMR32B1PC 0x4001 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Table 121. Match Control Register (TMR32B0MCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014) bit description. . . . . . .122
Table 122. Match registers (TMR32B0MR0 to 3, addresses
0x4001 4018 to 24 and TMR32B1MR0 to 3,
addresses 0x4001 8018 to 24) bit description 123
Table 123. Capture Control Register (TMR32B1CCR address 0x4001 8028) bit description. . . . . . .123
Table 124. Capture registers (TMR32B1CR0, addresses
0x4001 802C) bit description . . . . . . . . . . . . .124
Table 125. External Match Register (TMR32B0EMR address 0x4001 403C and TMR32B1EMR address0x4001 803C) bit description . . . . . . .125
Table 126. External match control . . . . . . . . . . . . . . . . . .126
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Table 127. Count Control Register (TMR32B0CTCR address 0x4001 4070 and TMR32B1TCR address 0x4001 8070) bit description . . . . . 127
Table 128. PWM Control Register (TMR32B0PWMC 0x4001 4074 and TMR32B1PWMC - 0x4001
8074) bit description. . . . . . . . . . . . . . . . . . . . 127
Table 129. Register overview: Watchdog timer (base
address 0x4000 4000) . . . . . . . . . . . . . . . . . . 133
Table 130. Watchdog Mode register (WDMOD - address
0x4000 4000) bit description . . . . . . . . . . . . . 133
Table 131. Watchdog operating modes selection . . . . . . 134
Table 132. Watchdog Constant register (WDTC - address
0x4000 4004) bit description . . . . . . . . . . . . . 134
Table 133. Watchdog Feed register (WDFEED - address
0x4000 4008) bit description . . . . . . . . . . . . . 134
Table 134. Watchdog Timer Value register (WDTV - address
0x4000 000C) bit description . . . . . . . . . . . . . 135
Table 135. Register overview: SysTick timer (base address
0xE000 E000) . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 136. System Timer Reload value register (SYST_RVR
- 0xE000 E014) bit description. . . . . . . . . . . . 138
Table 137. System Timer Current value register (SYST_CVR
- 0xE000 E018) bit description. . . . . . . . . . . . 138
Table 138. System Timer Calibration value register
(SYST_CALIB - 0xE000 E01C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 139. ADC pin description . . . . . . . . . . . . . . . . . . . 140
Table 140. Register overview: ADC (base address 0x4001
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 141. A/D Control Register (AD0CR - address
0x4001 C000) bit description . . . . . . . . . . . . . 142
Table 142. A/D Global Data Register (AD0GDR - address
0x4001 C004) bit description . . . . . . . . . . . . . 143
Table 143. A/D Status Register (AD0STAT - address
0x4001 C030) bit description . . . . . . . . . . . . . 144
Table 144. A/D Interrupt Enable Register (AD0INTEN address 0x4001 C00C) bit description. . . . . . 144
Table 145. A/D Data Registers (AD0DR0 to AD0DR4 addresses 0x4001 C010 to 0x4001 C020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 146. LPC1102 flash configuration . . . . . . . . . . . . . 146
Table 147. Flash sector configuration . . . . . . . . . . . . . . . 149
Table 148. Code Read Protection options . . . . . . . . . . . 150
Table 149. Code Read Protection hardware/software
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 150. ISP commands allowed for different
CRP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 151. UART ISP command summary . . . . . . . . . . . 153
Table 152. UART ISP Unlock command . . . . . . . . . . . . . 153
Table 153. UART ISP Set Baud Rate command. . . . . . . 153
Table 154. UART ISP Echo command . . . . . . . . . . . . . . 154
Table 155. UART ISP Write to RAM command. . . . . . . . 154
Table 156. UART ISP Read Memory command . . . . . . . 155
Table 157. UART ISP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 158. UART ISP Copy command . . . . . . . . . . . . . . 157
Table 159. UART ISP Go command . . . . . . . . . . . . . . . . 157
Table 160. UART ISP Erase sector command . . . . . . . . 158
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Table 161. UART ISP Blank check sector command . . .158
Table 162. UART ISP Read Part Identification command158
Table 163. Part identification number . . . . . . . . . . . . . . .158
Table 164. UART ISP Read Boot Code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Table 165. UART ISP Compare command . . . . . . . . . . .159
Table 166. UART ISP ReadUID command . . . . . . . . . . .159
Table 167. UART ISP Return Codes Summary. . . . . . . .160
Table 168. IAP Command Summary . . . . . . . . . . . . . . . .162
Table 169. IAP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Table 170. IAP Copy RAM to flash command . . . . . . . . .163
Table 171. IAP Erase Sector(s) command . . . . . . . . . . .164
Table 172. IAP Blank check sector(s) command . . . . . . .164
Table 173. IAP Read Part Identification command . . . . .164
Table 174. IAP Read Boot Code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Table 175. IAP Compare command. . . . . . . . . . . . . . . . .165
Table 176. IAP Reinvoke ISP . . . . . . . . . . . . . . . . . . . . .165
Table 177. IAP ReadUID command. . . . . . . . . . . . . . . . .166
Table 178. IAP Status Codes Summary . . . . . . . . . . . . .166
Table 179. Memory mapping in debug mode . . . . . . . . .167
Table 180. Flash configuration register (FLASHCFG,
address 0x4003 C010) bit description . . . . . .167
Table 181. Register overview: FMC (base address 0x4003
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Table 182. Flash Module Signature Start register
(FMSSTART - 0x4003 C020) bit description .168
Table 183. Flash Module Signature Stop register (FMSSTOP
- 0x4003 C024) bit description . . . . . . . . . . . .168
Table 184. FMSW0 register bit description (FMSW0,
address: 0x4003 C02C) . . . . . . . . . . . . . . . . .169
Table 185. FMSW1 register bit description (FMSW1,
address: 0x4003 C030) . . . . . . . . . . . . . . . . .169
Table 186. FMSW2 register bit description (FMSW2,
address: 0x4003 C034) . . . . . . . . . . . . . . . . .169
Table 187. FMSW3 register bit description (FMSW3,
address: 0x4003 40C8) . . . . . . . . . . . . . . . .169
Table 188. Flash module Status register (FMSTAT - 0x4003
CFE0) bit description . . . . . . . . . . . . . . . . . . .170
Table 189. Flash Module Status Clear register (FMSTATCLR
- 0x0x4003 CFE8) bit description . . . . . . . . . .170
Table 190. Serial Wire Debug pin description . . . . . . . . .172
Table 191. Summary of processor mode and stack use
options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Table 192. Core register set summary. . . . . . . . . . . . . . .177
Table 193. PSR register combinations . . . . . . . . . . . . . .178
Table 194. APSR bit assignments . . . . . . . . . . . . . . . . . .179
Table 195. IPSR bit assignments. . . . . . . . . . . . . . . . . . .179
Table 196. EPSR bit assignments . . . . . . . . . . . . . . . . . .180
Table 197. PRIMASK register bit assignments . . . . . . . .180
Table 198. CONTROL register bit assignments . . . . . . .181
Table 199. Memory access behavior . . . . . . . . . . . . . . . .185
Table 200. Properties of different exception types. . . . . .187
Table 201. Exception return behavior . . . . . . . . . . . . . . .192
Table 202. Cortex-M0 instructions . . . . . . . . . . . . . . . . . .195
Table 203. CMSIS intrinsic functions to generate some
Cortex-M0 instructions . . . . . . . . . . . . . . . . . .196
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Table 204. insic functions to access the special
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 205. Condition code suffixes . . . . . . . . . . . . . . . . . 202
Table 206. Access instructions . . . . . . . . . . . . . . . . . . . 202
Table 207. Data processing instructions . . . . . . . . . . . . . 208
Table 208. ADC, ADD, RSB, SBC and SUB operand
restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 209. Branch and control instructions. . . . . . . . . . . 217
Table 210. Branch ranges. . . . . . . . . . . . . . . . . . . . . . . . 218
Table 211. Miscellaneous instructions. . . . . . . . . . . . . . . 219
Table 212. Core peripheral register regions . . . . . . . . . . 226
Table 213. NVIC register summary. . . . . . . . . . . . . . . . . 227
Table 214. CMISIS access NVIC functions . . . . . . . . . . 227
Table 215. ISER bit assignments . . . . . . . . . . . . . . . . . . 228
Table 216. ICER bit assignments . . . . . . . . . . . . . . . . . . 228
Table 217. ISPR bit assignments . . . . . . . . . . . . . . . . . . 228
Table 218. ICPR bit assignments . . . . . . . . . . . . . . . . . . 229
Table 219. IPR bit assignments . . . . . . . . . . . . . . . . . . . 229
Table 220. CMSIS functions for NVIC control. . . . . . . . . 231
Table 221. Summary of the SCB registers . . . . . . . . . . . 232
Table 222. CPUID register bit assignments . . . . . . . . . . 232
Table 223. ICSR bit assignments . . . . . . . . . . . . . . . . . . 233
Table 224. AIRCR bit assignments . . . . . . . . . . . . . . . . . 235
Table 225. SCR bit assignments. . . . . . . . . . . . . . . . . . . 235
Table 226. CCR bit assignments . . . . . . . . . . . . . . . . . . 236
Table 227. System fault handler priority fields . . . . . . . . 236
Table 228. SHPR2 register bit assignments . . . . . . . . . . 237
Table 229. SHPR3 register bit assignments . . . . . . . . . . 237
Table 230. System timer registers summary. . . . . . . . . . 237
Table 231. SYST_CSR bit assignments . . . . . . . . . . . . . 238
Table 232. SYST_RVR bit assignments . . . . . . . . . . . . . 238
Table 233. SYST_CVR bit assignments . . . . . . . . . . . . . 239
Table 234. SYST_CALIB register bit assignments . . . . . 239
Table 235. Cortex M0- instruction summary . . . . . . . . . 239
Table 236. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 243
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© NXP B.V. 2010. All rights reserved.
249 of 258
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20.5 Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Fig 36.
Fig 37.
Fig 38.
Fig 39.
Fig 40.
Fig 41.
LPC1102 Block diagram . . . . . . . . . . . . . . . . . . . .5
LPC1102 memory map . . . . . . . . . . . . . . . . . . . . .8
LPC1102 CGU block diagram . . . . . . . . . . . . . . .10
System PLL block diagram . . . . . . . . . . . . . . . . .35
Power profiles usage . . . . . . . . . . . . . . . . . . . . . .45
Standard I/O pin configuration . . . . . . . . . . . . . . .51
Pin configuration WLCSP16 package . . . . . . . . .61
Masked write operation to the GPIODATA
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Masked read operation . . . . . . . . . . . . . . . . . . . .68
Auto-baud a) mode 0 and b) mode 1 waveform .82
Algorithm for setting UART dividers. . . . . . . . . . .84
UART block diagram . . . . . . . . . . . . . . . . . . . . . .89
Texas Instruments Synchronous Serial Frame
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . . .98
SPI frame format with CPOL=0 and CPHA=0 (a)
Single and b) Continuous Transfer) . . . . . . . . . . .99
SPI frame format with CPOL=0 and CPHA=1 . .100
SPI frame format with CPOL = 1 and CPHA = 0 (a)
Single and b) Continuous Transfer) . . . . . . . . . .101
SPI Frame Format with CPOL = 1 and
CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Microwire frame format (single transfer) . . . . . .103
Microwire frame format (continuos transfers) . .103
Microwire frame format setup and hold details .104
Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 115
A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . . 115
A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . . 115
16-bit counter/timer block diagram. . . . . . . . . . . 116
Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . .128
A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . .129
A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . .129
32-bit counter/timer block diagram. . . . . . . . . . .130
Watchdog block diagram . . . . . . . . . . . . . . . . . .135
System tick timer block diagram . . . . . . . . . . . .137
Boot process flowchart . . . . . . . . . . . . . . . . . . .148
IAP parameter passing . . . . . . . . . . . . . . . . . . .162
Algorithm for generating a 128 bit signature . . .171
Connecting the SWD pins to a standard SWD
connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Cortex-M0 implementation. . . . . . . . . . . . . . . . .174
Processor core register set . . . . . . . . . . . . . . . .177
APSR, IPSR, EPSR register bit assignments . .178
Generic ARM Cortex-M0 memory map . . . . . . .183
Memory ordering restrictions . . . . . . . . . . . . . . .184
Little-endian format . . . . . . . . . . . . . . . . . . . . . .186
Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
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Fig 42.
Fig 43.
Fig 44.
Fig 45.
Fig 46.
Fig 47.
Exception entry stack contents . . . . . . . . . . . . . 191
ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
LSR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
LSL #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
ROR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
IPR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
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Rev. 1 — 20 October 2010
© NXP B.V. 2010. All rights reserved.
250 of 258
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Chapter 20: LPC1102 Supplementary information
20.6 Contents
Chapter 1: LPC1102 Introductory information
1.1
1.2
1.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
1.4
1.5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 6
2.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: LPC1102 Memory mapping
2.1
How to read this chapter . . . . . . . . . . . . . . . . . . 7
Chapter 3: LPC1102 System configuration
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
3.5.14
3.5.15
3.5.16
3.5.17
3.5.18
3.5.19
3.5.20
3.5.21
3.5.22
3.5.23
3.5.24
3.5.25
3.5.26
3.5.27
How to read this chapter . . . . . . . . . . . . . . . . . . 9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clocking and power control . . . . . . . . . . . . . . . 9
Register description . . . . . . . . . . . . . . . . . . . . 10
System memory remap register . . . . . . . . . . . 12
Peripheral reset control register . . . . . . . . . . . 12
System PLL control register . . . . . . . . . . . . . . 13
System PLL status register. . . . . . . . . . . . . . . 13
System oscillator control register . . . . . . . . . . 13
Watchdog oscillator control register . . . . . . . . 14
Internal resonant crystal control register. . . . . 15
System reset status register . . . . . . . . . . . . . . 16
System PLL clock source select register . . . . 16
System PLL clock source update enable
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Main clock source select register . . . . . . . . . . 17
Main clock source update enable register . . . 17
System AHB clock divider register . . . . . . . . . 18
System AHB clock control register . . . . . . . . . 18
SPI0 clock divider register . . . . . . . . . . . . . . . 20
UART clock divider register . . . . . . . . . . . . . . 20
WDT clock source select register . . . . . . . . . . 20
WDT clock source update enable register . . . 21
WDT clock divider register . . . . . . . . . . . . . . . 21
POR captured PIO status register 0 . . . . . . . . 21
BOD control register . . . . . . . . . . . . . . . . . . . . 22
System tick counter calibration register . . . . . 23
Start logic edge control register 0 . . . . . . . . . . 23
Start logic signal enable register 0 . . . . . . . . . 24
Start logic reset register 0 . . . . . . . . . . . . . . . . 25
Start logic status register 0 . . . . . . . . . . . . . . 25
Deep-sleep mode configuration register. . . . . 26
3.5.28
3.5.29
3.5.30
3.6
3.7
3.8
3.8.1
3.8.1.1
3.8.2
3.8.2.1
3.8.2.2
3.8.2.3
3.8.3
3.8.3.1
3.8.3.2
3.8.3.3
3.9
3.9.1
3.9.2
3.9.3
Wake-up configuration register . . . . . . . . . . . 27
Power-down configuration register . . . . . . . . 28
Device ID register . . . . . . . . . . . . . . . . . . . . . 29
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Brown-out detection . . . . . . . . . . . . . . . . . . . . 30
Power management . . . . . . . . . . . . . . . . . . . . 30
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power configuration in Active mode. . . . . . . . 31
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power configuration in Sleep mode . . . . . . . . 31
Programming Sleep mode . . . . . . . . . . . . . . . 31
Wake-up from Sleep mode . . . . . . . . . . . . . . 32
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 32
Power configuration in Deep-sleep mode . . . 32
Programming Deep-sleep mode . . . . . . . . . . 32
Wake-up from Deep-sleep mode . . . . . . . . . . 33
Deep-sleep mode details . . . . . . . . . . . . . . . . 33
IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 33
Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Using the general purpose counter/timers to
create a self-wake-up event. . . . . . . . . . . . . . 34
3.10
System PLL functional description . . . . . . . . 34
3.10.1
Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10.2
Power-down control . . . . . . . . . . . . . . . . . . . . 35
3.10.3
Divider ratio programming . . . . . . . . . . . . . . . 36
Post divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Feedback divider . . . . . . . . . . . . . . . . . . . . . . . 36
Changing the divider values. . . . . . . . . . . . . . . 36
3.10.4
Frequency selection. . . . . . . . . . . . . . . . . . . . 36
3.10.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10.4.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 37
3.11
Flash memory access. . . . . . . . . . . . . . . . . . . 37
Chapter 4: LPC1102 PMU (Power Management Unit)
4.1
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register description . . . . . . . . . . . . . . . . . . . . 39
4.2.1
Power control register . . . . . . . . . . . . . . . . . . 39
5.3
5.4
5.4.1
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clocking routine . . . . . . . . . . . . . . . . . . . . . . . 40
set_pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 5: LPC1102 Power profiles
5.1
5.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Chapter 20: LPC1102 Supplementary information
5.4.1.1
5.4.1.2
5.4.1.3
5.4.1.4
5.4.1.4.1
5.4.1.4.2
5.4.1.4.3
5.4.1.4.4
System PLL input frequency and expected system
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
System PLL lock timeout . . . . . . . . . . . . . . . . 42
Code examples. . . . . . . . . . . . . . . . . . . . . . . . 42
Invalid frequency (device maximum clock rate
exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Invalid frequency selection (system clock divider
restrictions) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Exact solution cannot be found (PLL). . . . . . . 43
System clock less than or equal to the expected
value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4.1.4.5 System clock greater than or equal to the
expected value. . . . . . . . . . . . . . . . . . . . . . . . 43
5.4.1.4.6 System clock approximately equal to the expected
value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5
Power routine . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.1
set_power . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.1.1
New system clock . . . . . . . . . . . . . . . . . . . . . 46
5.5.1.2
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5.1.3
Current system clock . . . . . . . . . . . . . . . . . . . 46
5.5.1.4
Code examples . . . . . . . . . . . . . . . . . . . . . . . 47
5.5.1.4.1 Invalid frequency (device maximum clock rate
exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5.1.4.2 An applicable power setup. . . . . . . . . . . . . . . 47
Chapter 6: LPC1102 Interrupt controller
6.1
6.2
How to read this chapter . . . . . . . . . . . . . . . . . 48
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3
6.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 48
7.3.3
7.3.4
7.4
7.4.1
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D-mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . . .
I/O configuration registers IOCON_PIOn. . . .
8.2
Pin configuration. . . . . . . . . . . . . . . . . . . . . . . 61
9.3.6
9.3.7
9.3.8
9.3.9
9.4
9.4.1
GPIO interrupt mask register . . . . . . . . . . . . . 66
GPIO raw interrupt status register . . . . . . . . . 66
GPIO masked interrupt status register. . . . . . 66
GPIO interrupt clear register . . . . . . . . . . . . . 66
Functional description . . . . . . . . . . . . . . . . . . 67
Write/read data operation. . . . . . . . . . . . . . . . 67
Write operation. . . . . . . . . . . . . . . . . . . . . . . . . 67
Read operation . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 7: LPC1102 I/O Configuration
7.1
7.2
7.3
7.3.1
7.3.2
How to read this chapter . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . . .
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
50
50
51
51
52
52
52
53
Chapter 8: LPC1102 Pin configuration
8.1
How to read this chapter . . . . . . . . . . . . . . . . . 61
Chapter 9: LPC1102 General Purpose I/O (GPIO)
9.1
9.2
9.2.1
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
How to read this chapter . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . . .
GPIO data register . . . . . . . . . . . . . . . . . . . . .
GPIO data direction register . . . . . . . . . . . . . .
GPIO interrupt sense register . . . . . . . . . . . . .
GPIO interrupt both edges sense register . . .
GPIO interrupt event register . . . . . . . . . . . . .
63
63
63
63
64
65
65
65
65
Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
10.1
10.2
10.3
10.4
10.5
10.5.1
How to read this chapter . . . . . . . . . . . . . . . . . 69
Basic configuration . . . . . . . . . . . . . . . . . . . . . 69
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 69
Register description . . . . . . . . . . . . . . . . . . . . 69
UART Receiver Buffer Register ( DLAB = 0, Read
Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.5.2
UART Transmitter Holding Register (DLAB = 0,
Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.5.3
UART Divisor Latch LSB and MSB Registers
(DLAB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.5.4
UART Interrupt Enable Register ( DLAB = 0) . 72
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10.5.5
UART Interrupt Identification Register (U0IIR 0x4004 8008, Read Only) . . . . . . . . . . . . . . . 73
10.5.6
UART FIFO Control Register (Write Only) . . . 75
10.5.7
UART Line Control Register . . . . . . . . . . . . . 76
10.5.8
UART Line Status Register . . . . . . . . . . . . . . 77
10.5.9
UART Scratch Pad Register . . . . . . . . . . . . . 79
10.5.10 UART Auto-baud Control Register . . . . . . . . 79
10.5.11 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.5.12 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . . 81
10.5.13 UART Fractional Divider Register (U0FDR 0x4000 8028) . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.5.13.1 Baud rate calculation . . . . . . . . . . . . . . . . . . . 83
10.5.13.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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© NXP B.V. 2010. All rights reserved.
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Chapter 20: LPC1102 Supplementary information
10.5.13.1.2 Example 2: UART_PCLK = 12 MHz, BR =
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.14 UART Transmit Enable Register . . . . . . . . . .
10.5.15 UART RS485 Control register . . . . . . . . . . . .
10.5.16 UART RS-485 Address Match register
(U0RS485ADRMATCH - 0x4000 8050) . . . . .
10.5.17
85
85
86
87
10.6
90
90
90
90
91
91
92
93
94
94
95
95
96
96
11.6.9
11.7
11.7.1
RS-485/EIA-485 modes of operation . . . . . . . 87
RS-485/EIA-485 Normal Multidrop Mode
(NMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Chapter 11: LPC1102 SPI0 with SSP
11.1
11.2
11.3
11.4
11.5
11.6
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
How to read this chapter . . . . . . . . . . . . . . . . .
Basic configuration . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . . .
Pin description . . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . . .
SPI/SSP Control Register 0 . . . . . . . . . . . . . .
SPI/SSP0 Control Register 1 . . . . . . . . . . . . .
SPI/SSP Data Register . . . . . . . . . . . . . . . . .
SPI/SSP Status Register . . . . . . . . . . . . . . . .
SPI/SSP Clock Prescale Register . . . . . . . . .
SPI/SSP Interrupt Mask Set/Clear Register .
SPI/SSP Raw Interrupt Status Register . . . . .
SPI/SSP Masked Interrupt Status Register . .
SPI/SSP Interrupt Clear Register . . . . . . . . . 97
Functional description . . . . . . . . . . . . . . . . . . 97
Texas Instruments synchronous serial frame
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.7.2
SPI frame format . . . . . . . . . . . . . . . . . . . . . . 98
11.7.2.1 Clock Polarity (CPOL) and Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.7.2.2 SPI format with CPOL=0,CPHA=0. . . . . . . . . 99
11.7.2.3 SPI format with CPOL=0,CPHA=1. . . . . . . . 100
11.7.2.4 SPI format with CPOL = 1,CPHA = 0. . . . . . 100
11.7.2.5 SPI format with CPOL = 1,CPHA = 1. . . . . . 102
11.7.3
Semiconductor Microwire frame format . . . . 102
11.7.3.1 Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 104
Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.7.1
How to read this chapter . . . . . . . . . . . . . . . .
Basic configuration . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin description . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
Interrupt Register (TMR16B0IR and
TMR16B1IR). . . . . . . . . . . . . . . . . . . . . . . . .
12.7.2
Timer Control Register (TMR16B0TCR and
TMR16B1TCR) . . . . . . . . . . . . . . . . . . . . . . .
105
105
105
105
105
106
106
108
108
12.7.3
12.7.4
12.7.5
12.7.6
12.7.7
12.7.8
12.7.9
Timer Counter register . . . . . . . . . . . . . . . . . 108
Prescale Register . . . . . . . . . . . . . . . . . . . . 109
Prescale Counter register . . . . . . . . . . . . . . 109
Match Control Register . . . . . . . . . . . . . . . . 109
Match Registers 0 to 3 . . . . . . . . . . . . . . . . . . 111
External Match Register. . . . . . . . . . . . . . . . . 111
PWM Control register (TMR16B0PWMC and
TMR16B1PWMC) . . . . . . . . . . . . . . . . . . . . . 113
12.7.10 Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.8
Example timer operation . . . . . . . . . . . . . . . . 115
12.9
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.7.1
How to read this chapter . . . . . . . . . . . . . . . .
Basic configuration . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin description . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
Interrupt Register (TMR32B0IR and
TMR32B1IR). . . . . . . . . . . . . . . . . . . . . . . . .
13.7.2
Timer Control Register (TMR32B0TCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . .
13.7.3
Timer Counter (TMR32B0TC - address
0x4001 4008 and TMR32B1TC - address
0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . .
117
117
117
117
118
118
118
13.7.4
13.7.5
13.7.6
13.7.7
120
121
13.7.8
13.7.9
13.7.10
121
13.7.11
UM10429
User manual
Prescale Register (TMR32B0PR - address
0x4001 400C and TMR32B1PR - address
0x4001 800C) . . . . . . . . . . . . . . . . . . . . . . . 121
Prescale Counter Register (TMR32B0PC address 0x4001 4010 and TMR32B1PC - address
0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 121
Match Control Register (TMR32B0MCR and
TMR32B1MCR) . . . . . . . . . . . . . . . . . . . . . . 122
Match Registers (TMR32B0MR0/1/2/3 and
TMR32B1MR0/1/2/3) . . . . . . . . . . . . . . . . . . 123
Capture Control Register (TMR32B1CCR) . 123
Capture Register (TMR32B1CR0 - address
0x4001 802C) . . . . . . . . . . . . . . . . . . . . . . . 124
External Match Register (TMR32B0EMR and
TMR32B1EMR) . . . . . . . . . . . . . . . . . . . . . . 124
Count Control Register (TMR32B0CTCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . 126
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 October 2010
© NXP B.V. 2010. All rights reserved.
253 of 258
UM10429
NXP Semiconductors
Chapter 20: LPC1102 Supplementary information
13.7.12
13.7.13
PWM Control Register (TMR32B0PWMC and
TMR32B1PWMC) . . . . . . . . . . . . . . . . . . . . . 127
Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.8
13.9
Example timer operation . . . . . . . . . . . . . . . 129
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.7.1
Watchdog Mode register (WDMOD 0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Constant register (WDTC 0x4000 4004) . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Feed register (WDFEED 0x4000 4008) . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Value register (WDTV 0x4000 400C) . . . . . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 14: LPC1102 WatchDog Timer (WDT)
14.1
14.2
14.3
14.4
14.5
14.6
14.7
How to read this chapter . . . . . . . . . . . . . . . .
Basic configuration . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
WDT clocking . . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
131
131
131
131
132
132
132
14.7.2
14.7.3
14.7.4
14.8
133
134
134
135
135
Chapter 15: LPC1102 System tick timer
15.1
15.2
15.3
15.4
15.5
15.6
How to read this chapter . . . . . . . . . . . . . . . .
Basic configuration . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
136
136
136
136
137
137
15.6.1
15.6.2
15.6.3
15.6.4
15.7
System Timer Control and status register . . 138
System Timer Reload value register . . . . . . 138
System Timer Current value register . . . . . 138
System Timer Calibration value register
(SYST_CALIB - 0xE000 E01C) . . . . . . . . . . 138
Example timer calculations . . . . . . . . . . . . . 139
Example (system clock = 50 MHz). . . . . . . . . 139
Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
16.1
16.2
16.3
16.4
16.5
16.6
16.6.1
16.6.2
How to read this chapter . . . . . . . . . . . . . . . .
Basic configuration . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin description . . . . . . . . . . . . . . . . . . . . . . . .
ADC clocking . . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
A/D Control Register . . . . . . . . . . . . . . . . . .
A/D Global Data Register . . . . . . . . . . . . . .
140
140
140
140
141
141
141
143
16.6.3
16.6.4
16.6.5
16.7
16.7.1
16.7.2
16.7.3
A/D Status Register . . . . . . . . . . . . . . . . . . .
A/D Interrupt Enable Register . . . . . . . . . . .
A/D Data Registers . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware-triggered conversion . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy vs. digital receiver . . . . . . . . . . . .
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144
144
145
145
145
145
Chapter 17: LPC1102 Flash memory programming firmware
17.1
How to read this chapter . . . . . . . . . . . . . . . .
17.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3
General description . . . . . . . . . . . . . . . . . . . .
17.3.1
Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.2
Memory map after any reset. . . . . . . . . . . . .
17.3.3
Criterion for Valid User Code . . . . . . . . . . . .
17.3.4
Boot process flowchart . . . . . . . . . . . . . . . . .
17.3.5
Sector numbers . . . . . . . . . . . . . . . . . . . . . .
17.3.6
Flash content protection mechanism . . . . . .
17.3.7
Code Read Protection (CRP) . . . . . . . . . . . .
17.4
UART Communication protocol . . . . . . . . . .
17.4.1
UART ISP command format . . . . . . . . . . . . .
17.4.2
UART ISP response format . . . . . . . . . . . . .
17.4.3
UART ISP data format . . . . . . . . . . . . . . . . .
17.4.4
UART ISP flow control . . . . . . . . . . . . . . . . .
17.4.5
UART SP command abort . . . . . . . . . . . . . .
17.4.6
Interrupts during UART ISP . . . . . . . . . . . . .
17.4.7
Interrupts during IAP. . . . . . . . . . . . . . . . . . .
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17.4.8
17.4.9
17.5
17.5.1
17.5.2
RAM used by ISP command handler. . . . . . 152
RAM used by IAP command handler. . . . . . 152
UART ISP commands . . . . . . . . . . . . . . . . . . 152
Unlock <Unlock code> (UART ISP) . . . . . . . 153
Set Baud Rate <Baud Rate> <stop bit> (UART
ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
17.5.3
Echo <setting> (UART ISP) . . . . . . . . . . . . . 154
17.5.4
Write to RAM <start address> <number of bytes>
(UART ISP) . . . . . . . . . . . . . . . . . . . . . . . . . 154
17.5.5
Read Memory <address> <no. of bytes> (UART
ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
17.5.6
Prepare sector(s) for write operation <start sector
number> <end sector number> (UART ISP) 155
17.5.7
Copy RAM to flash <Flash address> <RAM
address> <no of bytes> (UART ISP) . . . . . . 156
17.5.8
Go <address> <mode> (UART ISP) . . . . . . 157
17.5.9
Erase sector(s) <start sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 158
All information provided in this document is subject to legal disclaimers.
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17.5.10
17.5.11
17.5.12
17.5.13
17.5.14
17.5.15
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.6.5
17.6.6
17.6.7
17.6.8
17.6.9
Blank check sector(s) <sector number> <end
sector number> (UART ISP). . . . . . . . . . . . . 158
Read Part Identification number (UART ISP) 158
Read Boot code version number (UART ISP) 159
Compare <address1> <address2> <no of bytes>
(UART ISP). . . . . . . . . . . . . . . . . . . . . . . . . . 159
ReadUID (UART ISP) . . . . . . . . . . . . . . . . . . 159
UART ISP Return Codes . . . . . . . . . . . . . . . 160
IAP commands . . . . . . . . . . . . . . . . . . . . . . . . 160
Prepare sector(s) for write operation (IAP) . . 162
Copy RAM to flash (IAP) . . . . . . . . . . . . . . . 163
Erase Sector(s) (IAP) . . . . . . . . . . . . . . . . . . 164
Blank check sector(s) (IAP) . . . . . . . . . . . . . 164
Read Part Identification number (IAP) . . . . . 164
Read Boot code version number (IAP) . . . . . 165
Compare <address1> <address2> <no of bytes>
(IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Reinvoke ISP (IAP). . . . . . . . . . . . . . . . . . . . 165
ReadUID (IAP) . . . . . . . . . . . . . . . . . . . . . . . 166
17.6.10 IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 166
17.7
Debug notes . . . . . . . . . . . . . . . . . . . . . . . . . 166
17.7.1
Comparing flash images . . . . . . . . . . . . . . . 166
17.7.2
Serial Wire Debug (SWD) flash programming
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
17.8
Flash memory access. . . . . . . . . . . . . . . . . . 167
17.9
Flash signature generation . . . . . . . . . . . . . 167
17.9.1
Register description for signature generation 168
17.9.1.1 Signature generation address and control
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
17.9.1.2 Signature generation result registers . . . . . . 169
17.9.1.3 Flash Module Status register . . . . . . . . . . . 169
17.9.1.4 Flash Module Status Clear register . . . . . . . 170
17.9.2
Algorithm and procedure for signature
generation . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Signature generation . . . . . . . . . . . . . . . . . . . 170
Content verification . . . . . . . . . . . . . . . . . . . . 171
Chapter 18: LPC1102 Serial Wire Debug (SWD)
18.1
18.2
18.3
18.4
How to read this chapter . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
172
172
172
172
18.5
18.6
18.6.1
18.6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . .
Debug notes . . . . . . . . . . . . . . . . . . . . . . . . .
Debug limitations . . . . . . . . . . . . . . . . . . . . .
Debug connections . . . . . . . . . . . . . . . . . . .
172
173
173
173
Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
19.1
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 174
About the Cortex-M0 processor and core
peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
19.2.1
System-level interface . . . . . . . . . . . . . . . . . 175
19.2.2
Integrated configurable debug . . . . . . . . . . . 175
19.2.3
Cortex-M0 processor features summary . . . 175
19.2.4
Cortex-M0 core peripherals . . . . . . . . . . . . . 175
19.3
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
19.3.1
Programmers model . . . . . . . . . . . . . . . . . . . 176
19.3.1.1 Processor modes . . . . . . . . . . . . . . . . . . . . . 176
19.3.1.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
19.3.1.3 Core registers . . . . . . . . . . . . . . . . . . . . . . . 176
19.3.1.3.1 General-purpose registers . . . . . . . . . . . . . . 177
19.3.1.3.2 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . 177
19.3.1.3.3 . . . . . . . . . . . . . . . . . . . . . . . . .Link Register 178
19.3.1.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . 178
19.3.1.3.5 Program Status Register . . . . . . . . . . . . . . . 178
19.3.1.3.6 Exception mask register . . . . . . . . . . . . . . . . 180
19.3.1.3.7 CONTROL register . . . . . . . . . . . . . . . . . . . . 180
19.3.1.4 Exceptions and interrupts . . . . . . . . . . . . . . . 181
19.3.1.5 Data types. . . . . . . . . . . . . . . . . . . . . . . . . . . 181
19.3.1.6 The Cortex Microcontroller Software Interface
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
19.3.2
Memory model . . . . . . . . . . . . . . . . . . . . . . . 182
19.3.2.1 Memory regions, types and attributes. . . . . . 183
19.3.2.2 Memory system ordering of memory accesses . .
184
19.3.2.3 Behavior of memory accesses . . . . . . . . . . . 184
19.3.2.4 Software ordering of memory accesses . . . . 185
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19.3.2.5 Memory endianness. . . . . . . . . . . . . . . . . . .
19.3.2.5.1 Little-endian format . . . . . . . . . . . . . . . . . . .
19.3.3
Exception model . . . . . . . . . . . . . . . . . . . . .
19.3.3.1 Exception states. . . . . . . . . . . . . . . . . . . . . .
19.3.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . .
19.3.3.3 Exception handlers . . . . . . . . . . . . . . . . . . .
19.3.3.4 Vector table . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.3.5 Exception priorities. . . . . . . . . . . . . . . . . . . .
19.3.3.6 Exception entry and return . . . . . . . . . . . . . .
19.3.3.6.1 Exception entry . . . . . . . . . . . . . . . . . . . . . .
19.3.3.6.2 Exception return. . . . . . . . . . . . . . . . . . . . . .
19.3.4
Fault handling . . . . . . . . . . . . . . . . . . . . . . .
19.3.4.1 Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.5
Power management. . . . . . . . . . . . . . . . . . .
19.3.5.1 Entering sleep mode . . . . . . . . . . . . . . . . . .
19.3.5.1.1 Wait for interrupt . . . . . . . . . . . . . . . . . . . . .
19.3.5.1.2 Wait for event. . . . . . . . . . . . . . . . . . . . . . . .
19.3.5.1.3 Sleep-on-exit . . . . . . . . . . . . . . . . . . . . . . . .
19.3.5.2 Wake-up from sleep mode . . . . . . . . . . . . . .
19.3.5.2.1 Wake-up from WFI or sleep-on-exit . . . . . . .
19.3.5.2.2 Wake-up from WFE . . . . . . . . . . . . . . . . . . .
19.3.5.3 Power management programming hints . . .
19.4
Instruction set . . . . . . . . . . . . . . . . . . . . . . . .
19.4.1
Instruction set summary. . . . . . . . . . . . . . . .
19.4.2
Intrinsic functions . . . . . . . . . . . . . . . . . . . . .
19.4.3
About the instruction descriptions . . . . . . . .
19.4.3.1 Operands . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.3.2 Restrictions when using PC or SP . . . . . . . .
19.4.3.3 Shift Operations . . . . . . . . . . . . . . . . . . . . . .
All information provided in this document is subject to legal disclaimers.
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19.4.3.3.1 ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.3.3.2 LSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.3.3.3 LSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.3.3.4 ROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.3.4 Address alignment . . . . . . . . . . . . . . . . . . . .
19.4.3.5 PC-relative expressions . . . . . . . . . . . . . . . .
19.4.3.6 Conditional execution . . . . . . . . . . . . . . . . . .
19.4.3.6.1 The condition flags . . . . . . . . . . . . . . . . . . . .
19.4.3.6.2 Condition code suffixes . . . . . . . . . . . . . . . .
19.4.4
Memory access instructions . . . . . . . . . . . . .
19.4.4.1 ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.1.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.1.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.1.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.1.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.2 LDR and STR, immediate offset . . . . . . . . . .
19.4.4.2.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.2.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.2.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.2.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.3 LDR and STR, register offset . . . . . . . . . . . .
19.4.4.3.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.3.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.3.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.3.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.4 LDR, PC-relative. . . . . . . . . . . . . . . . . . . . . .
19.4.4.4.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.4.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.4.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.4.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5 LDM and STM . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.5.6 Incorrect examples . . . . . . . . . . . . . . . . . . . .
19.4.4.6 PUSH and POP . . . . . . . . . . . . . . . . . . . . . .
19.4.4.6.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.6.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.6.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.6.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.4.6.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5
General data processing instructions . . . . . .
19.4.5.1 ADC, ADD, RSB, SBC, and SUB . . . . . . . . .
19.4.5.1.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.1.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.1.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.2 AND, ORR, EOR, and BIC . . . . . . . . . . . . . .
19.4.5.2.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.2.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.5.2.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
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206
206
206
206
206
207
207
207
207
207
207
207
208
208
208
209
209
209
210
210
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19.4.5.2.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.4.5.3 ASR, LSL, LSR, and ROR . . . . . . . . . . . . . . . 211
19.4.5.3.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.4.5.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
19.4.5.3.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 212
19.4.5.3.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 212
19.4.5.3.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
19.4.5.4 CMP and CMN. . . . . . . . . . . . . . . . . . . . . . . 212
19.4.5.4.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.4.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.4.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.4.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.5 MOV and MVN. . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.5.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.4.5.5.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.4.5.5.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.4.5.5.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 214
19.4.5.5.5 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.4.5.6 MULS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.4.5.6.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.4.5.6.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.4.5.6.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.4.5.6.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 215
19.4.5.6.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.4.5.7 REV, REV16, and REVSH . . . . . . . . . . . . . . 215
19.4.5.7.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.4.5.7.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.4.5.7.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.7.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.7.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.8 SXT and UXT. . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.8.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.8.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.8.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.8.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 216
19.4.5.8.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.5.9 TST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.5.9.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.5.9.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.5.9.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.5.9.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.5.9.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.4.6
Branch and control instructions . . . . . . . . . . 217
19.4.6.1 B, BL, BX, and BLX . . . . . . . . . . . . . . . . . . . 218
19.4.6.1.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
19.4.6.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
19.4.6.1.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 218
19.4.6.1.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 219
19.4.6.1.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
19.4.7
Miscellaneous instructions . . . . . . . . . . . . . . 219
19.4.7.1 BKPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.4.7.1.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.4.7.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.4.7.1.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.4.7.1.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 220
19.4.7.1.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.4.7.2 CPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 October 2010
© NXP B.V. 2010. All rights reserved.
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19.4.7.2.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.2.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.2.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.2.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.3 DMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.3.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.3.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.3.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.3.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.4 DSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.4.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.4.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.4.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.4.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.5 ISB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.5.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.5.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.5.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.5.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.5.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.6 MRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.6.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.6.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.6.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.6.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.6.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.7 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.7.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.7.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.7.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.7.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.7.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.8 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.8.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.8.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.8.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.8.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.8.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.9 SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.9.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.9.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.9.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.9.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.9.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.10 SVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.10.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.10.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4.7.10.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . .
220
220
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221
221
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221
221
221
221
221
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221
222
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222
222
222
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222
222
222
222
222
223
223
223
223
223
223
223
223
223
223
223
223
224
224
224
224
224
224
224
224
224
224
224
224
19.4.7.10.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . 224
19.4.7.10.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.11 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.11.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.11.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.11.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.11.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.11.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.12 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.12.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
19.4.7.12.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 226
19.4.7.12.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . 226
19.4.7.12.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . 226
19.4.7.12.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 226
19.5
Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . 226
19.5.1
About the ARM Cortex-M0. . . . . . . . . . . . . . 226
19.5.2
Nested Vectored Interrupt Controller . . . . . . 226
19.5.2.1 Accessing the Cortex-M0 NVIC registers using
CMSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
19.5.2.2 Interrupt Set-enable Register. . . . . . . . . . . . 227
19.5.2.3 Interrupt Clear-enable Register . . . . . . . . . . 228
19.5.2.4 Interrupt Set-pending Register. . . . . . . . . . . 228
19.5.2.5 Interrupt Clear-pending Register . . . . . . . . . 229
19.5.2.6 Interrupt Priority Registers . . . . . . . . . . . . . . 229
19.5.2.7 Level-sensitive and pulse interrupts. . . . . . . 230
19.5.2.7.1 Hardware and software control of interrupts 230
19.5.2.8 NVIC usage hints and tips . . . . . . . . . . . . . . 231
19.5.2.8.1 NVIC programming hints . . . . . . . . . . . . . . . 231
19.5.3
System Control Block. . . . . . . . . . . . . . . . . . 231
19.5.3.1 The CMSIS mapping of the Cortex-M0 SCB
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
19.5.3.2 CPUID Register . . . . . . . . . . . . . . . . . . . . . . 232
19.5.3.3 Interrupt Control and State Register . . . . . . 232
19.5.3.4 Application Interrupt and Reset Control
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
19.5.3.5 System Control Register . . . . . . . . . . . . . . . 235
19.5.3.6 Configuration and Control Register . . . . . . . 236
19.5.3.7 System Handler Priority Registers . . . . . . . . 236
19.5.3.7.1 System Handler Priority Register 2 . . . . . . . 236
19.5.3.7.2 System Handler Priority Register 3 . . . . . . . 237
19.5.3.8 SCB usage hints and tips. . . . . . . . . . . . . . . 237
19.5.4
System timer, SysTick . . . . . . . . . . . . . . . . . 237
19.5.4.1 SysTick Control and Status Register . . . . . . 238
19.5.4.2 SysTick Reload Value Register . . . . . . . . . . 238
19.5.4.2.1 Calculating the RELOAD value . . . . . . . . . . 238
19.5.4.3 SysTick Current Value Register . . . . . . . . . . 238
19.5.4.4 SysTick Calibration Value Register . . . . . . . 239
19.5.4.5 SysTick usage hints and tips . . . . . . . . . . . . 239
19.6
Cortex-M0 instruction summary . . . . . . . . . 239
Chapter 20: LPC1102 Supplementary information
20.1
20.2
20.3
20.3.1
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . .
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . .
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243
244
244
20.3.2
20.3.3
20.4
20.5
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 October 2010
244
244
245
249
© NXP B.V. 2010. All rights reserved.
257 of 258
UM10429
NXP Semiconductors
Chapter 20: LPC1102 Supplementary information
20.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
258
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 October 2010
Document identifier: UM10429
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