LPC-P2919 development prototype board

LPC-P2919 development prototype board
LPC-P2919 development board
Users Manual
All boards produced by Olimex are ROHS compliant
Rev.A, October 2009
Copyright(c) 2011, OLIMEX Ltd, All rights reserved
Page 1
INTRODUCTION:
LPC-P2919 board is easy to use development board with LPC2919 - ARM9
microcontroller with CAN and LIN produced by NXP Semiconductors.
With LPC-P2919 you can explore the features of LPC29XX family on budged, the
board has everything necessary to build simple applications: reset and oscillator
circuits, JTAG port for programming and debugging, CAN, LIN, RS232, SD/MMC,
LCD, three status LEDs and two user buttons.
There are plenty of GPIOs on extension headers where you can connect your
additional circuits.
BOARD FEATURES:
-
CPU: LPC2919FBD144 32 bit combine an ARM968E-S CPU core with two
integrated TCM blocks operating at frequencies of 80 MHz, CAN and LIN, 48
kB SRAM, 768 kB flash memory, external memory interface, two 10-bit ADCs,
and multiple serial and parallel interfaces in a single chip.
JTAG connector with ARM 2x10 pin layout for programming/debugging with
ARM-JTAG, ARM-USB-OCD, ARM-USB-TINY
-
RS232 port
-
two CAN drivers and connectors
-
two LIN drivers and connectors
-
LCD 8X1
-
SD/MMC card connector
-
two user buttons
-
trimpot connected to ADC
-
RESET circuit
-
RESET button
-
three status LEDs
-
power supply LED
-
jumper for Power Selection mode
-
three on board voltage regulators 1.8V, 3.3V and 5V with up to 800mA current
-
single power supply: External power supply +9VDC required, or takes power
from JTAG connector
-
16 Mhz crystal oscillator
-
UEXT connector with SPI, RS232 and power supply for connecting add-on
modules
-
Extension port connector for many of microcontrollers pins
-
Prototype area
-
PCB: FR-4, 1.5 mm (0,062"), red soldermask, silkscreen component print
-
Dimensions: 140x89mm (5.512x3.504")
Page 2
ELECTROSTATIC WARNING:
The LPC-P2919 board is shipped in protective anti-static packaging. The board must
not be subject to high electrostatic potentials. General practice for working with
static sensitive devices should be applied when working with this board.
BOARD USE REQUIREMENTS:
Cables: The cable you will need depends on the programmer/debugger you use. If
you use ARM-USB-OCD, you will need RS232 cable and 1.8 meter USB A-B cable
and if you use ARM-USB-TINY, you will need 1.8 meter USB A-B cable.
Hardware: Programmer/Debugger – one of the Olimex ARM Programmers: ARMUSB-OCD, ARM-USB-TINY.
Software: ARM C compiler and JTAG programmer, the possible options are:
- open source platform: GNU C compiler + OpenOCD and Eclipse
PROCESSOR FEATURES:
LPC-P2919 board use ARM9 32-bit microcontroller LPC2919FBD144 from NXP
Semiconductors with these features:
–
ARM968E-S processor at 80 MHz maximum
–
Multi-layer AHB system bus at 80 MHz with three separate layers
–
On-chip memory:
–
Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16
kB Data TCM (DTCM).
–
Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and
16 kB SRAM.
–
768 kB flash-program memory.
–
Two-channel CAN controller supporting Full-CAN and extensive message
filtering.
–
Two LIN master controllers with full hardware support for LIN communication
–
Two 550 UARTs with 16-byte Tx and Rx FIFO depths.
–
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations
deep; Tx FIFO and Rx FIFO.
–
Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
–
32-bit watchdog with timer change protection, running on safe clock.
–
108 general-purpose I/O pins with programmable pull-up, pull-down or bus
keeper.
–
Vectored Interrupt Controller (VIC) with 16 priority levels.
Page 3
–
Two 8-channel 10-bit ADCs provide a total 16 analog inputs, with conversion
times as low as 2.44 μs per channel. Each channel provides a compare function
to minimize interrupts.
–
24 level-sensitive external interrupt pins, including CAN and LIN wake- up
features.
–
External Static Memory Controller (SMC) with eight memory banks; up to 32bit data bus; up to 24-bit address bus.
–
Processor wake-up from power-down via external interrupt pins; CAN or LIN
activity.
–
Flexible Reset Generator Unit (RGU) able to control resets of individual
modules.
–
Flexible Clock-Generation Unit (CGU) able to control clock frequency of
individual modules.
–
–
On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz;
always on to provide a Safe_Clock source for system monitoring.
–
On-chip crystal oscillator with operating range from 10 MHz to 50 MHz
- max. PLL input 15 MHz.
–
On-chip PLL allows CPU operation up to a maximum CPU rate of 80
MHz.
–
Generation of up to 10 base clocks.
–
Seven fractional dividers.
Highly configurable system Power Management Unit (PMU).
–
clock control of individual modules.
–
allows minimization of system operating power consumption in any
configuration.
–
Standard ARM test and debug interface with real-time in-circuit emulator.
–
Boundary-scan test supported.
–
Dual power supply:
–
–
CPU operating voltage: 1.8 V ± 5%.
–
I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
−40 °C to 85 °C ambient operating temperature range.
Page 4
Block Diagram:
Page 5
MEMORY MAP:
For more details see LPC2919FBD144 datasheet.
Page 6
CAN1_L
SPLIT
R1 10
1 0k
R48
10k
R46
10k
2
3
R5 0
1 0k
R1
330 R
Page 7
2 VCC
6 VAC
9-12 VDC
PWR_JACK
C84
R8
33 k
C36
C43
C14
C27
3
1
IN
OUT
C18
100nF
C37
R54
C28
3 90R/1%
10uF/6.3V(NA)
R4
2 40R/1%
ADJ/GND
OUT
D7
BAT5 4C
VR3(3.3V)
L M1117IMPX-ADJ
IN
93
95
96
97
102
103
105
106
112
113
114
115
121
122
123
124
125
126
132
133
138
139
140
142
3
4
5
6
7
8
14
15
108
1
144
36
37
72
73
10uF/6.3V(NA)
R3
10 0R/1%
2 20R/1%
R2
C15
ADC2_IN7
UART1_ TXD
UART1_RXD
CP
WP
L ED3
L IN0 _TXD
LIN0_RXD
ADJ/GND
100nF
C25
10 0nF
C9
JTASEL
TDO
TDI
TMS
TCK
TRSTN
RSTN
VR2(1.8V)
LM111 7IMPX-ADJ
0R
107
110
109
111
BUT1
2
2
C29
CL O SE
3.3V_E
1
C24
100nF
C26
PWR
R55
330R
C22
1
CLO SE
1 .8V_ E
L PC2919 FBD144
R11
33k
SMD12x1 2x4.3
BUT1
BUT2
56 0R
C23
100nF
R76
R20
33k
3 .3V
S M D 1 2 x1 2 x4 . 3
BUT2
3.3V
1 .8V
3.3V
G ND_
1 .8V
R6 6
3 3k
3.3 V
LED1
LIN0_NSLP
L IN1 _NSLP
CAN1_STB
CAN1_TXD
CAN1_ RXD
LIN1_TXD
LIN1_RXD
SPI2_SCS0
SPI2 _MO SI
SPI2_MISO
SPI2_SCK
L ED2
CAN0_STB
CAN0_TXD
CAN0_ RXD
98
99
118
120
134
135
12
13
23
24
47
48
58
61
80
81
UEXT-1
UEXT-2
UEXT-3
UEXT-4
UEXT-5
UEXT-6
UEXT-7
UEXT-8
UEXT-9
UEXT-10
UART1_TXD
UART1_ RXD
P1.11
P1.10
SPI2_MISO
SPI2 _MO SI
SPI2_SCK
SPI2_SCS0
3.3 V
R64
4.7k
3.3 V
BUT1
BUT2
MMC_PW R
SPI0 _SCS0
SPI0_SCK
SPI0_MISO
SPI0_ MO SI
RS
RW
E
DB4
DB5
DB6
DB7
TXD0
RXD0
P1 .10
P1.11
LED1
45
46
54
55
62
63
69
79
83
84
91
92
100
101
116
117
129
130
136
137
143
2
10
11
16
17
27
28
90
87
86
85
71
70
68
67
66
64
57
56
52
51
50
49
44
42
41
40
39
38
35
34
33
32
30
29
26
25
22
20
R9 0
560R
LED1
red
3.3 V
R65
4.7k
3.3 V
P2.14
P2 .15
P2.16
P2.17
P2.18
P2.19
P2.20
P2.21
P2 .22
P2.23
P2.2 4
P2 .25
P2.0
P2.1
P2 .2
P2.3
P2.4
P2 .5
P2.6
P2.7
P2.8
P1.24
P1.12
P1.13
P1.14
P1.15
P1.1 6
P1 .17
P1.18
P1.19
P1.20
P1.21
P1 .0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1 .7
P1.8
P1.9
LED2
R8 9
560R
LED2
red
3.3 V
LED3
R7
560R
LED3
red
3.3 V
USER'S LEDS
UEXT
P3.0/PWM2_MAT0/EXTBUS_CS6
P3.1/PWM2_MAT1/EXTBUS_CS7
P3.2/TIMER3_MAT0/PWM2_MAT2
P3.3/TIMER3_MAT1/PWM2_MAT3
P3.4/TIMER3_MAT2/PWM2_MAT4/CAN1_TXD
P3.5/TIMER3_MAT3/PWM2_MAT5/CAN1_RXD
P3.6/SPI0_SCS3/PWM1_MAT0/LIN1_TXD
P3.7/SPI2_SCS1/PWM1_MAT1/LIN1_RXD
P3.8/SPI2_SCS0/PWM1_MAT2
P3.9/SPI2_SDO/PWM1_MAT3
P3.10/SPI2_SDI/PWM1_MAT4
P3.11/SPI2_SCK/PWM1_MAT5
P3.12/SPI1_SCS0/EXTINT4
P3.13/SPI1_SDO/EXTINT5
P3.14/SPI1_SDI/EXTINT6/CAN0_TXD
P3.15/SPI1_SCK/EXTINT7/CAN0_RXD
P2.0/TIMER2_MAT0/PWM_TRAP3/EXTBUS_D8
P2.1/TIMER2_MAT1/PWM_TRAP2/EXTBUS_D9
P2.2/TIMER2_MAT2/PWM_TRAP1/EXTBUS_D10
P2.3/TIMER2_MAT3/PWM_TRAP0/EXTBUS_D11
P2.4/TIMER1_MAT0/EXTINT0/EXTBUS_D12
P2.5/TIMER1_MAT1/EXTINT1/EXTBUS_D13
P2.6/TIMER1_MAT2/EXTINT2/EXTBUS_D14
P2.7/TIMER1_MAT3/EXTINT3/EXTBUS_D15
P2.8/PWM0_MAT0/SPI0_SCS2
P2.9/PWM0_MAT1/SPI0_SCS1
P2.10/PWM0_MAT2/SPI0_SCS0
P2.11/PWM0_MAT3/SPI0_SCK
P2.12/PWM0_MAT4/SPI0_SDI
P2.13/PWM0_MAT5/SPI0_SDO
P2.14/PWM0_CAP0/EXTBUS_BLS0
P2.15/PWM0_CAP1/EXTBUS_BLS1
P2.16/UART1_TXD/PWM0_CAP2/EXTBUS_BLS2
P2.17/UART1_RXD/PWM1_CAP0/EXTBUS_BLS3
P2.18/PWM1_CAP1/EXTBUS_D16
P2.19/PWM1_CAP2/EXTBUS_D17
P2.20/PWM2_CAP0/EXTBUS_D18
P2.21/PWM2_CAP1/EXTBUS_D19
P2.22/PWM2_CAP2/EXTBUS_D20
P2.23/PWM3_CAP0/EXTBUS_D21
P2.24/PWM3_CAP1/EXTBUS_D22
P2.25/PWM3_CAP2/EXTBUS_D23
P2.26/TIMER0_CAP2/TIMER0_MAT2/EXTINT6
P2.27/TIMER0_CAP3/TIMER0_MAT3/EXTINT7
P1.0/EXTINT0/PWM3_MAT0/EXTBUS_A0
P1.1/EXTINT1/PWM3_MAT1/EXTBUS_A1
P1.2/SPI2_SCS3/PWM3_MAT2/EXTBUS_A2
P1.3/SPI2_SCS1/PWM3_MAT3/EXTBUS_A3
P1.4/SPI2_SCS2/PWM3_MAT4/EXTBUS_A4
P1.5/SPI1_SCS1/PWM3_MAT5/EXTBUS_A5
P1.6/SPI1_SCS2/UART1_TXD/EXTBUS_A6
P1.7/SPI1_SCS3/UART1_RXD/EXTBUS_A7
P1.8/SPI1_SCS0/LIN1_TXD/EXTBUS_CS0
P1.9/SPI1_SDO/LIN1_RXD/EXTBUS_CS1
P1.10/SPI1_SDI/EXTBUS_CS2
P1.11/SPI1_SCK/EXTBUS_CS3
P1.12/EXTINT2/EXTBUS_OEN
P1.13/EXTINT3/EXTBUS_WEN
P1.14/TIMER2_CAP0/SPI0_SCS3/EXTBUS_D0
P1.15/TIMER2_CAP1/SPI0_SCS0/EXTBUS_D1
P1.16/TIMER2_CAP2/SPI0_SCK/EXTBUS_D2
P1.17/TIMER2_CAP3/SPI0_SDI/EXTBUS_D3
P1.18/TIMER3_CAP0/SPI0_SDO/EXTBUS_D4
P1.19/TIMER3_CAP1/SPI0_SCS2/EXTBUS_D5
P1.20/TIMER3_CAP2/SPI0_SCS1/EXTBUS_D6
P1.21/TIMER3_CAP3/TIMER1_CAP3,MSCSS_PAUSE/EXTBUS_D7
P1.22/UART0_TXD/EXTBUS_CS4
P1.23/UART0_RXD/EXTBUS_CS5
P1.24/PWM0_MAT0/PWM3_MAT0
P1.25/PWM1_MAT0/PWM3_MAT1
P1.26/PWM2_MAT0/PWM_TRAP3/PWM3_MAT2
P1.27/TIMER1_CAP2/ADC2_EXT_START/PWM_TRAP2/PWM3_MAT3
P1.28/TIMER1_CAP1,ADC1_EXT_START/PWM_TRAP1/PWM3_MAT4
P1.29/TIMER1_CAP0,EXT_START/PWM_TRAP0/PWM3_MAT5
P1.30/TIMER0_CAP0/TIMER0_MAT0/EXTINT4
P1.31/TIMER0_CAP1/TIMER0_MAT1/EXTINT5
56 0R
C47
100nF
R52
P0.0/CAN0_TXD/EXTBUS_D24
P0.1/CAN0_RXD/EXTBUS_D25
P0.2/PWM0_MAT0/EXTBUS_D26
P0.3/PWM0_MAT1/EXTBUS_D27
P0.4/PWM0_MAT2/EXTBUS_D28
P0.5/PWM0_MAT3/EXTBUS_D29
P0.6/PWM0_MAT4/EXTBUS_D30
P0.7/PWM0_MAT5/EXTBUS_D31
P0.8/ADC1_IN0/LIN0_TXD/EXTBUS_A20
P0.9/ADC1_IN1/LIN0_RXD/EXTBUS_A21
P0.10/ADC1_IN2/PWM1_MAT0/EXTBUS_A8
P0.11/ADC1_IN3/PWM1_MAT1/EXTBUS_A9
P0.12/ADC1_IN4/PWM1_MAT2/EXTBUS_A10
P0.13/ADC1_IN5/PWM1_MAT3/EXTBUS_A11
P0.14/ADC1_IN6/PWM1_MAT4/EXTBUS_A12
P0.15/ADC1_IN7/PWM1_MAT5/EXTBUS_A13
P0.16/ADC2_IN0/UART0_TXD/EXTBUS_A22
P0.17/ADC2_IN1/UART0_RXD/EXTBUS_A23
P0.18/ADC2_IN2/PWM2_MAT0/EXTBUS_A14
P0.19/ADC2_IN3/PWM2_MAT1/EXTBUS_A15
P0.20/ADC2_IN4/PWM2_MAT2/EXTBUS_A16
P0.21/ADC2_IN5/PWM2_MAT3/EXTBUS_A17
P0.22/ADC2_IN6/PWM2_MAT4/EXTBUS_A18
P0.23/ADC2_IN7/PWM2_MAT5/EXTBUS_A19
P0.24/UART1_TXD/CAN1_TXD/SPI2_SCS0
P0.25/UART1_RXD/CAN1_RXD/SPI2_SDO
P0.26/SPI2_SDI
P0.27/SPI2_SCK
P0.28/TIMER0_CAP0/TIMER0_MAT0
P0.29/TIMER0_CAP1/TIMER0_MAT1
P0.30/TIMER0_CAP2/TIMER0_MAT2
P0.31/TIMER0_CAP3/TIMER0_MAT3
JTAGSEL
TDO
TDI
TMS
TCK
TRSTN
RSTN
VDD(A3V3)
VREFP
NC
VREFN
XIN_OSC
VSS(OSC)
VSS(PLL)
VDD(OSC)
XOUT_OSC
VSS(CORE)
VSS(CORE)
VSS(CORE)
VSS(CORE)
VDD(CORE)
VDD(CORE)
VDD(CORE)
VDD(CORE)
VSS(IO)
VSS(IO)
VSS(IO)
VSS(IO)
VSS(IO)
VSS(IO)
+
+
R63
330R/1%
C35
4
2
1-2 - +5V_EXT
3-4 - +5V_JLINK
+5V
P0.2 9
P0 .30
P0.31
P0 .10
P0.11
P0.12
P0.13
P0.14
P0.15
P0.1 6
P0 .17
P0.18
P0.1 9
P0 .20
P0.21
P0.22
P0 .0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0 .7
R16
0R(NA)
0R
76
74
78
77
75
128
88
59
19
18
60
89
127
141
119
94
65
43
21
U1
VDD(IO)
VDD(IO)
VDD(IO)
VDD(IO)
VDD(IO)
VDD(IO)
47uF/6.3V
10uF/6 .3V(NA)
R62
3 30R/1%
+5V_JLINK
+5V_EXT
PWR_SEL
+5V
h ttp://www.o limex.co m/dev
CO PYRIG HT(C), 2009
Rev. A
C7
100nF
R15
0R(NA)
Q1
100nF
C19
100nF
C6
16.000MHz/20pF
100nF
C16
100nF
C5
9
31
53
82
104
131
AN_TRIM
10k
100nF
G ND
OUT
ADJ/GND
R61
220R/1%
LIN_PO WER
VR1(5 V)
LM111 7IMPX-ADJ
1 N58 19S
IN
RSTN
C8
10uF/6.3V
LPC-P2919
POWER SUPPLY
D1
330R
R60
RSTN
JTASEL
TDO
TDI
TMS
TCK
TRSTN
RSTN
L1
100nF
C21
100nF
100nF
Ferrite _Bea d
3.3V
C11
C10
C1 2
33pF
C13
33pF
100nF
100nF 100nF 100nF
1.8V
C4
C2
C17
NA
C3
C1
3.3V(I/O )_E
CLO SE
3.3V
1k
R6
+
100u F/16VDC
VIN
3 .3V
REC
DB104S(SMD)
10 0nF
C20
3 .3V
100nF(NA)
3
R12
330R
3 3k
R34
R32
5 60R
red
SD
100n F
C3 3
R56
R68
R69
L2
8
1
8
1
3
R18
4 7uF/6.3V
C59
33k
33k
33k
13
8
14
7
6
2
1k
SPI0_MISO
1
VDD
VO
VSS
DB4
DB5
DB6
DB7
CONTRAST
3 .3V
3.3V
R44
R45
SPI0_MISO
SPI0_SCK
SPI0_SCS0
SPI0_MO SI
33k
2k
33k
2k
13
15
1
2
3
4
5
6
7
8
9
10
14
D5
CP1
CP2
SD-CARD
CP
LIN0
1
2
3
LIN1
TB3-3.5MM
6
7
8
9
G2
WP
1
2
3
TB3-3.5MM
G1
CD/DAT3/CS
CMD/DI
VSS1
VDD
CLK/SCLK
VSS2
DAT0/DO
DAT1/RES
DAT2/RES
WP1
WP2
SD/MMC
1
2
3
4
5
RS2 32_0
DB9-F
RS232
NA
L IN1 _BUS
SD/MMC
R43
R42
2
L IN1 _PW R
CLO SE
1
D3
LIN1_PW R_E
NA
C32
C87
0 R(NA)
#XRESET
#CSB
RS C O N T R O L
S IGN A L S
RW
E
0R
2
LIN0_BUS
NA
G DSC-0801 WP-01-MENT
11
12
10
6
7
8
9
DB4
DB5
DB6
DB7
(0 )
(1 )
LCD
R17
C53
100nF
C52
1 00nF
1
LIN0_PWR
CLO SE
LIN0_PW R_E
C39
2
LIN_PO WER
NA
C3 0
2
L IN1 _MASTER_E
CLO SE
D4
1N4148(SMD)
2
4
5
MMC_PW R
R38
3k
1
LIN_PO W ER
LIN0_MASTER_E
CLO SE
D2
1N4148 (SMD)
RS
RW
E
R13
1
3
R101
1k
R1 9
LCD
R22
1 .5k
RW
SPI0_SCS0
SPI0_MO SI
R40
1 0k
470nH/08 05
33k
NA
1k
R33
+5V
3.3V
R5
1 0k
R1IN
R2IN
T1OUT
T2OUT
V-
V+
C57
1 00nF
ST32 32(SO 16)
R1OUT
R2OUT
T1IN
T2IN
C2-
C2+
C1-
C1+
10k
3.3 V
12
9
10
0R(NA) 11
5
C51
4
100nF
GND15
5
7
6
5
7
6
U6PWR
10k
GND
BAT
LIN
10k
16VCC
U6
TXD
RXD
NSLP
INH
NWAKE
BAT
GND
U2
TJA1020T
R25
TXD
RXD
NSLP
INH
NWAKE
LIN
LIN
U3
TJA10 20T
C50
1
10 0nF
3 .3V
3
2
4
R10
10k
3
2
4
R23
10k
R35
3 30R
R67
R41
RXD0
0R
R9
10k
R14
TXD0
R24
10k
100n F(NA)
C56
R21
10k
3.3V 3.3V 3.3V
R27
3 30R
T4
IRLML640 2
3 .3V
R116
2k
L IN1 _TXD
LIN1_RXD
LIN1_NSLP
L IN0 _TXD
L IN0_ RXD
LIN0_NSLP
R26
10k
3.3V 3.3V 3.3V
1 0k
RESET
GND
RESET 1
NA
U10
MCP130T(NA)
R14 0
TDO
RSTN
TRSTN
TDI
TMS
TCK
R53
NA
3.3V
ADC2_ IN7
3 .3V
USER BUTTONS
DATA
D6
1N4 148(SMD)
3.3V
R57
NA
CAN1_RXD
CAN1_TXD
CAN1 _STB
R58
+5V
C4 1
100n F
0R
3.3V
CAN0_RXD
CAN0_ TXD
CAN0_STB
R59
+5V
C34
100 nF
0R
JTASEL
ARM_DBG _ E
R47
10k
NA
NA
4
R37
1 0R(NA)
8
1
2
R1 09
1 0k
1
3
5
7
9
11
13
15
17
19 +5V_JLINK
R49
10k
3 .3V
GND
VCC
RXD
TXD
STB
2
3
4
R30
1 0 R(NA)
8
3 .3V
POTENTIOMETER
+
RESET CIRCUIT
JTAG
GND
VCC
RXD
TXD
STB
U8
TJA1040T
CANH
R36 6 CANL
5
7
CANL
SPLIT
CANH
R39
NA
1
JTAG
6 2R
1nF C42
R31
R2 9 6
5
7
R51
NA
3.3V
1N4 75 1(B ZX 85C3 0)
2
4
6
8
10
12
14
16
18
20
62R
CAN1_ H
62 R
CAN0_L
2
3
2
1
R28
1nF C38
CAN0 _H
6 2R
U4
TJA1040T
3.3V
1 N475 1(B ZX 85 C30)
CAN1
TB3-3.5MM
3
2
1
CAN0
TB3-3.5MM
CAN
SCHEMATIC
+
47uF/6.3V
+
10uF/6.3V
47uF/6.3V
100nF
+
100nF
BOARD LAYOUT
Page 8
POWER SUPPLY CIRCUIT
LPC-P2919 can take power from two sorces:
–
External power supply 9.0-12.0 V DC or 6.0V AC.
–
+5V_JLINK from JTAG connector
RESET CIRCUIT
LPC-P2919 reset circuit includes pin 15 of JTAG connector, pin 73 of U1 and RESET
button.
CLOCK CIRCUIT
Quartz crystal 16 MHz is connected to LPC-P2919 pin 75 (XOUT_OSC) and pin 76
(XIN_OSC).
JUMPER DESCRIPTION
PWR_SEL
When 1-2 are shorted – the board is supplied from PWR_JACK, when 3-4 are shorted
– the board is supplied from JTAG.
Default state is 1-2.
ARM_DBG_E
When this jumper is shorted – selects the ARM debug mode; when it is open – selects
boundary scan and flash programming; pulled up internally.
Default state is closed.
LIN0_MASTER_E
Enable LIN0 master's pull-up.
Default state is closed.
LIN0_PWR_E
Enable power supply to LIN0.
Default state is closed.
LIN1_MASTER_E
Enable LIN1 master's pull-up.
Default state is closed.
LIN1_PWR_E
Enable power supply to LIN1.
Default state is closed.
Page 9
3.3V(I/O)_E
Connects 6 pins (VDD(IO)) of LPC2919 to 3.3V.
Default state is closed.
1.8V_E
Enable regulator VR2(1.8V) – LM1117
Default state is closed.
3.3V_E
Enable regulator VR3(3.3V) – LM1117
Default state is closed.
INPUT/OUTPUT
SD/MMC LED (red) with name SD connected to SD/MMC pin 4.
Status LED1 (red) with name LED1 connected to LPC2919 pin 98
(P3.0/PWM2_MAT0/EXTBUS_CS6).
Status LED2 (red) with name LED2 connected to LPC2919 pin 58
(P3.12/SPI1_SCS0/EXTINT4).
Status LED3 (red) with name LED3 connected to LPC2919 pin 7
(P0.28/TIMER0_CAP0/TIMER0_MAT0).
Power-on LED (red) with name PWR – this led shows that +3.3V is applied to the
board.
User button with name BUT1 connected to LPC2919 pin 27
(P2.26/TIMER0_CAP2/TIMER0_MAT2/EXTINT6).
User button with name BUT2 connected to LPC2919 pin 28
(P2.27/TIMER0_CAP3/TIMER0_MAT3/EXTINT7).
Reset button with name RESET connected to LPC2919 pin 73 (RSTN).
Trimpot with name AN_TRIM connected to LPC2919 pin 142
(P0.23/ADC2_IN7/PWM2_MAT5/EXTBUS_A19).
LCD 8X1
Page 10
CONNECTOR DESCRIPTIONS
JTAG:
The JTAG connector allows the software debugger to talk via a JTAG (Joint
Test Action Group) port directly to the core. Instructions may be inserted and
executed by the core thus allowing LPC2919 memory to be programmed with code
and executed step by step by the host software.
For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access
Port and Boundary Scan Architecture and LPC2919 datasheets and users manual.
Pin #
Signal Name
Pin #
Signal Name
1
3.3V
2
3.3V
3
TRSTN
4
GND
5
TDI
6
GND
7
TMS
8
GND
9
TCK
10
GND
11
NC
12
GND
13
TDO
14
GND
15
RSTN
16
GND
17
PULL-DOWN
18
GND
19
+5V_JLINK
20
GND
Page 11
RS232:
Pin #
Signal Name
1
NC
2
T2OUT
3
R2IN
4
NC
5
GND
6
NC
7
NC
8
NC
9
NC
UEXT:
Pin #
Signal Name
1
3.3V
2
GND
3
UART1_TXD
4
UART1_RXD
5
P1.11
6
P1.10
7
SPI2_MISO
8
SPI2_MOSI
9
SPI2_SCK
10
SPI2_SCS0
PWR_JACK:
Pin #
Signal Name
1
Power Input
2
GND
Page 12
CAN0:
Pin# Signal
Description
1
GND
Ground
2
CAN0_L
CAN LOW
3
CAN0_H
CAN HIGH
CAN1:
Pin# Signal
Description
1
GND
Ground
2
CAN1_L
CAN LOW
3
CAN1_H
CAN HIGH
LIN0:
Pin# Signal
Description
1
LIN0_PWR LIN Power
2
LIN0_BUS LIN
3
GND
Ground
LIN1:
Pin# Signal
Description
1
LIN1_PWR LIN Power
2
LIN1_BUS LIN
3
GND
Ground
Page 13
SD/MMC
Pin #
Signal Name
Pin #
Signal Name
1
SPI0_SCS0
9
MCIDAT2
2
SPI0_MOSI
10
WP1
3
GND
11
NC
4
3.3V
12
NC
5
SPI0_SCK
13
CP1
6
GND
14
WP2
7
SPI0_MISO
15
CP2
8
MCIDAT1
Page 14
EXT
Pin #
Signal Name
Pin #
Signal Name
1
+5V
2
+3.3V
3
P0.0
4
P0.1
5
P0.2
6
P0.3
7
P0.4
8
P0.5
9
P0.6
10
P0.7
11
P0.10
12
P0.11
13
P0.12
14
P0.13
15
P0.14
16
P0.15
17
P0.16
18
P0.17
19
P0.18
20
P0.19
21
P0.20
22
P0.21
23
P0.22
24
P0.29
25
P0.30
26
P0.31
27
P1.1
28
P1.0
29
P1.3
30
P1.2
31
P1.5
32
P1.4
33
P1.7
34
P1.6
35
P1.9
36
P1.8
37
P1.13
38
P1.13
39
P1.15
40
P1.14
41
P1.17
42
P1.16
43
P1.19
44
P1.18
45
P1.21
46
P1.20
47
P2.0
48
P1.24
49
P2.2
50
P2.1
51
P2.4
52
P2.3
53
P2.6
54
P2.5
55
P2.8
56
P2.7
57
P2.15
58
P2.14
59
P2.17
60
P2.16
61
P2.19
62
P2.18
63
P2.21
64
P2.20
65
P2.23
66
P2.22
67
P2.25
68
P2.24
69
+1.8V
70
GND
Page 15
I2C
The LPC2919 contain two I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a
serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a
unique address and can operate as either a receiver-only device or as a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode,
depending on whether the chip has to initiate a data transfer or is only addressed.
The I2C is a multi-master bus, and it can be controlled by more than one bus master
connected to it.
The main features if the I2C-bus interfaces are:
SPI
–
I2C0 and I2C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2Cbus) and do not support powering off of individual devices connected to the
same bus lines.
–
Easy to configure as master, slave, or master/slave.
–
Programmable clocks allow versatile rate control.
–
Bidirectional data transfer between masters and slaves.
–
Multi-master bus (no central master).
–
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
–
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus.
–
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
–
All I2C-bus controllers support multiple address recognition and a bus monitor
mode.
The LPC2919 contains three Serial Peripheral Interface modules (SPIs) to
allow synchronous serial communication with slave or master peripherals.
The key features are:
–
Master or slave operation.
–
Each SPI supports up to four slaves in sequential multi-slave operation.
–
Supports timer-triggered operation.
–
Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock.
–
Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations
deep.
–
Programmable choice of interface operation: Motorola SPI or Texas Instruments
Synchronous Serial Interfaces.
–
Programmable data-frame size from 4 to 16 bits.
–
Independent masking of transmit FIFO, receive FIFO and receive overrun
interrupts.
Page 16
–
Serial clock-rate master mode: fserial_clk ≤ fCLK(SPI)/2.
–
Serial clock-rate slave mode: fserial_clk = fCLK(SPI)/4.
–
Internal loopback test mode.
The SPI module can operate in:
–
–
Master mode:
–
Normal transmission mode.
–
Sequential slave mode.
Slave mode.
Page 17
MECHANICAL DIMENSIONS
All measures are in inches.
Page 18
AVAILABLE DEMO SOFTWARE
–
Buttons and LCD demo
–
Port_LCD_UART demo
–
SD slot demo
Page 19
ORDER CODE
LPC-P2919 – assembled and tested (no kit, no soldering required)
How to order?
You can order to us directly or by any of our distributors.
Check our web www.olimex.com/dev for more info.
Board revision history:
Rev. A
- created October 2009
Manual revision history:
Rev. A
- created February 2011 – microcontroller features were wrong –
instead of LPC2919FBD144 features, were given for LPC2919FBD144/01.
Page 20
Disclaimer:
© 2011 Olimex Ltd. All rights reserved. Olimex®, logo and combinations thereof, are registered trademarks of
Olimex Ltd. Other terms and product names may be trademarks of others.
The information in this document is provided in connection with Olimex products. No license, express or implied
or otherwise, to any intellectual property right is granted by this document or in connection with the sale of
Olimex products.
Neither the whole nor any part of the information contained in or the product described in this document may be
adapted or reproduced in any material from except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous development and improvements. All particulars
of the product and its use contained in this document are given by OLIMEX in good faith. However all warranties
implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are
excluded.
This document is intended only to assist the reader in the use of the product. OLIMEX Ltd. shall not be liable for
any loss or damage arising from the use of any information in this document or any error or omission in such
information or any incorrect use of the product.
Page 21
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