Software Defined AIS receiver for AAUSAT3

Software Defined AIS receiver for AAUSAT3
Software Defined
AIS Receiver
for
AAUSAT3
Group 651
Troels Jessen
Jeppe Ledet-Pedersen
Hans Peter Mortensen
AAUSAT3
Department of Electronic Systems
Aalborg University
Spring 2009
AAUSAT3
The Faculties of Engineering, Science
Medicine
Department of Electronic Systems
Frederik Bajers Vej 7
and
Phone: +45 99 40 86 00
http://es.aau.dk
Title: Software Defined AIS Receiver for Abstract:
This report documents the development of
AAUSAT3
a software defined AIS receiver for the
Theme: Robust Communication
AAUSAT3 student satellite. AIS is a stanProject period:
dardized protocol designed to enhance safety at
February 2nd - June 3rd, 2009
Project group: 09gr651
Group members:
Troels Jessen
Jeppe Ledet-Pedersen
Hans Peter Mortensen
Supervisor:
Ole Kiel
Number of copies: 6
Number of pages: 60
Appended documents:
(6 appendices, 1 CD-ROM)
Total number of pages: 82
Finished: June 3rd, 2009
sea by automatic exchange of ship information.
The AIS receiver and a prototype of AAUSAT3
will be tested on the BEXUS high-altitude balloon flight in October 2009.
The report begins with an analysis of the AIS
standard with special focus on the physical
and data link layers. The GMSK modulation
scheme, line coding and HDLC framing are analyzed to identify the requirements for the receiver.
Based on these requirements, a non-coherent
demodulator with support for packet detection
and frequency estimation is designed and implemented in MATLAB. A modulator with adjustable signal-to-noise ratio is developed for
testing purposes, and the MATLAB receiver is
successfully tested for receiving both simulated
and real-life AIS signals.
A prototype PCB with a commercial radio
front-end and Analog to Digital Converter has
been constructed, and a Digital Signal Processor is selected for implementation for the
BEXUS flight. The mechanical design for the
balloon flight is documented in a separate section.
Finally, the acceptance test shows that the implemented algorithms are suitable for receiving
and decoding AIS signals. Further work is still
needed to port the receiver to the DSP.
Table of Contents
Preface
v
1 Introduction
1.1 The AAUSAT3 Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 The NAVIS Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Project Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
3
4
2 Analysis
2.1 Automatic Identification System
2.2 Wireless Communication . . . . .
2.3 Line Coding . . . . . . . . . . . .
2.4 Channel Estimation . . . . . . .
2.5 Digital Modulation . . . . . . . .
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5
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12
13
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3 Problem Description
23
3.1 Requirement Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Test Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Design
4.1 Information Source . . .
4.2 AIS Data Encapsulation
4.3 GMSK Modulator . . .
4.4 AWGN Channel . . . .
4.5 Packet Detection . . . .
4.6 Frequency Estimation .
4.7 GMSK Demodulator . .
4.8 AIS Data Extraction . .
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5 Proof of Concept
6 Implementation
6.1 VHF Antenna . . . . . . . . . . . . . . . . .
6.2 Low Noise Amplifier . . . . . . . . . . . . .
6.3 SAW Filter . . . . . . . . . . . . . . . . . .
6.4 Power Splitter . . . . . . . . . . . . . . . . .
6.5 RF Front-end . . . . . . . . . . . . . . . . .
6.6 Analog to Digital Converter . . . . . . . . .
6.7 Digital Signal Processor . . . . . . . . . . .
6.8 Analog Devices ADSP-BF537 Architecture
6.9 PCB Schematics and Layout . . . . . . . .
6.10 Experiment Setup . . . . . . . . . . . . . .
25
26
26
28
29
29
31
32
36
39
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43
43
43
45
47
47
48
49
50
51
52
iii
TABLE OF CONTENTS
7 Acceptance Test
57
8 Conclusion
59
8.1 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A Interface Control Documents
61
B Hardware diagrams
65
C Component List
69
D Work agreement (Danish)
71
E Contents of the CD
77
F Abbreviations
79
Bibliography
81
iv
Preface
This report serves as documentation for the development of a software defined radio for receiving
signals from the Automatic Identification System (AIS). The project is carried out by three 6th
semester Communication Systems students from Aalborg University in Denmark.
The AIS receiver will be the main payload for the AAUSAT3 student satellite, which is planned
to be launched in the spring of 2011. Prior to the launch, the receiver will be tested on the
BEXUS 8 (Balloon EXperiment for University Students) balloon flight in October 2009. The
BEXUS project is jointly sponsored by the European Space Agency (ESA), the Swedish Space
Corporation (SSC), the Swedish National Space Board (SNSB) and the German Aerospace Center
(DLR) and allows European university students to test scientific experiments in high altitude.
The semester has been carried out in close cooperation with group 09gr650, who has developed
an alternative AIS receiver for the satellite. The workload of the semester has been wider than
expected for a normal semester project, as the whole experiment for the BEXUS flight has been
carried out by these two groups. The cooperation of the groups has been named NAVIS (North
Atlantic Vessel Identification System) and has been approved by the Study Board, as described
in section D on page 71. An additional outcome of the NAVIS project is the SED (Student
Experiment Description) which provides an elaborate description of the design and construction
of the experiment. The SED is attached as a separate report and contains information about
the NAVIS experiment not otherwise related to this project. The main purpose of the SED is to
provide this information to the BEXUS involved partners.
Chapter Organization
Chapter 1 serves as an introduction to readers who are unfamiliar with AAUSAT3. The chapter
also describes the NAVIS and BEXUS projects in further details and outlines the scope of this
project.
Chapter 2 analyzes the AIS standard and provides an introduction to wireless communication
systems. A number of digital modulation schemes including Gaussian Minimum Shift Keying
(GMSK) used in AIS is explained in detail, with focus on the AWGN channel and bit error
probability.
Chapter 3 contains the project description and requirement specification of the system.
Chapter 4 describes the design of algorithms used for packet detection, bit synchronization and
the non-coherent GMSK demodulation.
Chapter 5 contains a ”proof of concept” implementation of the AIS receiver using a National
Instruments Sample Card and MATLAB.
Chapter 6 documents the implementation of hardware and software, including schematics, PCB
layout and DSP selection for further development.
Chapter 7 lists the acceptance test of the system.
Chapter 8 contains the conclusion which sum up the results of the report.
The appendices contain hardware diagrams, component lists and Interface Control Documents for
the AIS subsystem.
v
PREFACE
Conventions
References to external sources used in the project are enclosed in brackets. An example reference
to a paper published in 2009 will thus be [Example 09]. The bibliography in page 81 contains a
table with information about all sources used. All sources are also included on the CD. Figures,
tables and code excerpts are numbered for use in cross references. In some cases, the size of the
figures and tables makes it necessary to place it on the following page. The unit Nautical Mile is
abbreviated nmi as recommended by IEEE [IEEE 07].
Acknowledgements
The authors would like to thank Aalborg University, the Danish Maritime Safety Administration
and the rest of the AAUSAT3 sponsors. Without their help, the students satellite project would
not have been possible. ESA, SSC, SNSB and DLR are thanked for selecting the NAVIS project
for inclusion on the BEXUS flight and allowing the AIS receivers to be tested in high altitude
conditions. Jens Dalsgaard Nielsen, Johan Christiansen and the rest of the AAUSAT3 system
engineering group are thanked for providing valuable input and helping out with the preparation
of the NAVIS experiment. Daniel Winther Uhrenholt has been a great help with the experiments
mechanical design and construction.
The authors of the report can be contacted at {09gr650, tjessen, jledet, hp000}@es.aau.dk
Thank you for reading our report!
Troels Jessen
Jeppe Ledet-Pedersen
Hans Peter Mortensen
vi
Chapter 1
Introduction
This chapter serves as a short introduction to readers who are unfamiliar with the AAUSAT3 and
NAVIS projects. The final section of the chapter outlines the scope of this project report.
1.1
The AAUSAT3 Project
AAUSAT3
AAUSAT3 is the third student satellite developed at Aalborg University. The satellite is the
successor to AAUSAT-II which was launched in 2008 and, at the time of writing, has been operational for more than a year — longer than any other Danish student satellite. The AAUSAT3
project was initiated in the fall of 2007 and the satellite is expected to be launched in the first
half of 2011.
The satellite project is jointly sponsored by Aalborg University and the Danish Maritime
Safety Administration (DaMSA) who is responsible for the safety in the seas around Denmark,
Greenland and the Faroe Islands. In the Danish waters, DaMSA monitors the ship traffic using the
Automatic Identification System (AIS) by using strategically placed ground stations and buoys.
The ground stations are placed along the Danish coast line and are used to receive identification
signals from ships, as well as act as electronic lighthouses.
AIS is a data exchange protocol standardized by the International Telecommunication Union
(ITU) and designed to enhance safety at sea by automatic exchange of ship identification data. All
ships with a gross tonnage of more than 300 tons and all ships carrying passengers is required by
law to have an AIS transponder on board. For all other ships it is an optional safety feature. At
regular intervals, AIS transponders broadcasts info such as registration number, position, speed,
destination and name to nearby ships as well as shore based stations. The system is designed to
function autonomously and allow ships to exchange information without influence of an operator.
AIS defines numerous packet types, so not all information is contained in each transmitted packet.
Section 2.1 describes the technical details AIS in further detail.
AIS has several advantages compared to conventional radar systems. First of all, the AIS
signals can be received even if the transmitting ship is hidden by landmass, where traditional
radar systems cannot detect vessels. AIS signals also contains information about more than just
ship position, and the on board AIS receiver is thus often coupled directly to the ships radar
monitor. This allows the ships crew to view the position, course and speed of nearby vessels in
1
CHAPTER 1. INTRODUCTION
one place. Not all ships are required to have AIS equipment on board, so the system does not
give a complete picture of nearby ships. AIS is thus not intended to replace traditional radar or
collision avoidance systems, but to function as an additional safety feature.
Around Greenland, which is also DaMSAs area of responsibility, a ground station based network of AIS receivers is impractical. Due to Greenland’s extensive coast line, the number of
ground stations required would be very high. Furthermore, the environment in Greenland is so
hostile that maintenance of the ground stations will be a considerable challenge. The DaMSA,
through the sponsorship of AAUSAT3, therefore wishes to investigate the possibility of receiving
AIS signals in space, as a satellite based receiver will be able to cover a much wider area than
conventional ground stations.
1.1.1
Satellite Structure
The primary payload of AAUSAT3 will be two student developed AIS receivers, designed to
evaluate the possibility of receiving AIS in space. The reception of AIS signals in space impose
a number of challenges, such as increased noise and packet collisions, which must be addressed.
In addition to the AIS receivers, the satellite consists of seven subsystems that are all built by
students at Aalborg University. Seven subsystems are located inside the satellite, while two are
located on ground. This is illustrated in Figure 1.1.
EPS
C OM
LOG+FP
AIS2
ADC S
AIS1
Spacelink
GND
MC C
Figure 1.1: AAUSAT3 subsystem structure and internal CAN bus
The main functionalities of the individual subsystems are listed below:
EPS The Electronic Power Supply (EPS) is responsible for charging of the batteries with power
from the solar panels, as well as power conversion and distribution.
LOG The Logging subsystem (LOG) is responsible for logging data and states from all subsystems.
FP The Flight Planner (FP) schedules flight operations and subsystem functionalities, allowing
the operator to plan events for execution when the satellite is out of range.
ADCS The Attitude Determination and Control System (ADCS) detumbles the satellite and
stabilizes the satellites attitude. This is important when communicating using directional
antennas.
COM The Communication subsystems (COM) provides the space link used for transmission of
telecommands and telemetry.
GND The Ground Station (GND) tracks the satellite and positions the antennas on ground.
GND also controls the radio to correct for Doppler shift.
MCC The Mission Control Center allows the satellite operators to issue telecommands and
presents telemetry data received from the satellite.
AIS The AIS receivers are the main payload, responsible for investigating the possibility of
receiving AIS in space.
2
1.2. THE NAVIS PROJECT
The subsystems internal to the satellite communicates using a Controller Area Network (CAN)
bus, which is traditionally used for automotive applications.
1.2
The NAVIS Project
The North Atlantic Vessel Identification System (NAVIS) is a subproject of AAUSAT3. NAVIS
consists of a prototype built for testing on a balloon flight in October 2009 and includes a subset
of the AAUSAT3 subsystems. The balloon flight is made possible through the BEXUS (Balloon
EXperiments for University Students) program, sponsored by ESA, DLR, SSC and SNSB. BEXUS
allows European students to test scientific experiments in high altitude.
BEXUS experiments are launched on a balloon with a total volume of 12,000 m3 to a maximum
altitude of approximately 35 km, depending on total experiment mass (40–100 kg). The flight
duration is 2–5 hours. EuroLaunch, a cooperation between the Esrange Space Center of the
Swedish Space Corporation (SSC) and the Mobile Rocket Base (MORABA) of DLR, is responsible
for the campaign management and operations of the launch vehicles, while experts from ESA, SSC
and DLR provide technical support to the student teams throughout the project. The balloons
are launched from Esrange Space Center in Kiruna, Sweden.
The NAVIS experiment contains prototypes of the EPS and COM subsystems, as well as two
AIS receivers based on different methods: AIS1 is based on a COTS hardware transceiver for
demodulation of the AIS signals, while AIS2 samples the down converted output of a similar
chip, but performs the demodulation in a DSP (Digital Signal Processor). AIS1 is developed by
group 09gr650. The advantage of using a hardware based solution is lower power consumption.
However, the hardware transceivers optimum package detection requires a training sequence of
48 bits or more[Analog Devices 07a, p. 36], but the AIS standard only include 24 training bits
(section 2.1).
The goal of this project (09gr651) is to develop a working software defined AIS receiver (AIS2)
that is expected to be used on AAUSAT3. The receiver must be developed such that it fits the
requirements of the NAVIS experiment. Another reason for developing a software defined AIS
receiver for AAUSAT3 is, that when the satellite is in space, there are no possibility of changing
hardware. A software defined receiver allows for upload of new software to existing hardware,
which is usable for optimization and reconfiguration of algorithms. At the same time, a software
defined receiver is more feasible to detect the short AIS bursts, to compensate for Doppler shift
and use interference cancellation and soft decision to improve the bit error rate.
1.2.1
Time Schedule
The following list gives an overview of the NAVIS project time line and involvement.
Dec 2008 BEXUS experiment application sent to ESA.
Feb 2009 Project accepted by ESA (4 students at selection workshop at ESTEC, The Netherlands).
Feb 2009 Two 6th semester groups (09gr650 and 09gr651) officially working on the BEXUS
flight.
Mar 2009 Submission of status report to ESA.
Mar 2009 Preliminary Design Review (4 students at training week at DLR, Oberpfaffenhofen).
3
CHAPTER 1. INTRODUCTION
May 2009 Submission of status report to ESA.
Jun 2009 6th semester project report submission to Aalborg University.
Jun 2009 Critical Design review (4 students at ESTEC, The Netherlands).
Sep 2009 Experiment delivery to DLR.
Oct 2009 Flight Campaign (Esrange Space Center, Kiruna, Northern Sweden).
Jan 2010 Final experiment report submission to ESA.
1.3
Project Scope
Figure 1.2 illustrates the general flowchart of the software defined AIS receiver developed in this
project. The signals received at the antenna are fed to the RF front-end which downconverts
the signal to a frequency suitable for sampling with the Analog to Digital Converter (ADC). The
sampled data is used as input for the Digital Signal Processor (DSP), which demodulates and
decodes the AIS packets.
A ntenna
RF
Front end
A DC
DSP
Figure 1.2: General flowchart diagram of the software defined AIS receiver.
The projects primary focus is the physical and link layers of the AIS standard. The physical
layer defines the modulation and line coding schemes used, while the link layer provides framing
and error detection mechanisms. The TDMA (Time Division Multiple Access) channel access
method will only be mentioned briefly, as the access scheme is most important when developing
a transmitter that will participate in the scheme. Detailed interpretation of the received packets
is outside the scope of this project, and only executed to the extent needed to verify the received
data.
4
Chapter 2
Analysis
2.1
Automatic Identification System
This section describes the technical details of the Automatic Identification System (AIS). As described in the report introduction in Chapter 1.1, AIS is a ITU-R standardized system designed
to improve safety at sea. Ships equipped with an AIS transponder continuously broadcasts navigational data to other ships and ground based stations. The current AIS standard is documented
in ITU-R Recommendation M.1371-3[ITU 07] which is used as the primary source for this section.
The description is concentrated on receiving AIS messages, and only briefly considers the various
Time Division Multiple Access (TDMA) schemes used for self-organized Medium Access Control
(MAC).
AIS messages either contain static or dynamic information. Static information includes the
name of the transmitting ship, call sign, type of ship etc. Dynamic information contains data such
as position and heading. Both packet types contains the ships MMSI (Maritime Mobile Service
Identity) number, which uniquely identifies the ship. MMSI numbers are 9 digits long, of which
the first 3 are the Maritime Identification Digits (MID) that indicates in which country the ship is
registered. The danish MID are 219 and 220. Static information packets are transmitted every 6
min. The reporting interval of dynamic information depends on if the ships is at anchor or sailing.
Table 2.1 lists the reporting interval for dynamic data. Ground stations transmits information
every 10 s.
Ship’s dynamic conditions
Nominal reporting interval
Ship
Ship
Ship
Ship
Ship
Ship
Ship
Ship
3 min
10 s
10 s
3 1/3 s
6s
2s
2s
2s
at anchor or moored and not moving faster than 3 knots
at anchor or moored and moving faster than 3 knots
0-14 knots
0-14 knots and changing course
14-23 knots
14-23 knots and changing course
>23 knots
>23 knots and changing course
Table 2.1: Reporting interval for dynamic information.
The AIS standard classifies transponders in two categories: Class A and class B. The main
difference between the classes is the maximum transmission power. Class A transponders are
required to transmit with 12.5 W while Class B only transmit with 1 W. Class B transponders are
also not required to support Self-Organized TDMA MAC scheme and may use the simpler Carrier5
CHAPTER 2. ANALYSIS
Sense TDMA (CSTDMA) instead. Class A AIS transponders should be able to both receive
and transmit short safety related messages, containing important navigational or meteorological
notifications. Class B receivers should only be capable of receiving these notifications. The rest
of this section focuses on Class A transponders.
The AIS standard covers layer 1 to 4 in the OSI (Open Systems Interconnection) Reference
Model. This description only covers the physical and link layers. The network layer is responsible
for prioritization of messages, distribution of packets between transmission channels and data link
congestion resolution, and is mainly relevant when developing AIS transmitters. The transport
layers primary function is to implement sequencing and split messages that occupy multiple AIS
slots. The AIS receiver developed in this project, does not support multi-slot binary messages.
2.1.1
Physical Layer
The physical layer is responsible for NRZI (Non-Return to Zero Inverted) encoding the data and
applying the GMSK (Gaussian Minimum Shift Keying) modulation scheme for transmission on
the VHF data link (VDL). NRZI and GMSK are explained in detail in Sections 2.5.4 and 2.3.
Table 2.2 lists the main parameters of the physical layer. AIS signals are transmitted on maritime
VHF channels 87B and 88B at 161.975 and 162.025 MHz. Each channel has a bandwidth of 25 kHz.
AIS transponders should listen for AIS packets on both channels but alternate its transmissions
between the channels. The channel distribution algorithm is implemented in the network layer.
The AIS standard does not include any forward error correction, interleaving or bit scrambling
mechanisms.
Parameter Name
Setting
Unit
AIS channel 1
AIS channel 2
Modulation scheme
Carrier frequency error
Transmit output power
Modulation index
Transmit BT product
Receive BT product
Bit rate
Maximum bit rate deviation
Training sequence
161.975
162.025
GMSK
± 500
12.5
∼ 0.5
∼ 0.4
∼ 0.5
9600
50
24
MHz
MHz
Hz
W
min
max
bit/s
ppm
bits
Table 2.2: AIS specifications.
Figure 2.1 shows the theoretical spectrum of the two AIS channels. Figure 2.2 plots a measurement of the AIS channel spectrum. This figure is created using a VHF antenna connected
directly to a Rohde & Schwarz FSEA spectrum analyzer, and clealy shows peaks around the two
channel frequencies. Due to the short AIS packages, the spectrum analyzer is set to peak hold,
and approximately one minute is analyzed to plot the spectrum. Naturally, the noise around the
channels are also peak values.
25 kHz
25 kHz
Frequen cy [MHz]
161.97 5
AIS Cha nnel 1
162
162.02 5
AIS Cha nnel 2
Figure 2.1: Expected AIS channel spectrum.
6
2.1. AUTOMATIC IDENTIFICATION SYSTEM
Rec. ITU-R M.1371-3
–
–
–
–
2.1.2
3.2
17
Internal allocation: meaning that the slot is allocated by own station and can be used for
transmission.
External allocation: meaning that the slot is allocated for transmission by another station.
Available: meaning that the slot is externally allocated by a station and is a possible
candidate for slot reuse (see § 4.4.1).
Figure 2.2: Measured AIS channel spectrum.
Unavailable: meaning that the slot is externally allocated by a station and cannot be a
candidate for slot reuse (see § 4.4.1).
Sub layer 2: data link service (DLS)
Link Layer
The DLS sub layer provides methods for:
The link–layer is
divided
into three
sub layers: Medium Access Control (MAC), Data Link Service
data
link activation
and release;
(DLS) and
– Link
dataManage
transfer; orEntity (LME). The MAC and LME layers main functionality is the
channel –accesserror
arbitration.
channels are shared among transmitting ships using TDMA
detection andThe
control.
schemes, by dividing time into transmission slots. AIS uses 1 minute frames that are subdivided
3.2.1
link activation
and release
bit/s, one slot will thus allow 256 bits to be transmitted. The
into 2250
slots Data
of 26.67
ms. At 9600
Based on the MAC
sub layer
DLSone
willslot,
listen,but
activate
or release
themessages
data link. Activation
and up to 5
default transmission
messages
fitstheinto
special
binary
may occupy
release
should be in accordance with § 3.1.5. A slot, marked as free or externally allocated,
consecutive
slots.
indicates
be in
receive”master
mode andships”
listen for
other
data link users.
At open
sea that
it isown
notequipment
desirableshould
to have
special
that
determine
whenThis
other ships
should also be the case with slots, marked as available and not to be used by own station for
are allowed
to
broadcast.
The
AIS
uses
a
Self-Organized
TDMA
scheme
using
a
common
time
transmission (see § 4.4.1).
reference. If possible, the AIS transponders are synchronized to UTC and decides on which slots
Data
transfer
it should3.2.2
use for
transmissions
depending on received transmissions from other AIS transponders.
If UTC synchronization
nota bit-oriented
available, protocol
the standard
alternate
methods
for control
time synchroData transfer shouldisuse
which isdefines
based on
the high-level
data link
as specified
3309:
– Definition TDMA
of packetzones
structure.
packetsmanner.
nization.(HDLC)
This way,
ships by
areISO/IEC
arranged
in1993
synchronized
in aInformation
self-organized
(I-Packets)
be used with the
exception
controlaims
field isfor
omitted
(see zones
Fig. 6).not to be smaller
To ensure
correctshould
communication
in the
AIS, that
thethe
system
TDMA
than 20 3.2.2.1
nmi andBitnot
larger than 200 nmi. The typical size of a TDMA zone is approximately
stuffing
30 nmi. The bit stream of the data portion and the FCS, see Fig. 6, § 3.2.2.5 and § 3.2.2.6, should be subject
The to
DLS
is responsible
for data transfer
error
and control.
shows the
bit stuffing.
On the transmitting
side, thisand
means
that detection
if five (5) consecutive
ones Figure
(1’s) are 2.3
found
AIS packet
AIS uses
a should
packetbeformat
to the
High-Level
Data
in thestructure.
output bit stream,
a zero
insertedidentical
after the five
(5) consecutive
ones
(1’s).Link
This Control
to all an
bits additional
between the 24
HDLC
(start sequence
flag and end
flag, see
On of
thethe
receiving
(HDLC),applies
but with
bit flags
training
added
to Fig.
the 6).
start
packet. The
the firstconsists
zero afterof
five
(5) consecutive
ones(0)
(1’s)
should
removed.
training side,
sequence
alternating
zeros
and
onesbe(1)
and aids receivers in attaining bit
synchronization.
The standard
does not specify if the training sequence starts with a zero or a
3.2.2.2 Packet
format
one bit, Data
so the
receiver
should
be
able to handle both cases. Table 2.3 lists the packets fields in
is transferred using a transmission packet as shown in Fig. 6:
AIS. The total length of a data frame is 256 bits, includes including training sequence and 24 bits
buffer. The packet thus fits into a single AIS transmission slot.
frame.
The packet should be sent fromFigure
left to 2.3:
right.AIS
Thisdata
structure
is identical to the general HDLC
structure, except for the training sequence. The training sequence should be used in order to
synchronize the VHF receiver and is discussed in § 3.2.2.3. The total length of the default packet
The isstart
flagThis
is 8is equivalent
bits longtoand
consists
256 bits.
one (1)
slot. of a standard HDLC flag. It is used in order to
detect the start of a transmission packet. The start flag consists of the bit pattern 01111110,
corresponding to 0x7E in hexadecimal notation. The default data field is 168 bits long, although
transponders may occupy up to a maximum of five consecutive slots for one continuous transmission. Only a single application of overhead is required for a long transmission packet. The length
7
CHAPTER 2. ANALYSIS
Name
bits
Ramp up
Training sequence
Start flag
Data
FCS (frame check sequence)
End flag
Buffer
8
24
8
168
16
8
24
Total
256
Table 2.3: AIS data frame details [ITU 07, p. 17].
of a transmission packet should not be longer than necessary to transfer the data, i.e. the AIS
transponder cannot be expected to add filler.
The Frame Check Sequence (FCS) uses a cyclic redundancy check (CRC) 16-bit polynomial
to calculate a checksum as defined in ISO/IEC 3309. The CRC bits should be pre-set to one (1)
at the beginning of a CRC calculation. Only the data portion should be included in the CRC
calculation. The end flag is identical to the start flag.
The buffer is silence on the frequency which negates distance delay and synchronization jitter.
The data and FCS fields should be subject to bit stuffing. If five consecutive 1 bits are found in
the output data, the transmitter must insert an additional 0 bit. Similarly, the receiver should
remove the first 0 bit following five 1 bits. Bit synchronization is used for two reasons: First of all
to ensure that the HDLC start/end flags not occur in the middle of a transmission packet, but also
to aid receivers to attain bit synchronization. The data stream is NRZI encoded in the physical
layer. NRZI only has transitions when sending a 0 bit, so a long period of 1 bits could lead to the
receiver losing synchronization. Bit stuffing ensures that a transition will occur after maximum
five bits. According to statistical analysis performed by the ITU-R, most packages requires three
bits or less for bit stuffing. The packet bytes are transmitted Least Significant Bit (LSB) first, in
accordance with the HDLC specification.
2.1.3
AIS from High Altitude
In this section, the special circumstances when receiving AIS in space is considered. First, the
worst case Doppler shift will be evaluated. The satellite is expected to be in a orbit of around
600 km above the earth, which equals a velocity of about 7500 m/sec.
The Doppler effect is given as[Serway 04, p. 525]:
f0 =
c + vo
f
c − vs
where in worst case:
c is the speed of light, 299792458 m/s.
vo is the speed of the observer, in this case the satellite, 7500 m/s.
vs is the speed of the source, in this case the AIS transmitting ship, ignored (0 m/s).
f is the transmitter frequency, in this case approx. 162 MHz for both channels.
The resulting frequency, when the satellite is flying directly towards the ship:
f0 =
c − 7500 m/s
162 MHz = 162.004 MHz
c
And in the case of the satellite flying directly away from the ship:
f0 =
8
c + 7500 m/s
162 MHz = 161.996 MHz
c
2.1. AUTOMATIC IDENTIFICATION SYSTEM
This means that a frequency deviation of ±4 kHz is expected for each AIS channel, which the
receiver will have to compensate for. Note that this situation cannot be expected, as the satellite
will never have the direction directly against or away from a ship.
As the satellite travels above an AIS transmitting ship, the Doppler changes. This is illustrated
in Figure 2.4. Here the ship is placed in the center of the circle and the satellite moves from right to
left. Note that during the transmission time of one AIS message (max 133 ms) the satellite moves
998 m (0.5 nmi). This movement will not make a significant change of the received frequency
3.3 Link Budget
17
during the transmission.
Doppler shift [Hz]
3000
Ground Range (y) [nm]
1000
2000
500
1000
0
0
−1000
−500
−2000
−1000
−3000
−1500
−1000
−500
0
500
Ground Range (x) [nm]
1000
1500
FigureFigure
3.5: 2.4:
Doppler
shift for shift
shipsfor
in LEO
the FOV
measured
at p.
the17].
satellite
AIS Doppler
satellite
[Dahl 06,
Another interesting part about AIS from high altitude is the collisions that is expected. The AIS
3.3
Link intended
Budget
system
was originally
to be used for ship-to-ship and ship-to-land transmission. This
raises some challenges receiving messages from a much larger area than a ground station, due to
A substantial
part of
themeans
receiver
is might
to evaluate
received
power due
the increased
line-of-sight.
This
that design
a satellite
receive the
collided
AIS massages,
to thefrom
fact that
a ship compared
only synchronizes
transmissions
with
ships within the(C/N
line-of-sight.
the ships
to theitsnoise
power, i.e
theother
Carrier-to-Noise
)
ratio.1 In this section, a simple link budget with signal strength compared to
sensitivity
will be evaluated for the AIS message reception situation.
2.1.4receiver
Previous
Analyses
The
simulations
are
done in Matlab[1], see Appendix A for source code.
The possibility of receiving AIS messages in space has been analyzed in a semester report by
The most
significant
parameters
in the developed
link budget
are listed
3.1signal
group 07gr506
from Aalborg
University.
The project
simulations
of in
theTable
received
andatare
denoted
a symbol.
Each of
of AIS
these
will becollisions
discussed
strength
given
heightby
and
the probability
message
as anext.
consequence of the
enlarged footprint. This section will summarize their result with a short description associated as
well as the results from group 09gr650 and ESA researchers.
3.3.1 Ship Transmitter Parameters
Figure 2.5 illustrate the simulated link budget of a satellite based AIS receiver placed in a
1000 From
km altitude
TheAIS
shipmobile
antennas
are placed
a height
of 30 Pmt and
transmitting
Table orbit.
2.2, the
station
at a in
ship
transmits
= 12.5
W
12.5 W as defined in AIS standard for Class A transponder. Reflections from the water has
(default setting). A half-wave dipole antenna has been assumed as the shipbeen taken into consideration, which is why the signal strength has some sharp dives caused by
antenna.
The
pattern
for a half-wave
dipolereceiving
antenna
signaltransmit
cancellation.
Note that
the radiation
signal strength
is calculated
with the satellite
with an
directed
in
the
z-direction
(vertically)
is
given
in
[16]
as
isotropic antenna.
Figure 2.6 illustrates the link budget expected for the BEXUS flight with the balloon in 35 km
cos [(π/2)
cos θ]
altitude. This simulation does not
reflections
into consideration,
but simulates (3.15)
the BEXUS
fsattake
(θ, φ)
=
.
2
experiment antenna with a half wavelength dipole sin
on the
θ receiver. According to the analysis, a
−90 dBm received power corresponds to a SNR at 33 dB at the receiver. Figure 2.7 shows the
The pattern
is independent
azimuthuncorrupted
angle φ. during
Also anote
the ship,
probability
that at least
1 AIS messageof
willthe
be received
pass that
from each
antenna is vertically polarized. The maximum gain for such an antenna can
be shown to be 2.15 dB. The gain pattern Gsat (θ, φ) is shown graphically
in Figure 3.6. It reaches its maximum in the horizontal plane of the ship
and decreases to zero radiation when approaching the direction parallel to
1
Note that for now, noise is considered as thermal noise only, co-channel interference
will be considered later.
9
CHAPTER 2. ANALYSIS
Analysis
−80
Power density at the satellite´s position [dBm]
−100
−120
−140
−160
−180
−200
−220
−240
−260
0
5
10
15
20
25
30
35
Angle between satellite and ship in the center of the earth [degrees]
40
45
Figure 2.7: The logarithmic plot of the power density in the vicinity of the satellite as a
function
of the angle
the ship and1the
satellite.is
The
indirect wave
Figure 2.5: Link budget
- AIS
frombetween
AAUSAT3.
degree
approximately
111 km
is added to the direct wave, thus creating the low points in the plot. This
[07gr506 07].
plot is for a fixed antenna height of 30 m and a satellite height of 1000
−72
−74
−78
−80
nd
a
ite
−82
ll
ate
ns
ee
tw
be
gle
An
−84
na
s]
ee
gr
e
[d
−86
er
ov
the
ter
wa
ten
an
the
of
t
igh
He
ip
sh
Received power in dBm
−76
Power density at satellites’s position [W]
km. The total radiated power is 12.5 W.
−88
Figure 2.8: The 3D plot shows that ships with different antenna heights located in the
same angle to the satellite can deliver signals of very different power.
−90
24
−92
0
1
2
3
4
5
6
Angle between ship and balloon in the centre of earth
Figure 2.6: Link budget - AIS from balloon flight. 1 degree is approximately 111 km
[09gr650 09].
10
2.1. AUTOMATIC IDENTIFICATION SYSTEM
when the ships is sending a message every 6 sec. The blue line plots the optimal pass for the
satellite, which is when the satellite pass directly over the ship. The red line illustrates a shorter
pass period. The simulation is done by ESA, with a footprint of 3000 nmi in diameter. Figure
1
0.9
Probability of ship detection
0.8
0.7
Tv=740 s
0.6
0.5
0.4
Tv=80s
0.3
0.2
0.1
0
0
500
1000
1500
2000 2500 3000
Number of vessels
3500
4000
4500
5000
Figure 2.7: Probability of uncollided AIS packages [Cervera 08].
2.8 shows the expected antenna footprint on the BEXUS balloon flight. On the basis of this, it is
expected that a certain number of ships will be in range in the Baltic sea. Undisclosed data from
DaMSA showed 720 ships within this range of the BEXUS footprint at a given date in February
2009.
Figure 2.8: Antenna footprint from balloonflight [09gr650 09].
11
PSfrag replacements
CHAPTER 2. ANALYSIS
2.2
8
Wireless Communication
This section gives a short introduction to wireless communication systems, and introduces concepts
such as orthogonal
signals, signal constellation
bit error probability.
Terminology and notation
Digital communication
system and
considered
in this course:
from [Fleury 07] is used.
U
BSS
Digital
Transmitter
bit rate 1/Tb
Binary
Sink
Û
X(t)
rate 1/T
Digital
Receiver
Waveform
Channel
Y (t)
Figure 2.9: General wireless communication system [Fleury 07, p. 8].
• shows
Source:
U =wireless
[U1, . .digital
. , UKcommunication
], Ui ∈ {0, 1}system. The information source is
Figure 2.9
a typical
considered to be a Binary Symmetric Source (BSS) that outputs a sequence of K independent
• distributed
Transmitter:
X(t)
u)], Ui ∈ {0, 1} at a bit rate of 1/Tb . Each bit thus
and uniformly
bits, U
= [U=
. . , UK
1 , .x(t,
has a duration of Tb . The output of an efficient information encoder will look like the output
of a BSS, so•this
introduces
Sink:
Û = no
[Û1loss
, . . in
. , generality.
ÛK ], Ûi ∈The
{0,Digital
1} Transmitter maps the K bits to
a continuous function of time, X(t), and outputs symbol waveforms at a rate of 1/T = 1/(KTb ),
each with a duration of T . Note that X(t) = 0 for t ∈
/ [0, T [. The waveforms are transmitted
• Bit
1/Tb noise, phase and frequency distortion, and interference from
over a channel
that rate:
may introduce
e.g. multiple transmission paths, before being received in the Digital Receiver. The receiver maps
Rate (ofY (t)
waveforms):
1/T =Û1/(KT
the received •waveforms
to the bit sequence
= [Û1 ,b.). . , ÛK ], Ui ∈ {0, 1}, before feeding
the sequence to the Binary Sink destination. The receiver attempts to map the received symbols
to Û such that
Û =error
U . The
probability of receiving erroneous bits, Pb , is called the Bit Error
• Bit
probability
Probability (BEP).
K
1 X
Pb =
P r(Uk =
6 ÛkP) b
K
k=1
K
1 X
Pr(Uk 6= Ûk )
=
K
(2.1)
k=1
In AIS the BSS consists of two parts. An information source that outputs identification data, and
a source encoder. The source encoder encodes the data from the information source in HDLC
Objective:
Design
ofwhich
efficient
digital
communication
frames, using
NRZI and bit
stuffing,
is covered
in Section
2.3. AIS uses systems
a Gaussian Minimum
Shift Keying (GMSK) modulation scheme in the Digital Transmitter. GMSK and a number of
( in Section 2.5 with consideration of BER in MSK and
similar modulation schemes are described
small bit error probability and
GMSK.
Efficiency
means
The Digital Transmitter maps the input bit sequence U = [U1 , . . . , UK ] ∈ U = {0, 1}K to an
high bit rate 1/Tb. lookup table (LUT). The LUT
output waveform x(t) ∈ S = {s1 (t), . . . , sM (t)} using a waveform
mapping U 7→ x(t) is bijective, meaning that each waveform is the mapping of exactly one bit
sequence.
The waveforms in S = {s1 (t), . . . , sM (t)} spans a vector space. An orthonormal basis of vectors
Sψ = {ψ1 (t), ψ2 (t), . . . , ψD (t)} spanning the same space as spanned by S can be constructed by
using the Gram-Schmidt orthogonalization process. A pair of vectors are orthogonal if their inner
Modulation
NavCom
product Land,
is zeroFleury:
and a Digital
set of vectors
form1 an orthonormal set if:
(
Z ∞
0 for k 6= l
hψk (t), ψl (t)i =
ψk (t)ψl (t)dt =
(2.2)
1 for k = l
−∞
12
where u ∈ U and x(t) ∈ S.
From the previous section, we know how to synthesize the waveform sm(t) from sm (see also Appendix A) with respect to a set of
basis functions
2.3. LINE CODING
Sψ := {ψ1(t), ψ2(t), . . . , ψD (t)}.
Making
usevectors
of thisinmethod,
can 1split
waveform
look-up
Meaning that each
of the
Sψ is of we
length
and the
orthogonal
to all
other vectors in the
tableininto
a vector
look-up table
and acombinations
waveform synthesizer:
set. The waveforms
S can
be constructed
as linear
of the vectors in Sψ :
uX
=D [u1, . . . , uK ]
smwhere
(t) =
sm,i · ψi (t),
i=1
7→
x = [x1, x2, . . . , xD ]
m = 1, 2, . . . , M
7→
x(t),
(2.3)
u ∈ U = {0, 1}K ,
Each of the waveforms s1 (t), . . . , sM (t) can thus be formed by weighting
the waveforms ψ1 (t), . . . , ψD (t)
D
x ∈ ]X
T = {s1 , s2 , . . . , sD } ⊂ R ,
with
the
vector
s
=
[s
,
.
.
.
,
s
.
Figure
2.10
illustrates
the
mapping
from the bit stream
m
m,1
m,D
PSfrag replacements
x(t)used
∈ S as
= {s
s2 (t), for
. . . ,ψs1M, .(t)}.
U to waveform. X1 , . . . , XD are
the
weights
. . , ψD . The vector encoder maps
1 (t),
the input bit sequence to the correct waveform and outputs the weights for the orthonormal basis
functions to theThis
waveform
The modulator
adds
the signals
and outputs the X(t)
splittingmodulator.
procedure leads
to the sought
canonical
decomposiwaveform to thetion
channel.
of a digital transmitter:
[U1, . . . , UK ]
Vector
Encoder
Vector
Look-up Table
[0 . . . 0] 7→ s1
[1 . . . 1] 7→ sM
X1
Waveform
Modulator
ψ1(t)
X(t)
XD
ψD (t)
Land, Fleury:
Modulation 1of the digital transmitter [Fleury 07,NavCom
Figure
2.10: Digital
Decomposition
p. 13].
2.3
Line Coding
The output bit stream from the AIS information source is NRZI (Non Return to Zero Inverted)
encoded. NRZI is a differential line code, that encode data as a transition of the signalling level
when a 0 bit is sent, and no transition when a 1 bit is sent. This means that a bit sequence
can be NRZI encoded as two different sequences depending on the initial level of the line. NRZI
encoding has the advantage, that decoded data is unaffected by the receiver swapping the 0 and
1 waveforms. A transition always indicates that a 0 was transmitted. The main disadvantage
of NRZI is that a long series of 1 bits will have no transitions of the signalling level, making it
difficult for the receiver to attain clock synchronization. AIS uses bit stuffing for sequences of
more than five consecutive 1 bits, ensuring that the line will have at least one transition for every
6 bits transmitted. Figure 2.11 shows the original and NZRI encoded versions of 7 bits from an
AIS training sequence. The AIS standard does not specify if training sequences should start with
a 0 or 1 bit. Figure 2.11a is the original sequence starting with a 0 bit and Figure 2.11b and 2.11c
are the NRZI encoded streams.
2.4
Channel Estimation
The wireless channel shown in Figure 2.9 can be estimated as a Additive White Gaussian Noise
(AWGN) channel. Satellite communication is normally the textbook example on a AWGN channel,
because multi patch signals are minimal, due the the high gain directional antennas normally
used in satellite communication. However, AIS vessels uses omni directional antennas to improve
horizontal communication, and this might to some extend introduce a signal patch where the
ocean reflect the radio waves. The transmitter design and channel characterization impact the
optimum receiver design. In this report, the focus is on a AWGN channel.
13
CHAPTER 2. ANALYSIS
a
1
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
Tb
6
7
8
9
b
1
0
c
1
0
15
1.4
TheFigure
Additive
White
2.11: 7 training
bits NRZIGaussian-Noise
encoded.
Channel
PSfrag replacements
W (t)
Y (t)
X(t)
Figure white
2.12: Additive
White
Gaussian
Noisechannel-model
channel.
The additive
Gaussian
noise
(AWGN)
is
widely used in communications. The transmitted signal X(t) is
superimposed by a stochastic noise signal W (t), such that the
transmitted signal reads
Figure 2.12 shows the AWGN channel. Here, the Gaussian distributed white noise are received
together with the transmitted signal. The noise is normal distributed, have zero mean, and
Y (t) = X(t) + W (t).
variance N0/2. That is:
W ∼ N (µ, σ 2 )
The stochastic process W (t) is a stationary process with the
µ = E [W ] = 0
following properties:
N0
σ 2 = E W − µ2 =
2
(i) W (t) is a Gaussian
process, i.e., for each time t, the
Where W is the samesamples
dimension
as
X.
v = w(t) are Gaussian distributed with zero mean
(2.4)
(2.5)
(2.6)
and variance σ 2:
2.5
Digital Modulation
1
v2 pV (v) = √
exp − 2 .
2
This section analyzes various Angle Modulation2πσ
schemes,
in2σ
order to understand the Gaussian
Minimum Shift Keying (GMSK) modulation used in AIS. The section starts with a description of
simple Binary Frequency-Shift
(BFSK),spectrum
after which with
Minimum-Shift
Keying (MSK), which
(ii) W (t) has Keying
a flat power
height N0/2:
is BFSK with minimum frequency separation, is examined. Finally MSK is extended to Gaussian
N0
Minimum Shift Keying (GMSK)
S (f ) =
W
2.5.1
2
Binary Frequency-Shift
(Therefore it isKeying
called “white”.)
In Binary Frequency-Shift Keying(BFSK), the information UK is modulated as two frequencies,
(t) has the
f1 and f2 . The(iii)
firstW
frequency
f1 autocorrelation
in the duration function
of one bit, Tb , indicates a logic ”0”, and the
RW (τ ) =
14
Land, Fleury: Digital Modulation 1
N0
δ(τ ).
2
NavCom
2.5. DIGITAL MODULATION
second frequency f2 indicates a logic ”1”.
q
 2Eb cos (2πf1 t) for symbol 0
T
s(t) = q b
 2Eb cos (2πf2 t) for symbol 1
Tb
(2.7)
Where:
Eb is the transmitted energy per bit
Tb is the bit duration, measured in seconds
f1 is the transmitted frequency when transmitting 0
f2 is the transmitted frequency when transmitting 1
Figure 2.13 shows an example of BFSK, where the bit sequence 0b0111001 is transmitted with
one bit pr. second.
1
0
−1
0
1
2
3
4
5
6
7
Figure 2.13: BFSK, 1 b/s, f1 = 1 Hz, f2 = 2 Hz.
Typically, the two frequencies f1 and f2 are chosen such as:
n
Tb
n+1
f2 =
Tb
f1 =
(2.8)
(2.9)
Where n is a integer. In Figure 2.13 n = 1, which is the minimum theroretical frequency choice.
This is done to avoid discontinuities in the phase. Another possibility is to remember the phase
at the end of the previous symbol, and compensate for that when transmitting the next symbol
(Continuous Phase-FSK).
2.5.2
Minimum-Shift Keying
Minimum Shift Keying is a special case of BFSK, which ensures the minimum distance between
the two frequencies, and thereby limiting the power spectrum - while still having orthonormal
signal constellation and continuous phase. The frequency separation f∆ = 1/2T used in MSK is
the minimum separation such that s1 (t) and s2 (t) are still orthogonal. The proof is as follows:
The two waveforms and the frequency separation are defined as:
√
s1 (t) = 2P · cos(2πf1 t)
(2.10)
√
s2 (t) = 2P · cos(2πf2 t)
(2.11)
f∆ = |f1 − f2 |
(2.12)
Where P is the transmitted power, and f1 and f2 are the frequencies of the waveforms. A necessary
requirement for s1 (t) and s2 (t) to be orthogonal, is that the scalar product of the waveforms is
zero:
Z ∞
hs1 (t), s2 (t)i =
s1 (t)s2 (t) dt = 0
(2.13)
−∞
15
CHAPTER 2. ANALYSIS
Applying Eulers formula:
ej2πf0 t+e + e−j2πf0 t
2
cos(2πf0 t) =
(2.14)
And inserting in the expression of the scalar product:
Z ∞
hs1 (t), s2 (t)i =
s1 (t)s2 (t) dt
(2.15)
−∞
T
Z
= 2P
cos(2πf1 t) · cos(2πf2 t)
(2.16)
ej2πf1 t + e−j2πf1 t ej2πf2 t + e−j2πf2 t
·
dt
2
2
(2.17)
0
T
Z
= 2P
=
P
2
Z
0
T
ej2π(f1 +f2 )t + e−j2π(f1 +f2 )t + ej2π(f1 −f2 )t + e−j2π(f1 −f2 )t dt
(2.18)
0
In accordance with equation (2.12) f1 − f2 = f∆ :
Z
hs1 (t), s2 (t)i = P
T
Z
cos(2π(f1 + f2 )t) dt +
0
=
!
T
cos(2πf∆ t) dt
(2.19)
0
P · sin(2π(f1 + f2 )T ) P · sin(2πf∆ T )
+
2π(f1 +2 )
2πf∆
(2.20)
As sin(x) ∈ [−1, 1] and f1 + f2 is usually 1, the first term is approximately zero:
hs1 (t), s2 (t)i =
P · sin(2πf∆ T )
2πf∆
(2.21)
Since sin(nπ) = 0 for n ∈ Z, solving (2.21) for f∆ yields:
hs1 (t), s2 (t)i =
1
P · sin(2πf∆ T )
= 0 ⇒ f∆ =
· k, k ∈ Z \ 0
2πf∆
2T
(2.22)
Hence, the minimum frequency separation is for k = ±1. Requiring f∆ to be positive:
f∆ =
1
2T
(2.23)
A simple example of the minimum frequency separation is shown in Figure 2.14a, where 0b0111001
is transmitted with 1 b/s, f1 = 1 Hz and f2 = 1.5 Hz.
Here the minimum frequency separation means that the phase must be remembered in the transmitter, and when the phase is π, the following symbol must be flipped vertically to avoid phase
discontinuities, see Figure 2.14b. This gives the signal constellation shown in Figure 2.15.
16
2.5. DIGITAL MODULATION
136
1
a
0
Remark:
The modulation
symbol
at discrete
time
j is written
as
−1
0
1
2
3
4
5
6
X j = (Xj,1 , Xj,2 )T.
1
b
7
0
√
For example,
X
−1
j = s12 means3 Xj,1 = 4 Es and5 Xj,2 =6 0.
0
1
7
Tb
Figure constellation:
2.14: MSK waveform introduces memory to prevent phase discontinuities.
Signal
ψ2
PSfrag replacements
s3
ψ1
s2
s1
s4
Figure 2.15: MSK Signal constellation [Fleury 07, p. 136].
Remark:
The signal constellation corresponds to:
MSK and QPSK
have the same signal constellation. However, the
p
(2.24)
s1 = + Es · ψ 1 (t)
p
two modulation
schemes are not equivalent because their vector
s2 = − Es · ψ 1 (t)
(2.25)
p different. This is discussed in the following.
encoders are
s3 = + Es · ψ 2 (t)
(2.26)
p
s4 = − Es · ψ 2 (t)
(2.27)
Where:
r
2
cos(2πf1 t)
T
r
2
ψ 2 (t) =
cos(2πf2 t)
T
ψ 2 (t) =
(2.28)
(2.29)
This looks like the signal constellation of Quadrature Phase Shift Keying(QPSK), however the
modulation scheme is not the same. In QPSK, each symbol represent two bits, but in MSK only
one bit is transmitted for each symbol. The previous accumulated phase thereby limit the next
allowed transmitted symbol. This is shown in Figure 2.16. Hence, the bold pathway corresponds
to 01100.
With the minimum frequency separation, f∆ , and a desired center frequency, the modulation
scheme may be represented by:
Land, Fleury: r
Digital
NavCom
2Eb Modulation 1
cos (2πfc t + θ(t))
(2.30)
s(t) =
Tb
17
PSfrag replacements
141
The temporal
CHAPTER 2. ANALYSIS
behavior of the encoder can be described by the
trellis diagram:
0/s2
0/s2
0/s2
π
0/s2
π
1/
π
1/
π
1/
π
1/
π
1/
s3
1/
s3
1/
s3
1/
s3
1/
s3
s4
s4
s4
s4
0 0/s
1
0 0/s
1
0 0/s
1
0 0/s
1
0 0/s
1
0
0
1
2
3
4
5
The Figure
emphasized
path corresponds to the input sequence
2.16: MSK trellis [Fleury 07, p. 141]. With f as basis.
1
[U0, U1, U2, U3, U4] = [0, 1, 1, 0, 0].
Where θ(t) is defined as follows:
±h · tConventions
General
θ(t)
=
+ θ(0)
2Tb
(2.31)
For 0 ≤ t ≤ Tb . (i) The input sequence of length L is written as
u = [uto0, the
u1, .center
. . , uL−1
].
Here, θ(0) is the phase memory in relation
frequency.
When h = 0.5 as defined in
the AIS standard, each bit transmitted will make a phase turn of 0.5π either positive or negative,
depending on the
(ii)transmitted
The initial bit.
state Ais trellis
V0 = 0.diagram showing the phase variation for the bit
sequence 0b0111001 is show in figure 2.17.
(iii) The final state is VL = 0.
1
4Tb
1
f2The
= fclast
+ bit UL−1 is selected such that the encoder is driven back
4Tb
f1 = fc −
(2.32)
(2.33)
to state 0:
1
−→
−→
VL−1 = 0
VL−1 = 1
UL−1 = 0,
UL−1 = 1.
Phase [π]
Therefore, UL−1 does not carry information.
0.5
0
Land, Fleury:
Digital Modulation 1
−0.5
0
1
2
NavCom
3
4
Time [bit]
5
6
7
Figure 2.17: MSK Trellis diagram showing the bit sequence 0b0111001. With fc as
basis.
2.5.3
MSK Demodulation and Bit Error Rate
The signal at the receiver is denoted Y (t) as in Figure 2.9 on page 12.
Figure 2.18 shows an example of a non-coherent receiver using correlators, also known as
product-integrators. Two correlators are required, one for f1 and one for f2 . The output of each
correlator is denoted Yj,1 and Yj,2 , and is therefore a measurement of the content of a transmitted
f1 or f2 during the latest bit-time.
18
τ ∈ [0, T ).
t = jT + τ,
The demodulation for τ = t − jT ∈ [0, T ), j = 2.5.
0, 1, DIGITAL
2, . . . , can
MODULATION
then be implemented as follows:
PSfrag replacements
cos(2πf1 τ )
q R
T
2
Yj,1
T
qT
2
T
0
q R
T
2
Yj,2
T
0
(.)dτ
Y (t)
(.)dτ
cos(2πf2 τ )
Figure 2.18: MSK demodulator [Fleury 07, p. 144].
The Decision Rule
By subtracting the two correlator output, y is created. A zero-crossing in y therefore indicates a
bit transition, while a positive value indicates ”1” and negative indicates ”0”. When y is sampled
bK is found. The decision rule is illustrated in Figure 2.19,
at Tb , the estimated bit sequence U
where the non-coherent receiver only is able to estimate the transmitted frequency, and not the
phase.
Land, Fleury: Digital Modulation 1
NavCom
Figure 2.19: Non-coherent MSK decision rule.
This is the Most Likelihood decision rule, choosing the signal constellation closest to the received
vector.
Bit Error Rate
Errors occurs only when the noise vector is large enough to move the transmitted vector to the
other side of the decision rule boundary. That is, given s3 is transmitted, error occurs when:
2
2
|y − s1 | < |y − s3 |
Where y is the received vector. Let de denote the distance between s1 and s3 , and
noise variation. Then the error probability is given by [Vasudevan 07, p. 9]:
v
u 2 
u t de 
1


Pe = erfc 
2
8σ 2 
Where erfc is the complementary error function:
Z ∞
2
2
erfc(x) = √
e−y dy
π y=x
(2.34)
N0/2
denote the
(2.35)
(2.36)
19
CHAPTER 2. ANALYSIS
2
And e−y is shown in Figure 2.20.
1
2
e−y
0.8
0.6
0.4
0.2
0
−4
−3
−2
−1
0
y
1
2
3
4
Figure 2.20: Normal distribution.
2
e is
In this case, the distance |d|
Pe,nc
1
= erfc
2
r
√
2
Es +
!
√
2
Es .
Es
2N0
(2.37)
This BER is shown in Figure 2.26.
Another possibility is to demodulate coherently. That is, recover the phase of the signal in the
receiver, and hence being able to detect whether s1 or −s1 was transmitted. Due to the phase
memory in the transmitter, it is the possible to use most likelihood sequence estimation, and
archive a BER 3 dB better[Haykin 01, p. 394]:
r !
1
Es
Pe,c = erfc
(2.38)
2
N0
2.5.4
Gaussian Minimum-Shift Keying
The GMSK modulation technique is an enhancement of MSK, where a filter is convoluted with the
NRZ encoded bits before generating the modulated signal. The Gaussian filter impulse response
is defined in the time domain as follows:
s
h(t) =
W =
2π
2π 2
W exp −
W 2 t2
ln(2)
ln(2)
BT
Tb
(2.39)
(2.40)
where BT is the time-bandwidth product which determines the softness of the filter. From
section 2.1 it is known that BT ≈ 0.5. BT is mentioned as W Tb in some literature.
Figure 2.21 shows how one square bit is shaped by the Gaussian filter. BT = 0.3 is shown to
compare with the GSM standard.
In Figure 2.22 a Gaussian filtered bit sequence is compared to the unfiltered bit sequence. Figure
2.23 shows the phase that is formed by the same bit sequence.
Figure 2.23 shows the MSK phase that is formed by the same bit sequence, with and without
Gaussian filter.
Figure 2.24 shows how the Gaussian filter improve the power spectral density.
20
2.5. DIGITAL MODULATION
1
MSK
BT = 0.5
BT = 0.3
Amplitude
0.8
0.6
0.4
0.2
0
−2
−1.5
−1
−0.5
0
0.5
Normalized time, t/Tb
1
1.5
2
Figure 2.21: Gaussian filter applied to one bit.
1
0.8
Bit value
fc+Tb/4
No filter
Gaussian filter
0.6
fc
0.4
0.2
fc−Tb/4
0
0
1
2
3
4
Time [bit]
5
6
7
Figure 2.22: Bit sequence 0111001 with and without Gaussian applied filter.
1.5
MSK
GMSK
Phase [π]
1
0.5
0
GMSK –Practical
−0.5GMSK Data Transmission
0
1
4
2
3
Application Note
4
5
6
7
SPECTRAL DENSITY (dB)
Still referring to Figure 3, notice that a bit is spread over
approximately
3 bit periods for BT=0.3 and two bit
Time
[bit]
periods for BT=0.5. This gives rise to a phenomena called inter-symbol interference (ISI). For BT=0.3
adjacent symbols or bits will interfere with each other more than for BT=0.5. GMSK with BT= is equivalent to
MSK. In other words, MSK does not intentionally introduce ISI. Greater ISI allows the spectrum to be more
compact,
making
demodulation
more difficult.
Hence,
spectral
the primary with
trade-offand
in going
Figure
2.23:
Trellis
diagram
showing
the
bit compactness
sequence is0111001
without
from MSK to Gaussian pre-modulation filtered MSK. Figure 4 displays the normalized spectral densities for
Gaussian
filter
applied.
MSK and
GMSK.
Notice the reduced sidelobe energy for GMSK. Utlimately, this means channel spacing can
be tighter for GMSK when compared to MSK for the same adjacent channel interference.
0
MSK
-10
-20
-30
-40
GMSK
BT=0.5
GMSK
BT=0.3
-50
-60
.5
1
1.5
FREQUENCY
BIT RATE
Figure 4: Spectral density for MSK and GMSK
Figure 2.24: Power Spectral Density for MSK and GMSK with BT 0.3 and 0.5
[MX Performance
Com 95, p. 4].
Measurements
The performance of a GMSK modem is generally quantified by measurement of the signal-to-noise ratio
(SNR) versus BER. SNR is related to Eb/N0 by
Eb
S
S B n
N0 RN0 N R where,
S signal power
R data rate in bits per second
N0 noise power spectral density (watts/Hz)
E b energy per bit
B n x N0 N noise power
B n noise BW of IF filter
21
CHAPTER 2. ANALYSIS
2.5.5
Demodulating GMSK
Figure 2.25 shows the degradation in BER as a function of the BT [Haykin 01, p. 399]. This
result is not found analytically, but empirical by means of simulations.
Figure 2.25: BER of GMSK compared to MSK [Haykin 01, p. 399].
In AIS the BT is 0.5, and therefore the degradation in BER is assumed to be about 0.1 dB. Figure
2.26 shows the Gaussian impact on the BER from section 2.5.3.
0
10
−2
10
−4
BER
10
−6
10
msk coherent
gmsk coherent
msk non coherent
gmsk non coherent
−8
10
−10
10
−4
−2
0
2
4
6
8
10
Eb/N0
Figure 2.26: BER of MSK and GMSK.
22
12
14
Chapter 3
Problem Description
The introduction and analysis yields the following problem description:
”How do you construct a software defined radio that can be used on AAUSAT3 to test the possibility to receive AIS signals in space?”
The goal of this project can be divided into the following two subgoals:
1. To develop and test prototype hardware and software for the software defined AIS receiver
for AAUSAT3.
2. To sample raw data on the BEXUS flight, in order to investigate AIS from high altitude.
3.1
Requirement Specification
The receiver must:
1. Be able to sample raw data which contains both AIS channels with a sufficient sample rate
to satisfy the Nyquist sample theorem.
2. Demodulate GMSK in software.
3. Be able to update all parts of the demodulating and decoding software remotely.
4. Be able to compensate for frequency drift, including Doppler shift when the satellite is
moving with 7.5 km/s.
5. Be able to store raw sampled data for 3600 sec (1 hr).
6. Be functional from −40 - +85◦ C.
7. Have a weight of maximally 150 g.
8. Be operating for at least 6 months.
9. Comply with the standards defined by the AAUSAT3 system engineering group.
a) Be able to run at 3.3 V and/or 5 V only.
b) Use no more power than 1 W.
c) Comply with the PCB layout for AAUSAT3 including definition of stack connector and
board outline.
d) Have at least one temperature sensor placed on a central part of the PCB.
23
CHAPTER 3. PROBLEM DESCRIPTION
e) Be able to be controlled completely over CSP.
f) Send telemetry to the LOG subsystem.
3.2
Test Specification
1. Be able to sample raw data which contains both AIS channels with a sufficient sample rate
to satisfy the Nyquist sample theorem.
The front-end and ADC setup is investigated, and it is verified whether the sample rate is
sufficient.
2. Demodulate GMSK in software.
A antenna is connected to the system, and the software demodulator is tested.
3. Be able to update all parts of the demodulating and decoding software remotely.
A changed version of the demodulating and decoding software is written and uploaded to
the subsystem, after which it is tested whether the changes takes effect.
4. Be able to compensate for frequency drift, including Doppler shift when the satellite is moving
with 7.5 km/s.
An artificial signal with a worst case frequency drift in both directions is generated using a
GMSK modulator, and it is observed whether the signal is demodulated correctly.
5. Be able to store raw sampled data for 3600 sec (1 hr).
The receiver is admitted to run until the memory limit is reached, and the amount of raw
data is observed.
6. Be functional from −40 - +85◦ C.
The receiver is tested for worst case temperatures, and in vacuum chamber.
7. Have a weight of maximally 150 g.
The weight of the experiment setup is measured.
8. Be operating for at least 6 months.
9. Comply with the standards defined by the AAUSAT3 system engineering group.
a) Be able to run at 3.3 V and/or 5 V only.
The required input voltages to the system is observed.
b) Use no more power than 1 W.
The power consumption is measured with the system running fully operational.
c) Comply with the PCB layout for AAUSAT3 including definition of stack connector and
board outline.
The size of the PCB is measured and the electric interface is tested.
d) Have at least one temperature sensor placed on a central part of the PCB.
Tested by observing and measuring using the on board sensor.
e) Be able to be controlled completely over CSP.
Commands is sent to the subsystem, and it is checked whether the correct messages is
returned.
f) Send telemetry to the LOG subsystem.
It is observed whether the relevant telemetry data is logged.
24
Chapter 4
Design
The purpose of this chapter is to give an overview of the simulation setup used to design and
test the GMSK demodulator. MATLAB code will be used to test the quality of these methods
before implementing the decoder on a DSP. To ensure relevant testing data, a GMSK modulator
which creates the same output as expected from the front-end is programmed. Note that only
some parts of the code is shown in this report. The complete source code can be found on the
attached CD. Figure 4.1 shows the included parts in the signal path. A front-end, ADF7020Information
Source
AIS Data
Encapsulation
GMSK
Modulator
+
Information
Sink
AIS Data
Extraction
GMSK
Demod
Pack Detect
Freq. Estimate
Figure 4.1: Simulation setup overview.
1[Analog Devices 05], has been selected as downconverter. This is due to the fact that it has
been used previously in the AAUSAT3 project, and because it fits the requirements for the AIS
receiver. The ADF7020-1 is a complete transceiver, but can be used as a downconverter only.
When correctly configured, the receiver downconverts from 162 MHz to an intermediate frequency
of 200 kHz, such that the two AIS channels will be centered around 175 kHz and 225 kHz. Both the
in-phase and the quadrature output is available from the downconverter. The front end contains
an image rejection filter rejecting frequencies outside the band from 150 kHz to 250 kHz. The
configuration is described in section 6.5.
The simulation setup must therefore have the properties as seen in table 4.1 to match the
specifications of respectively the AIS standard and the properties of the chosen front-end.
25
CHAPTER 4. DESIGN
Parameter Name
AIS channel 1
AIS channel 2
Pandpass filter
Modulation scheme
Carrier frequency drift
Modulation index
BT product
Bit rate
Training sequence
Start and stop byte
Total packet length
Setting
Unit
175
225
150 – 250
GMSK
±4
∼ 0.5
∼ 0.5
9.6
24
0x7E
224
kHz
kHz
kHz
kHz
max
kbps
bits
Table 4.1: Requirements to the modulator.
4.1
Information Source
The information source uniformly distributed random bits. A CRC16 calculator is not implemented, so the bits corresponding the FCS are also random bits. In AIS this is the real data, such
as MMSI and position, here denoted Ik .
4.2
AIS Data Encapsulation
The output from the information source must be encapsulated prior to modulation, in order
to resemble an AIS packet. This section describes the bit stuffing, HDLC framing and NRZI
encoding.
4.2.1
Bit Stuffing
The encapsulated data must be bitstuffed due to the definition of HDLC and the AIS standard.
In Code Example 4.1 MATLAB is first used to find sequences of 5 or more 1’s. After this, it is
checked whether these results are valid. This is because if for example seven 1’s will appear in
a row, MATLAB will return 3 values, althrough only the first one should be used. When the
superfluous placements has been found and removed, an extra zero is added each time five 1’s
appear in a row in the data.
1 b i t s t u f p l a c e m e n t = f i n d s t r (U, [ 1 1 1 1 1 ] ) ;
2 % Remove r e s u l t s t h a t l e s s than 5 b i t s a p a r t
3 i i = 2;
4 while i i <= length ( b i t s t u f p l a c e m e n t )
5
i f b i t s t u f p l a c e m e n t ( i i ) < b i t s t u f p l a c e m e n t ( i i −1) + 5 , \
6
bitstufplacement ( i i ) = [ ] ;
7
else , i i = i i + 1 ; end
8 end
9 % Insert the actual b i t s t u f f i n g
10 f o r i i = 1 : length ( b i t s t u f p l a c e m e n t )
11
U = [U( 1 : b i t s t u f p l a c e m e n t ( i i ) +4) 0 \
12
U( b i t s t u f p l a c e m e n t ( i i ) +5: length (U) ) ] ;
13 end
Matlab Code 4.1: Bit stuffing.
26
4.2. AIS DATA ENCAPSULATION
4.2.2
HDLC Frame Format
After bit stuffing, the frame must be encoded due to the AIS standard, i.e. the start flag (0x7E) is
added to the start and the end of the content. Code Example 4.2 shows this procedure. Also, the
24 alternating bits are added in this example, such that the packet contains all the information
that shall be modulated after NRZI encoding. Note line 1 where a random bit is chosen to decide
whether the training sequence shall start with either a 0 or a 1. This is due to the uncertainty of
the initial NRZI state.
1
2
3
4
5
6
7
8
j j = rand ( 1 ) <0.5;
f o r i i =1:24
t r a i n i n g ( i i ) = mod( i i +j j , 2 ) ;
end
STX = [ 0 1 1 1 1 1 1 0 ] ;
U = [ t r a i n i n g STX U STX ] ;
U = NRZI(U, rand ( 1 ) <0.5) ;
Matlab Code 4.2: HDLC encoding.
4.2.3
NRZI Encoding
The NRZI (Non Return to Zero Inverted) is the next part of the simulator. It is implemented in
Code Example 4.3.
1
2
3
4
5
6
U = [ round ( rand ( 1 ) ) U ] ;
f o r i i = 2 : length (U)
i f U( i i ) == 1 , U( i i ) = i n v e r t (U( i i −1) ) ; ,
e l s e i f U( i i ) == 0 , U( i i ) = U( i i −1) ; , end
end
x = x ( 2 : length ( x ) ) ;
Matlab Code 4.3: NRZI encoding.
In this example, a random bit is inserted at the start of the bit stream. This simulates the two
possibilities for the start of the transmission that can be expected. An example of the two ways
a bit stream can be encoded, is shown in example 4.2. The initial state of the NRZI encoder is
listed in the second column.
Original Stream:
NRZI:
NRZI:
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
Table 4.2: The two ways a bit stream can be NRZI encoded.
27
CHAPTER 4. DESIGN
4.3
GMSK Modulator
In this section, a GMSK modulator that accepts a bit streams as input will be created in MATLAB.
The output of the modulator must be a 1 Msps signal. This choice is based on the expected output
of the ADF7020-1 front-end chip.
4.3.1
Gaussian Filtering
The NRZI encoded data stream must be applied a Gaussian filter to fulfil the definition of GMSK.
Figure 2.21 shows a square pulse convoluted with a Gaussian filter for varying time-bandwidth
products. The variable Fs defines samples per second while W is the time-bandwidth product. XUj
is the bitstream, but with Tb/Fs samples per bit.
1
2
3
n = linspace ( −150 , 1 5 0 , 3 0 1 ) ;
g a u s s = sqrt ( 2 ∗ pi / log ( 2 ) ) ∗W∗exp(−2∗ pi ˆ2/ log ( 2 ) ∗Wˆ 2 ∗ ( n/ Fs ) . ˆ 2 ) / Fs ;
XUj = conv ( XUj , g a u s s ) ;
Matlab Code 4.4: Gaussian filtering.
Code Example 4.4 shows the creation of the Gaussian pulse by formula 2.39 and the convolution
of this and the array XUj, which contains the data stream sampled at F s. Note that the filter is
normalized by the variable Fs (samples per second).
4.3.2
Phase Establishment
The filtered bit stream must be used to generate the phase used for modulating the carrier
frequency, as described in section 2.5.
1
2
3
4
5
XUj = ( XUj−0.5) ∗ 2 ;
P( 1 ) = 0 ;
f o r i i =2: length ( XUj )
P( i i ) = p ( i i −1) + XUj ( i i ) ∗ pi ∗h/ spb ;
end
Matlab Code 4.5: Phase Generation.
Code Example 4.5 shows the construction of the phase in discrete time. The variable h is the
deviation which in MSK in equal to 1/2. The phase change is normalized by spb (samples per bit),
so that a phase turn of π · h = π/2 will occur at each bit, either positive or negative correspondint
to the transmitted bit.
4.3.3
Frequency Modulation
The array XUj that now contains the gaussian filtered phase of the desired signal, will be used to
create the frequency deviation during the frequency modulation.
Code Example 4.6 shows the frequency modulation. First a random carrier frequency ± 4 kHz,
according to section 2.1.3 is chosen to simulate a possible Doppler shift. A delay is then added
to randomize the start of the bits, so a realistic test of the bit synchronizer is possible. The
modulated signal gm is a combined version of I and Q, which is produced by formula 2.30.
4.3.4
Signal Addition
In the above sections, a GMSK signal has been generated. To fulfil the requirements of the
AIS standard, two modulated signals must be added to simulate the use of the two channels.
28
4.4. AWGN CHANNEL
1
2
3
4
f c = f c − 4000 + 8000∗ rand ( 1 ) ;
f o r i i = s t a r t d e l a y +1 : l e n
X( i i ) = cos ( 2 ∗ pi ∗ i i ∗ f c / Fs + P( i i ) ) ;
end
Matlab Code 4.6: Frequency modulation.
The signals is transferred at 161.975 MHz and 162.025 MHz, which corresponds to 175 kHz and
225 kHz when downconverted through the selected front-end. Therefore, the code from the above
sections is executed twice to generate the two signals before they are combined as shown in Code
Example 4.7.
1
X = X1 + X2 ;
Matlab Code 4.7: Signal addition.
4.4
AWGN Channel
The modulated signal, X, must have noise added to simulate the wireless channel. Therefore, the
code in Code Example 4.8 is generated to add Gaussian noise to the signal using the MATLAB
function AWGN(). The input signal-to-noise is pr. sample (SN Rb), which is the desired SNR
divided by the number of samples pr. bit. After the signal is bandpass filtered to make the same
bandwidth as the output from the ADF7020-1 radio front-end. The filter used is a 5th order
Butterworth filter which is the same as used in the actual front-end. The variable SNR is the
desired signal-to-noise ratio while fci is the center frequency of the downconverted signal and BW
is the bandwidth of the filter. The bandwidth is planned to be 100 kHz, but is adjustable in the
frontend. SNR is the signal-to-noise ratio per sample, and SNRb.
1
2
SNRb = SNR − 10∗ log10 ( Fs ∗Tb) ;
Y = awgn (X, SNRb) ;
Matlab Code 4.8: AWGN Channel
1
2
3
4
low = 2 ∗ ( f c i −BW/ 2 ) / Fs ;
h i g h = 2 ∗ ( f c i +BW/ 2 ) / Fs ;
[ b , a ] = b u t t e r ( 5 , [ low h i g h ] ) ;
Y = f i l t e r ( b , a , Y) ;
Matlab Code 4.9: IF filter
4.5
Packet Detection
The first part of the AIS decoding is the packet detection. It is important that the packet detection
is fast, so that it is possible to execute the detector on the DSP in real-time. In the following
section, a detector using FFTs is described.
29
CHAPTER 4. DESIGN
When the detector is running, it continuously evaluates an FFT of a few bits durations,
equalling a few hundred samples. The FFTs are calculated with a step so an AIS packet is
guaranteed to be included in at least one FFT. The approximate area that is used for Fouier
transforms is seen in Figure 4.2. Computational power will be saved by not calculating the FFT
of the entire dataset. The areas of the FFTs just have to be large enough to reach sufficient
frequency resolution. Zero padding to improve the resolution will have no purpose in this case,
because calculating the FFT over more data will need allmost the same computation power. The
3
2
1
0
−1
−2
−3
80
90
100
110
120
130
140
Time [ms]
150
160
170
180
Figure 4.2: Continuously fourier transforms in selected areas.
frequency analysis is filtered by convolving with a Blackman window after which the value at
200 kHz and the maximum value between the two spectrums of the AIS channels, approximately
170 kHz – 180 kHz and 220 kHz – 230 kHz, is found. The difference of the 200 kHz value and
the maximum value of the two AIS channels is used to determine whether the data that has
been basis for the Fouier transform contains any AIS packets. Note that because the FFT used
is very rough, no accurate frequency estimation is performed by this method. Figure 4.3 shows
the frequency spectrum when a packet is detected. If the maximum value of the filtered FFT is
8
Contains no signal
Contains AIS signal on ch. 2
6
4
2
0
0
50
100
150
200
250
300
Frequency [kHz]
350
400
450
500
Figure 4.3: Rough FFT.
above the determined threshold, the data around the discovered packet is sent to a new function
which seeks the data more accurate for finding the precise packet start and stop. The frequency
estimation also uses FFTs, but with a smaller step size. The start and stop of the signal is now
marked to be in the first couple of bits in the training sequence and a few bit times after the stop
bit.
30
4.6. FREQUENCY ESTIMATION
4.5.1
Verification of Packet Detection
The packet detector is verified by creating 100 seconds of simulated output from the RF frontend,
each containing 1 AIS packet on each channel. Packets are subject to frequency drift and time
randomization. The signal is generated with an SNR of 20 dB and 1 Msps. Figure 4.4 shows the
difference from the actual packet start to the detected packet start. 1 bit equals approximately
104 µs which means that between 1 and 4 bits of the training sequence is missing. 187 of 200
packets was detected. This number might be possible to increase by fine tuning variables.
400
350
Delay [µs]
300
250
200
150
100
50
0
0
20
40
60
80
100
120
Test number
140
160
180
200
Figure 4.4: Test of packet detection.
4.6
Frequency Estimation
The frequency estimation exploits the 24-bit training sequence of the AIS packet. When the
training sequence is found by the packet detector, an FFT over a multiple of 4 bits (maximum 16
to avoid that the FFT is made partly over the start sequence) is calculated. By calculating the
FFT over a multiple of four bits, the training sequence will contain an equal number of 1 and 0
bits, so that the center frequency will appear as the maximum value when applying a suitable filter
on the FFT. Note that zero padding is possible if considered neccesary for making an accurate
frequency estimation. Figure 4.5 shows an FFT of 4 training sequence bits, zero padded to a
total length of 12. An improvement of the frequency estimation could be to correlate the signal
5000
4000
3000
2000
1000
0
0
100
200
300
Frequency [kHz]
400
500
Figure 4.5: FFT of training sequence.
31
CHAPTER 4. DESIGN
by signals of different frequency when the approximate freqency has been estimated by above
method, and select the frequency with the highest correlation coefficient. This has not yet been
implemented.
4.6.1
Verification of Frequency Estimation
The packet detector is verified by creating 100 seconds of simulated output from the RF front-end,
each containing 1 AIS packet on each channel. Packets are subject to frequency drift and time
randomization. The signal is generated with a SNR of 20 dB and 1 Msps per second. The packet
detector is used to find the packets, which is why only 185 tests are performed. Figure 4.6 shows
the difference from the actual modulation frequency to the frequency detected. The figure shows
that most frequencies are found with a variation less than 200 Hz. This precision is possible to
increase by using correlators when the approximate frequency is found.
Frequency deviation [Hz]
600
400
200
0
−200
−400
−600
0
20
40
60
80
100
120
Test number
140
160
180
200
Figure 4.6: Test of frequency estimation.
4.7
GMSK Demodulator
The demodulator is designed as described in Section 2.5.3. First, two waveforms are generated,
used to search for f1 and f2 , which is placed around the center frequency found by the frequency
estimator.
f∆
f1 = fc −
(4.1)
2
f∆
f2 = fc +
(4.2)
2
The two waveforms are generated over one bit time, Tb , with the sample rate Fs :
1
, n ∈ {0, 1, 2, ..., spb − 1, spb}
Fs
waveform1 = cos (2πtf1 )
(4.4)
waveform2 = cos (2πtf2 )
(4.5)
t=n
(4.3)
Yj is the received signal. Let Yj,1 denote the cross correlation between waveform1 and Yj . That
is:
Yj,1 (m) =
N −m−1
X
n=0
32
waveform1n+m Yn
(4.6)
4.7. GMSK DEMODULATOR
And similar for Yj,2 . A simple example of a correlator is shown in Figure 4.7. Here, the correlation
between one period of a sine is correlated with two periods of a cosine. Figure 4.8 shows the actual
1
0.5
0
x
y
−0.5
−1
0
10
20
30
40
50
60
70
20
xcorr(x,y)
10
0
−10
−20
0
20
40
60
80
100
120
140
n
Figure 4.7: Example of a correlator.
demodulator. The correlator, or product integrator, is used and a soft output of the bit stream
Uj,s is generated. The bit synchronization is illustrated by a switch sampling at every Tb . Figure
Figure 4.8: The demodulator.
4.9 shows the correlator output Yj,1 and Yj,2 , of a training sequence and start flag at 25 dB SNR.
4.7.1
Bit Synchronization
The Bit synchronization is used to recover the clock of the received signal. The 24 bit NRZI
encoded training sequence in the AIS standard ensures 11 bit transactions and thereby 11 zero
crossings in the correlator demodulator output. The packet detector determines the package start
and use this to ensure that the correlator demodulator starts just at the beginning of the training
sequence. Therefore, the first 10 zero crossings are used to estimate the bit placement. The packet
detector might miss the first zero crossing due to inaccuracy in the detection. First, the zero crosses
33
CHAPTER 4. DESIGN
70
Yj,1
Yj,2
60
50
40
30
20
100
200
300
400
Sample no.
500
600
700
Figure 4.9: The waveform demodulator output Yj,1 and Yj,2 .
are detected. This is done in Code Example 4.11.
1
2
3
4
5
6
7
j =1;
f o r i i =2: length ( Ujs )
i f ( sign ( Ujs ( i i ) )˜= sign ( Ujs ( i i −1) ) )
c r o s s d e t e c t e d ( j ) = i i −1 −0.5;
j = j +1;
end
end
The first 10 zero crossings are then used to
% Zero−c r o s s d e t e c t number
% I f s i g n has changed
% save zero cross placement
%
Matlab Code 4.10: Zero cross detection
determine the bit placement best fitted for the mean of this training sequence, knowing that the
time 2Tb is expected between each zero crossing. This is shown in Code Example 4.11.
1
2
3
4
5
6
7
crossdetected = crossdetected (1:10) ;
error = 0 ;
f o r i i = 1 : length ( c r o s s d e t e c t e d )
c u r r e n t e r r o r = c r o s s d e t e c t e d ( i i ) − ( i i −1) ∗ ( 2 ∗ spb / d e c i m a t i o n ) ;
error = error + c u r r e n t e r r o r ;
end
b i t p h a s e = error / length ( c r o s s d e t e c t e d ) ;
Matlab Code 4.11: Bit phase determination
Using the accumulated error per bit, the bit phase, the final bit placement in the pack is
determined. This bit synchronization ”lock” is used throughout the package, by adding the
expected bit time Tb between each reading of the bit value. In Code Example 4.12 nobits is the
number of bits expected throughout the soft output bit stream U js.
Further work is needed to
evaluate if the bit synchronization algorithm needs to be adaptive, to compensate for clock and
frequency drifts, when receiving longer AIS packets.
34
4.7. GMSK DEMODULATOR
1
2
3
4
5
6
7
n o b i t s = f l o o r ( ( length ( Ujs )−b i t p h a s e ) / ( spb / d e c i m a t i o n ) ) ;
for i i = 1 : n o b i t s
b i t p l a c e m e n t ( i i ) = round ( \
bitphase \
+ ( i i −1)∗ spb / d e c i m a t i o n \
+ spb / d e c i m a t i o n / 2 ) ;
end
Matlab Code 4.12: Final bit placement
4.7.2
Decision rule
The hard decision rule is as follows:
U j h a t = ( sign ( Ujs ( b i t p l a c e m e n t ) ) +1) / 2 ;
Matlab Code 4.13: Decision Rule
At each bit placement the sign of the soft output (U js) from the demodulator is read. The
sign is then converted from the range [−1 : 1] to [0 : 1]. Figure 4.10 shows the implemented
decision rule, where the blue dots indicates a bit placement.
4.7.3
Verification of GMSK Demodulator
Figure 4.10 shows the soft output, U js, of the demodulator, simulated at 25 dB SNR. The
corresponding U j is 0b00110011... Figure 4.11 shows a simulation where the demodulator part
30
20
Demodulator soft output
1
10
0
−10
−20
−30
100
200
300
400
500
Sample no.
600
700
800
Figure 4.10: Soft output from the demodulator and bit placements.
itself is tested, estimating perfect bit synchronization.
The test is performed by modulating 20000 random bits for each SNR from 1 to 25 dB. AWGN
is added to get the desired SNR, and the demodulator estimates the transmitted bits. The
transmitted data is then compared to the demodulated and the number of errors are divided by
35
CHAPTER 4. DESIGN
0
10
−1
10
−2
BER
10
−3
10
−4
10
−5
10
Theoretic MSK NC
Simulated MSK
Simulated GMSK
−6
10
−5
0
5
10
SNR [dB]
15
20
25
Figure 4.11: Test of GMSK demodulator
the total number of bits to calculate the BER. This is done both for MSK and GMSK with BT
product 0.5.
4.8
AIS Data Extraction
The AIS data extracion performs the inverse operations of the data encapsulation. Each operation
is explained in the following section.
4.8.1
NRZI Decoding
The first operation when receiving the raw demodulated bit stream, is the NRZI decoding. In
Code Example 4.14 the procedure for this step is shown. The overall idea is to look at the bit
shifts to decide whether a bit transition has occurred. In such case, a 0-bit has been transmitted,
otherwise a 1-bit was sent.
1
2
3
4
f o r i i =1: length ( Uj )−1
i f Uj ( i i ) ˜= Uj ( i i +1) , Uj ( i i ) = 0 ;
else , Uj ( i i ) = 1 ; , end
end
Matlab Code 4.14: NRZI decoding
4.8.2
HDLC Decoding
After the NRZI decoding, the start and stop flags must be found. Code Example 4.15 shows this
procedure in line 1. The code example also shows the extraction of the packet from the sequence
(line 6) after it has been checked whether both the start and stop flag has been found. After the
extraction, it is checked whether the packet is long enough to re recognised as a valid AIS packet.
36
4.8. AIS DATA EXTRACTION
In such case, the bit destuffing is executed by searching after five consecutive 1-bits in a row, after
which the following 0-bit bit is removed.
1 placement = f i n d s t r ( Uj , [ 0 1 1 1 1 1 1 0 ] ) ;
2
3 % P a c k e t found ?
4 i f length ( placement ) > 1
5
% E x t r a c k t pack from s t a r t and s t o p
6
rawpack = Uj ( placement ( 1 ) +8: placement ( 2 ) −1) ;
7
8
i f length ( rawpack ) >150
9
% Bit d e s t u f f i n g
10
b i t s t u f p l a c e m e n t = f i n d s t r ( Uj , [ 1 1 1 1 1 ] ) ;
11
f o r i i = 1 : length ( b i t s t u f p l a c e m e n t )
12
Uj ( b i t s t u f p l a c e m e n t ( i i ) +5−( i i −1) ) = [ ] ;
13
end
14
...
15
16
end
17 end
Matlab Code 4.15: HDLC decoding
4.8.3
Data Extraction
When the packet has been extracted, a CRC check should be executed to validate the packet
content. A CRC check has been prepared to be implemented, although the implementation of the
CRC routine itself is outside this project scope. Code example 4.16 shows the procedure to get
the message ID, which is saved as Ij(1). The MMSI number of the transmitting ship (Ij(2))
and the FCS checksum are extracted in the following lines.
1
2
3
I j ( 1 ) = b i n 2 d e c ( strrep ( i n t 2 s t r ( Uj ( 1 : 6 ) ) , ’
’ , ’ ’));
I j ( 2 ) = b i n 2 d e c ( strrep ( i n t 2 s t r ( Uj ( 9 : 3 8 ) ) , ’
’ , ’ ’));
I j ( 3 ) = CRCcheck ( Uj ) ;
Matlab Code 4.16: Data extraction.
37
Chapter 5
Proof of Concept
To proof the receiver concept, a simple version of the receiver is implemented. For simplicity, a
standard PC with MATLAB is used for signal processing and an analog sampling card is used to
sample the output from a development board radio receiver.
The ADF7021 development board used by 09gr650 is used for the proof of concept. The receiver
is configured over SPI, using a microcontroller platform developed for AAUSAT3 (AT90CAN128
[08gr414 08]). The receivers Local Oscillator (LO) is programmed to 161.925 MHz, thereby centering AIS ch. 2 (162.025 MHz) at the 100 kHz IF frequency. The Automatic Frequency Control
(AFC) is disabled to ensure that the LO is fixed, rather than searching for a signal. The Automatic Gain Control (AGC) is used to ensure sufficient amplitude of the output. The ADF7021
has a differential output after the IF filter, thereby giving a 25 kHz bandwidth centered around
the IF frequency, and providing image rejection.
A standard PC and an analog sampling card are used to sample the differential IF output
using two analog 16-bit channels at 500 kSps. Furthermore, the Low Noise Amplifier and antenna
described in section 6.1 are used for the receiver. Finally, the setup is places on the roof of the
university, to ensure good reception and minimize obstacles in the line of sight.
Figure 5.1: The Proof of Concept setup on the roof.
39
CHAPTER 5. PROOF OF CONCEPT
Figure 5.2: FFT waterfall plot of raw received data.
Figure 5.2 shows an FFT waterfall plot of 25 seconds of sampled data, in the frequency range
from 80 to 120 kHz. AIS packets are clearly visible as high amplitude bursts centered at 100 kHz.
The raw sampled data can be found in 2.mat on the attached CD.
Figure 5.3 shows the correlator demodulator output from time 22.1 sec. and onwards. The
green dots indicate a detected zero-crossing, and the blue crosses indicates where to apply the
decision rule to read a bit value. The output shows the 20 bits of NRZI encoded training sequence,
the 0x7E HDLC start flag and the first 10 bits on the AIS packet. Figure 5.4 is generated by
50
40
30
Relativ "Soft" bit
20
10
0
−10
−20
−30
−40
−50
0.5
1
1.5
2
2.5
3
3.5
Time [s]
4
−3
x 10
Figure 5.3: Correlator output from 22.1 sec. and forward.
reading the output of the two correlators on the estimated bit-placement positions. The content
of each of the orthonormal basis functions ψ1 andψ2 is plotted to show the signal constellation of
the received package. The dashed line illustrates the decision rule boundary. The hard decision
of the bit placements yields the following bit sequence:
01100110 01100110 11111110 10100101 01010101 10010100 001100...
40
80
70
60
ψ2
50
40
30
20
10
0
0
10
20
30
40
ψ1
50
60
70
80
Figure 5.4: Signal constellation of the received package.
The initial state of the NRZI output stream is unknown, so the NRZI decoded data is:
?0101010 10101010 01111110 00001000 00000000 10100001 110101...
The raw data package, when omitting the training sequence and start flag (01111110), therefore
is:
00001000 00000000 10100001 11010101 00101011 10111110 01010100 11010101...
After bit destuffing the packet is:
00001000 00000000 10100001 11010101 00101011 10111110 10101001 1010101...
HDLC frames are transmitted with LSB first, so the endianness is reversed to get MSB first:
00010000 00000000 10000101 10101011 11010100 01111101 10010101...
The 16-bit CRC16 checksum 01111000 10000011 is successfully validated with software written
by the user Steve Underwood from the signal processing forum at dsprelated.com [dsprelated.com 07].
His code can be found in checkcrc.c on the attached CD. The first 6 bits in the packet indicate
the Message ID. Packet type 000100 = 4 is Base station reports. The rest of the packet is decoded
according to the AIS standard [ITU 07, p. 100]. The output parameter, bit placement, value and
description are listed in table 5.1. The longitude and latitude is converted to degrees:
5894510
= 9.824183 ◦ E
10000 · 60
(5.1)
34202243
= 57.003738 ◦ N
10000 · 60
(5.2)
Longitude =
Latitude =
41
CHAPTER 5. PROOF OF CONCEPT
Parameter
Number of bits
Value
Description
Message Type
Repeat indicator
User ID
UTC year
UTC month
UTC day
UTC hour
UTC minute
UTC second
Position accuracy
Longitude
Latitude
6
2
30
14
4
5
5
6
6
1
28
27
4
0
002190069
2009
5
21
12
19
51
0
5894510
34202243
Identifier for this message
Number of message repetitions.
MMSI number
1-9999; 0 = UTC year not available
1-12; 0 = UTC month not available
1-31; 0 = UTC day not available
0-23; 24 = UTC hour not available
0-59; 60 = UTC minute not available
0-59; 60 = UTC second not available
1 = >10 m; 0 = <10 m; 0 = default
Longitude in 1/10 000 min
Latitude in 1/10 000 min
Table 5.1: Received AIS package decoded.
This position is verified by finding the position of MMSI 002190069 online. MMSI 002190069
is known as the Frejlev Transmitter, placed approximately 10 km from the experiment setup.
MMSI numbers starting with 00 are base stations, while 219 is the Maritime Identification Digits
used for danish ships and base stations. Figure 5.5 shows a screenshot from Google Maps of the
transmitter position.
Figure 5.5: The Frejlev Transmitter in Google Maps.
42
Chapter 6
Implementation
Figure 6.1 shows the signal path through the AIS receiver. The implementation of each block,
from antenna to signal processor, is described in this chapter. The algorithms from Chapter 4 are
not implemented on the Digital Signal Processor, so the section on the DSP is concentrated on
selecting a suitable implementation platform for the BEXUS flight.
LNA
Splitter
RF
Front-end
ADC
DSP
To HW-AIS
Figure 6.1: Hardware overview.
6.1
VHF Antenna
A maritime VHF dipole designed for signals with a frequency of 156–162 MHz is used for the
receiving antenna. The length of the antenna itself is 90 cm which approximately makes it a half
wave dipole for AIS signals:
c
λ
=
= 92.5 cm ≈ 90 cm
2
2 · 162 M Hz
(6.1)
The impedance of a half wavelength is approximately 73 + j42.5 Ω, but the antenna is impedance
matched to 50 Ω, which is the same as the LNA and cables used in the signal path.
6.2
Low Noise Amplifier
The purpose of the Low Noise Amplifier (LNA) is to amplify the signal close to the VHF antenna,
in order to introduce as little noise as possible. The antenna will be mounted underneath the
BEXUS gondola, so the LNA and a filter are placed inside a small box suitable for mounting
external to the gondola.
6.2.1
Mechanical Design
The LNA must have interfaces to the antenna and the experiment box. The antenna is fitted
with a female UHF connector, so for simplicity this type of connector is used for both interfaces
43
CHAPTER 6. IMPLEMENTATION
to the LNA box.This also makes it possible to remove the LNA and test the connection without
extra amplification. A male-male adapter will be used to connect the LNA case to the antenna.
The box is 80x55x25 mm and weighs 79 g. The assmbled LNA box is shown in Figure 6.2.
Figure 6.2: LNA box with UHF connectors.
6.2.2
Electronic Design
The Maxim MAX2371 EVKit development board is used for the LNA. A 3rd order Chebyshev
low pass filter with 0.5 dB ripple, designed to attenuate UHF frequencies, is mounted directly
on the development board. The normalized Chebyshev filter is calculated using the MATLAB
function cheby1. Scaling the transfer function to a 180 MHz cutoff frequency yields the following
transfer function:
1
2
3
1.0352e27
H(s) = 3
2
s + 1.4168e9 · s + 1.9630e18 · s + 1.0352e27
A
(6.2)
Equation (6.2) is realized as a third order LC ladder filter of two capacitors and one inductor. An
LC ladder filter is chosen to have as few components as possible through the signal path. The
circuit realized with ideal components is illustrated in Figure 6.3.
L1
R_in
In
50R
Out
48.5nH
C1
28.2pF
R1
50R
C2
28.2pF
GND
B
Figure 6.3: CLC filter with ideal components.
L1_R2
L1_C
Two simulations of the filter has been performed.
One with ideal components and one where
10R
0.111pF
the ideal components are changed to match the ones
available in the department laboratory. The
L1
L1_R1
R_in
schematics for the simulation
is 50R
shown in Figure
6.4,47nH
while the results of the simulations
are shown
In
Out
0.2R
R1
C1_R
C2_R
in Figure 6.5.
50R
0.2R
0.2R
C
44
C1
27pF
C1
27pF
C1_L
1nH
C2_L
1nH
GND
28.2pF
28.2pF
GND
6.3. SAW FILTER
L1_R2
10R
R_in
In
50R
L1_C
0.111pF
L1_R1
L1
0.2R
47nH
C1_R
0.2R
Out
R1
50R
C2_R
0.2R
C1
27pF
C1
27pF
C1_L
1nH
C2_L
1nH
GND
Figure 6.4: CLC filter with real components.
0
Gain [dB]
1
Title
Ideal components
Real components
−10
Size
−20
A4
−30
Date:
File:
2
3
−40
−50
−60
−70
100
200
400
800
Frequency [MHz]
Figure 6.5: Simulation of Chebychev filter with real and ideal components.
6.2.3
Test
The LNA configuration and filter performance has been tested with a signal generator and a
network analyzer. The main reason for using the filter is the transmitter from the service module
on the BEXUS balloon, transmitting at 402.2 MHz [SSC 09]. Therefore special attention is given
to the attenuation at this frequency. Figure 6.6 and 6.7 plots the LNA amplification with and
without the filter applied. The attenuation of approximately 30 dB at 402 MHz is assessed to be
sufficient, without disturbing the desired signal at 162 MHz. At 162 MHz, the LNA gives a gain
of approximately 14 dB, which is considered enough for the BEXUS flight.
6.3
SAW Filter
To remove as much unwanted signal as possible, a SAW filter is inserted in the signal path. The
main disturbance will be the BEXUS EBASS signal transmitted on 402.2 MHz [SSC 09]. SAW
filters designed for a 162 MHz pass band and with a low insertion loss are rare, as the frequency is
not used by much equipment. However, the LBT16201 from the Chinese company SIPAT matches
the AIS bandwidth very well. The LBTs frequency response is shown in Figure 6.8. The filter has
a relatively high insertion loss of 2 dB, and is therefore placed after the signal has been amplified
by the LNA. Unfortunately, the filter did not arrive before the project submission and is therefore
not tested.
45
Number
10/05/2009
Sheet1.SchDoc
CHAPTER 6. IMPLEMENTATION
20
Without filter
With low pass filter
Gain [dB]
0
−20
−40
−60
100
200
Frequency [MHz]
400
800
Figure 6.6: Test of LNA with and without filter applied.
16
Without filter
With low pass filter
Gain [dB]
14
12
10
China Electronics Technology Group Corporation
No.26 Research Institute
8
S6IPAT Co., Ltd.
140
w120
ww. sipatsaw
.com
170
Par
200
Frequency [MHz]
Figure Typical
6.7: Test of Performance
LNA with and without filter applied, focus on AIS frequencies
(162 MHz).
Frequency Respond
Passba
Type Performance
7.9956
-0.5044
-2.0044
-1.0044
-12.0044
-1.5044
-22.0044
Magnitude(dB)
-2.0044
-32.0044
-2.5044
-42.0044
-3.0044
-52.0044
-3.5044
-62.0044
-4.0044
-72.0044
-82.0044
-4.5044
156
158
160
162
Frequency(MHz)
164
166
168
Horizontal:
2MHz/Div
Vertical:
Figure
6.8: SAW
filter frequency response
[SIPAT10dB/Div
Co. 09].
160
Type Performance
15
900
10
800
700
5
X: 162.7
Y: 540.7
(deg)
Time(ns)
X: 161.7
Y: 602.1
X: 162.2
Y: 555
161
Phase Line
1000
600
161
Horizontal: 0.5MHz/Div
Group Delay Variation(f0±0.5MHz)
46
160.5
0
0.04
0.04
0.11
1.03
1.04
1.05
0.01
28.15
0.01
26.67
0.01
25.63
6.4. POWER SPLITTER
0.01
24.87
0.00
24.45
0.07
0.12
0.08
0.14
0.19
1.06
1.08
1.09
1.09
1.09
3.33
3.32
0.00
24.36
340.00
3.37
3.37
0.01
24.50
F powerGsplitter must be360.00
3.38
3.37
A
inserted to split
the signal
to the other0.00
AIS receiver on 24.69
the BEXUS
.055
.100
380.00
3.42
3.42
0.00
24.97 splitter
experiment, as only a single VHF antenna is mounted on the balloon. An ADP-2-1 passive
400.00
3.41
3.41
0.00
25.39
1.40
2.54
0.26
0.29
0.24
0.28
0.37
1.08
1.07
1.07
1.05
1.04
ggested Layout,
ce to be within ±.002
30.00
60.00
90.00
3.16
3.18
3.21
3.16
3.19
3.21
0.00
0.01
0.00
120.00
160.00
200.00
240.00
280.00
3.21
3.26
3.28
3.29
3.34
3.22
3.25
3.27
3.27
3.35
33.18
31.23
29.53
ensions ( inch
6.4) Power Splitter 320.00
mm
by Mini-Circui is used due to its low insertion loss (0.3 dB at 160 MHz) and small footprint. A
frequency
in Figure 6.9.
wt plot of the power splitter is shown ADP-2-1
INSERTION LOSS
grams
4.0
40
0.25
MCL P/N: TB-208
B Layout (PL-116)
S-1(dB)
ADP-2-1
ISOLATION
S-2(dB)
3.8
ISOLATION (dB)
L
300
.62
E
.162
4.11
INSERTION LOSS (dB)
D
100
.54
3.6
3.4
3.2
3.0
35
30
25
20
0
50
100
150
200
250
300
350
400
0
50
FREQUENCY (MHz)
100
150
200
FREQUENC
ADP-2-1
VSWR
1.20
Figure 6.9: Power Splitter insertion loss.
#S-VSWR
#1-VSWR
electrical sc
#2-VSWR
1.15
RF Front-end
VSWR
6.5
1.10
ADF7020-1 from Analog Devices is used as radio front-end for the software defined AIS receiver.
The ADF7021 with similar
1.05 configuration, is used by 09gr650 and for the UHF radio on AAUSAT3.
The ADF7020-1 is able to output the in-phase, I and quadrature, Q signals downconverted to a
center frequency of 200 kHz. The output uses pins I, I¯ (I inverted), Q and Q̄ (Q inverted) and
1.00
measurements indicates a DC offset of approximately 1.1 V.
0
50
100 150 200 250 300 350 400
A configurable image rejection pass band filter is available in the front-end. Figure 6.10 shows
FREQUENCY (MHz)
the filter response by different passband bandwidths. The Intermediate Frequency (IF) I and
EW
ALL N
Q output are not well documented in the ADF7020-1 datasheet. The pins®are referred to as
minicircu
”Signal Chain Test Pins” and described as ”High Impedance Output” [Analog Devices 05, p. 11].
Therefore a test is performed to evaluate
the I/Q
ISO 9001
ISOoutput
14001 possibilities
CERTIFIED and their relation to the
AGC
with
the
lower
and
upper
threshold
in
the
AGC
configured
−70 dBm specs
and −30
dBm. online see Mini-Circui
166, Brooklyn, New York 11235-0003 (718) 934-4500 Fax (718) 332-4661 For detailed to
performance
& shopping
The results are listed in table 6.1. It is possible to adjust the AGC to change the output voltage.
The Design Engineers Search Engine Provides ACTUAL Data Instantly From MINI-CIRCUITS At: www.minicircuits.com
Schematics for the frontend can be found in Appendix B.
RF/IF MICROWAVE COMPONENTS
Mini-Circuits
Input level [dBm]
-70
-80
-90
AGC setting
I/Q output peak-peak [V]
Automatic
Automatic
Automatic
60 mV
60 mV
60 mV
Table 6.1: Measuered I/Q output vs. AGC settings and input.
6.5.1
Configuration
The ADF7020-1 is configured by setting 13 registers through SPI. As the IC can be used for both
receiving (including hardware based demodulation) and transmitting, not all of these registers are
actually configured.
47
CHAPTER 6. IMPLEMENTATION
0
–5
200kHz FILTER BW
–10
ATTENUATION LEVEL (dB)
–15
–20
–25
–30
–35
–40
150kHz FILTER BW
–45
–50
–55
100kHz FILTER BW
–60
–70
–400 –300 –200 –100
0
100 200 300 400 500 600
–350 –250 –150 –50
50
150 250 350 450 550
IF FREQ (kHz)
05669-009
–65
Figure 9. IF Filter Response
Figure 6.10: ADF7020-1 intermediate filter [Analog Devices 05].
The most important part is to configure the receiver frequency. A 19.2 MHz crystal oscillator
is chosen for external oscillator, after which the appropriate properties is configured as follows in
Equation (6.3). Note that the frequency of the Phase-Locked Loop (PLL) must be 200 kHz lower
than 162 MHz to get the signal centered at 200 kHz. The frequency is calculated to be the twice
the desired frequency (= 323.6 MHz), and then halved by using the VCO divide by two property.
XT AL
NFractional
FPLL =
· NInteger +
[MHz]
(6.3)
R
215
23211
19, 2 · 106
· 33 + 15
=
= 323.6 MHz
2
2
The filter bandwidth of the front-end is configured based on the maximum bandwidth of the
signals being 25 kHz with a deviation of 50 kHz. When a Doppler shift and oscillator frequency
drift of 2 times 5 kHz is added, the maximum bandwidth needed is 85 kHz. Therefore, a filter
bandwidth of 100 kHz with a center bandwidth of 200 kHz is used.
6.6
Analog to Digital Converter
¯ Q
The Analog to Digital Converter (ADC) is used to convert the downconverted signals I, I,
and Q̄ to a serial digital signal that is readable from the DSP. Due to the Nyquist theorem, the
sample rate should be at least twice the highest frequency component of the input signal. The
RF front-end outputs signals centered at 200 kHz so an ADC with a maximum sample rate of 1
million samples per second is used.
The Analog Devices AD7262 [Analog Devices 08] is a dual differential ADC, with an adjustable
sample rate of maximum 1 Msps. The ADC has a built-in amplifier, such that the signals with a
peak-peak amplitude of 60 mV can be amplified to get an optimum digital resolution. The ADC
expects that the input signals has a DC average of 2.5 V compared to 1.1 V that is the average
output of the front-end IC. To compensate from this, a change in the DC offset is created by four
48
6.7. DIGITAL SIGNAL PROCESSOR
high pass filters and a quad operational amplifier. The operational amplifier is controlled by a
reference voltage from the ADC. The design of the schematic can be found in Appendix B.
6.6.1
Interface and Configuration
As mentioned, the ADC is configured and used through the serial interface. The ADC contains one
12-bit control register, where the desired gain and an optional power-down mode is selected, and
an internal calibration routine is started. It is possible to read back the result of the calibration.
Measurements are carried out from the ADC by sending a continuous clock to it. It is possible for the ADC to send measurements on either one or two channels. It is obvious that the
requirements for the board layout is less stringent if the data is read over two channels.
6.7
Digital Signal Processor
This section describes the selection of implementation platform for the demodulator, for which
two DSPs from Texas Instruments and Analog Devices have been considered. Both DSPs provide
a high speed serial interface for data acquisition from the ADC but differ in a number of other
features. The DSPs are described in the following two sections.
6.7.1
Texas Instruments OMAP3530
The OMAP3530 from Texas Instruments is a 600 MHz ARM Cortex-A8 and a 430 MHz TI
TMS320C64x+ 16-bit fixed point DSP integrated in a single package. The OMAP supports up to
1 GB of DDR memory which can be soldered on using the Package-on-Package (PoP) technique,
where the memory chip is installed on top of the OMAP. The processor includes a high speed
Multi-channel Buffered Serial Port (McBSP) for data transfer from the ADC. The OMAP3530
does not support CAN, so an external controller is thus required for communication with the
other subsystems on the satellite.
A low-cost community designed OMAP3530 development board is available through the Beagleboard project [Beagleboard 09]. The Beagleboard hardware design is open and the boards ARM
processor is able to run the Ångström Linux distribution, which specifically targets embedded systems such as multimedia players and handhelds. Texas Instruments provide a dspbridge module
for the Linux kernel to interface with the TMS320C64x+, but a license to TI Code Composer
Studio is still required to compile code for the DSP. An open GNU toolchain, used for building the
Linux distribution, exists for the ARM Cortex-A8. A growing community have emerged around
the Beagleboard, but experience with development for the integrated DSP is limited, with only a
few code examples available.
6.7.2
Analog Devices Blackfin BF537
The Analog Devices ADSP-BF537 Blackfin is a 500 MHz single core 16-bit fixed point DSP with
a RISC-like instruction set. The DSP incorporates the Micro Signal Architecture designed as
a cooperation between Analog Devices and Intel. The BF537 supports maximally 512 MB of
SD-RAM memory and includes two high speed Serial Ports (SPORT) for data acquisition from
serial peripherals as well as a CAN 2.0B compliant CAN interface.
An open development board using the BF537 is available in the ADZS-BF537-STAMP board
from Analog Devices. The STAMP board is targeted to support the development of Linux on
the Blackfin Series DSPs. The uClinux distribution with the U-Boot boot loader and a complete
implementation of the GNU toolchain (gcc, ld, as etc.) is provided by the Blackfin Koop project
which is supported by Analog Devices [Blackfin Koop 09]. The Blackfin Koop website hosts a
well established community and comprehensive documentation with code examples for Linux on
the Blackfin architecture. Linux device drivers for the Blackfin peripherals, including CAN and
SPORT, are included in the uClinux distribution.
49
CHAPTER 6. IMPLEMENTATION
6.7.3
Score Chart
The score chart in Table 6.2 assess the features described in the previous sections. The OMAP3530’s dual processing unit architecture is superior when comparing computational power, but
increases the complexity of software development. An OMAP-based demodulator would thus require code for both the ARM Cortex-A8 and TMS320C64x+ which could introduce parallelization
issues and requires knowledge of two architectures. The need for the dspbridge kernel module is
a minor drawback as the module is still in development. Open design development board exists
for both processors which reduces the workload when designing hardware for the system. The
Package-on-Package technology used in the OMAP3530 allows easy placement of memory, whilst
the Blackfin requires memory devices placed on the PCB. The BF537 Blackfin’s open toolchain is
widely used and increases the reproducibility of the receiver, as an expensive IDE such as Code
Composer Studio, is not required. The Blackfin includes a CAN interface, which is required for
communication with the other subsystems in the satellite. An external CAN transceiver is required for the OMAP3530 to exchange data with the other subsystems. Finally, a large Blackfin
community and the lack of available documentation for Linux with the DSP in the OMAP3530 is
in favor for the BF537. The final selection is therefore to use Analog Devices ADSP-BF537 with
embedded uClinux.
TI OMAP3530
ADI BF537
Dual Core Processing Power
Dual Core Complexity
Linux + DSPBridge
Code Composer Studio
Open Design Beagleboard
PoP Memory
No CAN Controller
+
+
+
-
Single Core Processing Power
Single Core Complexity
Native Linux
Open Source Toolchain
Open Design ADZS-BF537-STAMP
Separate RAM ICs
Integrated CAN Controller
+
+
+
+
+
Total +’s
3
Total +’s
5
Table 6.2: DSP Score Chart. A + indicates advantages while - indicates disadvantages.
6.8
Analog Devices ADSP-BF537 Architecture
This section gives a more detailed description of the internal architecture of the ADSP-BF537 from
Analog Devices. Further information is available in the ADSP-BF537 datasheet [Analog Devices 09a]
and Hardware Reference [Analog Devices 09b]. Figure 6.11 shows a functional block diagram of
the Blackfin core and the main peripherals and data buses. The core contains two 16-bit MACs
(Multiply-Accumulate), two 40-bit ALUs (Arithmetic Logic Unit), two 40-bit accumulators and
a 40-bit barrel shifter. The two MAC units are both able to execute one 16-bit by 16-bit multiplication and accumulate the result in one of the 40-bit accumulator in a single clock cycle. The
40-bit ALUs can execute regular 16 or 32-bit arithmetic instructions, and includes special DSP instructions such as modulo 232 multiplication and saturation/rounding arithmetics useful for signal
processing. The barrel shifter is used for bit shifts and rotations. The hardware supports zerooverhead loop structures, which are useful for speeding up signal processing algorithms such as
correlations, FFTs and filters. The Blackfin processors use a modified Harvard architecture with
dedicated L1 memory blocks for data and instructions. Stack and local variables are stored in a
special L1 scrathpad memory. The Blackfins Memory Management Unit (MMU) does not support
virtual memory, but provides supervisor and user mode memory protection. The uClinux kernel
exploits this for separating user space applications from the kernel memory. Internal and external memory blocks, including peripheral I/O registers and Memory Mapped Registers (MMR)
are located in a common 4 GB address space, of which up to 512 MB is available for external
50
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
On-chip PLL capable of 0.5ⴛ to 64ⴛ frequency multiplication
Debug/JTAG interface
6.9. PCB SCHEMATICS AND LAYOUT
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
WATCHDOG TIMER
RTC
B
CAN
TWI
PORT J
SPORT0
L1
DATA
MEMORY
DMA
CONTROLLER
DMA CORE BUS
EXTERNAL ACCESS BUS
SPORT1
PPI
DMA
EXTERNAL
BUS
L1
INSTRUCTION
MEMORY
INTERRUPT
CONTROLLER
GPIO
PORT G
UART0-1
SPI
EXTERNAL PORT
FLASH, SDRAM CONTROL
GPIO
PORT F
TIMER7-0
ETHERNET MAC
(See Table 1)
16
GPIO
PORT H
BOOT ROM
Figure 1. Functional Block Diagram
Figure 6.11: ADSP-BF537 Blackfin architecture [Analog Devices 09a].
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. G
SDRAM. Two full duplex synchronous serial ports (SPORT0 and SPORT1) are included in the
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
CAN
or otherwise under any patent or patent rights of Analog
Devices. Trademarks
and
Satellite
registered trademarks are the property of their respective
owners.
Subsystems
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
SPI
ADF7020-1
Fax: 781.461.3113 (RF Frontend)
©2009 Analog Devices, Inc. All rights reserved.
SPORT
AD7262
(ADC)
Figure 6.12: Peripheral connections for the ADSP-BF537 AIS receiver.
ADSP-BF537 architecture for high speed transfers. The SPORTs implements bidirectional transfers with support for Direct Memory Access (DMA), allowing data acquisition without blocking
the processing unit for the transmission time. Figure 6.12 shows how the peripherals are used in
the AIS receiver design. Sampled data from the ADF7020-1 in-phase and quadrature outputs is
transferred from the AD7262 ADC using the SPORT. The ADF7020-1 is configured using Serial
Peripheral Interface (SPI) bus. Communication with the satellite subsystems uses the built-in
CAN controller.
6.9
PCB Schematics and Layout
To test the front-end of the software defined AIS receiver, a PCB is designed. This includes all of
the hardware between the LNA and DSP. The desired features of the PCB is:
• LNA connector (RF input)
• Saw filter and power splitter
• Down converter and IF filter
• Analog to Digital converter
51
CHAPTER 6. IMPLEMENTATION
• Connector to DSP interface
• Data storage
• AAUSAT3 mech. outline and stack connector.
The circuit and layout is inspired by the application notes for the ADC[Analog Devices 08, p. 30]
and the ADF7020-1 development board[Analog Devices 07b]. To follow some of the basic EMC
rules[Armstrong 07], the PCB is designed using a standard 4 layered FR4 print type. The two
inner layers are used for uncorrupted Vcc and GN D plane, and the top and button layers are
used for signalling. The PCB has been produced by Elprint A/S, via the normal AAU discount
procedure. Figure 6.13 shows the layers of the PCB.
Figure 6.13: PCB Layer stackup.
Figure 6.14 shows a photo of the final PCB. The board outline is as defined in the AAUSAT3
standard with shape, holes and stack connector matched to the standard. On the top right is the
interface for the DSP development board, connecting the microSD card and the ADC to the DSP
(just beneath the DSP connector). The stack connector is placed in the button left corner, and
supplies the board with power and CAN communication. The CAN transceiver is placed in the
left side. The right side of the PCB is the HF part, with SMA connector for RF input. The HF
filtering (SAW filter, power splitter and the possibility to add extra π- or T -filter) is placed in
a square, prepared for EMC shielding. In the middle of the board is the downconverter and IF
filter (ADF7020-1), with the debug and test connector just left of it. The differential I/Q signal
from the AFD7020-1 is offset adjusted and connected to the ADC input.
The full schematics and PCB layout is shown in section B on page 65, followed by the component
list.
6.10
Experiment Setup
The two AIS receivers and a prototype of AAUSAT3 will be included on the BEXUS flight in October 2009. The balloon will pass through the Earths atmosphere to an altitude of approximately
35 km and experience temperatures from 20 ◦ C to less than -80 ◦ C. Figure 6.15 plots the expected
ambient temperature as a function of the balloon altitude. Consequently, the experiment must
be able to operate in this temperature range. This section explains the mechanical structure and
thermal considerations for the experiment.
6.10.1
Mechanical Structure
The experiment subsystems will be mounted in a modified AAUSAT-II frame, with the frame
height extended to 16 cm to accommodate six batteries. The experiment will not have solar panels,
so extra batteries are needed to have sufficient power for 6 hours of operation and for heating the
experiment. The entire frame will be fitted inside an insulated box for mounting on the balloon
gondola to ensure a reliable temperature for the essential parts of the experiment. The outer
box is constructed of SE20-3 aluminum corners from System Standex [System Standex A/S 09]
and 20x20 mm aluminum profile with 2mm walls. The total weight of the outer box is 2986 g.
52
6.10. EXPERIMENT SETUP
Figure 6.14: Photo of front end PCB Rev 1.0.
Figure 6.15: Expected temperature for the experiment[SSC 09].
53
CHAPTER 6. IMPLEMENTATION
Figure 6.16 shows the outer box with insulation and the extended frame. The final experiment
box will be fitted with aluminum sides to keep the experiment and insulation foam in place. One
side of the box will contain connectors for VHF and UHF antennas and the umbilical cable used
for charging and external access to the CAN bus.
The PCBs are designed in accordance with the AAUSAT3 PCB layout standard illustrated in
Figure 6.17.
Figure 6.16: Insulated experiment box and frame.
Number of
Description
8
4
8
4
2
Corner
220 mm
160 mm
260x200
200x200
tube
tube
mm Side shield
mm End shield
Weight[g]
Total Weight [g]
74
86
63
281
216
592
344
504
1124
432
Total
2986
Table 6.3: Mass budget for the experiment box.
54
6.10. EXPERIMENT SETUP
21
87
5
87
11
7
6x45~
4
1
Ø
11
15
18
Figure 6.17: AAUSAT3 PCB standard.
Tegnet af:
6.10.2
Thermal Considerations
Tegningsnr.:
Antal:
Materiale:
DMS9 Gr. 69B
Komponent:
Aalborg Universitet
EPS-PCB
Institut
Maskinteknik
As seen in the section 6.10.1, the outer frame of the experiment makes room
forfor
5 cm
of insulation
Pontoppidanstræde
101 Første vinkel:
material. A type of foam normally used to line flight cases is used, since
it has the mechanical
9220 Aalborg
strength such that the Cubesat frame does not need special mountings to the outer frame that
normally will result in a thermal bridge.
To ensure that the batteries will supply as expected, it is desired to calculate the power usage
necessary for keeping an internal experiment temperature of minimum 0 ◦ C. In Figure 6.15 the
measured temperature from another BEXUS experiment is shown. The mechanics are designed
for a insulation thickness, x, of 5 cm. The radiated power is calculated using the law of thermal
conduction[Serway 04, p. 624]:
P = kA
∆T
x
(6.4)
Where the surface area of the Cubesat frame is give by:
A = 4 · 0.016 m2 + 2 · 0.01 m2 = 0.084 m2
Experiments have shown that the foam has an insulating effect such that 2.7 W dissipated inside
55
CHAPTER 6. IMPLEMENTATION
Usage
Component
Speed
Precision
RF downconverter
DSP clock
IQD FREQUENCY PRODUCTS - LF TVXO018792
EPSON MA-505 M-co
19.2 MHz
25.0 MHz
±3 ppm
±50 ppm
Table 6.4: Precision of the oscillators.
the box raises the temperature by 28 ◦ C. By this, formula (6.4) can be rewritten, such that the
temperature deviation depends only at the dissipated power times a constant. The constant is
defined as:
K=
2.7 W
mW
P
=
= 96.4
∆T
28 K
K
The necessary power to secure an internal temperature of approximately 0 ◦ C, when the lowest
expected temperature is −80 ◦ C will be:
K · (0 ◦ C − −80 ◦ C) = 7.7 W
(6.5)
This heat will be generated by the subsystems themselves and with power resistors placed around
the batteries. The resistors will be actively controlled based on the inside temperature of the experiment. Experiences from AAUSAT-II has shown that the inner heat transport will be sufficient
to keep all subsystems within their designed range.
6.10.3
Clock Drift
With the expected internal experiment temperature and the chosen components for the design, is
it now possible to calculate the worst case clock drift. Due to table 6.4 the worst possible clock
drift will be 53 ppm. On basis of this, frequency drift at 162 MHz will be as follows:
Dclk = 162 · 106 ·
53
= 8.6 kHz
106
(6.6)
Added to the calculated Doppler shift of up to ±4 kHz (see section 2.1.3) the total worst case
frequency drift will be 12 kHz. This can be minimized by choosing another oscillator for the DSP.
It is possible to get temperature compensated oscillators which fits to the DSP with a frequency
drift of less than 50 ppm. This will bring down the total worst case frequency deviation including
Doppler shift to ±5.3 kHz which will be sufficient for the algorithms.
56
Chapter 7
Acceptance Test
1. Be able to sample raw data which contains both AIS channels with a sufficient sample rate
to satisfy the Nyquist sample theorem.
The front end and ADC setup is investigated, and it is verified whether the sample rate
is sufficient. As the DSP and SPORT interface for the ADC has not been implemented,
this have not been tested although the setup is prepared for sampling with 1 Msamples per
second. The I/Q signal from the front end (ADF7020-1) is sampled with a PC, and it is
verified that the IF frequency is centered around 200 kHz and with its highest frequency
component under 300 kHz. Therefore it is concluded that the selected setup is sufficient.
2. Demodulate GMSK in software.
An antenna is connected to the system, and the software demodulator is tested. It is shown
in Chapter 5 that the software demodulator is working on real data in MATLAB, using
ADF7021 for downconversion and thereby receiving only one AIS channel. At the same
time it is shown through simulation that the algorithms will work, using ADF7020 and
demodulating both AIS channels at the same time.
3. Be able to update all parts of the demodulating and decoding software remotely.
A changed version of the demodulating and decoding software is written and uploaded to
the subsystem, after which it is tested whether the changes takes effect. As the software on
the DSP has not been implemented yet, it is not possible to test this requirement.
4. Be able to compensate for frequency drift, including Doppler shift when the satellite is moving
with 7.5 km/s.
An artificial signal with a worst case frequency drift in both directions is generated using
the GMSK simulator, and it is observed whether the signal is demodulated correctly. Only
the Doppler shift has been simulated and tested. However the algorithm has proven usable,
and the up to 200 kHz IF bandwidth is be enough to compensate for clock drift also.
5. Be able to store raw sampled data for 3600 sec (1 hr).
The receiver is admitted to run until the memory limit is reached, and the amount of raw
data is observed. The DSP and SPORT interface is not implemented, so the test is not
executed. However, the SD storage should prove sufficient.
6. Be functional from -40 - +85◦ C.
The receiver is tested for worst case temperatures, and in the vacuum chamber. Only the
DSP development board and SD card storage has been tested in climate chamber. No
problem were encountered.
7. Have a weight of maximally 150 g.
The weight of the experiment setup is measured. The current running setup uses a PC for
57
CHAPTER 7. ACCEPTANCE TEST
signal processing. Therefore, the weight limit is exceeded. However, the front end and DSP
should be able to fit one PCB and comply with the weight requirement. The weight of the
PCB developed through this project is 43 g.
8. Be operating for at least 6 months.
As the final system is not implemented, the final burn-in test is not executed.
9. Comply with the standards defined by the AAUSAT3 system engineering group.
a) Be able to run at 3.3 V and/or 5 V only.
The required input voltages to the system is observed. 3.3 V and 5 V is needed.
b) Use no more power than 1 W.
The power consumption is measured with the system running fully operational. The
estimated total power usage is around 1 W, depending on the needed DSP clock speed.
Again, the missing final implementation means that this can not be fully tested.
c) Comply with the PCB layout for AAUSAT3 including definition of stack connector and
board outline.
The size of the PCB is measured and the electric interface is tested. The PCB is
87 x 87 mm, and fits inside the produced frame. The final electrical interface has not
been tested as the AIS2 PCB is the first PCB developed by AAUSAT3 standards.
d) Have at least one temperature sensor placed on a central part of the PCB.
Tested by observing and measuring using the on board sensor. The PCB layout is
prepared for the temperature sensor, but the sensor has not been tested as the platform
system that must interface to the temperature sensor has not yet been developed.
e) Be able to be controlled completely over CSP.
Commands is sent to the subsystem, and it is checked whether the correct messages is
returned. CAN and CSP are not yet implemented.
f) Send telemetry to the LOG subsystem.
It is observed whether the relevant telemetry data is logged. As the DSP is not implemented, this is not yet tested.
58
Chapter 8
Conclusion
The purpose of this project is to develop a software defined AIS receiver for the AAUSAT3
student satellite. The satellites mission objective is to evaluate the possibility to receive AIS
signals in space. Previous scientific work by groups from Aalborg University and ESA indicates
that uncollided messages with sufficient signal strength should be available in space. A satellite
based AIS receiver will be able to cover a large area on ground, and enables the Danish Maritime
Safety Administration to monitor vessels in the remote seas around Greenland.
A software defined receiver is desirable in space, as it allows for reconfigurations and optimizations of the algorithms after the satellite has been launched.
The AIS receiver and a prototype of AAUSAT3 will be tested on the BEXUS high-altitude
balloon flight in October 2009. The BEXUS program allows European students to test scientific
experiments in altitudes of up to 35 km and in temperatures below -80 ◦ C. On the BEXUS balloon,
the AIS receiver should be able to receive messages from most of the Baltic sea and parts of the
Norwegian coasts.
The report begins with an analysis of the AIS standard with special focus on the physical and
data link layers of the protocol. AIS uses a GMSK modulation scheme with NRZI encoded data
and HDLC framing, so the receiver must be developed to support this standard. The signals are
transmitted on two maritime VHF channels, with frequencies around 162 MHz. AIS transponders
multiplex their transmission between the two channels, so the receiver must be able to cover
signals at both frequencies. Furthermore, Doppler shift and oscillator drifts introduces frequency
deviations that must also be taken into account. The analysis is used as a foundation for the
requirement specification in Section 3.1.
The design chapter focus on the development of the receiver algorithms. A non-coherent
correlator demodulator with support for packet detection and frequency estimation is designed
and implemented in MATLAB. To verify the demodulator, algorithms are developed to generate
realistic test data. A commercial radio front-end is chosen to downconvert the received signals
to a frequency suitable for sampling with an ADC. The modulator is designed to simulate the
sampled output of this front-end. A random bit stream is encapsulated in an HDLC frame and
then NRZI encoded and GMSK modulated. Gaussian noise with an adjustable signal-to-noise
ratio can be added to the signal, to simulate the transmission through a real channel.
The quality of the demodulator has been tested using this simulation setup. The required
signal-to-noise ratio to achieve a Bit Error Rate of 10−3 is found to be approximately 8 dB
above the theoretical value possible with a non-coherent GMSK demodulator. The demodulation
algorithms could be optimized by using a quadrature demodulator and implementing soft decision.
Adaptive bit synchronization could be implemented to minimize the effect of small drifts in the
bit timing.
The developed receiver algorithms have also been tested with real-life AIS signals. A setup
using a National Instruments sample card and a standard PC was installed on the roof of the
university. Using a VHF antenna and a Low Noise Amplifier, data sets of 25 s was sampled and
59
CHAPTER 8. CONCLUSION
processed with the MATLAB algorithms. Bit synchronization was achieved, and several packets
were received and demodulated successfully.
For both the BEXUS flight and the final satellite, the receiver algorithms must be ported
to a DSP. A DSP from Analog Devices is found to be suitable for the system. The current
implementation includes a prototype PCB with a COTS radio front-end and an Analog to Digital
Converter. The front-ends intermediate frequency output is sampled for processing in DSP. A
connector is included for connection to the DSP development board.
Finally, the acceptance test shows that the implemented algorithms are suitable for receiving
and decoding AIS signals. However, several requirement tests could not be passed, so additional work is needed. The deadline for the experiment delivery to the BEXUS flight is in early
September, so the summer holiday will be used for further implementation and preparation for
the BEXUS flight.
8.1
Further Work
This section lists the remaining tasks for preparing the software defined AIS receiver for the
BEXUS flight.
The main task is to prepare the DSP for using the high-speed serial port for data acquisition
from the ADC. A successfully sampled set of raw data from high altitude will be valuable for
post-flight development of the demodulation algorithms. The BEXUS flight allows the sampling
of data from varying altitudes, useful for evaluation of the SNR and collisions.
The current prototype PCB contains the radio front-end, the ADC and data storage for the
DSP. The final flight model must furthermore include the DSP itself and necessary peripherals
such as memory and oscillators.
Finally, the receiver algorithms must be ported and optimized for the DSP architecture, to
allow real-time decoding. The AIS receiver must conform to the AAUSAT3 internal communication structure and implement the message protocols used for inter-subsystem communication in
the satellite. It is desirable that the receiver is able to analyze the quality of the received data,
to minimize down link bandwidth requirements.
60
Appendix A
Interface Control Documents
PRELIMINARY VERSION - TO BE CONFIRMED!
Be aware that this is a preliminary version. Arguments and return values are a work in progress.
The ICD is primarily included to provide a functional overview of the AIS subsystem. In the
NAVIS project, the software defined AIS receiver is referred to as AIS2.
The Interface Control Document (ICD) defines the interface and functionality provided by the
subsystems. The AIS2 subsystem has two main states: Manual Mode or Automatic Mode. This
is illustrated in Figure A.1.
Figure A.1: AIS2 Main States
Comment:
Abort Current Operation
Abort the current operation and return to Manual Mode
AIS2 ABORT
None
AIS2 OK on success. If any issues arise, the system should still
return to Manual Mode but return AIS2 WARNING
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Get Current System State
Get System State: Mode, Memory Usage, Temperature, etc.
AIS2 ABORT
None
System State Data on success, AIS2 FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
61
APPENDIX A. INTERFACE CONTROL DOCUMENTS
Response:
Comment:
Enable Automatic Mode
Set the AIS2 subsystem in Automatic Mode
AIS2 MODE AUTO(SUB MODE)
SUB MODE (
AIS2 MODE AUTO SAMPLE
AIS2 MODE AUTO PTRACK
AIS2 MODE AUTO FREQEST
AIS2 MODE AUTO DEMOD
AIS2 MODE AUTO BITSYNC
AIS2 MODE AUTO DECODE
)
Selected mode on succes, AIS2 FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Enable Manual Mode
Set the AIS2 subsystem in Manual Mode
AIS2 MODE MANUAL
None
AIS2 OK on success, AIS2 FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Sample Data
Sample Data
AIS2 SAMPLE
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Track Packets
Track packets in the sampled data
AIS2 PTRACK
None
Number of packets found in data
Preliminary Version! Low resolution FFT
Purpose:
Command:
Arguments:
Response:
Comment:
Center Frequency Estimation
Estimate the center frequency of packets in the sampled data
AIS2 FREQEST
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version! High resolution FFT
Purpose:
Command:
Arguments:
Response:
Comment:
Demodulate Data
Demodulate packets in the sampled data
AIS2 DEMOD
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Bit Synchronization
Perform bit synchronization on the demodulated data
AIS2 BITSYNC
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
62
Purpose:
Command:
Arguments:
Response:
Comment:
Decode AIS packets
Decode AIS packets in demodulated data
AIS2 BITSYNC
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Command:
Arguments:
Response:
Comment:
Received Packets Stats
Return stats on received packets: Number of packets, Passed/Failed
CRC, Package type distribution
AIS2 RECEIVER STATS
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
List Received Packets Headers
List received packets headers
AIS2 LIST PACKETS
None
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Get Specific Packet Content
Get specific packet content
AIS2 GET PACKET
Package number
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Set Algorithm Parameters
Set Algorithm Parameter
AIS2 ALGORITHM PARAM
Sample length, Store Failed CRC packets, Log settings, etc
AIS2 MODE OK on success, AIS2 MODE FAIL on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Run Test Case
Run Test Case
AIS2 TEST
Test case number
AIS2 TEST PASSED on success, AIS2 TEST FAILED on failure
Preliminary Version!
Purpose:
Command:
Arguments:
Response:
Comment:
Power-On Self-Test (POST)
Run Power-on Self Test
AIS2 POST
None
AIS2 TEST PASSED on success, AIS2 TEST FAILED on failure
Preliminary Version!
Purpose:
63
Appendix B
Hardware diagrams
The following two pages contain hardware diagrams and PCB layout for the software defined
AIS receiver. The files are included on the attached CD, including the hw 651.PrjPcb Altium
Designer project file.
65
1
2
3
4
5
6
7
8
VCC
10uF
0r
1
IN
SMB
C18
C17
C16
33nF
270pF
C9
100nF
L1
AGND
25
SDATA 26
VCC
P4
Pad_mount
H2
Pad_mount
H3
1
Pad_mount
H4
SCLK
SREAD
28
AGND
29
5.1pF 100nF
C26
C25
CREG2
AGND
Header 7X2
VCC
ADC_IP 30
32
INT/LOCK 33
5.1pF 100nF
C27
C28
Data_I/O
34
Data_CLK 35
CANL
CREG3
CANH
VCC
U10
3
5
2
B
RxD_can
TxD_can
4
1
GND
VCC
Vref
GND
8
Rs
C20
5.1pF
100nF
37
XTAL2
38
XTAL1
39
VCC
R10
0r
AGND
40
C21
C22
5.1pF
100nF
CREG3
41
CPOUT
42
43
CANH
6
CANL
7
CANH
44
45
L3
SN65HVD230QDQ1
VCC
XTAL1
1
Header 5X2
GND
GND OUT
GND VDD
RxD_can
TxD_can
2
4
6
8
10
180r
47
RLNA
SWD
VDD4
GND4
MUXOUT
MIX_I
OSC2
MIX_I
OSC1
MIX_Q
VDD3
MIX_Q
CREG3
FILT_I
CPOUT
FILT_I
L2
FILT_Q
GND
FILT_Q
ADF7021
AGND
AGND
AGND
8
R2
9
1.1K
12
C6
C7
13
5.1pF
100nF
15
AGND
17
FILT_I
FILT_I
18
FILT_I
FILT_I
19
AGND
AGND
20
FILT_Q
FILT_Q
21
FILT_Q
FILT_Q
SS9
SDA
CANL
SS0
GND
SS1
SS2
SS3
SS4
GND
SCL
CANH
SS5
GND
SS6
SS7
SS8
GND
4
24
CE
CE
AGND
AVCC
A1
GND
A2
VA-
R11 10K
VA+
R12 10K
AVCC
U9
VREFA
1
2
3
4
OUTA
-INA
+INA
GND
VCC
OUTB
-INB
+INB
8
7
6
5
VB+
R14 10K
VB-
C65
100nF
AGND
AGND
C57
100nF
VCC_5
AVCC
AGND
SS6
C56
100nF
VCC
AVCC
AGND
GND
AGND
VA100nF VA+
C54
100nF
FILT_I
FILT_I
VB+
VB-
100nF
AGND
C53
C
U2
AD7262
CA_CB_VCC
AVCC
VAVA+
AGND
AGND
AVCC
AGND
VB+
VBAVCC
CC_CD_VCC
CAL
CS
SCLK
AVCC
DOUTA
DOUTB
COUTA
COUTB
DGND
VDRIVE
COUTC
COUTD
CC+
CCCD+
CDCC_CD_GND
VREFB
AGND
AVCC
PD2
PD1
PD0/DIN
REFSEL
1
2
3
4
5
6
7
8
9
10
11
12
C55
FILT_Q
FILT_Q
C58
1µF
RFSx
RSCLKx
GND
AVCC
DRxPRI
DRxSEC
VCC
C64
100nF
U100
A1
A2
AGND
C63
100nF
A3
A4
A5
13
14
15
16
17
18
19
20
21
22
23
24
AVCC
36
35
34
33
32
31
30
29
28
27
26
25
VCC
GND
8
VCC_5
V_UNREG
RSCLKx
C60
100nF
VREFB
C59
100nF
Loop back clock
TXSCLKx
A6
A7
DTxPRI
VDDEXT
PH11
PH12
PH13
PH14
PH15
CLKBUF
7
AGND
P2
6
1
3
5
7
9
11
13
15
17
CS
19
21
23
25
MMC_Enable
27
29
31
33
5
VCC
Reset
RFSx
GND
GND
D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
C61
1µF
AGND
BF537
VCC
TXSCLKx
DRxPRI
DRxSEC
DTxPRI
RSCLKx
MOSI
MISO
SPCK
SPORT_Blackfin
AGND
R28
100k
J1
R24
100k
1
DAT2
2
CD/DAT3
AGND
R25
100k
CLK
7
DAT0
R22
R27
100k
R29
100k
D
SPCK
100r
MISO
R23
VCC
AGND
100r
8
DAT1
MOSI
100r
5
6
VSS
C62
100nF
100r
R21
R26
100k
4
VDD
CS
R20
3
CMD
AVCC
R30
0r Only one resistor inserted!
MMC_Enable
Micro_sd_socket
Title
GND
Size
GND
Number
A2
Date:
File:
GND
2
AAUSAT3 NAVIS:
AIS2 Saftware AIS receiver frontend
R31
0r
1
VREFB
R13 10K
AVCC
SS0
O.S.
I/Q
23
TEST_A
AVCC
DS75LVU+
GND
B
22
AGND
U8
3
1
2
3
4
5
100nF
Temp. sensor. One for each of the folowing:
- Battery 1
- Battery 2
- CPU
- Radio
(TBD: different adress)
O.S.
2
5
P3
C52
A0
H
H
AGND
16
AGND
SS0
AGND
AGND
C51
100nF
VDD
5
3.6K
AGND
GND
P0
SCL
100nF
AGND
14
AGND
SDA
C5
5.1pF
AD8607
Production_no
2
7
C3
C4
R3
100nF
1
AGND
10
11
AVCC
C50
100nF AVCC
SCL
AGND
VCC
100nF
GND
C0
100nF
L2
Inductor
7
SS3
SDA
C34
CREG1
22nF
SubSystem power-pin assignment (BEXUS-08) :
GND
RF1
Inductor
C35
C14
2
4
6
8
10
12
14
16
18
SS9
SDA
CANL
SS0
GND
SS1
SS2
SS3
SS4
5
6
GND4
CVCO
L6
Inductor
C13
1
SCL
3
CANH 5
SS5
7
9
SS6
11
SS7
13
SS8
15
17
C
P12
SMB
AGND
L5
AGND
P1
STACK
SS0 = I2C_3.3V (Vcc I2C bus for temp. sensor.)
SS1 = AIS1_3.3V
SS2 = ELA_3.3V
SS3 = AIS2_3.3V
SS4 =
SS5 =
SS6 = AIS2_5V
SS7 =
SS8 =
SS9 =
RF2
AGND
C1
C36
GND4
C15
Stack connector:
CAN = comunication bus between subsystems.
I2C = Internal sensor bus.
SS = Power supply for each subsystem from EPS.
AGND
3
4
A
C2
C12
5.1pF
AGND
RSET
CLKOUT
CREG1
3
CREG4
GND1
48
Y1
Oscillator
50MHz
RFINB
VDD2
L1
?nH
U4
ADP-2-1
PORT1
PORT2
4
RFIN
CREG2
C11
100nF
AGND
2
2
1
3
5
7
9
46
3
4
P5
R6
RFGND
VDD
GND
CANL
R
D
CAN_sleep
C19
MUX
GND2
TxRxCLK
XCLKOUT 36
AGND
R9
120r
Optional
Terminering for CAN
RFOUT
TxRxDATA
GND
1
VDD1
SCLK
ADCIN
31
1
Pad_mount
CREG1
VREFA
1
XCLKOUT
Data_I/O
ADC_IP
SREAD
SLE
CE
VCOIN
SDATA
48
47
46
45
44
43
42
41
40
39
38
37
1
SREAD 27
1
2
3
4
5
6
7
8
9 10
11 12
13 14
Data_CLK
INT/LOCK
SCLK
SDATA
MUX
1
SLE
CA+
CACB+
CBCA_CB_GND
VREFA
AGND
AVCC
G0
G1
G2
G3
1
SUM
49
1
RF_SAW 1
AGND
AGND
SLE
H1
AGND
6
5.1pF
VCC
U6
1
C10
2
1.5nF
A
U1
SAW
OUT
Ground
RF_IN
6
P6
GND GND
R1
10
910r
GND GND
180r
4
C33
100nF
GND GND
10uF
C32
100nF
GND GND
C31
100nF
C8
3
C30
R4
9
VCC
R5
8
AGND
CPOUT
3
4
5
6
7
17/05/2009
C:\aausat3\..\651_hw.SchDoc
Revision
1.0
Sheet 1 of 1
Drawn By: 09gr651
8
Appendix C
Component List
Here the component list is shown. To read the actual value of the component, please refer to the
Altium Designer files on the CD.
69
APPENDIX C. COMPONENT LIST
Quantity
Designator
Description
Comment
Footprint
3
47
C0, C8, C30
C1, C2, C3, C4, C5, C6,
C7, C9, C10, C11, C12,
C13, C14, C15, C16, C17,
C18, C19, C20, C21, C22,
C25, C26, C27, C28, C31,
C32, C33, C34, C35, C36,
C50, C51, C52, C53, C54,
C55, C56, C57, C58, C59,
C60, C61, C62, C63, C64,
C65
H1, H2, H3, H4
J1
L1, L2, L3, L5, L6
P0
P1
P2
P3
P4
P5
P6, P12
R1, R2, R3, R4, R5, R6,
R10, R11, R12, R13, R14,
R20, R21, R22, R23, R24,
R25, R26, R27, R28, R29,
R30, R31
R9
U1
U2
U4
U6
U8
U9
U10
Y1
Capacitor
Capacitor
Cap Semi
Cap Semi
C1206
1608[0603]
AAUSAT3 mounting pad
Micro sd socket
Inductor
Production no
Stack connector - AAUSAT3
Header, 17-Pin, Dual row
Header, 5-Pin
Header, 7-Pin, Dual row
Header, 5-Pin, Dual row
SMB Straight Connector
Semiconductor Resistor
Pad mount
micro-SD-conn
Inductor
Production no
STACK
SPORT Blackfin
I/Q
Header 7X2
Header 5X2
SMB
Res Semi
MountM3
Semiconductor Resistor
SAW - 162 MHz - SIPATSAW
ADC. 1 MSPS, 12-Bitg
2 way power splitter
ADF7021 transceiver
DS75LVU+
AD8607
CAN Bus Transceiver
Fox CMOS cheramic oscillator
Optional
SAW
AD7262
ADP-2-1
ADF7021
uSOP8
SOIC8
SN65HVD230
Oscillator
4
1
5
1
1
1
1
1
1
2
23
1
1
1
1
1
1
1
1
1
70
2012 Chip
STACK
HDR2X17
MHDR1X5
HDR2X7
HDR2X5
SMB V-RJ45
1608[0603]
1608[0603]
SAW
LQFP48
ADP-2-1
CP-48-3
CAN
TXO83
Appendix D
Work agreement (Danish)
The following page shows the work agreement approval (Godkendelse for projektsamarbejde). In
connection to this document is the 3 page description of the project and cooperation, that the
study board granted the approval based on (AIS modtager til ESA BEXUS ballon flyvning).
71
AIS modtager til
ESA BEXUS ballon flyvning
1. Baggrund og motivation
Farvandsvæsnet i Danmark har til opgave at administrere trafikken i de danske farvande og derved
sørge for skibssikkerheden til vands. Dette gøres i dag med bøjer samt trafikseparation. De er godt
undervejs i de danske farvande men i de grønlandske farvande, som også er Farvandsvæsnets
ansvarsområde, er overvågningen af skibe mangelfuld. Derfor ønsker Farvandsvæsnet at overvåge
disse skibe vha. det Automatiske IdentifikationsSystem (AIS), som det allerede foregår i de danske
farvande.
AIS systemet
AIS er et civilt automatisk identifikationssystem, der gør det muligt at udveksle oplysninger mellem
skibe indbyrdes og mellem skibe og landstationer. AIS er obligatorisk for alle skibe over 300
bruttotons samt alle kommercielle skibe. Oplysningerne omfatter identifikation, navigation (for
eksempel position, kurs og fart) og rejserelaterede data (for eksempel destination og dybgang).
I Danmark modtages skibenes AIS signaler af 15 jordstationer, men denne metode er upraktisk ved
Grønland da stationerne ikke kan modtage signaler udover line of sight. Målet med AAUSAT 3
projektet er derfor at evaluere muligheden for at modtage AIS signaler fra skibe i de Grønlandske
farvande via satellit med henblik på senere udvikling af operative AIS satellitter.
Projektmål
Formålet med dette projekt er at udvikle udstyr til modtagelse af AIS signaler på ESA's BEXUS
ballonopsendelse, med henblik på evaluering af muligheden for at modtage AIS signaler i rummet
og dermed udvikling af en AIS modtager til AAUSAT3. Projektet vil bygge på allerede udførte
studier af de teoretiske muligheder for AIS modtagelse i rummet.
ESA BEXUS – eksperimentel ballonflyvning
BEXUS står for "Balloon-borne Experiments for University Students", og er et tilbud fra en
sammenslutning af følgende organisationer:
- ESA (The European Space Agency)
- SNSB (Swedish National Space Board)
- SSC (Swedish Space Corporation)
- DLR (Deutschen Zentrum für Luft- und Raumfahrt)
Projektets formål er at give universitetsstuderende mulighed for at udføre forsøg under en
ballonflyvning. Flyvningen finder sted i oktober 2009 fra Kiruna i nordsverige, og vil typisk vare 5
timer og nå en højde på 35 km. Under flyvningen er formålet med AIS-eksperimentet, at afprøve to
forskellige prototyper af AIS-modtagere i realistiske omgivelser, inden det endelige design til
AAUSAT3 fastlægges.
AIS eksperimentet er pr. 10. februar blevet udvalgt af ESA til flyvningen i oktober 2009.
1
2. Projektbeskrivelser
Gruppe 650
Projektet vil tage udgangspunkt i udviklingen af et system til modtagelse af AIS data pakker fra
skibe, eventuelt analysere disse, og sende disse videre til senere behandling. Systemet vil blive
monteret på en ballon der opsendes til ca. 35km højde i samarbejde med ESA. Systemet vil bestå
af en COTS radiomodtager, samt en mikrokontroller til dekodning af AIS signalerne. Dette signal vil
blive analyseret og behandlet, således det kan bruges til sammenligning med referencesignaler fra
de jordbaserede AIS modtagestationer.
Projektet omfatter således følgende:
Analyse af AIS standarden*
Analyse af GMSK modulationstypen*
Link budget for modtagelse af AIS signaler fra BEXUS ballonen*
Implementering af COTS** radiomodtager
Udvikling og implementering dekoder til AIS protokollen
Målet med projektet er således at have en fungerende AIS modtager prototype.
**COTS: Commercial Of The Shelf
Gruppe 651
Projektet vil tage udgangspunkt i udviklingen af et system til modtagelse af AIS datapakker fra
skibe. Systemet skal implementeres i en digital radiomodtager. Modtageren vil blive monteret på
en ballon der opsendes til ca. 35 km højde i samarbejde med ESA.
Projektet omfatter således følgende:
Analyse af AIS standarden*
Analyse af GMSK modulationstypen*
Link budget for modtagelse af AIS signaler fra BEXUS ballonen*
Implementering af softwarebaseret modtager/demodulator + RF frontend
2
3. Samarbejde mellem projektgrupper
To projektgrupper vil forestå udviklingen af hver deres AIS modtager, til montering på BEXUS
ballonen. Således vil den ene gruppe fokusere på en COTS RF modtager og demodulator mens den
anden gruppe vil fokusere på en softwarebaseret modtager. Dette indbefatter en ADC og en DSP,
samt de tilhørende algoritmer og implementering.
Grundet projektets omfang vil det være nødvendigt for de to grupper at samarbejde om flere af
emnerne i projekterne. Dette falder naturligt, da begge grupper arbejder på at løse samme
problem, på to forskellige måder. Målet med samarbejdet er at nå længere, end hvis hver gruppe
arbejdede isoleret.
De emner der samarbejdes om, er følgende:
- Indledning til AAUSAT3-projektet
- Analyse af AIS standarden
- Beskrivelse af BEXUS projektet
- Linkbudget for modtagelse af AIS signaler fra BEXUS ballonen
De to gruppers rapporter bliver individuelle, hvad angår design, implementering, test og
konklusion (alt teknisk indhold), mens introduktioner og analyser vil være fælles beskrevet.
Det vil af rapporterne fremgå hvilke grupper der har samarbejdet, samt hvilke afsnit i rapporterne
der er fælles udarbejdet. Gruppemedlemmerne vil således, som normalt, underskrive deres
respektive gruppers rapport og dermed stå inde for såvel materiale udarbejdet af gruppen som
fælles udarbejdet materiale.
3
Appendix E
Contents of the CD
The attached CD contains the report, all MATLAB code developed in the project and data sheets
from all major components.
+report
-report.pdf
-CDR_SED.pdf
-CDR_Appendix.pdf
+matlab
-ADFoutput.m
-BitGen.m
-bitrev.m
-BitsToPhase.m
-Demodulate.m
-DetermineFrequency.m
-Extract.m
-FindPacket.m
-FindPackets.m
-GMSKmodulator.m
-Main.m
-NRZI.m
-PhaseToFrequency.m
-ReadFromDAQ.m
-ReadFromFile.m
-SaveToFile.m
-WaterfallPlot.m
+datasheets
-All datasheets used in project
+sources
-All digital sources
77
Appendix F
Abbreviations
ADC
ADF
AGC
AIS
AWGN
BER
BPF
CAN
CDR
COTS
CSDR
CSP
DaMSA
DLR
DSP
ESA
Esrange
ESTEC
ESW
FSK
GMSK
LNA
NMEA
PCB
PDR
SNSB
SAW
SED
SNR
SSC
STW
TBD
UHF
VHF
Analog to Digital Converter
ADF7020 Radio transceiver
Automatic Gain Control
Automatic Identification System
Additive White Gaussian Noise
Bit Error Rate
Band Pass Filter
Controller Area Network
Critical Design Review
Commercial off-the-shelf
Center for Software Defined Radio
CAN Space Protocol
Danish Maritime Safety Administration
Deutsches Zentrum für Luft- und Raumfahrt
Digital Signal Processor
European Space Agency
European Sounding Rocket Launching Range
European Space Research and Technology Centre, ESA
Experiment Selection Workshop
Frequency Shift Keying
Gaussian Minimum Shift Keying
Low-Noise Amplifier
National Marine Electronics Association
Printed Circuit Board
Preliminary Design Review
Swedish National Space Board
Surface Acoustic Wave
Student Experiment Documentation
Signal to Noise Ratio
Swedish Space Corporation (Eurolaunch)
Student Training Week
To be determined
Ultra High Frequency
Very High Frequency
79
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