20F050P00 E1 User Manual - Diamond Point International

20F050P00 E1 User Manual - Diamond Point International

20F050P00 E1 – 2009-11-20

F50P – 3U CompactPCI

®

PlusIO MPC8548 SBC

Configuration example

(8 HP, with heat sink unmounted)

User Manual

®

F50P – 3U CompactPCI® PlusIO MPC8548 SBC

F50P – 3U CompactPCI® PlusIO MPC8548 SBC

The F50P is a versatile, rugged PowerPC® based single-board computer for embedded applications. It is controlled by an MPC8548, or optionally an MPC8543

PowerPC® processor (alternatively with encryption unit) with clock frequencies between 800 MHz and 1.5 GHz. The SBC is equipped with ECC-controlled, soldered-on DDR2 RAM for data storage, with up to 16 GB of solid-state Flash disk for program storage as well as industrial FRAM and SRAM.

The board provides up to three Gigabit Ethernet channels, six USB ports, up to two

SATA interfaces and up to 64 user-definable I/O lines controlled by an optional onboard FPGA. These interfaces can be combined in many variations and are available at the front or at the rear using the board's J2 connector. The J2 pin assignment and connector type are in compliance with the PICMG 2.30

CompactPCI PlusIO standard – the migration path towards CompactPCI Plus. Two

USB and two RJ45 Ethernet connectors are already provided at the front panel, and space is left for an optional VGA connector.

The large FPGA on the F50P allows to add additional user-defined functions such as graphics, touch, serial interfaces, fieldbus controllers, binary I/O etc. for the needs of the individual application in an extremely flexible way. Before boot-up of the system, the FPGA is loaded from boot Flash. Updates of the FPGA contents can be made inside the boot Flash during operation. If the FPGA is assembled, the card needs an extra 4 HP in front panel space.

Equipped with a PCI-bridge chip, the F50P offers a full CompactPCI® interface

(system slot functionality) for reliable system expansion. Apart from that, the F50P can also be used as a busless, stand-alone board, with power supply from the backplane.

Being designed for operation in a conduction or convection cooled environment, the

F50P provides flexibility also in its cooling concept. Its firmly plugged-on CPU module is embedded in a covered frame. This ensures EMC protection and allows efficient conductive cooling for the F50C model , which is also available by standard. For air cooling, the F50P version comes with a tailor-made heat sink on top of the cover, requiring an 8-HP front panel, for an extended temperature range of

-40 to +70°C. The soldered components on the F50P withstand shock and vibration, and the board design is optimized for conformal coating.

The F50P comes with MENMON™ support. This firmware/BIOS can be used for bootstrapping operating systems (from disk, Flash or network), for hardware testing, or for debugging applications without running any operating system.

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Technical Data

Technical Data

CPU

• PowerPC® PowerQUICC™ III MPC8548, MPC8548E, MPC8543 or

MPC8543E

- 800MHz up to 1.5GHz

- Please see

Configuration Options

for available standard versions.

- e500 PowerPC® core with MMU and double-precision embedded scalar and vector floating-point APU

- Integrated Northbridge and Southbridge

Memory

• 2x32KB L1 data and instruction cache, 512KB/256KB L2 cache integrated in

MPC8548/MPC8543

• Up to 2GB SDRAM system memory

- Soldered

- DDR2 with or without ECC

- Up to 300 MHz memory bus frequency, depending on CPU

• Up to 16GB soldered Flash disk (SSD solid state disk)

• Up to 32MB additional DDR2 SDRAM, FPGA-controlled, e.g. for video data

• 16MB boot Flash

• 2MB non-volatile SRAM

- With GoldCap backup

• 128KB non-volatile FRAM

• Serial EEPROM 4kbits for factory settings

Mass Storage

• Parallel IDE (PATA)

- Up to 16GB soldered ATA Flash disk (SSD solid state disk)

• Serial ATA (SATA)

- Up to two ports via rear I/O J2

- Transfer rates up to 150MB/s (1.5 Gbits/s)

- Via PCI-to-SATA bridge

- See Interface Configuration Matrix showing possible I/O combinations

Graphics

• FPGA-controlled (optional)

• VGA connector prepared at front panel

I/O

• USB (host)

- Five USB 2.0 host ports

- One series A connector at front panel

- Four ports via rear I/O J2

- OHCI and EHCI implementation

- Data rates up to 480Mbits/s

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Technical Data

• USB (client)

- One USB client port on series A connector at front panel

- Via UART-to-USB converter

- Data rates up to 115.2kbits/s

- 16-byte transmit/receive buffer

- Handshake lines: none

• Ethernet

- Up to three 10/100/1000Base-T Ethernet channels with MPC8548/E (two channels with MPC8543/E)

- Two RJ45 connectors at front panel

- Two front-panel LEDs for channels for LAN link, activity status and connection speed

- All three possible also via rear I/O J2 (Note: requires additional Ethernet transformers on rear I/O board or backplane.)

- See Interface Configuration Matrix showing possible I/O combinations

• User-defined I/O

- FPGA-controlled (optional)

- Up to 64 I/O lines

- Connection via rear I/O J2

- See Interface Configuration Matrix showing possible I/O combinations

Front Connections (Standard)

• One USB 2.0 host (Series A)

• One USB client (Series A)

• Two Ethernet (RJ45)

Rear I/O

• Four USB 2.0

• Up to three 1000Base-T Ethernet

• Up to two SATA

• Up to 64 I/O lines with optional FPGA

- Reduces Ethernet/SATA interfaces

- See Interface Configuration Matrix showing possible I/O combinations

• Standard version compatible with PICMG 2.30 CompactPCI PlusIO

- Four USB 2.0

- Two SATA

FPGA

• The FPGA offers the possibility to add customized I/O functionality. See

Configuration Options

• Standard: FPGA not assembled

Miscellaneous

• Real-time clock with GoldCap backup

• Temperature sensor, power supervision and watchdog

• Status LED at the front

• Reset button

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Technical Data

CompactPCI® Bus

• Compliance with CompactPCI® Core Specification PICMG 2.0 R3.0

• System slot

• 32-bit/32-MHz PCIe®-to-PCI bridge

• V(I/O): +3.3V (+5V tolerant)

Busless Operation

• Board can be supplied with +5V, +3.3V and +12V from backplane, all other voltages are generated on the board

• Backplane J1 connector used only for power supply

Electrical Specifications

• Supply voltage/power consumption:

- +5V (-3%/+5%), 800mA approx.

- +3.3V (-3%/+5%), 350mA approx.

- ±12V (-5%/+5%), 1A approx.

Mechanical Specifications

• Dimensions: conforming to CompactPCI® specification for 3U boards

• Front panel:

- 8HP without FPGA

- 12HP with FPGA

- See also

Figure 1, Map of the board – front panel view, on page 17

• Weight: 626g

Environmental Specifications

• Temperature range (operation):

- -40..+70°C (screened)

- Airflow: min. 1.0m/s

- Conduction cooled variety F50C also available

• Temperature range (storage): -40..+85°C

• Relative humidity (operation): max. 95% non-condensing

• Relative humidity (storage): max. 95% non-condensing

• Altitude: -300m to + 3,000m

• Shock: 15g/11ms

• Bump: 10g/16ms

• Vibration (sinusoidal): 1g/10..150Hz

• Conformal coating on request

MTBF

• 162,822h @ 40°C according to IEC/TR 62380 (RDF 2000)

Safety

• PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Technical Data

EMC

• Tested according to EN 55022 (radio disturbance), IEC1000-4-2 (ESD) and

IEC1000-4-4 (burst)

BIOS

• MENMON™

Software Support

• Linux

• VxWorks®

• QNX® (on request; support of the FPU is currently not provided by QNX®)

• INTEGRITY® (Green Hills® Software)

• OS-9® (on request)

• For more information on supported operating system versions and drivers see online data sheet.

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Block Diagram

Block Diagram

System

SDRAM

DDR2

Boot

Flash

FRAM SRAM

PowerPC®

MPC8548 or

MPC8543

I²C

EEPROM RTC

Ethernet

10/100/1000Base-T

Ethernet

10/100/1000Base-T

Ethernet

10/100/1000Base-T

Supervisor

F R

F R

R

(only with

MPC8548)

UART-to-USB

PCI

Bus

66

PCI

Bus

33

PCI-to-USB

(5 ports)

(MPC8543)

(MPC8548)

PCI-to-SATA

(3 ports)

PCIe x1

F

F

R

(client)

SATA-to-PATA

R

SSD Flash

F Front connector

R

Rear I/O connector

Options

Ethernet

USB

SATA

0/1/2/3

4

0/1/2

and/or:

user-defined I/O from FPGA up to 64

R

FPGA

(option, adds 4 HP, up to 64 user I/O lines)

SDRAM

Additional

Flash

VGA

(with optional

FPGA) up to 64

F

R

Option: Busless

The F50P provides great flexibility for routing functions to rear I/O.

Please refer to “Configuration...“ for more information.

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Configuration Options

Configuration Options

CPU

• Several PowerQUICC™ III types with different clock frequencies

• MPC8548 or MPC8548E

- 1 GHz, 1.2 GHz, 1.33 GHz or 1.5 GHz

• MPC8543 or MPC8543E

- 800 MHz or 1 GHz

Memory

• System RAM

- 512 MB, 1 GB or 2 GB

- With or without ECC

• Flash Disk

- 2 GB, 4 GB, 6 GB, 8 GB, 12 GB or 16 GB

• FRAM

- 0 KB or 128 KB

• Additional SDRAM

- 0 MB or 32 MB

- With optional FPGA

I/O

• See

Interface Configuration Matrix showing possible I/O combinations

• VGA at front (with optional FPGA)

• Ethernet

- Up to two channels at front

- Up to three channels at rear

- Only two channels total with MPC8543

• SATA

- Up to two channels at rear

• Up to 64 user-defined I/O lines

- With optional FPGA, see below

- Reduces number of Ethernet/SATA channels

FPGA

• The optional onboard FPGA offers the possibility to implement customized I/O functionality.

• FPGA Altera® Arria® GX AGX35C

- 33,520 logic elements

- 1,348,416 total memory bits

- Connected to CPU via PCI Express® x1 link

• Connection

- Available pin count: 64 pins

- Functions available via rear I/O J2 connector

• Please note that the FPGA expands the board's width by 4 HP, to 12 HP!

- See also

Figure 1, Map of the board – front panel view, on page 17

• You can find more information on our web page "User I/O in FPGA"

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Configuration Options

Cooling concept

• -40..+70°C on 8 HP with heat sink (without FPGA) for convection cooling

• Conduction cooled variety F50C also available, for -40..+85°C

Please note that some of these options may only be available for large volumes.

Please ask our sales staff for more information.

Interface Configuration Matrix

FPGA I/O pins

(No FPGA)

29 38 47 56 33 42 51 60 37 46 55 64

Front I/O

Rear I/O

2 USB

2 ETH

-

2 SATA

4 USB

8/12 HP

2 ETH

1 ETH

No VGA

2 USB

1 ETH

2 SATA

2 ETH

2 SATA

4 USB

8/12 HP

VGA (routed to FPGA)

2 USB

-

3 ETH

-

3 ETH

1 ETH 2 ETH

2 ETH 1 ETH

-

-

-

3 ETH

1 ETH

2 ETH

2 ETH

1 ETH

-

-

2 SATA 2 SATA 2 SATA 2 SATA 2 SATA 1 SATA 1 SATA 1 SATA 1 SATA

4 USB

12 HP

- 1 ETH 2 ETH

3 ETH 2 ETH 1 ETH

- - -

Form factor

The standard configuration is compatible with the PICMG 2.30 CompactPCI PlusIO specification.

-

-

-

The standard configuration is highlighted in

bold blue

in the table.

For available standard configurations see online data sheet.

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Product Safety

Product Safety

!

Electrostatic Discharge (ESD)

Computer boards and components contain electrostatic sensitive devices.

Electrostatic discharge (ESD) can damage components. To protect the board and other components against damage from static electricity, you should follow some precautions whenever you work on your computer.

• Power down and unplug your computer system when working on the inside.

• Hold components by the edges and try not to touch the IC chips, leads, or circuitry.

• Use a grounded wrist strap before handling computer components.

• Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system.

• Store the board only in its original ESD-protected packaging. Retain the original packaging in case you need to return the board to MEN for repair.

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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About this Document

About this Document

This user manual describes the hardware functions of the board, connection of peripheral devices and integration into a system. It also provides additional information for special applications and configurations of the board.

The manual does not include detailed information on individual components (data sheets etc.). A list of literature is given in the appendix.

History

E1

Issue

First issue

Comments Date

2009-11-20

Conventions

!

italics

bold

monospace hyperlink

IRQ#

/IRQ in/out

This sign marks important notes or warnings concerning proper functionality of the product described in this document. You should read them in any case.

Folder, file and function names are printed in italics.

Bold type is used for emphasis.

A monospaced

font type is used for hexadecimal numbers, listings, C function descriptions or wherever appropriate. Hexadecimal numbers are preceded by "0x".

Hyperlinks are printed in blue color .

The globe will show you where hyperlinks lead directly to the Internet, so you can look for the latest information online.

Signal names followed by "#" or preceded by a slash ("/") indicate that this signal is either active low or that it becomes active at a falling edge.

Signal directions in signal mnemonics tables generally refer to the corresponding board or component, "in" meaning "to the board or component", "out" meaning

"coming from it".

Vertical lines on the outer margin signal technical changes to the previous issue of the document.

MEN Mikro Elektronik GmbH

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About this Document

Legal Information

MEN Mikro Elektronik reserves the right to make changes without further notice to any products herein. MEN makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does MEN assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.

MEN does not convey any license under its patent rights nor the rights of others.

Unless agreed otherwise, MEN products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the MEN product could create a situation where personal injury or death may occur. Should Buyer purchase or use MEN products for any such unintended or unauthorized application, Buyer shall indemnify and hold MEN and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that MEN was negligent regarding the design or manufacture of the part.

Unless agreed otherwise, the products of MEN Mikro Elektronik are not suited for use in nuclear reactors or for application in medical appliances used for therapeutical purposes. Application of MEN products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product.

ESM™, ESMini™, MDIS™, MDIS4™, MENMON™, M-Module™, M-Modules™, SA-Adapter™, SA-Adapters™,

UBox™, USM™ and the MBIOS logo are trademarks of MEN Mikro Elektronik GmbH. PC-MIP® is a registered trademark of MEN Micro, Inc. and SBS Technologies, Inc. MEN Mikro Elektronik®, ESMexpress®, MIPIOS® and the MEN logo are registered trademarks of MEN Mikro Elektronik GmbH.

Altera®, Arria®, Avalon®, Cyclone®, Nios® and Quartus® are registered trademarks of Altera Corp. Freescale™ and

PowerQUICC™ are trademarks of Freescale Semiconductor, Inc. PowerPC® is a registered trademark of IBM Corp. Green

Hills® and INTEGRITY® are registered trademarks of Green Hills Software, Inc. OS-9®, OS-9000® and SoftStax® are registered trademarks of RadiSys Microware Communications Software Division, Inc. FasTrak™ and Hawk™ are trademarks of RadiSys Microware Communications Software Division, Inc. RadiSys® is a registered trademark of RadiSys Corporation.

PCI Express® and PCIe® are registered trademarks of PCI-SIG. QNX® is a registered trademark of QNX Ltd. Tornado® and

VxWorks® are registered trademarks of Wind River Systems, Inc.

All other products or services mentioned in this publication are identified by the trademarks, service marks, or product names as designated by the companies who market those products. The trademarks and registered trademarks are held by the companies producing them. Inquiries concerning such trademarks should be made directly to those companies. All other brand or product names are trademarks or registered trademarks of their respective holders.

Information in this document has been carefully checked and is believed to be accurate as of the date of publication; however, no responsibility is assumed for inaccuracies. MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability, function or design. MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document.

Copyright © 2009 MEN Mikro Elektronik GmbH. All rights reserved.

Please recycle

Germany

MEN Mikro Elektronik GmbH

Neuwieder Straße 5-7

90411 Nuremberg

Phone +49-911-99 33 5-0

Fax +49-911-99 33 5-901

E-mail [email protected]

www.men.de

France

MEN Mikro Elektronik SA

18, rue René Cassin

ZA de la Châtelaine

74240 Gaillard

Phone +33 (0) 450-955-312

Fax +33 (0) 450-955-211

E-mail [email protected]

www.men-france.fr

USA

MEN Micro, Inc.

24 North Main Street

Ambler, PA 19002

Phone (215) 542-9575

Fax (215) 542-9577

E-mail [email protected]

www.menmicro.com

MEN Mikro Elektronik GmbH

20F050P00 E1 – 2009-11-20

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Contents

Contents

1 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1 Maps of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.2 Integrating the Board into a System . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3 Installing Operating System Software . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4 Installing Driver Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 Board Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4 Processor Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.2

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.5 Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5.1

Host-to-PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5.2

Local PCI Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5.3

Local PCI Express Connections . . . . . . . . . . . . . . . . . . . . . . 23

2.6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.6.1

DRAM System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.6.2

FRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.6.3

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.6.4

Boot Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.6.5

Solid State Flash Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.7 Mass Storage: Serial ATA (SATA) / SSD . . . . . . . . . . . . . . . . . . . . . . 25

2.8 USB Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.8.1

Front-Panel Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.8.2

Rear I/O Connection (CompactPCI PlusIO) . . . . . . . . . . . . . 26

2.9 Ethernet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.9.1

Front-Panel Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.9.2

Rear I/O Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.9.3

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.9.4

10Base-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.9.5

100Base-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.9.6

1000Base-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.10 CompactPCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.11 Rear I/O (CompactPCI PlusIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.11.1

User-Defined I/O from Onboard FPGA . . . . . . . . . . . . . . . . 31

2.11.2

Standard and Possible Pin Assignments . . . . . . . . . . . . . . . . 32

2.12 Reset Button and Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Contents

3 MENMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.1

State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2 Interacting with MENMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2.1

Entering the Setup Menu/Command Line . . . . . . . . . . . . . . 40

3.3 Configuring MENMON for Automatic Boot . . . . . . . . . . . . . . . . . . . 40

3.4 Updating Boot Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4.1

Update via the Serial Console using SERDL . . . . . . . . . . . . 41

3.4.2

Update from Network using NDL. . . . . . . . . . . . . . . . . . . . . 41

3.4.3

Update via Program Update Menu . . . . . . . . . . . . . . . . . . . . 41

3.4.4

Automatic Update Check . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4.5

Updating MENMON Code . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5 Diagnostic Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.5.1

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.5.2

SDRAM, SRAM and FRAM . . . . . . . . . . . . . . . . . . . . . . . . 44

3.5.3

EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.5.4

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.5.5

Hardware Monitor Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.5.6

RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.6 MENMON Configuration and Organization . . . . . . . . . . . . . . . . . . . . 48

3.6.1

Consoles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.6.2

MENMON Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.6.3

MENMON BIOS Logical Units . . . . . . . . . . . . . . . . . . . . . . 50

3.6.4

System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.7 MENMON Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 Organization of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1 Memory Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.2 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.3 SMB Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.4 Onboard PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1 Literature and Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.1

PowerPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.2

SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.3

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.4

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.5

CompactPCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.6

CompactPCI PlusIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2 Finding out the Board’s Article Number, Revision and Serial Number62

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Figures

Figure 1. Map of the board – front panel view . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Map of the board – top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3. MENMON – State diagram, Degraded Mode/Full Mode . . . . . . . . . . 38

Figure 4. MENMON – State diagram, main state . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 5. Label giving the board’s article number, revision and serial number . 62

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Tables

Table 1.

Processor core options on F50P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 2.

Pin assignment of USB front-panel connectors . . . . . . . . . . . . . . . . . . 26

Table 3.

Signal mnemonics of USB front-panel connectors . . . . . . . . . . . . . . . 26

Table 4.

Pin assignment and status LEDs of Ethernet front-panel connectors. . 27

Table 5.

Signal mnemonics of Ethernet front-panel connectors. . . . . . . . . . . . . 28

Table 6.

Pin assignment of rear I/O connector J2 – standard board version (PICMG

2.30 CompactPCI PlusIO compatible) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7.

Pin assignment of rear I/O connector J2 – I/O options: Ethernet, USB,

SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8.

Pin assignment of rear I/O connector J2 – I/O options: maximum FPGA control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 9.

Signal mnemonics of rear I/O connector J2 . . . . . . . . . . . . . . . . . . . . . 35

Table 10. MENMON – Program update files and locations . . . . . . . . . . . . . . . . 41

Table 11. MENMON – Diagnostic tests: Ethernet. . . . . . . . . . . . . . . . . . . . . . . . 43

Table 12. MENMON – Diagnostic tests: SDRAM, SRAM and FRAM . . . . . . . 44

Table 13. MENMON – Diagnostic tests: EEPROM . . . . . . . . . . . . . . . . . . . . . . 45

Table 14. MENMON – Diagnostic tests: USB. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 15. MENMON – Diagnostic tests: hardware monitor . . . . . . . . . . . . . . . . 46

Table 16. MENMON – Diagnostic tests: RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 17. MENMON – System parameters for console selection and configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 18. MENMON – Address map (full-featured mode) . . . . . . . . . . . . . . . . . 49

Table 19. MENMON – Boot Flash memory map . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 20. MENMON – Controller Logical Units (CLUNs). . . . . . . . . . . . . . . . . 50

Table 21. MENMON – Device Logical Units (DLUNs) . . . . . . . . . . . . . . . . . . . 50

Table 22. MENMON – F50P system parameters – Autodetected parameters . . . 51

Table 23. MENMON – F50P system parameters – Production data . . . . . . . . . . 52

Table 24. MENMON – F50P system parameters – MENMON persistent parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 25. MENMON – F50P system parameters – VxWorks bootline parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 26. MENMON – Reset causes through system parameter rststat. . . . . . . . 55

Table 27. MENMON – Command reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 28. Memory map – processor view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 29. Address mapping for PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 30. Dedicated interrupt line assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 31. Interrupt numbering assigned by MENMON . . . . . . . . . . . . . . . . . . . . 59

Table 32. SMB devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 33. Onboard PCI devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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Getting Started

1 Getting Started

This chapter gives an overview of the board and some hints for first installation in a system.

1.1

Maps of the Board

Figure 1. Map of the board – front panel view

With FPGA

F50P Standard 8HP

®

Additional space needed because of

FPGA

F50P

Note: VGA can be implemented as an option with an onboard FPGA.

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Figure 2. Map of the board – top view

USB-0

USB-1

(UART-to-USB)

LAN-0

LAN-1

VGA

(option)

Heat Sink

Getting Started

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Getting Started

!

1.2

Integrating the Board into a System

If you need electrical isolation between shield (rack or enclosure) and (digital) ground, you need to use guide rails without a shield strip in your CompactPCI rack for the slot where the F50P is inserted.

You can use the following check list when installing the board in a system for the first time and with minimum configuration.

; Power-down the system.

; Remove all boards from the CompactPCI system.

; Insert the F50P into the system slot of your CompactPCI system, making sure that the CompactPCI connectors are properly aligned.

Note: The system slot of every CompactPCI system is marked by a triangle on the backplane and/or at the front panel. It also has red guide rails.

You should generally use a host computer for first operation, typically under Linux or Windows.

; Install a USB-to-UART driver on your host computer.

You can use a Windows driver provided by MEN (article number 13T005-70, third-party) or go to the FTDI web site ( www.ftdichip.com/FTDrivers.htm

) and download a driver there.

; Connect your host computer to the front panel USB-1 port of the F50P (UARTto-USB interface). To do this, you need a suitable USB cable (type A to A).

; Power-up the system.

; Start up a terminal program on your host computer, e.g. HyperTerm under Windows, and open a terminal connection.

; Set your terminal connection to the following protocol:

- 9600 baud data transmission rate

- 8 data bits

- 1 stop bit

- No parity

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Getting Started

; When the terminal connection is made, press Enter. Now you can use the MEN-

MON BIOS/firmware (see detailed description in

Chapter 3 MENMON on page 37

).

If you enter command "LOGO" on the MENMON prompt, the terminal displays a message similar to the following:

________ Secondary MENMON for MEN MPC8548 Family (XM50) 1.7 _________________

| |

| (c) 2007 - 2008 MEN Mikro Elektronik GmbH Nuremberg |

| MENMON 2nd Edition, Created Jun 12 2008 10:45:08 |

|_____________________________________________________________________________|

| CPU Board: XM50-03 | CPU: MPC8548 |

|Serial Number: 4 | CPU/MEM Clk: 1386 / 198 MHz |

| HW Revision: 00.00.00 | CCB/LBC Clk: 396 / 50 MHz |

| | |

| PCI1/PCI2: 32Bit 66MHz/32Bit 33MHz| PCIe: x4 |

| DDR2 SDRAM: 512 MB ECC on 3.0/3/8 | FRAM/SRAM: 128 /2048 kB |

| Produced: | FLASH: 16 MB |

| Last repair: | Reset Cause: Power On |

|_____________________________________________________________________________|

| Carrier Board: F503-00, Rev 00.01.00, Serial 3 |

\___________________________________________________________________________/

Note: Don’t power off the F50P now, otherwise the USB-to-UART interface on the host computer will be disconnected.

; Observe the installation instructions for the respective software.

!

1.3

Installing Operating System Software

The board supports Linux, VxWorks, and INTEGRITY.

By default, no operating system is installed on the board. Please refer to the respective manufacturer's documentation on how to install operating system software!

You can find any software available on MEN’s website .

1.4

Installing Driver Software

For a detailed description on how to install driver software please refer to the respective documentation.

You can find any driver software available for download on MEN’s website .

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2

Functional Description

Functional Description

The following describes the individual functions of the board and their configuration on the board. There is no detailed description of the individual controller chips and the CPU. They can be obtained from the data sheets or data

books of the semiconductor manufacturer concerned ( Chapter 5.1 Literature and

Web Resources on page 61 ).

2.1

Power Supply

The board is supplied via CompactPCI connector J1 with +5 V, +3.3 V and ±12 V.

All other required voltages are generated on the board.

The F50P may also be operated as a stand-alone card, without the CompactPCI bus.

In this case, power is also supplied via the J1 connector. Three voltages are needed:

+5 V, +3.3 V and +12 V.

2.2

Board Supervision

The board features a temperature sensor and voltage monitor.

A voltage monitor supervises all used voltages and holds the CPU in reset condition until all supply voltages are within their nominal values.

In addition the board contains a PLD watchdog that must be triggered. After configuration the CPU serves the PLD watchdog. The watchdog timeout is automatically set to 1.12 s after the first trigger pulse by the CPU.

The watchdog can be enabled or disabled through MENMON and can be triggered by a software application. This function is normally supported by the board support package (see BSP documentation).

2.3

Real-Time Clock

The board includes an RA8581 real-time clock. Interrupt generation of the RTC is not supported. For data retention during power off the RTC is supplied by a

GoldCap.

A control flag indicates a back-up power fail condition. In this case the contents of the RTC cannot be expected to be valid. A message will be displayed on the

MENMON console in this case.

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Functional Description

2.4

Processor Core

The board is equipped with the MPC8548 or MPC8543 processor, which includes a

32-bit PowerPC e500 core, the integrated host-to-PCI bridge, Ethernet controllers and UARTs.

2.4.1

General

The MPC8548/3 family of processors integrates an e500v2 processor core built on

Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8548/3 is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology.

The MPC8548/3 offers a double-precision floating-point auxiliary processing unit

(APU), up to 512 KB of level-2 cache, up to four integrated 10/100/1Gbits/s enhanced three-speed Ethernet controllers with TCP/IP acceleration and classification capabilities, a DDR/DDR2 SDRAM memory controller, a programmable interrupt controller, two I²C controllers, a four-channel DMA controller, a general-purpose I/O port, and dual universal asynchronous receiver/ transmitters (DUART).

The MPC8548/3 is available with (MPC8548/3E) or without an integrated security engine with XOR acceleration.

Table 1. Processor core options on F50P

Processor Type

MPC8548

MPC8548E

MPC8543

MPC8543E

Core Frequency

1 GHz, 1.2 GHz, 1.33 GHz or

1.5 GHz

1 GHz, 1.2 GHz, 1.33 GHz or

1.5 GHz

800 MHz or 1 GHz

800 MHz or 1 GHz

L2 Cache

512 KB

512 KB

256 KB

256 KB

Encryption Unit Ethernet Ports

No 3

Yes

No

Yes

3

2

2

!

2.4.2

Thermal Considerations

The F50P generates around 17 W of power dissipation when operated at 1.33 GHz.

A suitable heat sink is provided to meet thermal requirements.

Please note that if you use any other heat sink than that supplied by MEN, or no heat sink at all, warranty on functionality and reliability of the F50P may cease. If you have any questions or problems regarding thermal behavior, please contact MEN.

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Functional Description

2.5

Bus Structure

2.5.1

Host-to-PCI Bridge

The integrated host-to-PCI bridge is used as host bridge and memory controller for the PowerPC processor. All transactions of the PowerPC to the PCI bus are controlled by the host bridge. The FRAM, SRAM and boot Flash are connected to the local memory bus of the integrated host-to-PCI bridge.

The PCI interface is PCI bus Rev. 2.2 compliant and supports all bus commands and transactions. Master and target operations are possible. Only big-endian operation is supported.

2.5.2

Local PCI Buses

Two local PCI buses are controlled by the integrated host-to-PCI bridge. One is connected to the PCI-to-USB bridge and runs at 33 MHz. The other connects the

PCI-to-SATA bridge and operates at 66 MHz. Board versions with the MPC8543 processor only have one local PCI bus operating at 33 MHz.

The I/O voltage is fixed to 3.3V. The data width is 32 bits.

2.5.3

Local PCI Express Connections

A PCI Express x1 link connects the PowerPC processor with the CompactPCI bus

(via a PCIe-to-PCI bridge) and with the optional FPGA.

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Functional Description

2.6

Memory

2.6.1

DRAM System Memory

The board provides up to 2 GB onboard, soldered DDR2 (double data rate) SDRAM on nine memory components (incl. ECC). The memory bus is 72 bits wide and operates at up to 300 MHz (physical), depending on the processor type.

Depending on the board version the SDRAM may have ECC (error-correcting code). ECC memory provides greater data accuracy and system uptime by protecting against soft errors in computer memory.

2.6.2

FRAM

The board has up to 128 KB non-volatile FRAM memory connected to the local bus of the CPU.

The FRAM does not need a back-up voltage for data retention.

2.6.3

SRAM

The board has up to 2 MB non-volatile SRAM memory connected to the local bus of the CPU. For data retention during power off the SRAM is supplied with a backup voltage by a GoldCap.

2.6.4

Boot Flash

The board has 16 MB of onboard Flash. It is controlled by the CPU.

Flash memory contains the boot software for the MENMON/operating system bootstrapper and application software. The MENMON sectors are softwareprotected against illegal write transactions through a password in the serial

download function of MENMON (cf. Chapter 3.4.1 Update via the Serial Console using SERDL on page 41

).

2.6.5

Solid State Flash Disk

The board includes up to 16 GB soldered NAND Flash disk.

A solid state disk (SSD) is a data storage device that uses solid-state memory to store persistent data. An SSD behaves like a conventional hard disk drive. On F50P it has a PATA interface connected to a SATA-to-PATA bridge and controlled by one

SATA channel. (See also

Chapter 2.7 Mass Storage: Serial ATA (SATA) / SSD on page 25

.)

With no moving parts, a solid state disk is more robust, effectively eliminating the risk of mechanical failure, and usually enjoys reduced seek time and latency by removing mechanical delays associated with a conventional hard disk drive.

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Functional Description

2.7

Mass Storage: Serial ATA (SATA) / SSD

The F50P provides three serial ATA channels through a PCI-to-SATA converter that is connected to the PowerPC processor via a dedicated 66-MHz PCI bus. (On board versions with the MPC8543 processor PCI-to-SATA shares one 33-MHz PCI bus with PCI-to-USB.)

The SATA interfaces support 1.5 Gbits/s.

One SATA channel is used for the SSD solid state Flash disk. (See also Chapter

2.6.5 Solid State Flash Disk on page 24

.) The other two SATA channels are led to the rear I/O J2 connector. The pin assignment is in compliance with the PICMG

2.30 CompactPCI PlusIO standard.

See

Chapter 2.11 Rear I/O (CompactPCI PlusIO) on page 30

for J2 rear I/O pin assignments.

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Functional Description

2.8

USB Interfaces

The F50P provides five USB 2.0 host ports with OHCI/EHCI implementation and one USB client port. One host port (USB-0) and the client port (UART-to-USB,

USB-1) are led to the front panel. Up to four host ports are available via rear I/O on connector J2.

The host ports are controlled via PCI-to-USB bridges from the PowerPC processor, while the client port is driven by a UART-to-USB converter.

The UART-to-USB interface supports data rates up to 115.2 kbits/s. It has no handshake lines. In connection with USB-to-UART driver software it can be used as a COM interface and is supported by MENMON as a console device.

2.8.1

Front-Panel Connection

One host port (USB-0) and the client port (UART-to-USB, USB-1) are accessible at the front panel.

Connector types:

• 4-pin USB Series A receptacle according to Universal Serial Bus Specification

Revision 1.0

• Mating connector:

4-pin USB Series A plug according to Universal Serial Bus Specification Revision 1.0

Table 2. Pin assignment of USB front-panel connectors

1

2

3

4

3

4

1

2

+5V

USB_D-

USB_D+

GND

Table 3. Signal mnemonics of USB front-panel connectors

+5V

GND

Signal

USB_D+, USB_D-

USB-0: out

USB-1: in

-

Direction

in/out

Function

+5 V power supply

Output for host port USB-0

Input for client port USB-1

Digital ground

USB lines, differential pair

2.8.2

Rear I/O Connection (CompactPCI PlusIO)

Up to four USB interfaces are accessible via rear I/O in compliance with the

PICMG 2.30 CompactPCI PlusIO standard.

See

Chapter 2.11 Rear I/O (CompactPCI PlusIO) on page 30

for J2 rear I/O pin assignments.

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Functional Description

!

!

2.9

Ethernet Interfaces

The F50P has up to three Ethernet interfaces controlled by the CPU. All channels support up to 1000 Mbits/s and full-duplex operation.

LAN-0 and LAN-1 are accessible at the front panel, while LAN-2 is available as an option at the J2 rear I/O connector. As an option, even all three Ethernet channels can be made available via J2 rear I/O. The rear Ethernet interfaces are not compliant with PICMG 2.30 CompactPCI PlusIO.

Please note that LAN-2 is not available on board versions with the MPC8543 processor.

The unique MAC address is set at the factory and should not be changed. Any attempt to change this address may create node or bus contention and thereby render the board inoperable. The MAC addresses on F50P are:

• LAN-0:

• LAN-1:

• LAN-2:

0x 00 C0 3A 87 xx xx

0x 00 C0 3A 88 xx xx

0x 00 C0 3A 89 xx xx where "00 C0 3A" is the MEN vendor code, "87", "88" and "89" are the MEN product codes, and "xx xx" is the hexadecimal serial number of the product, which depends on your board, e. g. "...

00 2A

" for serial number "000042".

2.9.1

Front-Panel Connection

Two standard RJ45 connectors for ports LAN-0 and LAN-1 are available at the front panel. There are also two status LEDs for each channel at the front panel.

The pin assignment corresponds to the Ethernet specification IEEE802.3.

Connector types:

• Modular 8/8-pin mounting jack according to FCC68

• Mating connector:

Modular 8/8-pin plug according to FCC68

Table 4. Pin assignment and status LEDs of Ethernet front-panel connectors

Blinks whenever there is transmit or receive activity

On: 1000Base-T link

Off: 10/100Base-T link

1/3

2/4

1

8

1

2

3

4

5

6

7

8

1000Base-T 10/100Base-T

BI_DA+ TX+

BI_DA-

BI_DB+

TX-

RX+

BI_DC+

BI_DC-

BI_DB-

BI_DD+

BI_DD-

-

-

RX-

-

-

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Functional Description

Table 5. Signal mnemonics of Ethernet front-panel connectors

Signal

BI_Dx+/-

RX+/-

TX+/in/out in

Direction

out

Function

Differential pairs of data lines for 1000Base-T

Differential pair of receive data lines for 10/

100Base-T

Differential pair of transmit data lines for 10/

100Base-T

2.9.2

Rear I/O Connection

All of the three Ethernet channels can alternatively be routed to the J2 rear I/O connector. By default, no Ethernet is led to connector J2.

See

Chapter 2.11 Rear I/O (CompactPCI PlusIO) on page 30

for more information and possible J2 rear I/O pin assignments.

2.9.3

General

Ethernet is a local-area network (LAN) protocol that uses a bus or star topology and supports data transfer rates of 100 Mbits/s and more. The Ethernet specification served as the basis for the IEEE 802.3 standard, which specifies the physical and lower software layers. Ethernet is one of the most widely implemented LAN standards.

Ethernet networks provide high-speed data exchange in areas that require economical connection to a local communication medium carrying bursty traffic at high-peak data rates.

A classic Ethernet system consists of a backbone cable and connecting hardware

(e.g. transceivers), which links the controllers of the individual stations via transceiver (transmitter-receiver) cables to this backbone cable and thus permits communication between the stations.

2.9.4

10Base-T

10Base-T is one of several adaptations of the Ethernet (IEEE 802.3) standard for

Local Area Networks (LANs). The 10Base-T standard (also called Twisted Pair

Ethernet) uses a twisted-pair cable with maximum lengths of 100 meters. The cable is thinner and more flexible than the coaxial cable used for the 10Base-2 or

10Base-5 standards. Since it is also cheaper, it is the preferable solution for costsensitive applications.

Cables in the 10Base-T system connect with RJ45 connectors. A star topology is common with 12 or more computers connected directly to a hub or concentrator.

The 10Base-T system operates at 10 Mbits/s and uses baseband transmission methods.

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Functional Description

2.9.5

100Base-T

The 100Base-T networking standard supports data transfer rates up to 100 Mbits/s.

100Base-T is actually based on the older Ethernet standard. Because it is 10 times faster than Ethernet, it is often referred to as Fast Ethernet. Officially, the 100Base-T standard is IEEE 802.3u.

There are several different cabling schemes that can be used with 100Base-T, e.g.

100Base-TX, with two pairs of high-quality twisted-pair wires.

2.9.6

1000Base-T

1000Base-T is a specification for Gigabit Ethernet over copper wire (IEEE

802.3ab). The standard defines 1 Gbit/s data transfer over distances of up to 100 meters using four pairs of CAT-5 balanced copper cabling and a 5-level coding scheme.

Because many companies already use CAT-5 cabling, 1000Base-T can be easily implemented.

Other 1000Base-T benefits include compatibility with existing network protocols

(i.e. IP, IPX, AppleTalk), existing applications, Network Operating Systems, network management platforms and applications.

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Functional Description

!

2.10

CompactPCI Interface

The F50P is a 3U CompactPCI system slot board. It implements a 32-bit PCI interface to the CompactPCI backplane which uses a +3.3 V signaling voltage. It also tolerates +5 V.

The CompactPCI bus connects to the MPC8548/MPC8543 processor via a PCI

Express x1 link and a PCIe-to-PCI bridge.

The pin assignment of connector J1 as defined in the CompactPCI specification will not be repeated here.

2.11

Rear I/O (CompactPCI PlusIO)

The F50P provides great flexibility for routing functions to rear I/O. An optional onboard FPGA allows to implement customized functions on rear I/O connector J2 of the board, with a total available pin count of 64 pins. Different combinations of interfaces controlled by the CPU and the FPGA are possible. The standard version of the F50P is compliant to the PICMG 2.30 CompactPCI PlusIO standard. It supports the pin assignment defined by PICMG 2.30 with 2 SATA and 4 USB interfaces at the J2 connector.

The four USB ports are always routed to the J2 connector.

Please note that the rear I/O Ethernet interfaces of the F50P are not compliant to the CompactPCI PlusIO standard! The Ethernet transformers for the rear

Ethernet ports are not located on the F50P but must be placed on a rear I/O

board or on the backplane. This means that it is possible to route up to three

Ethernet channels to rear I/O, but additional transformers need to be implemented then, and the pinout will not be compliant with PICMG 2.30 CompactPCI PlusIO.

MEN offers a rear I/O transition module on which the two SATA and four USB interfaces from the J2 connector can be accessed, the CT12. Please note that because of the fixed PICMG 2.30 J2 pin assignment of CT12, only PICMG 2.30

compliant versions of F50P should be used with the CT12. Otherwise signals that have a different function on the F50P may interfere with the CT12 signals.

!

The Interface Configuration Matrix shows an overview of all varieties that are pos-

sible.

Chapter 2.11.2 Standard and Possible Pin Assignments on page 32

gives the standard pin assignment along with possible signal routings.

For further information on the CT12 rear I/O transition module see MEN’s website .

In any case please contact our sales team for specially configured board versions. This chapter only summarizes the board’s options.

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Functional Description

!

2.11.1

User-Defined I/O from Onboard FPGA

The F50P provides the option to include an onboard FPGA. The component is a powerful Altera Arria GX AGX35C device, and is connected to the CPU via a fast, serial PCI Express x1 link. It permits to configure the board’s rear I/O according to your needs without any hardware modifications.

Please note that a J2 pin assignment compliant with the PICMG 2.30 CompactPCI

PlusIO standard is not possible when customized functions are implemented through the FPGA.

With regard to the FPGA resources such as available logic elements or pins it is not possible to grant all possible combinations of FPGA IP cores.

You can find an overview and descriptions of all available FPGA IP cores on

MEN’s website .

Table 8, Pin assignment of rear I/O connector J2 – I/O options: maximum FPGA control on page 34

gives the I/O pins available for custom FPGA functions (64 pins).

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Functional Description

2.11.2

Standard and Possible Pin Assignments

Table 6. Pin assignment of rear I/O connector J2 – standard board version (PICMG 2.30 CompactPCI

PlusIO compatible)

22

21

F E D C B A Z

1

F

22 GND

21 GND

20 GND

19 GND

18 GND

17 GND

16 GND

15 GND

14 GND

13 GND

12 GND

11 GND

10 GND

9 GND

E

GA0

-

-

-

-

GNT6#

-

GNT5#

-

-

-

-

-

-

8 GND SATA2_RX+ -

7 GND SATA2_RXSATA2_TX+

6 GND SATA1_RX+ SATA2_TX-

5 GND SATA1_RXSATA1_TX+

4 GND

3 GND

2 GND

1 GND

-

GNT4#

REQ3#

REQ2#

SATA1_TX-

REQ4#

GNT2#

GNT1#

GND

REQ5#

-

-

-

-

-

-

D

GA1

-

-

-

-

REQ6#

-

-

-

-

-

-

-

-

B

GA3

GND

GND

GND

-

-

-

GND

CLK3

GND

-

-

-

-

-

USB6+

USB6-

USB5+

-

-

-

-

-

-

-

-

C

GA2

-

USB5-

USB4+

USB4-

USB3+

USB3-

GNT3#

SYSEN#

REQ1#

-

-

-

-

-

-

-

-

A

GA4

CLK6

CLK5

GND

-

-

VIO

CLK4

CLK2

CLK1

-

-

-

-

GND

GND

GND

GND

GND

GND

GND

GND

Z

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Note: The F50P’s J2 connector type complies with the PICMG 2.30 CompactPCI

PlusIO standard.

Note: The signal mnemonics in the above table correspond to the PICMG 2.30

CompactPCI PlusIO standard and therefore do not show the F50P-internal interface numbering. Please see

Chapter Table 7. Pin assignment of rear I/O connector J2 – I/O options: Ethernet, USB, SATA on page 33

for the boardinternal numbering.

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Functional Description

The following table shows all options for non-FPGA-controlled interfaces. For this reason, only those pins are marked for FPGA I/O that cannot be used for other functions. See

Table 8, Pin assignment of rear I/O connector J2 – I/O options: maximum FPGA control on page 34 for the assignment of the maximum number of

FPGA-controlled pins.

Table 7. Pin assignment of rear I/O connector J2 – I/O options: Ethernet, USB, SATA

22

21

F E D C B A Z

1

F

22 GND

E

GA0

21 GND ETH0_1+

20 GND ETH0_1-

19 GND ETH0_0+

18 GND ETH0_0-

17 GND GNT6#

16 GND ETH0_VCC

D

GA1

ETH0_3+

ETH0_3-

ETH0_2+

ETH0_2-

REQ6#

GND

15 GND GNT5# REQ5#

14 GND ETH0_ACT# ETH0_LNK#

13 GND

12 GND

IO[29]

IO[27]

IO[28]

IO[26]

11 GND

10 GND

IO[25]

IO[23]

9 GND IO[21]

8 GND SATA2_RX+

IO[24]

IO[22]

IO[20]

IO[18]

7 GND SATA2_RXSATA2_TX+

6 GND SATA1_RX+ SATA2_TX-

5 GND SATA1_RXSATA1_TX+

4 GND IO[11] SATA1_TX-

3 GND

2 GND

1 GND

GNT4#

REQ3#

REQ2#

REQ4#

GNT2#

GNT1#

-

IO[63]

-

IO[64]

USB6+

USB6-

USB5+

USB5-

C

GA2

ETH1_1+

ETH1_1-

ETH1_0+

ETH1_0-

-

-

USB4+

USB4-

USB3+

USB3-

GNT3#

SYSEN#

REQ1#

B

GA3

GND

GND

A

GA4

CLK6

CLK5

Z

GND

GND

GND

GND

ETH1_2+

GND GND

ETH1_3+ GND

ETH1_2ETH1_3GND

ETH1_ACT# ETH1_VCC GND

ETH2_0+ ETH1_LNK# GND

ETH2_0ETH2_1+ GND

ETH2_2+

ETH2_2-

ETH2_1-

ETH2_3+

GND

GND

ETH2_ACT# ETH2_3GND

+3.3V

ETH2_VCC GND

ETH2_LNK#

+5V

+3.3V

+5V

GND

GND

IO[6]

IO[8]

USB_OC5/6#

USB_OC3/4#

GND

CLK3

GND

IO[5]

IO[7]

IO[9]

VIO

CLK4

CLK2

CLK1

GND

GND

GND

GND

GND

GND

GND

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Functional Description

Table 8. Pin assignment of rear I/O connector J2 – I/O options: maximum FPGA control

22

21

F E D C B A Z

1

-

IO[63]

-

IO[64]

USB6+

USB6-

USB5+

USB5-

C

GA2

IO[44]

IO[43]

IO[42]

IO[41]

-

-

USB4+

USB4-

USB3+

USB3-

GNT3#

SYSEN#

REQ1#

REQ5#

IO[30]

IO[28]

IO[26]

IO[24]

IO[22]

IO[20]

IO[18]

D

GA1

IO[40]

IO[39]

IO[38]

IO[37]

REQ6#

GND

IO[16]

IO[14]

IO[12]

IO[10]

REQ4#

GNT2#

GNT1#

GNT5#

IO[31]

IO[29]

IO[27]

IO[25]

IO[23]

IO[21]

IO[19]

E

GA0

IO[36]

IO[35]

IO[34]

IO[33]

GNT6#

IO[32]

IO[17]

IO[15]

IO[13]

IO[11]

GNT4#

REQ3#

REQ2#

F

22 GND

21 GND

20 GND

19 GND

18 GND

17 GND

16 GND

15 GND

14 GND

13 GND

12 GND

11 GND

10 GND

9 GND

8 GND

7 GND

6 GND

5 GND

4 GND

3 GND

2 GND

1 GND

IO[51]

IO[53]

IO[55]

IO[57]

IO[59]

IO[61]

IO[2]

IO[4]

B

GA3

GND

GND

GND

IO[45]

IO[47]

IO[49]

IO[6]

IO[8]

USB_OC5/6#

USB_OC3/4#

GND

CLK3

GND

IO[52]

IO[54]

IO[56]

IO[58]

IO[60]

IO[62]

IO[1]

IO[3]

A

GA4

CLK6

CLK5

GND

IO[46]

IO[48]

IO[50]

IO[5]

IO[7]

IO[9]

VIO

CLK4

CLK2

CLK1

GND

GND

GND

GND

GND

GND

GND

GND

Z

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

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Functional Description

Table 9. Signal mnemonics of rear I/O connector J2

Power

GND

VIO

+3.3V

+5V

CompactPCI

CLK[6:1]

GA[4:0]

GNT#[6:1]

Ethernet

Signal

REQ#[6:1]

SYSEN#

ETH0_[3:0]+, ETH0_[3:0]-

ETH1_[3:0]+, ETH1_[3:0]in in in/out in/out

ETH2_[3:0]+, ETH2_[3:0]in/out

ETH0_ACT#, ETH1_ACT#, ETH2_ACT# out in out in out in in

-

Direction

SATA

ETH0_LNK#, ETH1_LNK#, ETH2_LNK# out

Function

Ground

3.3 V V(I/O) supply voltage

+3.3V supply voltage, optional

+5V supply voltage, optional

Clocks 1 to 6

Geographic addressing signals 0 to 4

Grant 1 to 6

Request 1 to 6

System slot identification

Differential data pairs 0 to 3, port 0

Differential data pairs 0 to 3, port 1

Differential data pairs 0 to 3, port 2

Signal for activity status LED, ports 0 to

2, optional

Signal for link status LED, ports 0 to 2, optional

Reference voltage, ports 0 to 2

Differential SATA receive lines, port 1

USB

ETH0_VCC, ETH1_VCC, ETH2_VCC

SATA1_RX+, SATA1_RX-

(PICMG 2.30: 1_SATA_Rx+, 1_SATA_Rx-) out in

SATA1_TX+, SATA1_TX-

(PICMG 2.30: 1_SATA_Tx+, 1_SATA_Tx-)

SATA2_RX+, SATA2_RX-

(PICMG 2.30: 2_SATA_Rx+, 2_SATA_Rx-) out in out SATA2_TX+, SATA2_TX-

(PICMG 2.30: 2_SATA_Tx+, 2_SATA_Tx-)

USB3+, USB3-

(PICMG 2.30: 1_USB2+, 1_USB2-) in/out in/out USB4+, USB4-

(PICMG 2.30: 2_USB2+, 2_USB2-)

USB5+, USB5-

(PICMG 2.30: 3_USB2+, 3_USB2-)

USB6+, USB6-

(PICMG 2.30: 4_USB2+, 4_USB2-)

USB_OC3/4#, USB_OC5/6# in/out in/out in

Differential SATA transmit lines, port 1

Differential SATA receive lines, port 2

Differential SATA transmit lines, port 2

Differential USB 2.0 lines, port 3

Differential USB 2.0 lines, port 4

Differential USB 2.0 lines, port 5

Differential USB 2.0 lines, port 6

FPGA I/O

IO[64:1] in/out

USB overcurrent, ports 3 and 4,and ports 5 and 6, optional

FPGA I/O pins, 64 lines

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Functional Description

2.12

Reset Button and Status LED

The F50P has a reset button and one status LED at the front panel. The reset button is recessed within the front panel and requires a tool, e.g. paper clip to be pressed, preventing the button from being inadvertently activated.

The yellow status LED shows board status messages. If the onboard FPGA is implemented, the LED lights up as soon as the FPGA was initialized. If no FPGA is implemented on the board, the LED has no function.

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3

MENMON

MENMON

3.1

General

MENMON is the CPU board firmware that is invoked when the system is powered on.

The basic tasks of MENMON are:

• Initialize the CPU and its peripherals.

• PCI/PCIe auto configuration.

• Perform self-test.

• Provide debug/diagnostic features on MENMON command line.

• Interaction with the user via touch panel/TFT display (if supported through

FPGA).

• Boot operating system.

• Update firmware or operating system.

The following description only includes board-specific features. For a general description and in-depth details on MENMON, please refer to the MENMON 2nd

Edition User Manual .

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MENMON

3.1.1

State Diagram

Figure 3. MENMON – State diagram, Degraded Mode/Full Mode

Degraded Mode

EarlyInit

/do CPU early init

Check if secondary MENMON valid

Secondary MENMON valid

Secondary MENMON not valid or abort pin set

DegradedStartup

StartupPrologue

Determine clocks

I²C controller init

SYSPARAM init

Init early MMBIOS devs

Check for 'D' pressed

Parse SO-DIMM SPD

Init DRAM

Check for 'd' pressed

Quick DRAM test

’D’ or ’d’ pressed

DRAM not working

DRAM ok

Relocating

MainState

Secondary

MENMON

Full Mode

FullStartup

Init heap in DRAM

StartupPrologue

MainState

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MENMON

Figure 4. MENMON – State diagram, main state

Main State

Screen Menu do/ start network servers

Screen oriented Main menu

's' pressed

SETUP

Init

Init on-chip MMBIOS devs

PCI autoconfig

RTC init

(FPGA load)

Init further MMBIOS devs

Check for user abort

No user intervention

Selftest

Perform self tests

Check for user abort

Touch pressed outside setup

TouchCalib do/ touch calibration

No user intervention

Auto Update Check do/ check for update media

Execute Auto update dialog when suitable medium found

Leave dialog after 5 seconds

User abort or

Self-test error and stignfault=false

User abort or degraded mode

Booting

Execute mmstartup string

[mmstartup empty]

Jump to bootstrapper

No user intervention

User abort or

Boot failure

MenmonCli entry/ start network servers do/ process command line

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MENMON

3.2

Interacting with MENMON

To interact with MENMON, you can use the following consoles:

• UART-to-USB COM (via UART-to-USB interface)

• Touch panel / TFT interface (if present)

• Telnet via network connection

• HTTP /monpage via network connection

The default setting of the COM ports is 9600 baud, 8 data bits, no parity, and one stop bit.

3.2.1

Entering the Setup Menu/Command Line

During normal boot, you can abort the booting process in different ways during the self-test, depending on your console:

• With a touch panel press the "Setup" button to enter the Setup Menu.

• With a text console press the "s" key to enter the Setup Menu.

• With a text console press "ESC" to enter the command line.

By default, the self-test is not left until 3 seconds have elapsed (measured from the beginning of the self-test), even if the actual test has finished earlier, to give the user a chance to abort booting and enter the Setup Menu.

You can modify the self-test wait time through MENMON system parameter stwait

(see

stwait

).

3.3

Configuring MENMON for Automatic Boot

You can configure how MENMON boots the operating system either through the

Setup Menu or through the command line.

In the Basic Setup Menu you can select the boot sequence for the bootable devices on the F50P. The selected sequence is stored in system parameter mmstartup as a string of MENMON commands. For example, if the user selects: "Int. CF, Ether,

(None)", the mmstartup string will be set to "DBOOT 0; NBOOT TFTP".

You can view and modify this string directly, using the Expert Setup Menu, option

Startup string, or through the command-line command EE-MMSTARTUP.

(See also MENMON 2nd Edition User Manual for further details.)

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MENMON

3.4

Updating Boot Flash

3.4.1

Update via the Serial Console using SERDL

You can use command SERDL to update program data using the serial console.

The following table shows the F50P locations:

Table 10. MENMON – Program update files and locations

File Name

Extension

.SMM

.Fxxx

.Exx

Typical File Name

14XM50-00_01_02.SMM

MENMON

MYFILE.F000

-

MYFILE.E00

-

Password for

SERDL

Location

Secondary MENMON

Starting at sector xxx in boot Flash

Starting at byte xx in

EEPROM

3.4.2

Update from Network using NDL

You can use the network download command NDL to download the update files from a TFTP server in network. The file name extensions, locations and passwords are the same as for the SERDL command.

3.4.3

Update via Program Update Menu

MENMON scans an external medium connected to the first USB port (USB0) for files named 14XM50*.SMM. The Program Update Menu will then give a list of all files on this medium conforming with this name pattern for selection.

3.4.4

Automatic Update Check

MENMON’s automatic update check looks for some special files on an external medium connected to the first USB port (USB0). However, the F50P implementation does not support program update here but can boot from the external medium.

The file that is searched for has a name stored in system parameter bf or bootfile, or – if this is empty – BOOTFILE. If this file is found, it is assumed that the external medium is supposed to be booted from.

To allow MENMON to locate this file, it must be in the root directory of a DOS FS.

This works on unpartitioned media or on drives with one partition.

MENMON does not automatically start the boot but presents the following menu to the user:

Detected an update capable external medium

>Ignore, continue boot

Boot from external medium

If there is no user input for 5 seconds after the menu appears, booting continues.

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MENMON

!

3.4.5

Updating MENMON Code

Updates of MENMON are available for download from MEN’s website .

MENMON’s integrated Flash update functions allow you to do updates yourself.

However, you need to take care and follow the instructions given here. Otherwise, you may make your board inoperable!

In any case, read the following instructions carefully!

Please be aware that you do MENMON updates at your own risk. After an incorrect update your CPU board may not be able to boot.

Do the following to update MENMON:

; Unzip the downloaded file, e.g. 14xm50-00_01_02.zip, into a temporary directory.

; Power on your F50P.

; Connect a terminal emulation program with the UART-to-USB port of your

F50P and set the terminal emulation program to 9600 baud, 8 data bits, 1 stop bit, no parity, no handshaking (if you haven't changed the target baud rate on your own).

1

; Reset the F50P by pressing the reset button, or through software (e.g. reboot command under VxWorks).

; Press "ESC" immediately after resetting the F50P.

; In your terminal emulation program, you should see the "MenMon>" prompt.

; Enter "SERDL MENMON" to update the secondary MENMON. You should now see a "C" character appear every 3 seconds.

; In your terminal emulation program, start a "YModem" download of file

14xm50-00_01_02.smm (for example, with Windows Hyperterm, select Trans-

fer > Send File with protocol "YModem").

; When the download is completed, reset the F50P.

1

You can change the baud rate at runtime using command cons-baud. See

Table 27,

MENMON – Command reference (page 56)

. If you want to accelerate file transfer you can select a higher baud rate in MENMON and then set the terminal emulation program accordingly.

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MENMON

3.5

Diagnostic Tests

3.5.1

Ethernet

Table 11. MENMON – Diagnostic tests: Ethernet

Test Name

ETHER0

ETHER1

Description

Ethernet 0/1/2 (LAN-0/1/2) internal loopback test

Groups: POST AUTO

ETHER2

ETHER0_X

ETHER1_X

ETHER2_X

Ethernet 0/1/2 (LAN-0/1/2) external loopback test

Groups: NONAUTO ENDLESS

Availability

Always

(except ETHER2 with an

MPC8543 processor)

Always

(except ETHER2 with an

MPC8543 processor)

3.5.1.1

Ethernet Internal Loopback Test

The test

• configures the network interface for loopback mode (on PHY)

• verifies that the interface's ROM has a good checksum

• verifies that the MAC address is valid (not

0xFFFFFF

…)

• sends 10 frames with

0x400

bytes payload each

• verifies that frames are correctly received on the same interface.

If the network interface to test is the currently activated interface for the MENMON network stack, the interface is detached from the network stack during test and reactivated after test.

Checks:

• Connection between CPU and LAN controller

• Connection between LAN controller and PHY

Does not check:

• Connection between PHY and physical connector

• Interrupt line

• All LAN speeds

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MENMON

3.5.1.2

Ethernet External Loopback Test

This test is the same as the Ethernet Internal Loopback Test, but requires an external loopback connector. Before sending frames, the link state is monitored. If it is not ok within 2 seconds, the test fails.

Note: A loopback connector makes a connection between the following pins of the

8-pin Ethernet connector: 1-3, 2-6, 4-7, 5-8.

Checks:

• Connection between CPU and LAN controller

• Connection between LAN controller and PHY

• Connection between PHY and physical connector

Does not check:

• Interrupt line

• All LAN speeds

3.5.2

SDRAM, SRAM and FRAM

Table 12. MENMON – Diagnostic tests: SDRAM, SRAM and FRAM

Test Name

SDRAM

SDRAM_X

Description

Quick SDRAM connection test

Groups: POST AUTO

Full SDRAM test

Always

Always

Availability

SRAM

SRAM_X

FRAM

FRAM_X

Groups: NONAUTO ENDLESS

Quick SRAM test

Groups: POST AUTO

Full SRAM test

Groups: NONAUTO ENDLESS

Quick FRAM test

Groups: POST AUTO

Full FRAM test

Groups: NONAUTO ENDLESS

F50P is known to have

SRAM

F50P is known to have

FRAM

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MENMON

3.5.2.1

Quick RAM Test

This quick test checks most of the connections to the RAM chips but does not test all RAM cells. It executes very quickly (within milliseconds).

This test is non-destructive (saves/restores original RAM content).

Checks:

• All address lines

• All data lines

• Byte enable signals

• Indirectly, checks clock and other control signals

Does not check:

• SDRAM cells

• Burst mode

3.5.2.2

Extended RAM Test

This full-featured memory test allows to test all RAM cells. Depending on the size of the SDRAM, this test can take up to one minute.

It tests 8-, 16- or 32-bit access, each with random pattern, and single and burst access.

On each pass, this test first fills the entire memory (starting with the lowest address) with the selected pattern, using the selected access mode, and then verifies the entire block.

This test is destructive.

Checks:

• All address lines

• All data lines

• All control signals

• All SDRAM cells

3.5.3

EEPROM

Table 13. MENMON – Diagnostic tests: EEPROM

Test Name

EEPROM

Description

I²C access/Magic nibble check

Groups: POST AUTO ENDLESS

Always

Availability

This test reads the first EEPROM cell over SMB and checks if bits 3..0 of this cell contain the magic nibble

0xE

.

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MENMON

3.5.4

USB

Table 14. MENMON – Diagnostic tests: USB

Test Name Description

USB0..USB5

USB device access / sector 0 access

Groups: NONAUTO ENDLESS

Always

Availability

The test performs a sector 0 read from the Flash disk without verifying the content of the sector.

Checks:

• USB control lines (Data- / Data+)

• Basic USB transfer

Does not check:

• IRQ signals

• Partition table or file system on disk

3.5.5

Hardware Monitor Test

Table 15. MENMON – Diagnostic tests: hardware monitor

Test Name

LM81

Description

LM81 basic access test

Groups: POST AUTO

Always

Availability

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3.5.6

RTC

Table 16. MENMON – Diagnostic tests: RTC

Test Name

RTC

Description

Quick presence test of RTC

RTC_X

Groups: POST AUTO

Extended test of RTC

Groups: NONAUTO ENDLESS

Always

Availability

Always

3.5.6.1

RTC Test

This is a quick presence test of the real-time clock (RTC) and is executed on POST.

Checks:

• Presence of RTC (I²C access)

Does not check:

• If RTC is running

• RTC backup voltage

3.5.6.2

Extended RTC Test

Checks:

• Presence (e.g. I²C access)

• RTC is running

Does not check:

• RTC backup voltage

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3.6

MENMON Configuration and Organization

3.6.1

Consoles

You can select the active consoles by means of system parameters con0..con3 and configure the console through parameters ecl, gcon, hdp and tdp. MENMON

commands CONS(-xxx) also give access to the console settings (see Chapter 3.7

MENMON Commands (page 56) ).

Table 17. MENMON – System parameters for console selection and configuration

Parameter

cbr (baud)

Baud rate of all UART consoles

(decimal) (default: 9600 baud, 8n1)

con0..con3

CLUN of console 0..3

CLUN=

0x00: disable

CLUN=

0xFF: Autoselect next available console

ecl

(alias)

Description

con0 is implicitly the debug console

9600

Default

con0: to-USB COM)

con1:

con2:

08 (UART-

00 (none)

00 (none)

con3:

00 (none)

0xFF

User

Access

Read/write

Read/write

Read/write

gcon hdp tdp

CLUN of attached network interface (hex)

CLUN=

0x00: none

CLUN=

0xFF: first available Ethernet

CLUN of graphics device to display boot logo

CLUN=

0x00: disable

CLUN=

0xFF: Autoselect first available graphics console

HTTP server TCP port (decimal)

0: don't start telnet server

-1: use default port 23 else: TCP port for telnet server

Telnet server TCP port (decimal)

0xFF (AUTO)

-1

-1

Read/write

Read/write

Read/write

0: don't start HTTP server

-1: use default port 80 else: TCP port for HTTP server

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3.6.2

MENMON Memory Map

3.6.2.1

MENMON Memory Address Mapping

Table 18. MENMON – Address map (full-featured mode)

Address Space

0x 0000 0000 .. 0000 1400

Size

5 KB

0x 0000 3000 .. 0000 3FFF

4 KB

0x 0000 4200 .. 0000 42FF

256 bytes

0x 0000 4300 .. 00FF FFFF

Nearly

16 MB

0x 01D0 0000 .. 01DF FFFF

2 MB

0x 01E0 0000 .. 01EF FFFF

1 MB

0x 01F0 0000 .. 01F1 FFFF

128 KB

0x 01F2 0000 .. 01F4 FFFF

128 KB

0x 01F5 0000 .. 01FE FFFF

0x 01FF 0000 .. 01FF FFFF

0x 0200 0000 .. End of RAM

640 KB

64 KB

Description

Exception vectors

MENMON parameter string

VxWorks bootline

Free

Heap2

Text + Reloc

Stack

Stack for user programs and operating system boot

Heap

Not touched for OS post mortem buffer i.e. VxWorks

WindView or MDIS debugs

(requires ECC to be turned off!)

Free or download area

3.6.2.2

Boot Flash Memory Map

Table 19. MENMON – Boot Flash memory map

Flash Offset CPU Address Size

0x 00 0000 0x FF00 0000 14 MB

(- 128 KB)

0x DE 0000 0x FFDE 0000 128 KB

0x E0 0000 0x FFE0 0000 1 MB

0x F0 0000 0x FFF0 0000 1 MB

Description

Available to user

System parameter section in boot

Flash (if useflpar system parameter is set to 1)

Secondary MENMON

Primary MENMON

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3.6.3

MENMON BIOS Logical Units

The following table shows fixed assigned CLUNs. All other CLUNs are used dynamically.

0x02

0x03

0x04

0x06

0x08

0x0A

0x10

0x11

0x12

0x2x

Table 20. MENMON – Controller Logical Units (CLUNs)

CLUN

0x40

0x41

MENMON BIOS

Name

ETHER0

ETHER1

ETHER2

USB

Description

Ethernet #0 (LAN-0)

Ethernet #1 (LAN-1)

Ethernet #2 (LAN-2)

USB controller

UART-to-USB COM MPC854X DUART channel #0

TOUCH Reserved for touch console

SATA0

SATA1

SATA2

SATA port 0 (routed to SSD Flash)

SATA port 1

SATA port 2

All other devices dynamically detected on PCI or

FPGA devices

Telnet console

HTTP monitor console

Table 21. MENMON – Device Logical Units (DLUNs)

CLUN/DLUN

0x06/0x00

0x10/0x00

0x11/0x00

0x12/0x00

MENMON

BIOS Name

USB

SATA0

SATA1

SATA2

USB controller

1

Description

Disk at SATA port 0 (onboard SSD Flash)

Disk at SATA port 1

Disk at SATA port 2

1

The actual disks can be selected through command USBDP, see also page 57 .

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3.6.4

System Parameters

System parameters are parameters stored in EEPROM. Some parameters are automatically detected by MENMON (such as CPU type and frequency). The parameters can be modified through the EE-xxx command via the command line.

3.6.4.1

Physical Storage of Parameters

Most parameters are stored in the 1024-byte serial EEPROM on the F50P.

If required, you can configure MENMON to store some strings in boot Flash rather than in EEPROM.

3.6.4.2

Start-up with Faulty EEPROM

If a faulty EEPROM is detected (i.e. the checksum of the EEPROM section is wrong), the system parameters will use defaults. The behavior is the same if the

EEPROM is blank. The default baud rate is 9600.

3.6.4.3

F50P System Parameters

Note: Parameters marked by "Yes" in section "Parameter String" are part of the

MENMON parameter string.

Table 22. MENMON – F50P system parameters – Autodetected parameters

Parameter

(alias)

ccbclkhz clun cons cpu cpuclkhz dlun flash0 fram0 immr mem0 mem1 memclkhz

Description

CCB clock frequency (decimal, Hz)

MENMON controller unit number that

MENMON used as the boot device

(hexadecimal)

Selected console. Set to name of first selected console

CPU type as ASCII string (e.g.

"MPC8548E")

CPU core clock frequency (decimal, Hz)

MENMON device unit number that

MENMON used as the boot device

(hexadecimal)

Flash size (decimal, kilobytes)

FRAM size (decimal, kilobytes)

Physical address of CCSR register block

RAM size (decimal, kilobytes)

Size of SRAM

1

(decimal, kilobytes)

Memory clock frequency (decimal, Hz)

Standard Default

Parameter

String

Yes

Yes

User

Access

Read-only

Read-only

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

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Parameter

(alias)

mm mmst nmac0/1/2 pciclkhz rststat usbdp

Description

Info whether primary or secondary

MENMON has been used for booting, either "smm" or "pmm"

Status of diagnostic tests, as a string

MAC address of Ethernet interface x

(0..n). Format e.g. "00112233445566".

Set automatically according to serial number of the board

PCI bus clock frequency = system input clock (decimal, Hz)

Reset status code as a string, see

Chapter 3.6.4.4 Reset Cause – Parameter rststat on page 55

USB boot device path in format

“bus>1st_port_no>…>last_port_no”

(e.g. “00>02>01” for USB bus = 0, port no. 1 = 2, port no. 2 = 1)

Standard Default

Parameter

String

Yes

User

Access

Read-only

Yes

Yes

Yes

Yes

Yes

Read-only

Read-only

Read-only

Read-only

Read-only

1

If implemented.

Table 23. MENMON – F50P system parameters – Production data

Parameter

(alias)

brd brdmod brdrev prodat repdat sernbr

Description

Board name

Board model "mm"

Board revision "xx.yy.zz"

Board production date MM/DD/YYYY -

-

-

-

Board last repair date MM/DD/YYYY

Board serial number

-

-

Standard Default

Parameter

String

Yes

Yes

User

Access

Read-only

Read-only

Yes

Yes

Yes

Yes

Read-only

Read-only

Read-only

Read-only

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Table 24. MENMON – F50P system parameters – MENMON persistent parameters

Parameter

(alias)

bsadr (bs) cbr (baud) con0..con3

eccsth ecl gcon hdp kerpar stdis stdis_XXX

Description

Bootstrapper address. Used when BO command was called without arguments. (hexadecimal, 32 bits)

Baudrate of all UART consoles (dec)

CLUN of console 0..3. (hex) (see Chapter 3.6.1 Consoles on page 48

)

ECC single-bit error threshold

CLUN of attached network interface

(hex)

CLUN of graphics screen (hex) (see

Chapter 3.6.1 Consoles on page 48 )

HTTP server TCP port (decimal)

Linux Kernel Parameters (399 chars max). Part of VxWorks bootline if usefl-

par=0. (400 chars max if useflpar=1)

ldlogodis mmstartup

(startup)

Disable load of boot logo (bool)

Start-up string

256 chars max if useflpar=0

512 chars max if useflpar=1

Disable ASCII banner on start-up

nobanner noecc

Do not use ECC even if board supports it (bool)

nspeed0/1/3

Speed setting for Ethernet interface

0..3.

Possible values: AUTO, 10HD, 10FD,

100HD, 100FD, 1000

Disable POST (bool)

Disable POST test with name XXX

(bool)

Standard Default

0

Parameter

String

No

User

Access

Read/write

9600

0xFF = auto

32

0xFF

0xFF = auto

-1

Empty string

0

Empty string

0

0

AUTO

0

0

Yes

No

No

No

No

No

No

No

No

No

No

Yes

No

No

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

stignfault stwait

stdis_ether – Internal ETHER0/1/2 loopback

stdis_fram – FRAM test

1

stdis_sram – SRAM test

2

stdis_touch – Touch controller test

Ignore POST failure, continue boot

(bool)

Time in 1/10 seconds to stay at least in

SELFTEST state (decimal)

0 = Continue as soon as POST has finished

1

30

No

No

Read/write

Read/write

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MENMON

Parameter

(alias)

tdp tries tto u00..u15

updcdis useflpar vmode wdt

Description

Telnet server TCP port (decimal)

Number of network tries

Minimum timeout between network retries (decimal, in seconds)

User parameters (hex, 16 bits)

Disable auto update check (bool)

Store kerpar and mmstartup parameters in boot Flash rather than in

EEPROM (bool)

Vesa Video Mode for graphics console

(hex)

Time after which watchdog timer shall reset the system after MENMON has passed control to operating system

(decimal, in 1/10 s)

If 0, MENMON disables the watchdog timer before starting the operating system.

Note: The F50P watchdog supports only the following values:

0: Disable watchdog timer

11: Short time-out (1.12 seconds)

260: Long time-out (26.0 seconds)

1

2

If FRAM is implemented.

If SRAM is implemented.

-1

20

0

Standard Default

Parameter

String

No

No

No

User

Access

Read/write

Read/write

Read/write

0x0000

0

0

0x0101

0 (disabled)

No

No

No

No

No

Read/write

Read/write

Read/write

Read/write

Read/write

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Table 25. MENMON – F50P system parameters – VxWorks bootline parameters

Parameter

(alias)

bf (bootfile) bootdev e (netip) g (netgw) h (nethost) hostname netaddr netsm

Description

Boot file name (127 chars max)

VxWorks boot device name

IP address, subnet mask, e.g.

192.1.1.28:ffffff00

IP address of default gateway

Host IP address (used when booting over NBOOT TFTP)

VxWorks name of boot host

Access the IP address part of netip parameter

Access the subnet mask part of netip parameter

procnum s

VxWorks processor number (decimal)

VxWorks start-up script

tn (netname)

Host name of this machine

unitnum

VxWorks boot device unit number (decimal)

Standard Default

Empty string

Empty string

Empty string

Empty string

Empty string

Empty string

0

Empty string

Empty string

0

No

No

No

No

No

No

No

No

No

Parameter

String

No

No

No

User

Access

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

Read/write

3.6.4.4

Reset Cause – Parameter rststat

The following rststat values are possible:

When MENMON starts up, it determines the reset cause and sets system parameter

rststat accordingly:

Table 26. MENMON – Reset causes through system parameter rststat

rststat Value

cbrst pwon swrst wdog

Description

Board was reset using the reset button

Power On

Board was reset by software (by means of the board’s reset controller).

Board was reset by watchdog timer unit

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MENMON

3.7

MENMON Commands

The following table gives all MENMON commands that can be entered on the F50P

MENMON prompt. You can call this list also using the H command.

Table 27. MENMON – Command reference

Command

.[<reg>] [<val>]

ACT [<addr>] [<size>]

ARP

B[DC<no>] [<addr>]

BIOS_DBG <mask> [net] | cons

<clun>

Description

Display/modify registers in debugger model

Execute a HWACT script

Dump network stack ARP table

Set/display/clear breakpoints

Set MENMON BIOS or network debug level, set debug console

BO [<addr>] [<opts>]

BOOTP [<opts>]

Call OS bootstrapper

Obtain IP config via BOOTP

C[BWLLNAX#] <addr> [<val> ...] Change memory

CHAM [<clun>] Dump FPGA Chameleon table

CONS Show active consoles

CONS-ACT <clun1> [<clun2>] ...

Test console configuration

CONS-BAUD <baud>

CONS-GX <clun>

Change baud rate instantly without storing

Test graphics console

D [<addr>] [<cnt>] Dump memory

DBOOT [<clun>] [<dlun>] [<opts>] Boot from disk

DCACHE OFF | ON

DIAG [<which>] [VTF]

Enable/disable data cache

Run diagnostic tests

DSKRD <args>

DSKWR <args>

EE[-xxx] [<arg>]

EER[-xxx] [<arg>]

Read blocks from RAW disk

Write blocks to RAW disk

Persistent system parameter commands

Raw serial EEPROM commands

ERASE <D> [<O>] [<S>]

FI <from> <to> <val>

GO [<addr>]

H

HELP

I [<D>]

ICACHE OFF | ON

IOI

LM81

LOGO

LS <clun> <dlun> [<opts>]

Erase Flash sectors

Fill memory (byte)

Jump to user program

Print help

List board information

Enable/disable instruction cache

Scan for BIOS devices

Show current voltage and temperature values

Display MENMON start-up text screen

List files/partitions on device

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MENMON

Command

MC <addr1> <addr2> <cnt>

MII <clun> [<reg>] [<val>]

MO <from> <to> <cnt>

MS <from> <to> <val>

MT [<opts>] <start> <end>

[<runs>]

NBOOT [<opts>]

NDL [<opts>]

NETSTAT

PCI

PCIC <dev> <addr> [<bus>]

[<func>] [<val>]

PCID[+] <dev> [<bus>] [<func>]

PCIR

PCI-VPD[-] <devNo> [<busNo>]

[<capId>]

PFLASH <D> <O> <S> [<A>]

PGM-XXX <args>

PING <host> [<opts>]

RELOC

RST

RTC[-xxx] [<arg>]

S [<addr>]

SERDL [<passwd>]

SETUP

UNZIP src size [<opt>] [<dest>]

[<size>]

USB [<bus>]

USBT [<bus> <p1>..<p5>]

USBDP [<bus p1..p5>] [-d<x>]

Description

Compare memory

Ethernet MII register command

Move (copy) memory

Search pattern in memory

Memory test

Boot from network

Update Flash from network

Show current state of networking parameters

PCI probe

PCI config register change

PCI config register dump

List PCI resources

PCI Vital Product Data dump

Program Flash

Media copy tool

Network connectivity test

Relocate MM to RAM

Cause an instant system reset

Real time clock commands

Single step user program

Update Flash using YModem protocol

Open interactive Setup menu

Unzip memory zipped by gzip

Init USB controller and devices on a USB bus

Shows the USB device tree

Display/modify USB device path

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Organization of the Board

4 Organization of the Board

To install software on the board or to develop low-level software it is essential to be familiar with the board’s address and interrupt organization.

4.1

Memory Mappings

Table 28. Memory map – processor view

CPU Address Range Size

0x 0000 0000..End of RAM 512/1024/

2048 MB

0x 8000 0000..DFFF FFFF

1536 MB

0x E000 0000..E7FF FFFF

128 MB

0x E800 0000..EFFF FFFF

128 MB

0x F000 0000..F00F 0000

128 MB

0x F200 0000..F200 3FFF

0x F300 0000..F301 FFFF

0x F400 0000..F41F FFFF

0x FB00 0000..FBFF FFFF

16 MB

0x FC00 0000..FC00 7FFF

32 KB

0x FF00 0000..FFFF FFFF

16 MB

SDRAM

Description

PCIe Memory Space

PCI1 Memory Space

PCI2 Memory Space

CCSR

Config PLD

FRAM (opt.)

SRAM (opt.)

PCIe I/O / ISA Space

PCI1 I/O Space

Flash

Table 29. Address mapping for PCI

CPU Address Range Interface

0x 8000 0000..9FFF FFFF PCIe

0x A000 0000..DFFF FFFF PCIe

0x E000 0000..E7FF FFFF PCI1

0x E700 0000..EFFF FFFF PCI2

0x FB00 0000..FBFE FFFF PCIe

0x FBFF 8000..FBFF FFFF

0x FC00 0000..FC00 7FFF

PCIe

PCI1

1

Mapped to PCI Space

0x 8000 0000..9FFF FFFF

(MEM)

0x A000 0000..DFFF FFFF

(MEM)

Description

PCIe memory space

(prefetchable BARs)

PCIe memory space

(non-prefetchable

BARs)

PCI1 memory space

0x E000 0000..E7FF FFFF

(MEM)

0x E700 0000..EFFF FFFF

(MEM)

0x 0000 0000..00FE FFFF

(ISA)

0x 0000..7FFF (I/O)

0x 8000..FFFF (I/O)

PCI2 memory space

PCIe ISA memory

PCIe I/O space

PCI1 I/O space

1

PCI2 not available for MPC8543.

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Organization of the Board

4.2

Interrupt Handling

Interrupt handling is done via the 12 external interrupt lines of the CPU

(IRQ[11:0]). While the IRQ lines 8 to 10 are used as PCI interrupt lines (see Table

31, Interrupt numbering assigned by MENMON, on page 59 ), the Ethernet function

unit interrupt is routed to a dedicated interrupt line. The mapping is as follows:

Table 30. Dedicated interrupt line assignment

MPC854X IRQ Input

IRQ0 Ethernet

Function

Table 31. Interrupt numbering assigned by MENMON

MPC854X IRQ

Input

IRQ0

IRQ1

IRQ2

IRQ3

IRQ8

IRQ9

IRQ10

PCI Interrupt

Line

PCIe_INTA

PCIe_INTB

PCIe_INTC

PCIe_INTD

PCI_INTA

PCI_INTB

PCI_INTC

-

FPGA

-

-

SATA

Function

1st USB Controller

(USB0/2)

2nd USB Controller

(USB3/4/5)

Assigned Number

(MENMON)

0xF0

0xF1

0xF2

0xF3

0x8

0x9

0xA

4.3

SMB Devices

Table 32. SMB devices

I²C Bus Address

0x0 0x5E

0xA2

0xA8

0x1

0xD2

0xAC

LM81 hardware monitor

Real-time clock

CPU EEPROM

Clock generator

ID EEPROM

Function

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Organization of the Board

4.4

Onboard PCI Devices

Table 33. Onboard PCI devices

Interface Bus Device Vendor ID Device ID

PCI1

0x00 0x00 0x1057 0x0013

PCI2

0x10

0x01 0x00

0x1095

0x1057

0x3114

0x0013

PCIe

0x11

0x12

0x02 0x00

0x03 0x00

0x1033

0x1957

0x12D8

0x12D8

0x0035/

0x00E0

0x0013

0x0404

0x0404 0x04 0x01

0x02

0x03

0x05 0x00

0x06 0x00

0x1A88

0x12D8

0x4D45

0xE110

SATA

Function

PCI host bridge in MPC854X

PCI host bridge in MPC854X

1st USB Controller (USB0/2)

-

Interrupt

PCI_INTA (IRQ8)

-

PCI_INTB (IRQ9)

2nd USB Controller (USB3/4/5) PCI_INTC (IRQ10)

PCIe bridge in MPC854X

PCIe switch for CompactPCI bus

-

-

FPGA (if implemented) PCIe_INTB (IRQ 1)

PCIe bridge (CompactPCI bus) -

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Appendix

5 Appendix

5.1

Literature and Web Resources

• F50P data sheet with up-to-date information and documentation: www.men.de/products/02F050P.html

5.1.1

PowerPC

• MPC8548:

MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual

MPC8548ERM; 2007; Freescale Semiconductor, Inc.

www.freescale.com

5.1.2

SATA

• Serial ATA International Organization (SATA-IO) www.serialata.org

5.1.3

USB

• USB:

Universal Serial Bus Specification Revision 1.0; 1996; Compaq, Digital Equipment Corporation, IBM PC Company, Intel, Microsoft, NEC, Northern Telecom www.usb.org

5.1.4

Ethernet

• ANSI/IEEE 802.3-1996, Information Technology - Telecommunications and

Information Exchange between Systems - Local and Metropolitan Area Networks - Specific Requirements - Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications;

1996; IEEE www.ieee.org

• Charles Spurgeon's Ethernet Web Site

Extensive information about Ethernet (IEEE 802.3) local area network (LAN) technology.

www.ethermanage.com/ethernet/

• InterOperability Laboratory, University of New Hampshire

This page covers general Ethernet technology.

www.iol.unh.edu/services/testing/ethernet/training/

5.1.5

CompactPCI

• CompactPCI Specification PICMG 2.0 R3.0:

1999; PCI Industrial Computers Manufacturers Group (PICMG) www.picmg.org

• PCI Local Bus Specification Revision 2.2:

1995; PCI Special Interest Group

P.O. Box 14070

Portland, OR 97214, USA www.pcisig.com

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Appendix

5.1.6

CompactPCI PlusIO

• CompactPCI PlusIO Specification PICMG 2.30 R1.0:

2009; PCI Industrial Computers Manufacturers Group (PICMG) www.picmg.org

• Introduction to CompactPCI PlusIO on Wikipedia: en.wikipedia.org/wiki/CompactPCI_PlusIO

5.2

Finding out the Board’s Article Number, Revision and

Serial Number

MEN user documentation may describe several different models and/or hardware revisions of the F50P. You can find information on the article number, the board revision and the serial number on two labels attached to the board.

Article number: Gives the board’s family and model. This is also MEN’s ordering number. To be complete it must have 9 characters.

Revision number: Gives the hardware revision of the board.

Serial number: Unique identification assigned during production.

If you need support, you should communicate these numbers to MEN.

Figure 5. Label giving the board’s article number, revision and serial number

Complete article number

Article No.:

02F050P00

Serial No.:

000001

Rev.

00.00.00

Serial number

Revision number

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