Gian Luca Bonato, Angel Bóveda and Olga Ripollés
Telettra Espaiia S.A.
Madrid - Spain
This paper describes the design and performance of a GaAs monolithic Low Noise Amplifier and
Mixer designed for use in communication systems in the 1.5 - 2.5 GHz frequency band. The low noise
amplifier uses a reactive serial feedback configuration and has a measured noise figure of 1.8 dB at
room temperature and an associated gain of 20 dB over the full bandwidth. The mixer IC uses an
active adder and a FET Mixer, including also an IF output buffer. It provides 9 dB conversion gain
without need of external bias networks. This was the first design step towards the integration of the
two circuit functions on a single chip.
Keywords: L-Band, Low Noise Amplifier, Mixer, Front-end
Recent developments in GaAs material technology and the parallel stabilization of manufacturing
processes are resulting in an increasing employement of MMIC as key circuits to reduce costs and to
improve performance in telecommunication systems. This paper describes the work we have developed
under a concrete application pull for the realization of suitable LNA and MIXER circuits to be
integrated in a front-end module for use in point to multipoint digital radio links. After the definition
of the final target, the design philosophy was directed to select suitable configurations for each circuit
and a consolidated process of 0.8 um MESFET gate length was chosen to guarantee the specified
global performance with low cost, high-yield devices. The good measurement results on the
demonstrators after the first processing iteration in the foundry gave us important information and the
necessary confidence to integrate the two functions on a single chip. The fabrication of this chip is
currently in progress as conclusive part of the front-end design.
The front-end module consists of a low noise amplifier and a FET mixer, and was designed to use a
band-pass external filter to reject out-of-band noise (Ref.1,2), as showed in fig.1.
- e a a
Gala = 20 d
МЕ = 1.7 db
E > 1 =
AF O—|
{from antenna)
GaAs chip
D () OL
Figure 1: Block diagram of the front end module.
A total gain conversion greater than 15 dB and a noise figure of about 2 dB were required. This meant
the design of a very low noise amplifier and of a mixer with positive gain conversion. Circuits were
designed using the circuit simulators Touchstone and Libra for linear and non-linear analysis
respectively (Ref.7). Measured FET S-parameters and equivalent circuits for passive elements were
used, including all parasitic effects. FET non-linear model parameters (Ref.8) were optimized by an
in-house software, fitting its DC curves and measured S-parameters at different operation bias points.
2.1.Low Noise Amplifier
Among diferent circuit topologies for a LNA (Ref.1-3), a lumped LC matching configuration was
selected as the most suitable to achieve low noise figure and a high gain with a relatively low power
consumption. This parameter, not very severe for our application, was taken into account for save
power in the remote units. Two stages of amplification using 600 um gate width FETs allowed a
predicted gain of more than 18 dB and a noise figure of about 1.6 dB (fig.5). Similar performance
could be obtained using FETs with larger gate width (900 um). In the first stage, besides lumped LC
elements for impedance matching , inductive series feedback at the source was employed to improve
amplifier input VSWR and noise figure (Ref.3). The drawback of reactively matching at L-band
frequency is the need of some monolithic spiral inductors with large inductance values. High
inductance can be obtained increasing the number of spiral turns, that is the total line length, but
degrading the real RF performance for the large influence of the parasitics, as well as the total MMIC
size. The value for all the spiral inductors employed in the MMICs was held below 10 nH, so
guaranteeing a resonant frequency greater than 5 GHz and consequently the accuracy of the MMIC
design in the interest frequency band. The loss of the input matching network adversely affect the
amplifier noise figure performance, so that serie parasitic resistance of the inductors had to be
minimized in first stage, increasing the spiral line width. As a consequence, bigger size inductors are
clearly visible in the first stage matching circuit (see chip photograph in fig.2).
Figure 2: Circuit diagram and photograph of the LNA chip.
The second stage, designed to have gain increasing with frequency, compensates the opposite
behaviour of the first one to obtain an equalized amplifier gain. The using of resistors in the matching
networks of the second stage is not a problem, because here the signal has already been amplified, and
their contribution to the global noise figure is negligible. Fig.2 shows the complete circuit diagram
and the photograph of the Low Noise Amplifier. The chip size is 1.65 x 1.63 mm”.
As mixing element a 0.8 x 600 um Single-Gate FET was chosen. Its square law characteristic can be
applied to frequency conversion. Several configurations are available to supply LO and RF power to
the device. We decided to implement a gate FET configuration applying both the RF and LO power
across the gate (Ref.4). The large signal LO linearly modulates the trasconductance (g,) of the device
so that, when a small signal RF is applied simultaneously, the drain current is proportional to their
product. To get the maximum conversion efficiency, the FET should be biased at the point where the
derivative of the transconductance is maximum. This point is close to the pinch-off of the FET. A
filter consisting of a capacitor eliminates the sum of frequencies signal, the LO and the RF, so only
the frequency difference signal -the IF- remains. An input matching network composed of two
inductors grounds any spurious signals or noise at the IF frequency. It is placed at the gate of the
mixer FET to match its input impedance with the active adder output and to equalize the conversion
gain. The active adder combines the RF and LO signals (Ref.5). It consists of two common-gate drain
connected FETs, presenting at their source an input impedance equal to 1/g,, where g_ is the
transconductance of the FET. Choosing an appropriate gate width and biasing the FET so g_=20mS,
this impedance will be 50 ©. The active adder, besides giving a good input matching, provides
isolation between the RF and the LO ports because of the unilateral behaviour of the transistors. A
DC-coupled source-follower output stage is used to amplify the IF signal and as impedance buffer to
guarantee an output impedance close to 50 Q at IF frequency. Fig.3 shows the circuit diagram and a
photograph of the device. The chip size is 1.2 x 0.95 mm?.
Figure 3: Circuit diagram and photograph of the Mixer chip
2.2.1.Mixer Biasing
In order to achieve a small chip area, a full active bias is used for mixer circuit. The current is
injected to the source of common-gate (active adder) and common-drain (buffer) FETs by FETs
working as current sources. To avoid the stability problems at DC of the conventional active loads,
frequency dependent active loads (Ref.6) have been used for the rest of the circuit. At high frequency,
the capacitor between gate and source of the load behaves as a short circuit, so the FET presents Rı,
as source impedance. At DC, the FET behaves as a source-follower stage and the impedance shown
at the source is 1/g,, much lower than R,. This allows to use the network as frequency choke and
at the same time to maintain fixed its source DC voltage to the value applied at its gate, without being
affected by changes in LO power across the device, or by parameters spread of the process.
MMICs were fabricated using a funded selfaligned processing technique called DIOM (Double
Implantation One Metallization) (Ref.9) with a gate length of 0.8 um. The use of via-holes was
avoided to achieve a better fabrication yield. Airbridge technology was also available for MMIC's
layout design. The chips are provided of large ground pads for multiple ground connections.
4.1.Lna Performance
The LNA circuits were characterized on chip with cascade probes and on bench by suitable testing
jigs. For cascade measurement the circuits were attached to a metal plate by epoxy resin, the bias
being applied to the relevant pads through wire bondings to 100 pF bypass capacitors connected by
pointed probes to the bias supply. The test was carried out under different current bias conditions for
each amplifier stage to determine the optimum D.C. bias points. A gain of 20 dB and a noise figure
below 1.8 dB, a little worse than the predicted one, were achieved. Simulation results and on chip
measurements are compared in fig.4. S11 and S22 parameters are showed in fig.5. Similar
performance were obtained on bench with the assembled testing jigs.
HP8970B Noise Fi Meter
35. 00
ВЕ m 5-000
-E/DIV )
E “An
: 3, LULU
3100 10. 00
FdB (0.350 /DIV)
45.00 1.500 -15, ON
2.000 FREG-GHZ 3.000 1000 FREQ. ( 200.0 MHz/DIV ) 3000
Figure 4: Simulated and measured gain and noise figure of the LNA.
REF @ dB REF @ dB
5 dB 5 dB-
STOP 4.83 GHz STOP 4.03 GHz
Figure 5: S11 and $22 measured parameters (5 samples).
4.2 Mixer Performance
For the mixer circuit cascade measurement was not possible owing to chip dimensions which required
not conventional GSG probeheads and a special needle card for bias supply. The circuit was mounted
on a testing jig (fig.6) and tested in the whole RF bandwidth at different IF frequencies (from 30 to
100 MHz). The necessary local oscillator power for maximum efficiency is between -5 and 0 dBm.
The input matching at the LO and RF ports is better than -15 dB over the full bandwidth. The output
impedance at the IF ports is also close to 50 ©. The RF to LO isolation is of about 20 dB all over the
band, demonstrating the good operation of the active adder (Fig.7). Fig.8 shows the conversion gain
and noise figure versus RF frequency compared to simulation for a fixed IF of 70 MHz. The
conversion gain decrease at higher IF frequencies due to the RF filter capacitors.
S12 log MAG
REF 0.0 de
10.0 dB/
START 1. 000000000 GH:
STOP 3.000000000 GHz
Figure 6: Mixer testing jig photograph Figure 7: LO to RF isolation measurement
9 um HP89708 Noise Fi Meter
R£ 22.00 15. 00
15. 00
Ss =
e 8
= o
0. 000 _ oi
SB =
= =
ne 12.00 -15. 00
2. 800 FREG-GHZ 1300 FREQ. ( 300.0 MHz/DIV ) 4300
Figure 8: Mixer simulation and measurement comparison
4.3.Low Noise Converter Performance
To evaluate the global performance, measurements of the whole front-end module were carried out
connecting in serie LNA and Mixer testing jigs. A total gain conversion of 29 dB an SSB noise figure
of 2.4 dB could be obtained (fig.9).
HP8970B Noise Fi Mater
7.000 40. 00
чи >
e ©
2 ®
с =
— ui
о =
Lie <
2. 000 -10. 00
1300 FREQ. ( 200.0 MHz/DIY ) 3300
Figure 9: LNC gain conversion and noise figure
Two MMICs, a Low Noise Amplifier and a Mixer, were developed for L-Band low noise applications.
The LNA showed a noise figure lower than 1.8 dB with an associated gain of 20 dB. The MIXER
showed a positive gain conversion of 9 dB. These performance were obtained using a low-cost 0.8
pm MESFET process.
The authors wish to acknowledge the contribution of Siemens Semiconductor Group for its effort
during design and fabrication of the MMICs. They would also like to thank Telettra GaAs and
packaging laboratories for their help in the devices measuring and assembly.
This work has been supported by the European Strategic Programme for Research and Development
in Information Technology (ESPRIT) under Project No. 5018.
[1] Y. Imai et al. "Design and performance of low current GaAs MMICs" IEEE Transaction on
Microwave Theory and Techniques Vol.39 n.2 pp 209-215, Feb 1991
[2] 1990-1991 EC ESPRIT Reports from Project 5018
[3] J .Enberg. "Symultaneous Input Power Match and Noise Optimization Using Feedback".
European Microwave Conference Digest 1974, pp 385-389.
[4] S.A. Maas. "Microwave Mixers" Artech House, INC. 19
[5] R.S. Pengelly "Microwave field effect transistors - Theory, design and applications" Wiley and
Sons INC. 1986
[6] V. Pauker & M. Binet "Wide high gain small size monolithic GaAs FET amplifiers" IEEE
MTT-S Digest 1983, pp50-53
[7] Touchstone & Libra "User's manual" version 3.0 EESOF Inc.1990
[8] W.R. Curtice "A mesfet model for use in the design of GaAs integrated circuits" IEEE
Transaction on Microwave Theory and Techniques Vol.28 n.5 pp 448-455, May 1980
[9] E. Pettenpaul "State of the art of MMIC Technology and design in West- Germany" IEEE MTT-
$ Digest 1987, pp.763-766
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