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TPA3112D1 www.ti.com
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
25-W FILTER-FREE MONO CLASS-D AUDIO POWER AMPLIFIER with SPEAKER GUARD™
Check for Samples: TPA3112D1
1
FEATURES
2
• 25-W into an 8-
Ω
Load at < 0.1% THD+N From a 24-V Supply
• 20-W into an 4-
Ω
Load at 10% THD+N From a
12-V Supply
• 94% Efficient Class-D Operation into 8-
Ω
Load
Eliminates Need for Heat Sinks
• Wide Supply Voltage Range Allows Operation from 8 to 26 V
• Filter-Free Operation
• SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter plus DC Protection
• Flow Through Pin Out Facilitates Easy Board
Layout
• Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection with Auto-Recovery Option
• Excellent THD+N/ Pop Free Performance
• Four Selectable, Fixed Gain Settings
• Differential Inputs
DESCRIPTION
The TPA3112D1 is a 25-W efficient, Class-D audio power amplifier for driving a bridge tied speaker.
Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard™ speaker protection system includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a
"virtual" voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.
The TPA3112D1 can drive a mono speaker as low as
4 Ω . The high efficiency of the TPA3112D1, > 90%, eliminates the need for an external heat sink when playing music.
The outputs are fully protected against shorts to
GND, V
CC
, and output-to-output. The short-circuit protection and thermal protection includes an autorecovery feature.
APPLICATIONS
• Televisions
• Consumer Audio Equipment
1uF
Audio
Source
OUT+
OUT -
INP
INN
TPA3112D1
25W
PVCC
Figure 1. Simplified Application Diagram
8 to 26V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SpeakerGuard, PowerPad are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
TPA3112D1
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
V
V
T
T
T
R
CC
I
A
J stg
L
Supply voltage AVCC, PVCC
SD, FAULT,GAIN0, GAIN1, AVCC (Pin 14)
Interface pin voltage
PLIMIT
INN, INP
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
(2)
Storage temperature range
Minimum Load Resistance
Electrostatic discharge
BTL
Human body model
(3)
(all pins)
Charged-device model
(4)
(all pins)
UNIT
–0.3 V to 30 V
–0.3 V to V
CC
+ 0.3 V
< 10 V/ms
–0.3 V toGVDD + 0.3 V
–0.3 V to 6.3 V
See Thermal Inforamtion Table
–40°C to 85°C
–40°C to 150°C
–65°C to 150°C
3.2
±2 kV
±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3112D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method C101-A
THERMAL INFORMATION
θ
JA
θ
JCtop
θ
JB
ψ
JT
ψ
JB
θ
JCbot
THERMAL METRIC
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
(1) (2)
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TPA3112D1
PWP (28 PINS)
30.3
33.5
17.5
0.9
7.2
0.9
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator
2
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Copyright © 2009–2012, Texas Instruments Incorporated
TPA3112D1 www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
I
IH
I
IL
T
A
V
CC
V
IH
V
IL
V
OL
PARAMETER
Supply voltage
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level input current
Low-level input current
Operating free-air temperature
TEST CONDITIONS
PVCC, AVCC
SD, GAIN0, GAIN1
SD, GAIN0, GAIN1
FAULT, R
PULLUP
=100k Ω , V
CC
=26V
SD, GAIN0, GAIN1, V
I
= 2, V
CC
= 18 V
SD, GAIN0, GAIN1, V
I
= 0.8V, V
CC
= 18 V
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
DC CHARACTERISTICS
T
A
= 25°C, V
CC
= 24 V, R
L
= 8 Ω (unless otherwise noted)
| V
OS
|
I
CC
I
CC(SD)
PARAMETER TEST CONDITIONS
Class-D output offset voltage (measured differentially)
V
I
= 0 V, Gain = 36 dB
Quiescent supply current SD = 2 V, no load, PVcc=21V
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=21V r
DS(on)
G
Drain-source on-state resistance
Gain
I
O
T
J
= 500 mA,
= 25°C
GAIN1 = 0.8 V
GAIN1 = 2 V
High Side
Low side
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V t
ON t
OFF
GVDD
Turn-on time
Turn-off time
Gate Drive Supply
SD = 2 V
SD = 0.8 V
I
GVDD
= 2mA
MIN
8
2
–40
MAX UNIT
26 V
0.8
0.8
V
V
50
5
85
V
µA
µA
°C
MIN TYP MAX UNIT
1.5
15 mV
19
25
31
35
6.5
40
400
240
240
20
26
32
36
10
2
6.9
7.3
21
27
33
37 mA
µA m Ω dB dB ms
μ
V s
DC CHARACTERISTICS
T
A
= 25°C, V
CC
= 12 V, R
L
= 8
Ω
(unless otherwise noted)
PARAMETER
| V
OS
|
I
CC
I
CC(SD)
TEST CONDITIONS
Class-D output offset voltage (measured differentially)
V
I
= 0 V, Gain = 36 dB
Quiescent supply current SD = 2 V, no load, PVcc=12V
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=12V r
DS(on)
Drain-source on-state resistance
I
O
T
J
= 500 mA,
= 25°C
High Side
Low side
G Gain t
ON t
OFF
Turn-on time
Turn-off time
GVDD Gate Drive Supply
PLIMIT Output Voltage maximum under PLIMIT control
GAIN1 = 0.8 V
GAIN1 = 2 V
SD = 2 V
SD = 0.8 V
I
GVDD
= 2mA
V
PLIMIT
=2.0 V; V
I
=6.0V differential
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
MIN TYP MAX UNIT
1.5
15 mV
19
25
31
35
20
26
32
36
10
20
200
240
240
2
6.5
6.9
7.3
6.75
7.90
8.75
21
27
33
37 mA
µA m Ω dB dB ms
μ
V
V s
Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s):
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TPA3112D1
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
AC CHARACTERISTICS
T
A
= 25°C, V
CC
= 24 V, R
L
= 8 Ω (unless otherwise noted)
K
SVR
PARAMETER
Power Supply ripple rejection
TEST CONDITIONS
200 mV
PP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
P
O
Continuous output power
THD+N Total harmonic distortion + noise
THD+N ≤ 0.1%, f = 1 kHz, V
CC
= 24 V
V
CC
= 24 V, f = 1 kHz, P
O
= 12 W (half-power)
V n
Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
SNR f
OSC
Crosstalk
Signal-to-noise ratio
Oscillator frequency
Thermal trip point
Thermal hysteresis
V
O
= 1 Vrms, Gain = 20 dB, f = 1 kHz
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
AC CHARACTERISTICS
T
A
= 25°C, V
CC
= 12 V, R
L
= 8 Ω (unless otherwise noted)
K
SVR
PARAMETER
Supply ripple rejection
TEST CONDITIONS
200 mV
PP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
P
O
P
O
Continuous output power
Continuous output power
THD+N Total harmonic distortion + noise
THD+N ≤ 10%, f = 1 kHz , R
L
= 8 Ω
THD+N ≤ 10%, f = 1 kHz , R
L
= 4 Ω
R
L
= 8 Ω , f = 1 kHz, P
O
= 5 W (half-power)
V n
SNR f
OSC
Output integrated noise
Crosstalk
Signal-to-noise ratio
Oscillator frequency
Thermal trip point
Thermal hysteresis
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
P o
= 1 W, Gain = 20 dB, f = 1 kHz
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SD
FAULT
GND
GND
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
INN
INP
NC
AVCC
PWP (TSSOP) Package
(Top View)
3
4
5
1
2
6
11
12
13
14
7
8
9
10
18
17
16
15
22
21
20
19
28
27
26
25
24
23
PVCC
PVCC
BSN
OUTN
PGND
OUTN
BSN
BSP
OUTP
PGND
OUTP
BSP
PVCC
PVCC
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MIN TYP MAX UNIT
–70 dB
250
25
<0.05
65
–80
–70
102
310 350
150
15 kHz
°C
°C
W
%
µV dBV dB dB
MIN TYP MAX UNIT
250
–70
10
20
<0.06
65
–80
–70
102
310 350
150
15 dB kHz
°C
°C dB
W
W
%
µV dBV dB
4
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Copyright © 2009–2012, Texas Instruments Incorporated
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NAME
SD
PIN
FAULT
PLIMIT
BSP
BSN
OUTN
PGND
OUTN
BSN
PVCC
PVCC
INN
INP
NC
AVCC
PVCC
PVCC
BSP
OUTP
PGND
OUTP
GND
GND
GAIN0
GAIN1
AVCC
AGND
GVDD
Pin #
1
2
10
21
22
23
24
25
26
27
28
16
17
18
19
20
11
12
13
14
15
5
6
7
8
3
4
9
I
I
P
O
I
P
P
O
I
I
O
O
I
I
I
P
I
O
P
P
I/O
I
O
TPA3112D1
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
PIN FUNCTIONS
DESCRIPTION
Shutdown logic input for audio amp(LOW = outputs Hi-Z, HIGH = outputs enabled).
TTL logic levels with compliance to AVCC.
Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting
FAULT pin to SD pin. Otherwise both the short circuit faults and dc detect faults must be reset by cycling PVCC.
Connect to local ground
Connect to local ground
Gain select least significant bit. TTL logic levels with compliance to AVCC.
Gain select most significant bit. TTL logic levels with compliance to AVCC.
Analog supply.
Analog supply ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 7V. May also be used as supply for PLILMIT divider. Add a 1 μ F cap to ground at this pin.
Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a
1 μ F cap to ground at this pin.
Negative audio input. Biased at 3V.
Positive audio input. Biased at 3V.
Not connected
Connect AVCC supply to this pin
Power supply for H-bridge. PVCC pins are also connected internally.
Power supply for H-bridge. PVCC pins are also connected internally.
Bootstrap I/O for positive high-side FET.
Class-D H-bridge positive output.
Power ground for the H-bridges.
Class-D H-bridge positive output.
Bootstrap I/O for positive high-side FET.
Bootstrap I/O for negative high-side FET.
Class-D H-bridge negative output.
Power ground for the H-bridges.
Class-D H-bridge negative output.
Bootstrap I/O for negative high-side FET.
Power supply for H-bridge. PVCC pins are also connected internally.
Power supply for H-bridge. PVCC pins are also connected internally.
Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s):
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TPA3112D1
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAM
www.ti.com
OUTP FB
FAULT
SD
GAIN0
GAIN1
INP
INN
Gain
Control
OUTN FB
TTL
Buffer
Gain
Control
PLIMIT
AVDD
AVCC
LDO
Regulator
GVDD
GVDD
PLIMIT
Reference
PLIMIT
Ramp
Generator
Biases and
References
Startup Protection
Logic
SC Detect
DC Detect
Thermal
Detect
UVLO/OVLO
PWM
Logic
PVCC
GVDD
Gate
Drive
PVCC
Gate
Drive
GVDD
PVCC
BSP
OUTP FB
OUTP
PGND
PVCC
BSN
OUTN FB
OUTN
PGND
AGND
6
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TPA3112D1 www.ti.com
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
TYPICAL CHARACTERISTICS
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is available at ti.com.)
10
1
TOTAL HARMONIC DISTORTION vs
FREQUENCY
Gain = 20 dB
V
Z
CC
L
= 12 V
= 8
Ω
+ 66
µ
H
10
TOTAL HARMONIC DISTORTION vs
FREQUENCY
Gain = 20 dB
V
Z
CC
L
= 24 V
= 8
Ω
+ 66
µ
H
1
0.1
0.1
P
O
= 1 W
P
O
= 1 W
0.01
0.001
20
P
O
= 2.5 W
P
O
= 5 W
100 1k f − Frequency − Hz
Figure 2.
10
TOTAL HARMONIC DISTORTION vs
FREQUENCY
Gain = 20 dB
V
Z
CC
L
= 12 V
= 4
Ω
+ 33
µ
H
1
P
O
= 5 W
10k 20k
G001
0.1
P
O
= 10 W
0.01
P
O
= 10 W
P
O
= 5 W
0.001
20 100 1k f − Frequency − Hz
Figure 3.
10k 20k
G002
10
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
Gain = 20 dB
V
Z
CC
L
= 12 V
= 8
Ω
+ 66
µ
H
1 f = 1 kHz f = 20 Hz
0.1
0.01
P
O
= 1 W
0.001
20 100 1k f − Frequency − Hz
Figure 4.
0.01
10k 20k
G003
0.001
0.01
f = 10 kHz
0.1
1
P
O
− Output Power − W
Figure 5.
10 30
G004
Copyright © 2009–2012, Texas Instruments Incorporated
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TPA3112D1
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is available at ti.com.)
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
10 10
Gain = 20 dB
V
Z
CC
L
= 24 V
= 8
Ω
+ 66
µ
H
Gain = 20 dB
V
Z
CC
L
= 12 V
= 4
Ω
+ 33
µ
H
1 1 f = 1 kHz f = 20 Hz
0.1
0.1
f = 1 kHz f = 20 Hz
0.01
f = 10 kHz
0.001
0.01
0.1
1
P
O
− Output Power − W
Note: Dashed lines represent thermally limited region.
Figure 6.
10
30
25
MAXIMUM OUTPUT POWER vs
PLIMIT VOLTAGE
Gain = 20 dB
V
Z
CC
L
= 24 V
= 8
Ω
+ 66
µ
H
30
G005
20
15
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
PLIMIT
− PLIMIT Voltage − V
G007
Note: Dashed line represents thermally limited region.
Figure 8.
0.01
0.001
0.01
f = 10 kHz
0.1
1
P
O
− Output Power − W
Figure 7.
30
25
OUTPUT POWER vs
PLIMIT VOLTAGE
Gain = 20 dB
V
Z
CC
L
= 12 V
= 4
Ω
+ 33
µ
H
20
10 30
G006
15
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
PLIMIT
− PLIMIT Voltage − V
G008
Figure 9.
8
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SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is available at ti.com.)
GAIN/PHASE vs
FREQUENCY
EFFICIENCY vs
OUTPUT POWER
40
100
100
90
35
50
V
CC
= 24 V
30
Phase
0
80
70
V
CC
= 12 V
25
−50
60
Gain
20
−100
−150
50
40
15
10
5
0
10
C
I
= 1
µ
F
Gain = 20 dB
Filter = Audio Precision AUX-0025
V
CC
= 12 V
V
I
= 0.1 Vrms
Z
L
= 8
Ω
+ 66
µ
H
100 1k f − Frequency − Hz
10k
Figure 10.
−200
30
20
−250
−300
100k
G009
10
Gain = 20 dB
Z
L
= 8
Ω
+ 66
µ
H
0
0 5 10 15 20
P
O
− Output Power − W
Note: Dashed line represents thermally limited region.
Figure 11.
25 30
G012
EFFICIENCY vs
OUTPUT POWER
SUPPLY CURRENT vs
TOTAL OUTPUT POWER
100
90
80
70
60
50
40
30
V
CC
= 12 V
V
CC
= 24 V
1.2
1.0
0.8
0.6
0.4
Gain = 20 dB
Z
L
= 8
Ω
+ 66
µ
H
V
CC
= 12 V
V
CC
= 24 V
20
10
Gain = 20 dB
Z
L
= 4
Ω
+ 33
µ
H
0
0 5 10 15 20
P
O
− Output Power − W
Note: Dashed line represents thermally limited region.
Figure 12.
25 30
G013
0.2
0.0
0 5 10 15 20
P
O(Tot)
− Total Output Power − W
25
Note: Dashed line represents thermally limited region.
Figure 13.
30
G014
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SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3112D2 EVM which is available at ti.com.)
SUPPLY CURRENT vs
TOTAL OUTPUT POWER
SUPPLY RIPPLE REJECTION RATIO vs
FREQUENCY
1.8
0
1.6
Gain = 20 dB
V
Z
CC
L
= 12 V
= 4
Ω
+ 33
µ
H
−20
Gain = 20 dB
V
Z
CC
L
= 12 V
= 8
Ω
+ 66
µ
H
1.4
1.2
−40
1.0
0.8
0.6
0.4
0.2
0.0
0
−60
−80
−100
−120
20
5 10 15 20
P
O(Tot)
− Total Output Power − W
25
Figure 14.
30
G015
100 1k f − Frequency − Hz
Figure 15.
10k 20k
G016
DEVICE INFORMATION
Gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3112D1 is set by two input terminals, GAIN0 and GAIN1. The voltage slew rate of these gain terminals, along with terminals 1 and 14, must be restricted to no more than 10V/ms. For higher slew rates, use a 100k Ω resistor in series with the terminals.
The gains listed in
are realized by changing the taps on the input resistors inside the amplifier. This causes the input impedance (Z
I
) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 7.2 k Ω , which is the absolute minimum input impedance of the TPA3112D1. At the lower gain settings, the input impedance could increase as high as 72 k
Ω
GAIN1
1
1
0
0
Table 1. Gain Setting
GAIN0
0
1
0
1
AMPLIFIER GAIN (dB)
TYP
20
26
32
36
INPUT IMPEDANCE
(k Ω )
TYP
60
30
15
9
10
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SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
SD OPERATION
The TPA3112D1 employs a shutdown mode of operation designed to reduce supply current (I
CC
) to the absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage.
PLIMIT
The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Also add a 1 μ F capacitor from pin 10 to ground.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is 4 times the voltage at the
PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
TPA3112D1 PLimit Operation
Figure 16. PLIMIT Circuit Operation
The PLIMIT circuits sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to fixed maximum value. This limit can be thought of as a “virtual” voltage rail which is lower than the supply connected to PVCC. This “virtual” rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
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SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
P
OUT
=
æ
ç
æ
ç
è
R
L
R
L
R
S
ö
÷
ø
´
V
P
ö
2
÷
2
´
R
L for unclipped power
Where:
R
S
R
L is the total series resistance including R
DS(on)
, and any resistance in the output filter.
is the load resistance.
V
P is the peak amplitude of the output possible within the supply rail.
V
P
= 4 × PLIMIT voltage if PLIMIT < 4 × V
P
P
OUT
(10%THD) = 1.25 × P
OUT
(unclipped)
Table 2. PLIMIT Typical Operation
PLIMIT Voltage
6.97
Output Power (W)
22.1
Output Voltage
Amplitude (V
P-P
)
26.9
Test Conditions ()
PVCC=24V, Vin=1Vrms,
RL=4 Ω , Gain=20dB
PVCC=24V, Vin=1Vrms,
RL=4 Ω , Gain=20dB
PVCC=24V, Vin=1Vrms,
RL=4 Ω , Gain=20dB
PVCC=12V, Vin=1Vrms,
RL=4 Ω , Gain=20dB
PVCC=12V, Vin=1Vrms,
RL=4 Ω , Gain=20dB
PVCC=12V, Vin=1Vrms,
RL=4
Ω
, Gain=20dB
1.92
1.24
6.95
1.75
1.20
10
5
17.2
10
5
15.0
10.0
20.9
15.3
10.3
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(1)
GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also used to supply the
PLIMIT voltage divider circuit. Add a 1 μ F capacitor to ground at this pin.
DC Detect
TPA3112D1 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential duty-cycle exceeds 14% (eg. +57%, -43%) for more than
420 ms at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2
Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative input to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are shown in Table
must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect.
Table 3. DC Detect Threshold
AV(dB)
20
26
32
36
Vin (mV, differential)
112
56
28
17
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SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE
TPA3112D2 has protection from over-current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This will allow the FAULT pin function to automatically drive the SD pin low which will clear the short circuit protection latch.
THERMAL PROTECTION
Thermal protection on the TPA3112D1 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT terminal.
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APPLICATION INFORMATION
PVCC
100 μF 0.1 μF
1000pF
Control
System
Audio
Source
PVCC
10 Ω
1 k Ω
AVCC
1 uF
1 uF
AVCC
1 uF
1 uF
100k Ω
100 kW
(1)
1
2
3
4
SD
FAULT
GND
GND
5
GAIN0
6
GAIN1
7
8
AVCC
TPA3112D1
AGND
9
GVDD
10
PLIMIT
11
INN
12
INP
13
NC
PVCC
28
PVCC
27
BSN
26
OUTN
25
PGND
24
OUTN
23
BSN
22
BSP
21
OUTP
PGND
OUTP
BSP
PVCC
20
19
18
17
16
14
AVCC
GND
PVCC
29
PowerPAD
15
PVCC
0.47 μF
0.47 μF
(1) 100 k Ω resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 17. Mono Class-D Amplifier with BTL Output
FB
FB
0.1 μF
1000 pF
1000 pF
1000pF
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CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3112D1.
SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
TPA3112D1 Modulation Scheme
The TPA3112D1 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I
2
R losses in the load.
OUTP
Differential
Voltage
Across
Load
OUTN
+12 V
0 V
-12 V
Current
Output = 0 V
OUTP
Differential
Voltage
Across
Load
OUTN
+12 V
0 V
-12 V
Output > 0 V
Current
Figure 18. The TPA3112D1 Output Voltage and Current Waveforms Into an Inductive Load
Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3112D1 amplifier it is possible to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. it is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter.
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One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at very low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable.
Examples of ferrite beads which have been tested and work well with the TPA3112D2 include 28L0138-80R-10 and HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to ground. Suggested values for a simple RC series snubber network would be 10 ohms in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPad™ beneath the chip.
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x V
CC
, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3112D1 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is V
CC instead of 2 x V
CC
. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression
The TPA3112D1 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3112D1 EVM passes FCC Class B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are circuits near which are sensitive to noise. Therefore, a classic second order Butterworth filter similar to those shown in
through
can be used.
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OUTP
33
m
H
L1
C2
1 mF
OUTN
33 mH
L2
C3
1 mF
Figure 19. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8
Ω
OUTP
15
m
H
L1
C2
2.2 mF
OUTN
15 mH
L2
C3
2.2 mF
Figure 20. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4
Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 21. Typical Ferrite Chip Bead Filter (Chip Bead Example: Steward HI0805R800R-10)
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INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 k Ω ±20%, to the largest value, 60 k Ω ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps.
Z f
C i
Z i
Input
Signal
IN
The -3-dB frequency can be calculated using
. Use the Z
I
1 f =
2 p
Z C i i values given in
.
(2)
INPUT CAPACITOR, C
I
In the typical application, an input capacitor (C
I
) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C
I and the input impedance of the amplifier (Z
I
) form a highpass filter with the corner frequency determined in
-3 dB f = c
1
2
p
Z C i i f c
(3)
The value of C
I is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where Z
I is 60 k Ω and the specification calls for a flat bass response down to 20 Hz.
is reconfigured as
.
1
C = i
2 p
Z f i c
(4)
In this example, C
I is 0.13 µF; so, one would likely choose a value of 0.15
the gain is known and is constant, use Z
I from
to calculate C
I
μ F as this value is commonly used. If
. A further consideration for this capacitor is the leakage path from the input source through the input network C
I
) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. If a ceramic capacitor is used, use a high quality capacitor with good temperature and voltage coefficient. An X7R type works well and if possible use a higher voltage rating than required. This will give a better C vs voltage characteristic. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly.
POWER SUPPLY DECOUPLING, C
S
The TPA3112D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
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SLOS654C – SEPTEMBER 2009 – REVISED JULY 2012
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-seriesresistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to the device PVCC pins and system ground (either PGND pins or PowerPad) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality capacitor typically 0.1 mF to 1 μ F placed as close as possible to the device PVCC leads works best For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 mF or greater placed near the audio power amplifier is recommended. The 220 mF capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220 μ F or larger capacitor should be placed on each
PVCC terminal. A 10 μ F capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between
AVCC and PVCC can be used to keep high frequency class D noise from entering the linear input amplifiers.
BSN and BSP CAPACITORS
The full H-bridge output stage uses only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 470-nF ceramic capacitor, rated for at least 16 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 470-nF capacitor must be connected from OUTP to BSP, and one 470-nF capacitor must be connected from OUTN to BSN. (See the application circuit diagram in
.)
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.
DIFFERENTIAL INPUTS
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3112D1 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3112D1 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 14 msec power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.
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PRINTED-CIRCUIT BOARD (PCB) LAYOUT
The TPA3112D1 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are very fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (220 μ F or greater) bulk power supply decoupling capacitors should be placed near the TPA3112D1 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220 pF and 1000 pF and a larger mid-freqency cap of value between 0.1mF and 1mF also of good quality to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
• Output filter—The ferrite EMI filter should be placed as close to the output terminals as possible for the best
EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows of solid vias (three vias per row, 0.33 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See TI Application Report
SLMA002 for more information about using the TSSOP thermal pad.
For an example layout, see the TPA3112D1 Evaluation Module (TPA3112D1EVM) User Manual. Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com
.
SPACER
REVISION HISTORY
Changes from Original (September 2009) to Revision A Page
• Added slew rate adjustment information .............................................................................................................................
• Added updates for
Changes from Revision A (July 2010) to Revision B Page
• In the BSN and BSP CAPACITORS section, the 220-nf capacitor rated for at least 25V was changed to a 470-nf capacitor rated to at least 16V ............................................................................................................................................
Changes from Revision B (August 2010) to Revision C Page
• Added < 10 V/ms to V
I in the Absolute Maximum Ratings table ..........................................................................................
• Added a 100k Ω resistor to AVCC Pin 14 and Note 1 to
....................................................................................
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PACKAGE OPTION ADDENDUM
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17-Mar-2012
PACKAGING INFORMATION
Orderable Device
Status
(1) Package Type Package
Drawing
Pins Package Qty
Eco Plan
(2) Lead/
Ball Finish
MSL Peak Temp
(3) Samples
(Requires Login)
TPA3112D1PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPA3112D1PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
14-Jul-2012
*All dimensions are nominal
Device
TPA3112D1PWPR
Package
Type
Package
Drawing
HTSSOP PWP
Pins
28
SPQ
2000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
16.4
A0
(mm)
6.9
B0
(mm)
10.2
K0
(mm)
P1
(mm)
1.8
12.0
W
(mm)
Pin1
Quadrant
16.0
Q1
Pack Materials-Page 1
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PACKAGE MATERIALS INFORMATION
14-Jul-2012
*All dimensions are nominal
Device
TPA3112D1PWPR
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
2000
Length (mm) Width (mm) Height (mm)
367.0
367.0
38.0
Pack Materials-Page 2
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Table of contents
- 1 FEATURES
- 1 APPLICATIONS
- 1 DESCRIPTION
- 2 ABSOLUTE MAXIMUM RATINGS
- 2 THERMAL INFORMATION
- 3 RECOMMENDED OPERATING CONDITIONS
- 3 DC CHARACTERISTICS
- 3 DC CHARACTERISTICS
- 4 AC CHARACTERISTICS
- 4 AC CHARACTERISTICS
- 7 TYPICAL CHARACTERISTICS
- 10 DEVICE INFORMATION
- 10 Gain setting via GAIN0 and GAIN1 inputs
- 11 SD OPERATION
- 11 PLIMIT
- 12 GVDD Supply
- 12 DC Detect
- 13 SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE
- 13 THERMAL PROTECTION
- 14 APPLICATION INFORMATION
- 15 CLASS-D OPERATION
- 15 TPA3112D1 Modulation Scheme
- 15 Ferrite Bead Filter Considerations
- 16 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
- 16 When to Use an Output Filter for EMI Suppression
- 18 INPUT RESISTANCE
- 18 INPUT CAPACITOR, CI
- 18 POWER SUPPLY DECOUPLING, CS
- 19 In the BSN and BSP CAPACITORS section, the 220-nf capacitor rated for at least 25V was changed to a 470-nf capacitor rated to at least 16VBSN and BSP CAPACITORS
- 19 DIFFERENTIAL INPUTS
- 19 USING LOW-ESR CAPACITORS
- 20 PRINTED-CIRCUIT BOARD (PCB) LAYOUT
- 20 REVISION HISTORY