MICRO 3000 SELFTEST and MAINTENANCE MODE

MICRO 3000 SELFTEST and MAINTENANCE MODE
HP 3000 Computer Systems
MICRO 3000 SELFTEST and
MAINTENANCE MODE
Diagnostic Manual
8010 FOOTHILLS BLVD., ROSEVILLE, CA 95678
Part No. 30534-90001
E i 286
Printed in U. S. A. 12/86
NOTICE
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERiAL, iNCLUDiNG, BUT NOT LiMITED TO, THE IMPLIED WARRANTIES OF
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is not furnished by Hewlett -Packard.
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without the prior written consent of Hewlett-Packard Company.
Copyright © 1986 by HEWLETf-PACKARD COMPANY
PRINTING HISTORY
New editions are complete revisions of the manual. Update packages, which are issued between editions,
contain additional and replacement pages to be merged into the manual by the customer. The dates on
the title page change only when a new edition or a new update is published.
No information is
incorporated into a reprinting unless it appears as a prior update; the edition does not change when an
update is incorporated.
First Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dec 1986
DEC 86
111
LIST OF EFFECTIVE PAGES
The List of Effective Pages gives the date of the most recent version of each page in the manual.
To verify that your manual contains the most current information, check the dates printed at
the bottom of each page with those listed below. The date on the bottom of each page reflects
the edition or subsequent update in which that page was printed.
Effective Pages
Date
all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dec 1986
DEC 1986
iv
CONTENTS
Section I
GENERAL INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Required Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self test ROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Seiftest Executive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Remote Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
)-1
I-I
1- 2
i- 2
1- 2
1- 3
1- 4
Section 2
OPERA TING INSTRUCTIONS
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ...........
Keyswitch Capabilities. . . . . . . . . . . . . . . . . . . . . .
. ...........
Test Execution Time. . . . . . . . . . . . . . . . . . . . . . .
. ...........
Front Panel LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Self test Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . .
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Operator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Establishing the Remote Console Link . . . . . . . . . . . . . . . . . . , . , , .. , ..
Disconnecting the Remote Console Link . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-)
2-2
2-2
2- 3
2-4
2-6
2-6
2-7
2-7
Section 3
MAINTENANCE MODE COMMAND DESCRIPTIONS
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Warmstart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coldstart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cooistart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Newsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-1
3-1
3- 2
3- 2
3- 3
3-3
3-4
3-4
3- 5
3-5
3-6
3-6
3-6
DEC 86
v
I
CONTENTS (continued)
Speed . . . . . . .
Start. . . . . . . .
Tape . . . . . . . .
Test . . . . . . . .
Update . . . . . .
Warmstart . . . .
·
·
·
·
·
·
.
.
.
.
.
.
......
......
......
......
......
......
3-6
3-7
3-7
3-7
3-8
3-8
Section 4
TEST MODE COMMAND DESCRIPTIONS
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Mode Commands . . . . . . . . . . . . . . . . . . . . . . .
All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel . . . . . .
ATP Test . . . .
PIC Test. . . . .
LANIC Test ..
CPU . . . . . . . . .
Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Help . . . . . . . . . . . . . . . . . .
IOMA~ . . . . . . . . . . . . . . . . . . . . . .
Memory . . . . . . . . . . . . . . . . . . . . .
PON . . . . . . . . . . . . . . . . . . . . . . . .
·
·
·
·
·
..........
..........
..........
..........
..........
. ........
. ........
· ..
· ..
· ..
· ..
4-1
4-1
4-1
4-3
4-3
4-3
4-4
4-4
4-5
4-6
4-6
· .. 4-7
· ..........
4~8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Com rna nd Desc ri pt ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modify Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ......
Register Operations . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
Execution Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ..
Input/Output Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU ROMS Date Code 2647 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-1
5- 2
5- 2
5- 3
5- 4
5-5
5- 5
5- 5
5-6
Section 5
SOFTPANEL
DEC 86
CONTENTS (continued)
Appendix A
ERROR CODES
ATP Test Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , A-I
ATP Test Section I . . . . . . . . . . . . . . . . . . . . .
A-I
ATP Test Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , A-I
ATP Test Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A - 2
ATP Test Section 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
ATP Test Section 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 2
ATP Test Section 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
ATP Test Section 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A - 3
PIC Test Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A - 4
PIC Test Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , A-4
PIC Test Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , A-4
PIC Test Section 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A - S
PIC Test Section 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A - 5
PIC Test Section 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-6
PIC Test Section 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , A-6
PIC Test Section 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-6
PIC Test Section 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-7
PIC Test Section 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A - 7
LANIC Self test Subtest and Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
LANIC Selftest Subtest Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
LANIC Self test Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
CPU Test Error Codes . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . A-I 0
Memory Test Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-I 0
Power-On Self test LED Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-II
0
• • • • • • • • • • • • • • •
,
Appendix B
TOe RAM INFORMATION
TOC RAM Data and Status Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
DEC 86
vii
FIGURES AND TABLES
LIST OF TABLES
Table 2-1. Keyswitch Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2. Maintenance Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3. Test Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table A -1. Power-On Self test LED Interpretation . . . . . . . . . . . . . . . . . . . . A -II
Table B-1. TOC RAM Data and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Table 8-2. Last-Stop Value Meanings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Table B-3. System Halt Causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
LIST OF FIGURES
Figure 2-1. ACTIVITY/FAULT LEOs and Keyswitch . . . . . . . . . . . . . . . . . . 2-2
DEC 86
viii
~ER_R_O_R_C_O_D_E_S______________~lrH!H,
Appendix A includes aU error codes associa ted wiih i he -MiCRO 3000 seJftest. The errOi codes are listed
according to the test sequence they are associated with: ATP, PIC, LANle. CPU, ur MEMOR Y.
A TP TEST ERROR CODES
The ATP error codes are divided according to one of the nine sections of the ATP test that detected the
error.
The slot test will display (lne of the following error codes if the ATP test fads. The tests are run in the
same sequence as the test sections. Testing stops when the first failure is detected.
ATP Test Section 1
This section is the initializ.ation test which initiahl.es the ATP and verifies registers l:ontain expected data.
Code
Error
0108
0109
010A
010C
0100
010E
010F
Register
Register
Register
Register
Register
Register
Register
8 initialization error (expected $0800)
9 initializ.ation error (expeded $08(0)
A initializ.ation error (expected
C initializa tion error (expected
D initialization error (expected
E initializa tion error (expected
F initialization error (expected
$FFOU)
$0000)
$0000)
$ 5004)
$ 5004)
ATP Test Section 2
This section tests basic operations, and OBII, IPOLL, SMSK and RMSK.
Code
Error
0201
0202
0203
0204
0205
SMSK/RMSK test; ATP did not respond with mask bit set.
SMSK/RMSK test; ATP did not respond with mask bit clear.
A TP did not set IRQ.
Improper IPOLL response (none, wrong, or mUltiple channels).
Improper OBU response.
DEC 86
A-I
Error Codes
ATP Test Section 3
The section is the port register test which tests registers 0-7 on ports 0-7.
Code
Error
0300
0301
Port 0, register 0 pa ttern test failure
Port 0, register I pa ttern test failure
0307
0310
Port 0, register 7 pattern test failure
Port I, register 0 pattern test failure
0377
Port 7, register 7 pattern test failure
ATP Test Section 4
This section is the DMA test. SIMB write Word.
Code
Error
0401
0402
0403
0404
0405
0406
DMA state ma\,;hine failed to ~o to state 4.
DMA state machine failed 10 K{) to litatc 3.
DMA write to memory lrallliferrcd improper data.
DMA read from memory to RBYTE transferred improper data.
DMA read from memory to LBYTE transferred improper data.
DMA counter test failed.
ATP Test Section 5
Port selftest.
Code
Error
0500
0501
Port 0 self test failure
Port I selftest failure
0507
Port 7 selftesl failure
DEC 86
I
I
Error Codes
ATP Test Section 6
This section is the DMA loopback to port test.
Code
Error
0600
0601
Port 0 loopback failure
Port 1 loop back failure
0607
Port 7 loop back failure
A TP Test Section 7
This section is the DMA loopback data test.
Code
Error
0700
0701
Port 0 loopback data failure
Port 1 loopback data failure
0707
Port 7 loopback data failure
DEC 86
A-3
Error Codes
PIC TEST ERROR CODES
If the PIC test fails, the slot test will display one of the following error codes. The tests are run in the
same sequence as the test sections. Testing stops when the first failure is detected.
PIC Test Section 1
This section is the initialization test whidl initializes the PIC and verifies regi!;ters contain expected data.
Code
Error
0104
0105
0106
0107
0108
010A
010C
010f
Register
Register
Register
Register
Register
Register
Register
Register
4 initialization
5 initialization
6 initializa tion
7 initialization
error (expected SOOOO)
error (expected SOOOO)
error (expected $0020)
error (expected SOOnG)
8 initializa tion error (expected $0000)
A initialization error (expected $0000)
C initiallza tion error (expect.ed $0000)
F initialization error (expected $0087+(8 t channelH»
PIC Test Section 2
This sedion tests basic operations and 0811, IPOLl, SMSK and RMSK.
Code
Error
0201
0202
0203
0204
St'tlSK/RMSK test; PIC did not respond with mask bit set.
SMSK/RMSK test; PIC did not respond with mask bit cleared.
PIC did not set IRQ after SMSK on selected channel.
Improper IPOtl. response after SMSK (no response,
wrong response, or multiple channels responding).
Improper OBII data from this channel after SMSK.
Improper register D response after SMSK.
Improper IPOll response (should have been clear).
Received no CSRQ after issuing a SlOP.
\Vrong channel is responding to SPOlL.
Improper CBS! data after SPOLL
Improper register F data after SPOlL.
Improper CSRQ response after IIIOP (should have been zero).
Improper SPOLl after IIIOP (should have been zero).
Improper 08SI response to SPOLL after IHOP
(should have pointed to device 7).
0205
0206
0207
0208
0209
020A
0208
020C
0200
020E
DEC 86
.
_I'
Error Codes
PIC Test Section 3
This section tests the Btl-ill
~oniroiier
chip Status Register (PIC Register
n
Code
Error
0301
0302
Initialization error - bits 0 to 7 should be zero.
Initialization error - bits 10, 13, and 14 slhluld he 7.cro
ami bits I I and 12 should be one.
Hit 13 should be I, bit 14 should be zero when the IIP-IB
controller chip is addressed to talk, but not listen.
Bits 13 and 14 should both be one when the liP-In controller
chip is addressed to talk and listen.
Bit 14 should be one, bit 13 should be 7.cro when the 111'-18
controller chip is addresscd to listen, but not to talk.
nits 13 and 14 should both be zero whcn the liP-In controller
chip is not addressed to talk or to listen.
0303
0304
0305
0306
PIC Test Section 4
This section tests the liP-III controller I.:hip Interrupt Register (PIC Register 2) and Interrupt Mask
Register (PIC Register 3).
Code
Error
0401
0402
Reg2, bit 0 should be set (an interrupt is pending).
Reg 2, bits 9 and 13 should be clear
(no handshake abort and inbound FIFO empty).
Reg2, bit 12 should be set (outbound FIFO room available).
Reg 2, bit 14 should be set (out bound FIFO idle).
Reg2, bit 8 should be clear (no status change).
Reg 2, bit 0 should be clear (no interrupt pending).
Reg 2, bit 8 should be set (status change occurred).
Reg2. bit 9 should be clear (no handshake abort).
Reg 2, bits 12 and 14 should be clear. nit I 3 should be set
(outbound FIFO rOlll11 not available, l)utbllUlHI FIFO not idle,
and illh,llll11i FiFO not empi y. ._> FIFO Oits iii uprh'siCc
state).
Reg 2, bit 9 should be set (handshake abort).
Reg2. bit 9 should be clear (no handshake abort).
0403
0404
0405
0406
0407
0408
0409
040A
0406
DEC 86
Error Codes
PIC Test Section 5
This section tests PiC registers 4 and 5 by reading and writing data. Functions are not tested.
Code
Error
0501
0502
0503
0504
Register
Register
Register
Register
4
5
4
5
fails
fails
fails
fails
to
to
to
to
show
show
show
show
data
data
data
data
patterns
patterns
patterns
patterns
SOOe.
SOOAA.
S0055.
S0055.
PIC Test Section 6
This section tests PIC register 6 (IIP-18 control register).
Code
Error
0601
0602
0603
Register 6 fails to show patterns $802A for read/write test.
Register 6 fails to show patterns $4054 for read/write test.
Bits 12 and 14 of the liP-In controller chip interrupt
register (PIC register 2) should be set (outbound FIFO NOT
full and idle.
Bits 12 and 14 of the liP-In controller chip interrupt
register (PIC register 2) should be clear (outbound 1-"1£70
NOT full and idle.
Bit 15 of register 6 should be set (clear out bound FI£70) via
the liP-Ill controller chip interrupt register test. Bits 12
and 14 of the uP-In controller chip interrupt register
should be clear.
0604
0605
PIC Test Section 7
This section tests PIC register 7 {IIP-IB address).
Code
Error
0701
0702
0703
Regisier 7 fails io show patterns $ SOGA for read/write test.
Register 7 fails to show patterns $4015 for read/write test.
Bit 9 of Register 7 should be set (talk always) via the liP-In
controller chip status register (PIC register I) test.
Bits 13 or 14 of the IIP-IB controller chip register should
be off to indicate NOT a laik or a iisten.
Bit 10 of register 7 should be set (listen always) via the
111)-11\ controller 'hip status register test. Bit 13 of the
HP-IB controller chip status register must be on to indicate
a talk always.
0704
DEC 86
Error Codes
0705
0706
Same as 0704 except bit 14 of the IIP-IB controller chip
stat us register must be off to indicate NOT a listen always.
Same as 0704 except the IIP-IB controller chip status register
is again updated and bit 13 of the UP-In (;ontroller chip
status n:;gisler must be on to indicate NOT a listen always.
to indicate NOT a listen always.
PIC Test Section 8
TIllS section tests PIC register 8, 9 and 10 with read/write data only. Register H is tested for lower 8 bits
only. Register 9 and 10 (SA) are tested for all 16 bits.
Code
Error
0801
Register
Register
Register
Register
Register
Register
0802
0803
0804
0805
0806
8 fails to show da ta patterns SOOAA.
9 fails to show data patterns SAAAA.
10 fails to show data patterns SAAAA.
8 fails to show data patterns S0055.
9 fails to show data patterns S5555.
10 fails to show data patterns S 5 555.
PIC Test Section 9
This section tests DMA Write/Read/Abort from memory to PIC FIFO, and from PIC FIFO to memory.
Code
Error
0901
0902
CSRQ response & test via OBSI failed the DMA write to PIC.
Data transferred to the PIC FIFO by the above transfer
(assuming the DMA write abort test passed) is incorrect.
Bit 9 of the interrupt register (PIC reg 2) should be clear
(no handshake abort) the DMA write abort (PIC reg E) test.
CSRQ response & test via OBSI failed the DMA write abort.
Bit 5 of PIC register B should be set for the DMA write abort
termination test.
Bit 6 of PIC register B should be set for the DMA write abort
termination test.
CSRQ response & test via onsl failed the DMA read from PIC.
Data reat! from PIC on J)MA read test dlffercnt than expected.
CSRQ response & test via onsl failed for the DMA read abort.
Bit 5 of PIC register B should be set for the DMA read abort
termination test.
Bit 6 of PIC register B should be set for the DMA read abort
termination test.
Timeout. Waiting for CSRQ.
0903
0904
0905
0906
0907
0908
090A
0908
090e
090r
DEC 86
A-7
Error Codes
LANIC TEST ERROR CODES
LANIC Self test Subtest Codes
LANIC self test subtest descriptions and c(l<ics are h!lited below:
Code
Test
0001
0002
0003
0004
0005
0005
0006
0007
0008
0009
Z80 instruction set
EPROM checksum
Station address PROM checksum
Iligh byte la tch
RAM data (background test)
Byte RAM data (even addresses)
Byte RAM data (odd addresses)
Byte RAM address (in,rementing addresses)
Byte RAM address (decrementing addresses)
\Vord RAM address
OOOA
OOOB
OOOC
0000
OOOE
OOOF
\Vord/Byte address mapping
Z80 memory reference instructions
Values from reset MDIAG,SYSCON
eTC data tcst
CTC mode 0 counting
CTC mode 2 counting
0010
0011
0012
0013
0014
0015
0016
0017
0018
00 19
eTC mode 4 counting
Interrupt PAL (bit 4)
Z80 interrupt
Z80 non-maskable interrupt
Master handshake disabled (MHSDIS)
PAODR TO BADDR (low 15 bits)
ZBANKL
ZBANKH
Preliminary FIFO (INREADY, ADVREAOY, OUTREADY)
FIFO data (HDATA 7)
001A
001 B
OOtC
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
0010
001 E
001 F
DEC 86
data
data
data
data
data
data
(ilEA 7,8)
(BOAT A 2:6)
(BDATA 0,1,13:15)
(BDATA (8:12)
(BA 11: 15)
(BA 6: I 0)
Error Codes
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
FIFO data (SA 1: 5)
R 14 configuration register
OBII value; channel number not 0
COMCON values from reset
MAU power on/off
R i 3 CR, CR fuii bit
R 15 self test result register
82586 interrupt
81586 reset
Register decode (PilUS register addressing)
002A
002B
002C
002D
002£
82586 LANIC RAM addressing
82586 diagnose command
Level I chip lo\)pback
82586 write to FIFOS
MAU loopback on media
LANIC Self test Error. Codes
The system console will display ,)Ile of the following error codes if the LANIC test fails:
Code
Error
0179
Failure while performing 82586 initiali1.ation for the
LANIC diagnostic.
The 82586 did not clear its command word prior to
interrupting.
Self test result register (R 15) bit is bad.
Z 80 stack underflow during self test.
Unexpected Z80 non-maskable interrupt (NMI).
Unexpected Z 80 interrupt.
LANIC was reset but selflest never started, or I.ED circuitry
failed. (This code is set in the LEDs by the hard reset
preceding every full self test. ) In t his case, the selftest
may have a failure code or a random value.
017A
o17B
o17C
017D
017£
017f
DEC 86
A-9
Error Codes
CPU TEST ERROR CODES
The system console displays one of the following error codes if the epu test fails. The tests are run in the
same sequence as the test sections. Testing stops when the first failure is detected.
Test Section 1 - Bank register tests
a 10 1
0102
0103
0104
Pbank read/ A bank
Dbank read/Shank
Sbank read/Dbank
Abank read/Pbank
write
write
write
write
failure
failure
failure
failure
Test Section 2 - Toe RAM tests
020 1 TOe RAM test not done (power fail)
0202 TOe RAM data failure
Test Section 3 - Toe count verification
0203 TOe not counting
Test Section 4 - MPE timer verification
0301 TOe not counting
Test Section 5 - Watchdog timer verification
050 1 Watchdog timer did not rollover
MEMORY TEST ERROR CODES
The system console displays one of the following error codes if the memory test fails. The tests are run in
the same sequence as the test sections. Testing stops when the first failure is detected.
DEe 86
Code
Error
0000
000 1
0002
0003
0004
0005
PFAR test failed (memory dead)
Memory size test failed
Memory initialization test failed
Memory address test failed
Memory pattern test failed
Parity test failed
Error Codes
POWER-ON SELFTEST LED INTERPRET A TION
Table A-I. Power-On SeUtest LED Interpretation
ACTIVITY
LED
OFF
ON
FAULT
LED
OFF
ON
LED
INTERPRET ATION
ACTION
TOTAKE
No Power.
Check for AC. Measure
DC supply output.
Processor completely dead.
Replace processor.
Executing self test.
Wait for self test
completion.
System in ba ttery
back -up mode.
Wait for AC power
return.
OFF
ON
CPU or 0-2 Mb memory
failed.
Replace processor PCA.
OFF
Flashing single
blink
llnsupported ATP
detected.
Remove unsupported
ATP.
OFF
Flashing double
blink
Console ATP failed.
Replace ATP in slot I or
replace processor PCA.
Fast/slow 51MB I/F
failed.
OFF
Flashing triple
blink
Console failed to speed
sense.
Check cable connection
between console and ATP.
Check that console is in
REMOTE mode.
OFF
Flashing triple
blink
Console failed to speed
sense.
Console rna y be defective.
Attempt loopback
da lacomm test.
Replace ATP.
ON
OFF
Selftest execution
complete.
"H for help" prompt
displayed.
DEC 86
A-II
~1~14i1H,
T_E_S_T_M_O_DE________________
_COMMAND
DESCRIPTIONS
_
L _ ..
INTRODUCTION
This section provides a definition of test mode and a description of test mode commands.
Test mode allows the system operator to initiate and manually direct the self tests. Test mode allows for
looping up to 9999 times; the default is 1. Looping is disabled when the keyswitch is in position 111"
(NORMAL).
Use the maintenance mode TE [s t] command to enter test mode.
Error messages can be found in Appendix A.
TEST MODE COMMANDS
Test mode allows you to enter the following commands at the "Test ->" prompt:
All
Channel
Help
CPU
Memory
PON
Exit
IOMAP
All
The ALL command runs all of the manually directed self tests except the PON test in the following order:
• CPU test
• Memory test
• Channel test
• IOMAP
DEC 86
AI_I
Test Mode Command Descriptions
The test may be looped by specifying the desired number of loops in count. Count must be an integer
between I and 9999; the default is I. (A space is required before specifying count.)
The correct syntax for this command is:
AL [L]
[ coun t
]
The following illustrates the use of the ALL command:
1-NORMAL
Test ->AL
TOC RAM
Addr Data
OOOE 0000
OOOf 0000
0010 0000
0011 0000
0012 0004
0013 OOOE
0014 0000
0015 0000
CPU Test passed
Memory Test passed
Channel 1 - Terminal Interface Controller
Channel 4 - Peripheral Interface Controller
Test Passed
System I/O Configuration
Memory Size (MEGABYTES) = nn
Load:
Channel 4 Device 3
Start/Dump:
Channel 4 Device
Channel
ID=4
Channel 4
Device 3
Device 1
ID=2 - Peripheral Interface Controller
10=0260 - 9144 Cartridge Tape Unit
ID=$022B
7958 Disc Drive Unit
l-NORMAL
Test ->
DEC 86
- Terminal Interface Controller
Test Mode Command Descriptions
Channel
The CHANNEL test performs the ATP, PIC, and LANIC tests. The CHANNEL test may be looped by
specifying the desired number of loops in count. Count must be an integer between 1 and 9999; the
default is 1. (A space is required before specifying count.) Count must be specified whenever a specific
channel is selected with the channel command. If a particular channel is nut specified, all channels are
tested. The appropriate test (A TP, PIC, LANIC or none) is run for each PCA installed in the CPU. If a
failure occurs, the failure code is displayed on the system console next to the PCA description. Refer to
Appendix A for ATP, PIC, and LANIC test error codes.
ATP Test
The ATP test has six sections:
1. Init check. Performs an ATP initializ.ation and tests to verify registers contain proper data.
2. Basic I/O operations. Issues OBII, IPOLL, SMSK, and RMSK and verifies a proper response.
3. Port register tests. Writes patterns to registers 0-7 of ports 0-7 and verifies the data.
4. Diagnostic loopback using DMA sequencer ROM.
5. Initiates pec
test~
on all 8 ports.
6. Performs DMA data loopback test on all 8 ports.
The console A TP is speed sensed and communication lines are tested with the local console.
PIC Test
The PIC test has nine sections:
1. Init check. Performs PIC initializ.ation and verifies registers contain proper data.
2. Basic I/O operations. Issues OBII, IPOLL, SMSK, and RMSK and verifies a proper response.
3. Tests the HP-IB controller chip status register (PIC register 1).
4. Tests the lIP-IB controller chip interrupt (PIC register 2) and interrupt mask registers (PIC
register 3).
5. Tests PIC registers 4 and 5 using data patterns.
6. Tests PIC register 6.
7. Tests PIC register 7.
8. Tests PIC registers 8, 9, and A using data patterns.
9. Fills HP-IB controller chip FIFO and executes DMA to and from memory.
registers associated with DMA transfers.
Tests PIC
DEC 86
4-3
Test Mode Command Descriptions
LANIC Test
The LANIC code is not included in the selftest microcode. The LANIC PCA executes its own
self test.
After the ATP, PIC, and LANIC tests execute, return is to the "Tes t - >" prompt.
The correct syntax for this command is:
CH[an][ count[,channel]
The following illustrates the use of CHAN:
1-NORMAL
Test ->CH
Channel
- Terminal Interface Controller
Channel 4 - Peripheral Interface Controller
Test Passed
1-NORMAL
Test -)
CPU
The test mode CPU command executes the following CPU tests not run at power-on:
• P, D, S, and A bank register tests.
• TOC RAM loea tion test.
• TOC counting verification.
• MPE timer counting verification.
• Watchdog Timer Force Condition verification and FMD capability test.
Te,sts not performed by this CPU test, but executed by the power-on CPU test are:
• ROM checksum test.
• Full processor chip function test.
• Full WCS address and data test.
• Register file address and data test.
Test Mode Command Descriptions
The test may be looped by specifying the desired number of loops in count. Count must be an integer
between 1 and 9999; the default is 1. (A space is required before specifying count.) The correct syntax
for this command is:
CPU [ count]
The following illustrates the use of CPU:
1-NORMAL
Test ->CP
TOC RAM
Addr Data
OOOE 0000
0000
0010 0000
0011 0000
0012 0004
0013 OOOE
0014 0000
0015 0000
CPU test passed
ooor
1-NORMAL
Test ->
Exit
The test mode EXIT command returns execution to maintenance mode and displays the "H for help- >"
prompt.
The correct syntax for this command is:
E[xit]
The following illustrates the use of EXIT:
Test ->E
H for help->
DEC 86
A~C
Test Mode Command Descriptions
Help
The HELP command does not appear in the test mode menu. When issued, the HELP command displays the
available test mode commands and the ROM version number.
The correct syntax for this command is:
HELP
The following illustrates the use of HELP:
l-NORMAL
Test ->H
ROM Version:
nnnn
Self test Menu:
AL[l] [ count]
CH[an] [ count [ ,chan] ]
CP[u] [ count 1
E[xit]
I [omap] [ count ]
M[emory] [ count
PON [ count ]
l-NORMAL
Test ->
IOMAP
The IOMAP command executes a version of IOMAP contained in the selftest ROM. This version of
IOMAP runs the memory size portion of the memory test, displays the number of megabytes installed in
the system, lists the load and start/dump devices, and identifies all peAs installed in the system. All
supported HP-IB devices attached to the PIC are identified and their 10 code is displayed with a device
description.
The test may be looped by specifying the desired number of loops in count. Count must be an integer
between I and 9999; the default is 1. (A space is required before specifying count.)
The correct syntax for this command is:
I [omap] [ count]
DEC 86
A
£
Test Mode Command Descriptions
The following illustrates the use of IOMAP:
t-NORMAL
Test ->1
System I/O Configuration
Memory Size (MEGABYTES)
Load:
Channel 4 Device 3
Start/Dump:
Channel 4 Device
= nn
Channel
10=4
- Terminal Interface Controller
Channel 4
Device 3
10=2 - Peripheral Interface Controller
10=$0260 - 9144 Cartridge Tape Unit
l-NORMAL
Test ->
Memory
The test mode MEMORY command executes the power-on memory test. The amount of installed memory is
determined, then memory is initialized before a refresh test, an address test, a pattern test and a parity test
are performed. Upon test completion, memory is left with $30F8 (halt 8) in all locations.
The full memory test executes. If an error is detected, the system console displays the memory test section
number the error was detected in. The FAULT LED will light and the ACTIVITY LED will go out.
Refer to Appendix A for list of memory test error codes.
The test may be looped by specifying the desired number of loops in coun t. Coun t must be an integer
between 1 and 9999; the default is l. (A space is required before specifying coun t.)
Return is to the "Test ->" mode prompt.
The correct syntax for this command is:
M[emory]
[ count}
The following illustrates the u·se of MEMORY:
l-NORMAL
Test ->M
Memory Test passed
DEC 86
Test Mode Command Descriptions
PON
The test mode PON command executes the power-on self test count times. This command is like the ALL
test mode command except the power-on CPU test is executed in place of the manually executed CPU
test, and IOMAP is not executed. The PON test is initiated by toggling the PON hne.
NOTE
This command cannot be run from keyswitch poslhon "3" (REMOTE) or
from keyswitch position "2" (LOCAL) directly from position "3" (REMOTE).
The correct syntax for this command is:
PON [count]
The following illustrates the use of PON:
2-LOCAL (from Normal)
Self Test ->PON
Power on Self Test
Memory Test passed
Memory Size (MEGABYTES) = nn
Channel 1 - Terminal Interface Controller
Channel 4
Peripheral Interface Controller
2-LOCAL (from Normal)
Self Test ->
DEC 86
A._!Z
~SO_F_T_P_AN_E_L________________~lr~'
INTRODUCTION
Softpanel is a diagnostic tool used to examine software. Softpanel allows the user to display and modify
memory, perform register and I/O operations, and perform other necessary functions. All commands
requiring parameters must have a "+", "_If, or a space between the the command and the parameter. The
following commands are allowed in softpanel:
Input/Output Operations
RIO
WIO
Display Memory
Modify Memory
Other /Miscellaneous
T
Register Operations
DR
MR
ENV
RTOC
WTOC
Execution Control
E
R()X
RUN
ST
COMMAND PARAMETERS
Softpanel command parameters are defined as:
bank
One of the following numeric fields limited to a range of 0 - 255 (8 bits): the
current radix numeric field, a hexadecimal numeric field preceded by a $ or a
digit, or an octal numeric field preceded by a ~
count
One of the following numeric fields limited to a 16 bit maximum: the current
radix numeric field, a hexadecimal numeric field preceded by a $ or a digiti or
an octal numeric field preceded by a "/e.
epxr
A combination of
numeric
and
op.
Operations are performed from left to
right with no precedence.
ioaddr
One of the following numeric fields limited to a 16 bit maximum: the current
radix numeric field, a hexadecimal numeric field preceded by a $ or a digit, or
an octal numeric field preceded by a "/e.
DEC 86
Softpanel
iodata
One of the following numeric fields limited to a 16 bit maximum: the cllrrent
radix numeric field, a hexadecimal numeric field preceded by a $ or a digit, or
an octal numeric field preceded by a 1-.
numeric
One of Ihe following numeric fields limited to a I tl bit IIl:Ullllum: the current
radix numeric field, a hexadecimal numeric field preceded by a $ or a digit, or
an octal numeric field preceded by a %.
op
One of: a +, -, or *. Operations done on numeric fields are signed. Bit (0: 1) is
the sign bit. : is the indirection operator.
reg
One of the following registers: DB, DL, Q, S, PB, PL, Z, STA (the liP 3000
status register), SB (the split bank flag, I bit wide), CIR, X, SW (the switch
register containing load/boot device DRT), Dbank, Sbank, Pbank, LPFlg, DISP,
or ICS.
regfile
One of the following numeric fields limited to a range of 0 - 255 (8 bits): the
current radix numeric field, a hexadecimal numeric field preceded by a $ or a
digit, or an octal numeric field preceded by a 1..
tocaddr
One of the following numeric fields limited to a 16 bit maximum: the current
radix numeric field, a hexadecimal numeric field preceded by a $ or a digit, or
an octal numeric field preceded by a 1-.
tocdata
One of the foHowing numeric fields limited to a 16 bit maximum: the current
radix numeric field, a hexadecimal numeric field preceded by a $ or a digit, or
an octal numeric field preceded by a ~.
COMMAND DESCRIPTIONS
Display Memory
The D command continues from the last screen displayed and displays another half screen of data. All
display commands display in the current radix (refer to SDM [Set Display Mode] command). The display
command will always show multiples of 8 words in the current radix and in ASCII.
The options are:
DA expr [: [
~~
l
expr] ] [ ,coun t ]
DEA bank.expr[:
[+
]
][:[
[ [expr]]
DSY [ -expr
DEC 86
s-,
Displays memory at the given absol ute address in bank O.
[~~ ~expr]] [,count]
Displays the absolute address relative to the specified bank.
l~ 1expr] ] [ ,coun t ]
Displays the absolute address relative to sysglobal.
Softpanel
[+
]
DDB[-expr ][: [~:lexpr]][tcount]
[ [expr]]
rU',\1
[+
r _D-r-nr
.......... L
~-t"
]
1 r.
r [+] D-r-nrl1
r .....;"\UH# 1
j j L ,........ " .. J
J L • L [ _ ]
~-t'
Displays the absolute address relative to the DB register.
Displays the absolute ad,lress relative to the DL iegistei .
[ [expr]]
[+
DO
]
[-expr ][:[f:~expr]][,Count]
[ [expr]]
[+
]
DPB[-expr ][: [f:~expr]] [,count]
[ [expr]]
[+
DS
[+
Displays the absolute address relative to the S register.
]
[-expr ][: [~:~expr]] [,count]
[ [expr]]
DP [-expr
Displays the absolute address relative to the PB register.
)
[-expr ][: [f:~expr]][,count]
[ [expr]]
[+
DZ
Displays the absolute address relative to the Q register.
Displays the absolute address relative to the Z register,
]
l[:[~:lexprl][tcount]
Displays the absolute address relative to the P register.
[ [expr]]
[+
]
OPL[-expr ][:[f:~expr]][,count]
[ [expr]]
Displays the absolute address relative to the PI. register.
Modify Memory
Modify memory commands will display the current address, current contents, and wait for the user to
input a new value. Input the new value using a numeric field with the current default radix or force the
new value using the radix forces ("%" or "S"). The command will terminate when the user inputs either"."
or "' /" in response to the prompt.
The options are:
MA expr[: [I:lexpr]]
MEA
bank.expr[:[~:lexpr]]
[+
Modify the absolute address in bank O.
Modify the absolute address in the specified bank.
]
MSY[-expr ][:[~:lexpr]]
[ [expr]]
Modify the absolute address in sysglobal.
DEC 86
5-3
Softpanel
[+
]
MDB[-expr ][:[~~~exprJl
[ [expr]]
[+
MOL [-expr
Modify the absolute address in the D8 register.
1
J[: [I~~exprl]
Modify the absolute address in the DL register.
[ [expr]]
[+
MQ
[+
MS.
]
l
[-expr ] [ : [ ~: expr] ]
[ [expr]]
[+
MZ
J
[-expr ][:[I:lexpr]]
[ [expr]]
Modify the absolute address in the MPS register.
]
] [:[I~~exprl)
[ [exprJ]
MP [-expr
[+
Modify the absolute address in the Z register.
]
MPB[-expr ][: [{~~expr]]
[ [expr]J
(+
Modify the absolute address in the S register.
]
[-expr ][: [f:lexpr]]
[ [expr]]
[+
Modify the absolute address in the Q register.
Modify the absolute address in the P register.
]
MPL[-expr ] [:[t~~expr]]
[ [expr] J
Modify the absolute address in the PL register.
Register Operations
The DR command will display the common registers (i.e., P, PB, PL, CIR, DB, Q, S, etc.).
specified to DR then all common registers will be displayed.
The options are:
DR
MR
[reg
]
[regfile [,count jj
Display the value contained in a register.
{reg
}
regfile
Modify the value contained in a register.
DEC 86
If no field is
Softpanel
Execution Control
The options are:
E
Exit back to maintenance mode
RUN
Run (return to software)
Input/Output Operations
The addresses and data patterns for Input/Output operations conform to 1MB and 51MB formats.
The options are:
RIO ioaddr
WIO
ioaddr~iodata
Read I/O from address
Write I/O address
ioaddr
ioaddr with data iodata
Miscellaneous Commands
The T (Trace) command allows the user to trace the current (or specified) stack. ENV allows the user to
move back markers of the current stack and access data there as if it were at the current marker. ROX
aJIows the user to change the current radix. Softpanel starts with the radix set to octal. The ENV
command specified with no parameters will turn ENV off (q-relative addresses revert to the current
en vironmen t).
The options are:
T[ [numeric.]numeric]
ENV[
numeric]
Trace stack.
Change the environment.
RTOC tocaddr
Read TOC RAM address.
WTOC tocaddr,tocdata
Write TOC RAM with data.
ROX
ST
{~
Change the current radix. (H - Ilex; 0 - Octal)
Give softpanel status.
DEC 86
c _c
Softpanel
CPU ROMS Date Code 2647 Exceptions
1. In the softpane!: Any hcx.adel.imal value starting with an alphabetic character (for example,
"A"." A oo.....C 0") must be prel:eded by either a zero or a dollar sign. even if the current radix is set to
hexadecimal. Imbedded letters in a hex value starting with a numeric charadcr (for example. "ICOO") do
not have this restriction. The reason for this qualification for numeric in the hex radix is to distinguish
between the DB register and the value "SOB".
2. In the softpanel, the T (Trace) command to a non -ex.istent s-bank does not print an error message.
3. In the softpanel. the T (Trace) command will print the last user stack if the current stack is the ICS,
but there is no way to use the ENV command to move back to the user stack.
4. In the softpanel, using t he RIO command to a non -existent register produces a watchdog timer
interrupt. and the (,;onsolc comes back to the maintenance Illode prompt.
5. The switch register (SR) is not ill the default register display. It may be dIsplayed manually.
6. In the software display. the status register flags M. I. T, R, 0, and C indicate a value of 1 with an upper
case letter and a value of 0 with a lower case letter.
DEC 86
Toe RAM INFORMATION
~_ ______________________________________________
~I~B;!l16i
_~
Appendix B contains tables defining the TOe RAM locations displayed on the system console during
self test execution.
Toe RAM DA T A AND ST A TUS TABLES
Table 8-1. TOe RAM Data and Status
Toe RAM ADDRESS
ST ATUS AND OAT A STORED IN TOC RAM ADDRESS
$OA
Register A
SOB
Register B
SOC
Register
SOD
Register D
$OE
Undefined
$OF
Console ATP port 0 interrupt time-out flag*
$10
Last stop information. See Table 8- 2.
S 11
Sta rt device
S12
Load device
$13
Undefined
$14
Test loop counter (lower byte)
SI5
Test loop counter (upper byte)
SI6-S3F
e
Undefined
* If
the ATP port 0 interrupt time -out flag is set (contains SAA) this means port 0 of the ATP
in slot 1 of the SPU has failed to produce an expected interrupt within 500 milliseconds and the
microcode has timed-out. This flag should be checked if the RUN command cannot be executed.
If the flag is set, port 0 configuration information was not stored and thus could not be restored
upon executing the RUN command.
DEC 86
Toe RAM Information
Table 8-2. Last-Stoll Value Meanings
VALUE
MEANING
$OO-$OF
Halts 0 through 15 (halt instructions executed)
$IO-$IF
System Halt 0 through 15 (firmware detected traps). See Table 8- 3.
$20
WCS parity error
$11
Watc.:hdog Timer
$22
Power failure
$23
Control B (maintenance mode invoked)
$24
Mult iple bit paril y error
$25
51MB bus parity error
$7F
MPE UP status removed by software. Disables Power Fail Auto
Restart.
$80
System was runnillg MPE or other software. Enables Power Fail Auto
Restart.
$81-$FF
Unused. These values may be seen upon TOC power-on.
NOTE
Values between
SOD and $FF not shown in Table H-2 are undefined.
Toe RAM Information
Table 8-3. System lIalt Causes
SYSTEM HALT
Toe VALUE
I
SII
STT violation segment 1
2
$12
Absent trap while on les
3
SI3
Code segment I tnp violation
4
$14
ICS stack overflow
6
$16
Initial program load failure
7
$17
Illegal SBnk at QI- 5 during IXIT
9
$19
I'suedo-Enable when enabled
CAUSE
NOTE
Values between SI 0 and $1 f not shown ill Table B- 3 are undefined.
DEC 86
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