USER`S MANUAL

USER'S MANUAL

S3C84MB/F84MB

8-BIT CMOS MICROCONTROLLERS

January 2009

REV 1.00

Confidential Proprietary of Samsung Electronics Co., Ltd

Copyright © 2009 Samsung Electronics, Inc. All Rights Reserved

Important Notice

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S3C84MB/F84MB 8-Bit CMOS Microcontrollers

User's Manual, Revision 1.00

Publication Number: 21-S3-C84MB/F84MB-012009

Copyright

© 2006~2009 Samsung Electronics Co., Ltd.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and

objectives.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Dong, Giheung-Gu,

Yongin-City, Gyunggi-Do, Korea

C.P.O. Box #37, 446-711

TEL: (82)-(31)-209-5238

FAX: (82)-(31)-209-6494

Home Page: http://www.samsung.com

Printed in the Republic of Korea

NOTIFICATION OF REVISIONS

ORIGINATOR:

Samsung Electronics, LSI Development Group, Gi-Heung, South Korea

PRODUCT NAME:

S3C84MB/F84MB 8-bit CMOS Microcontroller

DOCUMENT NAME:

S3C84MB/F84MB User's Manual, Revision 1.00

DOCUMENT NUMBER:

21.00-S3-C84MB/F84MB - 012009

EFFECTIVE DATE:

January, 2009

REVISION HISTORY

Revision No

0.00

1.00

Description of Change

−

In a tool program mode, user must connect

TEST pin to Vdd.

Refer to

−

−

Author(s)

−

Th.Kim

Date

−

January 2009

REVISION DESCRIPTIONS FOR REVISION 1.0

Chapter

Chapter Name

21. Flash Memory MCU

Subjects (Major changes comparing with last version)

Page

1 ~ 6

Flash Memory MCU sector is added.

Preface

The S3C84MB/F84MB Microcontroller User's Manual is designed for application designers and programmers who are using the S3C84MB/F84MB microcontroller for application development.

It is organized in two main parts:

Part I Programming Model Part II Hardware Descriptions

Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters:

Chapter 1

Chapter 2

Chapter 3

Product Overview

Address Spaces

Addressing Modes

Chapter 4

Chapter 5

Chapter 6

Control Registers

Interrupt Structure

Instruction Set

Chapter 1, "Product Overview," is a high-level introduction to S3C84MB/F84MB with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the

S3C8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3C84MB/F84MB interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in

Part II. If you are not yet familiar with the S3C-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the

S3C84MB/F84MB microcontroller. Also included in Part II are electrical, mechanical, Flash MCU, and development tools data. It has 16 chapters:

Chapter 7

Chapter 8

Clock Circuit

RESET and Power-Down

Chapter 9 I/O Ports

Chapter 10 Basic Timer

Chapter 11 8-bit Timer A/B/C(0/1)

Chapter 12 16-bit Timer 1(0/1)

Chapter 13 Serial I/O Port

Chapter 14 UART(0/1)

Chapter 15

Chapter 16

Chapter 17

Chapter 18

Chapter 19

Chapter 21

Chapter 22

10-bit A/D Converter

PWM

Pattern Generation Module

Embedded Flash Memory Interface

Electrical Data

Chapter 20 Mechanical Data

S3F84MB Flash MCU

Development Tools

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER iii

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

S3C8-Series Microcontrollers ........................................................................................................................1-1

S3C84MB/F84MB Microcontroller .................................................................................................................1-1

Features .........................................................................................................................................................1-2

Block Diagram................................................................................................................................................1-3

Pin Assignment ..............................................................................................................................................1-4

Pin Descriptions .............................................................................................................................................1-6

Pin Circuits .....................................................................................................................................................1-9

Chapter 2 Address Spaces

Overview ........................................................................................................................................................2-1

Program Memory (ROM) ...............................................................................................................................2-2

Smart Option.........................................................................................................................................2-3

Register Architecture .....................................................................................................................................2-4

Register Page Pointer (PP) ..................................................................................................................2-6

Register Set 1 .......................................................................................................................................2-7

Register Set 2 .......................................................................................................................................2-7

Prime Register Space...........................................................................................................................2-8

Working Registers ................................................................................................................................2-9

Using the Register Pointers..................................................................................................................2-10

Register Addressing.......................................................................................................................................2-12

Common Working Register Area (C0H–CFH) .....................................................................................2-14

4-Bit Working Register Addressing ......................................................................................................2-15

8-Bit Working Register Addressing ......................................................................................................2-17

System and User Stack .................................................................................................................................2-19

Chapter 3 Addressing Modes

Overview ........................................................................................................................................................3-1

Register Addressing Mode (R).......................................................................................................................3-2

Indirect Register Addressing Mode (IR).........................................................................................................3-3

Indexed Addressing Mode (X) .......................................................................................................................3-7

Direct Address Mode (DA) .............................................................................................................................3-10

Indirect Address Mode (IA) ............................................................................................................................3-12

Relative Address Mode (RA) .........................................................................................................................3-13

Immediate Mode (IM) .....................................................................................................................................3-14

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER v


(Continued)

Chapter 4 Control Registers

Overview .............................................................................................................................................. 4-1

Chapter 5 Interrupt Structure

Overview........................................................................................................................................................ 5-1

Interrupt Types ..................................................................................................................................... 5-2

S3C84MB/F84MB Interrupt Structure.................................................................................................. 5-3

Interrupt Vector Addresses .................................................................................................................. 5-5

Enable/Disable Interrupt Instructions (EI, DI) ...................................................................................... 5-7

System-Level Interrupt Control Registers............................................................................................ 5-7

Interrupt Processing Control Points ..................................................................................................... 5-8

Peripheral Interrupt Control Registers ................................................................................................. 5-9

System Mode Register (SYM) ............................................................................................................. 5-10

Interrupt Mask Register (IMR) ............................................................................................................. 5-11

Interrupt Priority Register (IPR)............................................................................................................ 5-12

Interrupt Request Register (IRQ)......................................................................................................... 5-14

Interrupt Pending Function Types........................................................................................................ 5-15

Interrupt Source Polling Sequence ...................................................................................................... 5-16

Interrupt Service Routines ................................................................................................................... 5-16

Generating interrupt Vector Addresses ............................................................................................... 5-17

Nesting of Vectored Interrupts ............................................................................................................. 5-17

Chapter 6 Instruction Set

Overview ....................................................................................................................................................... 6-1

Data Types........................................................................................................................................... 6-1

Register Addressing............................................................................................................................. 6-1

Addressing Modes ............................................................................................................................... 6-1

Flags Register (FLAGS)....................................................................................................................... 6-6

Flag Descriptions ................................................................................................................................. 6-7

Instruction Set Notation........................................................................................................................ 6-8

Condition Codes .................................................................................................................................. 6-12

Instruction Descriptions........................................................................................................................ 6-13

vi S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER


(Continued)

Part II Hardware Descriptions

Chapter 7 Clock Circuit

Overview ........................................................................................................................................................7-1

System Clock Circuit ............................................................................................................................7-1

Clock Status During Power-Down Modes ............................................................................................7-2

System Clock Control Register (CLKCON) ..........................................................................................7-3

Chapter 8 RESET and Power-Down

System Reset ................................................................................................................................................8-1

Overview ...............................................................................................................................................8-1

Normal Mode Reset Operation.............................................................................................................8-1

Hardware Reset Values........................................................................................................................8-2

Power-Down Modes ......................................................................................................................................8-6

Stop Mode ............................................................................................................................................8-6

Idle Mode ..............................................................................................................................................8-7

Chapter 9 I/O Ports

Overview ........................................................................................................................................................9-1

Port Data Registers ..............................................................................................................................9-2

Port 0 ....................................................................................................................................................9-3

Port 1 ....................................................................................................................................................9-5

Port 2 ....................................................................................................................................................9-8

Port 3 ....................................................................................................................................................9-11

Port 4 ....................................................................................................................................................9-14

Port 5 ....................................................................................................................................................9-18

Port 6 ....................................................................................................................................................9-21

Port 7 ....................................................................................................................................................9-22

Port 8 ....................................................................................................................................................9-24

Chapter 10 Basic Timer

Overview ........................................................................................................................................................10-1

Basic Timer (BT)...................................................................................................................................10-1

Basic Timer Control Register (BTCON) ...............................................................................................10-1

Basic Timer Function Description.........................................................................................................10-3

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER vii


(Continued)

Chapter 11 8-bit Timer A/B/C(0/1)

8-Bit Timer A.................................................................................................................................................. 11-1

Overview .............................................................................................................................................. 11-1

Function Description ............................................................................................................................ 11-2

Timer A Control Register (TACON) ..................................................................................................... 11-3

Block Diagram...................................................................................................................................... 11-4

8-Bit Timer B.................................................................................................................................................. 11-5

Overview .............................................................................................................................................. 11-5

Block Diagram...................................................................................................................................... 11-5

Timer B Control Register (TBCON) ..................................................................................................... 11-6

Timer B Pulse Width Calculations ....................................................................................................... 11-7

8-Bit Timer C (0/1) ......................................................................................................................................... 11-11

Overview .............................................................................................................................................. 11-11

Timer C (0/1) Control Register (TCCON0, TCCON1) ......................................................................... 11-12

Block Diagram...................................................................................................................................... 11-13

Chapter 12 16-bit Timer 1(0/1)

Overview........................................................................................................................................................ 12-1

Function Description ............................................................................................................................ 12-2

Timer 1(0/1) Control Register (T1CON0, T1CON1) ............................................................................ 12-3

Block Diagram...................................................................................................................................... 12-6

Chapter 13 Serial I/O Port

Overview........................................................................................................................................................ 13-1

Programming Procedure...................................................................................................................... 13-1

SIO Control Register (SIOCON) .......................................................................................................... 13-2

SIO Prescaler Register (SIOPS, SIOPS1)........................................................................................... 13-3

Block Diagram...................................................................................................................................... 13-3

Serial I/O Timing Diagrams.................................................................................................................. 13-4

viii S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER


(Continued)

Chapter 14 UART(0/1)

Overview ........................................................................................................................................................14-1

Programming Procedure ......................................................................................................................14-1

Uart Control Register (UARTCON0, UARTCON1, UARTCON2) ........................................................14-2

Uart Interrupt Pending Register (UARTPND).......................................................................................14-3

Uart Parity Control and Status Register (UARTPRT)...........................................................................14-4

Uart Data Register (UDATA0, UDATA1, UDATA2) .............................................................................14-5

Uart Baud Rate Data Register (BRDATA0, BRDATA1, BRDATA2) ....................................................14-5

Baud Rate Calculations (UART0).........................................................................................................14-5

Block Diagram................................................................................................................................................14-7

Uart Mode 0 Function Description ........................................................................................................14-8




Serial Communication for Multiprocessor Configurations ....................................................................14-12

Chapter 15 10-bit A/D Converter

Overview ........................................................................................................................................................15-1

Function Description ......................................................................................................................................15-1

A/D Converter Control Register (ADCON) ...........................................................................................15-2

Internal Reference Voltage Levels .......................................................................................................15-4

Conversion Timing................................................................................................................................15-4

Internal A/D Conversion Procedure......................................................................................................15-5

Chapter 16 Pulse Width Modulation

Overview........................................................................................................................................................16-1

PWM Control Register (PWMCON) .....................................................................................................16-1

PWM2–PWM3 ...............................................................................................................................................16-3

PWM2, PWM3 Function Description ....................................................................................................16-4

Staggered PWM Outputs......................................................................................................................16-5

PWM0–PWM1 ...............................................................................................................................................16-6

PWM Counter .......................................................................................................................................16-6

PWM Data and Extension Registers ....................................................................................................16-6

PWM Clock Rate ..................................................................................................................................16-6

PWM0 and PWM1 Function Description ..............................................................................................16-8

Chapter 17 Pattern Generation Module

Overview........................................................................................................................................................17-1

Pattern Gneration Flow.........................................................................................................................17-1

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER ix


(Continued)

Chapter 18 Embedded FLASH Memory Interface

Overview........................................................................................................................................................ 18-1

Flash Memory Control Registers................................................................................................................... 18-4

Flash Memory Control Register ........................................................................................................... 18-4

Flash Memory User Programming Enable Register ............................................................................ 18-4

Flash Memory Sector Address Register .............................................................................................. 18-5

Sector Erase ........................................................................................................................................ 18-6

Programming ................................................................................................................................................. 18-10

Reading ......................................................................................................................................................... 18-15

Hard Lock Protection..................................................................................................................................... 18-16

Chapter 19 Electrical Data

Overview .............................................................................................................................................. 19-1

Chapter 20 Mechanical Data

Overview .............................................................................................................................................. 20-1

Chapter 21 S3F84MBJ Flash MCU

Overview........................................................................................................................................................ 21-1

Operating Mode Characteristics .......................................................................................................... 21-5

Chapter 22 Development Tools

Overview........................................................................................................................................................ 22-1

Target Boards ...................................................................................................................................... 22-1

Programming Socket Adapter.............................................................................................................. 22-1

TB84MB Target Board ......................................................................................................................... 22-3

Idle LED ............................................................................................................................................... 22-5

Stop LED.............................................................................................................................................. 22-5

OTP/MTP Programmer (Writer) ........................................................................................................... 22-8

x S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER

Number

3-1

3-2

3-3

3-4

3-5

3-6

3-7

2-9

2-10

2-11

2-12

2-13

2-14

2-15

2-16

3-8

3-9

3-10

3-11

3-12

3-13

3-14

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

1-1

1-2

1-3

1-4

1-5

1-6

1-7

1-8

1-9

1-10

List of Figures

Number

S3C84MB/F84MB Block Diagram ..............................................................................1-3

S3C84MB/F84MB Pin Assignment (80-QFP) ............................................................1-4

S3C84MB/F84MB Pin Assignment (80-TQFP) ..........................................................1-5

Pin Circuit Type B (RESETB) .....................................................................................1-9

Pin Circuit Type C.......................................................................................................1-9

Pin Circuit Type D (P0, P1, P2 except P2.3, P3, P8 except P8.4, P8.5) ...................1-10

Pin Circuit Type D-1 (P4, P8.4, P8.5).........................................................................1-10

Pin Circuit Type E (ADC0-ADC7)...............................................................................1-11

Pin Circuit Type F (P6) ...............................................................................................1-11

Pin Circuit Type G (P5.7-P5.4) ...................................................................................1-11

Program Memory Address Space ..............................................................................2-2

Smart Option...............................................................................................................2-3

Internal Register File Organization.............................................................................2-5

Register Page Pointer (PP) ........................................................................................2-6

Set 1, Set 2, Prime Area Register ..............................................................................2-8

8-Byte Working Register Areas (Slices) .....................................................................2-9

Contiguous 16-Byte Working Register Block .............................................................2-10

Non-Contiguous 16-Byte Working Register Block .....................................................2-11

16-Bit Register Pair ....................................................................................................2-12

Register File Addressing ............................................................................................2-13

Common Working Register Area................................................................................2-14

4-Bit Working Register Addressing ............................................................................2-16

4-Bit Working Register Addressing Example .............................................................2-16

8-Bit Working Register Addressing ............................................................................2-17

8-Bit Working Register Addressing Example .............................................................2-18

Stack Operations ........................................................................................................2-19

Register Addressing ...................................................................................................3-2

Working Register Addressing.....................................................................................3-2

Indirect Register Addressing to Register File.............................................................3-3

Indirect Register Addressing to Program Memory .....................................................3-4

Indirect Working Register Addressing to Register File ..............................................3-5

Indirect Working Register Addressing to Program or Data Memory ..........................3-6

Indexed Addressing to Register File ..........................................................................3-7

Indexed Addressing to Program or Data Memory with Short Offset ..........................3-8

Indexed Addressing to Program or Data Memory......................................................3-9

Direct Addressing for Load Instructions .....................................................................3-10

Direct Addressing for Call and Jump Instructions ......................................................3-11

Indirect Addressing.....................................................................................................3-12

Relative Addressing....................................................................................................3-13

Immediate Addressing................................................................................................3-14

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER xi

Number

7-3

9-1

9-2

9-3

9-4

9-5

9-6

9-7

9-8

9-9

9-10

9-11

9-12

9-13

9-14

9-15

9-16

9-17

9-18

5-7

5-8

5-9

6-1

7-1

7-2

4-1

5-1

5-2

5-3

5-4

5-5

5-6

List of Figures

(Continued)

Number

Register Description Format ...................................................................................... 4-5

S3C8-Series Interrupt Types ..................................................................................... 5-2

S3C84MB/F84MB Interrupt Structure........................................................................ 5-4

ROM Vector Address Area ........................................................................................ 5-5

Interrupt Function Diagram ........................................................................................ 5-8

System Mode Register (SYM) ................................................................................... 5-10

Interrupt Mask Register (IMR) ................................................................................... 5-11

Interrupt Request Priority Groups .............................................................................. 5-12

Interrupt Priority Register (IPR) ................................................................................. 5-13

Interrupt Request Register (IRQ)............................................................................... 5-14

System Flags Register (FLAGS) ............................................................................... 6-6

Main Oscillator Circuit (Crystal or Ceramic Oscillator) .............................................. 7-1

System Clock Circuit Diagram ................................................................................... 7-2

System Clock Control Register (CLKCON) ............................................................... 7-3

Port 0 Control Register (P0CON) .............................................................................. 9-4


Port 1 Extension Control Register (P1CONEX)......................................................... 9-7

Port 2 High-Byte Control Register (P2CONH)........................................................... 9-9

Port 2 Low-Byte Control Register (P2CONL) ............................................................ 9-10





Port 4 Interrupt Control Register (P4INT) .................................................................. 9-17

Port 4 Interrupt Pending Register (P4INTPND)......................................................... 9-17



Port 6 Control Register (P6CONL) ............................................................................ 9-21




Port 8 Interrupt Pending Register (P8INTPND)......................................................... 9-27

xii S3C84MB/F84MB MICROCONTROLLER

Number

10-1

10-2

11-1

11-2

11-3

11-4

11-5

11-6

11-7

11-8

12-1

12-2

12-3

13-1

13-2

13-3

13-4

13-5

13-6

14-1

14-2

14-3

14-4

14-5

14-6

14-7

14-8

14-9

14-10

15-1

15-2

15-3

15-4

15-5

List of Figures

(Continued)

Number

Basic Timer Control Register (BTCON) .....................................................................10-2

Basic Timer Block Diagram ........................................................................................10-4

Timer A Control Register (TACON)............................................................................11-3

Timer A Functional Block Diagram.............................................................................11-4

Timer B Functional Block Diagram.............................................................................11-5

Timer B Control Register (TBCON)............................................................................11-6

Timer B Data Registers (TBDATAH, TBDATAL) .......................................................11-6

Timer B Output Flip-Flop Waveforms in Repeat Mode ..............................................11-8

Timer C (0/1) Control Register (TCCON0, TCCON1) ................................................11-12

Timer C (0/1) Functional Block Diagram ....................................................................11-13

Timer 1(0/1) Control Register (T1CON0, T1CON1)...................................................12-4

Timer A and Timer 1(0/1) Pending Register (TINTPND) ...........................................12-5

Timer 1(0/1) Functional Block Diagram......................................................................12-6

SIO Module Control Register (SIOCON)....................................................................12-2

SIO Prescaler Register (SIOPS) ................................................................................12-3

SIO Functional Block Diagram ...................................................................................12-3

SIO Timing in Transmit/Receive Mode (Tx at falling edge, SIOCON.4=0) ................12-4

SIO Timing in Transmit/Receive Mode (Tx at rising edge, SIOCON.4=1).................12-4

SIO Timing in Receive-Only Mode (Rising edge start) ..............................................12-5

UART Control Register (UARTCON0, UARTCON1, UARTCON2) ...........................14-2

UART Interrupt Pending Register (UARTPND)..........................................................14-3

UART Parity Register .................................................................................................14-4

UART Data Register (UDATA0, UDATA1, UDATA2) ................................................14-5

UART Baud Rate Data Register (BRDATA0, BRDATA1, BRDATA2) .......................14-5

UART Functional Block Diagram................................................................................14-7

Timing Diagram for UART Mode 0 Operation ............................................................14-8



Connection Example for Multiprocessor Serial Data Communications .....................14-13

A/D Converter Control Register (ADCON) .................................................................15-2

A/D Converter Data Register (ADDATAH, ADDATAL) ..............................................15-3

A/D Converter Circuit Diagram ...................................................................................15-3

A/D Converter Timing Diagram ..................................................................................15-4

Recommended A/D Converter Circuit for Highest Absolute Accuracy ......................15-5

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER xiii

Number

18-5

18-6

18-7

18-8

18-9

19-1

19-2

19-3

19-4

19-5

20-1

20-2

21-1

21-2

22-1

22-2

22-3

22-4

16-1

16-2

16-3

16-4

16-5

16-6

17-1

17-2

17-3

18-1

18-2

18-3

18-4

List of Figures

(Concluded)

Number

PWM Control Register (PWMCON)........................................................................... 16-2

Block Diagram for PWM2 and PWM3........................................................................ 16-3

PWM Waveforms for PWM2, PWM3 ......................................................................... 16-4

PWM Clock to PWM2, PWM3 Output Delays ........................................................... 16-5

Block Diagram for PWM0 and PWM1........................................................................ 16-7

Decision Flowchart for PWM0 Programming Tip....................................................... 16-9

Pattern Generation Flow ............................................................................................ 17-1

PG Control Register (PGCON) .................................................................................. 17-2

Pattern Generation Circuit Diagram........................................................................... 17-2

Program Memory Address Space.............................................................................. 18-2

Flash Memory Control Register (FMCON) ................................................................ 18-4

Flash Memory User Programming Enable Register (FMUSR).................................. 18-4

Flash Memory Sector Address Register (FMSECH) ................................................. 18-5

Flash Memory Sector Address Register (FMSECL).................................................. 18-5

Sectors in User Program Mode ................................................................................. 18-6

Sector Erase Flowchart in User Program Mode ........................................................ 18-7

Byte Program Flowchart in a User Program Mode.................................................... 18-11

Program Flowchart in a User Program Mode ............................................................ 18-12

Input Timing for External Interrupts (Ports 4, Port 8.5, Port 8.6) ............................... 19-5

Input Timing for RESET ............................................................................................. 19-5

Stop Mode Release Timing Initiated by Interrupts..................................................... 19-6

Clock Timing Measurement at X

IN

............................................................................. 19-10

Operating Voltage Range .......................................................................................... 19-10

S3C84MB/F84MB 80-QFP Standard Package Dimension (in Millimeters)............... 20-1

S3C84MB/F84MB 80-TQFP Standard Package Dimension (in Millimeters) ............ 20-2

S3F84MBJ Pin Assignments (80-QFP) ..................................................................... 21-2

S3F84MBJ Pin Assignments (80-TQFP) ................................................................... 21-3

Development System Configuration .......................................................................... 22-2

TB84MB Target Board Configuration ........................................................................ 22-3

40-Pin Connectors for TB84MB (S3C84MBJ, 80-QFP Package) ............................. 22-6

TB84MB Cable for 80-QFP Adapter .......................................................................... 22-6

xiv S3C84MB/F84MB MICROCONTROLLER

8-1

8-2

8-3

8-4

9-1

9-2

14-1

16-1

16-2

18-1

Number

1-1

4-1

4-2

4-3

4-4

5-2

5-3

List of Tables

Number

S3C84MB/F84MB Pin Descriptions (80-QFP) ...........................................................1-6

Set 1, Bank 0 Registers..............................................................................................4-1



Page 8 Registers ........................................................................................................4-4

Interrupt Control Register Overview ...........................................................................5-7

Interrupt Source Control and Data Registers .............................................................5-9

S3C84MB/F84MB Set 1, Bank 0 Register Values after RESET ................................8-2



S3C84MB/F84MB Page 8 Register Values after RESET ..........................................8-5

S3C84MB/F84MB Port Configuration Overview ........................................................9-1

Port Data Register Summary......................................................................................9-2

Commonly Used Baud Rates Generated by BRDATA0, BRDATA1, BRDATA2 .......14-6

PWM0 and PWM1 Control and Data Registers .........................................................16-7

PWM Output "Stretch" Values for Extension Registers PWM0EX and PWM1EX .....16-8

ISP Sector Size...........................................................................................................18-3

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER xv

Number

21-1

21-2

22-1

22-2

22-3

19-1

19-2

19-3

19-4

19-5

19-6

19-7

19-8

19-9

19-10

19-11

List of Tables

(Continued)

Number

Absolute Maximum Ratings ....................................................................................... 19-2

D.C. Electrical Characteristics ................................................................................... 19-2

A.C. Electrical Characteristics ................................................................................... 19-5

Input/Output Capacitance .......................................................................................... 19-6

Data Retention Supply Voltage in Stop Mode ........................................................... 19-6

A/D Converter Electrical Characteristics ................................................................... 19-7

LVR(Low Voltage Reset) Circuit Characteristics ....................................................... 19-7

Flash Memory D.C. Electrical Characteristics ........................................................... 19-8

Flash Memory A.C. Electrical Characteristics ........................................................... 19-8

Main Oscillator Frequency (f

OSC1

)............................................................................. 19-9

Main Oscillator Clock Stabilization Time (t

ST1

).......................................................... 19-9

Descriptions of Pins Used to Read/Write the Flash ROM ......................................... 21-4

Operating Mode Selection Criteria............................................................................. 21-5

Power Selection Settings for TB84MB....................................................................... 22-4

Emulator Version Selection Settings for TB84MB ..................................................... 22-4

Using Single Header Pins as the Input Path for External Trigger Sources ............... 22-5

xvi S3C84MB/F84MB MICROCONTROLLER

List of Programming Tips

Description

Chapter 2: Address Spaces

Page

Number

Using the Page Pointer for RAM clear (Page 0, Page 1)..............................................................................2-6

Setting the Register Pointers ........................................................................................................................2-10

Using the RPs to Calculate the Sum of a Series of Registers ......................................................................2-11

Addressing the Common Working Register Area .........................................................................................2-15

Standard Stack Operations Using PUSH and POP ......................................................................................2-20

Chapter 11:

8-bit Timer A/B/C(0/1)

To generate 38 kHz, 1/3duty signal through P2.4 .........................................................................................11-9

To generate a one pulse signal through P2.4................................................................................................11-10

Using the Timer A ..........................................................................................................................................11-14

Using the Timer B ..........................................................................................................................................11-15

Using the Timer C(0)......................................................................................................................................11-16

Chapter 12: 16-bit Timer 1(0/1)

Using the Timer 1(0)......................................................................................................................................12-7

Chapter 13:

Serial I/O Port

Use Internal Clock to Transmit and Receive Serial Data..............................................................................13-5

Chapter 15: 10-Bit A/D Converter

Configuring A/D Converter ............................................................................................................................15-6

Chapter 17:

Pattern Generation Module

Using the Pattern Generation........................................................................................................................17-3

Chapter 18:

Embedded FLASH Memory Interface

Sector Erase ..................................................................................................................................................18-8

Programming..................................................................................................................................................18-13

Reading ..........................................................................................................................................................18-15

Hard Lock Protection .....................................................................................................................................18-16

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER xvii

Register

Identifier

ADCON

BRDATA0

BRDATA1

BRDATA2

BTCON

FMCON

FMUSR

FMSECH

FMSECL

List of Register Descriptions

Full Register Name Page

Number

A/D Converter Control Register ................................................................................. 4-6

UART0 Baud Rate Data Register .............................................................................. 4-7



Basic Timer Control Register ..................................................................................... 4-8

Flash Memory Control Register ................................................................................. 4-11

Flash Memory User Programming Control Register .................................................. 4-12

Flash Memory Sector Address Register (High Byte) ................................................. 4-12

Flash Memory Sector Address Register (Low Byte) .................................................. 4-12

P0CON

P1CON

P1CONEX

P2CONH

P2CONL

P3CONH

P3CONL

P4CONH

P4CONL

P4INT

P4INTPND

P5CONH

P5CONL

P6CON

P7CON

P8CONH

P8CONL

P8INTPND

Port 0 Control Register............................................................................................... 4-17


Port 1 Extension Control Register.............................................................................. 4-19

Port 2 Control Register (High Byte)............................................................................ 4-20

Port 2 Control Register (Low Byte) ............................................................................ 4-21





Port 4 Interrupt Control Register ................................................................................ 4-26

Port 4 Interrupt Pending Register............................................................................... 4-27







Port 8 Interrupt Pending Register............................................................................... 4-34

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER xix

Register

Identifier

PWM0EX/1EX

PWMCON

List of Register Descriptions

(Continued)


Number

PWM 0/1 Extension Register......................................................................................4-37

PWM Control Register ...............................................................................................4-38

T1CON0

T1CON1

TACON

TBCON

TCCON0

TCCON1

TINTPND

Timer 1(0) Control Register ........................................................................................4-46

Timer 1(1) Control Register ........................................................................................4-47

Timer A Control Register ............................................................................................4-48

Timer B Control Register ............................................................................................4-49

Timer C(0) Control Register .......................................................................................4-50

Timer C(1) Control Register .......................................................................................4-51

Timer A,1 Interrupt Pending Register .........................................................................4-52

UARTPRT UART0, 1, 2 Parity Control Register ..........................................................................4-57

xx S3C84MB/F84MB MICROCONTROLLER

List of Instruction Descriptions

Instruction

Mnemonic


Number

ADD

AND

BAND

BCP

BITC

Add ............................................................................................................................. 6-15

Logical AND ............................................................................................................... 6-16

Bit AND....................................................................................................................... 6-17

Bit Compare ............................................................................................................... 6-18

Bit Complement.......................................................................................................... 6-19

BITS

BOR

BTJRF

BTJRT

BXOR

CALL

CCF

CLR

COM

CP

CPIJNE

DA

DEC

DECW

Bit Set ......................................................................................................................... 6-21

Bit OR ......................................................................................................................... 6-22

Bit Test, Jump Relative on False ............................................................................... 6-23

Bit Test, Jump Relative on True................................................................................. 6-24

Bit XOR....................................................................................................................... 6-25

Call Procedure............................................................................................................ 6-26

Complement Carry Flag ............................................................................................. 6-27

Clear ........................................................................................................................... 6-28

Complement ............................................................................................................... 6-29

Compare..................................................................................................................... 6-30

Compare, Increment, and Jump on Non-Equal ......................................................... 6-32

Decimal Adjust ........................................................................................................... 6-33

Decrement .................................................................................................................. 6-35

Decrement Word ........................................................................................................ 6-36

DIV

DJNZ

EI

ENTER

EXIT

Divide (Unsigned)....................................................................................................... 6-38

Decrement and Jump if Non-Zero.............................................................................. 6-39

Enable Interrupts ........................................................................................................ 6-40

Enter ........................................................................................................................... 6-41

Exit.............................................................................................................................. 6-42

IDLE Idle Operation............................................................................................................. 6-43

INC Increment ................................................................................................................... 6-44

INCW Increment Word.......................................................................................................... 6-45

IRET Interrupt Return .......................................................................................................... 6-46

JP Jump........................................................................................................................... 6-47

JR

LD

LDB

Jump Relative............................................................................................................. 6-48

Load............................................................................................................................ 6-49

Load Bit ...................................................................................................................... 6-51

S3C84MB/F84MB_UM_REV1.00 MICROCONTROLLER xxi

List of Instruction Descriptions

(Continued)

Instruction

Mnemonic

LDC/LDE

LDCD/LDED

LDCPD/LDEPD

LDCPI/LDEPI

RLC

RR

RRC

SB0

SB1

SBC

SCF

MULT

NEXT

NOP

OR

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

RCF

RET

RL

SRP/SRP0/SRP1

STOP

SUB

SWAP

TCM

TM

WFI

XOR


Number

Load Memory..............................................................................................................6-52

Load Memory and Decrement ....................................................................................6-54

Load Memory with Pre-Decrement.............................................................................6-56

Load Memory with Pre-Increment ..............................................................................6-57

Multiply (Unsigned) .....................................................................................................6-59

Next.............................................................................................................................6-60

No Operation ..............................................................................................................6-61

Logical OR ..................................................................................................................6-62

Pop from Stack ...........................................................................................................6-63

Pop User Stack (Decrementing).................................................................................6-64

Pop User Stack (Incrementing) ..................................................................................6-65

Push to Stack..............................................................................................................6-66

Push User Stack (Decrementing) ...............................................................................6-67

Push User Stack (Incrementing) ................................................................................6-68

Reset Carry Flag.........................................................................................................6-69

Return .........................................................................................................................6-70

Rotate Left ..................................................................................................................6-71

Rotate Left through Carry ...........................................................................................6-72

Rotate Right................................................................................................................6-73

Rotate Right through Carry.........................................................................................6-74

Select Bank 0..............................................................................................................6-75

Select Bank 1..............................................................................................................6-76

Subtract with Carry .....................................................................................................6-77

Set Carry Flag.............................................................................................................6-78

Set Register Pointer....................................................................................................6-80

Stop Operation............................................................................................................6-81

Subtract ......................................................................................................................6-82

Swap Nibbles..............................................................................................................6-83

Test Complement under Mask ...................................................................................6-84

Test under Mask .........................................................................................................6-85

Wait for Interrupt .........................................................................................................6-86

Logical Exclusive OR..................................................................................................6-87

xxii S3C84MB/F84MB MICROCONTROLLER

S3C84MB/F84MB_UM_REV1.00

1

PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. The major CPU features are:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode released by interrupt or reset

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.

S3C84MB/F84MB MICROCONTROLLER

The S3C84MB/F84MB single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process, based on Samsung’s latest CPU architecture.

The S3C84MB is a microcontroller with a 64K-byte mask-programmable ROM embedded.

The S3F84MB is a microcontroller with a 64K-byte Full-Flash ROM embedded.

Using a proven modular design approach, Samsung engineers have successfully developed the

S3C84MB/F84MB by integrating the following peripheral modules with the powerful SAM8RC core:

— Nine programmable I/O ports, including eight 8-bit ports and one 6-bit ports, for a total of 70 pins.

— Ten bit-programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).

— Four 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes.

— 3 asynchronous UART

— 2 synchronous SIO

— 15-channel A/D converter

The S3C84MB/F84MB is versatile microcontroller for CD-ROM and ADC application, etc. They are currently available in 80-pin QFP and 80-pin TQFP package.

1-1


FEATURES

CPU

• core

Memory

•

2064-bytes internal register file

•

64K-bytes internal program memory

- S3C84MB: Mask ROM

- S3F84MB: Flash type memory

Oscillation Sources

•

Ceramic

•

CPU clock divider (1/1, 1/2, 1/8, 1/16)

Instruction Set

• instructions

•

IDLE and STOP instructions added for powerdown modes

Instruction Execution Time

•

400 ns at 10-MHz f

OSC

(minimum)

Interrupts

•

27 interrupt sources with 27 vectors.

•

8 level, 27 vector interrupt structure

I/O Ports

•

Total 70 bit-programmable pins

Timers and Timer/Counters

•

One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog-timer function.

•

One 8-bit timer/counter (Timer A) with three operating modes; Interval mode, capture mode and PWM mode.

•

One 8-bit timer/counter (Timer B) Carrier frequency (or PWM) generator.

•

Two 8-bit timer with PWM mode (Timer C0,C1)

•

Two 16-bit capture timer/counter (Timer 10,11) with two operating modes; Interval mode,

Capture mode for pulse period or duty.


•

A/D Converter

•

15 analog input channels

•

Max 2.5MHz f

ADC

clock.

PWM

•

Two 14-bit PWM

•

Two 8-bit PWM

Asynchronous UART

•

Full duplex 3 channels UARTs

•

Programmable baud rate

•

Supports serial data transmit/receive operations with 8-bit, 9-bit in UART

Synchronous SIO

•

Programmable baud rate

•

Two synchronous serial I/O modules

Pattern Generation Module

•

Pattern generation module triggered by timer match signal and S/W.

Operating Temperature Range

•

–40°C to + 85°C

Operating Voltage Range

•

2.4 V to 5.5 V at 10MHz f

OSC

•

4.5 V to 5.5 V at 16MHz f

OSC

Package Type

•

80 pin QFP, 80 pin TQFP

Built-in RESET circuit (LVR)

•

•

Low Voltage check to make system reset

V

LVR

= 2.8 / 4.0 V (by Smart Option)

Smart Option

1-2


BLOCK DIAGRAM

AV

REF

AV

SS

P0.0-P0.7

P1.0-P1.7

A/D Port 0 Port 1

X

IN

X

OUT

RESETB

P2.7/TAOUT

P2.6/TACAP

P2.5/TACK

P2.4/TBOUT

P3.7/TCOUT1

P3.6/TCOUT0

P3.4/T1OUT0

P3.2/T1CAP0

P3.0/T1CK0

P3.5/T1OUT1

P3.3/T1CAP1

P3.1/T1CK1

P2.2/SCK0

P2.1/SI0

P2.0/SO0

P8.0/SO1

P8.1/SI1

P8.2/SCK1

P5.3/RXD0

P5.2/TXD0

P5.1/RXD1

P5.0/TXD1

P1.1/RXD2

P1.0/TXD2

OSC/RESETB

8-Bit

Basic Timer

8-Bit

Timer

/CounterA,B

8-Bit

Timer/Counter

C0,C1

16-Bit

Timer

/Counter10,11

SIO0,1/

UART0,1,2

I/O Port and Interrupt Control

SAM8 RC CPU

64K-Byte

ROM

14bit PWM0,1

8bit PWM2,3

PGM

2064-Byte

RAM

Port 8 Port 7

Port 2

Port 3

Port 4

Port 5

Port 6

P1.4/PWM0

P1.5/PWM1

P1.6/PWM2

P1.7/PWM3

P0.7~P0.0

PG7~PG0

P8.0-P8.5/

INT8,INT9

P7.0-P7.7/

ADC0~ADC7

Figure 1-1. S3C84MB/F84MB Block Diagram

P2.0-P2.7

P3.0-P3.7

P4.0-P4.7/

INT0~INT7

P5.0-P5.7

P6.0-P6.7

ADC8~ADC14

1-3


PIN ASSIGNMENT


TAOUT/P2.7

TACAP/P2.6

TACK/P2.5

TBPWM/P2.4

P2.3

SCK0/P2.2

SI0/P2.1

SO0/P2.0

P5.7

SDAT/P5.6

SCLK/P5.5

VDD1

VSS1

X

OUT

X

IN

TEST

P5.4

RxD0/P5.3

RESETB

TxD0/P5.2

RxD1/P5.1

TxD1/P5.0

TCOUT1/P3.7

TCOUT0/P3.6

15

16

17

18

11

12

13

14

7

8

9

10

3

4

5

6

1

2

19

20

21

22

23

24

S3C84MB/F84MB

(80-QFP-1420C)

50

49

48

47

54

53

52

51

58

57

56

55

64

63

62

61

60

59

46

45

44

43

42

41

P8.0/SO1

P8.1/SI1

P8.2/SCK1

P8.3

P8.4/INT8

P8.5/INT9

P6.0/ADC8

P6.1/ADC9

P6.2/ADC10

P6.3/ADC11

P6.4/ADC12

VDD2

VSS2

P6.5/ADC13

P6.6/ADC14

P6.7

P7.0/ADC0

P7.1/ADC1

P7.2/ADC2

P7.3/ADC3

AVSS

AVREF

P7.4/ADC4

P7.5/ADC5

Figure 1-2. S3C84MB/F84MB Pin Assignment (80-QFP)

1-4


TACK/P2.5

TBPWM/P2.4

P2.3

SCK0/P2.2

SI0/P2.1

SO0/P2.0

P5.7

SDAT/P5.6

SCLK/P5.5

VDD1

VSS1

X

OUT

X

IN

TEST

P5.4

RxD0/P5.3

RESETB

TxD0/P5.2

RxD1/P5.1

TxD1/P5.0

17

18

19

20

13

14

15

16

7

8

5

6

9

10

11

12

3

4

1

2

S3C84MB/F84MB

(80-TQFP-1212)

44

43

42

41

48

47

46

45

56

55

54

53

52

51

50

49

60

59

58

57

P8.2/ SCK1

P8.3

P8.4/INT8

P8.5/INT9

P6.0/ ADC8

P6.1/ ADC9

P6.2/ ADC10

P6.3/ ADC11

P6.4/ ADC12

VDD2

VSS2

P6.5/ ADC13

P6.6/ ADC14

P6.7

P7.0/ADC0

P7.1/ADC1

P7.2/ADC2

P7.3/ADC3

AVSS

AVREF

Figure 1-3. S3C84MB/F84MB Pin Assignment (80-TQFP)

1-5

PRODUCT OVERVIEW S3C84MB/F84MB_UM_REV1.00

PIN DESCRIPTIONS

Pin

Name

Pin

Type

Table 1-1. S3C84MB/F84MB Pin Descriptions (80-QFP)

Pin

Description

P0.0–P0.7 I/O Bit programmable port; input or output mode selected by software; input or push-pull output.

Software assignable pull-up.

Alternately, P0.0–P0.7 can be used as the PG output port (PG0–PG7).



Circuit

Type

Pin

Number

Share

Pins

PWM0,PWM1

PWM2,PWM3



Alternately, P2.0~P2.7 can be used as I/O for

TIMERA, TIMERB, SIO

SI0

SCK0

TBPWM

TACK

TACAP

TAOUT



Alternately, P3.0~P3.7 can be used as I/O for

TIMERC0/C1, TIMER10/11

T1CK1

T1CAP0

T1CAP1

T1OUT0

T1OUT1

TCOUT0

TCOUT1

1-6


Pin

Name

Pin

Type

Table 1-1. S3C84MB/F84MB Pin Descriptions (80-QFP) (Continued)

Pin

Description



P4.0–P4.7 can alternately be used as inputs for external interrupts INT0–INT7, respectively (with noise filters and interrupt controller)



Alternately, P5.0~P5.3 can be used as I/O for serial por, UART0, UART1, respectively.

Circuit

Type

Pin

Number

Share

Pins

INT7

RxD1

TxD0

RxD0 analog input pins for A/D converter modules. used as analog input pins for A/D converter modules.



P8.4, P8.5 can alternately be used as inputs for external interrupts INT8, INT9, respectively (with noise filters and interrupt controller)

ADC14

ADC7

D,D-1 64-59 INT8,INT9

SO1

SI1

SCK1

1-7


Pin

Name

AD0–AD7

TEST

VDD1, VDD2,

VSS1, VSS2

X

IN

, X

OUT

AVREF, AVSS

RxD0, RxD1

TxD0, TxD1

TACK

TACAP

TAOUT

TBPWM

TCOUT0

TCOUT1

T1CK0

T1CK1

T1CAP0

T1CAP1

T1OUT0

T1OUT1

SI,SO,SCK

RESETB

Table 1-1. S3C84MB/F84MB Pin Descriptions (80-QFP) (Continued)

Pin

Type

I

–

I/O Serial data RxD pin for receive input and transmit output (mode 0)

O Serial data TxD pin for transmit output and shift clock input (mode 0)

I

I

External clock input pins for timer A

Capture input pins for timer A

O

O

O

I

Pin

Description

Analog input pins for A/D converter module.

Alternatively used as general-purpose digital input port 7.

A/D converter reference voltage and ground

Pulse width modulation output pins for timer A

Carrier frequency output pins for timer B

Timer C 8-bit PWM mode output or counter match toggle output pins

External clock input pins for timer 1

Circuit

Type

–

D 20,

D

D

D

D

3

2

1

4

P2.5

P2.6

P2.7

P2.4

D 24, P3.6,P3.7

D

Pin

Number

42-39

43, 44

D 18,

39, 30

Share

Pins

–

P5.3,P5.1

P5.2,P5.0

P3.0,P3.1

I Capture input pins for timer 1 D 28, 27 P3.2,P3.3

D 26, P3.4,P3.5

O Timer 1 16-bit PWM mode output or counter match toggle output pins

I/O Synchronous SIO pins

I

I

–

System reset pin (pull-up resistor: 240 k

Ω)

Pull – down register connected internally

Power input pins

– Main oscillator pins

D

B 19 –

–

–

–

7, 8, 9 P2.1,P2.0,

P2.2

16

12, 53,

13, 52

15, 14

–

–

–

1-8


PIN CIRCUITS

V

DD

Pull-Up

Resistor

In

Schmitt Trigger

Figure 1-4. Pin Circuit Type B (RESETB)

Data

Output

Disable

Figure 1-5. Pin Circuit Type C

V

DD

P-CH

N-CH

Out

1-9


V

DD

Pull-Up

Resistor

Pull-Up

Enable

Data

Output

Disable

Pin Circuit

Type C

I/O

Figure 1-6. Pin Circuit Type D (P0, P1, P2 except P2.3, P3, P8 except P8.4, P8.5)

V

DD

Pull-Up

Resistor

Pull-Up

Enable

Data

Output

Disable

Pin Circuit

Type C

I/O

Ext.INT

Noise

Filter

Input

Normal

Figure 1-7. Pin Circuit Type D-1 (P4, P8.4, P8.5)

1-10


In

ADC In

Enable

Data

Open-drain

Enable

Data

Output

Disable

To ADC

Figure 1-8. Pin Circuit Type E (ADC0-ADC7)

Data

N-Channel

ADC En

I/O

ADC

Figure 1-9. Pin Circuit Type F (P6)

V

DD

V

DD

P-CH

N-CH

I/O

Pull-up

Enable

Digital Input

Figure 1-10. Pin Circuit Type G (P5.7-P5.4)

1-11


2

ADDRESS SPACES

OVERVIEW

The S3C84MB/F84MB microcontroller has two types of address space:

— Internal program memory (ROM)

— Internal register file (RAM)

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.

The S3C84MB/F84MB has an internal 64-Kbyte mask-programmable ROM/FLASH ROM and 2064-byte RAM.

2-1

ADDRESS SPACES S3C84MB/F84MB_UM_REV1.00

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program codes or table data. The S3C84MB has 64-Kbytes of internal mask programmable program memory. The program memory address range is therefore 0H–FFFFH (see Figure 2-1).

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which a program execution starts after a reset is 0100H.

(Decimal)

65,535 64-KByte

(HEX)

FFFFH

255 0FFH

Interrupt

Vector Area

0 0H

Figure 2-1. Program Memory Address Space

2-2


SMART OPTION

Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The default value of ROM is FFH.

ROM Address : 003CH

.5

.4

.3

.2

MSB

.7

.6

.1

.0

LSB

MSB .7

.6

Not Used

ROM Address : 003DH

.5

.4

.3

.2

.1

.0

LSB

MSB .7

Not Used

.6

IVC Control Bit In STOP Mode

0

1

Disable IVC in STOP

Always Enable

Not Used

ROM Address : 003EH

.5

.4

.3

.2

Internal V

DD

Selection Bit

00

01

10

11

(2)

V

DD

V

DD

= 3.3V

= 4.5V

V

DD

= 5.5V

Not Used

.1

.0

LSB

ISP Protection

Enable Bit

0

1

Enable

Disable

00

01

10

11

Protection Size

Selection Bit

(1)

256 Byte

512 Byte

1024 Byte

2048 Byte

MSB .7

.6

ROM Address : 003FH

.5

.4

.3

.2

.1

.0

LSB

Not Used

LVR Enable Control Bit

0

1

Enable LVR

Disable LVR

LVR Level Selection Bit

01

10

Others

2.8 V

4.0 V

Not Used

NOTES :

1. Protection Start Address is ‘0100h’

2. This internal V

DD

level is used when the IVC is disabled in STOP mode.

3. The value of unused bits of 03CH,03DH,03EH and 03FH must be logic "1"

Figure 2-2. Smart Option

2-3


REGISTER ARCHITECTURE

In the S3C84MB/F84MB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In addition, set 2 is logically expanded

8 separately addressable register pages, page 0–page 7.

In case of S3C84MB/F84MB the total number of addressable 8-bit registers is 2,164. Of these 2,164 registers, 16 bytes are for CPU and system control registers, 84 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 2,048 registers are for general-purpose use.

You can always address set 1 register locations, regardless of which of the 9 register pages is currently selected.

Set 1 locations, however, can only be addressed using direct addressing modes.

The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer

(PP).

Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1.

Table 2-1. S3C84MB/F84MB Register Type Summary

Register Type

General-purpose registers (including 16-byte common working register area, the 192-byte prime register area, and the 64-byte set 2 area)

CPU and system control registers

Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

Number of Bytes

2,064

16

84

2,164

2-4


FFH

Set 1

Bank 1

Bank 0

System and Peripheral

Control Registers

(Register Addressing Mode)

E0H

64

Bytes

DFH

D0H

CFH

System and Peripheral

Control Registers


General Purpose Register


C0H

Page 7

Page 6

Page 5

Page 4

Page 3

Page 2

Page 1

Page 0

32

Bytes

FFH

Set 2

C0H

BFH

General-Purpose

Data Registers

Page

Page

Page

Page

Mode, and Stack Operations)

Page

Page

Page

Page 0

192

Bytes

Prime

Data Registers

(All Addressing Modes )

00H

Figure 2-3. Internal Register File Organization

256

Bytes

13H

2-5


REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 2,064-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C84MB/F84MB microcontroller, a paged register file expansion is implemented for data registers, and the register page pointer must be changed to address other pages.

After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always

"0000", automatically selecting page 0 as the source and destination page for register addressing.

MSB .7

.6

Register Page Pointer (PP)

DFH, Set1, R/W

.5

.4

.3

.2

.1

.0

LSB

Destination page selection bits :

0000

...

1000

Destination : Page 0

...

Destination : Page 8

Source page selection bits :

0000

...

1000

Source : Page 0

...

Source : Page 8

NOTE: In the S3C84MB/F84MB microcontroller, pages 0~8 are implemented.

A hardware reset operation writes the 4-bit destination and source values

shown above to the register page pointer. These values should be modified to

address other pages.

Figure 2-4. Register Page Pointer (PP)

)

PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1)

LD

RAMCL0 CLR

CLR

LD

RAMCL1 CLR

CLR

R0,#0FFH

@R0

@R0

R0,#0FFH

@R0

@R0

; Page 0 RAM clear starts

; R0 = 00H

; Page 1 RAM clear starts

; R0 = 00H

NOTE:

You should refer to page 6-40 and use DJNZ instruction properly when DJNZ instruction is used in your program.

2-6


REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and

bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing.

The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 64 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common working register area (C0H–CFH). You can use the common working register area as a “scratch” area for data operations being performed in other areas of the register file.

Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, “Addressing Modes.”)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another

64 bytes of register space. This expanded area of the register file is called set 2. For the S3C84MB/F84MB, the set 2 address range (C0H–FFH) is accessible on pages 0-7.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only

Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register

Indirect addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-7


PRIME REGISTER SPACE

The lower 192 bytes (00H–BFH) of the S3C84MB/F84MB's eight 256-byte register pages is called prime register

area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing

Modes.")

The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, or 1 you must set the register page pointer (PP) to the appropriate source and destination values.

FFH

F0H

E0H

D0H

C0H

Bank 0

Set 1

Bank 1

CPU and system control

General-purpose

Peripheral and I/O

FFH

FFH

FFH

Page 7

…

Page 0

Set 2

C0H

BFH

Page 0

Prime

Space

00H

Figure 2-5. Set 1, Set 2, Prime Area Register

13H

2-8


WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2.

The base addresses for the two selected 8-byte register slices are contained in register pointers

RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

1 1 1 1 1 X X X

RP1 (Registers R8-R15)

Each register pointer points to one 8-byte slice of the register space, selecting a total 16byte working register block.

0 0 0 0 0 X X X

RP0 (Registers R0-R7)

~

Slice 32

Slice 31

Slice 2

Slice 1

~

10H

FH

8H

7H

0H

FFH

F8H

F7H

F0H

Set 1

Only

CFH

C0H

Figure 2-6. 8-Byte Working Register Areas (Slices)

2-9


USING THE REGISTER POINTERS

After a reset, RP# point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.

(see Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You can not, however, use the register pointers to select a working register space in set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice

(see Figure 2-6).

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements.

)

PROGRAMMING TIP — Setting the Register Pointers

RP0

← no change, RP1 ← 48H,

RP0

← no change, RP1 ← 0F8H

Register File

Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

0 0 0 0 0 X X X

RP0

8-Byte Slice

8-Byte Slice

FH (R15)

8H

7H

0H (R0)

16-Byte

Contiguous

Working

Register block

Figure 2-7. Contiguous 16-Byte Working Register Block

2-10


8-Byte Slice

CFH (R15)

C8H (R8)

1 1 0 0 1 X X X

RP1

0 0 0 0 0 X X X

RP0

Register File

Contains 32

8-Byte Slices

8-Byte Slice

7H (R7)

0H (R0)

Figure 2-8. Non-Contiguous 16-Byte Working Register Block

16-Byte

Non-Contiguous

Working

Register block

)

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively:

RP0

← R0 + R1

R0

← R0 + R3 + C

R0

← R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used:

80H

← (80H) + (82H) + C

80H

← (80H) + (84H) + C

← (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-11


REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific

8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

Rn+1 n = Even address

Figure 2-9. 16-Bit Register Pair

2-12


Special-Purpose Registers

FFH

Bank 1 Bank 0

Control

Registers

E0H

D0H

C0H

BFH

System

Registers

CFH

RP1

Register

Pointers

RP0

Each register pointer (RP) can independently point to one of the 24 (8-byte) "slices" of the register file

(other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH

(that is, to the common working register area).

General-Purpose Register

FFH

C0H

Prime

Registers

Set 2

NOTE:

In the S3C84MB/F84MB microcontroller, pages 0-8 are implemented. Pages 0-7 contain all of the addressable registers in the internal register file.

00H

Register Addressing Only

Can be pointed by Register Pointer

Page 0-8

All

Addressing

Modes

Page 0-7

Indirect Register,

Indexed Addressing

Modes

Figure 2-10. Register File Addressing

2-13


COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations

C0H–CFH, as the active 16-byte working register block:

This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.

FFH

F0H

E0H

D0H

C0H

Set 1

Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH.

RP0 =

RP1 =

1100

1100

0000

1000

FFH

FFH

FFH

Page 7

...

Page0

Set 2

C0H

BFH

Page 0

Prime

Space

00H

Figure 2-11. Common Working Register Area

13H

2-14


)

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.

Examples 1: LD 0C2H,40H ; Invalid addressing mode!

Use working register addressing instead:

#0C0H

R2,40H

Examples 2: ADD 0C3H,#45H ; Invalid addressing mode!

Use working register addressing instead:

#0C0H

R3,#45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).

— The five high-order bits in the register pointer select an 8-byte slice of the register space.

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction

"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-15


Selects

RP0 or RP1

Address OPCODE

RP0

RP1

Register pointer provides five high-order bits

4-bit address provides three low-order bits

Together they create an

8-bit register address

Figure 2-12. 4-Bit Working Register Addressing

RP0

0 1 1 1 0 0 0 0

0 1 1 1 0 1 1 0

Register address

(76H)

Selects RP0

RP1

0 1 1 1 1 0 0 0

R6 OPCODE

0 1 1 0 1 1 1 0

Instruction

'INC R6'

Figure 2-13. 4-Bit Working Register Addressing Example

2-16


8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing. Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address, the three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 3 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from

RP1 and the three address bits from the instruction are concatenated to form the complete register address,

0ABH (10101011B).

These address bits indicate 8-bit working register addressing

RP0

RP1

Selects

RP0 or RP1

1 1 0 0

Address

8-bit logical address

Three low-order bits Register pointer provides five high-order bits

8-bit physical address

Figure 2-14. 8-Bit Working Register Addressing

2-17


RP0

0 1 1 0 0 0 0 0

Selects RP1

R11

1 1 0 0 1 0 1 1

8-bit address form instruction

'LD R11, R2'

Specifies working register addressing

RP1

1 0 1 0 1 0 0 0

1 0 1 0 1 0 1 1

Register address

(0ABH)

Figure 2-15. 8-Bit Working Register Addressing Example

2-18


SYSTEM AND USER STACK

The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C84MB/F84MB architecture supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS registers are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15.

High Address

Top of stack

PCL

PCH

PCL

PCH

Flags

Top of stack

Stack contents after a call instruction

Stack contents after an interrupt

Low Address

Figure 2-16. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL, SPH)

Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.

The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3C84MB/F84MB, the SPL must be initialized to an

8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary.

When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H".

2-19


)

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

; (Normally, the SPL is set to 0FFH by the initialization

•

•

•

PUSH

PUSH

PUSH

PUSH

•

PP

RP0

RP1

R3

•

•

; Stack address 0FEH

← PP

; Stack address 0FDH

← RP0

; Stack address 0FCH

← RP1

; Stack address 0FBH

← R3

R3

← Stack address 0FCH

RP0

← Stack address 0FEH

2-20


3

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM8RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are:

— Indirect Register (IR)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

3-1

ADDRESSING MODES S3C84MB/F84MB_UM_REV1.00

REGISTER ADDRESSING MODE (R)

In Register addressing mode (R), the operand value is the content of a specified register or register pair

(see Figure 3-1).

Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Register File

Point to One

Register in Register

File

Value used in

Instruction Execution

OPERAND

Sample Instruction:

DEC CNTR ; Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File

MSB Point to

RP0 ot RP1

RP0 or RP1

Program Memory

4-bit

Working Register dst src

OPCODE

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD R1, R2

3 LSBs

Point to the

Working Register

(1 of 8)

OPERAND

; Where R1 and R2 are registers in the currently

selected working register area.

Selected

RP points to start of working register block

Figure 3-2. Working Register Addressing

3-2


INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using the Indirect Register addressing mode.

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Point to One

Register in Register

File

Address of Operand used by Instruction

Register File

ADDRESS

OPERAND

Value used in

Instruction Execution

Sample Instruction:

RL @SHIFT ; Where SHIFT is the label of an 8-bit register address

Figure 3-3. Indirect Register Addressing to Register File

3-3


INDIRECT REGISTER ADDRESSING MODE (Continued)


Register File

Example

Instruction

References

Program

Memory

Program Memory dst

OPCODE

Points to

Register Pair

Sample Instructions:

CALL

JP

@RR2

@RR2

REGISTER

PAIR

Value used in

Instruction

Program Memory

OPERAND

16-Bit

Address

Points to

Program

Memory

Figure 3-4. Indirect Register Addressing to Program Memory

3-4


INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4-bit

Working

Register

Address

Program Memory dst src

OPCODE

~

3 LSBs

Point to the

Working Register

(1 of 8)

~

ADDRESS

Sample Instruction:

OR R3, @R6

Value used in

Instruction

OPERAND

~

~

Selected

RP points to start fo working register block

Figure 3-5. Indirect Working Register Addressing to Register File

3-5


INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File

MSB Points to

RP0 or RP1

RP0 or RP1

Selected


4-bit Working

Register Address

Example Instruction

References either

Program Memory or

Data Memory

Program Memory dst src

OPCODE

Next 2-bit Point

to Working

Register Pair

(1 of 4)

LSB Selects

Register

Pair

Program Memory or

Data Memory

Value used in

Instruction

OPERAND

16-Bit address points to program memory or data memory


LDC

LDE

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6


INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address

(see Figure 3-9).

The only instruction that supports indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory, when implemented.

Register File

RP0 or RP1

Two-Operand

Instruction

Example

Value used in

Instruction

+

Program Memory

Base Address dst/src x

OPCODE

3 LSBs

Point to One of the

Working Register

(1 of 8)

~

~

OPERAND

~

~

Selected RP points to start of working register block

INDEX

Sample Instruction:

LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7


INDEXED ADDRESSING MODE (Continued)


4-bit Working

Register Address

Program Memory

OFFSET dst/src x

OPCODE

MSB Points to

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

(1 of 4)

LSB Selects

8-Bits

+

16-Bits

~

Register File

RP0 or RP1

~

Selected


Register

Pair

Program Memory or

Data Memory

16-Bit address added to offset

16-Bits

OPERAND

Value used in

Instruction


LDC R4, #04H[RR2]

LDE R4,#04H[RR2]

; The values in the program address (RR2 + 04H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8


INDEXED ADDRESSING MODE (Continued)

Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4-bit Working

Register Address

Program Memory

OFFSET

OFFSET dst/src src

OPCODE

NEXT 2 Bits

Point to Working

Register Pair

~

Register

Pair

~

Selected


16-Bit address added to offset

LSB Selects

16-Bits

+

16-Bits

Program Memory or

Data Memory

16-Bits

OPERAND

Value used in

Instruction


LDC

LDE

R4, #1000H[RR2]

R4,#1000H[RR2]

; The values in the program address (RR2 + 1000H)




Figure 3-9. Indexed Addressing to Program or Data Memory

3-9


DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Program Memory

Upper Address Byte

Lower Address Byte dst/src "0" or "1"

OPCODE

Memory

Address

Used

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory


LDC

LDE

R5,1234H

R5,1234H

; The values in the program address (1234H)




Figure 3-10. Direct Addressing for Load Instructions

3-10


DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory

Address

Used

Upper Address Byte

Lower Address Byte

OPCODE


JP C,JOB1

CALL DISPLAY

; Where JOB1 is a 16-bit immediate address

; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11


INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.

Program Memory

Current

Instruction dst

OPCODE

Next Instruction

LSB Must be Zero

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H ; The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12


RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current Instruction

Displacement

OPCODE

Current

PC Value

Signed

Displacement Value

+


JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13


IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD R0,#0AAH

Figure 3-14. Immediate Addressing

3-14


4

CONTROL REGISTERS

OVERVIEW

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual.

The locations and read/write characteristics of all mapped registers in the S3C84MB/F84MB register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and Power-

Down."

Register Name

Timer B control register

Timer B data register (high byte)

Timer B data register (low byte)

Basic timer control register

Clock control register

System flags register

Register pointer 0

Register pointer 1

Stack pointer (high byte)

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Register page pointer

Table 4-1. Set 1, Bank 0 Registers

Mnemonic

TBCON

TBDATAH

TBDATAL

BTCON

CLKCON

FLAGS

RP0

RP1

SPH

SPL

IPH

IPL

IRQ

IMR

SYM

PP

Decimal Hex R/W

208 D0H R/W

209 D1H R/W

210 D2H R/W

211 D3H R/W

212 D4H R/W

213 D5H R/W

214 D6H R/W

215 D7H R/W

216 D8H R/W

217 D9H R/W

218 DAH R/W

219 DBH R/W

220 DCH R

221 DDH R/W

222 DEH R/W

223 DFH R/W

4-1

CONTROL REGISTERS S3C84MB/F84MB_UM_REV1.00

Register Name

Port 0 data register









Timer A/1 interrupt pending register

Timer A control register

Timer A data register

Timer A counter register

Port 8 control register (high byte)

Port 8 control register (low byte)

Port 8 interrupt/pending register

Port 0 control register










Port 4 interrupt control register

Port 4 interrupt/pending register

Basic timer counter register

Interrupt priority register


TACNT

P8CONH

P8CONL

P8INTPND

P0CON

P1CON

P2CONH

P2CONL

P3CONH

P3CONL

P4CONH

P4CONL

P5CONH

P5CONL

Mnemonic

P0

P1

P2

P3

P4

P5

P6

P7

P8

TINTPND

TACON

TADATA

Decimal

224

225

226

227

228

229

230

231

232

233 E9H R/W

234 EAH R/W

235

236

Hex

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

EBH

ECH

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

237 EDH R/W

238 EEH R/W

239 EFH R/W

240 F0H R/W

241 F1H R/W

242 F2H R/W

243 F3H R/W

244 F4H R/W

245 F5H R/W

246 F6H R/W

247 F7H R/W

248 F8H R/W

249 F9H R/W

P4INT

P4INTPND

250 FAH R/W

251 FBH R/W

Location FCH is factory use only

BTCNT 253

Location FEH is not mapped.

IPR

FDH R

255 FFH R/W

4-2


Register Name

SIO data register

SIO Control register

UART0 data register

UART0 control register

UART0 baud rate data register

UART0,1 pending register

Timer 1(0) data register (high byte)

Timer 1(0) data register (low byte)

Timer 1(1) data register (high byte)

Timer 1(1) data register (low byte)

Timer 1(0) control register

Timer 1(1) control register

Timer 1(0) counter register (high byte)

Timer 1(0) counter register (low byte)

Timer 1(1) counter register (high byte)

Timer 1(1) counter register (low byte)

Timer C(0) data register

Timer C(1) data register

Timer C(0) control register

Timer C(1) control register

SIO prescaler control register


A/D converter control register

A/D converter data register (high byte)

A/D converter data register (low byte)


Mnemonic

SIODATA

SIOCON

UDATA0

UARTCON0

BRDATA0

UARTPND

T1DATAH0

T1DATAL0

T1DATAH1

T1DATAL1

T1CON0

T1CON1

Decimal

224

Hex

E0H

R/W

R/W

225 E1H R/W

226 E2H R/W

227 E3H R/W

228 E4H R/W

229 E5H R/W

230

231

232

E6H

E7H

E8H

R/W

R/W

R/W

233 E9H R/W

234 EAH R/W

235 EBH R/W

T1CNTH0

T1CNTL0

T1CNTH1

T1CNTL1

TCDATA0

TCDATA1

TCCON0

236

237

238

239

ECH

EDH

EEH

EFH

R

R

R

R

240

241

F0H

F1H

R/W

R/W

242 F2H R/W

TCCON1

SIOPS

P7CON

243 F3H R/W

244 F4H R/W

245 F5H R/W

Location F6H is not mapped.

ADCON

247 F7H R/W

ADDATAH

ADDATAL

248

249

F8H

F9H

R

R



Flash memory control register

Pattern generation control register

Pattern generation data register

UARTCON1

BRDATA1

FMCON

PGCON

PGDATA

251 FBH R/W

252 FCH R/W

253 FDH R/W

254 FEH R/W

255 FFH R/W

4-3


Register Name

SIO1 control register

SIO1 prescaler control register

SIO1 data register



UART 0.1.2 parity register

PWM control register

PWM0 data register (main byte)

PWM0 data register (extension byte)



PWM2 Data register

PWM3 Data register

PORT1 Extension Control register

PORT6 Control register

Stop Mode Control Register

Flash memory user enable register

Flash memory sector register(High byte)

Flash memory sector register(Low byte)

Table 4-4. Page 8 Registers

Mnemonic

SIOCON1

SIOPS1

SIODATA1

UARTCON2

BRDATA2

Decimal

2

UARTPRT

PWMCON

PWMDAT0

PWM0EX

PWMDAT1

PWM1EX

PWMDAT2

PWMDAT3

P1CONEX

P6CON

STOPCON

FMUSR

FMSECH

FMSECL

Hex

0x02

R/W

R/W

8 0x08 R/W

10 0x0A R/W

11 0x0B R/W

12 0x0C R/W

13 0x0D R/W

14 0x0E R/W

15 0x0F R/W

16 0x10 R/W

17 0x11 R/W

18 0x12 R/W

19 0x13 R/W

4-4


Bit number(s) that is/are appended to the register name for bit addressing

Register ID Register name

Name of individual bit or related bits

Register address

(hexadecimal)

Register location in the internal register file

FLAGS -

System Flags Register

Bit Identifier

RESET Value

Read/Write

Bit Addressing

Mode

.7

D5H Set 1

.7

.6

.5

.4

x

R/W x

R/W x

R/W x

R/W

Register addressing mode only

.3

x

R/W

.2

x

R/W

.1

0

R

.0

0

R/W

.6

.5

Carry Flag (C)

0 Operation does not generate a carry or borrow condition

0 Operation generates carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

0

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

0

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

'-' = Not used

Type of addressing that must be used to address the bit

(1-bit, 4-bit, or 8-bit)

Description of the effect of specific bit settings

RESET value notation:

'-' = Not used

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

Bit number:

MSB = Bit 7

LSB = Bit 0

Figure 4-1. Register Description Format

4-5


ADCON

— A/D Converter Control Register F7H Set 1, Bank 1

RESET Value

Read/Write

Addressing Mode

7–.4

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R R/W R/W R/W


A/D Input Pin Selection Bits

Others Not used for the S3C84MB/F84MB

.0

.3

.2–.1

End-of-Conversion Bit (Read-only)

0

1

A/D conversion opration is in progress

A/D conversion opration is complete

Clock Source Selection Bits

f

XX f

XX f f

XX

XX

/16

/8

/4

/1

A/D Start or Enable Bit

1 Start operation

NOTE: Maximum ADC clock input = 2.5 MHz.

(1)

4-6


BRDATA0

— UART0 Baud Rate Data Register E4H Set1, Bank1

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

1 1 1 1 1 1 1 1

R/W R/W R/W R/W R/W R/W R/W R/W


Baud Rate Data for UART0

(NOTE)

: f

XX

/(16 × (BRDATA + 1))

NOTE: Refer to UARTCON0 register.

BRDATA1

— UART1 Baud Rate Data Register FCH Set 1, Bank1

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

1 1 1 1 1 1 1 1




(NOTE)

: f

XX

/(16 × (BRDATA + 1))


BRDATA2

— UART2 Baud Rate Data Register 04H Page 8

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

1 1 1 1 1 1 1 1


All addressing mode


(NOTE)

: f

XX

/(16 × (BRDATA + 1))


4-7


BTCON

— Basic Timer Control Register D3H Set 1

.0

.1

.3–.2

RESET Value

Read/Write

Addressing Mode

.7–.4

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



Watchdog Timer Function Disable Code (for System Reset)

1 0 1

Others

0 Disable watchdog timer function

Enable watchdog timer function

Basic Timer Input Clock Selection Bits

f

XX f f f

XX

XX

XX

/4096

(3)

/1024

/128

/16 (Not used)

Basic Timer Counter Clear Bit

1

(1)

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer

(2)

1 Clear both clock frequency dividers

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".

XX

is selected clock for system (main OSC. or sub OSC.).

4-8


CLKCON

— System Clock Control Register D4H Set 1

RESET Value

Read/Write

Addressing Mode

.7–.5

.4–.3

.2–.0

.7 .6 .5 .4 .3 .2 .1 .0

– – – 0 0 – – –


Not used for the S3C84MB/F84MB (must keep always 0)

CPU Clock (System Clock) Selection Bits

f

XX

/16 f

XX

/8 f

XX

/2 f

XX

/1 (non-divided)

(NOTE)


NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load

4-9


.1

.0

.2

.3

.7

.6

.5

.4

FLAGS

— System Flags Register D5H Set 1

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x 0 0

RESET Value

Read/Write

Addressing Mode


Carry Flag (C)

0 Operation does not generate a carry or underflow condition

1 Operation generates a carry-out or underflow into high-order bit 7

Zero Flag (Z)

0 Operation result is a non-zero value

1 Operation result is zero

Sign Flag (S)

0 Operation generates a positive number (MSB = "0")

1 Operation generates a negative number (MSB = "1")

Overflow Flag (V)

1 Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0 Add operation completed

1 Subtraction operation completed

Half-Carry Flag (H)

0 No carry-out of bit 3 or no underflow into bit 3 by addition or subtraction

1 Addition generated carry-out of bit 3 or subtraction generated underflow into bit 3

Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)

1 Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0 Bank 0 is selected

1 Bank 1 is selected

4-10

.1

.2

.0


.7–.4

.3

FMCON

— Flash Memory Control Register

RESET Value

Read/Write

Addressing Mode

FDH Set 1, Bank1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 – 0

R/W R/W R/W R/W R/W R – R/W


Flash Memory Mode Selection Bits

Others Not used for the S3C84MB/F84MB

Interrupt Enable Bit During Sector Erase

Sector Erase Status Bit

0 Sector is Successfully Erased

1 Sector Erase Fail

Not used for the S3C84MB/F84MB

Flash Operation Start Bit (Without Programming Mode & Read Mode )

4-11


FMUSR

— Flash Memory User Programming Control Register 11H Page 8

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


All addressing mode

Flash Memory Programing Mode Enable Bits

Others Disable User Programing Mode

10100101 Enable User Programing Mode

FMSECH

— Flash Memory Sector Address Register (High Byte) 12H Page 8

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


All addressing mode

Flash Memory Sector Address Bits

High address of sector that’s accessed

.7–.0

FMSECL

— Flash Memory Sector Address Register (Low Byte) 13H Page 8

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


All addressing mode

Flash Memory Sector Address Bits

Low address of sector that’s accessed

4-12


IMR

— Interrupt Mask Register DDH Set 1

RESET Value

Read/Write

Addressing Mode

.7

.6

.5

.4

.3

.2

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Interrupt Level 7 (IRQ7) Enable Bit

0 Disable (mask)

1

Enable (un-mask)


0

Disable (mask)

1 Enable (un-mask)


0 Disable (mask)

1 Enable (un-mask)


0 Disable (mask)

1 Enable (un-mask)


0 Disable (mask)

1 Enable (un-mask)


0 Disable (mask)

1 Enable (un-mask)


0 Disable (mask)

1 Enable (un-mask)


0 Disable (mask)

1 Enable (un-mask)

.1

.0

NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

4-13


IPH

— Instruction Pointer (High Byte) DAH Set 1

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).

IPL

— Instruction Pointer (Low Byte)

RESET Value

Read/Write

Addressing Mode

.7–.0

DBH Set 1

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH register (DAH).

4-14


IPR

— Interrupt Priority Register

.0

.5

.6

.2

.3

RESET Value

Read/Write

Addressing Mode

.7, .4, and .1

0 0 1 B > C > A

0 1 0 A > B > C

0 1 1 B > A > C

1 0 0 C > A > B

1 0 1 C > B > A

1 1 0 A > C > B

Interrupt Subgroup C Priority Control Bit

0 IRQ6 > IRQ7

1 IRQ7 > IRQ6

Interrupt Group C Priority Control Bit

0 IRQ5 > (IRQ6, IRQ7)

1 (IRQ6, IRQ7) > IRQ5

Interrupt Subgroup B Priority Control Bit

0 IRQ3 > IRQ4

1 IRQ4 > IRQ3

Interrupt Group B Priority Control Bit

0 IRQ2 > (IRQ3, IRQ4)

1 (IRQ3, IRQ4) > IRQ2

Interrupt Group A Priority Control Bit

0 IRQ0 > IRQ1

1 IRQ1 > IRQ0

FFH Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Priority Control Bits for Interrupt Groups A, B, and C

4-15


IRQ

— Interrupt Request Register

.0

.1

.2

.3

.4

.5

.6

RESET Value

Read/Write

Addressing Mode

.7 Level 7 (IRQ7) Request Pending Bit

1 Pending

Level 6 (IRQ6) Request Pending Bit

1 Pending


1 Pending


1 Pending


1 Pending


1 Pending


1 Pending


1 Pending

DCH Set 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0

R R R R R R R R


4-16


P0CON

— Port 0 Control Register F0H Set 1, Bank 0

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P0.7/P0.6/P0.5/P0.4

0

1

1

1

.5–.4 P0.3/P0.2

Input mode, pull-up

Alternative function mode (PGOUT<7:4>)

0 1 Input mode, pull-up

1 1 Alternative function mode (PGOUT<3:2>)

.3–.2 P0.1


1 1 Alternative function mode (PGOUT<1>)

.1–.0 P0.0

0

1

1

1

Input mode, pull-up

Alternative function mode (PGOUT<0>)

4-17


P1CON


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P1.7/P1.6

0 1

.5–.4 P1.5/P1.4

Input mode, pull-up

0 1

.3–.2 P1.3/P1.2

Input mode, pull-up

0 1

.1–.0 P1.1/P1.0

Input mode, pull-up


4-18


P1CONEX

— Port 1 Extention Control Register 0EH Page 8

.0

.4

.3–.2

.1

.5

.6

RESET Value

Read/Write

Addressing Mode

.7

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 – – 0 0

All addressing mode

P1.7/PWM3 Selection Bit

1 PWM3


1 PWM2


1 PWM1


1 PWM0


P1.1/UART2 Rx Selection Bit

P1.0/UART2 Tx Selection Bit

NOTE: 1. When the UART2 is operating in mode 0 (SIO) Rx input, P1CONEX.1 must be set to ‘0’ and P1CON.0-1 must be set to input mode or input with pull-up mode(‘00’ or ‘10’). In other operating modes(mode 0 Rx output, mode1, 2, 3),

P1CONEX.0-1 must be set to ‘1’ and P1CON.0-1 values are don’t care.

4-19


P2CONH

— Port 2 Control Register (High Byte) F2H Set 1, Bank 0

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P2.7/TAOUT

0

1

1

1

Input mode, pull-up

Alternative output mode(TAOUT)

.5–.4 P2.6/TACAP

0 1 Input mode, pull-up(TACAP)

.3–.2 P2.5/TACK

0 1 Input mode, pull-up(TACK)


1 1 Alternative output mode(TBPWM)

4-20


P2CONL

— Port 2 Control Register (Low Byte) F3H Set 1, Bank 0

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P2.3


.5–.4 P2.2/SCK

0 0 Input mode (SCK input)

0 1 Input mode, pull-up (SCK input)

1 1

.3–.2 P2.1/SI

Alternative output mode (SCK output)

0 1 Input mode, pull-up(SI)

.1–.0 P2.0/SO

0

1

1

1

Input mode, pull-up

Alternative output mode (SO)

4-21


P3CONH


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P3.7/TCOUT1

0

1

1

1

Input mode, pull-up

Alternative output mode(TCOUT1)

.5–.4 P3.6/TCOUT0

0

1

1

1

Input mode, pull-up

Alternative output mode(TCOUT0)


1 1 Alternative output mode(T1OUT1)


1 1 Alternative output mode(T1OUT0)

4-22


P3CONL


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P3.3/T1CAP1

0 0 Input mode (T1CAP1)

0 1 Input mode, pull-up (T1CAP1)

0 0 Input mode (T1CAP0)

0 1 Input mode, pull-up (T1CAP0)

.3–.3 P3.1/T1CK1

0 0 Input mode (T1CK1)

0 1 Input mode, pull-up (T1CK1)

.1–.0 P3.0/T1CK0

0 0 Input mode (T1CK0)

0 1 Input mode, pull-up (T1CK0)

4-23


P4CONH


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P4.7/INT7

0 0 Input mode; falling edge interrupt

0 1 Input mode; rising edge interrupt

1 0 Input mode, pull-up; falling edge interrupt










4-24


P4CONL


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P4.3/INT3


0

1

1

0

Input mode; rising edge interrupt

Input mode, pull-up; falling edge interrupt

.5–.4 P4.2/INT2

0

0

1

0

1

0

Input mode; falling edge interrupt

Input mode; rising edge interrupt

Input mode, pull-up; falling edge interrupt

.3–.2 P4.1/INT1




.1–.0 P4.0/INT0




4-25


P4INT

— Port 4 Interrupt Control Register

RESET

Value

Read/Write

Addressing Mode

.7

FAH Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



P4.7 External Interrupt (INT7) Enable Bit

.6

.5

.4

.3

.2

.1

.0








4-26


.0

P4INTPND

— Port 4 Interrupt Pending Register

.4

.5

.6

.7

.1

.2

.3

RESET

Value

Read/Write

Addressing Mode

FBH Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



P4.7/INT7 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0

1 Interrupt request is pending






















4-27


P5CONH


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P5.7


.5–.4 P5.6


.3–.2 P5.5


.1–.0 P5.4


4-28


P5CONL


RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P5.3/RxD0

0 0 Input mode (RxD0 input)

0

1

1

1

Input mode, pull-up mode (RxD0 input)

Alternative output mode (RxD0 output)

.5–.4 P5.2/TxD0

0 1 Input mode, pull-up mode

1 1 Alternative output mode (TxD0 output)

.3–.2 P5.1/RxD1

0 0 Input mode (RxD1 input)

0 1 Input mode, pull-up mode (RxD1 input)

1 1 Alternative output mode (RxD1 output)

.1–.0 P5.0/TxD1

0

1

1

1

Input mode, pull-up mode

Alternative output mode (TxD1 output)

4-29


P6CON

— Port 6 Control Register 0FH PAGE8

RESET

Value

Read/Write

.7 .6 .5 .4 .3 .2 .1 .0

– 0 0 0 0 0 0 0

– R/W R/W R/W R/W R/W R/W R/W

Addressing Mode

All addressing mode

.7 Not Used

.6 P6.6/ADC14

.5 P6.5/ADC13

.4 P6.4/ADC12

.3 P6.3/ADC11

.2 P6.2/ADC10

.1 P6.1/ADC9

.0 P6.0/ADC8

4-30


P7CON


RESET

Value

Read/Write

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


Addressing Mode


.7 P7.7/ADC7

4-31


P8CONH

— Port 8 Control Register (High Byte) EDH Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

– – – – 0 0 0 0

RESET Value

Read/Write

Addressing Mode

.7

−.4









4-32


P8CONL

— Port 8 Control Register (Low Byte) EEH Set 1, Bank 0

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



.7–.6 P8.3


.5–.4 P8.2

0 0 Input mode / SCK1(Input)

0 1 Input mode, pull-up / SCK1(Input)

.3–.2 P8.1

0 0 Input mode / SI1


.1–.0 P8.0


4-33

.0


P8INTPND

— Port 8 Interrupt Pending Register EFH Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

– – 0 0 – – 0 0

RESET

Value

Read/Write

Addressing Mode

.7–.6

.4

.5

.3–.2

.1










P8.5/INT9 Interrupt Enable

P8.4/INT8 Interrupt Enable

4-34


PGCON

— Pattern Generation Control Register FEH Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

– – – – 0 0 0 0

.1–.0

.3

.2

RESET Value

Read/Write

Addressing Mode

.7–.4



Software Trigger Start Bit

1 Software trigger start (will be automatically cleared)

PG Operation Disable/Enable Selection Bit

0 PG operation disable

1 PG operation enable

PG Operation Trigger Mode Selection Bits

0 0 Timer A match siganal triggering

0 1 Timer B underflow siganal triggering

1 0 Timer 1(0) match siganal triggering

1 1 Software triggering mode

4-35


PP

— Register Page Pointer DFH Set 1

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



Destination Register Page Selection Bits .7–.4

Other Value Not Used

Source Register Page Selection Bits .3–.0

Other Value Not Used

NOTE: In the S3C84MB/F84MB microcontroller, the internal register file is configured as eight pages (Pages 0-7).

The pages 0-1 are used for general-purpose register file, and page 2-7 is used for data register or general

4-36


PWM0EX/1EX

— PWM 0,1 Data Extention Register 09H, 0BH PAGE8

RESET Value

Read/Write

Addressing Mode

Extention Bit

7

6

5

2

1

4

3

0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 – –

R/W R/W R/W R/W R/W R/W – –

All addressing mode

“Stretched” Cycle Number

1, 3, 5, 7, 9,

…, 55, 57, 59, 61, 63

2, 6, 10, 14,

…, 50, 54, 58, 62

4, 12, 20,

…, 44, 52, 60

8, 24, 40, 56

16, 48

32

Not used

Not used

4-37


.7

.6–.4

.3–.1

.0

PWMCON

— PWM Control Register 07H PAGE8

.7 .6 .5 .4 .3 .2 .1 .0

– 0 0 0 – – – 0

RESET Value

Read/Write

Addressing Mode

All addressing mode

Not Used

Input Clock Selection Bits

f

XX

/1 f

XX

/2 f

XX

/3 f

XX

/4 f

XX

/5 f

XX

/6 f

XX

/7 f

XX

/8

Not Used

PWM Counter Enable Bit

4-38


RP0

— Register Pointer 0

RESET Value

Read/Write

Addressing Mode

.7–.3

D6H Set 1

.7 .6 .5 .4 .3 .2 .1 .0

1 1 0 0 0 – – –

R/W R/W R/W R/W R/W – – –

Register addressing only

Register Pointer 0 Address Value

Register pointer 0 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H.

.2–.0


RP1

— Register Pointer 1

RESET Value

Read/Write

Addressing Mode

.7–.3

D7H Set 1

.7 .6 .5 .4 .3 .2 .1 .0

1 1 0 0 1 – – –

R/W R/W R/W R/W R/W – – –

Register addressing only

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to address C8H in register set 1, selecting the 8-byte working register slice C8H–CFH.

.2–.0


4-39


.1

.2

.0

.3

.4

.5

.6

RESET Value

Read/Write

Addressing Mode

.7

SIOCON

— SIO Control Register E1H Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



SIO Shift Clock Selection Bit

0 Internal clock (P.S clock)

1 External clock (SCK)

Data Direction Control Bit

0 MSB first mode

1 LSB first mode

SIO Mode Selection Bit

0 Receive only mode

Shift Start Edge Selection Bit

0 Tx at falling edges, Rx at rising edges

1 Tx at rising edges, Rx at falling edges

SIO Counter Clear and Shift Start Bit

1 Clear 3-bit counter and start shifting (Auto-clear bit)

SIO Shift Operation Enable Bit

0 Disable shifter and clock counter

1 Enable shifter and clock counter

SIO Interrupt Enable Bit

0 Disable SIO interrupt

1 Enable SIO interrupt

SIO Interrupt Pending Bit

0 No interrupt pending

0 Clear pending condition (when write)

1 Interrupt is pending

4-40


SIOPS

— SIO Prescaler Register

RESET Value

Read/Write

Addressing Mode

.7–.0

F4H Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



Baud rate = Input clock (f

XX

)/[(SIOPS + 1) ×2] or SCK input clock

4-41


.1

.2

.0

.3

.4

.5

.6

RESET Value

Read/Write

Addressing Mode

.7

SIOCON1

— SIO1 Control Register 00H PAGE 8

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


All addressing mode

SIO Shift Clock Selection Bit

0 Internal clock (P.S clock)

1 External clock (SCK1)

Data Direction Control Bit

0 MSB first mode

1 LSB first mode

SIO1 Mode Selection Bit

0 Receive only mode

Shift Start Edge Selection Bit

0 Tx at falling edges, Rx at rising edges

1 Tx at rising edges, Rx at falling edges

SIO1 Counter Clear and Shift Start Bit

1 Clear 3-bit counter and start shifting (Auto-clear bit)

SIO1 Shift Operation Enable Bit

0 Disable shifter and clock counter

1 Enable shifter and clock counter

SIO1 Interrupt Enable Bit

0 Disable SIO1 interrupt

1 Enable SIO1 interrupt

SIO1 Interrupt Pending Bit


0 Clear pending condition (when write)

1 Interrupt is pending

4-42


SIOPS1

— SIO1 Prescaler Register 01H PAGE 8

RESET Value

Read/Write

Addressing Mode

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


All addressing mode


XX

)/[(SIOPS1 + 1) ×2] or SCK1 input clock

.7–.0

SPH

— Stack Pointer (High Byte)

RESET Value

Read/Write

Addressing Mode

.7–.0

D8H Set 1

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Stack Pointer Address (High Byte)

The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8). The lower byte of the stack pointer value is located in register

SPL (D9H). The SP value is undefined following a reset.

4-43


SPL

— Stack Pointer (Low Byte)

RESET Value

Read/Write

Addressing Mode

.7–.0

D9H Set 1

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Stack Pointer Address (Low Byte)

The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (SP7–SP0). The upper byte of the stack pointer value is located in register

SPH (D8H). The SP value is undefined following a reset.

STOPCON

— Stop Control Register 10H Page 8

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0


All addressing mode

Stop Control Bit

1010 0101 Enable STOP Instruction

Others Disable STOP Instruction

4-44


SYM

— System Mode Register DEH Set 1

.0

.1

RESET Value

Read/Write

Addressing Mode

.7–.5

.4–.2

.7 .6 .5 .4 .3 .2 .1 .0

– – – x x x 0 0

– – – R/W R/W R/W R/W R/W


Not used for S3C84MB/F84MB (must keep “0”)

Fast Interrupt Level Selection Bits

Fast Interrupt Enable Bit

0

1

Disable fast interrupt processing

Enable fast interrupt processing

Global Interrupt Enable Bit

(NOTE)

0 Disable global interrupt processing

1 Enable global interrupt processing

NOTE: Following a reset, you enable global interrupt processing by executing an EI instruction

(not by writing a "1" to SYM.0).

4-45


T1CON0

— Timer 1(0) Control Register

.0

.1

.2

.4–.3

RESET Value

Read/Write

Addressing Mode

.7–.5 Timer 1 Input Clock Selection Bits

f

XX

/1024 f

XX

(Non-divide) f

XX

/256

0 1 1 External clock falling edge f

XX

/64

1 0 1 External clock rising edge f

XX

/8

Timer 1 Operating Mode Selection Bits

0 1 Capture mode (Capture on rising edge, OVF can occur)

1 0 Capture mode (Capture on falling edge, OVF can occur)

Timer 1 Counter Enable Bit

1 Clear the timer 1 counter (Auto-clear bit)

Timer 1 Match/Capture Interrupt Enable Bit

Timer 1 Overflow Interrupt Enable

0 Disable overflow interrupt

1 Enable overflow interrupt

EAH Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-46


T1CON1

— Timer 1(1) Control Register

.0

.1

.2

.4–.3

RESET Value

Read/Write

Addressing Mode

.7–.5 Timer 1 Input Clock Selection Bits

f

XX

/1024 f

XX

(Non-divide) f

XX

/256

0 1 1 External clock falling edge f

XX

/64

1 0 1 External clock rising edge f

XX

/8

Timer 1 Operating Mode Selection Bits

0 1 Capture mode (Capture on rising edge, OVF can occur)

1 0 Capture mode (Capture on falling edge, OVF can occur)

Timer 1 Counter Enable Bit

1 Clear the timer 1 counter (Auto-clear bit)

Timer 1 Match/Capture Interrupt Enable Bit

Timer 1 Overflow Interrupt Enable



EBH Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-47


TACON

— Timer A Control Register

.0

.1

.2

.3

.5–.4

RESET Value

Read/Write

Addressing Mode

.7–.6 Timer A Input Clock Selection Bits

f

XX

/1024 f

XX

/256 f

XX

/64

1 1 External clock (TACK)

Timer A Operating Mode Selection Bits

0 0 Interval mode (TAOUT mode)

0 1 Capture mode (capture on rising edge, counter running, OVF can occur)

1 0 Capture mode (capture on falling edge, counter running, OVF can occur)

1 1 PWM mode (OVF interrupt can occur)

Timer A Counter Clear Bit

Timer A Overflow Interrupt Enable Bit



Timer A Match/Capture Interrupt Enable Bit

Timer A Start/Stop Bit

0 Stop Timer A

1 Start Timer A

EAH

1 Clear the timer A counter (After clearing, return to zero)

Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-48


TBCON

— Timer B Control Register D0H Set 1, Bank 0

.0

.1

.2

.3

.5–.4

RESET Value

Read/Write

Addressing Mode

.7–.6

0

0

1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



Timer B Input Clock Selection Bits

0

1

0 f

XX f

XX

/2 f

XX

/4 f

XX

/8

Timer B Interrupt Time Selection Bits

Elapsed time for low data value

Elapsed time for high data value

Elapsed time for low and high data values

Timer B Interrupt Enable Bit

Timer B Start/Stop Bit

0 Stop timer B

1 Start timer B

Timer B Mode Selection Bit

Timer B Output flip-flop Control Bit

0 T-FF is low

1 T-FF is high

NOTE: f

XX

is selected clock for system.

4-49


TCCON0

— Timer C(0) Control Register

.0

.1

.2

.3

RESET Value

Read/Write

Addressing Mode

.7

.6–.4 Timer C 3-bits Prescaler Bits

Divided 2

Divided 3

Divided 4

Divided 5

Divided 6

Divided 7

Divided 8

Timer C Counter Clear Bit

1 Clear the timer C(0) counter (Auto-clear bit)

Timer C Mode Selection Bit

0 f

XX

/1 & PWM mode

1 f

XX

/64 & interval mode

Timer C Interrupt Enable Bit

Timer C Pending Bit


0 Clear pending bit when write


.7 .6 .5 .4 .3 .2 .1 .0

– 0 0 0 0 0 0 0




4-50


TCCON1

— Timer C(1) Control Register

.0

.1

.2

.3

RESET Value

Read/Write

Addressing Mode

.7

.6–.4 Timer C 3-bits Prescaler Bits

Divided 2

Divided 3

Divided 4

Divided 5

Divided 6

Divided 7

Divided 8

Timer C Counter Clear Bit

1 Clear the timer C(1) counter (Auto-clear bit)

Timer C Mode Selection Bit

0 f

XX

/1 & PWM mode

1 f

XX

/64 & interval mode

Timer C Interrupt Enable Bit

Timer C Pending Bit




.7 .6 .5 .4 .3 .2 .1 .0

– 0 0 0 0 0 0 0




4-51


TINTPND

— Timer A, 1 Interrupt Pending Register

.0

.2

.1

.3

.5

.4

RESET Value

Read/Write

Addressing Mode

.7–.6


Timer 1(1) Overflow Interrupt Pending Bit



Timer 1(1) Match/Capture Interrupt Pending Bit



Timer 1(0) Overflow Interrupt Pending Bit



Timer 1(0) Match/Capture Interrupt Pending Bit



Timer A Overflow Interrupt Pending Bit



Timer A Match/Capture Interrupt Pending Bit



E9H Set 1, Bank 0

.7 .6 .5 .4 .3 .2 .1 .0

– – 0 0 0 0 0 0

– – R/W R/W R/W R/W R/W R/W


4-52


UARTCON0

— UART0 Control Register

.0

.1

.4

.5

RESET Value

Read/Write

Addressing Mode

.7–.6

.3

.2

E3H Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



Operating mode and baud rate selection bits

XX

/(16

× (BRDATA0 + 1))]

Mode 1: 8-bit UART [f

XX

/(16

× (BRDATA0 + 1))]

1 0 Mode 2: 9-bit UART [f

XX

/16]


XX

/(16

× (BRDATA0 + 1))]

Multiprocessor communication enable bit (for modes 2 and 3 only)

0 Disable

1 Enable

Serial data receive enable bit

0 Disable

1 Enable

If Parity disable mode, location of the 9 th data bit to be transmitted in UART mode 2,

3 ("0" or "1"). If Parity enable mode, parity selection bit for transmit data in UART mode 2, 3.

0: Even parity 1: Odd parity

If Parity disable mode, location of the 9 th data bit that was received in UART mode

2, 3 ("0" or "1").

If Parity enable mode, parity selection bit for receive data in UART mode 2, 3.


A result of parity error will be saved in UARTPRT register after parity checking of the received data.

Receive interrupt enable bit

0 Disable Receive interrupt

1 Enable Receive interrupt

Transmit interrupt enable bit

0 Disable Transmit interrupt

1 Enable Transmit Interrupt

4-53


.0

.1

UARTCON1

— UART1 Control Register

.4

.5

RESET Value

Read/Write

Addressing Mode

.7–.6

.3

.2

FBH Set 1, Bank 1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0




XX

/(16

× (BRDATA1 + 1))]


XX

/(16

× (BRDATA1 + 1))]


XX

/16]


XX

/(16

× (BRDATA1 + 1))]


0 Disable

1 Enable


0 Disable

1 Enable

If Parity disable mode, location of the 9 th data bit to be transmitted in UART mode 2,

3 ("0" or "1"). If Parity enable mode, parity selection bit for transmit data in UART mode 2, 3.



2, 3 ("0" or "1").










4-54


UARTCON2

— UART2 Control Register 03H Page 8

.0

.1

.4

.5

RESET Value

Read/Write

Addressing Mode

.7–.6

.3

.2

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0




XX

/(16

× (BRDATA2 + 1))]


XX

/(16

× (BRDATA2 + 1))]


XX

/16]


XX

/(16

× (BRDATA2 + 1))]


0 Disable

1 Enable


0 Disable

1 Enable

If Parity disable mode, location of the 9 th data bit to be transmitted in UART mode

2 , 3 ("0" or "1"). If Parity enable mode, parity selection bit for transmit data in UART mode 2, 3.



2, 3 ("0" or "1").










4-55


UARTPND

— UART0, 1, 2 Pending Register E5H Set 1, Bank 1

RESET Value

Read/Write

Addressing Mode

.7–.6

.7 .6 .5 .4 .3 .2 .1 .0

– – 0 0 0 0 0 0

– – R/W R/W R/W R/W R/W R/W


Not used for S3C84MB/F84MB

.3

.5

.4

UART2 receive interrupt pending flag

0 Not pending (read) / Clear pending bit (when write)

UART2 transmit interrupt pending flag




.2

.1

0

UART1 transmit interrupt pending flag

Not pending (read) / Clear pending bit (when write)



.0 UART0 transmit interrupt pending flag


NOTES:

1. In order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit.

2. To avoid programming errors, we recommend using load instruction (except for LDB), when manipulating UARTPND values.

4-56


.0

.1

.2

.4

.6

.5

.3

UARTPRT

— UART0, 1, 2 Parity Control Register 06H Page 8

.7 .6 .5 .4 .3 .2 .1 .0

– 0 0 0 – 0 0 0

RESET Value

Read/Write

Addressing Mode

.7

All addressing mode


UART2 Parity Status Bit




UART2 Parity Enable Bit

0 Disable

1 Enable


0 Disable

1 Enable


0 Disable

1 Enable

4-57

CONTROL REGISTERS

NOTES


4-58


5

INTERRUPT STRUCTURE

OVERVIEW

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3C84MB/F84MB interrupt structure recognizes eight interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for

S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3C84MB/F84MB uses twenty seven vectors.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.

Each vector can have several interrupt sources. In the S3C84MB/F84MB interrupt structure, there are twenty seven possible interrupt sources.

When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE S3C84MB/F84MB_UM_REV1.00

INTERRUPT TYPES

The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.

The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1: One level (IRQn) + one vector (V

1

) + one source (S

1

)

Type 2: One level (IRQn) + one vector (V

1

) + multiple sources (S

1

– S n

)

Type 3: One level (IRQn) + multiple vectors (V

1

– V n

) + multiple sources (S

1

– S n

, S n+1

– S n+m

)

In the S3C84MB/F84MB microcontroller, two interrupt types are implemented.

Levels

Type 1:

IRQn

Type 2:

IRQn

Type 3:

IRQn

Vectors

V1

V1

V1

V2

V3

Vn

NOTES:

1. The number of Sn and Vn value is expandable.

2. In the S3C84MB/F84MB implementation,

interrupt types 1 and 3 are used.

Figure 5-1. S3C8-Series Interrupt Types

Sources

S3

Sn

S1

S2

S1

S1

S2

S3

Sn

Sn + 1

Sn + 2

Sn + m

5-2


S3C84MB/F84MB INTERRUPT STRUCTURE

The S3C84MB/F84MB microcontroller supports twenty seven interrupt sources. All twenty seven of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware).

When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.

5-3


Levels Vectors Sources Reset(Clear)

B8H

BAH

C8H

BCH

BEH

C0H

C2H

C4H

C6H

CAH

ACH

CCH

CEH

E0H

E2H

E4H

E6H

E8H

EAH

ECH

EEH

F0H

F2H

F4H

F6H

A0H

A2H

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Timer A match/capture

Timer A overflow

H/W, S/W

H/W, S/W

Timer B underflow

Timer C(0) match/overflow


H/W

H/W, S/W

H/W, S/W

Timer 1(0) match/capture

Timer 1(0) overflow


Timer 1(1) overflow

SIO0 receive/transmit

H/W, S/W

H/W, S/W

H/W, S/W

H/W, S/W

S/W


P8.4 external interrupt










UART0 data receive

UART0 data transmit

UART1 data receive

UART1 data transmit

UART2 data receive

UART2 data transmit

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

S/W

NOTES:

1. Within a given interrupt level, the lower vector address has high priority. For example, B8H has

higher priority than BAH within the level IRQ0 the priorities within each level are set at the factory.

2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control

register setting.

Figure 5-2. S3C84MB/F84MB Interrupt Structure

5-4


INTERRUPT VECTOR ADDRESSES

All interrupt vector addresses for the S3C84MB/F84MB interrupt structure are stored in the vector address area of the internal 64-Kbyte ROM, 0H–FFFFH (see Figure 5-3).

You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).

The program reset address in the ROM is 0100H.

(Decimal)

65,535

(HEX)

FFFFH

64-Kbyte

Memory Area

255

0

Interrupt

Vector Area

0100H

FFH

RESET Address

00H

Figure 5-3. ROM Vector Address Area

5-5


Table 5-1. Interrupt Vectors

Vector Address

Decimal

Value

256

238

236

234

232

230

228

226

224

206

204

198

196

194

192

190

188

200

186

184

Hex

Value

100H

EEH

ECH

EAH

E8H

E6H

E4H

E2H

E0H

CEH

CCH

C6H

C4H

C2H

C0H

BEH

BCH

C8H

BAH

B8H

Interrupt Source

Basic timer(WDT) overflow











Timer 1(1) overflow


Timer 1(0) overflow




Timer B underflow

Timer A overflow


Request

Interrupt

Level

RESETB

IRQ3

IRQ2

IRQ1

IRQ0

Priority in

Level

-

3

2

1

0

1

0

-

1

0

IRQ4

Reset/Clear

H/W S/W

√

1

0

IRQ6 7

2

IRQ5

6

5

4

3

2

1

0

1

0

√

√

√

√

√

√

√

√

√

4

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

NOTES:

1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.

2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.

5-6


ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities.

NOTE

The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure.

During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented).

Control Register

Interrupt mask register

Interrupt priority register

Interrupt request register

System mode register

Table 5-2. Interrupt Control Register Overview

ID

IMR

IPR

IRQ

SYM

R/W Function Description

R/W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0–IRQ7.

R/W Controls the relative processing priorities of the interrupt levels.

The seven levels of S3C84MB/F84MB are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is

IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

R This register contains a request pending bit for each interrupt level.

R/W This register enables/disables fast interrupt processing, dynamic global interrupt processing, and external interface control (An external memory interface is not implemented in the S3C84MB/F84MB microcontroller).

NOTE: Before IMR register is changed to any value, all interrupts must be disabled.

Using DI instruction is recommended.

5-7


INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are:

— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0)

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information.

EI

RESET

IRQ0-IRQ7,

Interrupts

S

R

Q

Interrupt Priority

Register

Interrupt Request Register

(Read-only)

Polling

Cycle

Vector

Interrupt

Cycle

Interrupt Mask

Register

Global Interrupt Control

(EI, DI or SYM.0

manipulation)

Figure 5-4. Interrupt Function Diagram

5-8


PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3).

Table 5-3. Interrupt Source Control and Data Registers

Interrupt Source

Timer A overflow


Interrupt Level

IRQ0

Register(s)

TINTPND

TACON

TADATA

TACNT

Location(s) in Set 1

E9H, bank 0

EAH, bank 0

EBH, bank 0

ECH, bank 0

Timer B underflow IRQ1 TBCON D0H, bank 0

D1H, D2H, bank 0



Timer1(0) match/capture

Timer1(0) overflow

Timer1(1) match/capture

Timer1(1) overflow

SIO receive/transmit


IRQ2

IRQ3

IRQ4

TCCON0

TCCON1

TCDATA0

TCDATA1

T1DATAH0,T1DATAL0

T1DATAH1,T1DATAL1

T1CON0, T1CON1

T1CNTH0, T1CNTL0

T1CNTH1, T1CNTL1

SIOCON, SIODATA

SIOCON1, SIODATA1

F2H, bank 1

F3H, bank 1

F0H, bank 1

F1H, bank 1

E6H,E7H, bank 1

E8H,E9H, bank 1

EAH,EBH, bank1

ECH, EDH, bank1

EEH, EFH, bank1

E1H,E0H, bank1

00H, 02H, Page 8



P4.7 ~ 0 external interrupt

UART0 receive/transmit



IRQ5

IRQ6

IRQ7

P8CONH,P8CONL

P8INTPND

P4CONH

P4CONL

P4INT

P4INTPND

UARTCON0

UARTCON1

UARTCON2

UDATA0, UDATA1

EDH,EEH, bank0

EFH, bank0

F6H, bank 0

F7H, bank 0

FAH, bank 0

FBH, bank 0

E3H, bank 1

FBH, bank 1

03H, Page 8

E2H, FAH, bank 1

UARTPND E5H, bank 1

5-9


SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing (see

Figure 5-5).

A reset clears SYM.0 to "0".

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose.

MSB .7

.6

System Mode Register (SYM)

DEH, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB


(must keep ٛ0”)

Fast interrupt level selection bits:

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Global interrupt enable bit:

0 = Disable all interrupts processing

1 = Enable all interrupts processing

Fast interrupt enable bit:

0 = Disable fast interrupts processing

1 = Enable fast interrupts processing

Figure 5-5. System Mode Register (SYM)

5-10


INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's

IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode.

MSB .7

.6

Interrupt Mask Register (IMR)

DDH ,Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

IRQ4

IRQ3

IRQ2

IRQ7

IRQ6

IRQ5

Interrupt level # enable bit

0 = Disable IRQ# interrupt

1 = Enable IRQ# interrupt

IRQ1

IRQ0

Figure 5-6. Interrupt Mask Register (IMR)

5-11


INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7):

Group A IRQ0, IRQ1

Group B IRQ2, IRQ3, IRQ4

Group C IRQ5, IRQ6, IRQ7

IPR

Group A

IPR

Group B

IPR

Group C

A1 A2 B1 B2 C1 C2

IRQ0 IRQ1

B21

IRQ2 IRQ3

B22

IRQ4

C21

IRQ5 IRQ6

C22

IRQ7

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.

For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of group C interrupts.

— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,

6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-12


MSB .7

Group priority:

D7 D4 D1

0 0 0 = Undefined

0 0 1 = B > C > A

0 1 0 = A > B >C

0 1 1 = B > A > C

1 0 0 = C > A > B

1 0 1 = C > B > A

1 1 0 = A > C > B

1 1 1 = Undefined

.6

Interrupt Priority Register (IPR)

FFH ,Set 1, Bank 0, R/W

.5

.4

.3

.2

.1

.0

LSB

Group B

0 = IRQ2 > (IRQ3, IRQ4)

1 = (IRQ3, IRQ4) > IRQ2

Subgroup B

0 = IRQ3 > IRQ4

1 = IRQ4 > IRQ3

Group A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

Group C

0 = IRQ5 > (IRQ6, IRQ7)

1 = (IRQ6, IRQ7) > IRQ5

Subgroup C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

Figure 5-8. Interrupt Priority Register (IPR)

5-13


INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the

IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled.

MSB .7

.6

Interrupt Request Register (IRQ)

DCH ,Set 1, R

.5

.4

.3

.2

.1

.0

LSB

IRQ1

IRQ0

IRQ4

IRQ3

IRQ2

IRQ7

IRQ6

IRQ5

Interrupt level # request pending bit

0 = IRQ# interrupt is not pending

1 = IRQ# interrupt is pending

Figure 5-9. Interrupt Request Register (IRQ)

5-14


INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software.

In the S3C84MB/F84MB interrupt structure, the timer B underflow interrupt (IRQ1) belongs to this category of interrupts in which pending condition is cleared automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source’s mode or control register.

In the S3C84MB/F84MB interrupt structure, pending conditions for IRQ4, IRQ5, IRQ6, and IRQ7 must be cleared in the interrupt service routine.

5-15


INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the source's interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request is serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one level is currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.

The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.

5-16


GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs).

4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the procedure above to some extent.

5-17


6

INSTRUCTION SET

OVERVIEW

The instruction set is specifically designed to support large register files that are typical of most S3C8-series microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include:

— A full complement of 8-bit arithmetic and logic operations, including multiply and divide

— No special I/O instructions (I/O control/data registers are mapped directly into the register file)

— Decimal adjustment included in binary-coded decimal (BCD) operations

— 16-bit (word) data can be incremented and decremented

— Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES

The CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0–255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data, 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Chapter 2, "Address Spaces."


There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative

(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to

Chapter 3, "Addressing Modes."

6-1

INSTRUCTION SET S3C84MB/F84MB_UM_REV1.00

Table 6-1. Instruction Group Summary

Mnemonic Operands Instruction

Load Instructions

CLR dst Clear

LDE

LDC

LDED

LDCD

LDEI

LDCI

LDEPD

LDCPD

LDEPI

LDCPI dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src

Load external data memory

Load program memory

Load external data memory and decrement

Load program memory and decrement

Load external data memory and increment

Load program memory and increment

Load external data memory with pre-decrement

Load program memory with pre-decrement

Load external data memory with pre-increment

Load program memory with pre-increment

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI dst dst,src dst,src src dst,src dst,src

Pop from stack

Pop user stack (decrementing)

Pop user stack (incrementing)

Push to stack

Push user stack (decrementing)

Push user stack (incrementing)

NOTE:

LDE, LDED, LDEI, LDEPP, and LDEPI instructions can be used to read/write the data from the 64-Kbyte data

memory.

6-2


Table 6-1. Instruction Group Summary (Continued)


Arithmetic Instructions

ADC dst,src Add with carry

DEC dst Decrement

DECW dst Decrement

INC dst Increment

INCW dst Increment

MULT dst,src Multiply

SBC dst,src Subtract with carry

Logic Instructions

COM dst Complement

XOR dst,src Logical exclusive OR

6-3


Table 6-1. Instruction Group Summary (Continued)


Program Control Instructions

BTJRF

BTJRT dst,src dst,src

Bit test and jump relative on false

Bit test and jump relative on true

CALL dst Call

CPIJE

CPIJNE dst,src dst,src

DJNZ r,dst

ENTER

Compare, increment and jump on equal

Compare, increment and jump on non-equal

Decrement register and jump on non-zero

Enter

Exit EXIT

IRET

JP cc,dst Jump on condition code

JR cc,dst

NEXT

RET

WFI

Bit Manipulation Instructions

Jump relative on condition code

Next

Return

Wait for interrupt

TCM

TM dst,src dst,src

Test complement under mask

Test under mask

6-4


Table 6-1. Instruction Group Summary (Concluded)


Rotate and Shift Instructions

RLC dst Rotate left through carry

RRC

SRA dst dst

Rotate right through carry

Shift right arithmetic

SWAP dst Swap

CPU Control Instructions

CCF Complement carry flag

IDLE

NOP

RCF

SB0

SB1

SCF

SRP

SRP0

SRP1

STOP src src src

Enter Idle mode

Reset carry flag

Set bank 0

Set bank 1

Set carry flag

Set register pointers

Set register pointer 0

Set register pointer 1

Enter Stop mode

6-5


FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits which describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions. Two other flag bits, FLAGS.3 and FLAGS.2, are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether register bank 0 or bank 1 is currently being addressed.

FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then two write will simultaneously occur to the Flags register producing an unpredictable result.

MSB

Carry flag (C)

.7

Zero flag (Z)

.6

System Flags Register (FLAGS)

D5H ,Set 1, R/W

.5

.4

.3

.2

.1

Sign flag (S)

.0

LSB

Bank address status flag (BA)

Fast interrupt status flag (FS)

Half-carry flag (H)

Overflow flag (V) Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

6-6


FLAG DESCRIPTIONS

C

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations have been performed, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.

Z

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. In operations that test register bits, and in shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

S

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number.

V

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than

– 128. It is cleared to "0" after a logic operation has been performed.

D

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and it cannot be addressed as a test condition.

H

Half-Carry Flag (FLAGS.2

)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is normally not accessed directly by a program.

FIS

Fast Interrupt Status Flag (FLAGS.1)

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.

When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed.

BA

Bank Address Flag (FLAGS.0)

The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when the SB0 instruction is executed and is set to "1" (select bank 1) when the SB1 instruction is executed.

6-7


INSTRUCTION SET NOTATION

Table 6-2. Flag Notation Conventions

Flag Description

*

–

0

1 x

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

Table 6-3. Instruction Set Symbols

Symbol Description

@ Indirect register address prefix

FLAGS Flags register (D5H)

#

H

D

B

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix opc Opcode

6-8


Table 6-4. Instruction Notation Conventions

IA

Ir

IR

Irr

IRR

Notation

cc r rb r0 rr

R

Rb

RR

X

XS

XL

DA

RA

IM

IML

Condition code

Description

Working register only

Bit (b) of working register

Bit 0 (LSB) of working register

Working register pair

Register or working register

Bit "b" of register or working register

Register pair or working register pair

Actual Operand Range

See list of condition codes in Table 6-6.

Rn (n = 0–15)

Rn.b (n = 0–15, b = 0–7)

Rn (n = 0–15)

RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0–255, n = 0–15) reg.b (reg = 0–255, b = 0–7) reg or RRp (reg = 0–254, even number only, where p = 0, 2, ..., 14)

Indirect addressing mode

Indirect working register only

Indexed addressing mode

Indexed (short offset) addressing mode

Indexed (long offset) addressing mode

Direct addressing mode

Relative addressing mode addr (addr = 0–254, even number only)

@Rn (n = 0–15)

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Indirect working register pair only

Indirect register pair or indirect working register pair

@RRp (p = 0, 2, ..., 14)

@RRp or @reg (reg = 0–254, even only, where p = 0, 2, ..., 14)

#reg[Rn] (reg = 0–255, n = 0–15)

#addr[RRp] (addr = range –128 to +127, where p = 0, 2, ..., 14)

#addr [RRp] (addr = range 0–65535, where p = 2, ..., 14) addr (addr = range 0–65535)

Immediate addressing mode

Immediate (long) addressing mode addr (addr = a number from +127 to –128 that is an offset relative to the address of the next instruction)

#data (data = 0–255)

#data (data = 0–65535)

6-9


Table 6-5. OPCODE Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

– 0 1 2 3 4 5 6 7

U 0 DEC

R1

DEC

IR1

P 1 RLC

R1

RLC

IR1

P 2 INC

R1

INC

IR1

E 3 JP SRP/0/1

IRR1 IM

R 4 DA

R1

DA

IR1

5 POP POP

R1 IR1

N 6 COM

R1

COM

IR1

R2

RR1

B 9 RL

R1

RL

IR1

L A INCW INCW

RR1 IR1

E B CLR

R1

CLR

IR1

C RRC

R1

RRC

IR1

H D SRA

R1

E E RR

R1

SRA

IR1

RR

IR1

R1

IR2

IR1

IR1

ADD r1,r2

ADC r1,r2

SUB r1,r2

SBC r1,r2

OR r1,r2

AND r1,r2

TCM r1,r2

TM r1,r2

PUSHUD

IR1,R2

POPUD

IR2,R1

CP r1,r2

XOR r1,r2

CPIJE

Ir,r2,RA

CPIJNE

Irr,r2,RA

LDCD r1,Irr2

LDCPD r2,Irr1

ADD r1,Ir2

ADC r1,Ir2

SUB r1,Ir2

SBC r1,Ir2

OR r1,Ir2

AND r1,Ir2

TCM r1,Ir2

TM r1,Ir2

PUSHUI

IR1,R2

POPUI

IR2,R1

CP r1,Ir2

XOR r1,Ir2

LDC r1,Irr2

LDC r2,Irr1

LDCI r1,Irr2

LDCPI r2,Irr1

ADD

R2,R1

ADC

R2,R1

SUB

R2,R1

SBC

R2,R1

OR

R2,R1

AND

R2,R1

TCM

R2,R1

TM

R2,R1

MULT

R2,RR1

DIV

R2,RR1

CP

R2,R1

XOR

R2,R1

LDW

RR2,RR1

CALL

IA1

LD

R2,R1

CALL

IRR1

ADD

IR2,R1

ADC

IR2,R1

SUB

IR2,R1

SBC

IR2,R1

OR

IR2,R1

AND

IR2,R1

TCM

IR2,R1

TM

IR2,R1

MULT

IR2,RR1

DIV

IR2,RR1

CP

IR2,R1

XOR

IR2,R1

LDW

IR2,RR1

LD

R2,IR1

LD

IR2,R1

ADD

R1,IM

ADC

R1,IM

SUB

R1,IM

SBC

R1,IM

OR

R1,IM

AND

R1,IM

TCM

R1,IM

TM

R1,IM

MULT

IM,RR1

DIV

IM,RR1

CP

R1,IM

XOR

R1,IM

LDW

RR1,IML

IR1,IM

LD

R1,IM

CALL

DA1

BOR r0–Rb

BCP r1.b, R2

BXOR r0–Rb

BTJR r2.b, RA

LDB r0–Rb

BITC r1.b

BAND r0–Rb

BIT r1.b

LD r1, x, r2

LD r2, x, r1

LDC r1, Irr2, xL

LDC r2, Irr2, xL

LD r1, Ir2

Ir1, r2

LDC r1, Irr2, xs

LDC r2, Irr1, xs

6-10


Table 6-5. OPCODE Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

– 8 9 A B C D E F

U 0 LD r1,R2

P 1

↓

LD r2,R1

↓

DJNZ r1,RA

↓

JR cc,RA

↓

LD r1,IM

↓

JP cc,DA

↓

INC r1

↓

NEXT

ENTER

P 2

E

R

N

3

4

5

6

I 7

B

B

L

E

8

9

A

B

C

H D

E E

↓

↓

X F LD r1,R2

↓

↓

LD r2,R1

↓

↓

DJNZ r1,RA

↓

↓

JR cc,RA

↓

↓

LD r1,IM

↓

↓

JP cc,DA

↓

↓

INC r1

EI

RET

IRET

RCF

SCF

CCF

NOP

EXIT

WFI

SB0

SB1

IDLE

STOP

DI

6-11


CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions.

Table 6-6. Condition Codes

1001

0001

1010

0010

1111

(1)

0111

(1)

1011

0011

Binary Mnemonic Description

0000 F Always

1000 T Always

0111

(1)

C Carry

1111

(1)

0110

(1)

1110

(1)

NC

Z

NZ

No carry

Zero

Not zero

1101

0101

0100

1100

0110

(1)

1110

(1)

PL

MI

OV

NOV

EQ

NE

Plus

Minus

Overflow

No overflow

Equal

Not equal

GE

LT

GT

LE

UGE

ULT

UGT

ULE

Greater than or equal

Less than

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

–

–

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

NOTES:

1. It indicate condition codes which are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used.

Following a CP instruction, you would probably want to use the instruction EQ.

2. For operations using unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-12


INSTRUCTION DESCRIPTIONS

This Chapter contains detailed information and programming examples for each instruction in the S3C8-series instruction set. Information is arranged in a consistent format for improved readability and for quick reference. The following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Flag settings that may be affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

6-13


ADC

— Add with Carry

ADC

dst,src

Operation:

dst

Flags:

The source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple-precision arithmetic, this instruction lets the carry value from the addition of low-order operands be carried into the addition of high-order operands.

C:

Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z:

Set if the result is "0"; cleared otherwise.

S:

Set if the result is negative; cleared otherwise.

V:

Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D:

Always cleared to "0".

H:

Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

Format:

Bytes Cycles Opcode

(Hex)

Addr Mode dst src

opc dst | src 2 4 12 r r

6 13 lr

15 R IR

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH:

→

→

→

→

R1 = 14H, R2 = 03H

R1 = 1BH, R2 = 03H

Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H

01H,#11H Register 01H = 32H

In the first example, the destination register R1 contains the value 10H, the carry flag is set to "1" and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds

03H and the carry flag value ("1") to the destination value 10H, leaving 14H in the register R1.

6-14


ADD

— Add

ADD

dst,src

Operation:

dst

Flags:

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

C:

Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z:


S:


V:

Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D:


H:

Set if a carry from the low-order nibble occurred.

Format:


(Hex)



6 03 lr

05 R IR

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

R1,R2

R1,@R2

R1 = 15H, R2 = 03H

R1 = 1CH, R2 = 03H

01H,02H Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H


In the first example, the destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in the register R1.

6-15


AND —

Logical AND

AND

dst,src

Operation:

dst

The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.

Flags: C:

Unaffected.

Z:


S:

Set if the result bit 7 is set; cleared otherwise.

V:


D:

Unaffected.

H:

Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src


6 53 lr

55 R IR

Examples:


R1,R2

R1,@R2

R1 = 02H, R2 = 03H

R1 = 02H, R2 = 03H

01H,02H Register 01H = 01H, register 02H = 03H



In the first example, the destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in the register R1.

6-16


BAND

— Bit AND

BAND

dst,src.b

BAND

dst.b,src

Operation:

dst(0) or

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or the source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

Flags: C:

Unaffected.

Z:


S:

Cleared to "0".

V:

Undefined.

D:

Unaffected.

H:

Unaffected.

Format:

Bytes

(Hex) dst src

src 3 6 67 r0 dst 3 6 67 Rb

NOTE:

In the second byte of the 3-byte instruction formats, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

R1,01H.1 R1 = 06H, register 01H = 05H

01H.1,R1 Register 01H = 05H, R1 = 07H

In the first example, the source register 01H contains the value 05H (00000101B) and the destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1"

ANDs the bit 1 value of the source register ("0") with the bit 0 value of the register R1

(destination), leaving the value 06H (00000110B) in the register R1.

6-17


BCP

— Bit Compare

BCP

dst,src.b

Operation:

dst(0) – src(b)

Flags:

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.

The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.

C:

Unaffected.

Z:

Set if the two bits are the same; cleared otherwise.

S:

Cleared to "0".

V:

Undefined.

D:

Unaffected.

H:

Unaffected.

Format:

opc dst | b | 0 src


(Hex)


3 6 17 r0

NOTE

: In the second byte of the instruction format, the destination address is four bits, the bit address "0" is three bits, and the LSB address value is one bit in length.

Example:


R1,01H.1 R1 = 07H, register 01H = 01H

If the destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

6-18


BITC

— Bit Complement

BITC

dst.b

Operation:

dst(b)

Flags:

This instruction complements the specified bit within the destination without affecting any other bit in the destination.

C:

Unaffected.

Z:


S:

Cleared to "0".

V:

Undefined.

D:

Unaffected.

H:

Unaffected.

Format:

opc


(Hex)

Addr Mode dst

2 4 57 rb

NOTE

: In the second byte of the instruction format, the destination address is four bits, the bit address “b” is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H

R1 = 05H

If the working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in the register R1.

Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared.

6-19


BITR

— Bit Reset

BITR

dst.b

Operation:

dst(b)

Flags:

The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination.

No flags are affected.

Format:

opc


(Hex)

Addr Mode dst

2 4 77 rb

NOTE

: In the second byte of the instruction format, the destination address is four bits, the bit

address “0” is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

R1 = 05H

If the value of the working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B).

6-20


BITS

— Bit Set

BITS

dst.b

Operation:

dst(b)

Flags:

The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination.


Format:


(Hex)

Addr Mode dst

2 4 77 rb

NOTE:

In the second byte of the instruction format, the destination address is four bits, the bit address “b” is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

R1 = 0FH

If the working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B).

6-21


BOR

— Bit OR

BOR

BOR

dst,src.b dst.b,src

Operation:

dst(0) or

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.

No other bits of the destination are affected. The source is unaffected.

Flags: C:

Z:

S:

V:

Unaffected.


Cleared to "0".

Undefined.

D:

Unaffected.

H:

Unaffected.

Format:

opc

opc src dst


(Hex)


3 6 07 r0

3 6 07 Rb

NOTE

: In the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address “b” is three bits, and the LSB address value is one bit.

Examples:


01H.1 R1 = 07H, register 01H = 03H

R1 Register 01H = 07H, R1 = 07H

In the first example, the destination working register R1 contains the value 07H (00000111B) and the source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically

ORs bit one of the register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in the working register R1.

In the second example, the destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically

ORs bit two of the register 01H (destination) with bit zero of R1 (source). This leaves the value

07H in the register 01H.

6-22


BTJRF

— Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation:

If src(b) is a "0", then PC

← PC + dst

Flags:

The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter. Otherwise, the instruction following the BTJRF instruction is executed.


Format:

(note)


(Hex)


dst 3 10 37 rb

NOTE:

In the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

If the working register R1 contains the value 07H (00000111B), the statement "BTJRF

SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP (Remember that the memory location must be within the allowed range of + 127 to – 128).

6-23


BTJRT

— Bit Test, Jump Relative on True

BTJRT

dst,src.b

Operation:

If src(b) is a "1", then PC

← PC + dst

Flags:

The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC.

Otherwise, the instruction following the BTJRT instruction is executed.


Format:

(note)


(Hex)


dst 3 10 37 rb

NOTE:

In the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

If the working register R1 contains the value 07H (00000111B), the statement "BTJRT

SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP.

Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of + 127 to – 128.

6-24


BXOR

— Bit XOR

BXOR

dst,src.b

BXOR

dst.b,src

Operation:

dst(0) or

Flags:

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or the source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

C:

Unaffected.

Z:


S:

Cleared to "0".

V:

Undefined.

D:

Unaffected.

H:

Unaffected.

Format:

opc

opc src dst


(Hex)


3 6 27 r0

3 6 27 Rb

NOTE

: In the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):

R1,01H.1 R1 = 06H, register 01H = 03H

01H.2,R1 Register 01H = 07H, R1 = 07H

In the first example, the destination working register R1 has the value 07H (00000111B) and the source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of the register 01H (the source) with bit zero of R1 (the destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of the source register 01H is unaffected.

6-25

INSTRUCTION SET

CALL

— Call Procedure

CALL

dst

Operation:

SP


Flags:

Format:

The contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter.



(Hex)

Addr Mode dst

Examples:

Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:

@RR0

→

SP = 0000H

(Memory locations 0000H = 1AH, 0001H = 4AH, where, 4AH is the address that follows the instruction.)

SP = 0000H (0000H = 1AH, 0001H = 49H)

SP = 0000H (0000H = 1AH, 0001H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to the memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and the stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed.

Assuming that the contents of the program counter and the stack pointer are the same as in the first example, if the program address 0040H contains 35H and the program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example.

6-26


CCF

— Complement Carry Flag

CCF

Operation:

C

Flags:

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero. If C = "0", the value of the carry flag is changed to logic one.

C:

Complemented.

No other flags are affected.

Format:


(Hex)

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.

6-27


CLR

— Clear

CLR

dst

Operation:

dst

Flags:

The destination location is cleared to "0".


Format:


(Hex)

Addr Mode dst

4 B1

Examples:

Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

IR

00H

@01H

Register 00H = 00H


In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H.

In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.

6-28


COM

— Complement

COM

dst

Operation:

dst

The contents of the destination location are complemented (one's complement). All "1s" are changed to "0s", and vice-versa.

Flags: C:

Unaffected.

Z:


S:


V:

Always reset to "0".

D:

Unaffected.

H:

Unaffected.

Format:


(Hex)

Addr Mode dst

4 61 IR

Examples:

Given: R1 = 07H and register 07H = 0F1H:

R1

@R1

R1 = 0F8H

R1 = 07H, register 07H = 0EH

In the first example, the destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and logic zeros to logic ones, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of the destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-29


CP

—

Compare

CP

dst,src

Operation:

dst–src

The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.

Flags: C:

Set if a "borrow" occurred (src > dst); cleared otherwise.

Z:


S:


V:

Set if arithmetic overflow occurred; cleared otherwise.

D:

Unaffected.

H:

Unaffected.

Format:

opc dst | src


(Hex)


2 4

6

A2

A3 r r r lr

6 A5 R IR

Examples:

1. Given: R1 = 02H and R2 = 03H:

CP R1,R2

→

Set the C and S flags

The destination working register R1 contains the value 02H and the source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the

R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, the C and the S flag values are "1".

2. Given: R1 = 05H and R2 = 0AH:

CP

JP

R1,R2

UGE,SKIP

INC R1

SKIP LD R3,R1

In this example, the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in the working register R3.

6-30


CPIJE

— Compare, Increment, and Jump on Equal

CPIJE

dst,src,RA

Operation:

If dst–src = "0", PC

← PC + RA

The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the

CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed.


Flags:

Format:


(Hex)


Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 02H:

In this example, the working register R1 contains the value 02H, the working register R2 the value

03H, and the register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the

@R2 value 02H (00000010B) to 02H (00000010B). Because the result of the comparison is

equal

, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H.

Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of + 127 to – 128.

6-31


CPIJNE

— Compare, Increment, and Jump on Non-Equal

CPIJNE

dst,src,RA

Operation:

If dst–src ≠ "0", PC

← PC + RA

The source operand is compared to (subtracted from) the destination operand. If the result is not

"0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction.


Flags:

Format:


(Hex)


Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 04H:

The working register R1 contains the value 02H, the working register R2 (the source pointer) the value 03H, and the general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-

equal

, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.

Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of + 127 to – 128.

6-32


DA

— Decimal Adjust

DA

dst

Operation:

dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed (The operation is undefined if the destination operand is not the result of a valid addition or subtraction of BCD digits):

Instruction Carry

Before DA

Bits 4–7

Value (Hex)

H Flag

Before DA

Bits 0–3

Value (Hex)

Number Added to Byte

Carry

After DA

0 0–9 0 0–9 00 0

0 0–8 0 A–F 06 0

0 0–9 1 0–3 06 0

ADD 0 A–F 0 0–9 60 1

ADC 0 9–F 0 A–F 66 1

SUB

SBC

Flags:

1 0–2 0 0–9 60 1

1 0–2 0 A–F 66 1

1 0–3 1 0–3 66 1

0 0–9 0 0–9 00 = – 00 0

C:

0

1

1

0–8

7–F

6–F

1

0

1

6–F

0–9

6–F

FA = – 06

A0 = – 60

9A = – 66

Set if there was a carry from the most significant bit; cleared otherwise (see table).

0

1

1

Z:

Set if result is "0"; cleared otherwise.

S:

Set if result bit 7 is set; cleared otherwise.

V:

Undefined.

D:

Unaffected.

H:

Unaffected.

Format:


(Hex)

Addr Mode dst

4 41 IR

6-33


DA

— Decimal Adjust

Example:

Given: The working register R0 contains the value 15 (BCD), the working register R1 contains 27

(BCD), and the address 27H contains 46 (BCD):

C

← 3CH + 06

If an addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using the standard binary arithmetic:

0 0 0 1 0 1 0 1 15

0 0 1 1 1 1 0 0 = 3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:

0 0 1 1 1 1 0 0

0 1 0 0 0 0 1 0 = 42

Assuming the same values given above, the statements

C

← 31–0

leave the value 31 (BCD) in the address 27H (@R1).

6-34


DEC

— Decrement

DEC

dst

Operation:

dst

The contents of the destination operand are decremented by one.

Flags: C:

Unaffected.

Z:


S:

V:

Set if result is negative; cleared otherwise.


D:

Unaffected.

H:

Unaffected.

Format:


(Hex)

Addr Mode dst

4 01 IR

Examples:


R1

@R1

R1 = 02H

Register 03H = 0FH

In the first example, if the working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.

6-35


DECW

— Decrement Word

DECW

dst

Operation:

dst

The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.

Flags: C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:


(Hex)

Addr Mode dst

8 81 IR

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

RR0

@R2

R0 = 12H, R1 = 33H

Register 30H = 0FH, register 31H = 20H

In the first example, the destination register R0 contains the value 12H and the register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H.

NOTE:

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction.

To avoid this problem, it is recommended to use DECW as shown in the following example.

6-36


DI

— Disable Interrupts

DI

Operation:

SYM (0)

← 0

Flags:

Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.


Format:


(Hex)

Example:

Given: SYM = 01H:

DI

If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing.

6-37


DIV

— Divide (Unsigned)

Operation:

dst ÷ src

dst (UPPER)

← REMAINDER

dst (LOWER)

← QUOTIENT

Flags:

Format:

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is

≥ 2

8

, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers.

C:

Set if the V flag is set and the quotient is between 2

8

and 2

9

–1; cleared otherwise.

Z:

Set if the divisor or the quotient = "0"; cleared otherwise.

S:

Set if MSB of the quotient = "1"; cleared otherwise.

V:

Set if the quotient is

≥ 2 8 or if the divisor = "0"; cleared otherwise.

D:

Unaffected.

H:

Unaffected.


(Hex)


Examples:

2

6

/10 *

2

6

/10 *

* Execution takes 10 cycles if the divide-by-zero is attempted, otherwise, it takes 2

6

cycles.

Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:

RR0,R2

→

R0 = 03H, R1 = 20H

In the first example, the destination working register pair RR0 contains the values 10H (R0) and

03H (R1), and the register R2 contains the value 40H. The statement "DIV RR0,R2" divides the

16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1).

6-38


DJNZ

— Decrement and Jump if Non-Zero

Operation:

r

If r

≠ 0, PC ← PC + dst

The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is + 127 to – 128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement.

NOTE:

In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0 or SRP1 instruction.


Flags:

Format:

Example:

r | opc dst 2 8 (jump taken)

(Hex)

rA

8 (no jump) r = 0 to F

Given: R1 = 02H and LOOP is the label of a relative address:

dst

RA

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, the working register R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements the register R1 by one, leaving the value 01H.

Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label.

6-39


EI

— Enable Interrupts

EI

Operation:

SYM (0)

← 1

Flags:

The EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have the highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when the EI instruction is executed.


Format:


(Hex)

Example:

Given: SYM = 00H:

EI

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.)

6-40


ENTER

— Enter

ENTER

Operation:

SP

PC

← @IP

Flags:

This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two.


Format:

Bytes Opcode

(Hex)

Example:

The diagram below shows an example of how to use an ENTER statement.

Address

IP 0050

Data

Before

PC 0040

0022

Address

40

41

42

43

Enter

Address H

Address L

Address H

Data

1F

01

10

Address

IP 0043

Data

After

PC 0110

0020

Address

40

41

42

43

Enter

Address H

Address L

Address H

Data

1F

01

10

Memory

110

Routine

Memory

22 Data

Stack

20

21

22

IPH

IPL

Data

00

50

Stack

6-41

INSTRUCTION SET

EXIT

— Exit

EXIT

Operation:

IP


This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.


Flags:

Format:


(Hex)

Example:

The diagram below shows an example of how to use an EXIT statement.

Address

IP 0050

Data

Before

Address

PC 0040

50

51

0020

PCL old

PCH

Data

60

00

Address

IP 0043

Data

After

Address

PC 0110

60

0022

Main

Data

20

21

22

IPH

IPL

Data

00

50

Stack

140 Exit

Memory

22 Data

Stack

Memory

6-42


IDLE

— Idle Operation

IDLE

Flags:

Operation:

(See

The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue.

Idle mode can be released by an interrupt request (IRQ) or an external reset operation.


Format:


(Hex)


Example:

The instruction IDLE stops the CPU clock but it does not stop the system clock.

6-43


INC

— Increment

Operation:

dst

The contents of the destination operand are incremented by one.

Flags: C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:

Bytes Cycles

dst | opc 1 4

Opcode

(Hex)

Addr Mode dst

rE r = 0 to F r

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

R0

→ Register 00H = 0DH

In the first example, if the destination working register R0 contains the value 1BH, the statement

"INC R0" leaves the value 1CH in that same register.

The second example shows the effect an INC instruction has on the register at the location 00H, assuming that it contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of the register 1BH from 0FH to 10H.

6-44


INCW

— Increment Word

Operation:

dst

The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

Flags: C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:


(Hex)

Addr Mode dst

Examples:

8 A1

Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:

IR

RR0

@R1

R0 = 1AH, R1 = 03H


In the first example, the working register pair RR0 contains the value 1AH in the register R0 and

02H in the register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in the register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of the general register 03H from 0FFH to 00H and the register 02H from 0FH to 10H.

NOTE:

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an

INCW instruction. To avoid this problem, it is recommended to use the INCW instruction as shown in the following example:

6-45

INSTRUCTION SET

IRET

— Interrupt Return

IRET

Operation:

FLAGS PC

↔ IP

FLAGS

← FLAGS'

FIS

← 0


This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Flags:

Format:

IRET

(Normal)

opc


(Hex)

IRET

(Fast)

Bytes Cycles Opcode

(Hex)

opc

Example:

In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled. When an interrupt occurs, the program counter and the instruction pointer are swapped. This causes the PC to jump to the address 100H and the IP to keep the return address. The last instruction in the service routine is normally a jump to IRET at the address

FFH.

This loads the instruction pointer with 100H "again" and causes the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H.

NOTE

:

0H

FFH

100H

IRET

Interrupt

Service

Routine

JP to FFH

FFFFH

In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last tow instruction. The IRET cannot be immediately proceeded by an instruction which clears the interrupt status (as with a reset of the IPR register).

6-46


JP

— JUMP

JP

cc,dst (Conditional)

JP

dst (Unconditional)

Operation:

If cc is true, PC

← dst

Flags:

The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC.


Format:

(1)

(2) cc | opc

(Hex) dst

dst 3 DA cc = 0 to F

NOTES:

1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2. In the first byte of the 3-byte instruction format (conditional jump), the condition code and the

OPCODE are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H

→

→

LABEL_W = 1000H, PC = 1000H

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-47


JR

— Jump Relative

JR

cc,dst

Operation:

If cc is true, PC

← PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction following the JR instruction is executed. (See the list of condition codes at the beginning of this chapter).

Flags:

The range of the relative address is +127, –128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement.


Format:

(note) cc | opc


(Hex)

Addr Mode dst

cc = 0 to F

NOTE:

In the first byte of the two-byte instruction format, the condition code and the opcode are each four

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

PC = 1FF7H

If the carry flag is set (that is, if the condition code is “true”), the statement "JR C,LABEL_X" will pass control to the statement whose address is currently in the program counter. Otherwise, the program instruction following the JR will be executed.

6-48


LD

— LOAD

LD

dst,src

Operation:

dst

Flags:

The contents of the source are loaded into the destination. The source's contents are unaffected.


Format:

dst | opc src


(Hex)


2 4 rC r IM src | opc opc dst dst | src 2

2 4

4

4

6 r9 r = 0 to F

C7

D7

E5

R r

Ir

R lr r r

IR opc opc dst | src src | dst x x

3

3

6

6 87

97 r x [r] x [r] r

6-49


LD

— Load

LD

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

R0,#10H

R0,01H

01H,R0

→

→

→

→

00H,01H

02H,@00H

00H,#0AH

@00H,#10H

R0,#LOOP[R1]

R0 = 10H

R0 = 20H, register 01H = 20H

Register 01H = 01H, R0 = 01H

R1 = 20H, R0 = 01H

R0 = 01H, R1 = 0AH, register 01H = 0AH



Register 00H = 0AH


Register 00H = 01H, register 01H = 02, register 02H = 02H

R0 = 0FFH, R1 = 0AH

Register 31H = 0AH, R0 = 01H, R1 = 0AH

6-50


LDB

— Load Bit

LDB

dst,src.b

LDB

dst.b,src

Operation:

dst(0) or

Flags:

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.


Format:

opc

opc dst


(Hex)


src 3 6 47 r0

3 6 47 Rb

NOTE:

In the second byte of the instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0 = 06H and general register 00H = 05H:

→

LDB 00H.0,R0



In the first example, the destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the

00H register into bit zero of the R0 register, leaving the value 07H in the register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of the register R0 to the specified bit (bit zero) of the destination register, leaving 04H in the general register 00H.

6-51


LDC/LDE

— Load Memory

LDC

LDE

dst,src dst,src

Operation:

dst

Flags:

This instruction loads a byte from program or data memory into a working register or vice-versa.

The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr" or "rr" values an even number for program memory and an odd number for data memory.


Format:

1. opc dst | src


(Hex)


XS

3 12 E7 r

XS

3 12 F7

XL

L

XL

L

XL

XL

H

H

DA

L

DA

L

DA

H

DA

H

DA

L

DA

H

DA

L

DA

H

NOTES:

1. The source (src) or the working register pair [rr] for formats 5 and 6 cannot use the register pair 0–1.

2. For the formats 3 and 4, the destination "XS [rr]" and the source address "XS [rr]" are both one byte.

3. For the formats 5 and 6, the destination "XL [rr] and the source address "XL [rr]" are both two bytes.

4. The DA and the r source values for the formats 7 and 8 are used to address program memory. The second set of values, used in the formats 9 and 10, are used to address data memory.

5. LDE instruction can be used to read/write the data of 64-Kbyte data memory.

6-52


LDC/LDE

— Load Memory

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations

0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.

External data memory locations

; R0 = 1AH, R2 = 01H, R3 = 04H

;

0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

;

LDC

LDE

@RR2,R0

@RR2,R0

0104H;

; R0 = 2AH, R2 = 01H, R3 = 04H

; 11H (contents of R0) is loaded into program memory

; location 0104H (RR2); R0, R2, R3

→ no change

; 11H (contents of R0) is loaded into external data memory

; location 0104H (RR2); R0, R2, R3

→ no change

LDC #01H[RR2],R0

LDE

; (01H + RR2); R0 = 6DH, R2 = 01H, R3 = 04H

;

0105H

; (01H + RR2); R0 = 7DH, R2 = 01H, R3 = 04H

#01H[RR2],R0

; 11H (contents of R0) is loaded into program memory location

; 0105H (01H + 0104H)


; location 0105H (01H + 0104H)

R0,#1000H[RR2]

; (1000H + 0104H); R0 = 88H, R2 = 01H, R3 = 04H

R0,#1000H[RR2]

← contents of external data memory location

1104H

R0,1104H

; (1000H + 0104H); R0 = 98H, R2 = 01H, R3 = 04H

;

R0,1104H

; R0 = 88H

;

LDC 1105H,R0

LDE 1105H,R0

1104H;

; R0 = 98H

; 11H (contents of R0) is loaded into program memory location


; location 1105H; (1105H)

← 11H

NOTE:

The LDC and the LDE instructions are not supported by masked ROM type devices.

6-53


LDCD/LDED

— Load Memory and Decrement

LDCD

dst,src

Operation:

dst

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.

LDCD refers to program memory and LDED refers to external data memory. The assembler

makes "Irr" an even number for program memory and an odd number for data memory.


Flags:

Format:

Examples:


(Hex)


opc dst | src 2 10 E2 r Irr

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH:

LDCD

LDED

R8,@RR6

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one;

; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6

← RR6 – 1)

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

(RR6

; R8 = 0DDH, R6 = 10H, R7 = 32H

NOTE:

LDED instruction can be used to read/write the data of 64-Kbyte data memory.

6-54


LDCI/LDEI

— Load Memory and Increment

LDCI

dst,src

Operation:

dst

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes

"Irr" an even number for program memory and an odd number for data memory.


Flags:

Format:

Examples:


(Hex)


opc dst | src 2 10 E3 r Irr

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI R8,@RR6

LDEI R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one

(RR6

; R8 = 0CDH, R6 = 10H, R7 = 34H

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one

(RR6

; R8 = 0DDH, R6 = 10H, R7 = 34H

`

NOTE:

LDEI instruction can be used to read/write the data of 64-Kbyte data memory.

6-55


LDCPD/LDEPD

— Load Memory with Pre-Decrement

LDCPD

dst,src

Operation:

rr

These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location.

The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes "Irr" an even number for program memory and an odd number for external data memory.


Flags:

Format:

Examples:

opc src | dst

Given: R0 = 77H, R6 = 30H, and R7 = 00H:


(Hex)


2 14 F2 Irr r

NOTE:

; 77H (the contents of R0) is loaded into program memory

; location 2FFFH (3000H – 1H);

; R0 = 77H, R6 = 2FH, R7 = 0FFH

;

; 77H (the contents of R0) is loaded into external data memory

; location 2FFFH (3000H – 1H);

LDEPD instruction can be used to read/write the data of 64-Kbyte data memory.

6-56


LDCPI/LDEPI

— Load Memory with Pre-Increment

LDCPI

dst,src

Operation:

rr

These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory.


Flags:

Format:

Examples:


(Hex)


14 F3 Irr r opc src | dst

Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:

2

NOTE:

; 7FH (the contents of R0) is loaded into program memory

; location 2200H (21FFH + 1H);

; R0 = 7FH, R6 = 22H, R7 = 00H

;

; 7FH (the contents of R0) is loaded into external data memory

; location 2200H (21FFH + 1H);

; R0 = 7FH, R6 = 22H, R7 = 00H

LDEPI instruction can be used to read/write the data of 64-Kbyte data memory.

6-57


LDW

— Load Word

LDW

dst,src

Operation:

dst

The contents of the source (a word) are loaded into the destination. The contents of the source

Flags:

Format:


Bytes

(Hex)


8 C5 IR

Examples:

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H,

register 02H = 03H,and register 03H = 0FH

RR6,RR4 R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH

Register 00H = 03H, register 01H = 0FH,

RR2,@R7 register 02H = 03H, register 03H = 0FH

R2 = 03H, R3 = 0FH,

→

→

R6 = 12H, R7 = 34H

In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H and 03H into the destination word 00H and 01H. This leaves the value 03H in the general register 00H and the value 0FH in the register 01H.

Other examples show how to use the LDW instruction with various addressing modes and formats.

6-58


MULT

— Multiply (Unsigned)

MULT

dst,src

Operation:

dst

Flags:

The 8-bit destination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers.

C:

> 255; cleared otherwise.

Z:


S:

Set if MSB of the result is a "1"; cleared otherwise.

V:

Cleared.

D:

Unaffected.

H:

Unaffected.

Format:


(Hex)


22 85 IR

22 86 IM

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

02H Register 00H = 01H, register 01H = 20H,

00H, register 02H = 09H

Register 00H = 00H, register 01H = 0C0H

In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H).

The 16-bit product, 0120H, is stored in the register pair 00H, 01H.

6-59


NEXT

— Next

NEXT

Operation:

PC

The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.


Flags:

Format:


(Hex)

Example:

The following diagram shows an example of how to use the NEXT instruction.

Before

Address

IP 0043

Data

PC

0120

Address

43

44

45

Address H

Address L

Address H

01

30

Address

IP 0045

Data

After

PC

0130

Address

43

44

45

Address H

Address L

Address H

Data

120 Next

Memory

130 Routin e

Memory

6-60


NOP

— No Operation

NOP

Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are

executed in sequence in order to affect a timing delay of variable duration.

Flags:


Format:


(Hex)

Example:

When the instruction NOP is executed in a program, no operation occurs. Instead, there happens

a delay in instruction execution time which is of approximately one machine cycle per each NOP

instruction encountered.

6-61


OR

— Logical OR

OR

dst,src

Operation:

dst

Flags:

The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1", otherwise, a "0" is stored.

C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:


(Hex)



6 43 lr

6 45 IR

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H,

and register 08H = 8AH

R0,R1

R0,@R2

R0 = 3FH, R1 = 2AH

R0 = 37H, R2 = 01H, register 01H = 37H

00H,01H Register 00H = 3FH, register 01H = 37H

Register 00H = 08H, register 01H = 0BFH

00H,#02H Register 00H = 0AH

In the first example, if the working register R0 contains the value 15H and the register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in the destination register R0.

Other examples show the use of the logical OR instruction with various addressing modes and formats.

6-62


POP

— Pop from Stack

POP

dst

Operation:

dst

The contents of the location addressed by the stack pointer are loaded into the destination.

The stack pointer is then incremented by one.


Flags:

Format:


(Hex)

Addr Mode dst

8 51 IR

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H:

→

→

Register 00H = 55H, SP = 00FCH

Register 00H = 01H, register 01H = 55H, SP = 00FCH

In the first example, the general register 00H contains the value 01H. The statement "POP 00H" loads the contents of the location 00FBH (55H) into the destination register 00H and then increments the stack pointer by one. The register 00H then contains the value 55H and the SP points to the location 00FCH.

6-63


POPUD

— Pop User Stack (Decrementing)

POPUD

dst,src

Operation:

dst

This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.


Flags:

Format:


(Hex)


Example:

Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and

register 02H = 70H:

6FH

If the general register 00H contains the value 42H and the register 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of the register 42H into the destination register. The user stack pointer is then decremented by one, leaving the value 41H.

6-64


POPUI

— Pop User Stack (Incrementing)

POPUI

dst,src

Operation:

dst

The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.


Flags:

Format:

Example:


(Hex)


Given: Register 00H = 01H and register 01H = 70H:

70H

If the general register 00H contains the value 01H and the register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H.

The user stack pointer (the register 00H) is then incremented by one, changing its value from 01H to 02H.

6-65


PUSH

— Push to Stack

PUSH

src

Operation:

SP

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.


Flags:

Format:

Examples:

opc src 2 8 (internal clock)

8 (external clock)

(Hex)

70

8 (internal clock)

8 (external clock) 71

Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:

dst

R

IR

@40H

Register 40H = 4FH, stack register 0FFH = 4FH,

SPH = 0FFH, SPL = 0FFH

Register 40H = 4FH, register 4FH = 0AAH, stack register

0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH

In the first example, if the stack pointer contains the value 0000H, and the general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of the register 40H into the location 0FFFFH and adds this new value to the top of the stack.

6-66


PUSHUD

— Push User Stack (Decrementing)

PUSHUD

dst,src

Operation:

IR

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.


Flags:

Format:

Example:


(Hex)


Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: register 02H = 05H

If the user stack pointer (the register 00H, for example) contains the value 03H, the statement

"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H.

The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer.

6-67


PUSHUI

— Push User Stack (Incrementing)

PUSHUI

dst,src

Operation:

IR

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.


Flags:

Format:

Example:


(Hex)


Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: register 04H = 05H

If the user stack pointer (the register 00H, for example) contains the value 03H, the statement

"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer.

6-68


RCF

— Reset Carry Flag

RCF

RCF

Operation:

C

The carry flag is cleared to logic zero, regardless of its previous value.

Format:


Example:


(Hex)

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

6-69


RET

— Return

RET

Operation:

PC

The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement to be executed is the one that is addressed by the new program counter value.


Flags:

Format:

Example:


(Hex)

Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:

RET

→

PC = 101AH, SP = 00FEH

The RET instruction pops the contents of the stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in the location 00FEH (1AH) into the PC's low byte and the instruction at the location 101AH is executed. The stack pointer now points to the memory location 00FEH.

6-70


RL

— Rotate Left

RL

dst

Operation:

C dst (0)

← dst (7) dst (n + 1)

← dst (n), n = 0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag, as shown in the figure below.

C

C:

Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

7 0

Flags:

Format:


(Hex)

Addr Mode dst

4 91 IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

→

→

Register 00H = 55H, C = "1"

Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if the general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H

(01010101B) and setting the carry (C) and the overflow (V) flags.

6-71


Flags:

Format:

RLC

— Rotate Left through Carry

RLC

dst

Operation:

dst (0)

← C dst (n + 1)

← dst (n), n = 0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C), and the initial value of the carry flag replaces bit zero.

7 0

C

C:

Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z:


S:


V:

Set if arithmetic overflow occurred, that is, if the sign of the destination is changed during

the rotation; cleared otherwise.

D:

Unaffected.

H:

Unaffected.


(Hex)

Addr Mode dst

4 11 IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

00H

@01H


Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if the general register 00H has the value 0AAH (10101010B), the statement

"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register 00H, leaving the value 55H

(01010101B). The MSB of the register 00H resets the carry flag to "1" and sets the overflow flag.

6-72


RR

— Rotate Right

RR

dst

Operation:

C dst (7)

← dst (0) dst (n)

← dst (n + 1), n = 0–6

The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7 0

C

Flags: C:

Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z:


S:


V:



D:

Unaffected.

H:

Unaffected.

Format:


(Hex)

Addr Mode dst

4 E1

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

→

→


IR

Register 01H = 02H, register 02H = 8BH, C = "1"

In the first example, if the general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and the overflow flag are also set to "1".

6-73


RRC

— Rotate Right through Carry

Operation:

dst (7)

← C dst (n)

← dst (n + 1), n = 0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag, and the initial value of the carry flag replaces bit 7 (MSB).

Flags:

Format:

7 0

C

C:

Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z:

Set if the result is "0" cleared otherwise.

S:


V:



D:

Unaffected.

H:

Unaffected.


(Hex)

Addr Mode dst

4 C1

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

IR

00H

@01H

Register 00H = 2AH, C = "1"

Register 01H = 02H, register 02H = 0BH, C = "1"

In the first example, if the general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero

("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in the destination register 00H. The sign flag and the overflow flag are both cleared to "0".

6-74


SB0

— Select Bank 0

SB0

Operation:

BANK

Flags:

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file.


Format:


(Hex)

Example:

The

SB0

clears FLAGS.0 to "0", selecting the bank 0 register addressing.

6-75


SB1

— Select Bank 1

SB1

Operation:

BANK

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file.

NOTE:

Bank 1 is not implemented in some KS88-series microcontrollers.


Flags:

Format:


(Hex)

Example:

The

SB1

sets FLAGS.0 to “1”, selecting the bank 1 register addressing

(if bank 1 is implemented in the microcontroller’s internla register file).

6-76


SBC

— Subtract with Carry

SBC

dst,src

Operation:

dst

The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry

("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.

Flags: C:

Set if a borrow occurred (src

> dst); cleared otherwise.

Z:


S:


V:

D:

Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the

sign of the result is the same as the sign of the source; cleared otherwise.

Always set to "1".

H:

Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a “borrow”

Format:

opc dst | src


(Hex)


2 4 32 r r

6 33 lr

6 35 IR

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H,

and register 03H = 0AH:

→

→

→

→

R1 = 0CH, R2 = 03H

R1 = 05H, R2 = 03H, register 03H = 0AH

Register 01H = 1CH, register 02H = 03H

Register 01H = 15H, register 02H = 03H, register 03H = 0AH

Register 01H = 95H; C, S, and V = "1"

In the first example, if the working register R1 contains the value 10H and the register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value

("1") from the destination (10H) and then stores the result (0CH) in the register R1.

6-77


SCF

— Set Carry Flag

SCF

Operation:

C

← 1

The carry flag (C) is set to logic one, regardless of its previous value.

Flags: C:

Set to "1".


Format:


(Hex)

Example:

The statement SCF sets the carry flag to “1”.

6-78


SRA

— Shift Right Arithmetic

SRA

dst

Operation:

dst (7)

← dst (7) dst (n)

← dst (n + 1), n = 0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6.

7 6 0

C

C:

Set if the bit shifted from the LSB position (bit zero) was "1".

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Flags:

Format:


(Hex)

Addr Mode dst

4 D1 IR

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

→

→

Register 00H = 0CD, C = "0"

Register 02H = 03H, register 03H = 0DEH, C = "0"

In the first example, if the general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in the register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged).

This leaves the value 0CDH (11001101B) in the destination register 00H.

6-79


SRP/SRP0/SRP1

— Set Register Pointer

SRP

src

SRP0

SRP1

src src

Operation:

If src (1) = 1 and src (0) = 0 then: RP0 (3–7)

←


←


←

Flags:

src (3–7)

src (3–7)

src (4–7),

0

src (4–7),

1

The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.


Format:


(Hex)

Addr Mode src

Examples:

The statement SRP #40H sets the register pointer 0 (RP0) at the location 0D6H to 40H and the

register pointer 1 (RP1) at the location 0D7H to 48 H.

The statement "SRP0 #50H" would set RP0 to 50H, and the statement "SRP1 #68H" would set

RP1 to 68H.

NOTE:

Before execute the STOP instruction, You must set the STPCON register as “10100101b”.

Otherwise the STOP instruction will not execute.

6-80


STOP

— Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the

RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.

Flags:


Format:


(Hex)


Example:

The statement STOP halts all microcontroller operations.

6-81


SUB

— Subtract

SUB

dst,src

Operation:

dst

Flags:

The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

C:

Set if a "borrow" occurred; cleared otherwise.

Z:


S:


V:

Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the

sign of the result is of the same as the sign of the source operand; cleared otherwise.

D:

Always set to "1".

H:

Cleared if there is a carry from the most significant bit of the low-order four bits of the

result; set otherwise indicating a “borrow”.

Format:

Bytes Cycles

opc dst | src 2 4

Opcode

(Hex)


22 r r

Examples:


→

→

→

→

R1 = 0FH, R2 = 03H

R1 = 08H, R2 = 03H

Register 01H = 1EH, register 02H = 03H


01H,#90H Register 01H = 91H; C, S, and V = "1"

01H,#65H Register 01H = 0BCH; C and S = "1", V = "0"

In the first example, if he working register R1 contains the value 12H and if the register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in the destination register R1.

6-82


SWAP

— Swap Nibbles

SWAP

dst

Operation:

dst (0 – 3)

↔ dst (4 – 7) swapped.

The contents of the lower four bits and the upper four bits of the destination operand are

7 4 3 0

C:

Undefined.

Z:


S:


V:

Undefined.

D:

Unaffected.

H:

Unaffected.

Flags:

Format:


(Hex)

Addr Mode dst

4 F1

Examples:

Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:

SWAP 00H

→

@02H

Register 00H = 0E3H

Register 02H = 03H, register 03H = 4AH

IR

In the first example, if the general register 00H contains the value 3EH (00111110B), the statement "SWAP 00H" swaps the lower and the upper four bits (nibbles) in the 00H register, leaving the value 0E3H (11100011B).

6-83


TCM

— Test Complement under Mask

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and the source operands are unaffected.

Flags: C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:

opc dst | src


(Hex)


2 4 62 r r

6 63 lr

6 65 IR

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and

register 02H = 23H:

→

→

R0 = 0C7H, R1 = 02H, Z = "1"

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

00H,01H Register 00H = 2BH, register 01H = 02H, Z = "1"

Register 00H = 2BH, register 01H = 02H,

00H,#34 register 02H = 23H, Z = "1"

Register 00H = 2BH, Z = "0"

In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.

6-84


TM

— Test under Mask

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and the source operands are unaffected.

Flags: C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:

opc dst | src


(Hex)


2 4 72 r r

6 73 lr

6 75 IR

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and

register 02H = 23H:

→

→

R0 = 0C7H, R1 = 02H, Z = "0"

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

00H,01H Register 00H = 2BH, register 01H = 02H, Z = "0"

Register 00H = 2BH, register 01H = 02H,

00H,#54H register 02H = 23H, Z = "0"

Register 00H = 2BH, Z = "1"

In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.

6-85


WFI

— Wait for Interrupt

WFI

Operation:

The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take

place during this wait state. The WFI status can be released by an internal interrupt, including a

fast interrupt.

Flags:


Format:


(Hex)

( n = 1, 2, 3, … )

Example:

The following sample program structure shows the sequence of operations that follow a "WFI"

statement:

.

.

.

Main program

EI

.

.

.

WFI

(Next instruction)

Interrupt occurs

.

.

.

Interrupt service routine

Clear interrupt flag

IRET

(Enable global interrupt)

(Wait for interrupt)

Service routine completed

6-86


XOR

— Logical Exclusive OR

Operation:

dst

The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different. Otherwise, a "0" bit is stored.

Flags: C:

Unaffected.

Z:


S:


V:


D:

Unaffected.

H:

Unaffected.

Format:

Bytes Cycles

opc dst | src 2 4

6

Opcode

(Hex)


B2

B3 r r r lr

6 B5 R IR

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:

→

→

→

→

R0 = 0C5H, R1 = 02H

R0 = 0E4H, R1 = 02H, register 02H = 23H


Register 00H = 08H, register 01H = 02H,

00H,#54H register 02H = 23H

Register 00H = 7FH

In the first example, if the working register R0 contains the value 0C7H and if the register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.

6-87


7

CLOCK CIRCUIT

OVERVIEW

The clock frequency generated for the S3C84MB/F84MB by an external crystal can range from 1 MHz to 16 MHz.

The maximum CPU clock frequency is 16 MHz. The X

IN

and X

OUT

pins connect the external oscillator or clock source to the on-chip clock circuit.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal or ceramic resonator oscillation source (or an external clock source)

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (f

XX

divided by 1, 2, 8, or 16)

— System clock control register, CLKCON

C1 X

IN

S3C84MB/

F84MB

C2 X

OUT

Figure 7-1. Main Oscillator Circuit (Crystal or Ceramic Oscillator)

7-1

CLOCK CIRCUIT S3C84MB/F84MB_UM_REV1.00

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock.

— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/ counters. Idle mode is released by a reset or by an external or internal interrupt.

Main-System

Oscillator

Circuit

STOP Instruction fxx

1/8-1/4096

Frequency

Dividing

Circuit

1/1 1/2 1/8 1/16

CLKCON.4-.3

Selector 2

IDLE Instruction

Figure 7-2. System Clock Circuit Diagram

PERI

CPU

7-2


SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in the bank 0 of set 1, address D4H. It is read/write addressable and has the following functions:

— Oscillator frequency divide-by value

After the main oscillator is activated, and the f

XX

/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to f

XX

/8, f

XX

/2, or f

XX

/1.

When the divided clock is selected to system clock, be careful using interrupt. If the interrupt interval is short than interrupt service routine processing time, interrupt request cannot be guaranteed.

MSB .7

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not used (must keep always 0) Not used (must keep always 0)

Divide-by selection bits for

CPU clock frequency:

00 = fxx/16

01 = fxx/8

10 = fxx/2

11 = fxx/1 (non-divided)

Figure 7-3. System Clock Control Register (CLKCON)

7-3


RESET

and POWER-DOWN

8

RESET and POWER-DOWN

SYSTEM RESET

OVERVIEW

During a power-on reset, the voltage at V

DD

goes to High level and the RESETB pin is forced to Low level. The

RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C84MB/F84MB into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the RESETB pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond.

Whenever a reset occurs during normal operation (that is, when both V

DD

and RESETB are High level), the

RESETB pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values.

In summary, the following sequence of events occurs during a reset operation:

— Interrupt is disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0-8 are set to input mode(Port 6 is set to open-drain output).

— Peripheral control and data registers are disabled and reset to their default hardware values.

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed.

NORMAL MODE RESET OPERATION

In normal (masked ROM) mode, the Test pin is tied to V

SS

. A reset enables access to the 64-Kbyte on-chip ROM.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON.

8-1

RESET

and POWER-DOWN S3C84MB/F84MB_UM_REV1.00

HARDWARE RESET VALUES

Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An "x" means that the bit value is undefined after a reset.

— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.

Table 8-1. S3C84MB/F84MB Set 1, Bank 0 Register Values after RESET

Register Name

Address Bit Values After RESET

Mnemonic

Dec Hex 7 6 5 4 3 2 1 0

TBCON 208 D0H 0 0 0 0 0 0 0 0

TBDATAH 209 D1H 1 1 1 1 1 1 1 1

TBDATAL 210 D2H 1 1 1 1 1 1 1 1

BTCON 211 D3H 0 0 0 0 0 0 0 0

CLKCON 212 D4H 0 0 0 0 0 0 0 0

FLAGS 213 D5H x x x x x x 0 0

RP0 214 D6H 1 1 0 0 0 – – –

RP1 215 D7H 1 1 0 0 1 – – –

SPH 216 D8H x x x x x x x x

SPL 217 D9H x x x x x x x x

IPH 218 DAH x x x x x x x x

IPL 219 DBH x x x x x x x x

IRQ 220 DCH 0 0 0 0 0 0 0 0

IMR 221 DDH x x x x x x x x

SYM 222 DEH 0 – – x x x 0 0

PP 223 DFH 0 0 0 0 0 0 0 0

8-2


RESET

and POWER-DOWN


Register Name Mnemonic

Address Bit Values After Reset

Dec Hex 7 6 5 4 3 2 1 0

P0 224 E0H 0 0 0 0 0 0 0 0

P1 225 E1H 0 0 0 0 0 0 0 0

P2 226 E2H 0 0 0 0 0 0 0 0

P3 227 E3H 0 0 0 0 0 0 0 0

P4 228 E4H 0 0 0 0 0 0 0 0

P5 229 E5H 0 0 0 0 0 0 0 0

P6 230 E6H 0 0 0 0 0 0 0 0

P7 231 E7H 0 0 0 0 0 0 0 0

P8 232 E8H – – 0 0 0 0 0 0 pending 233 E9H – – 0 0 0 0 0 0

TACON 234 EAH 0 0 0 0 0 0 0 –

TADATA 235 EBH 1 1 1 1 1 1 1 1

TACNT 236 ECH 0 0 0 0 0 0 0 0

P8CONH 237 EDH – – – – 0 0 0 0

P8CONL 238 EEH 0 0 0 0 0 0 0 0

P8INTPND 239 EFH – – 0 0 – – 0 0

P0CON 240 F0H 0 0 0 0 0 0 0 0

P1CON 241 F1H 0 0 0 0 0 0 0 0

P2CONH 242 F2H 0 0 0 0 0 0 0 0

P2CONL 243 F3H 0 0 0 0 0 0 0 0

P3CONH 244 F4H 0 0 0 0 0 0 0 0

P3CONL 245 F5H 0 0 0 0 0 0 0 0

P4CONH 246 F6H 0 0 0 0 0 0 0 0

P4CONL 247 F7H 0 0 0 0 0 0 0 0

P5CONH 248 F8H 0 0 0 0 0 0 0 0

P5CONL 249 F9H 0 0 0 0 0 0 0 0

P4INT 250 FAH 0 0 0 0 0 0 0 0

P4INTPND 251 FBH 0 0 0 0 0 0 0 0

Location FCH is factory use only

BTCNT 253 FDH 0 0 0 0 0 0 0 0

Location FEH is not mapped

IPR 255 FFH x x x x x x x x

8-3

RESET



Register Name Mnemonic


Dec Hex 7 6 5 4 3 2 1 0

SIODATA 224 E0H 0 0 0 0 0 0 0 0

SIOCON 225 E1H 0 0 0 0 0 0 0 0

UDATA0 226 E2H 1 1 1 1 1 1 1 1

UARTCON0 227 E3H 0 0 0 0 0 0 0 0

BRDATA0 228 E4H 1 1 1 1 1 1 1 1

UARTPND 229 E5H – – 0 0 0 0 0 0

(high 230 E6H 1 1 1 1 1 1 1 1

(low T1DATAL0 231 E7H 1 1 1 1 1 1 1 1

(high 232 E8H 1 1 1 1 1 1 1 1

(low T1DATAL1 233 E9H 1 1 1 1 1 1 1 1

T1CON0 234 EAH 0 0 0 0 0 0 0 0

T1CON1 235 EBH 0 0 0 0 0 0 0 0 register(high 0 0 0 0 0 0 0 0 register(low 0 0 0 0 0 0 0 0 register(high 0 0 0 0 0 0 0 0 register(low 0 0 0 0 0 0 0 0

TCDATA0 240 F0H 1 1 1 1 1 1 1 1

TCDATA1 241 F1H 1 1 1 1 1 1 1 1

TCCON0 242 F2H 0 0 0 0 0 0 0 0

TCCON1 243 F3H 0 0 0 0 0 0 0 0

SIOPS 244 F4H 0 0 0 0 0 0 0 0

P7CON 245 F5H 0 0 0 0 0 0 0 0

Location F6H is not mapped.

ADCON 247 F7H 0 0 0 0 0 0 0 0

A/D converter data register(high byte) ADDATAH 248 F8H 0 0 0 0 0 0 0 0

A/D converter data register(low byte) 249 F9H 0 0 0 0 0 0 0 0

UDATA1 250 FAH 1 1 1 1 1 1 1 1

UARTCON1 251 FBH 0 0 0 0 0 0 0 0

BRDATA1 252 FCH 1 1 1 1 1 1 1 1

FMCON 253 FDH 0 0 0 0 0 0 0 0 control PGCON 254 FEH – – – – 0 0 0 0

PGDATA 255 FFH 0 0 0 0 0 0 0 0

8-4


RESET

and POWER-DOWN

Table 8-4. S3C84MB/F84MB Page 8 Register Values after RESET

Register Name



Mnemonic

Dec Hex 7 6 5 4 3 2 1 0

SIOCON1 0 00H 0 0 0 0 0 0 0 0

SIOPS1 1 01H 0 0 0 0 0 0 0 0

SIODATA1 2 02H 0 0 0 0 0 0 0 0

UARTCON2 3 03H 0 0 0 0 0 0 0 0

BRDATA2 4 04H 1 1 1 1 1 1 1 1

UDATA2 5 05H 1 1 1 1 1 1 1 1

UARTPRT 6 06H – 0 0 0 – 0 0 0

PWMCON 7 07H – 0 0 0 – – – 0

PWMDAT0 8 08H 1 1 1 1 1 1 1 1

PWM0EX 9 09H 0 0 0 0 0 0 – –

PWMDAT1 10 0AH 1 1 1 1 1 1 1 1

PWM1EX 11 0BH 0 0 0 0 0 0 – –





PWMDAT2 12 0CH 1 1 1 1 1 1 1 1

PWMDAT3 13 0DH 1 1 1 1 1 1 1 1

P1CONEX 14 0EH 0 0 0 0 – – 0 0

P6CON 15 0FH – 0 0 0 0 0 0 0

STOPCON 16 10H 0 0 0 0 0 0 0 0

Flash memory user enable register FMUSR 17 11H 0 0 0 0 0 0 0 0

Flash memory sector register(High FMSECH 18 12H 0 0 0 0 0 0 0 0

Flash memory sector register(Low byte) FMSECL 19 13H 0 0 0 0 0 0 0 0

8-5

RESET


POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than

200

μA. All system functions stop when the clock "freezes," but data stored in the internal register file is retained.

Stop mode can be released in one of two ways: by a reset or by interrupts.

NOTE

Do not use stop mode if you are using an external clock source because X

IN

input must be restricted internally to V

SS

to reduce current leakage.

Using RESET to Release Stop Mode

Stop mode is released when the RESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to

'00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H (and 0101H).

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode.

The external interrupts in the S3F84MBJ interrupt structure that can be used to release Stop mode are:

— External interrupts P4.0/INT0-P4.7/INT7, P8.4/INT8 and P8.5/INT9

Please note the following conditions for Stop mode release:

— If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged.

— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering

Stop mode.

— When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used.

— The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed.

Using an internal Interrupt to Release Stop Mode

Activate any enabled interrupt, causing stop mode to be released. Other things are same as using external interrupt.

8-6


RESET

and POWER-DOWN

IDLE MODE

Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered.

There are two ways to release idle mode:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock f

XX

/16 because CLKCON.4 and CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode.

2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed.

8-7


9

I/O PORTS

OVERVIEW

The S3C84MB/F84MB microcontroller has nine bit-programmable I/O ports, P0-P8. The port 8 are 6-bit ports and the others are 8-bit ports. This gives a total of 70 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.

Table 9-1 gives you a general overview of the S3C84MB/F84MB I/O port functions.

Table 9-1. S3C84MB/F84MB Port Configuration Overview

6

7

8

0

1

2

3

4

5

Bit programmable port; input or output mode selected by software; input or push-pull output.


Alternately, P0.0-P0.7 can be used as the PG output port (PG0-PG7).


Software assignable pull-up. Alternately, P1.4~P1.7 can be used as PWM0 ~ PWM4 output and

P1.0~P1.1 can be used as UART2 Tx, Rx



Alternately, P2.0~P2.7 can be used as I/O for TIMERA, TIMERB, SIO



Alternately, P3.0~P3.7 can be used as I/O for TIMERC0/C1, TIMER10/11



P4.0-P4.7 can alternately be used as inputs for external interrupts INT0-INT7, respectively (with noise filters and interrupt controller)



Alternately, P5.0~P5.3 can be used as I/O for serial port UART0, UART1, respectively.

N-channel, open-drain output only port. Alternately, P6.0~P6.6 can be used as ADC8~ADC14 input

General-purpose digital input ports. Alternatively used as analog input pins for A/D converter modules.



P8.4, P8.5 can alternately be used as inputs for external interrupts INT8, INT9, respectively (with noise filters and interrupt controller) P8.0~P8.2 can be used as I/O SIO1

9-1

I/O PORTS S3C84MB/F84MB_UM_REV1.00

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all five S3C84MB/F84MB I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, 6, 7 and 8 have the general format shown in Table 9-2.

Register Name










Table 9-2. Port Data Register Summary

Mnemonic

P0

P1

P2

P3

P4

P5

P6

P7

P8

Decimal

224

225

226

227

228

229

230

231

232

Hex

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

Location

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

Set 1, Bank 0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

9-2


PORT 0

Port 0 is an 8-bit I/O Port that you can use two ways:

— Alternative function: PGOUT7-PGOUT0

Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0.

Port 0 Control Register (P0CON)

Port 0 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 0:

P0CON (F0H).

When programming the port, please remember that any alternative peripheral I/O function you configure using the port 0 control registers must also be enabled in the associated peripheral module.

9-3


MSB .7

.6

Port 0 Control Register (P0CON)

F0H, Set 1, Bank 0, R/W

.5

.4

.3

.2

.1

.0

LSB

P0.7/P0.6/

P0.5/P0.4/

PGOUT[7:4]

P0.3/P0.2/

PGOUT[3:2]

P0.1/

PGOUT[1]

P0.0/

PGOUT[0]

.7 .6 bit/P0.7/P0.6/P0.5/P0.4

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative function mode(PGOUT[7:4])

.5 .4 bit/P0.3/P0.2

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative function mode(PGOUT[3:2])

.3 .2 bit/P0.1

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative function mode(PGOUT[1])

.1 .0 bit/P0.0

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative function mode(PGOUT[0])

Figure 9-1. Port 0 Control Register (P0CON)

9-4


PORT 1


— Alternative function: PWM0~PWM3 output




P1CON (F1H).


Alternative function (PWM0~PWM3) can be controlled in P1CONEX(PORT1 Extension Control register).

9-5


MSB

.7

.6



.5

.4

.3

.2

.1

.0

LSB

P1.7/P1.6

P1.5/P1.4

.7 .6 bit/P1.7/P1.6

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Not Used

.5 .4 bit/P1.5/P1.4

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Not Used

.3 .2 bit/P1.3/P1.2

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Not Used

.1 .0 bit/P1.1/P1.0

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Not Used

P1.3/P1.2

P1.1/P1.0


9-6


MSB

.7

Port 1 Extension Control Register (P1CONEX)


.6

.5

.4

.3

.2

.1

.0

LSB

P1.7

P1.6

P1.5

P1.4

Not Used

.7 / P1.7

0 Normal Port 1.7 Fucntion

1 Alternative function PWM3

.6 / P1.6



.5 / P1.5



.4 / P1.4



.3 .2 Not Used

.1 / P1.1


1 Alternative function UART2 Rx

(NOTE.1)

.0 / P1.0


1 Alternative function UART2 Tx

P1.1

P1.0

Figure 9-3. Port 1 Extension Control Register (P1CONEX)

NOTE: When the UART2 is operating in mode 0 (SIO) Rx input, P1CONEX.1 must be set to ‘0’ and P1CON.0-1 must be set to input mode or input with pull-up mode(‘00’ or ‘10’). In other operating modes(mode 0 Rx output, mode1, 2, 3),

P1CONEX.0-1 must be set to ‘1’ and P1CON.0-1 values are don’t care.

9-7


PORT 2

Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E2H in set 1, bank 0. P2.0–P2.7 can serve as inputs, outputs (push pull) or you can configure the following alternative functions:

— Low-byte pins (P2.0-P2.2): SCK0, SI0, SO0

— High-byte pins (P2.4-P2.7): TAOUT, TACAP, TACK, TBPWM

Port 2 Control Register (P2CONH, P2CONL)

Port 2 has two 8-bit control registers: P2CONH for P2.4–P2.7 and P2CONL for P2.0–P2.3. A reset clears the

P2CONH and P2CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull) and enable the alternative functions.


9-8


MSB .7

Port 2 Control Register, High Byte (P2CONH)


.6

.5

.4

.3

.2

.1

.0

LSB

P2.7/TAOUT

P2.6/TACAP

P2.5/TACK

P2.4/TBPWM

.7 .6 bit/P2.7/TAOUT

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative output mode(TAOUT)

00

01

10

11

.5 .4 bit/P2.6/TACAP

Input mode(TACAP)

Input mode, pull-up(TACAP)

Push-pull output

Not used

00

01

10

11

.3 .2 bit/P2.5/TACK

Input mode(TACK)

Input mode, pull-up(TACK)

Push-pull output

Not used

00

01

10

11

.1 .0 bit/P2.4/TBPWM

Input mode

Input mode, pull-up

Push-pull output

Alternative output mode(TBPWM)

NOTE:

When use this port 2, user must be care of the pull-up resistance status.

Figure 9-4. Port 2 High-Byte Control Register (P2CONH)

9-9


MSB .7

Port 2 Control Register, Low Byte (P2CONL)


.6

.5

.4

.3

.2

.1

.0

LSB

P2.3

P2.2/SCK0

.7 .6 bit/ P2.3

00 Input mode

01 Input mode, pull-up

10

11

Push-pull output

Not Used

P2.1/SI0

.5 .6 bit / P2.2 / SCK0

00 Input mode (SCK0 Input)

01 Input mode, pull-up (SCK0 Input)

10 Push-pull output

11 Alternative Function (SCK0 output)

.3 .2 bit / P2.1 / SI0

00 Input mode (SI0)

01 Input mode, pull-up (SI0)

10

11

Push-pull output

Not Used

.1 .0 bit / P2.0 / SO0

00 Input mode


10 Push-pull output

11 Alternative Function (SO0)

P2.0/SO0

NOTE: When use this port 2, user must be care of the pull-up resistance status.

Figure 9-5. Port 2 Low-Byte Control Register (P2CONL)

9-10


PORT 3

Port 3 is an 8-bit I/O port that can be used for general-purpose I/O. The pins are accessed directly by writing or reading the port 3 data register, P3 at location E3H in set 1, bank 0. P3.7–P3.0 can serve as inputs, outputs (push pull) or you can configure the following alternative functions:

— Low-byte pins (P3.0-P3.3): T1CAP1, T1CAP0, T1CK1, T1CK0

— High-byte pins (P3.4-P3.7): TCOUT1, TCOUT0, T1OUT1, T1OUT0

To individually configure the port 3 pins P3.0–P3.7, you make bit-pair settings in two control registers located in set 1, bank 0: P3CONL (low byte, F5H) and P3CONH (high byte, F4H).

Port 3 Control Registers (P3CONH, P3CONL)

Two 8-bit control registers are used to configure port 3 pins: P3CONL (F5H, set 1, Bank 0) for pins P3.0–P3.3 and

P3CONH (F4H, set 1, Bank 0) for pins P3.4–P3.7. Each byte contains four bit-pairs and each bit-pair configures one pin of port 3.

9-11




MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

P3.4/T1OUT0

P3.5/T1OUT1

P3.6/TCOUT0

P3.7/TCOUT1

.7 .6 bit : P3.7/TCOUT1

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative function(TCOUT1)

.5 .4 bit : P3.6/TCOUT0

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative function(TCOUT0)

.3 .2 bit : P3.5/T1OUT1

00

01

10

11

Input mode

Input mode, pull-up

Push-pull outputt

Alternative function(T1OUT1)

.1 .0 bit : P3.4/T1OUT0

00

Input mode

01

Input mode, pull-up

10

Push-pull outputt

11

Alternative function(T1OUT0)


9-12


MSB .7



.6

.5

.4

.3

.2

.1

.0

LSB

P3.3/T1CAP1

P3.2/T1CAP0

P3.1/T1CK1

P3.0/T1CK0

.7 .6 bit/P3.3/T1CAP1

00

01

1x

Input mode(T1CAP1)

Input mode, pull-up(T1CAP1)

Push-pull output

.5 .4 bit/P3.2/T1CAP0

00

01

1x

Input mode(T1CAP0)

Input mode, pull-up(T1CAP0)

Push-pull output

.3 .2 bit/P3.1/T1CK1

00

01

1x

Input mode(T1CK1)

Input mode, pull-up(T1CK1)

Push-pull output

.1 .0 bit/P3.0/T1CK0

00

01

1x

Input mode(T1CK0)

Input mode, pull-up(T1CK0)

Push-pull output


9-13


PORT 4


— External interrupt inputs for INT0-INT7



Port 4 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0:

P4CONL (low byte, F7H) and P4CONH (high byte, F6H).

When you select output mode, a push-pull circuit is configured. In input mode, three different selections are available:

— Schmitt trigger input with interrupt generation on falling signal edges.

— Schmitt trigger input with interrupt generation on rising signal edges.

— Schmitt trigger input with pull-up resistor and interrupt generation on falling signal edges.

Port 4 Interrupt Enable and Pending Registers (P4INT, P4INTPND)

To process external interrupts at the port 4 pins, two additional control registers are provided: the port 4 interrupt enable register P4INT (FAH, set 1, bank 0) and the port 4 interrupt pending register P4INTPND (FBH, set 1, bank

0).

The port 4 interrupt pending register P4INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P4INTPND register at regular intervals.

When the interrupt enable bit of any port 4 pin is “1”, a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P4INTPND bit is then automatically set to “1” and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must clear the pending condition by writing a “0” to the corresponding P4INTPND bit.

9-14


MSB .7



.6

.5

.4

.3

.2

.1

.0

LSB

P4.7/

INT7

P4.6/

INT6

P4.5/

INT5

P4.4/

INT4

.7 .6 bit/P4.7INT7

00

01

10

11

Input mode; (falling edge interrupt)

Input mode; (rising edge interrupt)

Input mode, pull-up; (falling edge interrupt)

Push-pull output

.5 .4 bit/P4.6/INT6

00

01

10

11




Push-pull output

.3 .2 bit/P4.5/INT5

00

01

10

11




Push-pull output

.1 .0 bit/P4.4/INT4

00

01

10

11




Push-pull output


9-15


MSB .7



.6

.5

.4

.3

.2

.1

.0

LSB

P4.3/

INT3

P4.2/

INT2

P4.1/

INT1

P4.0/

INT0

.7 .6 bit/P4.3/INT3

00

01

10

11




Push-pull output

.5 .4 bit/P4.2/INT2

00

01

10

11




Push-pull output

.3 .2 bit/P4.1/INT1

00

01

10

11




Push-pull output

.1 .0 bit/P4.0/INT0

00

01

10

11




Push-pull output


9-16


MSB .7

Port 4 Interrupt Control Register (P4INT)

FAH, Set 1, Bank 0, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

P4INT Bit Configuration Settings:

0

1

Interrupt disable

Interrupt enable

Figure 9-10. Port 4 Interrupt Control Register (P4INT)

MSB .7

Port 4 Interrupt Pending Register (P4INTPND)

FBH, Set 1, Bank 0, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0

P4INTPND Bit Configuration Settings:

0

1

Interrupt request is not pending, pending bit clear when write 0

Interrupt request is pending

Figure 9-11. Port 4 Interrupt Pending Register (P4INTPND)

9-17


PORT 5

Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E5H in set 1, bank 0. P5.7–P5.4 can serve as inputs, outputs (push pull or open-drain). P5.3–P5.0 can serve as inputs, outputs (push pull) or you can configure the following alternative functions:

— Low-byte pins (P5.3-P5.0): RxD0, TxD0, RxD1, TxD1


Port 5 has two 8-bit control registers: P5CONH for P5.4–P5.7 and P5CONL for P5.0–P5.3. A reset clears the

P5CONH and P5CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull, open-drain) and enable the alternative functions.


9-18




MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

P5.4

P5.6

P5.7

.7 .6 bit : P5.7

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Open-drain mode

.5 .4 bit : P5.6

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Open-drain mode

P5.5

.3 .2 bit : P5.5

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Open-drain mode

.1 .0 bit : P5.4

00

Input mode

01

Input mode, pull-up

10

Push-pull output

11

Open-drain mode


9-19


MSB .7



.6

.5

.4

.3

.2

.1

.0

LSB

P5.1/

RxD1

P5.3/

RxD0

P5.2/

TxD0

.7 .6 bit/P5.3/RxD0

00

01

10

11

Input mode(RxD0 input)

Input mode, pull-up(RxD0 input)

Push-pull output

Alternative output mode(RxD0 output)

P5.0/

TxD1

.5 .4 bit/P5.2/TxD0

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative output mode(TxD0 output)

.3 .2 bit/P5.1/RxD1

00

01

10

11

Input mode(RxD1 input)

Input mode, pull-up(RxD1 input)

Push-pull output

Alternative output mode(RxD1 output)

.1 .0 bit/P5.0/TxD1

00

01

10

11

Input mode

Input mode, pull-up

Push-pull output

Alternative output mode(TxD1 output)


9-20


PORT 6

Port 6 is an 8-bit I/O port that you can use two ways:

— Alternative function: ADC0-ADC7 input

Port 6 pins are accessed directly by writing the port6 data register, P6 at location E6H in set 1, bank 0.

MSB .7


0FH, Page 8, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not

Used

P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0

.6 bit / P6.6 /ADC14

0

1

Open-Drain output

Alternative Function ADC14

.5 bit / P6.5 /ADC13

0

1

Open-Drain output


.4 bit / P6.4 /ADC12

0

1

Open-Drain output


.3 bit / P6.3 /ADC11

0

1

Open-Drain output


.2 bit / P6.2 /ADC10

0

1

Open-Drain output


.1 bit / P6.1 /ADC9

0 Open-Drain output

1 Alternative Function ADC9

.0 bit / P6.0 /ADC8

0 Open-Drain output

1 Alternative Function ADC8


9-21


PORT 7

Port 7 is an 8-bit Input port that you can use two ways:

— Alternative function: ADC0-ADC7 input

Port 7 is accessed directly by reading the port 7 data register, P7 at location E7H in set 1, bank 0.



P7CON (F5H).

When programming the port, please remember that any alternative peripheral I function you configure using the port 7 control registers must also be enabled in the associated peripheral module.

9-22


MSB .7



.6

.5

.4

.3

.2

.1

.0

LSB

P7.7/ P7.6/ P7.5/ P7.4/ P7.3/ P7.2/ P7.1/ P7.0/

ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0

.7 bit : P7.7/ADC7

0

1

Input mode

ADC input mode

.6 bit : P7.6/ADC6

0

1

Input mode

ADC input mode

.5 bit : P7.5/ADC5

0

1

Input mode

ADC input mode

.4 bit : P7.4/ADC4

0

1

Input mode

ADC input mode

.3 bit : P7.3/ADC3

0

1

Input mode

ADC input mode

.2 bit : P7.2/ADC2

0

1

Input mode

ADC input mode

.1 bit : P7.1/ADC1

0

1

Input mode

ADC input mode

.0 bit : P7.0/ADC0

0 Input mode

1 ADC input mode


9-23


PORT 8

Port 8 is an 6-bit I/O Port that you can use three ways:

— Alternative function: SCK1, SI1, SO1

— External interrupt inputs for INT8-INT9



Port 8 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0:

P8CONL (low byte, EEH) and P8CONH (high byte, EDH).

When you select output mode, a push-pull circuit is configured. In input mode, three different selections are available:

— Schmitt trigger input with interrupt generation on falling signal edges.

— Schmitt trigger input with interrupt generation on rising signal edges.

— Schmitt trigger input with pull-up resistor and interrupt generation on falling signal edges.

Port 8 Interrupt Enable and Pending Registers (P8INTPND)

To process external interrupts at the port 8 pins, one additional control register is provided: the port 8 interrupt enable register P8INTPND (EFH, set 1, bank 0).

The port 8 interrupt pending register P8INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P8INTPND register at regular intervals.

When the interrupt enable bit of any port 8 pin is “1”, a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P8INTPND bit is then automatically set to “1” and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a “0” to the corresponding P8INTPND bit.

9-24



EDH, Set 1, Bank 0, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

P8.5/

INT9

P8.4/

INT8

.3 .2 bit : P8.5/INT9

00

01

10

11




Push-pull output

.1 .0 bit : P8.4/INT8

00

01



10 Input mode, pull-up; (falling edge interrupt)

11 Push-pull output


9-25


MSB .7


EEH, Set 1, Bank 0, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P8.3

P8.2/SCK1

.7 .6 bit/ P8.3

00 Input mode


10 Push-pull output

11 Not Used

P8.1/SI1

.5 .6 bit / P8.2 / SCK1

00 Input mode (SCK1 Input)

01 Input mode, pull-up (SCK1 Input)

10 Push-pull output

11 Alternative Function (SCK1 output)

.3 .2 bit / P8.1 / SI1

00 Input mode (SI1)

01 Input mode, pull-up (SI1)

10 Push-pull output

11 Not Used

.1 .0 bit / P8.0 / SO1

00 Input mode


10 Push-pull output

11 Alternative Function (SO1)

P8.0/SO1


9-26


MSB .7

Port 8 Interrupt Pending Register (P8INTPND)

EFH, Set 1, Bank 0, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

P8.5/ P8.4/

PND9 PND8

Not used

P8.5/

INT9

P8.4/

INT8

.5 bit : P8.5/PND9



.4 bit : P8.4/PND8



.1 bit : P8.5/INT9

0

1

Disable interrupt

Enable interrupt

.0 bit : P8.4/INT8

0 Disable interrupt

1 Enable interrupt

Figure 9-18. Port 8 Interrupt Pending Register (P8INTPND)

9-27

S3C84MB/F84MB_UM_REV1.00 BASIC TIMER

10

BASIC TIMER

OVERVIEW

BASIC TIMER (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.

— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (f

XX

divided by 4096, 1024 or 128) with multiplexer

— 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only)

— Basic timer control register, BTCON (set 1, D3H, read/write)

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using register addressing mode.

A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of f

XX

/4096. To disable the watchdog function, write the signature code '1010B' to the basic timer register control bits BTCON.7–BTCON.4.

The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0.

10-1

BASIC TIMER S3C84MB/F84MB_UM_REV1.00

MSB .7

Basic Timer Control Register (BTCON)

D3H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Watchdog timer enable bit:

1010B = Disable watchdog function

Other value = Enable watchdog function

Divider clear bit:

0 = No effect

1 = Clear divider

Basic timer counter clear bit:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bit:

00 = fxx/4096

01 = fxx/1024

10 = fxx/128

11 = fxx/16 (Not used)

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

S3C84MB/F84MB_UM_REV1.00 BASIC TIMER

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to

"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.

The MCU is reset whenever a basic timer counter overflow occurs, During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring, To do this, the

BTCNT value must be cleared (by writing a “1” to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when

Stop mode has been released by an external interrupt.

In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of f

XX

/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).

When BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when stop mode is released:

1. During stop mode, a power-on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts.

2. If a power-on reset occurred, the basic timer counter will increase at the rate of f

XX

/4096. If an interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows.

4. When a BTCNT.4 overflow occurs, normal CPU operation resumes.

10-3

BASIC TIMER S3C84MB/F84MB_UM_REV1.00

fxx

Bits 3, 2 fxx/4096

DIV fxx/1024 fxx/128

R

MUX

Bit 0

Bit 1

Clear

RESET or STOP

Basic Timer Control Register

(Write '1010xxxxB' to disable)

Data Bus

8-Bit Up Counter

(BTCNT, Read-Only)

OVF

Start the CPU

(note)

NOTE:

During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).

RESET

Figure 10-2. Basic Timer Block Diagram

10-4

S3C84MB/F84MB_UM_REV1.00 8-BIT TIMER A/B/C(0/1)

11

8-BIT TIMER A/B/C(0/1)

8-BIT TIMER A

OVERVIEW

The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, you can select one of them using the appropriate TACON setting:

— Interval timer mode (Toggle output at TAOUT pin)

— Capture input mode with a rising or falling edge trigger at the TACAP pin

— PWM mode (TAPWM); PWM output shares its output port with TAOUT pin

Timer A has the following functional components:


XX

divided by 1024, 256, or 64) with multiplexer

— External clock input pin (TACK)

— 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA)

— I/O pins for capture input (TACAP) or PWM or match output (TAPWM, TAOUT)

— Timer A overflow interrupt (IRQ0, vector BAH) and match/capture interrupt (IRQ0, vector B8H) generation

— Timer A control register, TACON (set 1, bank0, EAH, read/write)

11-1

8-BIT TIMER A/B/C(0/1) S3C84MB/F84MB_UM_REV1.00

FUNCTION DESCRIPTION

Timer A Interrupts (IRQ0, Vectors B8H and BAH)

The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector BAH. TAINT also belongs to interrupt level IRQ0, but is assigned the separate vector address, B8H.

A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A timer A match/capture interrupt, TAINT pending condition is also cleared by hardware when it has been serviced.

Interval Timer Function

The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt level IRQ0, and is assigned the separate vector address, B8H.

When timer A match interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register, TADATA. The match signal generates a timer A match interrupt (TAINT, vector B8H) and clears the counter.

If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches

10H. At this point, the TA interrupt request is generated, the counter value is reset, and counting resumes.

Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

TAPWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at FFH, and then continues incrementing from 00H.

Although timer A overflow interrupt is occurred, this interrupt is not typically used in PWM-type applications.

Instead, the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal

to (

≤ ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t

CLK

• 256 .

Capture Mode

In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the TA data register. You can select rising or falling edges to trigger this operation.

Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by setting the value of the timer A capture input selection bit in the port 2 control register, P2CONH, (set 1, bank 0,

F2H). When P2CONH.5.4 is 00, the TACAP input or normal input is selected. When P2CONH.5.4 is set to 10, normal output is selected.

Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into the TA data register.

By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.

11-2


TIMER A CONTROL REGISTER (TACON)

You use the timer A control register, TACON, to

— Select the timer A operating mode (interval timer, capture mode, or PWM mode)

— Select the timer A input clock frequency

— Clear the timer A counter, TACNT

— Enable the timer A overflow interrupt or timer A match/capture interrupt

— Clear timer A match/capture interrupt pending conditions

TACON is located in set 1, Bank 0 at address EAH, and is read/write addressable using Register addressing mode.

A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of f

XX

/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3.

The timer A overflow interrupt (TAOVF) is interrupt level IRQ0 and has the vector address BAH. When a timer A overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer A match/capture interrupt (IRQ0, vector B8H), you must write TACON.1 to "1". To generate the exact time interval, you should write “1” to TACON.3 and “0” to TINTPND.0, which cleared counter and interrupt pending bit .

MSB .7

Timer A Control Register (TACON)

EAH, Set 1, Bank 0, R/W, Reset: 00H

.6

.5

.4

.3

.2

.1

.0

LSB

Timer A input clock selection bit:

00 = fxx/1024

01 = fxx/256

10 = fxx/64

11 = External clock (TACK)

Timer A operating mode selection bit:

00 = Interval mode (TAOUT mode)

01 = Capture mode (capture on rising edge,

counter running, OVF can occur)

10 = Capture mode (capture on falling edge,

counter running, OVF can occur)

11 = PWM mode (OVF interrupt and match

interrupt can occur)

Not used

Timer A match/capture interrupt enable bit:

0 = Disable interrupt

1 = Enable interrrupt

Timer A overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrrupt

Timer A counter clear bit:

0 = No effect

1 = Clear the timer A counter (when write)

NOTE: When the counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically.

Pending bit of overflow and match/capture intterupt are located in

TINTPND (E9, bank0) register.

Figure 11-1. Timer A Control Register (TACON)

11-3


BLOCK DIAGRAM


TACAP

M

U

X

TACON.7-.6

fxx/1024 fxx/256 fxx/64

TACK

M

U

X

Data Bus

8

8-bit Up-Counter

(Read Only)

Overflow

TACON.2

Pending

TINTPND.1

Clear

TACON.3

TAOVF

8-bit Comparator

Timer A Buffer Reg

Match

M

U

X

TACON.1

TAINT

Pending

TINTPND.0

TAOUT(TAPWM)

TACON.5.4

Timer A Data Register

(Read/Write)

8

Data Bus

NOTES:

1. When PWM mode, match signal cannot clear counter.

2. Pending bit is located at TINTPND register.

TACON.5.4

PG output signal

Figure 11-2. Timer A Functional Block Diagram

11-4


8-BIT TIMER B

OVERVIEW

The S3C84MB/F84MB micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Pending bit of timer B is cleared automatically by hardware.

Timer B has two functions:

— As a normal interval timer, generating a timer B interrupt at programmed time intervals.

— To generate a programmable carrier pulse for a remote control signal at P2.4.

BLOCK DIAGRAM

fxx/1 fxx/2 fxx/4 fxx/8

TBCON.6-.7

M

U

X

TBCON.1

TBCON.2

CLK

PG output signal

TBCON.0

8-Bit

Down Counter

TB Underflow

(TBUF)

FF

TBPWM(P2.4)

Repeat

Control

MUX

TBCON.4-.5

Timer B Data

Low Byte Register

8

Data Bus

Timer B Data

High Byte Register

8

Data Bus

TBCON.3

IRQ1

(TBINT)

NOTE:

In case of setting TBCON.5-.4 at '10', the value of the TBDATAL register is loaded into the 8-bit counter when the operation of the timer B starts. And then if a underflow occurs in the counter, the value of the TBDATAH register is loaded with the value of the 8-bit counter.

However, if the next borrow occurs, the value of the TBDATAL register is loaded with the value of the 8-bit counter. To output TBPWM as carrier wave, you have to set P2CONH.1-.0 as "11".

Figure 11-3. Timer B Functional Block Diagram

11-5


TIMER B CONTROL REGISTER (TBCON)

MSB .7

Timer B Control Register (TBCON)

D0H, Set 1, Bank 0, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Timer B input clock selection bit:

00 = fxx/1

01 = fxx/2

10 = fxx/4

11 = fxx/8

Timer B interrupt time selection bit:

00 = Elapsed time for low data value

01 = Elapsed time for high data value

10 = Elapsed time for low and high data value

11 = Invaild setting

Timer B output flip-flop

control bit:

0 = T-FF is low

1 = T-FF is high

Timer B mode selection bit:

0 = One-shot mode

1 = Repeating mode

Timer B start/stop bit:

0 = Stop timer B

1 = Start timer B

Timer B interrupt enable bit:


1 = Enable interrupt

Figure 11-4. Timer B Control Register (TBCON)

MSB .7

Timer B Data High-Byte Register (TBDATAH)


.6

.5

.4

.3

.2

.1

.0

Reset Value: FFh

LSB

Timer B Data Low-Byte Register (TBDATAL)


MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value: FFh

Figure 11-5. Timer B Data Registers (TBDATAH, TBDATAL)

11-6


TIMER B PULSE WIDTH CALCULATIONS

t

HIGH t

LOW t

LOW

To generate the above repeated waveform consisted of low period time, t

LOW

, and high period time, t

HIGH

.

When T-FF = 0, t

LOW

= (TBDATAL + 2) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock. t

HIGH

= (TBDATAH + 2) x 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock.

When T-FF = 1, t

LOW

= (TBDATAH + 2) x 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock. t

HIGH

= (TBDATAL + 2) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.

To make t

LOW

= 24 us and t

HIGH

= 15 us. f

OSC

= 4 MHz, fx = 4 MHz/4 = 1 MHz

When T-FF = 0, t

LOW

= 24 us = (TBDATAL + 2) /fx = (TBDATAL + 2) x 1us, TBDATAL = 22. t

HIGH

= 15 us = (TBDATAH + 2) /fx = (TBDATAH + 2) x 1us, TBDATAH = 13.

When T-FF = 1, t

HIGH

= 15 us = (TBDATAL + 2) /fx = (TBDATAL + 2) x 1us, TBDATAL = 13. t

LOW

= 24 us = (TBDATAH + 2) /fx = (TBDATAH + 2) x 1us, TBDATAH = 22.

11-7


0H

Timer B Clock

T-FF = '0'

TBDATAL = 01-FFH

TBDATAH = 00H

T-FF = '0'

TBDATAL = 00H

TBDATAH = 01-FFH

T-FF = '0'

TBDATAL = 00H

TBDATAH = 00H

T-FF = '1'

TBDATAL = 00H

TBDATAH = 00H

0H

Timer B Clock

T-FF = '1'

TBDATAL = DEH

TBDATAH = 1EH

T-FF = '0'

TBDATAL = DEH

TBDATAH = 1EH

T-FF = '1'

TBDATAL = 7EH

TBDATAH = 7EH

T-FF = '0'

TBDATAL = 7EH

TBDATAH = 7EH

High

Low

Low

High

E0H

E0H

80H

80H

20H

80H

80H

20H

100H 200H

Figure 11-6. Timer B Output Flip-Flop Waveforms in Repeat Mode

11-8


)

PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P2.4

This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and

TBDATAH and TBDATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:

8.795

μs

17.59

μs

37.9 kHz 1/3 Duty

— Timer B is used in repeat mode

— Oscillation frequency is 4 MHz (0.25

μs)

— TBDATAL = 8.795

μs/0.25 μs = 35.18, TBDATAH = 17.59 μs/0.25 μs = 70.36

— Set P2.4 to TBPWM mode.

START DI

•

•

•

LD

LD

LD

LD

TBDATAH, #(70-2)

TBDATAL, #(35-2)

TBCON, #00100111B

P2CONH, #03H

•

•

•

; Set 17.5

μs

; Set 8.75

μs

; Clock Source

← f

XX

; Disable Timer B interrupt.

; Select repeat mode for Timer B.

; Start Timer B operation.

; Set Timer B Output flip-flop (T-FF) high.

;

; Set P2.4 to TBPWM mode.

; This command generates 38 kHz, 1/3 duty pulse signal

11-9


)

PROGRAMMING TIP — To generate a one pulse signal through P2.4

This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and

TBDATAH and TBDATAL to make a 40

μs width pulse. The program parameters are:

40

μs

— Timer B is used in one shot mode

— Oscillation frequency is 4 MHz (1 clock = 0.25

μs)

— TBDATAH = 40

μs / 0.25 μs = 160, TBDATAL = 1

— Set P2.4 to TBPWM mode

START DI

•

•

•

LD

LD

LD

LD

TBDATAH,# (160-2)

TBDATAL,# 1

TBCON,#00010001B

P2CONH, #03H

Pulse_out:

•

•

•

•

•

LD TBCON,#00010101B

; Set 40

μs

; Set any value except 00H

; Clock Source

← f

OSC

; Disable Timer B interrupt.

; Select one shot mode for Timer B.

; Stop Timer B operation.

; Set Timer B output flip-flop (T-FF) high

; Set P2.4 to TBPWM mode.

; Start Timer B operation

; to make the pulse at this point.

; After the instruction is executed, 0.75

μs is required

; before the falling edge of the pulse starts.

11-10


8-BIT TIMER C (0/1)

OVERVIEW

The 8-bit timer C (0/1) is an 8-bit general-purpose timer/counter. Timer C (0/1) has two operating modes, you can select one of them using the appropriate TCCON0, and TCCON1 setting:

— Interval timer mode (Toggle output at TCOUT0, TCOUT1 pin)

— PWM mode (TCOUT0, TCOUT1)

Timer C (0/1) has the following functional components:

— Clock frequency divider with multiplexer

— 8-bit counter, 8-bit comparator, and 8-bit reference data register (TCDATA0, TCDATA1)

— PWM or match output (TCOUT0, TCOUT1)

— Timer C (0) match/overflow interrupt (IRQ2, vector BCH) generation

— Timer C (1) match/overflow interrupt (IRQ2, vector BEH) generation

— Timer C (0) control register, TCCON0 (set 1, bank1, F2H, read/write)

— Timer C (1) control register, TCCON1 (set 1, bank1, F3H, read/write)

11-11


TIMER C (0/1) CONTROL REGISTER (TCCON0, TCCON1)


MSB

.7

Timer C Control Register

(TCCON0) F2H, Set 1, Bank 1, R/W, Reset: 00H

(TCCON1) F3H, Set 1, Bank 1, R/W, Reset: 00H

.6

.5

.4

.3

.2

.1

.0

LSB

Not Used

Timer C 3-bits prescaler bits :

000 = Non devided

001 = Devided by 2

010 = Devided by 3

011 = Devided by 4

100 = Devided by 5

101 = Devided by 6

110 = Devided by 7

111 = Devided by 8

Timer C pending bit :

0 = No interrupt pending

1 = interrupt pending

Timer C interrupt enable bit :



Timer C mode selection bit :

0 = fxx/1 & PWM mode

1 = fxx/64 & interval mode

Timer C counter clear bit :

0 = No effect

1 = Clear the timer A counter (when write)

NOTE:

When the counter clear bit (.3) is set, the 8-bit counter is cleared and it also is cleared automatically .

Figure 11-7. Timer C (0/1) Control Register (TCCON0, TCCON1)

11-12


BLOCK DIAGRAM

TCCON.2

TCCON.6-.4

fxx/1 fxx/64

M

U

X

3-bit

Prescaler

Data Bus

8

8-bit Up-Counter

(Read Only)

Overflow

Clear

TCCON.1

Pending

TCCON.0

Match

8-bit Comparator

Timer C Buffer Reg

TCINT

TCCON.3

TCCON.1

Pending

TCCON.0

TCOUT

TCINT

Timer C Data Register

(Read/Write)

8

Data Bus

NOTE: When PWM mode, match signal cannot clear counter.

Figure 11-8. Timer C (0/1) Functional Block Diagram

11-13


)

PROGRAMMING TIP — Using the Timer A


INITIAL:

LD

LD

LD

LD

SYM,#00h

IMR,#00000001b

SPH,#00000000b

BTCON,#10100011b

; Disable Global/Fast interrupt

→ SYM

; Enable IRQ0 interrupt

; Set stack area

; Disable watch-dog

LD TACON,#01001010b

EI

MAIN:

•

•

•

•

; Match interrupt enable

; 3.30 ms duration (10 MHz x’tal)

TAMC_INT:

•

•


•

•

IRET

TAOV_INT:

•


•

•

IRET

.END

11-14


)

PROGRAMMING TIP — Using the Timer B


INITIAL:

LD

LD

LD

LD

LD

SYM,#00h

IMR,#00000010b

SPH,#00000000b

BTCON,#10100011b



; Set stack area

; Disable Watch-dog

P2CONH,#00000011b ; Enable TBPWM output

LD TBCON,#11101110b

EI

MAIN:

•

•

•

•

•

•

JR MAIN

TBUN_INT:

•

•

•


•

•

•

IRET

.END

; Enable interrupt, repeating, f

Duration

XX

/8

11-15


)

PROGRAMMING TIP — Using the Timer C(0)


INITIAL:

LD

LD

LD

LD

SYM,#00h

IMR,#00000100b

SPH,#00000000b

BTCON,#10100011b



; Set stack area

; Disable Watch-dog, high speed

LD P3CONH,#00110000b ; Enable TCOUT0 output

LD TCCON0,#00001110b ; non-divide, interval, Enable interrupt

; Duration 0.825ms (10 MHz x’tal)

EI

MAIN:

•

•

•

•

•

•

JR MAIN

TCUN_INT:

•

•

•


•

•

•

IRET

.END

11-16

S3C84MB/F84MB_UM_REV1.00 16-BIT TIMER 1(0/1)

12

16-BIT TIMER 1(0/1)

OVERVIEW

The S3C84MBJ/F84MBJ has two 16-bit timer/counters. The 16-bit timer 1(0/1) is a 16-bit general-purpose timer/counter. Timer 1(0/1) has three operating modes, one of which you select using the appropriate T1CON0,

T1CON1 setting is:

— Interval timer mode (Toggle output at T1OUT0, T1OUT1 pin)

— Capture input mode with a rising or falling edge trigger at the T1CAP0, T1CAP1 pin

— PWM mode (T1PWM0, T1PWM1); PWM output shares their output port with T1OUT0, T1OUT1 pin

Timer 1(0/1) has the following functional components:


XX

divided by 1024, 256, 64, 8, or 1) with multiplexer

— External clock input pin (T1CK0, T1CK1)

— A 16-bit counter (T1CNTH0/L0, T1CNTH1/L1), 16-bit comparator, and two 16-bit reference data register

(T1DATAH0/L0, T1DATAH1/L1)

— I/O pins for capture input (T1CAP0, T1CAP1), or match output (T1OUT0, T1OUT1)

— Timer 1(0) overflow interrupt (IRQ3, vector C2H) and match/capture interrupt (IRQ3, vector C0H) generation

— Timer 1(1) overflow interrupt (IRQ3, vector C6H) and match/capture interrupt (IRQ3, vector C4H) generation

— Timer 1(0) control register, T1CON0 (set 1, EAH, Bank 1, read/write)

— Timer 1(1) control register, T1CON1 (set 1, EBH, Bank 1, read/write)

12-1

16-BIT TIMER 1(0/1) S3C84MB/F84MB_UM_REV1.00


Timer 1 (0/1) Interrupts (IRQ3, Vectors C6H, C4H, C2H and C0H)

The timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (T1OVF0), and the timer 1(0) match/capture interrupt (T1INT0). T1OVF0 is interrupt level IRQ3, vector C2H. T1INT0 also belongs to interrupt level IRQ3, but is assigned the separate vector address, C0H.

A timer 1(0) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.

A timer 1(0) match/capture interrupt, T1INT0 pending condition is also cleared by hardware when it has been serviced.

The timer 1(1) module can generate two interrupts, the timer 1(1) overflow interrupt (T1OVF1), and the timer 1(1) match/capture interrupt (T1INT1). T1OVF1 is interrupt level IRQ3, vector C6H. T1INT1 also belongs to interrupt level IRQ3, but is assigned the separate vector address, C4H.

A timer 1(1) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.

A timer 1(1) match/capture interrupt, T1INT1 pending condition is also cleared by hardware when it has been serviced.

Interval Mode (match)

The timer 1(0) module can generate an interrupt: the timer 1(0) match interrupt (T1INT0). T1INT0 belongs to interrupt level IRQ3, and is assigned the separate vector address, C0H.

In interval timer mode, a match signal is generated and T1OUT0 is toggled when the counter value is identical to the value written to the T1 reference data register, T1DATAH0/L0. The match signal generates a timer 1(0) match interrupt (T1INT0, vector C0H) and clears the counter.

The timer 1(1) module can generate an interrupt: the timer 1(1) match interrupt (T1INT1). T1INT1 belongs to interrupt level IRQ3, and is assigned the separate vector address, C4H.

In interval timer mode, a match signal is generated and T1OUT1 is toggled when the counter value is identical to the value written to the T1 reference data register, T1DATAH1/L1. The match signal generates a timer 1(1) match interrupt (T1INT1, vector C4H) and clears the counter.

Capture Mode

In capture mode for Timer 1(0), a signal edge that is detected at the T1CAP0 pin opens a gate and loads the current counter value into the T1 data register (T1DATAH0/L0 for rising edge, or falling edge). You can select rising or falling edges to trigger this operation.

Timer 1(0) also gives you capture input source, the signal edge at the T1CAP0 pin. You select the capture input by setting the capture input selection bit in the port 3 control register, P3CONL, (set 1 bank 0, F5H).

Both kinds of timer 1(0) interrupts (T1OVF0, T1INT0) can be used in capture mode, the timer 1(0) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(0) capture interrupt is generated whenever the counter value is loaded into the T1 data register (T1DATAH0/L0).

By reading the captured data value in T1DATAH0/L0, and assuming a specific value for the timer 1(0) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP0 pin.

In capture mode for Timer 1(1), a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the T1 data register (T1DATAH1/L1 for rising edge, or falling edge). You can select rising or falling edges to trigger this operation.

Timer 1(1) also gives you capture input source, the signal edge at the T1CAP1 pin. You select the capture input by setting the capture input selection bit in the port 3 control register, P3CONL, (set 1 bank 0, F5H).

Both kinds of timer 1(1) interrupts (T1OVF1, T1INT1) can be used in capture mode, the timer 1(1) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(1) capture interrupt is generated whenever the counter value is loaded into the T1 data register.

By reading the captured data value in T1DATAH1/L1, and assuming a specific value for the timer 1(1) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP1 pin.

12-2


PWM Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T1OUT0, T1OUT1 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0/1) data register. In PWM mode, however, the match signal does not clear the counter but can generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then continuous increasing from 0000H. Whenever an overflow is occurred, an overflow (OVF0,1) interrupt can be generated.

Although you can use the match or the overflow interrupt in the PWM mode, these interrupts are not typically used in PWM-type applications. Instead, the pulse at the T1OUT0, T1OUT1 pin is held to low level as long as the reference data value is less than or equal to(

≤) the counter value and then the pulse is held to high level for as long as the data value is greater than(

>) the counter value. One pulse width is equal to t

CLK

.

TIMER 1(0/1) CONTROL REGISTER (T1CON0, T1CON1)

You use the timer 1(0/1) control register, T1CON0, T1CON1, to

— Select the timer 1(0/1) operating mode (interval timer, capture mode, or PWM mode)

— Select the timer 1(0/1) input clock frequency

— Clear the timer 1(0/1) counter, T1CNTH0/L0, T1CNTH1/L1

— Enable the timer 1(0/1) overflow interrupt

— Enable the timer 1(0/1) match/capture interrupt

T1CON0 is located in set 1 and Bank 1 at address EAH, and is read/write addressable using Register addressing mode. T1CON1 is located in set 1 and Bank 1 at address EBH, and is read/write addressable using Register addressing mode.

A reset clears T1CON0, T1CON1 to ‘00H’. This sets timer 1(0/1) to normal interval timer mode, selects an input clock frequency of f

XX

/1024, and disables all timer 1(0/1) interrupts. To disable the counter operation, please set

T1CON(0/1).7-.5 to 111B. You can clear the timer 1(0/1) counter at any time during normal operation by writing a

“1” to T1CON(0/1).3. To generate the exact time interval, you should write “1” to T1CON(0/1).2 and clear appropriate pending bits of the TINTPND register.

To detect a match/capture or overflow interrupt pending condition when T1INT0, T1INT1 or T1OVF0, T1OVF1 is disabled, the application program should poll the pending bit TINTPND register, bank 0, E9H. When a “1” is detected, a timer 1(0/1) match/capture or overflow interrupt is pending.

When the sub-routine has been serviced, the pending condition must be cleared by software by writing a “0” to the interrupt pending bit. If interrupts (match/capture or overflow) are enabled, the pending bit is cleared automatically by hardware.

12-3

16-BIT TIMER 1(0/1) S3C84MB/F84MB_UM_REV1.00

MSB .7

.6

Timer 1 Control Register

(T1CON0) EAH, Set 1, Bank 1, R/W

(T1CON1) EBH, Set 1, Bank 1, R/W

.5

.4

.3

.2

.1

.0

LSB

Timer 1 clock source selection bit:

000 = fxx/1024

001 = fxx

010 = fxx/256

011 = External clock(T1CK) falling edge

100 = fxx/64

101 = External clock(T1CK) rising edge

110 = fxx/8

111 = Counter stop

Timer 1 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrrupt

Timer 1 match/capture interrupt enable bit:



Timer 1 counter clear bit:

0 = No effect

1 = Clear counter ( Auto-clear bit)

Timer 1 operating mode selection bit:

00 = Interval mode

01 = Capture mode (capture on rising edge, OVF can occur)

10 = Capture mode (capture on falling edge, OVF can occur)

11 = PWM mode (OVF and T1INT can occur)

NOTE:

Interrupt pending bits are located in TINTPND register.

Figure 12-1. Timer 1(0/1) Control Register (T1CON0, T1CON1)

12-4


MSB .7

.6

Timer A ,1 Pending Register ( TINTPND )

E9H, Set 1, Bank 0, R/W

.5

.4

.3

.2

.1

.0

LSB

Not used

Timer A match /capture interrupt pending bit:


1 = Interrrupt pending

Timer 1(1) overflow interrupt pendig bit:


1 = Interrupt pending

Timer 1(1) match/capture interrupt pending bit:



Timer A overflow interrupt pending bit:



Timer 1(0) match/capture interrupt pending bit:



Timer 1(0) overflow interrupt pending bit :



NOTE: "0" also means "Clear pending bit when write"

Figure 12-2. Timer A and Timer 1(0/1) Pending Register (TINTPND)

12-5

16-BIT TIMER 1(0/1)

BLOCK DIAGRAM


T1CON.7-.5

T1CK fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1

M

U

X

V

SS

T1CAP

M

U

X

Data Bus

8

16-bit Up-Counter

(Read Only)

Overflow

Clear

T1CON.0

Pending

TINTPND

T1CON.2

T1OVF

16-bit Comparator

Match

M

U

X

T1CON.1

Pending

TINTPND

16-bit Timer Buffer

T1INT

T1OUT

T1PWM

T1CON.4.3

T1CON.4.3

16-bit Timer Data Register

(T1DATAH/L)

8

Data Bus

NOTES:

1. When PWM mode, match signal cannot clear counter.

2. Pending bit is located at TINTPND register.

PG output signal

Figure 12-3. Timer 1(0/1) Functional Block Diagram

12-6


)

PROGRAMMING TIP — Using the Timer 1(0)

16-BIT TIMER 1(0/1)

INITIAL:

LD

LD

LD

LD

SYM,#00h

IMR,#00001000b

SPH,#00000000b

BTCON,#10100011b

SB1



; Set stack area

; Disable Watch-dog

SB0

EI

MAIN:

•

•

•

•

•

•

; Duration 6.17ms (10 MHz x’tal)

T1MC_INT:

•

•

•


•

•

•

IRET

.END

12-7

S3C84MB/F84MB_UM_REV1.00 SERIAL I/O PORT

13

SERIAL I/O PORT

OVERVIEW

Serial I/O module, SIO can interface with various types of external devices that require serial data transfer.

SIO has the following functional components:

— SIO data receive/transmit interrupt (IRQ4, vector CAH, ACH) generation

— 8-bit control register, SIOCON(set 1, bank 1, E1H, read/write), SIOCON1(Page 8, 00H, read/write)

— Clock selection logic

— 8-bit data buffer, SIODATA, SIODATA1

— 8-bit prescaler SIOPS (set 1, bank 1, F4H, read/write), SIOPS1 (Page 8, 01H, read/write)

— 3-bit serial clock counter

— Serial data I/O pins (SO0, SI0, SO1, SI1)

— External clock input/output pin (SCK0, SCK1)

The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.

PROGRAMMING PROCEDURE

To program the SIO modules, follow these basic steps(SIO0):

1. Configure P2.1, P2.0 and P2.2 to alternative function (SI0, SO0, SCK0) for interfacing SIO module by setting the P2CONL register to appropriately value.

2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter.

3. For interrupt generation, set the serial I/O interrupt enable bit, SIOCON.1 to "1".

4. To transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, then the shift operation starts.

5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an

SIO interrupt request is generated.

13-1

SERIAL I/O PORT S3C84MB/F84MB_UM_REV1.00

SIO CONTROL REGISTER (SIOCON)

The control register for the serial I/O interface module, SIOCON, is located in set 1, bank 1 at address E1H(SIO0) and Page 8 at address 00H(SIO1). It has the control settings for SIO module.

— Clock source selection (internal or external) for shift clock

— Interrupt enable

— Edge selection for shift operation

— Clear 3-bit counter and start shift operation

— Shift operation (transmit) enable

— Mode selection (transmit/receive or receive-only)

— Data direction selection (MSB first or LSB first)

A reset clears the SIOCON value to '00H'. This configures the corresponding module with an internal clock source, P.S clock at the SCK, selects receive-only operating mode, the data shift operation and the interrupt are disabled, and the data direction is selected to MSB-first.

So, if you want to use SIO module, you must write appropriate value to SIOCON.

MSB

.7

Serial I/O Module Control Registers (SIOCON)

E1H, Set 1, Bank 1 00H Page 8, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

SIO Shift clock selection bit:

0 = Internal clock (P.S clock)

1 = External Clock (SCK)

Data direction control bit:

0 = MSB-first mode

1 = LSB-first mode

SIO interrupt pending bit:


0 = Clear pending condition

(when write)

1 = Interrupt is pending

SIO interrupt enable bit:

0 = Disable SIO interrupt

1 = Enable SIO interrupt

SIO mode selection bit:

0 = Receive-only mode

1 = Transmit/receive mode

SIO shift operation enable bit:

0 = Disable shifter and clock counter

1 = Enable shifter and clock counter

Shift clock edge selection bit:

0 = Tx at falling edges, Rx at rising edges

1 = Tx at rising edges, Rx at falling edges

SIO counter clear and shift start bit:

0 = No action

1 = Clear 3-bit counter and start shifting

Figure 13-1. SIO Module Control Register (SIOCON)

13-2


SIO PRESCALER REGISTER (SIOPS, SIOPS1)

The control register for the serial I/O interface module, is located in set 1, bank 1, at address F4H(SIOPS) and

Page 8, at address 01H(SIOPS1).

The value stored in the SIO prescaler registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows:


XX

)/[(SIOPS value + 1) x 2] or SCK input clock

MSB

.7

SIO Pre - Scaler Register ( SIOPS )

F4 H( Set 1, Bank 1 ), 01H ( Page 8) R/W

.6

.5

.4

.3

.2

.1

.0

LSB

SIOPS Data Value

Baud rate = Input clock (fxx) / [(SIOPS + 1) x 2] or SCLK input clock

Figure 13-2. SIO Prescaler Register (SIOPS)

BLOCK DIAGRAM

SIOCON.7

(Shift Clock

Source Select)

SCK(P2.2) fxx

SIOPS

8-bit P.S.

1/2

M

U

X

Prescaled Value = 1/(SIOPS +1)

CLK

3-Bit Counter

Clear

SIOCON.0

Pending

SIO INT

IRQ4

SIOCON.3

SIOCON.1

(Interrupt Enable)

SIOCON.4

(Shift Clock

Edge Select)

CLK

SIOCON.2

(Shift Enable)

SIOCON.5

(Mode Select)

8-Bit SIO Shift Buffer

(SIODATA)

SO (P2.0)

SIOCON.6

(LSB/MSB First Mode Select)

8

SI (P2.1)

Data BUS

Figure 13-3. SIO Functional Block Diagram

13-3

SERIAL I/O PORT

SERIAL I/O TIMING DIAGRAMS


Shift

Clock

SI

(Data Input)

SO

(Data Output)

IRQ4

D7 D6

D7 D6

D5

D5

D4

D4

D3

D3

D2

D2

D1

D1

D0

D0

Transmit

Complete

SET SIOCON.3

Figure 13-4. SIO Timing in Transmit/Receive Mode (Tx at falling edge, SIOCON.4=0)

Shift

Clock

SI

(Data Input)

SO

(Data Output)

IRQ4

D7 D6

D7 D6

D5

D5

D4

D4

D3

D3

D2 D1

D2 D1

D0

D0

Transmit

Complete

SET SIOCON.3

Figure 13-5. SIO Timing in Transmit/Receive Mode (Tx at rising edge, SIOCON.4=1)

13-4


Shift

Clock

SI D7 D6 D5 D4

High Impedance

D3 D2 D1 D0

SO

IRQ4

Transmit

Complete

SET SIOCON.3

Figure 13-6 .

SIO Timing in Receive-Only Mode (Rising edge start)

)

PROGRAMMING TIP — Use Internal Clock to Transmit and Receive Serial Data

1. The method that uses interrupt is used.

•

•

DI

LD P2CONL, #03H

; Disable All interrupts

; P2.2–P2.0 are selected to alternative function for

; SI, SO, SCK, respectively

LD IMR, #00010000b ; Enable IRQ4 Interrupt

SB1

LD

LD

SIODATA, TDATA

SIOPS, #90H

LD

SB0

SIOCON, #2EH

; Load data to SIO buffer

; Baud rate = input clock(fxx)/[(144 + 1) x 2]

; Internal clock, MSB first, transmit/receive mode

; Select Tx falling edges to start shift operation

; Clear 3-bit counter and start shifting

; Enable shifter and clock counter

; Enable SIO interrupt and clear pending

EI

•

•

•

SIOINT PUSH RP0 ;

;

SB1

LD R0,SIODATA ; Load received data to general register

AND SIOCON,#11111110b ; Clear interrupt pending bit

IRET

13-5

SERIAL I/O PORT S3C84MB/F84MB_UM_REV1.00

)

PROGRAMMING TIP — Use Internal Clock to Transfer and Receive Serial Data (Continued)

2. The method that uses software pending check is used.

•

•

•

DI

SB1

LD SIODATA, TDATA

LD

LD

SIOPS, #90H

SIOCON, #2CH

EI

SIOtest: LD

BTJRF

R6,SIOCON

SIOtest,R6.0

NOP

AND SIOCON,#0FEH

; Disable All interrupts

; Load data to SIO buffer

; Baud rate = input clock(f

XX

)/[(144 + 1)

× 2]

; Internal clock, MSB first, transmit/receive mode

; Select falling edges to start shift operation

; clear 3-bit counter and start shifting

; Disable SIO interrupt and pending clear

; To check whether transmit and receive is finished

; Check pending bit

; Pending clear by software

•

•

•

SB0

•

•

•

13-6

S3C84MB/F84MB_UM_REV1.00 UART(0/1/2)

14

UART(0/1/2)

OVERVIEW

The UART block has a full-duplex serial port with programmable operating modes: There is one synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes:

— Serial I/O with baud rate of fxx/(16

× (BRDATA+1))

— 8-bit UART mode; variable baud rate

— 9-bit UART mode; fxx/16

— 9-bit UART mode, variable baud rate

UART receive and transmit buffers are both accessed via the data register, UDATA0, is set 1, bank 1 at address

E2H, UDATA1, is set 1, bank 1 at address FAH, UDATA2 is Page 8 at address 05H. Writing to the UART data register loads the transmit buffer; reading the UART data register accesses a physically separate receive buffer.

When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously received byte has been read from the receive register. However, if the first byte has not been read by the time the next byte has been completely received, the first data byte will be lost.

In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA0,

UDATA1, UDATA2 register as its destination address. In mode 0, serial data reception starts when the receive interrupt pending bit (UARTPND.1, UARTPND.3, UARTPND.5) is "0" and the receive enable bit (UARTCON0.4,

UARTCON1.4, UARTCON2.4) is "1". In mode 1, 2, and 3, reception starts whenever an incoming start bit ("0") is received and the receive enable bit (UARTCON0.4, UARTCON1.4, UARTCON2.4) is set to "1".

PROGRAMMING PROCEDURE

To program the UART0 modules, follow these basic steps:

1. Configure P5.3 and P5.2 to alternative function RxD0, TxD0 for UART0 module by setting the P5CONL register to appropriatly value.

2. Load an 8-bit value to the UARTCON0 control register to properly configure the UART0 I/O module.

3. For interrupt generation, set the UART0 interrupt enable bit (UARTCON0.1 or UARTCON0.0) to "1".

4. When you transmit data to the UART0 buffer, writing data to UDATA0, the shift operation starts.

5. When the shift operation (transmit/receive) is completed, UART0 pending bit (UARTPND.1 or UARTPND.0) is set to "1" and an UART0 interrupt request is generated.

14-1

UART CONTROL REGISTER (UARTCON0, UARTCON1, UARTCON2)

The control register for the UART is called UARTCON0 in set 1, bank 1 at address E3H, UARTCON1 in set 1, bank 1 at address FBH, UARTCON2 in Page8 at address 03H. It has the following control functions:

— Operating mode and baud rate selection

— Multiprocessor communication and interrupt control

— Serial receive enable/disable control

— 9th data bit location for transmit and receive operations (modes 2 and 3 only)

— UART transmit and receive interrupt control

A reset clears the UARTCON0, UARTCON1, UARTCON2 value to "00H". So, if you want to use UART0, UART1 or UART2 module, you must write appropriate value to UARTCON0, UARTCON1, UARTCON2.

MSB

UART Control Register

(UARTCON0) E3H, Set 1, Bank 1, R/W

(UARTCON1) FBH , Set 1, Bank 1, R/W

(UARTCON2) 03H, Page 8, R/W

MS1 MS0 MCE RE TB8 RB8 RIE TIE

LSB

See table below

Transmit interrupt enable bit :

0 = Disable, 1 = Enable

Multiprocessor communication enable bit (for modes 2 only):

0 = Disable , 1 = Enable

(1)

Received interrupt enable bit :


Serial data receive enable bit :


If PENn = 0:

Location of the 9th data bit to be transmitted in UART mode 2 ("0" or "1") else parity bit for Tx data .

0:Even 1:Odd

If PENn = 0:

Location of the 9th data bit that was received in UART mode 2 ("0" or "1") else parity bit for Rx data .

0:Even 1:Odd

Operating mode and baud rate selection bits

MS1 MS0 Mode Description

(2)

Baud Rate

0 0 0 Shift Register fXX /(16xBRDATA +1)

0 1 1 8 - bit UART fXX /(16xBRDATA+1)

1 0 2 8 - bit UART fXX /16

NOTES:

1 1 3 9 - bit UART fXX /(16xBRDATA+1)

1. In mode 2 or 3, if the UARTCON.5 bit is set to "1" then the receive interrupt will not be activated if the received 9 th data bit is "0". In mode 1, if UARTCON.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received .

2. The descriptions for 8 -bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.

3. Parity enable bits, PEN, is located in the UARTPRT register at address 06H Page 8.

4. Parity enable and parity error check can be available in 9-bit UART mode (Mode 2 and 3) only.

Figure 14-1. UART Control Register (UARTCON0, UARTCON1)

14-2


UART INTERRUPT PENDING REGISTER (UARTPND)

The UART interrupt pending register, UARTPND is located in set 1, bank 1 at address E5H, it contains the

UART0, 1, 2 data transmit interrupt pending bit and the receive interrupt pending bit.

In mode 0, the receive interrupt pending flag UARTPND.1, UARTPND.3, UARTPND.5 bit is set to "1" when the

8th receive data bit has been shifted. In mode 1, 2 or 3, the UARTPND.1, UARTPND.3, UARTPND.5 bit is set to

"1" at the halfway point of the stop bit's shift time. When the CPU has acknowledged the receive interrupt pending condition, the UARTPND.1, UARTPND.3, UARTPND.5 flag must then be cleared by software in the interrupt service routine.

In mode 0, the transmit interrupt pending flag UARTPND.0, UARTPND.2, UARTPND.4 is set to "1" when the 8th transmit data bit has been shifted. In mode 1, 2 or 3, the UARTPND.0, UARTPND.2, UARTPND.4 bit is set at the start of the stop bit. When the CPU has acknowledged the transmit interrupt pending condition, the UARTPND.0,

UARTPND.2, UARTPND.4 flag must then be cleared by software in the interrupt service routine.

MSB

–

UART Pending Register (UARTPND)

E5H, Set 1, Bank 1, R/W

– RIP2 TIP2 RIP1 TIP1 RIP0 TIP0

LSB

Not used

UART2 receive interrupt pending flag:

0 = Not pending

0 = Clear pending bit (when write)


UART2 transmit interrupt pending flag:

0 = Not pending




0 = Not pending




0 = Not pending




0 = Not pending




0 = Not pending



NOTES: 1. In order to clear a data transmit or receive interrupt pending

flag, you must write a "0" to the appropriate pending bit.

2. To avoid errors, we recommend using load instruction

(except for LDB), when manipulating UARTPND values.

Figure 14-2. UART Interrupt Pending Register (UARTPND)

14-3

UART PARITY CONTROL and STATUS REGISTER (UARTPRT)

In mode 2, 3 (9-bit UART data), by setting the parity enable bit (PEN0, 1, 2) of UARTPRT register to '1', the 9 th data bit of transmit data will be an automatically generated parity bit. Also, the 9 th data bit of the received data will be treated as a parity bit for checking the received data.

In parity enable mode (PENn = 1), UARTCON.3 (TB8) and UARTCON.2 (RB8) will be a parity selection bit for transmit and receive data respectively. The UARTCON.3 (TB8) is for settings of the even parity generation (TB8

= 0) or the odd parity generation (TB8 = 1) in the transmit mode. The UARTCON.2 (RB8) is also for settings of the even parity checking (RB8= 0) or the odd parity checking (RB8 =1) in the receive mode. The parity enable

(generation / checking) functions are not available in UART mode 0 and 1. If you don’t want to use a parity mode,

UARTCON.2 (RB8) and UARTCON.3 (TB8) are a normal control bit as the 9 th data bit, in this case, PENn must be disable (“0”) in mode 2, 3. Also it is needed to select the 9th data bit to be transmitted by writing TB8 to "0" or

"1".

The receive parity error flag (RPEn) will be set to ‘0’ or ‘1’ depending on parity error whenever the 8 th data bit of the received data has been shifted.

MSB

UART Parity Register (UARTPRT)

06H, Page 8, R/W

– RPE2 RPE1 RPE0 – PEN2 PEN1 PEN0

LSB

Not used Not used

UART2 Parity Error Status:

0 = No error

1 = Parity error


0 = No error

1 = Parity error

UART0 Parity Enable/Disable:

0 = Disable

1 = Enable


0 = Disable

1 = Enable


0 = No error

1 = Parity error


0 = Disable

1 = Enable

Figure 14-3. UART Parity Register

14-4


UART DATA REGISTER (UDATA0, UDATA1, UDATA2)

MSB

.7

UART Data Register

(UDATA0) E2H, Set 1, Bank 1, R/W

(UDATA1) FAH, Set 1, Bank 1, R/W

(UDATA2) 05H, Page 8, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

UART(0/1/2)

Transmit or receive data

Figure 14-4. UART Data Register (UDATA0, UDATA1, UDATA2)

UART BAUD RATE DATA REGISTER (BRDATA0, BRDATA1, BRDATA2)

The value stored in the baud rate register, BRDATA0, BRDATA1, BRDATA2 lets you determine the UART clock rate (baud rate).

MSB

.7

UART Baud Data Register

(BRDAT0) E4H, Set 1, Bank 1, R/W

(BRDAT1) FCH, Set 1, Bank 1, R/W

(BRDAT2) 04H, Page 8, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Baud Rate data

Figure 14-5. UART Baud Rate Data Register (BRDATA0, BRDATA1, BRDATA2)

BAUD RATE CALCULATIONS (UART0)

Mode 0 Baud Rate Calculation

In mode 0, the baud rate is determined by the UART0 baud rate data register, BRDATA0 in set1, bank 1 at address E4H.

Mode 0 baud rate = fxx/(16

× (BRDATA0 + 1))

Mode 2 Baud Rate Calculation

The baud rate in mode 2 is fixed at the f

OSC

clock frequency divided by 16:

Mode 2 baud rate = fxx/16

Modes 1 and 3 Baud Rate Calculation

In modes 1 and 3, the baud rate is determined by the UART0 baud rate data register, BRDATA0 in set 1, bank 1 at address E4H.

Mode 1 and 3 baud rate = fxx/(16

× (BRDATA0 + 1))

14-5

Mode 2

Mode 0

Mode 1

Mode 3

Mode

Table 14-1. Commonly Used Baud Rates Generated by BRDATA0, 1, 2

Baud Rate

0.5 MHz

230,400 Hz

115,200 Hz

57,600 Hz

38,400 Hz

19,200 Hz

9,600 Hz

4,800 Hz

62,500 Hz

9,615 Hz

38,461 Hz

12,500 Hz

19,230 Hz

9,615 Hz

Oscillation Clock

8 MHz

11.0592 MHz

11.0592 MHz

11.0592 MHz

11.0592 MHz

11.0592 MHz

11.0592 MHz

11.0592 MHz

10 MHz

10 MHz

8 MHz

8 MHz

4 MHz

4 MHz

BRDATA0, 1, 2

Decimal Hexdecimal x

02 x

02H

05

11

05H

0BH

64

12

39

12

25

17

35

71

143

09

40H

0CH

27H

0CH

19H

11H

23H

47H

8FH

09H

14-6


BLOCK DIAGRAM

RE

RIE

1-to-0

Transition

Detector

MS0

MS1

RxD fxx

BRDATA

Baud Rate

Generator

SAM8 Internal Data Bus

TB8

D

CLK

S

Q

UARTDATA

CLK

Zero Detector

Write to

UARTDATA

Start

Shift

Tx Clock

Tx Control

TIP

EN

Send

IRQ7

Interrupt

TIE

RIE

Rx Clock

RIP Receive

Rx Control

Start

Shift

Bit Detector

Shift

Value

Shift

Register

UARTDATA

SAM8 Internal Data Bus

MS0

MS1

Shift

Clock

Figure 14-6. UART Functional Block Diagram

UART(0/1/2)

RxD

TxD

TxD

14-7

UART0 MODE 0 FUNCTION DESCRIPTION

In mode 0, UART0 is input and output through the RxD0 (P5.3) pin and TxD0 (P5.2) pin outputs the shift clock.

Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first.

Mode 0 Transmit Procedure

1. Select mode 0 by setting UARTCON0.6 and .7 to "00B".

2. Write transmission data to the shift register UDATA0 (E2H, set 1, bank 1) to start the transmission operation.

Mode 0 Receive Procedure

1. Select mode 0 by setting UATCON0.6 and .7 to "00B".

2. Clear the receive interrupt pending bit (UARTPND.1) by writing a "0" to UARTPND.1.

3. Set the UART0 receive enable bit (UARTCON0.4) to "1".

4. The shift clock will now be output to the TxD0 (P5.2) pin and will read the data at the RxD0 (P5.3) pin. A

UART0 receive interrupt (IRQ7, vector F0H) occurs when UARTCON0.1 is set to "1".

Write to Shift Register (UDATA)

Shift

RxD (Data Out)

TxD (Shift Clock)

D0 D1 D2 D3 D4 D5 D6 D7

TIP

Write to UARTPND (Clear RIP and set RE)

RIP

RE

Shift

RxD (Data In)

TxD (Shift Clock)

D0 D1 D2 D3 D4 D5 D6

1 2 3 4 5 6 7

Figure 14-7. Timing Diagram for UART Mode 0 Operation

8

D7

14-8



In mode 1, 10-bits are transmitted through the TxD0 pin or received through the RxD0 pin. Each data frame has three components:

— Start bit ("0")

— 8 data bits (LSB first)

— Stop bit ("1")

When receiving, the stop bit is written to the RB8 bit in the UARTCON0 register. The baud rate for mode 1 is variable.


1. Select the baud rate generated by setting BRDATA0.

2. Select mode 1 (8-bit UART0) by setting UARTCON0 bits 7 and 6 to '01B'.

3. Write transmission data to the shift register UDATA0 (E2H, set 1, bank 1). The start and stop bits are generated automatically by hardware.


1. Select the baud rate to be generated by setting BRDATA0.

2. Select mode 1 and set the RE (Receive Enable) bit in the UARTCON0 register to "1".

3. The start bit low ("0") condition at the RxD0 (P5.3) pin will cause the UART0 module to start the serial data receive operation.

Shift

TxD

TIP

Tx

Clock

Write to Shift Register (UDATA)

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit

Rx

Clock

RxD

Bit Detect Sample Time

Shift

RIP

Start Bit

D0 D1 D2 D3 D4 D5 D6


D7 Stop Bit

14-9


In mode 2, 11-bits are transmitted (through the TxD0 pin) or received (through the RxD0 pin). Each data frame has four components:

— Start bit ("0")


— Programmable 9th data bit

— Stop bit ("1")

The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UARTCON0.3).

When receiving, the 9th data bit that is received is written to the RB8 bit (UARTCON0.2), while the stop bit is ignored. The baud rate for mode 2 is fosc/16 clock frequency.


1. Select mode 2 (9-bit UART0) by setting UARTCON0 bits 6 and 7 to '10B'. Also, select the 9th data bit to be transmitted by writing TB8 to "0" or "1".

2. Write transmission data to the shift register, UDATA0 (E2H, set 1, bank 1), to start the transmit operation.


1. Select mode 2 and set the receive enable bit (RE) in the UARTCON0 register to "1".

2. The receive operation starts when the signal at the RxD pin goes to low level.

Shift

TxD

TIP

Tx

Clock

Write to Shift Register (UARTDATA)

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit

Rx

Clock

RxD


Shift

RIP

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7 RB8

Stop

Bit


14-10



In mode 3, 11-bits are transmitted (through the TxD0) or received (through the RxD0). Mode 3 is identical to mode 2 except for baud rate, which is variable. Each data frame has four components:

— Start bit ("0")


— Programmable 9th data bit

— Stop bit ("1")


1. Select the baud rate generated by setting BRDATA0.

2. Select mode 3 operation (9-bit UART0) by setting UARTCON0 bits 6 and 7 to '11B'. Also, select the 9th data bit to be transmitted by writing UARTCON0.3 (TB8) to "0" or "1".

3. Write transmission data to the shift register, UDATA0 (E2H, set 1, bank 1), to start the transmit operation.


1. Select the baud rate to be generated by setting BRDATA0.

2. Select mode 3 and set the RE (Receive Enable) bit in the UARTCON0 register to "1".

3. The receive operation will be started when the signal at the RxD0 pin goes to low level.

Shift

TxD

TIP

Tx

Clock

Write to Shift Register (UARTDATA)

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit

Rx

Clock

RxD


Shift

RIP

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7 RB8

Stop

Bit


14-11

SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS

The S3C8-series multiprocessor communication feature lets a "master" S3C84MB/F84MB send a multiple-frame serial message to a "slave" device in a multi-S3C84MB/F84MB configuration. It does this without interrupting other slave devices that may be on the same serial line.

This feature can be used only in UART modes 2 or 3. In these modes 2 and 3, 9 data bits are received. The 9th bit value is written to RB8 (UARTCONn.2). The data receive operation is concluded with a stop bit. You can program this function so that when the stop bit is received, the serial interrupt will be generated only if RB8 = "1".

To enable this feature, you set the MCE bit in the UARTCONn register. When the MCE bit is "1", serial data frames that are received with the 9th bit = "0" do not generate an interrupt. In this case, the 9th bit simply separates the address from the serial data.

Sample Protocol for Master/Slave Interaction

When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In an address byte, the 9th bit is "1" and in a data byte, it is "0".

The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes.

The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the incoming data bytes.

While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit.

For mode 1 reception, if MCE is "1", the receive interrupt will be issue unless a valid stop bit is received.

14-12


Setup Procedure for Multiprocessor Communications

Follow these steps to configure multiprocessor communications:

1. Set all S3C84MB/F84MB devices (masters and slaves) to UART mode 2 or 3.

2. Write the MCE bit of all the slave devices to "1".

3. The master device's transmission protocol is:

— First byte: the address identifying the target slave device (9th bit = "1")

— Next bytes: data

(9th bit = "0")

4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1".

The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data. The other slaves continue operating normally.

Full-Duplex Multi-S3C84MB/F84MB Interconnect

TxD RxD

Master

S3C84MB

/F84MB

TxD RxD

Slave 1

S3C84MB

/F84MB

TxD RxD

Slave 2

S3C84MB

/F84MB

. . .

TxD RxD

Slave n

S3C84MB

/F84MB

Figure 14-11. Connection Example for Multiprocessor Serial Data Communications

14-13

S3C84MB/F84MB_UM_REV1.00 10-BIT A/D CONVERTER

15

10-BIT A/D CONVERTER

OVERVIEW

The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the fifteen input channels to equivalent 10-bit digital values. The analog input level must lie between the

AV

REF

and AV

SS

values. The A/D converter has the following components:

— Analog comparator with successive approximation logic

— D/A converter logic (resistor string type)

— ADC control register, ADCON (set 1, bank 1, F7H, read/write, but ADCON.3 is read only)

— Eight multiplexed analog data input pins (ADC0–ADC14)

— 10-bit A/D conversion data output register (ADDATAH, ADDATAL)

AV

REF

and AV

SS


To initiate an analog-to-digital conversion procedure, at first, you must configure P6.0~6, P7.0~7 to analog input before A/D conversions because the P6.0~6, P7.0~7 pins can be used alternatively as normal I/O or analog input pins. To do this, you load the appropriate value to the P6CON, P7CON (for ADC0 – ADC14) register.

And you write the channel selection data in the A/D converter control register ADCON to select one of the fifteen analog input pins (ADCn, n = 0–14) and set the conversion start or enable bit, ADCON.0.

An 10-bit conversion operation can be performed for only one analog input channel at a time.

The read-write ADCON register is located in set 1, bank 1 at address F7H.

During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate half-way point of a 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time.

You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6–4) in the ADCON register.

To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed,

ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH,

ADDATAL registers where it can be read. The ADC module enters an idle state. Remember to read the contents of ADDATAH and ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result.

NOTE

Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ADC0–ADC14 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to circuit noise, will invalidate the result.

15-1

10-BIT A/D CONVERTER S3C84MB/F84MB_UM_REV1.00

A/D CONVERTER CONTROL REGISTER (ADCON)

The A/D converter control register, ADCON, is located in set1, bank 1 at address F7H. ADCON is read-write addressable using 8-bit instructions only. But EOC bit, ADCON.3 is read only. ADCON has four functions:

— Bits 7–4 select an analog input pin (ADC0–ADC14).

— Bit 3 indicates the end of conversion status of the A/D conversion.

— Bits 2–1 select a conversion speed.

— Bit 0 starts the A/D conversion.

Only one analog input channel can be selected at a time. You can dynamically select any one of the eight analog input pins, ADC0–ADC14 by manipulating the 4-bit value for ADCON.7–ADCON.4

MSB

A/D Converter Control Register (ADCON)

F7H, Set 1, Bank 1, R/W (ADCON.3 bit is read-only)

.7

.6

.5

.4

.3

.2

.1

.0

LSB

A/D Input Pin Selection bits:

.7.6.5.4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

A/D Input Pin

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

ADC10

ADC11

ADC12

ADC13

ADC14

A/D Start or Enable bit

0 = Disable Operation

1 = Start Operation

Clock Selection bit:

.2 .1

0 0

0 1

1 0

1 1

Conversion Clock f

XX

/16 f

XX

/8 f

XX

/4 f

XX

/1

End-of-Conversion bit (read only):

0 = Conversion not complete

1 = Conversion complete

Figure 15-1. A/D Converter Control Register (ADCON)

15-2


MSB

Conversion Data Register High Byte (ADDATAH)

F8H, Set 1, Bank 1, Read only

.7

.6

.5

.4

.3

.2

.1

.0

LSB

MSB

Conversion Data Register Low Byte (ADDATAL)

F9H, Set 1, Bank 1, Read only x x x x x x .1

.0

LSB

Figure 15-2. A/D Converter Data Register (ADDATAH, ADDATAL)

ADCON.7-4

(Select one input pin of the assigned)

Input Pins

ADC0-ADC14

(P6.0-P7.6)

(P7.0-P7.7)

.

.

.

ADCON.2-1

Clock

Selector

To ADCON.3

(EOC Flag)

ADCON.0

(AD/C Enable)

-

+

Analog

Comparator

ADCON.0

(A/D Conversion enable)

10-bit D/A

Converter

Successive

Approximation

Logic

10-bit result is loaded into

A/D Conversion

Data Register

AV

REF

AV

SS

Conversion Result

(ADDATAH,ADDATAL)

Figure 15-3. A/D Converter Circuit Diagram

To Data

15-3


INTERNAL REFERENCE VOLTAGE LEVELS

In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AV

SS

to AV

REF

(usually AV

REF

= V

DD

).

Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 AV

REF

.

CONVERSION TIMING

The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion. Therefore, total of 50 clocks is required to complete a 10-bit conversion. With a maximum ADC input clock frequency (2.5 MHz), one clock cycle is 400 ns. If each bit conversion requires 4 clocks, the conversion rate is calculated as follows:

4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks

50 clock x 400 ns = 20

μs at f

ADC

=2.5 MHz, 1 clock time = 1/ f

ADC

ADCON.0 ← 1

Conversion

Start

EOC

50 ADC Clock

ADDATA

Previous

Value

9 8 7 6 5 4 3 2 1 0

ADDATAH (8-bit) + ADDATL (2-bit)

Setup Time

10 Clock

40 Clock

Figure 15-4. A/D Converter Timing Diagram

15-4


INTERNAL A/D CONVERSION PROCEDURE

1. Analog input must remain between the voltage range of AV

SS

and AV

REF

.

2. Configure P7.0–P7.7 for analog input before A/D conversions. To do this, you load the appropriate value to the P7CON (for ADC0–ADC14) register.

3. Before the conversion operation starts, you must first select one of the eight input pins (ADC0–ADC14) by writing the appropriate value to the ADCON register.

4. When conversion has been completed, (50 clocks have elapsed), the EOC, ADCON.3 flag is set to "1", so that a check can be made to verify that the conversion was successful.

5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), then the

ADC module enters an idle state.

6. The digital conversion result can now be read from the ADDATAH and ADDATAL register.

V

DD

Reference

Voltage

Input

C1 C2

R1

AV

REF

S3C84MB/

F84MB

Analog

Input

ADC0-ADC14

R2

C3

AV

SS

V

SS

NOTE: The symbol "R1" signifies an offset resistor with a value of from 50 to 100

Ω

ٛ

If this resistor is omitted, the absolute accuracy will be maximum of 3LSBs.

C1=10

μF, C2=100 to 1000pF, C3=100 to 1000pF, R1=50 to 100Ω, R2=10 to 1KΩ

ٛ

Figure 15-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy

15-5


)

PROGRAMMING TIP — Configuring A/D Converter

•

•

SB0

LD P7CON,#11111111B ; P7.7–P7.0 A/D Input MODE

•

•

SB1

LD

AD0_CHK: TM

JR

ADCON,#00000001B ; Channel ADC0, Conversion start

ADCON,#00001000B ; A/D conversion end ?

→ EOC check

Z, AD0_CHK ; No

LD AD0BUFL,ADDATAL ; 2-bit Conversion data

SB0

•

•

SB1

AD3_CHK:

LD

TM

ADCON,#00110001B ; Channel AD3, f

XX

/16, Conversion start

ADCON,#00001000B ; A/D conversion end ?

→ EOC check

Z,AD3_CHK No

LD AD3BUFL,ADDATAL ; 2-bit Conversion data

SB0

•

•

15-6


16

PULSE WIDTH MODULATION

OVERVIEW

The S3C84MB/F84MB microcontrollers have two 14-bit PWM circuits and two 8-bit PWM circuits. The 14-bit circuits are called PWM0 and PWM1; the 8-bit circuits are PWM2–PWM3. The operation of all the PWM circuits is controlled by a single control register, PWMCON. PWMCON also contains a 3-bit prescaler for adjusting the

PWM frequency (cycle).

The PWM counter is a 14-bit incrementing counter. It is used by the 14-bit PWM circuits. To start the counter and enable the PWM circuits, you must set PWMCON.0 to "1". If the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value.

The 3-bit prescaler controls the clock input frequency to the PWM counter. By modifying the prescaler value, you can divide the input clock by one (non-divided), two, three, four, five, six, seven, or eight. The prescaler output is the clock frequency of the PWM counter.

PWM CONTROL REGISTER (PWMCON)

The control register for the PWM module, PWMCON, is located at the register address 07H in Page 8. Bit settings in the PWMCON register control the following functions:

— 3-bit prescaler for scaling the PWM counter clock

— Stop/start (or resume) the PWM counter operation

A reset clears all PWMCON bits to logic zero, disabling the entire PWM module.

PWM

16-1

PWM S3C84MB/F84MB_UM_REV1.00

MSB

.7

PWM Control Register (PWMCON)

07H, Pwge 8, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not Used Not Used

000

001

010

011

100

101

110

111

Input Clock Selection bits : f

XX

/1 f

XX

/2 f

XX

/3 f

XX

/4 f

XX

/5 f

XX

/6 f

XX

/7 f

XX

/8

PWM Counter Enable bits :

0

1

Stop Counter

Start(Resume ) Counting

Figure 16-1. PWM Control Register (PWMCON)

16-2

S3C84MB/F84MB_UM_REV1.00 PWM

PWM2–PWM3

The S3C84MB/F84MB microcontrollers have two 8-bit PWM circuits, called PWM2–PWM3. These 8-bit circuits have the following components:

— 8-bit counter with 3-bit prescaler

— 8-bit comparators

— 8-bit PWM data registers (PWMDAT2–PWMDAT3)

— PWM output pins (PWM2–PWM3)

The PWM2–PWM3 circuits are controlled by the PWMCON register (07H, Page 8).

8-Bit

Data Register

8-Bit

Data Buffer

Overflow

8-Bit

Comparator

“0” When Data = Counter

“1” When Data > Counter

PWM Output f

OSC

PWMCON.0

8-bit Counter

Prescaler

Figure 16-2. Block Diagram for PWM2 and PWM3

16-3


PWM2, PWM3 FUNCTION DESCRIPTION

All the two 8-bit PWM circuits function identically: each has its own 8-bit data register and 8-bit comparator. Each circuit compares a unique data register value to the lower 8-bit value of the 8bit PWM counter.

The PWM2–PWM3 data registers are located in Page 8, at locations 0CH, 0DH, respectively. These data registers are read/write addressable. By loading specific values into the respective data registers, you can modulate the pulse width at the corresponding PWM output pins, PWM2–PWM3.

The level at the output pins toggles High and Low at a frequency equal to the counter clock, divided by 256 (2

8

).

The duty cycle of the PWM0 and PWM1 pins ranges from 0% to 99.6%, based on the corresponding data register values. To determine the PWM output duty cycle, its 8-bit comparator sends the output level High when the data register value is greater than the lower 8-bit count value. The output level is Low when the data register value is less than or equal to the lower 8-bit count value. The output level at the PWM2–PWM3 pins remains at Low level for the first 256 counter clocks. Then, each PWM waveform is repeated continuously, at the same frequency and duty cycle, until one of the following three events occurs:

— The counter is stopped

— The counter clock frequency is changed

— A new value is written to the PWM data register

Counter

Clock

PWMDAT = 0

PWMDAT = 1

PWMDAT = 80h

PWMDAT = FFh

Figure 16-3. PWM Waveforms for PWM2, PWM3

16-4


STAGGERED PWM OUTPUTS

The PWM0–PWM3 outputs are staggered in order to reduce the overall noise level on the pulse width modulation circuits. If you load the same value to the PWM0–PWM3 data registers, a match condition (data register value is equal to the lower 8-bit count value) will occur on the same clock cycle for all the PWM circuits. The output of

PWM1~3 is delayed by one-half of CPU clock for subsequent clock cycles (see Figure 16-4). f

XX

/1

PWM0

PWM1

? Clock Delay

PWM2

1 Clock Delay

PWM3

1? Clock Delay

Figure 16-4. PWM Clock to PWM2, PWM3 Output Delays

16-5


PWM0–PWM1

The S3C84MB/F84MB pulse width modulation (PWM) module has two 14-bit PWM circuits (PWM0 and PWM1).

The 14-bit PWM circuits have the following components:

— 14-bit counter with 3-bit prescaler (an 8-bit counter with 6-bit extension is used for 14-bit output resolution)

— 8-bit comparator and extension cycle circuit

— 8-bit reference data registers (PWM0, PWM1)

— 6-bit extension data registers (PWM0EX, PWM1EX)

— PWM output pins (PWM0, PWM1)

The PWM0 and PWM1 circuits are enabled by the PWMCON register (07H, Page 8).

PWM COUNTER

The PWM counter is a 14-bit increasing counter comprised of a lower byte counter and an upper byte counter. To determine the PWM module's base operating frequency, the lower byte counter is compared to the PWM data register value. In order to achieve higher resolutions, the lower six bits of the upper byte counter can be used to modulate the "stretch" cycle. To control the "stretching" of the PWM output duty cycle at specific intervals, the 6bit extended counter value is compared with the 6-bit value (bits 2–7) that you write to the module's extension register.

PWM DATA AND EXTENSION REGISTERS

Two PWM (duty) data registers, located Page 8, determine the output value generated by each 14-bit PWM circuit. PWM0 and PWM1 are read/write addressable.

— 8-bit data registers PWM0 (08H) and PWM1(0AH)

— 6-bit extension registers PWM0EX (F5H) and PWM1EX (F7H) of which only bits 2–7 are used

To program the required PWM output, you should load the appropriate initialization values into the 8-bit data registers (PWM0, PWM1) and the 6-bit extension registers (PWM0EX, PWM1EX). To start the PWM counter, or to resume counting, you should set PWMCON.5 to "1". A reset operation disables all PWM output. The current counter value is retained when the counter stops. When the counter starts, counting resumes at the retained value.

PWM CLOCK RATE

The timing characteristics of both 14-bit output channels are identical, and are based on the maximum CPU clock frequency. The 3-bit prescaler value in the PWMCON register determines the frequency of the counter clock.

You can set PWMCON.6-4 to divide the CPU clock frequency by 1 (non-divided), 2, 3, 4, 5, 6, 7, or 8.

Because the maximum CPU clock rate for the S3C84MB/F84MB microcontrollers is 16 MHz, the maximum base

PWM frequency is 62.5 kHz (16 MHz divided by 256). This assumes a non-divided CPU clock.

16-6


Register Name

PWM0 Data Register

PWM0 Data Register

PWM Control Register

Table 16-1. PWM0 and PWM1 Control and Data Registers

Mnemonic

PWM0

PWM0EX

PWM1

PWM1EX

PWMCON

Address (Page 8)

08h

09h

0Ah

0Bh

07h

Function

8-bit PWM0 basic cycle frame value

6-bit extension ("stretch") value

8-bit PWM1 basic cycle frame value

6-bit extension ("stretch") value

PWM0 counter stop/start (resume), and

3-bit prescaler for CPU clock; also contains capture A control settings

Upper 6-Bit of

14-bit Counter

6-Bit extension

Register

14-bit Counter Overflow

8-Bit

Data Register f

OSC

PWMCON.0

Extension

Data Buffer

8-Bit

Data Buffer

Extension

Control Logic

8-Bit

Comparator

“1” When Data = Counter

“1” When Data > Counter

Prescaler

Lower 8-Bit of

14-bit Counter

Figure 16-5. Block Diagram for PWM0 and PWM1

PWM Output

16-7


PWM0 AND PWM1 FUNCTION DESCRIPTION

The PWM output signal toggles to Low level whenever the lower 8-bit counter matches the reference value stored in the module's data register (PWM0, PWM1). If the value in the PWM data register is not zero, an overflow of the lower counter causes the PWM output to toggle to High level. In this way, the reference value written to the data register determines the module's base duty cycle.

The value in the 6-bit extension counter (the lower six bits of the upper counter) is compared with the extension settings in the 6-bit extension data register (PWM0EX, PWM1EX). This 6-bit extension counter value (bits 2–7), together with extension logic and the PWM module's extension register, is then used to "stretch" the duty cycle of the PWM output. The "stretch" value is one extra clock period at specific intervals, or cycles (see Table 16-2). If, for example, the value in the extension register is '1', the 32nd cycle will be one pulse longer than the other 63 cycles. If the base duty cycle is 50%, the duty of the 32nd cycle will therefore be "stretched" to approximately 51% duty. For example, if you write 80H to the extension register, all odd-numbered pulses will be one cycle longer. If you write FCH to the extension register, all pulses will be stretched by one cycle except the 64th pulse. PWM output goes to an output buffer and then to the corresponding PWM0 and PWM1 output pin. In this way, you can obtain high output resolution at high frequencies.

Table 16-2. PWM Output "Stretch" Values for Extension Registers PWM0EX and PWM1EX

PWM0EX/PWM1EX Bit

3

2

1

0

7

6

5

4

“Stretched” Cycle Number

1, 3, 5, 7, 9, ..., 55, 57, 59, 61, 63

2, 6, 10, 14, ..., 50, 54, 58, 62

4, 12, 20, 28, ..., 44, 52, 60

8, 24, 40, 58

16, 48

32

Not Used

Not Used

16-8


)

PROGRAMMING TIP — Programming PWM0 to Sample Specifications

This example shows how to program the 14-bit pulse-width modulation module, PWM0. The program parameters are as follows:

— The oscillation frequency of the main crystal is 6 MHz

— PWM0 data is in the working register R0

— PWM0EX (PWM0 extension value) is in the working register R1, bits 2–7

The program performs the following operations:

1. Set the PWM0 frequency to 23.437 kHz

2. If R3.0 = "1", then PWM

← PWM + 12H

(If an overflow occurs from R0, then R0

← 0FFH and R1 ← 0FCH.)

3. If R3.0 = "0", then PWM

← PWM – 11H

(If an underflow occurs from R0, then R0

← 00H and R1 ← 00H.)

PWMCON ← #01h

N(0)

R3.0 = 1?

N

R1 ← R1 - #20h

Underflow?

Y

Y(1)

R1 ← R1 + #48h

Carry?

Y

Y

R1 ← R1 - #20h

Borrow?

R0 ← Min.value

R1 ← Min.value

N

N

R0 ← R1 + #01h

Carry?

N

Y

R0 ← Max.value

R1 ← Max.value

PWM0EX ← R1

PWM0 ← R0

Figure 16-6. Decision Flowchart for PWM0 Programming Tip

16-9


)

PROGRAMMING TIP . Programming PWM0 to Sample Specifications (Continued)

•

•

•

LD PWMCON, #01H ; PS ← 0 (Select 23.437-kHz PWM frequency)

; Enable the PWM counter

•

•

•

BTJRF pwm0_dec, R3.0 ; If R3.0 = "0", then jump to pwm0_dec pwm0_inc:

ADD R1, #48H ; If R3.0 = "1", then add 48H to the PWM data

JR NC, pwm0_data_end ; If no carry, go to pwm0_data_end

INC R0 ; R0 ← R0 + 1

JR NZ, pwm0_data_end ; If no overflow, jump to pwm0_data_end for update

LD R0, #0FFH ; If overflow, set 0FFH to R0

LD R1, #0FCH ; Set 0FCH to R1

JR T, pwm0_data_end ; Jump to pwm0_data_end unconditionally pwm0_dec:

SUB R1, #44H ; R3.0 = "0", so subtract 44H from PWM data

JP NC, pwm0_data_end ; If no borrow, jump to pwm0_data_end for update

SUB R0, #01H ; Decrement R0 (R0 ← R0 . 1)

JR NC, pwm0_data_end ; If no borrow, jump to pwm0_data_end

CLR R0 ; Clear data R0

CLR R1 ; Clear data R1

.

.

. pwm0_data_end:

LD PWM0EX, R1

LD PWM0, R0

; Load new value to PWM0EX (bits 2.7)

; Load new value to PWM0

16-10

S3C84MB/F84MB_UM_REV1.00 PATTERN GENERATION MODULE

17

PATTERN GENERATION MODULE

OVERVIEW

PATTERN GENERATION FLOW

You can output up to 8-bit through P0.0-P0.7 by tracing the following sequence. First of all, you have to change the PGDATA into what you want to output. And then you have to set the PGCON to enable the pattern generation module and select the triggering signal. From now, bits of PGDATA are on the P0.0-P0.7 whenever the selected triggering signal occurs.

Write pattern data to PGDATA

Triggering signal selection: PGCON.3-.0

Triggering signal generation

Data output through P0.0-P0.7

Figure 17-1. Pattern Generation Flow

17-1

PATTERN GENERATION MODULE S3C84MB/F84MB_UM_REV1.00

Pattern Generation Module Control Register (PGCON)

FEH, Set 1, Bank 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

PGDATA

(Set 1, Bank 1, FFH)

.2

.1

.0

.5

.4

.7

.6

.3

Not used

00

01

10

11

PG operation mode selection bit

Timer A match signal triggering

Timer B underflow signal triggering

Timer 1(0) match signal triggering

S/W triggering mode

Bit2: 0 = PG operation disable

1 = PG operation enable

Bit3: 0 = No effect

1 = S/W trigger start (auto clear)

Figure 17-2. PG Control Register (PGCON)

PG Buffer

.5

.4

.7

.6

.3

.2

.1

.0

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

S/W

Timer A match signal

Timer B underflow signal

Timer 1(0) match signal

Figure 17-3. Pattern Generation Circuit Diagram

17-2

S3C84MB/F84MB_UM_REV1.00 PATTERN GENERATION MODULE

)

Programming Tip — Using the Pattern Generation

INITIAL:

SB0

LD

LD

LD

LD

SYM,#00h

IMR,#01h

SPH,#0h

SPL,#0FFh

; Disable Global interrupt

→ SYM


; High byte of stack pointer

→ SPH

; Low byte of stack pointer

→ SPL

LD P0CON,#11111111b

EI

; Enable PG output

MAIN:

NOP

NOP

SB1

LD

OR

SB0

PGDATA,#10101010b

PGCON,#00001111b

; Setting pattern data

; Triggering then pattern data are output

NOP

NOP

.END

17-3

S3C84MB/F84MB_UM_REV1.00 EMBEDDED FLASH MEMORY INTERFACE

18

EMBEDDED FLASH MEMEORY INTERFACE

OVERVIEW

The S3F84MB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash memory area any time you want. The S3F84MB‘s embedded 64K-byte memory has two operating features as below:

— User Program Mode

— Tool Program Mode: Refer to the chapter 21. S3F84MB FLASH MCU

Flash ROM Configuration

The S3F84MB flash memory consists of 512 sectors. Each sector consists of 128bytes. So, the total size of flash memory is 512x128 bytes (64KB). User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time.

— 64Kbyte Internal flash memory

— Sector size: 128-Bytes

— 10years data retention

— Fast programming Time:

Sector Erase: 10ms (min)

Byte Program: 40us (min)

— User programmable by ‘LDC’ instruction

— Sector (128-Bytes) erase available

— External serial programming support

— Endurance: 10,000 Erase/Program cycles (min)

— Expandable OBPTM (On Board Program)

User Program Mode

This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection).

The S3F84MB has the internal pumping circuit to generate high voltage. Therefore, 12.5V into V

PP

(TEST) pin is not needed. To program a flash memory in this mode several control registers will be used.

There are four kind functions in user program mode – programming, reading, sector erase, and one protection mode (Hard lock protection).

18-1

EMBEDDED FLASH MEMORY INTERFACE S3C84MB/F84MB_UM_REV1.00

ISP

TM

(ON-BOARD PROGRAMMING) SECTOR

ISP

TM

sectors located in program memory area can store On Board Program Software (Boot program code for upgrading application code by interfacing with I/O port pin). The ISP

TM

sectors can’t be erased or programmed by

‘LDC’ instruction for the safety of On Board Program Software.

The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart

Option. If you don’t like to use ISP sector, this area can be used as a normal program memory (can be erased or programmed by ‘LDC’ instruction) by setting ISP disable bit (“1”) at the Smart Option. Even if ISP sector is selected, ISP sector can be erased or programmed in the tool program mode by serial programming tools.

The size of ISP sector can be varied by settings of smart option (Refer to Figure 2-2 and Table 18-1). You can choose appropriate ISP sector size according to the size of On Board Program Software.

FFFFh

Internal

Program

Memory

(Flash )

NOTE

ISP Sector

Interrupt Vector Area

Smart Option Rom Cell

1FFh, 2FFh, 4FFh or 8FFh

100h

64 KByte

040h

03Ch

000h

Figure 18-1. Program Memory Address Space

NOTE: User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit (3EH.2) is ‘1’,

3EH.1 and 3EH.0 are meaningless

18-2


Table 18-1. ISP Sector Size

Smart Option (003EH) ISP Size Selection Bit

Area of ISP Sector

Bit 2 Bit 1 Bit 0

1 x x 0

0

0

0

0

0

0

1

1

0

1

0

1

100H – 1FFH (256 Bytes)

100H – 2FFH (512 Bytes)

100H – 4FFH (1024 Bytes)

100H – 8FFH (2048 Bytes)

ISP Sector Size

0

256 Bytes

512 Bytes

1024 Bytes

2048 Bytes

NOTE: The area of the ISP sector selected by smart option bit (3EH.2 – 3EH.0) can’t be erased and programmed by ‘LDC’ instruction in user program mode.

18-3


FLASH MEMORY CONTROL REGISTERS

FLASH MEMORY CONTROL REGISTER

FMCON register is available only in user program mode to program some data to the flash memory.

MSB

.7

.6

Flash Memory Control Register

(FMCON) FDH, Set 1, Bank 1, R/W

.5

.4

.3

.2

.1

.0

LSB

Flash Memory Mode Selection Bits

0101

1010

0110 others

Programing mode

Erase mode

Hard lock mode

Not used

INT Enable Bit

During Sector Erase

0 = Interrupt Disable

1 = Interrupt Enable

Not Used

Flash Operation Start Bit

0 = Operation stop

1 = Operation start

( This bit will be cleared automatically just after the corresponding operation completed. )

Setocr Erase Status Bit

0 = Sector is Sucessfully Erased

1 = Sector Erase Fail

Figure 18-2. Flash Memory Control Register (FMCON)

FLASH MEMORY USER PROGRAMMING ENABLE REGISTER

After reset, the user-programming mode is disabled, because the value of FMUSR is “00000000B”.

If necessary, you can use the user programming mode by setting the value of FMUSR is “10100101B”.

MSB

Flash Memory User Programming Enable Register

(FMUSR) 00H, Page 8, R/W

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash Memory User Programming Enable bits :

0000 0000

1010 0101 others

Disable user Programming Mode

Enable user Programming Mode

Not used

Figure 18-3. Flash Memory User Programming Enable Register (FMUSR)

18-4


FLASH MEMORY SECTOR ADDRESS REGISTERS

There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory

Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory

Address Sector Register High Byte) indicates the high byte of sector address.

One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of sector is XX00H or XX80H. So bit .6-.0 of FMSECL don’t mean whether the value is ‘1’ or ‘0’. We recommend that it is the simplest way to load the sector base address into FMSECH and FMSECL register. When programming the flash memory, user should program after loading a sector base address, which is located in the destination address to write data into FMSECH and FMSECL register. If the next operation is also to write one byte data, user should check whether next destination address is located in the same sector or not. In case of other sectors, user should load sector address to FMSECH and FMSECL Register according to the sector. (Refer to page 15-16

PROGRAMMING TIP — Programming)

Flash Memory Sector Address Register, High Byte

(FMSECH ) 12H, Page 8, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash Memory Sector Address Register Enable bit :

You have to input High address of sector that's accessed

Figure 18-4. Flash Memory Sector Address Register (FMSECH)

MSB

Flash Memory Sector Address Register, Low Byte

(FMSECL ) 13H, Page 8, R/W

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Flash Memory Sector Address Register Enable bit :

You have to input Low address of sector that's accessed

Figure 18-5. Flash Memory Sector Address Register (FMSECL)

18-5


SECTOR ERASE

User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and written in User Program Mode is called sector. The program memory of

S3F84MB, 64Kbytes flash memory, is divided into 512 sectors. Every sector has all 128-byte sizes. So the sector to be located destination address should be erased first to program a new data (one byte) into flash memory.

Minimum 10ms’ delay time for the erase is required after setting sector address and triggering erase start bit

(FMCON.0). Sector erase is not supported in tool program modes (MDS mode tool or programming tool).

Sector 511

(128 Byte)

Sector 510

(128 Byte)

.

.

.

.

.

.

Sector 19

(128 Byte)

Sector 18

(128 Byte)

Sector 0 - 17

(128 Byte x 18)

FFFFH

FF7FH

FEFFH

097FH

0900H

08FFH

0000H

Figure 18-6. Sectors in User Program Mode

18-6


The Sector Erase Procedure in User Program Mode

1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.

2. Set Flash Memory Sector Address Register (FMSECH/FMSECL).

3. Set Flash Memory Control Register (FMCON) to “10100001B”.


Start

SB1

FMUSR #0A5H

FMSECH High Address of Sector

FMSECL Low Address of Sector

FMCON #10100001B

FMUSR #00H

SB0

Finish One Sector Erase

; Select Bank1

; User Programimg Mode Enable

; Set Sector Base Address

; Mode Select & Start Erase

; User Prgramming Mode Disable

; Select Bank0

Figure 18-7. Sector Erase Flowchart in User Program Mode

NOTES

1. If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL,

FMUSR should be enabled just before starting sector erase operation. And to erase a sector, Flash

Operation Start Bit of FMCON register is written from operation stop ‘0’ to operation start ‘1’. That bit will be cleared automatically just after the corresponding operation completed. In other words, when

S3F84MB is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase, it will get the result of erasing selected sector as user’s a purpose and Flash Operation Start Bit of FMCON register is also clear automatically.

2. If user executes sector erase operation with FMUSR disabled, FMCON.0 bit, Flash Operation Start

Bit, remains 'high', which means start operation, and is not cleared even though next instruction is executed. So user should be careful to set FMUSR when executing sector erase, for no effect on other flash sectors.

18-7


Programming Tip — Sector Erase

Case1. Erase one sector

.

LD FMUSR, #0A5H

LD FMSECH, #2

LD FMSECL, #00H

SB1

LD FMCON, #10100001B

SB0

LD FMUSR, #0

; User Program mode enable

; Set Sector 4 (200H-27FH)

; You can set FMSECL from 00H to 7FH.

; Start sector erase

; User Program mode disable

Case2.Erase flash memory space from Sector (n) to Sector (n + m)

•

•

;;Pre-define the number of sector to erase

LD

LD

LD

LD

SecNumH, #00H ; Set sector number

SecNumL, #128 ; Selection the sector128 ( base address 4000H )

R6, #01H

R7, #7DH

; Set the sector range (m) to erase

; into High-byte(R6) and Low-byte(R7)

LD

LD

ERASE_LOOP:

R2, SecNumH

R3, SecNumL

XOR P4, #11111111B

INCW RR2

; Display ERASE_LOOP cycle

LD SecNumL, R3

DECW RR6

LD R8, R6

OR R8, R7

CP R8, #00H

JP NZ, ERASE_LOOP

•

•

18-8


SECTOR_ERASE:

LD R12, SecNumH

LD R14, SecNumL

MULT RR12, #80H

MULT RR14, #80H

ADD R13, R14

NOCARRY:

LD

LD

R10, R13

R11, R15

ERASE_START:

; Calculation the base address of a target sector

; The size of one sector is 128-bytes

; BTJRF FLAGS.7,NOCARRY

; INC R12

LD FMUSR, #0A5H ; User program mode enable

LD FMSECH, R10 ; Set sector address

LD

SB1

FMSECL, R11

LD

SB0

FMCON, #10100001B ; Select erase mode enable & Start sector erase

ERASE_STOP:

LD FMUSR, #00H ; User program mode disable

LD

RET

PP, #00h

18-9


PROGRAMMING

A flash memory is programmed in one byte unit after sector erase.

And for programming safety's sake, must set FMSECH, FMSECL to flash memory sector value.

The write operation of programming starts by ‘LDC’ instruction.

The Program Procedure in User Program Mode

1. Must erase sector before programming.



4. Set Flash Memory Sector Address Register (FMSECH, FMSECL) to sector value of the address to write data.

5. Load a transmission data into a working register.

6. Load a flash memory upper address into upper register of pair working register.

7. Load a flash memory lower address into lower register of pair working register.

8. Load transmission data to flash memory location area on ‘LDC’ instruction by indirectly addressing mode


NOTE: In programming mode, it doesn’t care whether FMCON.0’s value is “0” or “1”.

18-10


Start

FMSECH High Address of Sector

FMSECL Low Address of Sector

R(n) High Address to Write

R(n+1) Low Address to Write

R(data) 8-bit Data

FMUSR #0A5H

FMCON #01010000B

LDC @RR(n),R(data)

FMUSR #00H

Finish 1-BYTE Writing

; Set Secotr Base Address

; Set Address and Data

; User Program Mode Enable

; Mode Select

; Write data at flash

; User Program Mode Disable

Figure 18-8. Byte Program Flowchart in a User Program Mode

18-11


Start

FMSECH

FMSECL

High Address of Sector

Low Address of Sector

R(n) High Address to Write

R(n+1) Low Address to Write

R(data) 8-bit Data

FMUSR #0A5H

FMCON #01010000B

LDC @RR(n),R(data)

NO

NO

Same Sector?

YES

Continuous address?

YES

Write again?

NO

FMUSR #00H

Finish Writing

YES

INC R(n+1)

YES

Different Data?

R(data) New 8-bit Data

NO

; Set Secotr Base Address

; Set Address and Data

; User Program Mode Enable

; Mode Select

; Write data at flash



;; Check Sector

;; Check Address

;; Increse Address

;; Update Data to Write

Figure 18-9. Program Flowchart in a User Program Mode

18-12


Programming Tip — Programming

Case1. 1BYTE Programming

•

•

WR_BYTE: ; Write data “AAH” to flash memory address 4010H

LD FMUSR, #0A5H

SB1


LD FMCON, #01010001B ; Programming mode enable

SB0

LD FMSECH, #40H

LD FMSECL, #00H

LD R9, #0AAH

LD R10, #40H

LD R11, #10H

; Set flash sector address

; Set sector address of pointer to write data

; Load data “AA” to write

; Load flash memory upper address into upper register of pair working

; register

; Load flash memory lower address into lower register of pair working

LDC @RR10, R9

SB1

; register

; Write data 'AAH' at flash memory location(4010H)

LD FMCON, #01010000B ; Programming stop

SB0

LD FMUSR, #00H ; User Program mode disable

Case2. Programming in the same sector

•

•

WR_INSECTOR:

LD R0, #40H

; RR10-->Address copy (R10 .high address,R11-low address)

LD FMUSR, #0A5H

LD FMSECH, #40H

LD FMSECL, #00H


; Set sector address located in target address to write data

; SECTOR128- sector base address 4000H

SB1

LD FMCON, #01010001B ; Programming mode enable

SB0

LD R9, #33H ; Load data “33H” to write

LD R10, #40H

LD R11, #40H

; Load flash memory upper address into upper register of pair working

; register

; Load flash memory lower address into lower register of pair working

; register

WR_BYTE:

LDC @RR10, R9

INC R11

; Write data '33H' at flash memory location

; Reset address in the same sector by INC instruction

DJNZ R0, WR_BYTE

SB1

; Check whether the end address for programming reach 407FH or not.

LD FMCON, #01010000B ; Programming stop

SB0

LD FMUSR, #00H ; User Program mode disable

18-13


Case3. Programming to the flash memory space located in other sectors

•

•

WR_INSECTOR2:

LD

LD

LD

SB1

LD

SB0

LD

LD

FMUSR, #0A5H

FMSECH, #01H

FMSECL, #00H

FMCON, #01010001B

R9, #0CCH

R10, #01H

R11, #40H LD

CALL WR_BYTE

LD R0, #40H

WR_INSECTOR50:

LD

LD

LD

LD

FMSECH, #19H

FMSECL, #00H

R9, # 55H

R10, #19H

LD R11, #40H

CALL WR_BYTE

WR_INSECTOR128:

LD

LD

LD

LD

FMSECL, #00H

R9, #0A3H

R10, #40H

R11, #40H

WR_BYTE1:

LDC @RR10, R9

INC R11

SB1

LD

SB0

FMCON, #01010000B



; SECTOR2- sector base address 100H

; Programming mode enable

; Load data “CCH” to write

; Load flash memory upper address into upper register of pair

; working register

; Load flash memory lower address into lower register of pair

; working register


; SECTOR50 –sector base address 1900H

; Load data “55H” to write


; working register


; working register


; SECTOR128 –sector base address 4000H

; Load data “A3H” to write


; working register


; working register

; Write data 'A3H' at flash memory location

; Programming stop

18-14


LD FMUSR, #00H

•

•

WR_BYTE:

LDC @RR10, R9

INC R11

RET

READING


; Write data written by R9 at flash memory location

The read operation starts by ‘LDC’ instruction.

The program procedure in user program mode

1. Load a flash memory upper address into upper register of pair working register.

2. Load a flash memory lower address into lower register of pair working register.

3. Load receive data from flash memory location area on ‘LDC’ instruction by indirectly addressing mode

LOOP:

PROGRAMMING TIP — Reading

•

•

LD R2, #03H ; Load flash memory’s upper address

; to upper register of pair working register

; Load flash memory’s lower address

; to lower register of pair working register

R0, @RR2 ; Read data from flash memory location

; (Between 300H and 3FFH)

R3

R3, #0FFH

•

•

•

•

LDC

INC

CP

18-15


HARD LOCK PROTECTION

User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area.

This protection can be released by the chip erase execution in the tool program mode. In terms of user program mode, the procedure of setting Hard Lock Protection is following that. In tool mode, the manufacturer of serial tool writer could support Hardware Protection. Please refer to the manual of serial program writer tool provided by the manufacturer.

The program procedure in user program mode




PROGRAMMING TIP — Hard Lock Protection

•

•

•

•

LD

SB1

LD

SB0

LD

FMUSR, #0A5H

FMCON, #01100001B

FMUSR, #0


; Hard Lock mode set & start


18-16


19

ELECTRICAL DATA

OVERVIEW

In this chapter, S3C84MB/F84MB electrical characteristics are presented in tables and graphs.

The information is arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— A.C. electrical characteristics

— Oscillation stabilization time

— Data retention supply voltage in stop mode

— A/D converter electrical characteristics

19-1

ELECTRICAL DATA S3C84MB/F84MB_UM_REV1.00

Table 19-1. Absolute Maximum Ratings

(T

A

= 25

°

C)

Parameter Symbol

Supply voltage

Input voltage

V

DD

V

I

Output voltage

Output current high

V

O

I

OH

Conditions

One I/O pin active

All I/O pins active

Output current low

Operating temperature

Storage temperature

I

OL

T

A

T

STG

One I/O pin active

Total pin current for port

Rating Unit

– 0.3 to +6.5

V – 0.3 to V

DD

+ 0.3

– 0.3 to V

DD

+ 0.3

– 15

– 60 mA

+30

+200

– 40 to + 85

– 65 to + 150

°C

Table 19-2. D.C. Electrical Characteristics

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.4 V to 5.5 V)

Parameter Symbol Conditions

Operating voltage V

DD f

OSC

= 10 MHz

Input high voltage

Input low voltage

V

IH1

V

IH2

V

IL1

V

IL2

All input pins except V

IH2

X

IN


IL2

X

IN

Min Typ Max Unit

2.4 – 5.5

0.8 V

V

DD

DD

–0.5

– V

V

DD

DD

DD

V

– 0.4

19-2


Table 19-2. D.C. Electrical Characteristics (Continued)

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.4 V to 5.5 V)


Output high voltage V

OH1

V

DD

= 5 V; I

OH

All output pins except

Port 0,2,6

= –1 mA

V

OH2

Output low voltage V

OL1

V

DD

= 5 V; I

OH

= –4 mA

Port 0,2

V

DD

= 5 V; I

OL

= 4 mA

All output pins except V

OL2

V

V

DD

DD

– 1.0

– 2.0

Input high leakage current

V

OL2

I

LIH1

V

DD

= 5 V; I

OL

= 16 mA

Port 0, 2, 6

V

IN

= V

DD

All input pins except I

LIH2

I

LIH2

– –

3

– –

20

V

Input low leakage current

Output high leakage current

Output low leakage current

Pull-up resistor

I

I

I

LIL1

V

R

R

IN

LOH

LOL

P1

P2

DD

X , X

OUT

V

IN

= 0 V


IN

V

IN

= 0 V

X

IN

, X

OUT

V

OUT

= V

DD

All I/O pins and Output pins

V

OUT

= 0 V

All I/O pins and Output pins

V = 0 V; V

Port 0–8, T

DD

A

= 5 V

±10 %

= 25

°

C

All Output Pin except

RESETB

V = 0 V; V

DD

= 3 V

±10 %

Port 0–8, T

A

= 25

°

C

All Output Pin except

RESETB

V = 0 V; V

Port 0–8, T

DD

A

= 5 V

±10 %

= 25

°

C

RESETB

V = 0 V; V

Port 0–8, T

DD

A

= 3 V

±10 %

= 25

°

C

RESETB

–3

– –

–20

μA k

Ω

19-3


Table 19-2. D.C. Electrical Characteristics (Concluded)

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.4 V to 5.5 V)


Supply current

(1)

V

DD

= 4.5 V to 5.5 V

16 MHz Run mode

I

DD1

V

DD

= 2.4 V to 5.5 V

10 MHz Run mode

V

DD

= 4.5 V to 5.5 V

16 MHz Idle mode

I

DD2

I

DD3

V

DD

= 2.4 V to 5.5 V

10 MHz Idle mode

V

DD

= 2.4 V to 5.5 V

STOP mode, LVR Enable

I

DD4

V

DD

= 2.4 V to 5.5 V

STOP mode, LVR Disable

–

10 20

7 14 mA

2.5 5

2 4

200 400

100 200

I

I

DD5

DD6

V

DD

= 2.4 V to 5.5 V

STOP mode, LVR Enable

IVC Disable

V

DD

= 2.4 V to 5.5 V

STOP mode, LVR Disable

IVC Disable

μA

100 200

10 20

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

19-4


Table 19-3. A.C. Electrical Characteristics

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.4 V to 5.5 V)

Parameter Symbol Conditions Min

External Interrupt Input

High Voltage

External Interrupt Input Low

Voltage

V

V

EIH

EIL

–

–

0.8 V

–

DD

–

–

V

DD

0.2 V

DD

External Interrupt Input

Width t

INTH t

INTL

V

DD

= 5 V 10 %

V

V

180 – – ns

RESET input low width t

RSL

V

DD

= 5 V

Figure 19-1. Input Timing for External Interrupts (Ports 4, Port 8.5, Port 8.6)

t

RSL

RESET

0.2 V

DD

Figure 19-2. Input Timing for RESET

19-5


Table 19-4. Input/Output Capacitance

(T

A

= –40

°

C to +85

°

C, V

DD

= 0 V )

Parameter Symbol Conditions Min Typ Max Unit

Input capacitance

Output capacitance

I/O capacitance

C

C

C

IN

OUT

IO f = 1 MHz; unmeasured pins are tied to V

SS

Table 19-5. Data Retention Supply Voltage in Stop Mode

(T

A

= –40

°

C to +85

°

C)

Parameter Symbol

Data retention supply voltage

V

DDDR

Conditions

Stop mode

Data retention supply current

I

DDDR

Stop mode , V

DDDR

= 2.4 V

Min Typ Max Unit

2.4 – 5.5

– – 8

V

μA

NOTE:

Supply current does not include current drawn through internal pull-up resistors or external output current loads.

V

DD

Interrupt

~ ~

~ ~

Execution of

STOP Instruction

Stop Mode

Data Retention Mode

V

DDDR

0.2V

DD

Oscillation

Stabilization Time

Idle Mode t

WAIT

Normal

Operating Mode

NOTE:

t

WAIT

is the same as 4096 x 16 x BT clock

Figure 19-3. Stop Mode Release Timing Initiated by Interrupts

19-6


Table 19-6. A/D Converter Electrical Characteristics

(T

A

= –40

°C to +85 °C, V = 2.4 V to 5.5 V, V = 0 V)


Resolution – – bit

Total accuracy

Integral Linearity Error

ILE

V

DD

AV

= 5.12 V

REF

= 5.12V

– –

±3

– –

±2

Differential Linearity

Error

Offset Error of Top

Offset Error of Bottom

Conversion time

(1)

DLE

EOT

EOB

AV

SS

= 0 V f

ADC

= 2.5 MHz

–

–

– –

–

–

±1

±0.5

1

0.5

±1

±3

±2

3

1.5

LSB

T

CON

Analog input voltage V

IAN

Analog input impedance R

AN

Analog reference voltage AV

REF

10-bit resolution

Max f

ADC

= 2.5MHz

20 – –

– AV

–

SS

μs

2 1000 – M

Analog ground

Analog input current

Analog block current

(2)

AV

SS

I

ADIN

I

ADC

AV

AV

REF

= V

DD

= 5V

AV

REF

= V

DD

= 3V

AV

REF

REF

= V

= V

DD

DD

– V

= 5V

= 5V When

Power Down mode

SS

–

– AV

REF

DD

V

Ω

V mA

NOTES:

1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.

2. I

ADC

is an operating current during A/D conversion.

Table 19-7. LVR(Low Voltage Reset) Circuit Characteristics

(T

A

= –40

°C to +85 °C, V = 2.4 V to 5.5 V)


Low Voltage Level

V

LVR

LVR is enabled

T

A

= 25

°

C by smart option

2.4 2.8 3.2

3.5

4.0

4.5

V

19-7


(T

A

= –40

°C to +85 °C, V = 2.4 V to 5.5 V, V = 0 V)


Logic power supply

Flash memory operating current

(F

DD

)

Table 19-8. Flash Memory D.C. Electrical Characteristics

V

DD

F

F

DD1

DD2

V

DD

= 2.4 V to 5.5 V during reading

V

DD

= 2.4 V to 5.5 V during programming

2.4 5.0 5.5 V

F

DD3

V

DD

= 2.4 V to 5.5 V during erasing

Table 19-9. Flash Memory A.C. Electrical Characteristics

(T

A

= –40

°C to +85 °C, V = 2.4 V to 5.5 V, V = 0 V)


Programming time

(1)

Ft

P

Chip Erasing time

(2)

Sector Erasing time

(3)

Ft

Ft

P1

P2

V

DD

= 2.4 V to 5.5 V

Data access time Ft

RS

Number of writing/erasing

Data Retention Time

Fn

WE

Ft

DR

20 30 50

μS

10 – – mS

10 – – mS

– 100 – nS

– 10,000

– 10 Years

NOTES:

1. The Programming time is the time during which one byte(8-bit) is programmed.

2. The chip erasing time is the time during which all 64K-byte block is erased.

3. The sector erasing time is the time during which one 128-byte block is erased.

19-8


(T

A

= –40

°C to +85 °C, V = 2.4 V to 5.5 V)

Oscillator

Table 19-10. Main Oscillator Frequency (f

OSC

)

Clock Circuit Test Condition Min

Crystal

X

IN

X

OUT

V

DD

= 2.4 V to 5.5 V

V

DD

= 4.5 V to 5.5 V

1

1

Ceramic

C1

X

IN

X

OUT

C2

V

DD

= 2.4 V to 5.5 V

V

DD

= 4.5 V to 5.5 V

1

1

External clock

C1

X

IN

X

OUT

C2

V

DD

= 2.4 V to 5.5 V

V

DD

= 4.5 V to 5.5 V

1

1

Typ

–

–

Max

10

16

Unit

MHz

–

–

–

–

10

16

10

16

Table 19-11. Main Oscillator Clock Stabilization Time (t

ST1

)

(T

A

= –40

°C to +85 °C, V = 2.4 V to 5.5 V)

Min Unit

Ceramic Stabilization occurs when V

DD

is equal to the minimum oscillator voltage range.

External clock X

IN

NOTE:

Oscillation stabilization time (t

ST1

) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. ms

– – 4

19-9

ELECTRICAL DATA

X

IN

1/f

OSC1


t

XL t

XH

V

DD

- 0.5 V

0.4 V

16MHz

Figure 19-4. Clock Timing Measurement at X

IN

10MHz

5MHz

1MHz

2 3 4 5

2.4V

4.5V

5.5V

Figure 19-5. Operating Voltage Range

19-10


20

Mechanical Data

OVERVIEW

23.90

± 0.30

20.00

± 0.20

0-8

0.15

+ 0.10

- 0.05

80-QFP-1420C

0.10 MAX

#80

0.80

#1

0.35

+ 0.10

0.15 MAX

(0.80)

0.05 MIN

2.65

± 0.10

3.00 MAX

0.80

± 0.20

NOTE: Dimensions are in millimeters.

Figure 20-1. S3C84MB/F84MB 80-QFP Standard Package Dimension (in Millimeters)

20–1

MECHANICAL DATA

14.00 BSC

12.00 BSC


0-7

0.09-0.20

80-TQFP-1212

#80

0.50

#1

0.17-0.27

0.08 MAX M

(1.25)

0.05-0.15

1.00

± 0.05

1.20 MAX

NOTE: Dimensions are in millimeters.

Figure 20-2. S3C84MB/F84MB 80-TQFP Standard Package Dimension (in Millimeters)

20–2

S3C84MB/F84MB_UM_REV1.00 S3F84MB FLASH MEMORY MCU

21

S3F84MB FLASH MCU

OVERVIEW

The S3F84MB single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM. The

Flash ROM is accessed by serial data format.

NOTE

This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User Program

Mode, refer to the Chapter 18. Embedded Flash Memory Interface.

21-1

S3F84MB FLASH MEMORY MCU S3C84MB/F84MB_UM_REV1.00

TAOUT/P2.7

TACAP/P2.6

TACK/P2.5

TBPWM/P2.4

P2.3

SCK0/P2.2

SI0/P2.1

SO0/P2.0

P5.7

SDAT/P5.6

SCLK/P5.5

VDD1

VSS1

X

OUT

X

IN

V

PP

/TEST

P5.4

RxD0/P5.3

RESETB

TxD0/P5.2

RxD1/P5.1

TxD1/P5.0

TCOUT1/P3.7

TCOUT0/P3.6

14

15

16

17

18

9

10

11

12

13

5

6

7

8

1

2

3

4

19

20

21

22

23

24

S3C84MB/F84MB

(80-QFP-1420C)

51

50

49

48

47

56

55

54

53

52

60

59

58

57

64

63

62

61

46

45

44

43

42

41

P8.0/SO1

P8.1/SI1

P8.2/SCK1

P8.3

P8.4/INT8

P8.5/INT9

P6.0/ADC8

P6.1/ADC9

P6.2/ADC10

P6.3/ADC11

P6.4/ADC12

VDD2

VSS2

P6.5/ADC13

P6.6/ADC14

P6.7

P7.0/ADC0

P7.1/ADC1

P7.2/ADC2

P7.3/ADC3

AVSS

AVREF

P7.4/ADC4

P7.5/ADC5

Figure 21-1. S3F84MB Pin Assignments (80-QFP)

21-2


TACK/P2.5

TBPWM/P2.4

P2.3

SCK0/P2.2

SI0/P2.1

SO0/P2.0

P5.7

SDAT/P5.6

SCLK/P5.5

VDD1

VSS1

X

OUT

X

IN

V

PP

/TEST

P5.4

RxD0/P5.3

RESETB

TxD0/P5.2

RxD1/P5.1

TxD1/P5.0

11

12

13

14

15

16

17

18

19

20

6

7

8

9

10

3

4

5

1

2

S3C84MB/F84MB

(80-TQFP-1212)

50

49

48

47

46

45

44

43

42

41

55

54

53

52

51

60

59

58

57

56

P8.2/SCK1

P8.3

P8.4/INT8

P8.5/INT9

P6.0/ADC8

P6.1/ADC9

P6.2/ADC10

P6.3/ADC11

P6.4/ADC12

VDD2

VSS2

P6.5/ADC13

P6.6/ADC14

P6.7

P7.0/ADC0

P7.1/ADC1

P7.2/ADC2

P7.3/ADC3

AVSS

AVREF

Figure 21-2. S3F84MB Pin Assignments (80-TQFP)

21-3

S3F84MB FLASH MEMORY MCU S3C84MB/F84MB_UM_REV1.00

Main Chip

Pin Name

Table 21-1. Descriptions of Pins Used to Read/Write the Flash ROM

Pin Name Pin No. I/O

During Programming

Function

Serial data pin. Output port when reading and input an Input/push-pull output port.

TEST V

PP

RESETB RESETB 19(17)

V

DD

, V

SS

V

DD

, V

SS

12, 13

(10, 11)

Tool mode selection when TEST pin sets Logic value

‘1’. If user uses the flash writer tool mode (ex.spw2+ etc.), user should connect TEST pin to V

DD

.

(S3F84MB supplies high voltage 12.5V by internal high voltage generation circuit.)

I

Chip Initialization.

–

NOTE: Parentheses indicate pin number for 80-TQFP package.

Power supply pin for logic circuit. V

DD

should be tied to +3.3V during programming.

Test Pin Voltage

The TEST pin on socket board for OTP/MTP writer must be connected to V

DD

(3.3V). The TEST pin on socket board must not be connected V

PP

(12.5V) which is generated from OTP/MTP Writer. So the specific socket board for S3F84MB must be used, when writing or erasing using OTP/MTP writer.

21-4


OPERATING MODE CHARACTERISTICS

When logical high is supplied to the V

PP

(TEST) pin of the S3F84MB, the Flash ROM programming mode is entered.

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 21-2 below.

V

DD

V

PP

Table 21-2. Operating Mode Selection Criteria

(TEST) REG/nMEM

3.3V 3.3V

0

0

0

1

Address

(A15–A0)

0000H

0000H

0000H

0E3FH

R/W

(note)

1

0

1

0

Mode

Flash ROM Read

Flash ROM Program

Flash ROM Verify

Flash ROM Read Protection

NOTE: "0" means Low level; "1" means High level.

21-5

22

DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500 and SK-

1200, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options.

TARGET BOARDS

Target boards are available for all S3C8/S3F8-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. TB84MB is a specific target board for the development of application systems using S3F84MB

PROGRAMMING SOCKET ADAPTER

When you program S3F84MB’s flash memory by using an emulator or OTP/MTP writer, you need a specific programming socket adapter for S3F84MB.

22-1

DEVELOPMENT TOOLS S3C84MB/F84MB_UM_REV1.00

IBM-PC AT or Compatible

RS-232C/USB

Emulator (SK-1200 or OPENIce-i500)

PROM/OTP Writer Unit

Target

Application

System

RAM Break/Display Unit

Probe

Adapter

Trace/Timer Unit

SAM8 Base Unit

POD

TB84MB

Target

Board

EVA

Chip

Power Supply Unit

Figure 22-1. Development System Configuration

22-2


TB84MB TARGET BOARD

The TB84MB target board is used for the S3C84MB/F84MB microcontroller. It is supported by the SMDS2,

SMDS2+, SK-820, or SK-1000 development system.

Off

To User_V

CC

On

RESET

TB84MB

Idle Stop

74HC11

1

J101

2 1

J102

2

25

CN1

160 QFP

S3E84M0

EVA Chip

1 39 40 39 40

External Triggers

CH1

CH2

SMDS2

JP4

SMDS2+

Figure 22-2. TB84MB Target Board Configuration

22-3


Table 22-1. Power Selection Settings for TB84MB

"To User_V

CC

"

Settings

Operating Mode

TB84MB

V

CC

V

SS

Target

System

Comments

The ICE (SK-1200/OPENIce ) supplies V

CC

to the target board (evaluation chip) and the target system.

To User_V

CC

Off On

SK-1200/OPENIce

To User_V

CC

Off On

TB84MB

External

V

CC

V

SS

Target

System

The ICE (SK-1200/OPENIce ) supplies V

CC

only to the target board (evaluation chip). The target system must have its own power supply.

SK-1200/OPENIce

JP4 Settings

SMDS2

Table 22-2. Emulator Version Selection Settings for TB84MB

Emulator Version

SK–1200, OPENIce i500, SMDS2+

Comments

Default Setting

SMDS2+

JP4

SMDS

SMDS2

JP4

SMDS2+

22-4


Table 22-3. Using Single Header Pins as the Input Path for External Trigger Sources

Target Board Part Comments

External

Triggers

Ch1

Ch2

Connector from

External Trigger

Sources of the

Application System

You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) only for the SMDS2+ breakpoint and trace functions.

IDLE LED

The Green LED is ON when the evaluation chip (S3E84MB) is in idle mode.

STOP LED

The Red LED is ON when the evaluation chip (S3E84MB) is in stop mode.

22-5


TAOUT/P2.7

TACK/P2.5

P2.3

SI0/P2.1

P5.7

P5.5

V

SS1

N.C

P5.4

RESETB

RxD1/P5.1

TCOUT1/P3.7

T1OUT1/P3.5

T1CAP1/P3.3

T1CK1/P3.1

INT7/P4.7

INT5/P4.5

INT3/P4.3

INT1/P4.1

ADC7/P7.7

J101

22

24

26

28

12

14

16

18

20

2

8

10

4

6

30

32

34

36

38

40

29

31

33

35

19

21

23

25

27

37

39

11

13

15

17

5

7

1

3

9

P2.6/TACAP

P2.4/TBPWM

P2.2/SCK0

P2.0/SO0

P5.6

VDD1

N.C

N.C(TEST)

P5.3/RxD0

P5.2/TxD0

P5.0/TxD1

P3.6/TCOUT0

P3.4/T1OUT0

P3.2/T1CAP0

P3.0/T1CK0

P4.6/INT6

P4.4/INT4

P4.2/INT2

P4.0/INT0

P7.6/ADC6

ADC5/P7.5

AV

REF

ADC3/P7.3

ADC1/P7.1

P6.7

ADC13/P6.5

V

DD2

ADC11/P6.3

ADC9/P6.1

INT9/P8.5

P8.3

SI1/P8.1

PWM3/P1.7

PWM1/P1.5

P1.3

RxD2/P1.1

PG7/P0.7

PG5/P0.5

PG3/P0.3

PG1/P0.1

29

31

33

35

19

21

23

25

27

37

39

11

13

15

17

5

7

1

3

9

J102

22

24

26

28

12

14

16

18

20

2

8

10

4

6

30

32

34

36

38

40

N.C : Not connected

Figure 22-3. 40-Pin Connectors for TB84MB (S3C84MB/F84MB, 80-QFP Package)

Target Board

1

J101

2

J102

41 42

Target System

J102 J101

41 42 1 2

Target Cable for 40-Pin

Connector

Part Name: AS40D-A

Order Code: SM6306

39 40 79 80 79 80 39 40

Figure 22-4. TB84MB Cable for 80-QFP Adapter

P7.4/ADC4

AV

SS

P7.2/ADC2

P7.0/ADC0

P6.6/ADC14

V

SS2

P6.4/ADC12

P6.2/ADC10

P6.0/ADC8

P8.4/INT8

P8.2/SCK1

P8.0/SO1

P1.6/PWM2

P1.4/PWM0

P1.2

P1.0/TxD2

P0.6/PG6

P0.4/PG4

P0.2/PG2

P0.0/PG0

22-6


22.2 Third parties for development tools

SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an

OTP/MTP programmer.

In-Circuit Emulator for SAM8 family

— OPENice-i500

— SmartKit

OTP/MTP Programmer

— SPW-uni

— AS-pro

— US-pro

— BlueChips-Combi

— GW-PRO2 (8 - gang programmer)

Development Tools Suppliers

Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools.

8-bit In-Circuit Emulator

OPENice - i500

AIJI System

• TEL: 82-31-223-6611

• FAX: 82-331-223-6613

• E-mail : [email protected]

• URL : http://www.aijisystem.com

SK-1200

Seminix

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819

• E-mail: [email protected]

• URL: http://www.seminix.com

22-7


OTP/MTP PROGRAMMER (WRITER)

SPW-uni

Single OTP/ MTP/FLASH Programmer

• Download/Upload and data edit function

• PC-based operation with USB port

• Full function regarding OTP/MTP/FLASH MCU

programmer

(Read, Program, Verify, Blank, Protection..)

• Fast programming speed (4Kbyte/sec)

• Support all of SAMSUNG OTP/MTP/FLASH MCU

devices

• Low-cost

• NOR Flash memory (SST,Samsung…)

• NAND Flash memory (SLC)

• New devices will be supported just by adding

device files or upgrading the software.

AS-pro

On-board programmer for Samsung Flash MCU

• Portable & Stand alone Samsung

OTP/MTP/FLASH Programmer for After Service

• Small size and Light for the portable use

• Support all of SAMSUNG OTP/MTP/FLASH

devices

• HEX file download via USB port from PC

• Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

• Internal large buffer memory (118M Bytes)

• Driver software run under various O/S

(Windows 95/98/2000/XP)

• Full function regarding OTP/MTP programmer


• Two kind of Power Supplies

(User system power or USB power adapter)

• Support Firmware upgrade

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.


• URL:

http://www.seminix.com

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.


• URL:


US-pro

Portable Samsung OTP/MTP/FLASH Programmer

• Portable Samsung OTP/MTP/FLASH Programmer

• Small size and Light for the portable use

• Support all of SAMSUNG OTP/MTP/FLASH

devices

• Convenient USB connection to any IBM compatible

PC or Laptop computers.

• Operated by USB power of PC

• PC-based menu-drive software for simple operation

• Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.


• URL:


22-8


• Support Samsung standard Hex or Intel Hex format

• Driver software run under various O/S

(Windows 95/98/2000/XP)

• Full function regarding OTP/MTP programmer


• Support Firmware upgrade

BlueChips-Combi

BlueChips-combi is a programmer for all Samsung

MCU. It can program not only all Samsung OTP/MTP

(Flash) MCU but also the popular E(E)PROMs. New devices will be supported just by adding device files or upgrading the software. It is connected to host

PC’s serial port and controlled by the software.

AIJI System

• TEL: 82-31-223-6611

• FAX: 82-31-223-6613

• E-mail :

[email protected]

• URL : http://www.aijisystem.com

GW-PRO2

Gang Programmer for OTP/MTP/FLASH MCU

• 8 devices programming at one time

• Fast programming speed (1.2Kbyte/sec)

• PC-based control operation mode or Stand-alone

• Full Function regarding OTP/MTP program

(Read, Program, Verify, Protection, Blank..)

• Data back-up even at power break

After setup in Design Lab, it can be moved to the

factory site.

• Key Lock protecting operator's mistake

• Good/Fail quantity displayed and memorized

• Buzzer sounds after programming

• User friendly single-menu operation (PC)

• Operation status displayed in LCD panel

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.


• URL:


22-9