DSP56F803, 56F803 - Data Sheet
Freescale Semiconductor, Inc.
Datasheet: Technical Data
Document Number: DSP56F803
Rev. 17, 10/2015
56F803 Datasheet with Addendum
Rev.17
of the 56F803 Datasheet has two parts:
• The addendum to revision 16 of the datasheet, immediately following this cover page.
• Revision 16 of the datasheet, following the addendum. The changes described in the addendum have not been implemented in the specified pages.
© 2015 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor, Inc.
Datasheet Addendum
Document Number: DSP56F803AD
Rev. 0, 10/2015
Addendum to Rev.
16 of the 56F803 datasheet
This addendum identifies changes to Rev.16
of the 56F803 datasheet. The changes described in this addendum have not been implemented in the specified pages.
1 Update the incomplete Thermal Design
Considerations section
Location:
Thermal Considerations section in 56F803 datasheet Rev.16 is incomplete. The complete Thermal
Design Consideration section should be as follows:
An estimation of the chip junction temperature, T
J
, in °C can be obtained from the equation:
T
J
= T
A
+ (P
D
x R
JA
)
Eqn. 1
where:
T
A
= ambient temperature °C
R
JA
= package junction-to-ambient thermal resistance °C/W
P
D
= power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
R
JA
= R
JC
+ R
CA
Eqn. 2
© 2015 Freescale Semiconductor, Inc. All rights reserved.
Update the incomplete Thermal Design Considerations section
where
R
JA
= package junction-to-ambient thermal resistance °C/W
R
JC
= package junction-to-case thermal resistance °C/W
R
CA
= package case-to-ambient thermal resistance °C/W
R
JC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance,R
CA
. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from R
JA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate.
Definitions
A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (T
J
– T
T
)/P
D
where T
T
is the temperature of the package case determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at theinterface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the
Freescale Semiconductor, Inc.
Addendum to Rev.16 of 56F803 Technical Data, Rev. 0, 10/2015
3
4
Add missing Electrical Design Considerations section
interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
2 Add missing
Electrical Design Considerations section
Location:
Section 5.2, Page 52
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct DSP operation:
• Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place six 0.01–0.1 mF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the seven VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors must be 150 milliohm or less ESR capacitors.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS (GND) pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS .
• Bypass the VDD and VSS layers of the PCB with approximately 100 mF, preferably with a highgrade capacitor such as a tantalum capacitor.
• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal
3 Add missing Ordering part section
Location:
Section 6, Page 53
lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 1. 56F803 Ordering Information
Part
56F803
Supply
Voltage
Package Type
3.0–3.6 V Low Profile Plastic Quad Flat
Pack (LQFP)
Pin Count
Ambient
Frequency
(MHz)
100 80
Order Number
DSP56F803BU80
Addendum to Rev.16 of 56F803 Technical Data, Rev. 0, 10/2015
Freescale Semiconductor, Inc.
Part
Supply
Voltage
Add missing Ordering part section
Table 1. 56F803 Ordering Information
Package Type Pin Count
Ambient
Frequency
(MHz)
Order Number
100 80 DSP56F803BU80E
1
56F803 3.0–3.6 V Low Profile Plastic Quad Flat
Pack (LQFP)
1
This package is RoHS compliant
Freescale Semiconductor, Inc.
Addendum to Rev.16 of 56F803 Technical Data, Rev. 0, 10/2015
5
56F803
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F803
Rev. 16
09/2007
freescale.com
Version History
Rev. 16
Document Revision History
Description of Change
Added revision history.
Added this text to footnote 2 in
: “However, the high pulse width does not have to
be any particular percent of the low pulse width.”
56F803 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes
• 31.5K
× 16-bit words (64KB) Program Flash
• 512
× 16-bit words (1KB) Program RAM
• 4K
× 16-bit words (8KB) Data Flash
• 2K
× 16-bit words (4KB) Data RAM
• 2K
× 16-bit words (4KB) Boot Flash
• Up to 64K
× 16-bit words each of external Program and Data memory
• 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Quadrature Decoder
• CAN 2.0 B module
• Serial Communication Interface (SCI)
• Serial Peripheral Interface (SPI)
• Up to two General Purpose Quad Timers
• JTAG/OnCE
TM
port for debugging
• 16 shared GPIO lines
• 100–pin LQFP package
3
3
6
PWM Outputs
Current Sense Inputs
Fault Inputs
PWMA
Quad Timer B
Quad Timer C
Quad Timer D
CAN 2.0A/B
SCI or
GPIO
SPI or
GPIO
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
COP/
Watchdog
Application-Specific
Memory &
Peripherals
EXTBOOT
RESET
IRQA
IRQB
6
JTAG/
OnCE
Port
VCAPC V
DD
2 6
V
SS
6*
V
DDA
V
SSA
Digital Reg Analog Reg
Low Voltage
Supervisor
4
4
4
2
2
2
4
A/D1
A/D2 ADC
VREF
Quadrature
Decoder 0 /
Quad Timer A
Interrupt
Controller
Program Controller and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→ 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
•
•
PAB
PDB
•
•
XDB2
CGDB
XAB1
XAB2
•
•
INTERRUPT
CONTROLS
16
•
IPBB
CONTROLS
16
•
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
CLKO
XTAL
EXTAL
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
6
10
16
A[00:05]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
PS Select
DS Select
WR Enable
RD Enable
56F803 Block Diagram
* includes TCS pin which is reserved for factory use and is tied to VSS
56F803 Technical Data, Rev. 16
Freescale Semiconductor 3
4
Part 1 Overview
1.1 56F803 Features
1.1.1
Processing Core
• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16
× 16
bit parallel Multiplier-Accumulator (MAC)
• Two 36
bit accumulators, including extension bits
• 16
bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2
Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
— 31.5K
× 16-bit words of Program Flash
— 512K
× 16
bit words of Program RAM
— 4K
× 16
bit words of Data Flash
— 2K
× 16
bit words of Data RAM
— 2K
× 16
bit words of Boot Flash
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
× 16 bits of Data memory
— As much as 64K
× 16 bits of Program memory
1.1.3
Peripheral Circuits for 56F803
• Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes, supports Freescale’s patented dead time distortion correction
• Two 12
bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and
PWM modules can be synchronized
• Quadrature Decoder with four inputs (shares pins with Quad Timer)
56F803 Technical Data, Rev. 16
Freescale Semiconductor
56F803 Description
• Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins
• CAN 2.0 B module with 2-pin ports for transmit and receive
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
• Computer Operating Properly (COP) Watchdog timer
• Two dedicated external interrupt pins
• Sixteen multiplexed General Purpose I/O (GPIO) pins
• External reset input pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
Energy Information
• Fabricated in high-density CMOS with 5V
tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F803 Description
The 56F803 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact device and control code.
The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.
The 56F803 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory.
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
56F803 Technical Data, Rev. 16
Freescale Semiconductor 5
6 software routines that can be used to program the main Program and Data Flash memory areas. Both
Program and Data Flash memories can be independently bulk
– erased or erased in page sizes of 256 words.
The Boot Flash memory can also be either bulk- or page
erased.
A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal outputs
(the module is also capable of supporting three independent PWM functions, for a total of six PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both
BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance
Motors), and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters and patented PWM waveform distortion correction circuit are also provided. The PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM module provides a reference output to synchronize the ADC.
The 56F803 incorporates a separate Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include a Serial
Communications Interface (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller are also included on the 56F803.
1.3 State of the Art Development Environment
• Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Product Documentation
1.4 Product Documentation
The four documents listed in
are required for a complete description and proper design with the
56F803. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: www.freescale.com
Topic
56800E
Family Manual
DSP56F801/803/805/807
User’s Manual
56F803
Technical Data Sheet
56F803
Errata
Table 1-1 56F803 Chip Documentation
Description
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
Detailed description of memory, peripherals, and interfaces of the 56F801, 56F803, 56F803, and 56F807
Electrical and timing specifications, pin descriptions, and package descriptions (this document)
Details any chip issues that might be present
Order Number
56800EFM
DSP56F801-7UM
DSP56F803
DSP56F803E
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
Examples:
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Signal/Symbol Logic State Signal State
Voltage
1
PIN
PIN
PIN
PIN
True
False
True
False
Asserted
Deasserted
Asserted
Deasserted
1.
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Freescale Semiconductor
56F803 Technical Data, Rev. 16
7
8
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F803 are organized into functional groups, as shown in
, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power (V
DD
or V
DDA
)
Ground (V
SS
or V
SSA
)
Supply Capacitors
PLL and Clock
Address Bus
1
Data Bus
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Port
Serial Peripheral Interface (SPI) Port
1
Quadrature Decoder Port
2
Serial Communications Interface (SCI) Port
1
CAN Port
Analog to Digital Converter (ADC) Port
Quad Timer Module Port
JTAG/On-Chip Emulation (OnCE)
1.
Alternately, GPIO pins
2.
Alternately, Quad Timer pins
4
2
2
9
2
6
Number of
Pins
7
7
2
3
16
16
4
4
12
4
Detailed
Description
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Introduction
Power Port
Ground Port
Power Port
Ground Port
Other
Supply
Ports
PLL and
Clock
External
Address Bus or
GPIO
External
Data Bus
External
Bus Control
Quadrature
Decoder or
Quad Timer A
V
DD
V
SS
V
DDA
V
SSA
VCAPC
1
1
6
6*
2
6
3
3
PWMA0-5
ISA0-2
FAULTA0-2
EXTAL
XTAL
CLKO
A0-A5
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
D0–D15
PHASEA0 (TA0)
PHASEB0 (TA1)
INDEX0 (TA2)
HOME0 (TA3)
PS
DS
RD
WR
1
1
1
1
1
1
1
1
6
2
8
1
1
1
16
56F803
1
1
1
1
SCLK (GPIOE4)
MOSI (GPIOE5)
MISO (GPIOE6)
SS (GPIOE7)
1
1
TXD0 (GPIOE0)
RXD0 (GPIOE1)
8
1
ANA0-7
VREF
1
1
MSCAN_RX
MSCAN_TX
PWMA
Port
SPI Port or GPIO
SCI0 Port or GPIO
ADCA
Port
CAN
TD1-2
2
JTAG/OnCE
™
Port
TCK
TMS
TDI
TDO
TRST
DE
1
1
1
1
1
1
1
1
1
1
IRQA
IRQB
RESET
EXTBOOT
* includes TCS pin which is reserved for factory use and is tied to VSS
Figure 2-1 56F803 Signals Identified by Functional Group
1
1. Alternate pin functionality is shown in parenthesis.
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Quad
Timer D
Interrupt/
Program
Control
9
2.2 Power and Ground Signals
No. of Pins
6
1
Signal Name
V
DD
V
DDA
Table 2-2 Power Inputs
Signal Description
Power—These pins provide power to the internal structures of the chip, and should all be attached to V
DD.
Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply.
No. of Pins
5
1
1
Signal Name
V
SS
V
SSA
TCS
Table 2-3 Grounds
Signal Description
GND—These pins provide grounding for the internal structures of the chip, and should all be attached to V
SS.
Analog Ground—This pin supplies an analog ground.
TCS—This Schmitt pin is reserved for factory use and must be tied to V
SS
for normal use.
In block diagrams, this pin is considered an additional V
SS.
No. of
Pins
Signal
Name
Signal
Type
2 VCAPC Supply
Table 2-4 Supply Capacitors
State During
Reset
Signal Description
Supply VCAPC—Connect each pin to a 2.2
μF or greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, please refer to
Section 5.2
.
10
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Clock and Phase Locked Loop Signals
2.3 Clock and Phase Locked Loop Signals
No. of
Pins
1
Signal
Name
EXTAL
1
1
XTAL
CLKO
Signal
Type
Input
Input/
Output
Output
Table 2-5 PLL and Clock
State During
Reset
Input
Signal Description
Chip-driven
External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information,
.
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
.
Chip-driven
This pin can also be connected to an external clock source. For more
Clock Output—This pin outputs a buffered clock signal. By programming the CLKOSEL[4:0] bits in the CLKO Select Register
(CLKOSR), the user can select between outputting a version of the signal applied to XTAL and a version of the device’s master clock at the output of the PLL. The clock frequency on this pin can also be disabled by programming the CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
No. of
Pins
6
2
8
Signal
Name
A0–A5
A6–A7
Signal
Type
Output
GPIOE2
–
GPIOE3
Input/O utput
A8–A15
Output
Output
GPIOA0
–
GPIOA7
Input/O utput
Table 2-6 Address Bus Signals
State During
Reset
Tri-stated
Tri-stated
Signal Description
Address Bus—A0–A5 specify the address for external Program or Data memory accesses.
Address Bus—A6–A7 specify the address for external Program or Data memory accesses.
Input
Tri-stated
Input
Port E GPIO—These two pins are General Purpose I/O (GPIO) pins that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight pins are General Purpose I/O (GPIO) pins that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
56F803 Technical Data, Rev. 16
Freescale Semiconductor 11
No. of
Pins
16
Signal
Name
D0–D15
Signal
Type
Input/O utput
Table 2-7 Data Bus Signals
State During
Reset
Tri-stated
Signal Description
Data Bus— D0–D15 specify the data for external Program or Data memory accesses. D0–D15 are tri-stated when the external bus is inactive. Internal pull-ups may be active.
No. of
Pins
1
Signal
Name
PS
1
1
1
DS
WR
RD
Signal
Type
Output
Output
Output
Output
Table 2-8 Bus Control Signals
State During
Reset
Tri-stated
Signal Description
Tri-stated
Tri-stated
Tri-stated
Program Memory Select—PS is asserted low for external Program memory access.
Data Memory Select—DS is asserted low for external Data memory access.
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0–A15, PS, and
DS pins. WR can be connected directly to the WE pin of a Static RAM.
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the device data bus. When RD is deasserted high, the external data is latched inside the controller. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
2.5 Interrupt and Program Control Signals
No. of
Pins
1
Signal
Name
IRQA
1
IRQB
Table 2-9 Interrupt and Program Control Signals
Signal
Type
Input
(Schmitt)
Input
(Schmitt)
State During
Reset
Input
Input
Signal Description
External Interrupt Request A—The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered.
External Interrupt Request B—The IRQB input is an external interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or negative-edge-triggered.
56F803 Technical Data, Rev. 16
12 Freescale Semiconductor
Pulse Width Modulator (PWM) Signals
No. of
Pins
1
1
Table 2-9 Interrupt and Program Control Signals (Continued)
Signal
Name
RESET
Signal
Type
Input
(Schmitt)
State During
Reset
Input
Signal Description
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks.
EXTBOOT
Input
(Schmitt)
Input
To ensure a complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
External Boot—This input is tied to V
DD to force device to boot from off-chip memory. Otherwise, it is tied to V
SS
.
2.6 Pulse Width Modulator (PWM) Signals
No. of
Pins
6
3
3
Signal
Name
Table 2-10 Pulse Width Modulator (PWMA) Signals
Signal
Type
PWMA0
–
5
ISA0
–
2
Output
Input
(Schmitt)
FAULTA0
–
2
Input
(Schmitt)
State During
Reset
Tri-stated
Input
Input
Signal Description
PWMA0
–
5— These are six PWMA output pins.
ISA0
–
2— These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA.
FAULTA0
–
2— These three fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip.
Freescale Semiconductor
56F803 Technical Data, Rev. 16
13
2.7 Serial Peripheral Interface (SPI) Signals
No. of
Pins
1
1
1
1
Signal
Name
MISO
GPIOE6
MOSI
GPIOE5
SCLK
GPIOE4
SS
GPIOE7
Table 2-11 Serial Peripheral Interface (SPI) Signals
Signal
Type
Input/Out put
State During
Reset
Input
Signal Description
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high impedance state if the slave device is not selected.
Input/Out put
Input
Input/Out put
Input/Out put
Input/Out put
Input/Out put
Input
Input/Out put
Input
Input
Input
Input
Input
Input
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin.
After reset, the default state is MISO.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data.
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin.
After reset, the default state is MOSI.
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin.
After reset, the default state is SCLK.
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin.
After reset, the default state is SS.
14
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Quadrature Decoder Signals
2.8 Quadrature Decoder Signals
No. of
Pins
1
Signal
Name
PHASEA0
Table 2-12 Quadrature Decoder (Quad Dec0) Signals
Signal
Type
Input
State During
Reset
Input
Signal Description
Phase A—Quadrature Decoder #0 PHASEA input
1
1
1
TA0
PHASEB0
TA1
INDEX0
TA2
HOME0
TA3
Input/Output
Input
Input/Output
Input
Input/Output
Input
Input/Output
Input
Input
Input
Input
Input
Input
Input
TA0—Timer A Channel 0
Phase B—Quadrature Decoder #0 PHASEB input
TA1—Timer A Channel 1
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
Home—Quadrature Decoder #0 HOME input
TA3—Timer A Channel 3
2.9 Serial Communications Interface (SCI) Signals
No. of
Pins
1
1
Signal
Name
TXD0
Table 2-13 Serial Communications Interface (SCI0) Signals
Signal Type
Output
State During
Reset
Input
Signal Description
Transmit Data (TXD0)—SCI0 transmit data output
GPIOE0
Input/Output Input
RXD0
GPIOE1
Input
Input/Output
Input
Input
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin.
After reset, the default state is SCI output.
Receive Data (RXD0)— SCI0 receive data input
Port E GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin.
After reset, the default state is SCI input.
Freescale Semiconductor
56F803 Technical Data, Rev. 16
15
2.10 CAN Signals
No. of
Pins
1
Signal
Name
MSCAN_ RX
1
MSCAN_ TX
Signal
Type
Input
(Schmitt)
Output
Table 2-14 CAN Module Signals
State During
Reset
Input
Signal Description
Output
MSCAN Receive Data—This is the MSCAN input. This pin has an internal pull-up resistor.
MSCAN Transmit Data—MSCAN output. CAN output is open-drain output and a pull-up resistor is needed.
2.11 Analog-to-Digital Converter (ADC) Signals
No. of
Pins
4
4
1
Signal
Name
ANA0
–
3
ANA4
–
7
VREF
Table 2-15 Analog to Digital Converter Signals
Signal
Type
Input
Input
Input
State During
Reset
Input
Input
Input
Signal Description
ANA0
–
3—Analog inputs to ADC channel 1
ANA4
–
7—Analog inputs to ADC channel 2
VREF—Analog reference voltage for ADC. Must be set to V
DDA
-0.3V for optimal performance.
2.12 Quad Timer Module Signals
No. of Pins
2
Signal Name
TD1
–
2
Table 2-16 Quad Timer Module Signals
Signal Type
Input/Output
State During Reset
Input
Signal Description
TD1
–
2— Timer D Channel 1
–
2
16
56F803 Technical Data, Rev. 16
Freescale Semiconductor
JTAG/OnCE
2.13 JTAG/OnCE
Table 2-17 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
1
1
Signal
Name
TCK
TMS
Signal
Type
State During
Reset
Signal Description
Input
(Schmitt)
Input, pulled low internally
Test Clock Input—This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor.
Input
(Schmitt)
Input, pulled high internally
Test Mode Select Input—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
1
1
1
TDI
TDO
TRST
Input
(Schmitt)
Output
Input
(Schmitt)
Input, pulled high internally
Tri-stated
Input, pulled high internally
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
Test Data Output—This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted at power-up and whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
1
DE
Output Output
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a debugging environment, TRST may be tied to V
SS
through a 1K resistor.
Debug Event—DE provides a low pulse on recognized debug events.
Part 3 Specifications
3.1 General Characteristics
The 56F803 is fabricated in high-density CMOS with 5-V tolerant TTL-compatible digital inputs. The term “5-V tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
56F803 Technical Data, Rev. 16
Freescale Semiconductor 17
Absolute maximum ratings given in
are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device.
The 56F803 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic
Supply voltage
All other input voltages, excluding Analog inputs
Voltage difference V
DD to V
DDA
Voltage difference V
SS to V
SSA
Analog inputs ANA0-7 and VREF
Analog inputs EXTAL and XTAL
Current drain per pin excluding V
DD
, V
SS
, PWM outputs, TCS,
V
PP
, V
DDA
, V
SSA
Symbol
V
DD
V
IN
ΔV
DD
ΔV
SS
V
IN
V
IN
I
Min Max
V
SS
– 0.3
V
SS
+ 4.0
V
SS
– 0.3
V
SS
+ 5.5V
- 0.3
0.3
- 0.3
V
SSA
– 0.3
V
SSA
– 0.3
—
0.3
V
DDA
+ 0.3
V
SSA
+ 3.0
10
Unit
V
V mA
V
V
V
V
Table 3-2 Recommended Operating Conditions
Characteristic
Supply voltage, digital
Supply Voltage, analog
Voltage difference V
DD to V
DDA
Symbol
V
DD
V
DDA
ΔV
DD
Min
3.0
3.0
-0.1
Typ
3.3
3.3
-
Max
3.6
3.6
0.1
Unit
V
V
V
56F803 Technical Data, Rev. 16
18 Freescale Semiconductor
Table 3-2 Recommended Operating Conditions
Characteristic
Voltage difference V
SS to V
SSA
ADC reference voltage
Ambient operating temperature
Symbol
ΔV
SS
VREF
T
A
Min
-0.1
2.7
–40
Typ
-
–
–
Max
0.1
V
DDA
85
General Characteristics
Unit
V
V
°C
Characteristic
Table 3-3 Thermal Characteristics
6
Comments
Symbol
Value
100-pin LQFP
R
θJA
41.7
Unit Notes
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)
Junction to case
Junction to center of case
I/O pin power dissipation
Power dissipation
Junction to center of case
Four layer board (2s2p)
Four layer board (2s2p)
°C/W
R
θJMA
R
θJMA
(2s2p)
R
θJMA
R
θJC
Ψ
JT
P
I/O
P
D
P
DMAX
37.2
34.2
°C/W
°C/W
32
10.2
0.8
User Determined
P
D
= (I
DD
x V
DD
+ P
I/O
)
(TJ - TA) /R
θ
JA
°C/W
°C/W
°C/W
W
W
W
Notes:
1.
Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2.
Junction to ambient thermal resistance, Theta-JA (R
θJA
) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
3.
Junction to case thermal resistance, Theta-JC (R
θJC
), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink.
2
2
1,2
1,2
3
4, 5
7
56F803 Technical Data, Rev. 16
Freescale Semiconductor 19
4.
Thermal Characterization Parameter, Psi-JT (
Ψ
JT
), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2.
Ψ
JT
is a useful value to use to estimate junction temperature in steady state customer environments.
5.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
6.
See Section 5.1 from more details on thermal design considerations.
7.
TJ = Junction Temperature
TA = Ambient Temperature
3.2 DC Electrical Characteristic
Table 3-4 DC Electrical Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C, C
L
≤
50pF, f op
= 80MHz
Characteristic Symbol Min Typ Max Unit
Input high voltage (XTAL/EXTAL)
Input low voltage (XTAL/EXTAL)
Input high voltage (Schmitt trigger inputs)
1
Input low voltage (Schmitt trigger inputs)
1
Input high voltage (all other digital inputs)
Input low voltage (all other digital inputs)
Input current high (pullup/pulldown resistors disabled, V
IN
=V
DD
)
Input current low (pullup/pulldown resistors disabled, V
IN
=V
SS
)
Input current high (with pullup resistor, V
IN
=V
DD
)
Input current low (with pullup resistor, V
IN
=V
SS
)
Input current high (with pulldown resistor, V
IN
=V
DD
)
Input current low (with pulldown resistor, V
IN
=V
SS
)
Nominal pullup or pulldown resistor value
Output tri-state current low
Output tri-state current high
V
IHC
V
ILC
V
IHS
V
ILS
V
IH
V
IL
I
IH
I
IL
I
IHPU
I
ILPU
I
IHPD
I
ILPD
R
PU
, R
PD
I
OZL
I
OZH
2.0
-0.3
-1
2.25
0
2.2
-0.3
-1
-1
-210
20
-1
-10
-10
—
—
—
—
—
—
—
—
30
—
—
—
—
—
—
2.75
0.5
5.5
0.8
5.5
0.8
1
1
1
-50
180
1
10
10
V
V
V
μA
V
V
V
μA
K
Ω
μA
μA
μA
μA
μA
μA
56F803 Technical Data, Rev. 16
20 Freescale Semiconductor
DC Electrical Characteristic
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C, C
L
≤
50pF, f op
= 80MHz
Characteristic Symbol Min Typ Max
I
IHA
-15 — 15
Unit
μA
Input current high (analog inputs, V
IN
=V
DDA
)
2
Input current low (analog inputs, V
IN
=V
SSA
)
2
Output High Voltage (at IOH)
I
ILA
-15 —
—
15
—
μA
V
Output Low Voltage (at IOL)
Output source current
Output sink current
PWM pin output source current
3
PWM pin output sink current
4
V
OH
V
OL
I
OH
I
OL
I
OHP
I
OLP
V
DD
– 0.7
—
4
4
10
16
—
—
—
—
—
0.4
—
—
—
—
V mA mA mA mA
Input capacitance
Output capacitance
V
DD
supply current
C
IN
C
OUT
I
DDT
5
—
—
8
12
—
— pF pF
Run
6
Wait
7
Stop
Low Voltage Interrupt, external power supply
8
—
—
—
2.4
126
105
60
2.7
152
129
84
3.0
mA mA mA
V V
EIO
Low Voltage Interrupt, internal power supply
9 V
EIC
2.0
2.2
2.4
V
1.
Power on Reset
10 V
POR
— 1.7
2.0
V
1.
Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS, TDI, and
MSCAN_RX
2.
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3.
PWM pin output source current measured with 50% duty cycle.
4.
PWM pin output sink current measured with 50% duty cycle.
5.
I
DDT
= I
DD
+ I
DDA
(Total supply current for V
DD
+ V
DDA
)
6.
Run (operating) I
DD
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled.
7.
Wait I
DD
measured using external square wave clock source (f osc
= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. C
L
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I
DD
; measured with PLL enabled.
56F803 Technical Data, Rev. 16
Freescale Semiconductor 21
8.
This low-voltage interrupt monitors the V as V
DD via separate traces. If V
DDA under transient conditions when V
DDA
>V
EIO
DDA external power supply. V drops below V
DDA is generally connected to the same potential
EIO
, an interrupt is generated. Functionality of the device is guaranteed
(between the minimum specified V
DD
and the point when the V
EIO interrupt is generated).
9.
This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below V
EIC
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V).
10. Power
– on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally regulated voltage is typically 100mV less than V
DD
during ramp-up, until 2.5V is reached, at which time it self-regulates.
180
150
120
90
IDD Digital
IDD Analog
IDD Total
60
30
0 20
40
Freq. (MHz)
60
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in
80
3.3 AC Electrical Characteristics
are tested using the V
IL
and V
IH levels specified in the DC Characteristics
IH
and V
IL
for an input signal are shown.
22
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Flash Memory Characteristics
Input Signal
V
IH
Midpoint1
Fall Time
Low High
V
IL Rise Time
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
Figure 3-2 Input Signal Measurement References
shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached V
OL
or V
OH
• Data Invalid state, when a signal level is in transition between V
OL
and V
OH
Data1 Valid
Data1
Data2 Valid
Data2
Data Invalid State
Data Active
Data
Tri-stated
Figure 3-3 Signal States
3.4 Flash Memory Characteristics
Data3 Valid
Data3
90%
50%
10%
Data Active
Table 3-5 Flash Memory Truth Table
Mode
XE
1
YE
2
SE
3
OE
4
Standby
Read
Word Program
Page Erase
L
H
H
H
L
H
H
L
L
H
L
L
Mass Erase H L L
1.
X address enable, all rows are disabled when XE = 0
L
2.
Y address enable, YMUX is disabled when YE = 0
3.
Sense amplifier enable
4.
Output enable, tri-state Flash data out bus when OE = 0
L
H
L
L
PROG
5
H
L
L
L
L
ERASE
6
L
H
L
L
H
MAS1
7
L
L
L
L
H
NVSTR
8
H
H
L
L
H
56F803 Technical Data, Rev. 16
Freescale Semiconductor 23
24
5.
Defines program cycle
6.
Defines erase cycle
7.
Defines mass erase cycle, erase whole block
8.
Defines non-volatile store cycle
Mode
Read
Word program
Page erase
Mass erase
Table 3-6 IFREN Truth Table
IFREN = 1
Read information block
Program information block
Erase information block
Erase both block
IFREN = 0
Read main memory block
Program main memory block
Erase main memory block
Erase main memory block
Table 3-7 Flash Timing Parameters
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF
Characteristic Symbol Min Typ Figure
Program time
Erase time
T prog*
T erase*
20
20
–
–
–
– us ms
Mass erase time
Endurance
1
Data Retention
1
T me*
E
CYC
D
RET
100
10,000
10
–
20,000
30
–
–
– ms cycles years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set up time T nv*
– 5 – us
,
,
NVSTR hold time T nvh*
– 5 – us
NVSTR hold time (mass erase) – 100 – us
,
NVSTR to program set up time
T nvh1*
T pgs*
– 10 – us
Recovery time T rcv*
– 1 – us
,
,
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Flash Memory Characteristics
Table 3-7 Flash Timing Parameters (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF
Characteristic Symbol Min Typ Figure
Cumulative program
HV period
2
Program hold time
3
Address/data set up time
3
T
T hv pgh
–
–
3
–
–
– ms
T ads
– – –
Address/data hold time
3
T adh
– – –
1.
One cycle is equal to an erase program and read.
2.
Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase.
3.
Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
IFREN
XADR
XE
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tadh
Tads
Tprog
Tpgs
Thv
Figure 3-4 Flash Program Cycle
Tpgh
Tnvh
Trcv
Freescale Semiconductor
56F803 Technical Data, Rev. 16
25
26
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Terase
Figure 3-5 Flash Erase Cycle
Tnvh
Trcv
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tme
Figure 3-6 Flash Mass Erase Cycle
Tnvh1
Trcv
56F803 Technical Data, Rev. 16
Freescale Semiconductor
External Clock Operation
3.5 External Clock Operation
The 56F803 system clock can be derived from an external crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in
a recommended crystal oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal
56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in
no external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation:
CL =
CL1 * CL2
CL1 + CL2
+ Cs =
12 * 12
12 + 12
+ 3 = 6 + 3 = 9pF
This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit.
EXTAL XTAL
R z
Recommended External Crystal
Parameters:
R z
= 1 to 3 M
Ω f c
= 8MHz (optimized for 8MHz) f c
Figure 3-7 Connecting to a Crystal Oscillator
Freescale Semiconductor
56F803 Technical Data, Rev. 16
27
3.5.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. In
, a typical ceramic resonator circuit is shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in
no external load capacitors should be used.
EXTAL XTAL
R z
Recommended Ceramic Resonator
Parameters:
R z
= 1 to 3 M
Ω f c
= 8MHz (optimized for 8MHz) f c
Figure 3-8 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
3.5.3
External Clock Source
The recommended method of connecting an external clock is given in
source is connected to XTAL and the EXTAL pin is grounded.
56F803
XTAL EXTAL
External
Clock
V
SS
Figure 3-9 Connecting an External Clock Signal
28
56F803 Technical Data, Rev. 16
Freescale Semiconductor
External Clock Operation
Table 3-8 External Clock Operation Timing Requirements
3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)
1 f osc
0 — 80 MHz
Clock Pulse Width
2
,
3 t
PW
6.25
— — ns
1.
See
for details on using the recommended connection of an external clock driver.
2.
The high or low pulse width must be no smaller than 6.25ns or the chip will not function. However, the high pulse width does not have to be any particular percent of the low pulse width.
3. Parameters listed are guaranteed by design.
External
Clock
90%
50%
10% t
PW t
PW
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
Figure 3-10 External Clock Timing
V
IH
90%
50%
10%
V
IL
Freescale Semiconductor
56F803 Technical Data, Rev. 16
29
3.5.4
Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1 f osc f out
/2
4 8 10 MHz
PLL output frequency
2
PLL stabilization time
3
0 o
to +85 o
C
40 — 110 MHz t plls
— 1 10 ms
PLL stabilization time
3
-40 o
to 0 o
C t plls
— 100 200 ms
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and f out
/2, please refer to the OCCS chapter in the
User Manual. ZCLK = f op
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
3.6 External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing
1, 2
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C, C
L
≤
50pF, f op
= 80MHz
Characteristic Symbol
Min Max
Unit
Address Valid to WR Asserted
WR Width Asserted
Wait states = 0
Wait states > 0
WR Asserted to D0–D15 Out Valid
Data Out Hold Time from WR Deasserted
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
RD Deasserted to Address Not Valid
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0 t
AWR t
WR t
WRD t
DOH t
DOS t
RDA t
ARDD
6.5 —
7.5
(T*WS) + 7.5
—
4.8
2.2
(T*WS) + 6.4
0
18.7
(T*WS) + 18.7
—
—
—
—
—
—
4.2
— ns ns ns ns ns ns ns ns ns ns
56F803 Technical Data, Rev. 16
30 Freescale Semiconductor
External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing
Operating Conditions:
V
SS
= V
SSA
1, 2
(Continued)
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C, C
L
≤
50pF, f op
= 80MHz
Characteristic Symbol
Min Max
Unit
0 — ns Input Data Hold to RD Deasserted
RD Assertion Width
Wait states = 0
Wait states > 0
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
Address Valid to RD Asserted
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted t
DRD t
RD t
AD t
ARDA t
RDD t
WRRD t
RDRD t
WRWR t
RDWR
19
(T*WS) + 19
—
—
-4.4
—
—
6.8
0
14.1
12.8
—
—
1
(T*WS) + 1
—
2.4
(T*WS) + 2.4
—
—
—
— ns ns ns ns ns ns ns ns ns ns ns
Freescale Semiconductor
56F803 Technical Data, Rev. 16
31
1.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note) t
ARDD t
ARDA t
RDA t
RD t
RDRD
RD t
AWR t
WRWR t
WR t
WRRD t
RDWR
WR t
RDD t
WRD t
DOS t
AD t
DOH t
DRD
D0–D15
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 3-11 External Bus Asynchronous Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
1, 5
50pF
Characteristic
RESET Assertion to Address, Data and Control
Signals High Impedance
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
RESET De-assertion to First External Address Output
Symbol
t
RAZ t
RA t
RDA
Min
—
275,000T
128T
33T
Max
21
—
—
34T
Unit
ns ns ns ns
See Figure
56F803 Technical Data, Rev. 16
32 Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)
1, 5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF
Characteristic Symbol Min Max Unit See Figure
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the interrupt service routine
IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State
3 t
IRW t t
IDM t
IG
IRI
1.5T
15T
16T
13T
—
—
—
— ns ns ns ns
IRQA Width Assertion to Recover from Stop State
4
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1 t t
IW
IF
2T
—
—
—
275,000T
12T ns ns ns
Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1 t
IRQ
—
—
275,000T
12T ns ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1 t
II
—
—
275,000T
12T ns ns
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
Freescale Semiconductor
56F803 Technical Data, Rev. 16
33
RESET
A0–A15,
D0–D15
PS, DS,
RD, WR t
RAZ t
RA
Figure 3-12 Asynchronous Reset Timing
t
RDA
First Fetch
First Fetch
IRQA,
IRQB t
IRW
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
34
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
A0–A15,
PS, DS,
RD, WR
IRQA,
IRQB t
IDM
First Interrupt Instruction Execution a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA,
IRQB t
IG b) General Purpose I/O
Figure 3-14 External Level-Sensitive Interrupt Timing
IRQA,
IRQB
A0–A15,
PS, DS,
RD, WR t
IRI
First Interrupt Vector
Instruction Fetch
Figure 3-15 Interrupt from Wait State Timing
t
IW
IRQA t
IF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 35
t
IRQ
IRQA t
II
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
3.8 Serial Peripheral Interface (SPI) Timing
Operating Conditions:
V
SS
= V
SSA
Table 3-12 SPI Timing
1
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
Enable lead time
Master
Slave
Enable lag time
Master
Slave
Clock (SCLK) high time
Master
Slave
Clock (SCLK) low time
Master
Slave
Data set-up time required for inputs
Master
Slave
Data hold time required for inputs
Master
Slave
Access time (time to data active from high-impedance state)
Slave
Disable time (hold time to high-impedance state)
Slave t
C t
ELD t
ELG t
CH t
CL t
DS t
DH t
A t
D
50
25
—
25
—
100
17.6
12.5
24.1
25
20
0
0
2
4.8
3.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
15.2
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figures
Figure
Figure
Figures
Figures
Figures
Figures
Figure
Figure
56F803 Technical Data, Rev. 16
36 Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
Operating Conditions:
V
SS
= V
SSA
Table 3-12 SPI Timing
1
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
Min Max Unit Characteristic
Data Valid for outputs
Master
Slave (after enable edge)
Data invalid
Master
Slave
Rise time
Master
Slave
Fall time
Master
Slave
1.
Parameters listed are guaranteed by design.
Symbol
t
DV t
DI t
R t
F
—
—
0
0
—
—
—
—
4.5
20.4
—
—
11.5
10.0
9.7
9.0
ns ns ns ns ns ns ns ns
See Figure
,
,
,
,
SS
(Input)
SCLK (CPOL = 0)
(Output) t
CH t
CL
SS is held High on master t
C t
R t
CL t
F t
F t
R
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output) t
DH t
DS
MSB in t
DI t
CH
Bits 14–1 t
DV
LSB in t
DI
(ref)
Master MSB out t
F
Bits 14–1
Figure 3-18 SPI Master Timing (CPHA = 0)
Master LSB out t
R
Freescale Semiconductor
56F803 Technical Data, Rev. 16
37
SS
(Input) t
C
SS is held High on master t
F t
CL t
R
SCLK (CPOL = 0)
(Output) t
CH t
CL t
F
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output) t
CH t
R
LSB in t
DS t
DH
MSB in t
DI
Bits 14–1 t
DV t
DV
(ref)
Master MSB out t
F
Bits 14– 1
Figure 3-19 SPI Master Timing (CPHA = 1)
Master LSB out t
R
38
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
SS
(Input) t
C t
CL t
R t
F t
ELG
SCLK (CPOL = 0)
(Input) t
ELD t
CH t
CL
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input) t
DS t
A t
CH t
R
Slave MSB out
MSB in
Bits 14–1 t
DV t
DH
Bits 14–1 t
F t
D
Slave LSB out t
DI t
DI
LSB in
Figure 3-20 SPI Slave Timing (CPHA = 0)
Freescale Semiconductor
56F803 Technical Data, Rev. 16
39
SS
(Input) t
C t
CL t
R t
F
SCLK (CPOL = 0)
(Input) t
ELD t
CH t
CL t
ELG
SCLK (CPOL = 1)
(Input) t
DV t
CH
MISO
(Output) t
DS t
A
Slave MSB out t
F
Bits 14–1 t
DH t
DV
Bits 14–1
MOSI
(Input)
MSB in
Figure 3-21 SPI Slave Timing (CPHA = 1)
3.9 Quad Timer Timing
t
R t
D t
DI
Slave LSB out
LSB in
Operating Conditions:
V
Table 3-13 Timer Timing
1, 2
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit
Timer input period
Timer input high/low period
Timer output period
P
IN
P
INHL
P
OUT
4T+6
2T+3
2T
—
—
— ns ns ns
40
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Quadrature Decoder Timing
Operating Conditions:
V
Table 3-13 Timer Timing
1, 2
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
— ns Timer output high/low period P
OUTHL
1T
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
Timer Inputs
P
IN
P
INHL
P
INHL
Timer Outputs
P
OUT
P
OUTHL
Figure 3-22 Timer Timing
P
OUTHL
3.10 Quadrature Decoder Timing
Table 3-14 Quadrature Decoder Timing
1,2
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit
Quadrature input period
Quadrature input high/low period
P
IN
P
HL
8T+12
4T+6
—
— ns ns
Quadrature phase period P
PH
2T+3 — ns
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12. ns. V
SS
= 0 V, V
T
A
= –40
° to +85°C, C
L
≤
50pF.
DD
= 3.0 – 3.6V,
2.
Parameters listed are guaranteed by design.
Freescale Semiconductor
56F803 Technical Data, Rev. 16
41
42
P
PH
P
PH
P
PH
P
PH
Phase A
(Input)
P
IN
P
HL
P
HL
Phase B
(Input)
P
IN
P
HL
P
HL
Figure 3-23 Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
Operating Conditions:
V
SS
= V
SSA
Table 3-15 SCI Timing
4
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
Characteristic
Baud Rate
1
RXD
2
Pulse Width
Symbol
BR
RXD
PW
Min
—
0.965/BR
Max
(f
MAX
*2.5)/(80)
1.04/BR
Unit
Mbps ns
TXD
3
Pulse Width
TXD
PW
0.965/BR
1.
f
MAX is the frequency of operation of the system clock in MHz.
2.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4.
Parameters listed are guaranteed by design.
1.04/BR ns
RXD
SCI receive data pin
(Input)
RXD
PW
Figure 3-24 RXD Pulse Width
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Analog-to-Digital Converter (ADC) Characteristics
TXD
SCI receive data pin
(Input)
TXD
PW
Figure 3-25 TXD Pulse Width
3.12 Analog-to-Digital Converter (ADC) Characteristics
Characteristic
ADC input voltages
Resolution
Integral Non-Linearity
3
Differential Non-Linearity
Monotonicity
ADC internal clock
5
Conversion range
Power-up time
Conversion time
Sample time
Input capacitance
Gain Error (transfer gain)
5
Offset Voltage
5
Total Harmonic Distortion
5
Signal-to-Noise plus Distortion
5
Effective Number of Bits
5
Spurious Free Dynamic Range
5
Bandwidth
Table 3-16 ADC Characteristics
Symbol
V
ADCIN
R
ES
INL
DNL
Min
0
1
12
—
—
0.5
V
SSA
—
Typ
—
—
+/- 2.5
Max
V
REF
2
12
+/- 4
+/- 0.9
GUARANTEED
—
+/- 1
5
—
16
V
DDA
— f
ADIC
R
AD t
ADPU t
ADC t
ADS
C
ADI
E
GAIN
V
OFFSET
THD
SINAD
ENOB
SFDR
BW
—
—
9
65
—
—
0.95
-80
60
55
6
1
5
1.00
-15
64
60
10
70
100
—
—
—
—
—
—
1.10
+20
—
—
Unit
V
Bits
LSB
4
LSB
4
MHz
V t
AIC cycles
6 t
AIC cycles
6 t
AIC cycles
6 pF
6
— mV dB dB bit dB
KHz
56F803 Technical Data, Rev. 16
Freescale Semiconductor 43
Table 3-16 ADC Characteristics
Characteristic Symbol Min Typ Max Unit
ADC Quiescent Current (both ADCs) I
ADC
— 50 — mA
V
REF
Quiescent Current (both ADCs) I
VREF
— 12 16.5
mA
1.
For optimum ADC performance, keep the minimum V
ADCIN
value > 25mV. Inputs less than 25mV may convert to a digital output code of 0.
2.
V
REF
must be equal to or less than V
DDA
and must be greater than 2.7V. For optimal ADC performance, set V
REF
to V
D-
DA
-0.3V.
3.
Measured in 10-90% range.
4.
LSB = Least Significant Bit.
5.
Guaranteed by characterization.
6.
t
AIC
= 1/ f
ADIC
3
ADC analog input
1
2 4
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4.
Sampling capacitor at the sample and hold circuit. (1pf)
Figure 3-26 Equivalent Analog Input Circuit
3.13 Controller Area Network (CAN) Timing
Table 3-17 CAN Timing
2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40× to +85×C, C
L
£ 50pF, MSCAN Clock = 30MHz
Characteristic Symbol Min Max Unit
Baud Rate
Bus Wakeup detection
1
BR
CAN
T
WAKEUP
—
5
1
—
Mbps
μs
44
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Controller Area Network (CAN) Timing
1.
If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The value of 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
2.
Parameters listed are guaranteed by design.
MSCAN_RX
CAN receive data pin
(Input)
T
WAKEUP
Figure 3-27 Bus Wakeup Detection
Freescale Semiconductor
56F803 Technical Data, Rev. 16
45
3.14 JTAG Timing
Table 3-18 JTAG Timing
1, 3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
° to +85°C, C
L
≤
50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit
TCK frequency of operation
2 f
OP
DC 10
TCK cycle time
TCK clock pulse width
TMS, TDI data set-up time
TMS, TDI data hold time t
CY t
PW t
DS t
DH
100
50
0.4
1.2
—
—
—
—
TCK low to TDO data valid
TCK low to TDO tri-state t
DV t
TS
—
—
26.6
23.5
TRST assertion time t
TRST
50 —
DE assertion time t
DE
4T
1.
Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
—
2.
TCK frequency of operation must be less than 1/8 the processor rate.
3.
Parameters listed are guaranteed by design.
MHz ns ns ns ns ns ns ns ns t
CY t
PW t
PW
V
IH
TCK
(Input)
V
M
= V
IL
+ (V
IH
– V
IL
)/2
V
M
V
IL
V
M
Figure 3-28 Test Clock Input Timing Diagram
46
56F803 Technical Data, Rev. 16
Freescale Semiconductor
TCK
(Input)
TDI
TMS
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output) t
DS
Input Data Valid t
DH t
DV
Output Data Valid t
TS t
DV
Output Data Valid
Figure 3-29 Test Access Port Timing Diagram
TRST
(Input) t
TRST
Figure 3-30 TRST Timing Diagram
DE t
DE
Figure 3-31 OnCE—Debug Event
JTAG Timing
Freescale Semiconductor
56F803 Technical Data, Rev. 16
47
Part 4 Packaging
4.1 Package and Pin-Out Information 56F803
This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F803.
48
D10
D11
D12
D13
D14
D15
A0
V
DD
V
SS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
V
DD
PS
DS
PIN 1
ORIENTATION
MARK
PIN 26
Figure 4-1 Top View, 56F803 100-pin LQFP Package
PIN 76
PIN 51
PWMA5
PWMA4
PWMA3
PWMA2
PWMA1
PWMA0
HOME0
INDEX0
V
SS
V
DD
PHASEB0
PHASEA0
V
SS
V
DD
V
DD
V
DDA
V
SSA
EXTAL
XTAL
AN7
AN6
AN5
AN4
AN3
AN2
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Package and Pin-Out Information 56F803
Table 4-1 56F803 Pin Identification By Pin Number
Pin No.
Signal Name Pin No.
Signal Name Pin No.
Signal Name Pin No.
Signal Name
4
5
6
7
8
1
2
3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D10
D11
D12
D13
D14
D15
A0
V
DD
V
SS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
V
DD
PS
DS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A14
A15
V
SS
WR
RD
IRQA
IRQB
TCS
TCK
TMS
TDI
TDO
TRST
VCAPC
ISA0
ISA1
ISA2
FAULTA0
MSCAN_TX
FAULTA1
MSCAN_RX
FAULTA2
VREF
AN0
AN1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
AN2
AN3
AN4
AN5
AN6
AN7
XTAL
EXTAL
V
SSA
V
DDA
V
DD
V
DD
V
SS
PHASEA0
PHASEB0
V
DD
V
SS
INDEX0
HOME0
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TXD0
RXD0
EXTBOOT
RESET
DE
CLKO
TD1
TD2
SS
MISO
MOSI
SCLK
VCAPC
D0
D1
D2
V
DD
V
SS
D3
D4
D5
D6
D7
D8
D9
Freescale Semiconductor
56F803 Technical Data, Rev. 16
49
50
-AB-
C
E
H
9
0.15 (0.006) S
S
AC T-U S Z S
-T-
-U-
0.15 (0.006)
S
A
AB T-U
S
Z
S
AE
AD
-Z-
AE
96X
G
(24X PER SIDE)
0.100 (0.004) AC
-AC-
SEATING
PLANE
M °
R
0.25 (0.010)
GAUGE PLANE
W
DETAIL AD
X
K
Q°
D
F
N J
0.20 (0.008)
M
AC T-U
S
Z
S
SECTION AE-AE
Figure 4-2 100-pin LQPF Mechanical Information
NOTES:
1.
DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4.
DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5.
DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
6.
DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7.
DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8.
MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
9.
EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 13.950 14.050
0.549
0.553
B
13.950 14.050
0.549
0.553
C
1.400
1.600
0.055
0.063
D
0.170
0.270
0.007
0.011
E
1.350
1.450
0.053
0.057
F
0.170
0.230
0.007
0.009
G
0.500 BSC 0.020 BSC
H
0.050
0.150
0.002
0.006
J
0.090
0.200
0.004
0.008
K
0.500
0.700
0.020
0.028
M
°
N
0.090
0.160
0.004
0.006
Q
°
5
R
0.150
0.250
0.006
0.010
°
S
15.950 16.050
0.628
0.632
V 15.950 16.050
0.628
0.632
W
X
0.200 REF
1.000 REF
0.008 REF
0.039 REF
56F803 Technical Data, Rev. 16
Freescale Semiconductor
Thermal Design Considerations
Please see www.freescale.com for the most current case outline.
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T
J
, in
°C can be obtained from the equation:
Equation 1:
T
J
= T
A
+
(
P
D
×
R
θJA
)
Where:
T
A
= ambient temperature °C
R
θJA
= package junction-to-ambient thermal resistance °C/W
P
D
= power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
Equation 2:
R
θJA
= R
θJC
+ R
θCA
Where:
R
θJA
= package junction-to-ambient thermal resistance °C/W
R
θJC
= package junction-to-case thermal resistance °C/W
R
θCA
= package case-to-ambient thermal resistance °C/W
R
θJC
is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, R
θCA
. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from R
θJA
do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
56F803 Technical Data, Rev. 16
Freescale Semiconductor 51
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from
SST.
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts.
© 2005, 2007,2015 Freescale Semiconductor, Inc. All rights reserved.
Document Number: DSP56F803
Rev. 17
10/2015
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project
Related manuals
advertisement