Renesas 78K0/Kx2-L KY2-L, KA2-L, KB2-L, KC2-L microcontroller Application Note
Below you will find brief information for microcontroller 78K0/Kx2-L KY2-L, microcontroller 78K0/Kx2-L KA2-L, microcontroller 78K0/Kx2-L KB2-L, microcontroller 78K0/Kx2-L KC2-L. This sample program shows an example of using serial interface IICA (I2C). 16 bytes of data are transmitted and received via the I2C bus in slave operation. This note describes an operation overview of the sample program and how to use it, as well as how to set up and use serial interface IICA.
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Application Note
78K0/Kx2-L
Sample Program (Serial Interface IICA)
Slave Communication
This document describes an operation overview of the sample program and how to use it, as well as how to set up and use serial interface IICA. In the sample program, 16 bytes of data are transmitted and received via the I
2
C bus in slave operation.
Target devices
78K0/KY2-L microcontroller
78K0/KA2-L microcontroller
78K0/KB2-L microcontroller
78K0/KC2-L microcontroller
CONTENTS
CHAPTER 1 OVERVIEW...................................................................... 3
1.1
Primary Initial Settings ................................................................ 4
1.2
Processing After Main Loop ....................................................... 4
CHAPTER 2 CIRCUIT DIAGRAM........................................................ 5
2.1
Circuit Diagram ........................................................................... 5
2.2
Used Device Other than Microcontroller..................................... 6
CHAPTER 3 SOFTWARE..................................................................... 7
3.1
Included Files ............................................................................. 7
3.2
Internal Peripheral Functions to Be Used................................... 7
3.3
Initial Settings and Operation Overview ..................................... 8
3.4
Flow Charts ................................................................................ 9
CHAPTER 4 SETTING METHODS ................................................... 13
4.1
Setting up Serial Interface IICA ................................................ 13
4.2
Software Coding Example ........................................................ 25
CHAPTER 5 RELATED DOCUMENTS ............................................. 29
APPENDIX A PROGRAM LIST ......................................................... 30
APPENDIX B USING 78K0/KC2-L 44-PIN PRODUCTS ................. 59
A PPENDIX C REVISION HISTORY .................................................. 60
Document No. U19691EJ1V0AN00 (1st edition)
Date Published September 2009 N
2009
Printed in Japan
•
•
•
•
•
•
The information in this document is current as of May, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
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Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.
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"Special":
"Specific": and industrial robots.
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E0904E
2
U19691EJ1V0AN
CHAPTER 1 OVERVIEW
This sample program shows an example of using serial interface IICA. 16 bytes of data are transmitted and received via the I
2
C bus in slave operation.
[Operation overview]
Master device
I
2
C slave reception (16 bytes)
I 2 C slave transmission (16 bytes)
SCLA0
SDAA0
78K0/Kx2-L microcontroller
Serial interface IICA
• Operating mode: fast mode
• Transfer clock: 400 kHz
• Local address: A0H
The received data is processed to create transmission data.
Caution For a definition of the I 2 C bus, refer to the 78K0/Kx2-L User’s Manual .
Application Note U19691EJ1V0AN
3
CHAPTER 1 OVERVIEW
1.1 Primary Initial Settings
The primary initial settings are as follows:
<Option byte settings> z Allowing the internal low-speed oscillator to be programmed to stop z Disabling the watchdog timer z Setting the internal high-speed oscillation clock frequency to 8 MHz z Disabling LVI from being started by default
<Settings during initialization immediately after a reset ends> z Specifying the ROM and RAM sizes z Setting up I/O ports z Checking whether V
DD
is 2.7 V or more by using the low-voltage detector
Note 1 z Specifying that the CPU clock and peripheral hardware clock run on the internal high-speed oscillation clock (8
MHz) z Stopping the internal low-speed oscillator z Disabling peripheral hardware not to be used z Setting up serial interface IICA
• Specifying fast mode as the operating mode and setting the transfer clock frequency to 400 kHz
• Specifying A0H as the local address
• Specifying that P60/SCLA0 and P61/SDAA0 are used for the I 2
C bus
• Enabling the INTIICA0 interrupt Note 2 z Enabling interrupts
Notes 1. For details about the low-voltage detector, refer to the 78K0/Kx2-L User’s Manual .
2. In this sample program, the HALT mode is entered while the system waits for data communication to end, and the HALT mode is exited when the INTIICA0 interrupt is generated at the end of data communication.
When adding other interrupts to this sample program, make sure that these interrupts do not affect the HALT mode from being exited when the INTIICA0 interrupt occurs.
1.2 Processing After Main Loop
After the initial settings have been specified, the STOP mode is entered. If a local address is received, the STOP mode is exited, and then I
2
C communication starts. During reception, up to 16 bytes of data are received and then saved in the
RAM area. During transmission, received data is processed and then transmitted.
4
Application Note U19691EJ1V0AN
CHAPTER 2 CIRCUIT DIAGRAM
This chapter provides a circuit diagram used in this sample program.
A circuit diagram is shown below.
Master device
V
DD
V
DD
V
DD
V
DD
SCLA0
SDAA0
78K0/Kx2-L microcontroller
RESET
REGC
V
SS
Note 1
AV
SS
Note 2
V
DD
0.47 to 1
μ
F
Notes 1. This is shared with AV SS in the 78K0/KY2-L and 78K0/KA2-L.
2. This is provided only in the 78K0/KB2-L and 78K0/KC2-L.
Cautions 1. Use the microcontroller at a voltage in the range of 2.94 V
≤ V
DD
≤ 5.5 V.
2. Connect REGC to V SS via a capacitor (0.47 to 1
μ
F).
3. For the 78K0/KY2-L and 78K0/KA2-L, V
SS
is also used as the ground potential for the A/D converter. Be sure to connect V
SS
to a stable GND.
4. Make the AV
SS
pin have the same potential as V
SS
and connect it directly to GND (only for the
78K0/KB2-L and 78K0/KC2-L microcontrollers).
5. Connect the AV
REF
pin directly to V DD .
6. Handle unused pins that are not shown in the circuit diagram as follows:
• I/O ports: Set them to output mode and leave them open (unconnected).
• Input ports: Connect them independently to V
DD or V SS via a resistor.
7. Adjust the resistance of the pull-up resistors connected to the serial clock line and serial data bus line (enclosed in the dotted lines above) in accordance with the voltage and capacitance of the I
2
C bus and the transfer clock. In this sample program, resistors with a resistance of 2 to 10 k Ω are used.
8. In this sample program, the P121/X1/TOOLC0 and P122/X2/EXCLK/TOOLD0 pins are used for onchip debugging.
Application Note U19691EJ1V0AN
5
CHAPTER 2 CIRCUIT DIAGRAM
2.2 Used Device Other than Microcontroller
The following device is used in addition to the microcontroller:
(1) Master device
A device that performs master transmission and reception is used as the other party of I
2
C slave communication.
6
Application Note U19691EJ1V0AN
CHAPTER 3 SOFTWARE
This chapter describes the files included in the compressed file to be downloaded, internal peripheral functions of the microcontroller to be used, and initial settings and provides an operation overview of the sample program and the flow charts.
3.1 Included Files
The following table shows the files included in the compressed file to be downloaded.
File Name Description Compressed (*.zip) File Included main.asm
(Assembly language version) main.c
(C language version) op.asm
Source file for hardware initialization processing and main processing of microcontroller z Note
Kx2-L_IICAS.prw
Kx2-L_IICAS.prj
Assembler source file for setting the option byte
(This file is used for setting up the watchdog timer and internal low-speed oscillator and selecting the internal high-speed oscillation clock frequency.)
Work space file for integrated development environment PM+
Project file for integrated development environment PM+ z
Note “main.asm” is included with the assembly language version, and “main.c” with the C language version.
Remark : Only the source file is included.
: The files to be used with integrated development environment PM+ are included.
3.2 Internal Peripheral Functions to Be Used
The following internal peripheral functions of the microcontroller are used in this sample program.
(1) Peripheral hardware
• Serial interface IICA:
• Low-voltage detector:
(2) Pin functions
• SCLA0/P60:
• SDAA0/P61:
Performs I
2
C slave communication.
Checks whether V DD is 2.7 V or more.
Used as the I
2
C serial clock pin.
Used as the I
2
C serial data bus pin. z Note z z z
Application Note U19691EJ1V0AN
7
CHAPTER 3 SOFTWARE
3.3 Initial Settings and Operation Overview
In this sample program, initial settings including the selection of the clock frequency, setting of the I/O ports, and setting of serial interface IICA are performed. After the initial settings have been specified, the STOP mode is entered. If a local address is received, the STOP mode is exited, and then I
2
C communication starts. During reception, up to 16 bytes of data are received and then saved in the RAM area. During transmission, received data is processed and then transmitted.
The details are described in the state transition diagram shown below.
Initial settings
<Option byte settings> z Allowing the internal low-speed oscillator to be programmed to stop z Disabling the watchdog timer z Setting the internal high-speed oscillation clock frequency to 8 MHz z Disabling LVI from being started by default
<Settings during initialization immediately after a reset ends> z Specifying the ROM and RAM sizes z Setting up I/O ports z Checking whether V
DD
is 2.7 V or more by using the low-voltage detector z Specifying that the CPU clock and peripheral hardware clock run on the internal high-speed oscillation clock (8 MHz) z Stopping the internal low-speed oscillator z Disabling peripheral hardware not to be used z Setting up serial interface IICA
• Specifying fast mode as the operating mode and setting the transfer clock frequency to 400 kHz
• Specifying A0H as the local address
• Specifying that P60/SCLA0 and P61/SDAA0 are used for the I 2
C bus
• Enabling the INTIICA0 interrupt z Enabling interrupts
Enter the STOP mode.
INTIICA0 interrupt
(A start condition is detected.)
Check the communication direction.
16 bytes have
Transmission been transmitted.
Create transmission data and transmit it to
INTIICA0 interrupt
(1 byte has been transmitted.) the slave.
Transmission of 1 byte starts.
Reception of 1 byte starts.
Reception
Make the slave receive data and save that data.
16 bytes have been received.
INTIICA0 interrupt
(1 byte has been received.)
INTIICA0 interrupt
(A stop condition is detected.)
The system waits for an interrupt.
The system waits for an interrupt.
INTIICA0 interrupt
(A stop condition is detected.)
8
Application Note U19691EJ1V0AN
CHAPTER 3 SOFTWARE
The flow charts for the sample program are shown below.
<Initialization immediately after a reset ends>
Start
Disable interrupts.
Set up the register bank.
Specify the ROM and RAM sizes.
Specify the stack pointer.
Set up I/O ports.
Note 2
Set the low-voltage detection level of the low-voltage detector (V
LVI
) to 2.84
±0.1 V.
Enable low-voltage detection.
Note 3
No
V
LVI
≤ V
DD
?
Yes
The option byte is referenced.
Note 1
Stop low-voltage detection.
Specify that the CPU clock and peripheral hardware clock run on the internal highspeed oscillation clock (8
MHz).
Stop the internal low-speed oscillator.
Disable peripheral hardware not to be used.
Specify fast mode as the operating mode of serial interface IICA, set the transfer clock frequency to
400 kHz, and then specify
A0H as the local address.
Enable serial interface IICA.
Specify P60/SCLA0 and
P61/SDAA0 to be used for the I
2
C bus.
Initialization immediately after a reset ends
Initial settings for serial interface
IICA
Enable the INTIICA0 interrupt.
Enable interrupts.
1
Application Note U19691EJ1V0AN
9
1
Enable the wakeup function.
No
Enter the STOP mode.
Is data being communicated?
Yes
Is data to be transmitted?
Yes
No
Start data transmission.
Note 4
No
Is data being communicated?
Yes
Has the communication direction changed?
No
Yes
Has all data been transmitted?
Yes
Specify that data transfers are incomplete.
No
Has an acknowledge signal been detected?
No
Yes
Specify that data communication is not to be performed.
Make the system exit the wait status.
CHAPTER 3 SOFTWARE
Start data reception.
Note 4
Is data being communicated?
No
Yes
Has the communication direction changed?
No
Yes
Has all data been received?
Yes
Read the received data.
No
Specify that data transfers are incomplete.
Main loop
10
Application Note U19691EJ1V0AN
CHAPTER 3 SOFTWARE
<INTIICA0 interrupt servicing>
INTIICA0
Stop the wakeup function.
Has a stop condition been detected?
Yes
Specify reception as the communication direction.
Specify that data transfers are incomplete.
No
Specify that data communication is not to be performed.
Has a start condition been detected?
Yes
Has an address match been detected?
Yes
Read the communication direction.
Specify that data is being communicated.
Specify that data transfers are incomplete.
No
No
Specify reception as the communication direction.
Specify that data communication is not to be performed.
Specify that data transfers are incomplete.
Specify that data transfers are complete.
RETI
End of communication Address match
(start of communication)
Address mismatch Data transmission/reception
Application Note U19691EJ1V0AN
11
CHAPTER 3 SOFTWARE
Notes 1. The option byte is automatically referenced by the microcontroller immediately after a reset ends. In this sample program, the following settings are specified using the option byte:
• Allowing the internal low-speed oscillator to be programmed to stop
• Disabling the watchdog timer
• Setting the internal high-speed oscillation clock frequency to 8 MHz
• Disabling LVI from being started by default
2. P60/SCLA0 and P61/SDAA0 are specified as input ports so that port output does not affect the I
2
C bus.
3. The low-voltage detector is enabled, and then the system is made to wait at least 10
μ s until the low-voltage detector stabilizes.
4. The HALT mode is entered during communication, and then exited when the INTIICA0 interrupt occurs at the end of communication.
12
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
This chapter describes how to set up serial interface IICA and provides software coding examples.
For other initial settings, refer to the 78K0/Kx2-L Sample Program (Initial Settings) LED Lighting Switch Control
Application Note .
For how to set registers, refer to the 78K0/Kx2-L User’s Manual .
For assembler instructions, refer to the 78K/0 Series Instructions User’s Manual .
4.1 Setting up Serial Interface IICA
Serial interface IICA uses the following eight registers:
• IICA control register 0 (IICACTL0)
• IICA flag register 0 (IICAF0)
• IICA control register 1 (IICACTL1)
• IICA low-level width setting register (IICWL)
• IICA high-level width setting register (IICWH)
• Port output mode register 6 (POM6)
• Port mode register 6 (PM6)
• Port register 6 (P6)
Application Note U19691EJ1V0AN
13
CHAPTER 4 SETTING METHODS
[Example of the setup procedure when using serial interface IICA for I
2
C slave communication]
(The same procedure is used in the sample program.)
<1> Set bits 0 and 1 (PM60 and PM61) of PM6 to 1 (input mode).
Note
<2> Set up the transfer clock by using IICWL and IICWH.
<3> Specify the local address by using SVA0.
<4> Specify the conditions for starting I
2
C communication by using bit 1 (STCEN) of IICAF0.
<5> Set bit 2 (ACKE0) of IICACTL0 to 1 (to enable acknowledge signals).
<6> Set bit 3 (WTIM0) of IICACTL0 to 1 (to generate an interrupt request at the falling edge of the ninth clock cycle).
<7> Set bit 4 (SPIE0) of IICACTL0 to 1 (to enable an interrupt request to be generated when a stop condition is detected).
<8> Specify the operating mode and operation of the digital filter by using bit 3 (SMC0) and bit 2 (DFC0) of
IICACTL1, respectively.
<9> Set bit 7 (IICE0) of IICACTL0 to 1 (to enable the I
2
C bus).
<10> Set bits 0 and 1 (POM60 and POM61) of POM6 to 1 (N-ch open-drain output (V
DD
withstand voltage) mode).
<11> Set bits 0 and 1 (P60 and P61) of P6 to 1 (to output 1).
<12> Clear bits 0 and 1 (PM60 and PM61) of PM6 to 0 (output mode).
<13> Clear the INTIICA0 interrupt request (clear IICAIF0 to 0).
<14> Enable the INTIICA0 interrupt (clear IICAMK0 to 0).
<15> Enable interrupts (EI).
<16> Set bit 7 (WUP) of IICACTL1 to 1 (to enable the wakeup function when an address match occurs in the STOP mode).
Note P60/SCLA0 and P61/SDAA0 are specified as input ports so that port output does not affect the I
2
C bus.
14
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
(1) IICA control register 0 (IICACTL0)
This register is used to enable/stop I
2
C operations, set wait timing, and set other I
2
C operations.
Figure 4-1. Format of IICA Control Register 0 (IICACTL0) (1/4)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
WREL0
Note 1
Wait cancellation
0
1
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRC0 = 1), the SDAA0 line goes into the high impedance state (TRC0 = 0).
Condition for setting (WREL0 = 1) Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• Reset
• Set by instruction
LREL0
Note 1
Exit from communications
1
This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLA0 and SDAA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICACTL0) and IICA status register 0 (IICAS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
IICE0 I 2 C operation enable
0
1
Stop operation. Reset the IICA status register 0 (IICAS0)
Enable operation.
Note 2 . Stop internal operation.
Be sure to set this bit (1) while the SCLA0 and SDAA0 lines are at high level.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• Reset
Condition for setting (IICE0 = 1)
• Set by instruction
Notes 1. The signal of this bit is invalid while IICE0 is 0.
2. The IICAS0 register, the STCF and IICBSY bits of the IICAF0 register, and the CLD0 and DAD0 bits of the
IICACTL1 register are reset.
Caution The start condition is detected immediately after I
2
C is enabled to operate (IICE0 = 1) while the
SCLA0 line is at high level and the SDAA0 line is at low level. Immediately after enabling I
2
C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction.
Remark The values written in red in the above figure are specified in this sample program.
Application Note U19691EJ1V0AN
15
CHAPTER 4 SETTING METHODS
Figure 4-1. Format of IICA Control Register 0 (IICACTL0) (2/4)
ACKE0 N otes 1, 2
WREL0 STT0 SPT0
Acknowledgment control
1
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• Reset
Enable acknowledgment. During the ninth clock period, the SDAA0 line is set to low level.
Condition for setting (ACKE0 = 1)
• Set by instruction
WTIM0 No te 1 Control of wait and interrupt request generation
0
1
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge
(ACK) is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• Reset
Condition for setting (WTIM0 = 1)
• Set by instruction
SPIE0
No te 1
Enable/disable generation of interrupt request when stop condition is detected
0 Disable
1 Enable
Condition for clearing (SPIE0 = 0)
• Cleared by instruction
• Reset
Condition for setting (SPIE0 = 1)
• Set by instruction
Notes 1. The signal of this bit is invalid while IICE0 is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value.
Remark The values written in red in the above figure are specified in this sample program.
16
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
Figure 4-1. Format of IICA Control Register 0 (IICACTL0) (3/4)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
STT0
Note
Start condition trigger
0
1
Do not generate a start condition.
When bus is released (in STOP mode):
Generate a start condition (for starting as master). When the SCLA0 line is high level, the SDAA0 line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCLA0 is changed to low level (wait state).
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the wait period when ACKE0 has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as SPT0.
• Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for setting (STT0 = 1)
• Set by instruction
Condition for clearing (STT0 = 0)
• Cleared by setting STT0 to 1 while communication reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
Note The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
2. IICRSV: Bit 0 of IICA flag register 0 (IICAF0)
STCF: Bit 7 of IICA flag register 0 (IICAF0)
Application Note U19691EJ1V0AN
17
CHAPTER 4 SETTING METHODS
Figure 4-1. Format of IICA Control Register 0 (IICACTL0) (4/4)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
SPT0 Stop condition trigger
0
1
Do not generate a stop condition.
Generate a stop condition (termination of master device’s transfer).
After the SDAA0 line goes to low level, either set the SCLA0 line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDAA0 line changes from low level to high level and a stop condition is generated.
Cautions concerning set timing
• For master reception:
Cannot be set to 1 during transfer.
Can be set to 1 only in the wait period when ACKE0 has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set it during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as STT0.
• SPT0 can be set to 1 only when in master mode Note
.
• When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output of the ninth clock.
• Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status.
Caution When bit 3 (TRC0) of the IICA status register 0 (IICAS0) is set to 1, WREL0 is set to 1 during the ninth clock and wait is canceled, after which TRC0 is cleared and the SDAA0 line is set to high impedance.
Remark Bit 0 (SPT0) becomes 0 when it is read after data setting.
18
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
(2) IICA flag register 0 (IICAF0)
This register sets the operating mode of I
2
C and indicates the status of the I
2
C bus.
Figure 4-2. Format of IICA Flag Register 0 (IICAF0)
STCF
Note
IICBSY
Note
0
1
Enable communication reservation
Disable communication reservation
Condition for clearing (IICRSV = 0)
• Cleared by instruction
• Reset
Condition for setting (IICRSV = 1)
• Set by instruction
STCEN Initial start enable trigger
0
1
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting a stop condition.
Condition for clearing (STCEN = 0)
• Cleared by instruction
• Detection of start condition
• Reset
Condition for setting (STCEN = 1)
• Set by instruction
IICBSY I 2 C bus status flag
0
1
Bus release status (communication initial status when STCEN = 1)
Bus communication status (communication initial status when STCEN = 0)
Condition for clearing (IICBSY = 0)
• Detection of stop condition
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (IICBSY = 1)
• Detection of start condition
• Setting of IICE0 when STCEN = 0
STCF STT0 clear flag
0
1
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
Condition for clearing (STCF = 0)
• Cleared by STT0 = 1
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (STCF = 1)
• Generating start condition unsuccessful and STT0 cleared to 0 when communication reservation is disabled (IICRSV = 1).
Note Bits 7 and 6 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0).
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when
STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed.
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
4. Be sure to clear bits 5 to 2 to “0”.
Remark STT0: Bit 1 of IICA control register 0 (IICACTL0)
IICE0: Bit 7 of IICA control register 0 (IICACTL0)
Application Note U19691EJ1V0AN
19
CHAPTER 4 SETTING METHODS
(3) IICA control register 1 (IICACTL1)
This register is used to set the operating mode of I
2
C and detect the statuses of the SCLA0 and SDAA0 pins.
Figure 4-3. Format of IICA Control Register 1 (IICACTL1)
SMC0
0
1
CLD0
Note 1
DAD0
Note 1
SMC0 DFC0 0 0
DFC0 Digital filter operation control
0
1
Digital filter off
Digital filter on
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0).
The digital filter is used for noise elimination in fast mode.
Operates in standard mode.
Operates in fast mode.
Operating mode switching
DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1)
0
1
The SDAA0 pin was detected at low level.
The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0)
• When the SDAA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (DAD0 = 1)
• When the SDAA0 pin is at high level
CLD0
0
Detection of SCLA0 pin level (valid only when IICE0 = 1)
The SCLA0 pin was detected at low level.
1
Condition for clearing (CLD0 = 0)
• When the SCLA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
The SCLA0 pin was detected at high level.
Condition for setting (CLD0 = 1)
• When the SCLA0 pin is at high level
WUP Control of address match wakeup
0
1
Stops operation of address match wakeup function in STOP mode.
Enables operation of address match wakeup function in STOP mode.
Clear (0) WUP after the address has matched or an extension code has been received. The subsequent communication can be entered by clearing (0) WUP. (The wait must be released and transmit data must be written after WUP has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while
WUP = 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE0 bit is set to 1.
When WUP = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a start condition by setting (1) the STT0 bit, without waiting for the detection of the subsequent start condition or stop condition.
Condition for clearing (WUP = 0)
• Cleared by instruction (after address match or extension code reception)
Condition for setting (WUP = 1)
• Set by instruction (when MSTS0, EXC0, and COI0 are “0”, and STD0 also “0” (communication not entered))
Note 2
20
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
Notes 1. Bits 5 and 4 are read-only.
2. The status of IICAS0 must be checked and WUP must be set during the period shown below.
SCLA0
SDAA0
<1> <2>
A6
Caution Be sure to clear bits 6, 1, and 0 to “0”.
A5 A4 A3 A2 period from <1> to <2>.
A1 A0
The maximum time from reading IICAS0 to setting WUP is the
Check the IICAS0 operation status and set WUP during this period.
Remarks 1. IICE0: Bit 7 of IICA control register 0 (IICACTL0)
2. The values written in red in the above figure are specified in this sample program.
R/W
Application Note U19691EJ1V0AN
21
CHAPTER 4 SETTING METHODS
(4) IICA low-level width setting register (IICWL), IICA high-level width setting register (IICWH)
The IICA low-level width setting register (IICWL) is used to set the low-level width (t
LOW
) of the SCLA0 pin signal that is output by serial interface IICA being in master mode.
The IICA high-level width setting register (IICWH) is used to set the high-level width (t
HIGH
) of the SCLA0 pin signal that is output by serial interface IICA being in master mode.
Figure 4-4. Format of IICA Low-Level Width Setting Register (IICWL)
Figure 4-5. Format of IICA High-Level Width Setting Register (IICWH)
The slave transfer clock is set up as follows by using the IICWL and IICWH registers:
(The values are rounded to the nearest integer.)
• Fast mode
IICWL = 1.3
μ s × f
PRS
IICWL = (1.2
μ s − t
R
− t
F
) × f
PRS
• Standard mode
IICWL = 4.7
μ s
× f
PRS
IICWL = (5.3
μ s
− t
R
− t
F
)
× f
PRS
Caution The transfer clock frequency range that can be specified varies depending on the operating mode.
Standard mode: 0 to 100 kHz
Fast mode: 0 to 400 kHz
Remarks 1. t
F
: Falling time of the SDAA0 and SCLA0 signals t
R
: Rising time of the SDAA0 and SCLA0 signals f
PRS
(For details about t
F
and t
R
, see the electrical specifications in the
: Peripheral hardware clock frequency
2. In this sample program, IICWL is set to 10 and IICWH is set to 8.
78K0/Kx2-L User’s Manual .)
22
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
(5) Port output mode register 6 (POM6)
This register sets the output mode of P60 and P61 in 1-bit units. During I
2
C communication, set SCLA0/P60 and
SDAA0/P61 to N-ch open drain output (V DD tolerance) mode.
Figure 4-6. Format of Port Output Mode Register 6 (POM6)
POM63 Note POM62 Note POM61 POM60
POM6n
0
1
P6n pin output mode selection (n = 1, 0)
Normal output (CMOS output) mode
N-ch open drain output (V
DD
tolerance) mode
POM6n
0
1
P6n pin output mode selection (n = 3, 2)
Note
Normal output (CMOS output) mode
N-ch open drain output (V
DD
tolerance) mode
Caution Be sure to clear the following bits to 0:
78K0/KC2-L: Bits 7 to 4
(6) Port register 6 (P6)
This register writes the data to be output from the chip if port 6 is specified to output data.
If using the P60/SCLA0 pin as a clock signal I/O pin and the P61/SDAA0 pin as a serial data I/O pin, set the P60 and P61 output latches to 1.
Figure 4-7. Format of Port Register 6 (P6)
P63
Note
P62
Note
P61 P60
P61, 60
0
1
P63, 62 Note
0
1
Output data control (in output mode)
Output 0.
Output 1.
Input data read (in input mode)
Input low level.
Input high level.
Output data control (in output mode)
Output 0.
Output 1.
Input data read (in input mode)
Input low level.
Input high level.
Caution Be sure to clear the following bits to 0:
78K0/KC2-L: Bits 7 to 4
Application Note U19691EJ1V0AN
23
CHAPTER 4 SETTING METHODS
(7) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
If using the P60/SCLA0 pin as a clock signal I/O pin and the P61/SDAA0 pin as a serial data I/O pin, clear PM60 and PM61 to 0.
Set IICE0 (bit 7 of IICA control register 0 (IICACTL0)) to 1 before setting the output mode because the P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when IICE0 is 0.
Figure 4-8. Format of Port Mode Register 6 (PM6)
PM63
Note
PM62
Note
PM61 PM60
PM6n
0
1
P6n pin I/O mode selection (n = 1, 0)
Output mode (output buffer on)
Input mode (output buffer off)
PM6n
0
1
P6n pin I/O mode selection (n = 3, 2)
Note
Output mode (output buffer on)
Input mode (output buffer off)
Caution Be sure to set the following bits to 1:
78K0/KC2-L: Bits 7 to 4
24
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
The initialization of serial interface IICA, slave transmission, and slave reception performed by the 78K0/KC2-L source program are shown below as a software coding example.
(1) Assembly language
<1> Initializing serial interface IICA (common to slave transmission and slave reception)
XMAIN CSEG UNIT
IRESET:
...(Omitted)...
P60/SCLA0 and P61/SDAA0 are specified as input ports so that port output does not affect the I
2
C bus.
MOV PM6, the I2C bus from being affected)
...(Omitted)...
; Specify P60 and P61 as input ports (to prevent
Set the transfer clock frequency to 400 kHz.
MOV IICWL,
Specify A0H as the local address.
MOV SVA0,
; Specify the low-level width
; Specify the high-level width
; Specify the local address
Specify the conditions
2 for starting I C communication.
MOV IICAF0,
...(Omitted)...
; IICA flag register 0
Enable acknowledge signals, specify an interrupt request to be generated at the falling edge of the ninth clock cycle, and enable an interrupt request to be generated when a stop condition is detected.
MOV IICACTL0,#00011100B
...(Omitted)...
MOV IICACTL1,#00001100B
; IICA control register 0
Specify fast mode as the operating mode and enable the digital filter.
; IICA control register 1
...(Omitted)...
Enable the I
2
C bus.
SET1 IICE0 ;
; Enable I2C bus output
MOV POM6,
Specify P60/SCLA0 and P61/SDAA0 to be used for the I
2
C bus.
; Set P60/SCLA0 and P61/SDAA0 to N-ch open-drain
MOV P6, #00000011B to high level
MOV PM6,
CLR1 IICAIF0
CLR1 IICAMK0
...(Omitted)...
Enable the
INTIICA0 interrupt.
SET1 WUP
NOP
NOP
; Set the P60/SCLA0 and P61/SDAA0 output latches
; Specify P60/SCLA0 and P61/SDAA0 as output ports
; Clear the INTIICA0 interrupt request
; Enable the INTIICA0 interrupt
; Enable the wakeup function
; Make the system wait (3 clocks or more)
Set up the wakeup function and then make the system enter the STOP mode.
Application Note U19691EJ1V0AN
25
CHAPTER 4 SETTING METHODS
<2> Slave transmission
MMAIN_LOOP:
...(Omitted)...
MOV A,
ADD A,
LMAIN300:
[HL]
#010H
Start slave transmission.
; Read the received data
; Create transmission data (received data + 10H)
; Start transmission system until
(enter the HALT mode)
...(Omitted)...
BT ACKD0,
CLR1 FMODE is not being communicated
SET1 WREL0
LMAIN310:
End slave transmission.
; Has an acknowledge signal been detected? Yes,
; The communication mode flag indicates that data
; Make the system exit the wait status
<3> Slave reception
MMAIN_LOOP:
...(Omitted)...
SET1 WREL0
LMAIN700:
HALT
(enter the HALT mode)
...(Omitted)...
MOV A, IICA
MOV [HL], A
CLR1 FREADY communicated
SET1 WREL0
Start slave reception.
; Make the system exit the wait status
; Make the system wait until communication ends
Read the received data.
; Read the received data
; Save the received data
; The ready flag indicates that data cannot be
; Make the system exit the wait status
1 byte is received.
26
Application Note U19691EJ1V0AN
CHAPTER 4 SETTING METHODS
(2) C language
<1> Initializing serial interface IICA (common to slave transmission and slave reception) void hdwinit(void){
...(Omitted)...
P60/SCLA0 and P61/SDAA0 are specified as input ports so that port output does not affect the I
2
C bus.
PM6 = /* Specify P60 and P61 as input ports (to prevent the
I2C bus from being affected) */
...(Omitted)...
IICWL = 10;
Set the transfer clock frequency to 400 kHz.
/* Specify the low-level width */
IICWH = 8;
SVA0 = local address.
/* Specify the high-level width */
Specify A0H as the
/* Specify the local address */
Specify the conditions for starting I
2
C communication.
IICAF0 = 0b00000000; /* IICA flag register 0 */
...(Omitted)... Enable acknowledge signals, specify an interrupt request to be generated at the falling edge of the ninth clock cycle, and enable an interrupt request to be generated when a stop condition is detected.
IICACTL0 = 0b00011100; /* IICA control register 0 */
...(Omitted)...
Specify fast mode as the operating mode and enable the digital filter.
/* IICA control register 1 */ IICACTL1 = 0b00001100;
...(Omitted)...
Enable the I
2
C bus.
IICE0 = 1; /*
/* Enable I2C bus output */
POM6 =
Specify P60/SCLA0 and P61/SDAA0 to be used for the I
2
C bus.
/* Set P60/SCLA0 and P61/SDAA0 to N-ch open-drain */
*/
/* Set the P60/SCLA0 and P61/SDAA0 output latches to P6 = high level */
PM6 = /* Specify P60/SCLA0 and P61/SDAA0 as output ports */
IICAIF0 =
IICAMK0 =
...(Omitted)... Enable the INTIICA0 interrupt.
WUP = 1; /* Enable the wakeup function */
NOP(); /* Make the system wait (3 clocks or more) */
NOP(); Set up the wakeup function and then make the system enter the STOP mode.
STOP(); /* Enter the STOP mode */
/* Clear the INTIICA0 interrupt request */
/* Enable the INTIICA0 interrupt */
Application Note U19691EJ1V0AN
27
CHAPTER 4 SETTING METHODS
<2> Slave transmission void main(void)
{
...(Omitted)...
Start slave transmission.
IICA = ( ucRxBuffer[ucCounter] + 0x10 );
/* 1 byte is being transmitted */ while( !ucReady ){
HALT();
HALT mode) */
/* Make the system wait until communication ends (enter the
...(Omitted)...
End slave transmission.
if( !ACKD0 ) { ucMode = 0; /* The communication mode flag indicates */
/* that data is not being communicated */
}
}
WREL0 = 1; /* Make the system exit the wait status */
<3> Slave reception void main(void)
{
...(Omitted)...
Start slave reception.
WREL0 = 1; /* Make the system exit the wait status */
/* 1 byte is being received */ while( !ucReady ){
HALT(); /* Make the system wait until communication ends (enter the
HALT mode) */
...(Omitted)... Read the received data. ucRxBuffer[ucCounter] = IICA; /* Read the received data */
...(Omitted)...
1 byte is received.
WREL0 = 1; /* Make the system exit the wait status */
28
Application Note U19691EJ1V0AN
CHAPTER 5 RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Document Name English
78K0/Kx2-L User’s Manual
78K/0 Series Instructions User’s Manual
RA78K0 Assembler Package User’s Manual Language
CC78K0 C Compiler User’s Manual
Operation
Language
Operation
PM+ Project Manager User’s Manual
78K0/Kx2-L
Application Note
Sample Program (Initial Settings) LED Lighting Switch Control
Application Note U19691EJ1V0AN
29
APPENDIX A PROGRAM LIST
As a program list example, the 78K0/KC2-L microcontroller source program is shown below. z main.asm (assembly language version)
;*******************************************************************************
;
;
;
NEC Electronics 78K0/KC2-L Series
;*******************************************************************************
; 78K0/KC2-L Series Sample Program (Serial Interface IICA)
;*******************************************************************************
;*******************************************************************************
;<<History>>
; 2009.1.-- Release
;*******************************************************************************
;
;<<Overview>>
;
; This sample program presents an example of using serial interface IICA.
; 16 bytes of data are transmitted and received via the I2C bus in slave operation.
;
;
; <Primary initial settings>
;
; (Option byte settings)
; - Allowing the internal low-speed oscillator to be programmed to stop
; - Disabling the watchdog timer
; - Setting the internal high-speed oscillation clock frequency to 8 MHz
; - Disabling LVI from being started by default
; (Settings during initialization immediately after a reset ends)
; - Specifying the ROM and RAM sizes
; - Setting up I/O ports
; - Checking whether VDD is 2.7 V or more by using the low-voltage detector
; - Specifying that the CPU clock and peripheral hardware clock run on the internal
; high-speed oscillation clock (8 MHz)
; - Stopping the internal low-speed oscillator
; - Disabling peripheral hardware not to be used
; - Setting up serial interface IICA
;
→ Specifying fast mode as the operating mode and setting the transfer clock frequency to 400 kHz
;
→ Specifying A0H as the local address
; → Specifying that P60/SCLA0 and P61/SDAA0 are used for the I2C bus
; → Enabling the INTIICA0 interrupt
; - Enabling interrupts
;
30
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
;
; <Communication format>
;
; [Reception] ST + ADR/W + DT*16 + SP
; [Transmission] ST + ADR/R + DT*16 + SP
;
; ST : Start condition
; SP : Stop condition
; ADR/W : Slave address + W
; ADR/R : Slave address + R
; DT : Data
;
;
; <Address and data>
;
; Local address : A0H
; Reception data : 16 bytes (any)
; Transmission data : 16 bytes (every received byte is incremented by 10H and then transmitted)
;
;
; <I/O port settings>
; Output: P60, P61
; * Set all unused ports that can be specified as output ports as output ports.
;
;*******************************************************************************
;===============================================================================
;
;
;===============================================================================
DW RESET_START ;0000H RESET input, POC, LVI, WDT
Application Note U19691EJ1V0AN
31
APPENDIX A PROGRAM LIST
DW IINTIICA0 INTIICA0
;===============================================================================
;
; Define the RAM data table
;
;===============================================================================
DRAM DSEG SADDR
RIICINFO: DS 1
FMODE
FREADY
FDIR
EQU RIICINFO.7 ; Communication mode flag
; 0: Data is not being communicated
; 1: Data is being communicated
EQU RIICINFO.5 ; Ready flag
; 0: Data cannot be communicated
; 1: Data can be communicated
EQU RIICINFO.6 ; Communication direction flag
; EQU RIICINFO.4
; EQU RIICINFO.3
; EQU RIICINFO.2
; EQU RIICINFO.1
; EQU RIICINFO.0
RRXBUF:
RRXBUFE:
DS 16 ; Reception data save area (16 bytes)
; Last address of reception data save area + 1
;===============================================================================
;
32
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
;
;
Define the memory stack area
;===============================================================================
DSTK DSEG IHRAM
STACKEND:
DS
STACKTOP:
20H ; Memory stack area = 32 bytes
; Start address of the memory stack area
;*******************************************************************************
;
;
;
Servicing interrupts by using unnecessary interrupt sources
;*******************************************************************************
IINIT:
; If an unnecessary interrupt occurred, the processing branches to this line.
; The processing then returns to the initial original processing because no processing is performed here.
RETI
;*******************************************************************************
;
; Initialization after RESET
;
;*******************************************************************************
RESET_START:
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; Set up the register bank
;-------------------------------------------------------------------------------
SEL RB0 ; Set up the register bank
;-------------------------------------------------------------------------------
; Specify the ROM and RAM sizes
;-------------------------------------------------------------------------------
; Note that the values to specify vary depending on the model.
; Enable the settings for the model to use. (The uPD78F0588 is the default model.)
;-------------------------------------------------------------------------------
; Setting when using uPD78F0581 or uPD78F0586
;MOV IMS, #042H ; Specify the ROM and RAM sizes
Application Note U19691EJ1V0AN
33
APPENDIX A PROGRAM LIST
; Setting when using uPD78F0582 or uPD78F0587
;MOV IMS, #004H ; Specify the ROM and RAM sizes
; Setting when using uPD78F0583 or uPD78F0588
MOV IMS, #0C8H ; Specify the ROM and RAM sizes
;-------------------------------------------------------------------------------
; Initialize the stack pointer
;-------------------------------------------------------------------------------
MOVW SP, #STACKTOP ; Initialize the stack pointer
;-------------------------------------------------------------------------------
; Initialize port 0
;-------------------------------------------------------------------------------
MOV P0, #00000000B ; Set the P00 to P02 output latches to low level
MOV PM0, #11111000B ; Specify P00 to P02 as output ports
;-------------------------------------------------------------------------------
; Initialize port 1
;-------------------------------------------------------------------------------
MOV
MOV
MOV
ADPC1, #00000111B
P1,
PM1,
#00000000B
#00000000B
; Specify P10 to P12 as digital I/O ports
; Set the P10 to P17 output latches to low level
; Specify P10 to P17 as output ports
;-------------------------------------------------------------------------------
; Initialize port 2
;-------------------------------------------------------------------------------
MOV
MOV
MOV
ADPC0, #11111111B
P2,
PM2,
#00000000B
#00000000B
; Specify P20 to P27 as digital I/O ports
; Set the P20 to P27 output latches to low level
; Specify P20 to P27 as output ports
;-------------------------------------------------------------------------------
; Initialize port 3
;-------------------------------------------------------------------------------
MOV P3, #00000000B ; Set the P30 to P33 output latches to low level
MOV PM3, #11110000B ; Specify P30 to P33 as output ports
;-------------------------------------------------------------------------------
; Initialize port 4
;-------------------------------------------------------------------------------
MOV P4, #00000000B ; Set the P40 to P42 output latches to low level
MOV PM4, #11111000B ; Specify P40 to P42 as output ports
34
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
;-------------------------------------------------------------------------------
; Initialize port 6
;-------------------------------------------------------------------------------
MOV PM6, #11110011B ; Specify P60 and P61 as input ports (to prevent the I2C bus from being affected)
; Specify P62 and P63 as output ports
MOV P6, #00000000B ; Set the P60 to P63 output latches to low level
;-------------------------------------------------------------------------------
; Initialize port 7
;-------------------------------------------------------------------------------
MOV P7, #00000000B ; Set the P70 to P75 output latches to low level
MOV PM7, #11000000B ; Specify P70 to P75 as output ports
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; The low-voltage detector is used to check whether VDD is 2.7 V or more.
;-------------------------------------------------------------------------------
; Set up the low-voltage detector
SET1 LVIMK
CLR1 LVISEL
CLR1 LVIMD low voltage is detected
; Disable the INTLVI interrupt
; Specify VDD as the detection voltage
±0.1 V
MOV LVIS, #00001001B ; Set the low-voltage detection level (VLVI) to 2.84
; Specify that an interrupt signal is generated when a
SET1 LVION ; Enable low-voltage detection
; Make the system wait until the low-voltage detector stabilizes (10 us or more)
MOV B, #5 ; Specify the number of counts
HINI100:
NOP
DBNZ B, $HINI100 ; Has the wait period ended? No,
; Make the system wait until VLVI is less than or equal to VDD
HINI110:
NOP
BT LVIF, $HINI110
CLR1 LVION
; VDD < VLVI? Yes,
; Stop the low-voltage detector
;-------------------------------------------------------------------------------
; Specify the clock frequency
;-------------------------------------------------------------------------------
; Specify the clock frequency so that the device can run on the internal high-speed
Application Note U19691EJ1V0AN
35
APPENDIX A PROGRAM LIST oscillation clock.
;-------------------------------------------------------------------------------
;
MOV OSCCTL,#00000000B ; Clock operation mode
||||+||+------- Be sure to clear this bit to 0
;
;
;
;
|||| ++-------- RSWOSC/AMPHXT
||||
||||
||||
[XT1 oscillator oscillation mode selection]
00: Low power consumption oscillation
01: Normal oscillation
;
;
;
;
;
|||| 1x: Ultra-low power consumption oscillation
||++----------- EXCLKS/OSCSELS
||
||
||
[Subsystem clock pin operation setting]
(P123/XT1,P124/XT2/EXCLKS)
Specify the use of the pin as an I/O port pin by specifying 000 by also using XTSTART
; ++------------- EXCLK/OSCSEL
;
;
[High-speed system clock pin operation setting]
(P121/X1,P122/X2/EXCLK)
;
;
;
;
00: Input port
01: X1 oscillation mode
10: Input port
11: External clock input mode
;
;
;
;
MOV PCC, #00000000B ; Select the CPU clock (fCPU)
;
;
;
||| |
||| |
[CPU clock (fCPU) selection]
0000:fXP
||| |
||| |
||| |
||| |
0001:fXP/2
0010:fXP/2^2
0011:fXP/2^3
0100:fXP/2^4
;
;
;
;
;
;
;
;
;
;
;
;
OSCSELS
;
||| |
||| |
||| |
||| |
||| |
||| |
1000:fSUB/2
1001:fSUB/2
1010:fSUB/2
1011:fSUB/2
1100:fSUB/2
(Other than the above: Setting prohibited)
||| +---------- Be sure to clear this bit to 0
||
|
|
[CPU clock status]
[Subsystem clock pin operation setting]
Specify the use of the pin by also using EXCLKS and
+-------------- Be sure to clear this bit to 0
MOV RCM, #00000010B ; Select the operating mode of the internal oscillator
;
; ||||||| [Internal high-speed oscillator oscillating/stopped]
36
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
;
;
;
;
;
;
;
;
;
|||||||
|||||||
||||||
||||||
||||||
0: Internal high-speed oscillator oscillating
1: Internal high-speed oscillator stopped
[Internal low-speed oscillator oscillating/stopped]
0: Internal low-speed oscillator oscillating
1: Internal low-speed oscillator stopped
|+++++--------- Be sure to clear this bit to 0
[Status of internal high-speed oscillator] clock
MOV MOC, #10000000B ; Select the operating mode of the high-speed system
;
;
|+++++++------- Be sure to clear this bit to 0
;
;
;
;
;
;
;
;
[Control of high-speed system clock operation]
0: X1 oscillator operating/external clock from
EXCLK pin is enabled
1: X1 oscillator stopped/external clock from
EXCLK pin is disabled ;
MOV MCM, #00000000B ; Select the clock to supply
;
||||| |
||||| |
||||| |
||||| |
[Clock supplied to main system and
peripheral hardware]
00: Main system clock (fXP)
= internal high-speed oscillation clock (fIH)
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
||||| |
|||||
Peripheral hardware clock (fPRS)
= internal high-speed oscillation clock (fIH)
01: Main system clock (fXP)
= internal high-speed oscillation clock (fIH)
Peripheral hardware clock (fPRS)
= internal high-speed oscillation clock (fIH)
10: Main system clock (fXP)
= internal high-speed oscillation clock (fIH)
Peripheral hardware clock (fPRS)
= high-speed system clock (fIH)
11: Main system clock (fXP)
= high-speed system clock (fIH)
Peripheral hardware clock (fPRS)
= high-speed system clock (fIH)
||||| +-------- MCS
[Main system clock status]
+++++---------- Be sure to clear this bit to 0
MOV PER0, #00000000B ; Control the real-time counter control clock
;
;
|+++++++------- Be sure to clear this bit to 0
; [Real-time counter control clock]
Application Note U19691EJ1V0AN
37
APPENDIX A PROGRAM LIST
;
;
0: Stop supply of control clock
1: Supply control clock
;-------------------------------------------------------------------------------
; Disable peripheral hardware not to be used
;-------------------------------------------------------------------------------
; 16-bit timer/event counter 00
MOV TMC00, #00000000B ; Disable the counter
; 8-bit timer/event counters 50 and 51
MOV TMC50, #00000000B ; Disable timer 50
MOV TMC51, #00000000B ; Disable timer 51
; 8-bit timer H0
MOV ; Stop the timer
MOV RTCC0, #00000000B ; Stop the counter
; Clock output controller
MOV CKS, #00000000B ; Stop the clock frequency divider
; A/D converter
MOV ADM0, #00000000B ; Stop A/D conversion
; Operational amplifiers
MOV AMP0M, #00000000B ; Stop operational amplifier 0
MOV AMP1M, #00000000B ; Stop operational amplifier 1
TMHMD0,
; Real-time counter
#00000000B
; Serial interface UART6
MOV ASIM6, #00000001B ; Disable the interface
; Serial interfaces CSI10 and CSI11
MOV
MOV
CSIM10,
CSIM11,
#00000000B ; Disable CSI10
#00000000B ; Disable CSI11
MOVW MK0, #0FFFFH
MOVW MK1, #0FFFFH
; Disable all interrupts
;
MOV EGPCTL0,#00000000B ; Disable the detection of all external interrupts
; Key interrupts
MOV KRM, #00000000B ; Disable all key interrupts
;-------------------------------------------------------------------------------
; Set up serial interface IICA
;-------------------------------------------------------------------------------
38
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
; - Specify fast mode as the operating mode and set the transfer clock frequency to
400 kHz
; - Specify A0H as the local address
;-------------------------------------------------------------------------------
; Set up the transfer clock
MOV IICWL, #10 ; Specify the low-level width
MOV IICWH, #8 ; Specify the high-level width
;
;
;
;
;
;
;
;
;
;
MOV SVA0, #0A0H ; Specify the local address
MOV IICAF0,#00000000B ; IICA flag register 0
|||||||+------- IICRSV
||||||| [Communication reservation function disable bit]
|||||||
|||||||
0: Enable communication reservation
1: Disable communication reservation
||||||+-------- STCEN
|||||| [Initial start enable trigger]
;
;
;
;
||||||
||||||
||||||
||||||
||||||
||||||
0: After operation is enabled (IICE0 = 1), enable
generation of a start condition upon detection
of a stop condition
1: After operation is enabled (IICE0 = 1), enable
generation of a start condition without
detecting a stop condition
||++++--------- Be sure to clear this bit to 0
|+------------- IICBSY <Read only>
;
;
|
| when STCEN = 1)
; |
[I2C bus status flag]
0: Bus release status (communication initial status
1: Bus communication status (communication initial status when STCEN = 0)
; +-------------- STCF <Read only>
;
;
;
;
;
;
;
;
;
;
;
;
0: Generate start condition
1: Start condition generation unsuccessful:
clear STT0 flag
MOV IICACTL0,#00011100B ; IICA control register 0
|||||||+------ SPT0
|||||||
|||||||
[Stop condition trigger]
0: Do not generate a stop condition
||||||| 1: Generate a stop condition
||||||+------- STT0
|||||| [Start condition trigger]
|||||| 0: Do not generate a start condition
|||||| 1: Generate a start condition
;
;
;
|||||+-------- ACKE0
||||| [Acknowledgment control]
||||| 0: Disable acknowledgment
Application Note U19691EJ1V0AN
39
APPENDIX A PROGRAM LIST
;
;
;
;
||||| 1: Enable acknowledgment
||||+--------- WTIM0
||||
||||
[Control of wait and interrupt request generation]
0: Interrupt request is generated at the eighth clock’s falling edge
; |||| 1: Interrupt request is generated at the ninth clock’s falling edge
; |||+---------- SPIE0
;
;
;
;
;
|||
|||
[Enable/disable generation of interrupt request
when stop condition is detected]
||| 0: Disable
||| 1: Enable
||+----------- WREL0
;
;
;
;
1)]
;
;
;
;
;
;
;
;
||
||
[Wait cancellation]
0: Do not cancel wait
|| 1: Cancel wait
|+------------ LREL0
;
;
; | sets standby mode
;
;
|
|
[Exit from communications]
0: Normal operation
1: This exits from the current communications and
+------------- IICE0
0: Stop operation
1: Enable operation
;
;
;
;
;
;
MOV IICACTL1,#00001100B ; IICA control register 1
||||||++------ Be sure to clear this bit to 0
|||||+-------- DFC0
||||| [Digital filter operation control]
;
;
;
;
|||||
|||||
0: Digital filter off
1: Digital filter on
||||+--------- SMC0
|||| [Operating mode switching]
;
;
;
1)]
||||
||||
0: Operates in standard mode
1: Operates in fast mode
|||+---------- DAD0
||| [Detection of SDA0 pin level (valid only when IICE =
|||
|||
0: The SDA0 pin was detected at low level
1: The SDA0 pin was detected at high level
||+----------- CLD0
|| [Detection of SCL0 pin level (valid only when IICE =
||
||
0: The SCL0 pin was detected at low level
1: The SCL0 pin was detected at high level
|+------------ Be sure to clear this bit to 0
+------------- WUP
40
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
;
;
;
;
;
[Control of address match wakeup]
0: Stop operation of address match wakeup
function in STOP mode
1: Enable operation of address match wakeup
function in STOP mode
; Enable I2C bus output
MOV POM6, #00000011B ; Set P60/SCLA0 and P61/SDAA0 to N-ch open-drain level
MOV P6, #00000011B ; Set the P60/SCLA0 and P61/SDAA0 output latches to high
MOV PM6, #11110000B ; Specify P60/SCLA0 and P61/SDAA0 as output ports
CLR1 IICAIF0
CLR1 IICAMK0
; Clear the INTIICA0 interrupt request
; Enable the INTIICA0 interrupt
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
BR MMAIN_LOOP ; Go to the main loop
;*******************************************************************************
;
;
;*******************************************************************************
MMAIN_LOOP:
; Initialize the variables to use
AND RIICINFO,#00011111B ; The communication mode flag indicates that data is not being communicated
; The ready flag indicates that data cannot be communicated is being received
LMAIN010:
BF FMODE, $LMAIN900 ; Is data being communicated? No,
BF FDIR, ; Is transmission specified as the communication direction? No,
;-------------------------------------------------------------------------------
; Transmission
;-------------------------------------------------------------------------------
Application Note U19691EJ1V0AN
41
APPENDIX A PROGRAM LIST
LMAIN100:
MOVW HL, #RRXBUF area
LMAIN200:
MOV
ADD
MOV
LMAIN300:
A,
A,
[HL]
#010H
IICA, A
; Specify the start address of the reception data save
; Read the received data
; Create transmission data (received data + 10H)
; Start transmission
HALT the HALT mode)
; Make the system wait until communication ends (enter
BF
BF
BF
CLR1 communicated
FMODE, $LMAIN900
FREADY
; Is data being communicated? No,
FDIR, $LMAIN500 ; Has the communication direction changed? Yes,
FREADY,$LMAIN300 ; Has 1 byte been transmitted? No,
; The ready flag indicates that data cannot be
BT ACKD0, $LMAIN310
CLR1 FMODE being communicated
SET1 WREL0
; Has an acknowledge signal been detected? Yes,
; The communication mode flag indicates that data is not
; Make the system exit the wait status
LMAIN310:
INCW HL ; Go to the next reception data save area
AX, ;
CMPW AX, #RRXBUFE ; Have all save areas been referenced?
BC $LMAIN200 No,
LMAIN320:
BR LMAIN010
;-------------------------------------------------------------------------------
; Reception
;-------------------------------------------------------------------------------
LMAIN500:
MOVW HL, #RRXBUF ; Specify the start address of the reception data save area
LMAIN600:
SET1 WREL0
LMAIN700:
HALT
; Make the system exit the wait status
; Make the system wait until communication ends (enter the HALT mode)
BF
BT
BF
FMODE, $LMAIN900
FDIR, $LMAIN100
; Is data being communicated? No,
; Reception? No,
FREADY,$LMAIN700 ; Has 1 byte been received? No,
MOV A, IICA
MOV [HL], A
CLR1 FREADY
; Read the received data
; Save the received data
; The ready flag indicates that data cannot be communicated
SET1 WREL0
INCW HL
; Make the system exit the wait status
; Go to the next reception data save area
42
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
CMPW
AX, ;
AX, #RRXBUFE ; Have all save areas been referenced?
BC $LMAIN600 No,
LMAIN900:
; Communication standby status
SET1 WUP ; Enable the wakeup function
; Make the system wait (3 clocks or more) NOP
NOP
STOP ; Enter the STOP mode
BR LMAIN010
;*******************************************************************************
;
;
;
INTIICA0 interrupt servicing (using the IICA communication end interrupt)
;*******************************************************************************
IINTIICA0:
CLR1
BF
WUP
SPD0, $HIICA300
; Stop the wakeup function
; Has a stop condition been detected? No,
;-------------------------------------------------------------------------------
; When a stop condition is detected
;-------------------------------------------------------------------------------
AND RIICINFO,#00011111B ; The communication mode flag indicates that data is not being communicated
; The ready flag indicates that data cannot be communicated is being received
BR HIICA900
HIICA300:
BF STD0, $HIICA700 ; Has a start condition been detected? No,
;-------------------------------------------------------------------------------
; When a start condition is detected
;-------------------------------------------------------------------------------
BF COI0, $HIICA500 ; Does the address match? No,
; Address match
MOV1 CY, TRC0 is being transmitted or received
; The communication direction flag indicates that data
SET1 FMODE being communicated
CLR1 FREADY communicated
; The communication mode flag indicates that data is
; The ready flag indicates that data cannot be
Application Note U19691EJ1V0AN
43
APPENDIX A PROGRAM LIST
BR HIICA900
HIICA500:
; Address mismatch
AND RIICINFO,#00011111B ; The communication mode flag indicates that data is not being communicated
; The ready flag indicates that data cannot be communicated is being received
BR HIICA900
;-------------------------------------------------------------------------------
; When data is transmitted or received
;-------------------------------------------------------------------------------
HIICA700:
SET1 FREADY ; The ready flag indicates that data can be communicated
HIICA900:
RETI end
44
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST z main.c (C language version)
/*******************************************************************************
NEC Electronics 78K0/KC2-L Series
********************************************************************************
78K0/KC2-L Series Sample Program (Serial Interface IICA)
********************************************************************************
********************************************************************************
<<History>>
********************************************************************************
<<Overview>>
This sample program presents an example of using serial interface IICA.
16 bytes of data are transmitted and received via the I2C bus in slave operation.
<Primary initial settings>
(Option byte settings)
- Allowing the internal low-speed oscillator to be programmed to stop
- Disabling the watchdog timer
- Setting the internal high-speed oscillation clock frequency to 8 MHz
- Disabling LVI from being started by default
(Settings during initialization immediately after a reset ends)
- Specifying the ROM and RAM sizes
- Setting up I/O ports
- Checking whether VDD is 2.7 V or more by using the low-voltage detector
- Specifying that the CPU clock and peripheral hardware clock run on the internal
high-speed oscillation clock (8 MHz)
- Stopping the internal low-speed oscillator
- Disabling peripheral hardware not to be used
- Setting up serial interface IICA
→ Specifying fast mode as the operating mode and setting the transfer clock frequency to 400 kHz
→ Specifying A0H as the local address
→ Specifying that P60/SCLA0 and P61/SDAA0 are used for the I2C bus
→ Enabling the INTIICA0 interrupt
- Enabling interrupts
<Communication format>
[Reception] ST + ADR/W + DT*16 + SP
[Transmission] ST + ADR/R + DT*16 + SP
Application Note U19691EJ1V0AN
45
APPENDIX A PROGRAM LIST
ST : Start condition
SP : Stop condition
ADR/W : Slave address + W
ADR/R : Slave address + R
DT : Data
<Address and data>
Local address : A0H
Reception data : 16 bytes (any)
Transmission data : 16 bytes (every received byte is incremented by 10H and then transmitted)
<I/O port settings>
Output: P60, P61
* Set all unused ports that can be specified as output ports as output ports.
*******************************************************************************/
/*==============================================================================
Preprocessing directive (#pragma)
==============================================================================*/
#pragma SFR /* SFR names can be described at the C source level */
#pragma DI /* DI instructions can be described at the C source level */
#pragma EI /* EI instructions can be described at the C source level */
#pragma NOP /* NOP instructions can be described at the C source level */
#pragma HALT /* HALT instructions can be described at the C source level */
#pragma STOP /* STOP instructions can be described at the C source level */
#pragma interrupt INTIICA0 fn_intiica0 RB1 /* Declare the interrupt function: INTIICA0
*/
/*==============================================================================
Define variables and constants
==============================================================================*/ static unsigned char ucMode; /* Communication mode flag */ static unsigned char ucReady; /* Ready flag */
46
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST static unsigned char ucDirection; /* Communication direction flag */
#define CDATANUM 16 /* Number of received data units */ static unsigned char ucRxBuffer[CDATANUM]; /* Reception data save area (16 bytes) */
/*******************************************************************************
Initialization after RESET
*******************************************************************************/ void hdwinit( void )
{
unsigned char ucCounter; /* Count variable */
/*------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Specify the ROM and RAM sizes
--------------------------------------------------------------------------------
Note that the values to specify vary depending on the model.
Enable the settings for the model to use. (The uPD78F0588 is the default model.)
------------------------------------------------------------------------------*/
/* Setting when using uPD78F0581 or uPD78F0586 */
/*IMS = 0x42;*/ /* Specify the ROM and RAM sizes */
/* Setting when using uPD78F0582 or uPD78F0587 */
/*IMS = 0x04;*/ /* Specify the ROM and RAM sizes */
/* Setting when using uPD78F0583 or uPD78F0588 */
IMS = 0xC8; /* Specify the ROM and RAM sizes */
/*------------------------------------------------------------------------------
Initialize port 0
------------------------------------------------------------------------------*/
P0 = /* Set the P00 to P02 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 1
------------------------------------------------------------------------------*/
Application Note U19691EJ1V0AN
47
APPENDIX A PROGRAM LIST
P1 = /* Set the P10 to P17 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 2
------------------------------------------------------------------------------*/
P2 = /* Set the P20 to P27 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 3
------------------------------------------------------------------------------*/
P3 = /* Set the P30 to P33 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 4
------------------------------------------------------------------------------*/
P4 = /* Set the P40 to P42 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 6
------------------------------------------------------------------------------*/ being affected) */
/* Specify P62 and P63 as output ports */
P6 = /* Set the P60 to P63 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 7
------------------------------------------------------------------------------*/
P7 = /* Set the P70 to P75 output latches to low level */
/*------------------------------------------------------------------------------
Initialize port 12
------------------------------------------------------------------------------*/
48
Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
The low-voltage detector is used to check whether VDD is 2.7 V or more.
------------------------------------------------------------------------------*/
/* Set up the low-voltage detector */
LVIMK = 1; /* Disable the INTLVI interrupt */
LVISEL = 0; /* Specify VDD as the detection voltage */
LVIMD = /* Specify that an interrupt signal is generated when a low voltage is detected */
LVION = 1; /* Enable low-voltage detection */
/* Make the system wait until the low-voltage detector stabilizes (10 us or more) */
for( ucCounter = 0; ucCounter < 2; ucCounter++ ){
NOP();
}
/* Make the system wait until VLVI is less than or equal to VDD */
while(LVIF){
NOP();
}
LVION = 0; /* Stop the low-voltage detector */
/*------------------------------------------------------------------------------
Specify the clock frequency
--------------------------------------------------------------------------------
Specify the clock frequency so that the device can run on the internal high-speed oscillation clock.
------------------------------------------------------------------------------*/
/* ||||+||+---- Be sure to clear this bit to 0 */
/* |||| ++----- RSWOSC/AMPHXT */
/* |||| [XT1 oscillator oscillation mode selection] */
/* |||| 00: Low power consumption oscillation */
/* |||| 01: Normal oscillation */
/* |||| 1x: Ultra-low power consumption oscillation */
/* ||++-------- EXCLKS/OSCSELS */
/* || [Subsystem clock pin operation setting] */
/* || (P123/XT1,P124/XT2/EXCLKS) */
/* || Specify the use of the pin as an I/O port pin by specifying 000 by also using XTSTART */
/* ++---------- EXCLK/OSCSEL */
/* [High-speed system clock pin operation setting] */
/* */
Application Note U19691EJ1V0AN
49
APPENDIX A PROGRAM LIST
/* 00: Input port */
/* 01: X1 oscillation mode */
/* 10: Input port */
/* 11: External clock input mode */
/* |||+|+++---- CSS/PCC2/PCC1/PCC0 */
/* ||| | [CPU clock (fCPU) selection] */
/* ||| | 0000:fXP */
/* ||| | 0001:fXP/2 */
/* ||| | 0010:fXP/2^2 */
/* ||| | 0011:fXP/2^3 */
/* ||| | 0100:fXP/2^4 */
/* ||| | 1000:fSUB/2 */
/* ||| | 1001:fSUB/2 */
/* ||| | 1010:fSUB/2 */
/* ||| | 1011:fSUB/2 */
/* ||| | 1100:fSUB/2 */
/* ||| | (Other than the above: Setting prohibited) */
/* ||| +------- Be sure to clear this bit to 0 */
/* ||+--------- CLS */
/* || [CPU clock status] */
/* |+---------- XTSTART */
/* | [Subsystem clock pin operation setting] */
/* | Specify the use of the pin by also using EXCLKS and OSCSELS */
/* +----------- Be sure to clear this bit to 0 */
/* |||||||+---- RSTOP */
/* ||||||| [Internal high-speed oscillator oscillating/stopped] */
/* ||||||| 0: Internal high-speed oscillator oscillating */
/* ||||||| 1: Internal high-speed oscillator stopped */
/* ||||||+----- LSRSTOP */
/* |||||| [Internal low-speed oscillator oscillating/stopped] */
/* |||||| 0: Internal low-speed oscillator oscillating */
/* |||||| 1: Internal low-speed oscillator stopped */
/* |+++++------ Be sure to clear this bit to 0 */
/* +----------- RSTS */
/* [Status of internal high-speed oscillator] */
/* |+++++++---- Be sure to clear this bit to 0 */
/* +----------- MSTOP */
/* [Control of high-speed system clock operation] */
/* 0: X1 oscillator operating/external clock from EXCLK pin is enabled */
/* 1: disabled */
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Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
/* |||||+|+---- XSEL/MCM0 */
/* ||||| | [Clock supplied to main system and peripheral hardware] */
/* ||||| | 00: Main system clock (fXP) */
/* ||||| | = internal high-speed oscillation clock (fIH) */
/* ||||| | Peripheral hardware clock (fPRS) */
/* ||||| | = internal high-speed oscillation clock (fIH) */
/* ||||| | 01: Main system clock (fXP) */
/* ||||| | = internal high-speed oscillation clock (fIH) */
/* ||||| | Peripheral hardware clock (fPRS) */
/* ||||| | = internal high-speed oscillation clock (fIH) */
/* ||||| | 10: Main system clock (fXP) */
/* ||||| | = internal high-speed oscillation clock (fIH) */
/* ||||| | Peripheral hardware clock (fPRS) */
/* ||||| | = high-speed system clock (fIH) */
/* ||||| | 11: Main system clock (fXP) */
/* ||||| | = high-speed system clock (fIH) */
/* ||||| | Peripheral hardware clock (fPRS) */
/* ||||| | = high-speed system clock (fIH) */
/* ||||| +----- MCS */
/* ||||| [Main system clock status] */
/* +++++------- Be sure to clear this bit to 0 */
/* |+++++++---- Be sure to clear this bit to 0 */
/* +----------- RTCEN: */
/* [Real-time counter control clock] */
/* 0: Stop supply of control clock */
/* 1: Supply control clock */
/*------------------------------------------------------------------------------
Disable peripheral hardware not to be used
------------------------------------------------------------------------------*/
/* 16-bit timer/event counter 00 */
/* 8-bit timer/event counters 50 and 51 */
/* 8-bit timers H0 and H1 */
/* Real-time counter */
Application Note U19691EJ1V0AN
51
/* Clock output controller */
/* A/D converter */
/* Operational amplifiers */
APPENDIX A PROGRAM LIST
/* Serial interface UART6 */
/* Serial interfaces CSI10 and CSI11 */
/* Interrupts */
MK0 = 0xFFFF; /* Disable all interrupts */
EGPCTL0 = /* Disable the detection of all external interrupts */
EGPCTL1 =
/* Key interrupts */
/*------------------------------------------------------------------------------
Set up serial interface IICA
--------------------------------------------------------------------------------
- Specify fast mode as the operating mode and set the transfer clock frequency to 400 kHz
- Specify A0H as the local address
-------------------------------------------------------------------------------*/
/* Set up the transfer clock */
IICWL = 10; /* Specify the low-level width */
IICWH = 8; /* Specify the high-level width */
SVA0 = 0xA0; /* Specify the local address */
/*
/* ||||||| [Communication reservation function disable bit] */
/* ||||||| 0: Enable communication reservation */
/* ||||||| 1: Disable communication reservation */
/*
/*
/* |||||| 0: After operation is enabled (IICE0 = 1), enable */
/* |||||| generation of a start condition upon detection */
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APPENDIX A PROGRAM LIST
/* |||||| of a stop condition */
/* |||||| 1: After operation is enabled (IICE0 = 1), enable */
/* |||||| generation of a start condition without */
/* |||||| detecting a stop condition */
/* ||++++-------- Be sure to clear this bit to 0 */
/*
/*
/* | 0: Bus release status (communication initial status when STCEN
= 1) */
/* | 1: Bus communication status (communication initial status when
STCEN = 0) */
/*
/*
/*
/*
IICACTL0 = 0b00011100; /* IICA control register 0 */
/* |||||||+-----
/* ||||||| [Stop
/* ||||||| 0: Do not generate a stop condition */
/* ||||||| Generate stop
/* ||||||+------
/* ||||||
/* |||||| 0: Do not generate a start condition */
/* |||||| Generate condition */
/* |||||+-------
/* |||||
/* |||||
/* |||||
/* ||||+--------
/* |||| [Control of wait and interrupt request generation] */
/* |||| 0: Interrupt request is generated at the eighth clock’s falling edge */
/* |||| 1: Interrupt request is generated at the ninth clock’s falling edge */
/* |||+---------
/* ||| [Enable/disable generation of interrupt request */
/* ||| when stop condition is detected] */
/* |||
/* |||
/* ||+----------
/* ||
/* ||
/* ||
/* |+-----------
/* |
/* |
Application Note U19691EJ1V0AN
53
APPENDIX A PROGRAM LIST
/* | 1: This exits from the current communications and sets standby mode */
/* +------------
/*
/*
IICACTL1 = 0b00001100; /* IICA control register 1 */
/* ||||||++----- Be sure to clear this bit to 0 */
/* |||||+-------
/* |||||
/* |||||
/* |||||
/* ||||+--------
/* |||| [Operating
/* ||||
/* ||||
/* |||+---------
/* ||| [Detection of SDA0 pin level (valid only when IICE = 1)] */
/* ||| 0: The SDA0 pin was detected at low level */
/* ||| 1: The SDA0 pin was detected at high level */
/* ||+----------
/* || [Detection of SCL0 pin level (valid only when IICE = 1)] */
/* || 0: The SCL0 pin was detected at low level */
/* || 1: The SCL0 pin was detected at high level */
/* |+----------- Be sure to clear this bit to 0 */
/* WUP */
/* [Control wakeup] */
/* 0: Stop operation of address match wakeup */
/* function
/* 1: Enable operation of address match wakeup */
/* function
IICE0 = 1; /* Enable I2C */
/* Enable I2C bus output */
P6 = /* Set the P60/SCLA0 and P61/SDAA0 output latches to high level */
IICAIF0 = 0; /* Clear the INTIICA0 interrupt request */
IICAMK0 = 0; /* Enable the INTIICA0 interrupt */
/*-----------------------------------------------------------------------------
Enable interrupts
------------------------------------------------------------------------------*/
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Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
}
/*******************************************************************************
*******************************************************************************/ void main(void)
{
unsigned char ucCounter; /* Count variable */
/* Initialize the variables to use */
= /* The communication mode flag indicates that data is not being communicated */
ucReady = 0; /* The ready flag indicates that data cannot be communicated */ received */
/* Data is being communicated */ while( ucMode ){
/*---------------------------------------------------------------------
Transmission
---------------------------------------------------------------------*/
/* Transmit the specified number of bytes of data */ for( ucCounter = 0; ucCounter < CDATANUM; ucCounter++ ){
/* Process the received data and then transmit it */
IICA = ( ucRxBuffer[ucCounter] + 0x10 );
/* 1 byte is being transmitted */
HALT(); /* Make the system wait until communication ends (enter the
HALT mode) */
/* If data is not being communicated, or */
ucCounter /* Suspend transmission and put communication on standby */
break;
}
} ucReady = 0; /* The ready flag indicates that data cannot be communicated
*/
Application Note U19691EJ1V0AN
55
APPENDIX A PROGRAM LIST
/* No acknowledge signals are detected */ ucMode = 0; /* The communication mode flag indicates */
}
}
WREL0 = 1; /* Make the system exit the wait status */
}
/*---------------------------------------------------------------------
Reception
---------------------------------------------------------------------*/
else{
/* Receive the specified number of bytes of data */ for( ucCounter = 0; ucCounter < CDATANUM; ucCounter++ ){
WREL0 = 1; /* Make the system exit the wait status */
/* 1 byte is being received */ the HALT mode) */
/* If data is not being communicated, or */
ucCounter (CDATANUM specified number of bytes */ communication on standby */
}
}
/* If the received number of data units does not exceed the specified number of bytes */ ucCounter ){ ucRxBuffer[ucCounter] = IICA; /* Read the received data */
} ucReady = 0; /* The ready flag indicates that data cannot be communicated
*/
}
/* If the specified number of bytes have been received */ if( ucCounter == CDATANUM ){ ucMode = 0; /* The communication mode flag indicates that data is not being communicated */
}
WREL0 = 1; /* Make the system exit the wait status */
}
}
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Application Note U19691EJ1V0AN
APPENDIX A PROGRAM LIST
/* Communication standby status */
WUP = 1; /* Enable the wakeup function */
NOP(); /* Make the system wait (3 clocks or more) */
NOP();
STOP(); /* Enter the STOP mode */
}
}
/*******************************************************************************
INTIICA0 interrupt servicing (using the IICA communication end interrupt)
*******************************************************************************/
__interrupt void fn_intiica0(void)
{
WUP = 0; /* Stop the wakeup function */
/*-----------------------------------------------------------------------------
When a stop condition is detected
-----------------------------------------------------------------------------*/
if( SPD0 ){ ucDirection = 0; received */ ucMode = 0; /* The communication mode flag indicates that data is not being communicated */ ucReady = 0; /* The ready flag indicates that data cannot be communicated */
}
else{
/*-------------------------------------------------------------------------
When a start condition is detected
-------------------------------------------------------------------------*/ if( STD0 ){
/* Address match */ ucDirection = TRC0; /* The communication direction flag indicates that data is being transmitted or received */ ucMode = 1; /* The communication mode flag indicates that data is being communicated */ communicated */
}
/* Address mismatch */
else{ ucDirection = 0; /* The communication direction flag indicates that data is being received */ ucMode = 0; /* The communication mode flag indicates that data is not being communicated */
Application Note U19691EJ1V0AN
57
APPENDIX A PROGRAM LIST communicated */
}
}
/*-------------------------------------------------------------------------
When data is communicated
-------------------------------------------------------------------------*/ else{ ucReady = 1; /* The ready flag indicates that data can be communicated */
}
}
}
58
Application Note U19691EJ1V0AN
APPENDIX B USING 78K0/KC2-L 44-PIN PRODUCTS
All 78K0/KC2-L sample programs are intended for 48-pin products. To use a 78K0/KC2-L sample program for a 44pin product, specify the following settings:
(1) Initial settings of ports
• Setting up port 0
Change the value of bit 2 of port mode register 0 (PM0) from “0” to “1”.
• Setting up port 4
Change the value of bit 2 of port mode register 4 (PM4) from “0” to “1”.
• Setting up port 7
Change the values of bits 5 and 4 of port mode register 7 (PM7) from “00” to “11”.
(2) Disabling unused peripheral hardware
Delete the instruction used to set up the clock output selection register (CKS).
Application Note U19691EJ1V0AN
59
APPENDIX C REVISION HISTORY
Edition Date Page
1st edition September 2009
−
Revision
−
60
Application Note U19691EJ1V0AN
For further information, please contact:
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111 http://www.necel.com/
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Tel: 408-588-6000
800-366-9782 http://www.am.necel.com/
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Tel: 02-667541
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Tel: 040 265 40 10
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Tel: 010-8235-1155 http://www.cn.necel.com/
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Key features
- I2C bus slave operation
- 16-byte data transmission/reception
- Fast mode (400kHz)
- Sample program for implementation
- Detailed circuit diagram
- Flowcharts for program operation
- Software coding examples
- Register settings for IICA
- Interrupt handling
- Wakeup function