Technical Bulletin F re e s c a le S e m ic o n d u c to r, I n c . ..

Technical Bulletin F re e s c a le S e m ic o n d u c to r, I n c . ..

Freescale Semiconductor, Inc.

Rev 1.0 June 2001

Technical Bulletin

Design Considerations / Differences of MPC862SAR

Nigel Dick / European FAE Team

Netcomm Applications

Motorola, East Kilbride, Scotland

Section 1.0 Introduction

The MPC860SAR and MPC862SAR are both members of the MPC8xx PowerQUICC™ family. In addition to the standard MPC860MH capabilities, the MPC860SAR and MPC862SAR include the universal test and operations physical PHY interface for ATM called UTOPIA. Both devices also provide AAL5 and AAL0, segmentation and re-assembly (SAR) functionality, an ATM pace controller (APC) and transmission convergence (TC) sub-layer for

E1/DS1 and xDSL which is implemented by the serial channels.

In addition to these features, the allows the user to have simultaneous MII (Media Independent Interface) and

UTOPIA capability while still maintaining backwards compatibility with the existing MPC860SAR controller.

These particular features make the 862SAR a very adaptable ATM SAR controller that can be used for a variety of

ATM applications. Typical examples include:

• ATM line card controllers

• ATM to WAN interworking (frame relay, T1/E1 circuit emulation, xDSL applications)

• ATM25 applications.

• Residential broadband network interface units (ATM-to-Ethernet)

• High performance set-top controller.

• Bridging and routing applications.

The MPC862SAR is an enhanced version of the MPC860SAR. Although the MPC862SAR is pin compatible with both the MPC860 and MPC860SAR, a number of small, but significant programming changes have to be made to accommodate differences between the controllers.

The MPC857SART is a low cost derivative of the MPC862SAR including the same basic feature set with the exception that only 1 SCC is available to the user. Before selecting the MPC857SART as the host processor, careful consideration should be given as to whether the 1 SCC is capable of providing enough performance for the target application. In this instance, the use of the CPM PERFORMANCE SPREADSHEET given on the Motorola

Netcomm web page at “ http://www.mot.com/SPS/RISC/netcomm/tools/

”, is advised.

This document details the main differences in register and control bit settings that need to be taken into account when transitioning from the MPC8XXSAR to the Rev 0 MPC862SAR. The document references the “Enhanced

SAR Functionality Supplement to the MPC860 PowerQUICC™ User’s Manual” and the “MPC860

PowerQUICC™ User’s Manual”.

Both of these documents are available on the Motorola web site at the following URL:

“ http://www.mot.com/SPS/RISC/netcomm/docs/pubs/index.html

”.

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Section 2.0 ATM Enhancements

The MPC862 SAR has a number of additional features compared to the original MPC860 (Rev D and earlier revisions) of SAR. Table 1, below, details some of the additional features that the 862SAR processors can now support.

Table 1 – Main Functional Differences Between 860SAR & 862SAR

ATM

Feature

Clock frequency

UTOPIA interface.

Number of priority levels

(APC)

Memorymemory cell processing?

Port to Port switching ?

Simultaneo us MII &

UTOPIA operation ?

ATM APC

Queue

Handler ?

Backwards compatibilit y ?

UTOPIA -

Split Mode

Capability

(8-bit)

MPC860SAR

25 MHz

2

Yes, Serial loopback only.

Yes, only with

RAM microcode

No

No

Not applicable

No – 8 Shared data signals only (Mux mode)

MPC862SAR

50 MHz

Unlimited

Yes, Serial or UTOPIA loopback

Yes, no microcode needed!

Yes, when operating

UTOPIA in muxed bus

(Master) mode

** Yes, PTP queuing mechanism, flexible priority of queues

Yes, through the ESAR bits

Yes – Mux mode +

Split mode

(2 separate 8 bit Rx &

Tx buses in split mode).

* See last paragraph of section 5.1 - Parameter RAM conflicts

** APC Queue errata – this feature is currently broken on Rev E.0.

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Section 3.0 ATM Operational Differences

In order to highlight some of the operational differences between the 860SAR and the 862SAR, the reception and transmission of a typical ATM cell will be discussed for both processors.

3.1 ATM Cell Reception – 860SAR

1. Cell received from transmission line via UTOPIA interface and put into FIFO. When the RxClav signal (Receive

Cell Available) is found to be asserted by the PHY, the SAR will receive a cell from that PHY.

2. Read cell header. In SAR mode, the UTOPIA is controlled by microcode that uses 4 byte long registers. Hence, when the RxClav is sent to the CPM, the cell is read in to the processor four bytes at a time.

3. Address Look-up. Match the header to get the correct channel number.

4. Get parameters from memory.

5. Read data from PHY UTOPIA interface to the CPM. This involved calculating the CRC (Cyclic Redundancy

6.

Check) and also sending out the relevant address to the DMA for memory access.

The relevant parameters in memory are updated - Buffer descriptor pointers, CRC counters etc.

3.2 ATM Cell Reception – 862SAR

1. Cell received from transmission line via UTOPIA interface and put into FIFO When the RxClav signal (Receive

Cell Available) is found to be asserted by the PHY, the SAR will receive a cell from that PHY.

2. Read cell header. In 862SAR, there is a UTOPIA hardware block that reads the entire cell into an internal 2

cell FIFO in a minimal amount of time. Hence, when the RxClav is sent to the CPM, the cell (n bytes) is read in to the processor within (n) clock cycles.

3. Address Look-up. Match the header to get the correct channel number.

4. Get parameters from memory.

5. Read data from PHY UTOPIA interface to the CPM. This involved calculating the CRC (Cyclic Redundancy

Check) and also sending out the relevant address to the DMA for memory access.

6.

The relevant parameters in memory are updated i.e. Buffer descriptor pointers, counters etc.

The most noticeable difference between the 860SAR and 862SAR modes of operation is the actual implementation of how the whole cell is read into the CPM by the UTOPIA interface during cell reception. On the 860SAR, the

UTOPIA interface is controlled by microcode. However, the 862SAR has a cell FIFO that is implemented by the

UTOPIA hardware block and is independent from any microcode. This added 862SAR functionality requires some additional processing overheads although reading a cell takes a significantly shorter period of time on 862SAR compared to 860SAR.

For example, when the 860SAR reads a complete ATM cell of 53 bytes it takes between 300 – 500 CPM clock cycles depending on available bandwidth. The 862SAR, on the other hand, requires around 15-20% less clock cycles and is therefore much more efficient in terms of speed and bandwidth utilized.

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3.4 ATM Cell Transmission – 860SAR / 862SAR

The user-defined APC scheduler controls this process (assume IAQ bit is not set). The PHY will assert the TxClav signal (transmit cell available) when space is available in the PHY. If the APC is ready to transmit and space is available in the FIFO’s, the cell is transmitted.

1. If a cell is available (TxClav is asserted) and the APC scheduler is ready to transmit, then the channel number is read from the APC transmit queue.

2. Read channel parameters – buffer descriptors, counters etc.

3. Transmit header. If the cell to be transmitted is an AAL5 cell then the information resides in connection tables and parameter RAM. If the cell to be transmitted is an AAL0 cell then the information resides in memory.

4. Transmit payload. This includes direct memory access (DMA) from the buffers with optional cyclic redundancy

5. check (CRC).

Update parameters – parameter table entries.

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Section 4.0 Programming Considerations

In order to take advantage of the new features contained on the 862SAR device, a number of significant programming considerations must be taken into account. This is often a fundamental cause of many

860SAR/862SAR software bugs.

descriptors and data buffers required for 862SAR operation. Hence, this section of memory

MUST

be cleared during the initialization sequence prior to any 862SAR operation otherwise the 862SAR may not operate / may operate unpredictably.

bits must be cleared through the ESAR register set. The reason for this is to reduce the complexity of the internal microcode. Thus, the ESAR bits in registers SRSTATE, STSTATE, APCST should all be cleared. Similarly, if

862SAR functionality is required these bits should be set in all of the above registers.

the current CPM process. It is only possible to do this using the

WRITE_TO_MEMORY

command. Attempting to modify any memory location without using this command will cause system CPM failure. [Adding / removing internal channels and modifying the APC period can also be changed on-the-fly in both 860SAR and 862SAR modes.

Consult the supplementary 862SAR documentation at the following URL

“ http://www.mot.com/SPS/RISC/netcomm/docs/pubs/index.html

”, for further details].

0 to Rev A when using the Port–to–Port functionality.

In Rev 0, customers should ensure that the TB_PTR field inside any TCT (transmit connection table) used for PTP

(Point to Point connections) are initialised in the following manner:

The upper 16 bits (starting at offset 0x08 in the TCT) must be set to the same value as the receive buffer descriptor base pointer value (RBD_PTR). The lower 16 bits (starting at offset 0x0A in the TCT) must be cleared. This change will allow compatibility between revisions 0 and A. Software that is not initialised in this manner for Port-to-Port applications may exhibit erratic behaviour.

IMMR+0x3CB8, even for non-ATM applications, unless specifically required by Motorola. Rev A will reserve this location for internal CPM usage.

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Section 5.0 862SAR Mode - Internal Resource Conflicts

When operating an ATM application in 862SAR mode, the MPC862SAR loses some functionality due to internal resource conflicts. The following section details potential restrictions and conflicts that can arise.

5.1 Parameter RAM Conflicts

As 862SAR mode requires additional memory, users should be aware of the potential conflicts that can occur in parameter RAM. If operating in serial ATM mode on SCC1-4 or UTOPIA on SCC4, this will cause other peripherals to lose their parameter RAM. The serial ATM parameters of SCC1 extend into the I

2

C parameter

RAM. Similarly, the parameter RAM for SCC2/SPI, SCC3/SMC1 and SCC4/SMC2/PIP is affected in the same manner.

In order to relocate the parameter RAM for the SMC’s, I

2

C and SPI controllers to a non-conflicting location,

RAM- based microcode patches can be used. These microcode patches are available on the Motorola MPC8xx website - http://www.mot.com/SPS/RISC/netcomm/tools/ ”. (On MPC862 the relocation of the I2C/SPI does not require a RAM microcode patch. the device contains the relocatable I2C/SPI functionality and works as described in the pdf for the RAM loadable microcode of previous revisions.)

[On MPC862 Rev 0, a current bug in the implementation of the microcode means that when RAM microcodes are enabled, all information in the ROM microcode is lost at locations >=0x2000. The net result is that ATM functionality of the device is effectively lost. Currently no workaround exists although this bug should be resolved on silicon revision A.]

5.2 IDMA2 Conflicts

IDMA2 can only be used in level-sensitive mode when ATM is enabled. In order to achieve this mode, the user is required to set the RCCR[DR1M] bit.

5.3 UTOPIA Conflicts

The UTOPIA interface is implemented using the hardware of IDMA1 and the parameter RAM page of SCC4.

Therefore, if the UTOPIA port is used:

IDMA1 is unavailable. (The DREQ0 signal is lost, and the IDMA1 event and mask registers IDSR1 and

IDMR1 are used for UTOPIA events.) and REJECT4)

The UTOPIA interface can also be made to operate in either UTOPIA split bus mode of operation or using master mode operation. Depending on initial register programming, specific port pin functions become available or unavailable to the user:

In 862SAR multi-PHY mode:

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unavailable. However in UTOPIA muxed bus mode, the MII signals or the PCMCIA port A signals are still available on the PCMCIA port A pins.

In 862SAR multi-PHY mode: activated, the pin’s other signal functions become available. For example, if only eight PHYs are used in a

UTOPIA master application, the SMC1 data signals are still available.

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Section 6.0 Pin Assignment Comparison Between MPC860 &

MPC862SART

The table below illustrates the pin assignment differences between the MPC860 and the MPC862SART. The

Italic text displayed in green indicates 862SAR specific modes of operation.

PIN NAME

A2

CS1

A3

CE2_A/

MII-TXD3

A4

CS4

A5

WE3/BS_B3/PCWE

COMMENTS PIN NAME

862SAR Simultaneous

MII / UTOPIA

operation.

B1

UPWAITB/GPL_B4

B2

RD/WR

B3

CE1_A/

MII-TXD2

COMMENTS

862SAR Simultaneous

MII / UTOPIA operation.

A6

WE1/BS_B1/IOWR

A7

BS_A2

A8

VDDL

A9

A31

A10

A28

A11

A30

A12

A29

A13

A27

A14

A14

A15

A11

A16

A7

A17

A5

A18

A2

C1

UPWAITA/GPL_A4

C2

TA

C3

CS0

C4

CS7/CE(2)B

C5

GPL_A3/GPL_B3/CS3

C6

OE/GPL_A1/GPL_B1

C7

WE0/BS_B0/IORD

C8

BS_A1

C9

TSIZ1

C10

A26

C11

A24

C12

A20

C13

A16

C14

A12

C15

A9

C16

A3

C17

PB[31]/REJECT1/SPISEL

C18

PA[15]/RXD1

B4

CS5

B5

GPL_A2/GPL_B2/CS2

B6

WE2/BS_B2/PCOE

B7

MII_CRS

B8

BS_A3

B9

TSIZ0/REG

B10

A22

B11

A23

B12

A21

B13

A17

B14

A13

B15

A10

B16

A6

B17

A4

B18

A1

B19

A0

D1

TEA

D2

BDIP/GPL_B5

D3

GPL_A5

D4

CS2

D5

CS6/CE(1)B

D6

N/C

D7

GPL_A0/GPL_B0

D8

BS_A0

D9

A18

D10

A25

D11

A19

D12

A15

D13

N/C

D14

N/C

D15

A8

D16

PC[15]/DREQ0/RTS1/L1ST1/Rxclav

D17

PA[14]/TXD1

D18

PC[14]/DREQ1/L1ST2

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C19

PB[30]/SPICLK/RSTRT2

E1

BB

E2

BG

E3

BI

E4

CS3

E5

VDDH

E6

VDDH

E7

VDDH

E8

VDDH

E9

VDDH

E10

VDDH

E11

VDDH

E12

VDDH

E13

VDDH

E14

VDDH

E15

VDDH

E16

PB[29]/SPIMOSI

E17

PA[13]

E18

PC[13]/L1RQB/L1ST3

E19

PB[27]/I2CSDA/BRGO1

G1

IP_B3/IWP2/VF2

G2

IP_B4/LWP0/VF0

G3

FRZ/IRQ6

G4

BR

G5

VDDH

G6

GND

G7

GND

G8

GND

G9

GND

G10

GND

G11

GND

G12

GND

G13

GND

G14

GND

G15

VDDH

G16

PA[11]/L1TXDB

G17

TDO/DSDO

G18

TMS

G19

TRST

J1

ALE_B/DSCK/AT1

J2

IP_B2/IOIS16_B/AT2

J3

IP_B1/IWP1/VFLS1

J4

IP_B5/LWP1/VF1

J5

VDDH

J6

GND

J7

GND

J8

GND

J9

GND

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D19

PB[28]/SPIMISO/BRGO4

F1

BURST

F2

CR/IRQ3

F3

TS

F4

VDDH

F5

VDDH

F6

GND

F7

GND

F8

GND

F9

GND

F10

GND

F11

GND

F12

GND

F13

GND

F14

GND

F15

VDDH

F16

VDDH

F17

PA[12]

F18

PC[12]/L1RQA/L1ST4

F19

PB[26]/I2CSCL/BRGO2

H1

IP_B7/PTR/AT3

H2

IP_B0/IWP0/VFLS0

H3

RSV/IRQ2

H4

MII_COL

H5

VDDH

H6

GND

H7

GND

H8

GND

H9

GND

H10

GND

H11

GND

H12

GND

H13

GND

H14

GND

H15

VDDH

H16

TCK/DSDK

H17

TDI/DSDI

H18

MII_MDIO

H19

VDDL

K1

KR/IRQ4/RETRY/SPKROUT

K2

ALE_A/

MII-TXD1 862SAR Simultaneous

MII / UTOPIA operation

K3

IP_B6/DSDI/AT0

K4

BADDR30/REG

K5

VDDH

K6

GND

K7

GND

K8

GND

K9

GND

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J10

GND

J11

GND

J12

GND

J13

GND

J14

GND

J15

VDDH

J16

PB[25]/SMTXD1/

RXADDR3

/ TXADDR3

J17

PA[10]/L1RXDB

862SAR Multi-PHY mode operation only

K10

GND

K11

GND

K12

GND

K13

GND

K14

GND

K15

VDDH

K16

PB[21]/SMTXD2/L1CLKOB/

TXADDR1/

RXADDR1

K17

PB[23]/SMSYN1/SDACK1/

TXADDR2/

RXADDR2

K18

PA[9]/L1TXDA

862SAR Multi-PHY mode operation only

862SAR Multi-PHY mode operation only

J18

PB[24]/SMRXD1/

TXADDR3

/RXADDR3

J19

PC[11]/CTS1

862SAR Multi-PHY mode operation only

K19

PC[10]/CD1/TGATE1

L1

MODCK1/OP2/STS

L2

OP1

M1

VDDL

M2

BADDR29

L3

AS

M3

BADDR28

L4

OP0/

MII-TXD0/UtpClk_Aux 862SAR Simultaneous

M4

OP3/MODCK2/DSDO

MII / UTOPIA split bus operation.

L5

VDDH

L6

GND

M5

VDDH

M6

GND

L7

L8

L9

GND

GND

GND

L10

L11

L12

L13

L14

L15

GND

GND

GND

GND

GND

VDDH

L16

PB[20]/SMRXD2/L1CLKOA

/

TXADDR0/RXADDR0

L17

PA[8]/L1RXDA

L18

PC[9]

L19

PB[22]/SMSYN2/SDACK2/

TXADDR4/RXADDR4

862SAR Multi-PHY mode operation only

862SAR Multi-PHY mode operation only

M7

GND

M8

GND

M9

GND

M10

GND

M11

GND

M12

GND

M13

GND

M14

GND

M15

VDDH

M16

PC[7]/L1TSYNCB/SDACK2

M17

M18

M19

PA[6]/BRGCLK1/TOUT1/CLK2

PC8/TGATE2

PA[7]/CLK1/TIN1/L1RCLKA/BRGO1

N1

EXTAL

N2

EXTCLK

N3

TEXP

N4

HRESET

N5

VDDH

N6

GND

N7

GND

N8

GND

N9

GND

N10

GND

N11

GND

N12

GND

N13

GND

N14

GND

N15

VDDH

P1

P2

P3

P4

XTAL

SRESET

RSTCONF

VDDH

P5

VDDH

P6

GND

P7

GND

P8

GND

P9

GND

P10

GND

P11

GND

P12

GND

P13

GND

P14

GND

P15

VDDH

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N16

PB[16]/L1RQA/L1ST4/

TXADDR

0/RXADDR0

862SAR Multi-PHY mode operation only

N17

PB[18]/L1ST2/RTS2/

RXADDR4

/TXADDR4

862SAR Multi-PHY mode operation only

N18

PA5/CLK3/TIN2/L1TCLKA/BRG

OUT2

N19

PB[19]/L1ST1/RTS1

P16

VDDH

P17

PA[3]/CLK5/TIN3/BRGOUT3

P18

PB[17]/L1RQB/L1ST3/

DDR1

P19

PA[4]/TOUT2/CLK4

TXADDR1/RXA

862SAR Multi-PHY mode operation only

R1

KAPWR

R2

PORESET

R3

WAIT_A/

SOC_Aux

R4

R5

R6

WAIT_B

VDDH

VDDH

T1

VDDSYN

T2

XFC

862SAR Simultaneous

MII / UTOPIA split bus operation.

T3

IP_A7/

UTPB_Aux7/MII-RXDV

T4

IP_A1/

UTPB_Aux1/MII-RXD2

T5

T6

IP_A0/

IP_A6/

UTPB_Aux0/MII-RXD3

UTPB_Aux6/MII-TX-ERR

862SAR Simultaneous

MII / UTOPIA operation.

862SAR Simultaneous

MII / UTOPIA operation.

862SAR Simultaneous

MII / UTOPIA operation.

862SAR Simultaneous

MII / UTOPIA operation.

R7

VDDH

R8

VDDH

R9

VDDH

R10

VDDH

R11

VDDH

R12

VDDH

R13

VDDH

R14

VDDH

R15

VDDH

R16

PD[12]/L1RSYNCB/

MII-

MDC/UTPB3

R17

PB[15]/BRGO3/Txclav

R18

PA[2]/CLK6/TOUT3/L1RCL

KB/BRGCLK2

R19

PC[6]/L1RSYNCB

Available only in simultaneous MII &

UTOPIA operation

T7

D31

T8

D25

T9

D22

T10

D15

T11

D9

T12

D17

T13

D12

T14

VDDH

T15

PD[7]/MII-RX-ERR/UTPB4

T16

PD[11]/

MII-TX-ERR RXD3/RXENB

T17

T18

T19

PC[4]/L1RSYNCA

PC[5]/L1TSYNCA/SDACK1

PA[1]/CLK7/TIN4/BRGO4

Available only in simultaneous MII &

UTOPIA operation

U1

VSSSYN

U2

N/C

U3

IP_A2/IOIS16_A/

UTPB_Aux

2/MII-RXD1

U4

IP_A4/

RXCLK

U5

ERR

U6

U7

IP_A5/

D30

D26

UTPB_Aux4/MII-

UTPB_Aux5/MII-RX-

V1

VSSSYN1

V2

N/C

862SAR Simultaneous

MII / UTOPIA

V3

DP0/IRQ3

operation.

862SAR Simultaneous

V4

DP3/IRQ6

MII / UTOPIA operation.

862SAR Simultaneous

MII / UTOPIA operation.

V5

DP1/IRQ4

V6

D28

V7

D24

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U8

D21

U9

D19

U10

D16

U11

D11

U12

D23

U13

D8

U14

IRQ1

U15

PD[5]/

MII-

TXD3

/REJECT2/UTPB6

U16

TXD2

U17

PD[4]/

MII-

/REJECT3/UTPB7

PD[15]/L1TSYNCA/

RXD3

/UTPB0

MII-

U18

PB[14]/RSTRT1/

RXADDR2

Available only in simultaneous MII &

UTOPIA operation

Available only in simultaneous MII &

UTOPIA operation

Available only in simultaneous MII &

UTOPIA operation

U19

KB

PA[0]/CLK8/TOUT4/L1TCL

V8

D20

V9

D18

V10

D14

V11

D10

V12

D27

V13

D13

V14

IRQ0

V15

MII_TX_EN

V16

PD[6]/

MII-RXDV

/RTS4/UTPB5

Available only in simultaneous MII &

UTOPIA operation

Available only in

V17

PD[9]/

MII-TXD0

/RXD4/UTPCLK

simultaneous MII &

UTOPIA operation

V18

PD[13]/L1TSYNCB/

MII-RXD1

/UTPB2

Available only in simultaneous MII &

UTOPIA operation

V19

PD[14]/L1RSYNCA/

MII-RXD2

/UTPB1

Available only in simultaneous MII &

UTOPIA operation

W2

IP_A3/UTPB_Aux3/MII-

RXD0

W3

CLKOUT

W4

DP2/IRQ5

W5

D29

W6

D7

W7

D6

W8

VDDL

W9

D5

W10

D3

W11

D2

W12

D1

W13

D4

W14

D0

W15

IRQ7/MII_TXCLK

W16

PD[3]/MII-TXD1/SOC

W17

PD[8]/TXD4/

MII-

RX_CLK/MII-MDC

W18

PD[10]/TXD3/MII-

RXD0/TXENB

862SAR

Simultaneous MII /

UTOPIA operation.

Available only in simultaneous MII &

UTOPIA operation

Available only in simultaneous MII &

UTOPIA operation

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12

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7.0 Register Comparison Between 860SAR & 862SAR

The following spreadsheets detail the differences between 860SAR and 862SAR throughout the register set of the MPC8XX:

Connection Tables -

SAR vs ESAR

Receive Function Code & Status

Register

Base

Field

0 1 2 3

BO

4 5 6

FC

7 8

EXT

9

ACP

10

EC*

11

SNC*

12

ESAR

13

MCF

14

SER

15

MPHY

*

ESAR Must also be set to enable ESAR

MCF functionality

Enable management cell filter

* Available only in SCC4 UTOPIA mode; otherwise written as 0

Transmit Function

Code & Status

Register

Base

Field

0 1 2 3

BO

4

ESAR Must also be set to enable ESAR functionality

* Available only in SCC4 UTOPIA mode; otherwise written as 0

5 6

FC

7 8

EXT

9 10

EC*

11

SNC*

12

ESAR

13 14

SER

15

MPHY

*

APC

Status

Registe r

Base

Field

0 1

CSE

R

2 3

NSE

R

4 5 6

*

7 8 9

**

10

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11 12

ESAR

13

DIS

14

PL2**

*

15

MHY

ESAR

*

**

PL2***

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Must also be set to enable ESAR functionality

Was NMPHY on SAR, now bits [2..6] in MPHY status register on ESAR

Was CMPHY on SAR, now bits [10..14] in MPHY status register on ESAR

Used only if ESAR is not set for backwards compatibility with the MPC860SAR

MPHY

Status

Registe r

Base

Field

0 1 2

NMPHY

CMPHY

Number of

Multiple PHY's

Current Multiply

PHY

3 4

NMPH

Y

5 6 7 8 9 10 11 12

CMPH

Y

13 14 15

CPM

Comm and

Registe r

Base

Field RST

0

ATM

OPCOD

E

OPCODE

2

1 2

ATM OPCODE

3 4 5

OPCODE=1111

6 7 8

CH_

NU

M

111 = ATM ESAR Write to Memory Command or internal command (see OPCODE 2)

00 = RESERVED, normal ATM OPCODES apply when 00 is written to these two bits

01 = ACTIVATE PM - to activate PM session on the channel number specified by the COMM_CH field. *

10 = DEACTIVATE PM - To deactivate PM session on the channel number specified by the COMM_CH field. *

11 =

RE

SE

RV

ED

9

* OPCODE 2 commands are only valid when ATM OPCODE=111

10

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11 12 13

OPC

OD

E 2

14 15

FLG

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ESAR APC Status Register

(From APC Parameter RAM)

Base

Field

0

APCOM

*

1

*

APCOM

LAST

EQ

ESAR

DIS

MPHY

2

LAST

Rese rved

3

*

4 5

APC table overrun event mask for this

APC level.

This priority level is the last APC level for the specific PHY#.

6 7 8 9

APC table and PTP queue of this specific level have equal priority. The APC mechanism will schedule cells to be the DIS bit is NOT set.

Selects the new features of ESAR or allows backward compatibility with the older

SAR functionality. To enable

ESAR functionality, all bits must be programmed to the desired value throughout the ESAR register set.

10

APC table is disabled at this level. PTP queue will still be serviced. All lower levels down to LAST will still be serviced.

ESAR spec) to avoid conflict.

All M-PHY bits (throughout the ESAR register set) should be set to desired values when working with multi-PHY.

UTOPIA Mode Event Register

Base

Field

0

GUN

GOV

1 2 3 4 5 6

SYN

C

IQOV GINT

Global transmitter underrun in UTOPIA's tx cell FIFO.

GUN

Global receiver underrun in UTOPIA's rx cell FIFO.

7

GOV

11

EQ

12

ESAR

13

DIS

14

*

15

MPHY

Interrupt Queue

Entry

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Base

Field

1

W

2 3

CNG

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4 5 6 7 8

APC0

9 10

TQF

11

UN

12

RXF

Transmit queue full - this bit is valid in case that an APC bypass command was issued and the Transmit queue

13

BSY

14

TXB

15

RX

B where ITQ option is set.

Performance

Monitoring

Section 4.3 covers this new feature for ESAR. Correct configuration is achieved by programming table 4-2.

Connection Tables - SAR vs ESAR

Receive Connection Table - RCT

Base

CT_Offset + 0

CT_Offset + 2

CT_Offset + 4

CT_Offset + 6

CT_Offset + 8

CT_Offset + A

CT_Offset + C

CT_Offset + E

CT_Offset + 10

RB_P

TR

RTML

EN

RBD_

PTR

RBA

SE

0

FHN

T

PM

NCR

C

PTP

RBAL

EN

RCR

C

2 3 4 5 6 7

Performance

Monitoring

No CRC (AAL0 only) / Congestion (AAL5 only)

Port to Port cell switching / Congestion interrupt (AAL5 only)

8

HEC

9

CLP

10

CNG/

NCR

C

11

INF

12

CNGI

/PT

P

13

CDIS

14

AAL

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15

CT_Offset + 12

CT_Offset + 14

CT_Offset + 16

CT_Offset + 18 to

CT_Offset + 1F

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TSTA

MP

AAL2

AAL2

FT

FT

NIM

RPM

T

Reserv ed

IMAS

K

NIM RPM

T

Filter

Type

Non intrusive monitoring

Receive performance monitoring table number

Port to Port Specific Receive Connection Table - PTP RCT

When PTP function is used a new RCT must be defined called PTP RCT.

It is a specific RCT which must be initialized as page 2-15. All of the fields are new.

Transmit Connection Table

- TCT

Base

CT_Offset + 20

0

CT_Offset + 22

CT_Offset + 24

CT_Offset + 26

CT_Offset + 28

CT_Offset + 2A

CT_Offset + 2C

CT_Offset + 2E

CT_Offset + 30

CT_Offset + 32

2 3 4 5 6

PM

TBAL

EN

TCR

C

TB_P

TR

TTML

EN

TBD_

PTR

TBA

SE

Performance

Monitoring

TPM

TPM

T

Transmit Performance monitoring table number

7 8

PC

9 10 11

INF

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12

CR10

13

CDIS

14

AAL

AVC

F

15

ACT

CT_Offset + 34

CT_Offset + 36

CT_Offset + 38

CT_Offset + 3A

CT_Offset + 3C

CT_Offset + 3E

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T

AVC

F

ACT

Auto

VC off

Active

Statu s

CHE

AD

APCL

APC

PR

OUT

BNR

TSER

VICE

APC

P

APC

PF

TSE

R

APC

P

Buffer Not Ready (Internal Use)

Traffic service type

APCP <= 4094 instead of 32766 in SAR

Transmit connection Table Extensions TCTE

Located at TCTEBASE programmed in Parameter RAM, the TCTE are located in DPRAM.

They support VBR channels to hold additional parameters for traffic shaping.

Buffer Descriptors - SAR vs

ESAR

Receive Buffer

Descriptor

Base

Offset + 0

Offset + 2

0 2 3 4 5 6 7

E

F/OA

M

W I L F/OA

M

CM FMC

F (AAL5) First in

Frame.

OAM (AAL0) Operation and Maintenance cell indication.

Forward Monitoring Cell received + BRC fields added FMC

DATA LENGTH / Channel

Code

Data lengt h

Chann el

Number of bytes written into BD's data buffer (AAL5)

Channel number when AAL0 buffers + MCF bit set

8

HEC

9

CLP

10

CNG

11

ABT

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12 13 14

LN

15

CR

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Offset + 4

Offset + 8

Offset + A

Offset + C

Offset + 10

Offset + 14

Code

RX DATA BUFFER

POINTER

CPCS-

UU+

CPI

RESE

RVE

D

CELL HEADER

EXPANSION 1

CELL HEADER

EXPANSION 2

CELL HEADER

EXPANSION 3

Transmit Buffer

Descriptor

Base

Offset + 0

Offset + 2

Offset + 4

Offset + 8

Offset + A

Offset + C

Offset + 10

Offset + 14

0 2 3 4 5 6

R

OAM

ICNG

RH

W I L

User Cell / Non User Cell

Invert CNG bit (AAL5 only)

Replace header (AAL5 only)

ICLP Invert CLP bit (AAL5 only)

DATA

LEN

GTH

TX DATA BUFFER

POINTER

CPCS-UU+CPI/HEADER_L

OAM

HEAD

ER_L

Lower half word of the replacement header

Reserved/HEAD

ER_H

Upper half word of the replacement header HEAD

ER_

H

CELL HEADER

EXPANSION 1

CELL HEADER

EXPANSION 2

CELL HEADER

EXPANSION 3

CM

Parameter RAM Mapping - SAR vs

ESAR

7 8 9 10 11 12 13

ICNG

14

RH

15

ICLP

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Serial and Utopia Interface

Parameter RAM Map

Offset from

SCC Base

Name Description SAR Function

0x00

0x04

0x06

0x08

0x0C

0x10

0x12

0x14

0x18

0x1C

0x1E

0x20

0x22

0x24

0x28

0x2C

0x30

0x34

0x36

RBDBASE

SRFCR/SRSTATE

Base pointer for receive BDs

SAR receive function code and receive status

SRFCR/SRSTAE[12] does not exist

SRFCR/SRSTAE[13]= DIS

Disable Utopia receive process

TBDBASE

TSTATE

COMM_CH

STCHNUM

T_CNT

CTBASE

ECTBASE

INTBASE

INTPTR

C-MASK

SRCHNUM

INT_CNT

MRBLR

RSTATE

Reserved

R_CNT

STFCR/STSTATE

Maximum receive buffer length

SCC internal receive state parameters

Receive internal byte counter

STFCR/STSTATE[9] = TQF

Transmit Queue Full in 850SAR

STFCR/STSTATE[9] = Reserved in 860SAR until Rev C1

STFCR/STSTATE[9] = TQF

Transmit Queue Full in 860SAR in Rev D

STFCR/STSTATE[11] = PBF

Port B Flag

STFCR/STSTATE[12] = Reserved

Base pointer for transmit BDs

SCC internal transmit state parameters

Command channel

Current transmit channel number

Transmit internal byte counter

Connection table base address

External connection table base address

Interruput base pointer

Pointer to interrupt queue

Constant mask for CRC32

Current receive channel number

Interrupt counter

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ESAR Function

SRFCR/SRSTAE[12]= ESAR bit

Enable ESAR functions

SRFCR/SRSTAE[13]= MCF

Enable management cell filter

850 ESAR doesn't exist

STFCR/STSTATE[9] = Reserved

STFCR/STSTATE[9] = Reserved

STFCR/STSTATE[11] = Reserved

STFCR/STSTATE[12] = ESAR

Enable ESAR functions

0x38

0x3A

0x3C

0x3E

0x40

0x44

0x48

0x4A

0x4C

0x4E

0x50

INT_ICNT

TSTA

OLDLEN

SMRBLR

EHEAD

EPAYLOAD

TQBASE

TQEND

TQAPTR

TQTPTR

APCST

0x52

0x54

0x56

0x58

0x5A

0x5C

0x5E

0x60

APCPTR

AM1

AM2

AM3

AM4

AM5

ECSIZE

APCT_REAL

0x64

0x68

0x6C

0x70

R_PTR

RTEMP

T_PTR

TTEMP

0x74 to 0x7F Reserved

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Interrupt initial value

Time stamp timer address

Transmitter temporary length

SAR maximum receive buffer length register

Empty cell header

Empty cell payload

Transmit queue base pointer

Transmit queue end pointer

Transmit queue APC pointer

Transmit queue transmitter pointer

APC status

Number of multiple PHY

Current Multi PHY

Utopia Level 2 MPHY

Priority table Level 2

APC parameter pointer

Address match parameter

Address match parameter

Address match parameter

Address match parameter

Address match parameter

Expanded cell size/unassigned cell data

APC 32 bit counter

Receiver internal data pointer

Receiver temporary data storage

Transmit internal data pointer

Transmitter temporary data storage

APCST[5-7] = NMPHY

APCST[8-10] = CMPHY

APCST[12] = Reserved

APCST[14] = PL2

ESAR

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TQBASE: Reserved in MPHY mode

TQEND: Reserved in MPHY mode

TQAPT: Reserved in MPHY mode

TQTPTR: Reserved in MPHY mode

APCST[5-7] = Reserved

Reserved if ESAR bit in APCST = 1

APCST[8-10] = Reserved

Reserved if ESAR bit in APCST = 1

APCST[12] = ESAR

APCST[14] = PL2

Reserved if ESAR bit in APCST = 1

MPHY master: Points to MPHY

pointing table

ECSIZE: new configuration

Used internally by the APC for VBR traffic. Must be initialised to zero.

Parameters

Offset from

SCC Base

Name

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Description

0x80

0x84

0X88

0x8A

0x8C

FMCTIMESTMP

FMCTEMPLATE

PMPTR

PMCCHANNEL

Reserved

0x90

0x92

0x94

MPHYST

TCTEBASE

ETCTEBASE

0x98

0x9C

COMM_CH2

STATBASE

0x9C to 0xBF Reserved

OAM performance monitoring time stamp counter address

OAM performance monitoring - FMC template pointer

OAM performance monitoring table pointer

Temporary storage countaning pmchannel number

MultiPHY status

Internal TCT extension base

External TCT Extension Base pointer

Second host command channel / MSB = 0x0000

Statistics table base pointer

Serial Interface Parameter RAM Map

Offset from

SCC Base

Name Description

SAR Function

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

Doesn't exist

SAR Function

0xC0

0xC2

0xC4

0xC8

0xCA

0xCC

0xCE

0xD0

0xD2

0xD4

0xD8

0xDC

0xE0

0xE4

0xE8

ALPHA

DELTA

RSTUFF

SHUFFLESTATE

RHECTEMP

THECTEMP

ASTATUS

HEC_ERR

Reserved

RSCRAM

RSCRAM1

TSCRAM

TSCRAM1

RCRC

TCRC

Receiver delineation alpha/delta counters

Receiver delineation alpha/delta counters

Receive data stuffing location

Receiver data shuffling state

Receiver temporary HEC storage area

Transmitter temporary HEC storage area

Cell synchronization status register

HEC error counter

Receiver scrambling storage

Receiver scrambling storage

Transmitter scrambling storage

Transmitter scrambling storage

Receiver temporary CRC

Transmitter temporary CRC

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ESAR Function

ESAR Function

0xEC

0xF0

RCHAN

TCHAN

0xF4 to 0xFF Reserved

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Receiver current channel

Transmitter current channel

APC Parameter RAM Map

Offset from

APCPTR

Name Description

0x0E

0x10

0x12

0x14

0x16

0x00

0x02

0x04

0x06

0x08

0x0A

0x0C

APCT_BASE1

APCT_END1

APCT_PTR1

APCT_SPTR1

ETQBASE

ETQEND

ETQAPTR

ETQTPTR

APC_MI

NCITS

APCNT

APC table first priority base pointer

First APC table length

First APC pointer

First APC priority service pointer

Enhanced Transmit Queue base pointer

Enhanced Transmit Queue end pointer

Enhanced Transmit Queue APC pointer

Enhanced Transmit Queue transmitter pointer

APC - Maximum iteration

Number of cells in time slot

APC - N timer

Reserved

0x18

0x1A

0x1C

EAPCST

PTP COUNTER

PTP_TxCH

APC status of the first priority service

First priority PTP queue length

First priority PTP channel

0x1E

Reserved

* * * *

*

(n * 0x20) +

0x0

APCT_BASEn APC table— N’th priority table base pointer

N’th table — Length (n * 0x20) +

0x2

APCT_ENDn

(n * 0x20) +

0x4

APCT_PTRn N’th APC table pointer

SAR Function

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ESAR Function

(n * 0x20) +

0x6

APCT_SPTRn

(n * 0x20) + 0x8 -> +0x17 Reserved

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N’th table APC service pointer

(n * 0x20) +

0x18

EAPCSTn

(n * 0x20) +

0x1C

PTP_COUNTERn

(n * 0x20) +

0x1E

APC status of the N’th priority service

N’th priority PTP queue length.

Reserved

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