Texas Instruments DS90UR241/DS90UR124 SERDES Evaluation Kit User guide

SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual

SERDES Demonstration Kit

User Manual

Rev 0.2

NSID: SERDESUR-43USB

National Semiconductor Corporation

Date: 5/8/2008

Page 1 of 36


Table of Contents

TABLE OF CONTENTS ........................................................................................................................................... 2

INTRODUCTION: ..................................................................................................................................................... 3

CONTENTS OF THE EVALUATION KIT: ........................................................................................................... 4

SERDES TYPICAL APPLICATION:...................................................................................................................... 4

HOW TO SET UP THE EVALUATION KIT:........................................................................................................ 6

POWER CONNECTION: ......................................................................................................................................... 6

SERDES SERIALIZER BOARD DESCRIPTION: ................................................................................................ 7

C

ONFIGURATION

S

ETTINGS FOR THE

S

ERIALIZER

B

OARD

......................................................................................... 8

S

ERIALIZER

LVCMOS

AND

LVDS P

INOUT BY

IDC C

ONNECTOR

.......................................................................... 11

BOM (B

ILL OF

M

ATERIALS

) S

ERIALIZER

PCB: ...................................................................................................... 12

RX SERDES DE-SERIALIZER BOARD: ............................................................................................................. 13

C

ONFIGURATION

S

ETTINGS FOR THE

D

E

-

SERIALIZER

B

OARD

................................................................................. 14

O

UTPUT

M

ONITOR

P

INS FOR THE

D

E

-

SERIALIZER

B

OARD

...................................................................................... 15

D

E

-

SERIALIZER

LVDS P

INOUT AND

LVCMOS

BY

IDC C

ONNECTOR

.................................................................... 17

BOM (B

ILL OF

M

ATERIALS

) D

E

-

SERIALIZER

PCB: ................................................................................................ 18

TYPICAL CONNECTION AND TEST EQUIPMENT........................................................................................ 19

TROUBLESHOOTING ........................................................................................................................................... 21

APPENDIX................................................................................................................................................................ 23

SERIALIZER (TX) PCB SCHEMATIC:............................................................................................................... 23

DE-SERIALIZER (RX) PCB SCHEMATIC:........................................................................................................ 27

SERIALIZER (TX) PCB LAYOUT: ...................................................................................................................... 31

SERIALIZER (TX) PCB STACKUP: .................................................................................................................... 34

DESERIALIZER (RX) PCB LAYOUT:................................................................................................................. 35

DESERIALIZER (RX) PCB STACKUP:............................................................................................................... 38


Date: 5/8/2008

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Introduction:

National Semiconductor’s SERDES evaluation kit contains one (1) DS90UR241

Serializer (Tx) board, one (1) DS90UR124 De-serializer (Rx) board, and one (1) generic two (2) meter USB 2.0 Hi-SPEED cable assembly. National is not recommending using the USB 2.0 Hi-SPEED cable assembly but is provided in this kit as a generic solution to show the robustness of the chipset .

Note: the demo boards are not for EMI testing. The demo boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals, additional pads for termination, and multiple connector options.

The DS90UR241/124 chipset supports a variety of display applications. The single

LVDS interface is well-suited for any display system interface. Typical applications include: navigation displays, automated teller machines (ATMs), POS, video cameras, global positioning systems (GPS), portable equipment/instruments, factory automation, etc.

The DS90UR241 and DS90UR124 can be used as a 24-bit general purpose LVDS

Serializer and De-serializer chipset designed to transmit data at clocks speeds ranging from 5 to 43 MHz.

The DS90UR241 serializer board accepts LVCMOS input signals. The LVDS Serializer converts the LVCMOS parallel lines into a single serialized LVDS data pair with an embedded LVDS clock. The serial data stream toggles at 28 times the base clock rate.

With an input clock at 43 MHz, the transmission rate for the LVDS line is 1.204Gbps.

The DS90UR124 de-serializer board accepts the LVDS serialized data stream with embedded clock and converts the data back into parallel LVCMOS signals and clock.

Note that NO reference clock is needed to prevent harmonic lock as with other devices currently on the market.

Suggested equipment to evaluate the chipset, an LVCMOS signal source such as a video generator or word generator or pulse generator and oscilloscope with a bandwidth of at least 43 MHz will be needed.

The user needs to provide the proper LVCMOS/RGB inputs and LVCMOS/clock to the serializer and also provide a proper interface from the de-serializer output to an LCD panel or test equipment. The serializer and de-serializer boards can also be used to evaluate device parameters. A cable conversion board or harness scramble may be necessary depending on type of cable/connector interface used on the input to the

DS90UR241 and to the output of the DS90UR124.

Example of suggested display setup:

1) video generator with LVCMOS output

2) 6-bit LCD panel with a LVCMOS input interface.


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Contents of the Evaluation Kit:

1) One Serializer board with the DS90UR241

2) One De-serializer board with the DS90UR124

3) One 2-meter USB 2.0 Hi-SPEED cable assembly

4) Evaluation Kit Documentation (this manual)

5) DS90UR241/124 Datasheet

SERDES Typical Application:

Figure 1a. Typical SERDES Application (18-bit RGB Color)

Figure 1b. Typical SERDES System Diagram


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Figures 1a and 1b illustrate the use of the Chipset (Tx/Rx) in a Host to Flat Panel

Interface.

The chipsets support up to 18-bit color depth TFT LCD Panels.

Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board for more detailed information.


Date: 5/8/2008

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How to set up the Evaluation Kit:

The PCB routing for the serializer input pins (DIN) have been laid out to accept incoming LVCMOS signals from a 50-pin IDC connector. The TxOUT/RxIN (DOUT/RIN) interface uses a USB connector/cable assembly (provided). The PCB routing for the Rx output pins (ROUT) are accessed through a 50-pin IDC connector. Please follow these steps to set up the evaluation kit for bench testing and performance measurements:

1) A two (2) meter USB connector

/ cable assembly has been included in the kit.

A

Connect 4-pin USB A side of cable harness to the serializer board and

1 2 3 4

the other side 5-pin mini USB jack completes the LVDS interface connection.

MIN

to the de-serializer board. This

NOTE: The DS90C241 and DS90C124 are NOT USB compliant and should not be plugged into a USB device nor should a USB device be plugged into the demo boards.

2) Jumpers and switches have been configured at the factory; they should not require any changes for immediate operation of the chipset. See text on Configuration settings for more details. From the Video Decoder board, connect a flat cable (not supplied) to the Serializer board and connect another flat cable (not supplied) from the De-serializer board to the panel. Caution: The LVCMOS input levels should be within the specified range for optimal performance, not to exceed the absolute maximum rating of -0.3V to (VCC +0.3V).

Note: For 50 ohm LVCMOS input signal sources, add 50 ohm parallel termination resistors R1-R25 on the DS90UR241 Serializer board and provide appropriate 3.3V

LVCMOS input signal levels into DIN[23:0] and TCLK.

3) Power for the Tx and Rx boards must be supplied externally through Power Jack

(VDD). Grounds for both boards are connected through Power Jack (VSS) (see section below).

Power Connection:

The serializer and de-serializer boards must be powered by supplying power externally through J4 (VDD) and J5 (VSS) on serializer Board and J4 (VDD) and J5 (VSS) on deserializer board. Note +4V is the absolute MAXIMUM voltage (not operating voltage) that should ever be applied to the SERDES serializer (DS90UR241) or de-serializer

(DS90UR124) VDD terminal. Damage to the device(s) can result if the voltage maximum is exceeded.


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SERDES Serializer Board Description:

The 50-pin IDC connector J1 accepts 24 bits of LVCMOS RGB data (DIN0-DIN23) along with the clock input (TCLK).

The SERDES serializer board is powered externally from the J4 (VDD) and J5 (VSS) connectors shown below. For the serializer to be operational, the Power Down (S1-

TPWDNB) and Data Enable (S1-DEN) switches on S1 must be set HIGH. Rising or falling edge reference clock is also selected on S1-TRFB: HIGH (rising) or LOW

(falling). FPD_LINKII is an AC coupled LVDS (series 0.1

µF capacitors on each side of the LVDS serializer outputs and de-serializer inputs). JP1 and JP2 are configured from the factory to be shorted to VSS; these are the unused power wires in the cable harness.

The USB connector P2 (on the backside of the board) provides the interface connection to the LVDS signals to the de-serializer board. f

J4, J5

Note:

VDD and VSS MUST be applied externally from here. e

VR1, JP3

J1

S1 d e g g g g h

JP1, JP2

Note:

Connect cable

(USB A side) to P2 on BACKSIDE.

c

P2 (BACKSIDE) c

P1 (TOPSIDE)

(UNSTUFFED) c

LVDS OUTPUTS d

LVCMOS INPUTS e

FUNCTION CONTROLS f

POWER SUPPLY g

50

Ω INPUT TERMINATION

(For 50

Ω

signal sources, populated with 50ohm resistors to provide proper termination.)

h

UNUSED POWER WIRES IN CABLE


Date: 5/8/2008

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Configuration Settings for the Serializer Board

S1: Serializer Input Features Selection

Reference Description Input = L Input = H

tied low for normal operation

(Default)

TPWDNB tied low for normal operation

(Default)

PoWerDowN Bar Powers

Down

TRFB

RAOFF

RESRVD

Latch input data on Rising or

Falling edge of

TCLK

RAndomizer OFF

RESeRVeD

Falling

Edge

(Default)

Randomizer

ON.

(Default)

Note:

DS90UR124

RAOFF MUST also be set

Low.

MUST be tied low for normal operation

(Default)

Normal operation

(Default)

Rising

Edge

Randomizer

OFF.

Note:

DS90UR124

RAOFF MUST also be set

High.

Not allowed

Data ENabled

VOD SELect

≈350mV

(Default)

(Default)

≈700mV

S1


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JP3,VR1: Pre-Emphasis Feature Selection

Reference Description OPEN

JP3 Pre-Emphasis – helps to increase the eye pattern opening in the LVDS stream

(floating)

Disabled – no jumper

(Default)

(Path to GND)

Enabled –

With jumper

JP3 &

VR1

Pre-Emphasis adjustment

(via screw)

JP1 MUST have a jumper to

Clockwise Counter-

Clockwise use VR1 potentiometer.

VR1 = 0

Ω to 20KΩ,

JP1 + VR1 + 6K

Ω

(

R26) =

~6K

Ω (maximum predecreases

R

PRE

value which increases preemphasis emphasis) to

~26K

Ω (minimum preemphasis*).

I

PRE

= [1.2/(R

PRE

)] x 40,

R

PRE (minimum)

> 6K

Ω

*Note: maximum is based on resistor value. In this case ~26K on the ~6k

Ω

value is based

Ω

fixed resistor plus ~20K

Ω

maximum potentiometer value. User can use hundreds of Kohms to reduce the preemphasis value.

increases

R

PRE

value which decreases preemphasis

Pre-emphasis user note:

Pre-emphasis must be adjusted correctly based on application frequency, cable quality, cable length, and connector quality. Maximum pre-emphasis should only be used under extreme worse case conditions; for example at the upper frequency specification of the part and/or low grade cables at maximum cable lengths. Typically all that is needed is minimum pre-emphasis. Users should start with no pre-emphasis first and gradually apply pre-emphasis until there is clock lock and no data errors. The best way to monitor the pre-emphasis effect is to hook up a differential probe to the 100

Ω termination resistor (R1) on the

DS90UR124 Rx demo board (NOT to R27 on the DS90UR241 Tx demo board). The reason for monitoring R1 on the Rx side is because you want to see what the receiver will see the attenuation signal AFTER the cable/connector.


Date: 5/8/2008

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JP1, JP2: USB Cable Assembly - RED wire and BLK wire

Reference Description VDD VSS OPEN

JP1 RED wire in USB cable RED wire RED wire RED wire thru P1 connector.

Jumper RED to VSS recommended.

CAUTION:

Jumper settings should be set the same on the DS90UR124 board or a short can occur.

tied to VDD tied to VSS

(Default)

floating

(not recommended)

JP2 BLACK wire in USB cable thru P1 connector.

Jumper BLACK to VSS recommended.

CAUTION:


BLACK wire tied to VDD

BLACK wire tied to VSS

(Default)

BLACK wire floating

(not recommended)

JP1 and JP2 connections on connector P1

P1


Date: 5/8/2008

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Serializer LVCMOS and LVDS Pinout by IDC Connector

The following two (2) tables illustrate how the serializer inputs are mapped to the IDC connector J1, the LVDS outputs on the USB connector P2 pinout. Note – labels are also printed on the demo boards for both the TTL input and LVDS outputs.

LVCMOS INPUT

J1 pin no. name

LVDS OUTPUT

P2 pin no. name

2 DIN0

4 DIN1

6 DIN2

8 DIN3

26

28

30

32

34

36

38

18

20

22

24

10

12

14

16

40

42

44

46

48

50

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

DIN10

DIN11

DIN12

DIN13

DIN14

DIN15

DIN16

DIN17

DIN18

DIN19

DIN20

DIN21

DIN22

DIN23

TCLK all odd pins gnd

1 RED

2 DOUT+

3 DOUT-

4 BLK


Date: 5/8/2008

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BOM (Bill of Materials) Serializer PCB:

DS90UR241 Tx USB Demo Board - Board Stackup Revised: Friday, September 15, 2006

DS90UR241 Tx USB Demo Board Revision: 1

Bill Of Materials September 15,2006 19:21:34

Item Qty Reference Part

______________________________________________

0.1uF CAP/HDC-0402

2.2uF

22uF

0.1uF

3528-21_EIA

CAP/N

CAP/HDC-1206

12 1 P1

CAP/HDC-0603

CAP/HDC-0603

Header/3P

Header/2P

IDC2X25_Unshrouded IDC-50

BANANA CON/BANANA-S mini USB 5pin_open mini_B_USB_surface_mount

USB_TYPE_A_4P

R9,R10,R11,R12,R13,R14,

R15,R16,R17,R18,R19,R20,

R21,R22,R23,R24

49.9ohm_open

5.76K

0_ohm

RES/HDC-0201

RES/HDC-0805

RES/HDC-0402

RES/HDC-0402

RES/HDC-0201

21

22

1

1

R44,R45

U1

VR1

DS90UR241

SVR20K

TP_0402

RES/HDC-0805

DIP-16

48 ld TQFP

Surface Mount 4mm Square

TP/0402


Date: 5/8/2008

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Rx SERDES De-serializer Board:

The USB connector J2 provides the interface connection for LVDS signals to the serializer board.

The SERDES de-serializer board is powered externally from the J4 (VDD) and J5 (VSS) connectors shown below. For the de-serializer to be operational, the Power Down

(RPWDNB) and Receiver Enable (REN) switches on S1 and S2 must be set HIGH.

Rising or falling edge reference clock is also selected by S1: HIGH (rising) or LOW

(falling).

The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs. f

J4, J5

Note:

Vcc and Gnd MUST be applied externally here d

JP4 e

S1 c

J2 c

J1 (BACKSIDE)

(UNSTUFFED) g

JP1, JP2 e

S2 d

JP3 d

J3 c

LVDS INPUTS d

LVCMOS OUTPUTS e

FUNCTION CONTROLS f

POWER SUPPLY g

UNUSED POWER WIRES IN

CABLE


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Configuration Settings for the De-serializer Board

S1, S2: De-serializer Input Features Selection

Reference Description Input = L

(Disabled)

Input = H

RPWDNB Normal

Operational

(Default)

PTOSEL Progressive Turn On

SELect

RESRVD RESeRVeD

Enabled

(Default)

Disabled

Don’t care Don’t care

Reference

RRFB

Description

Latch input data on Rising or Falling edge of TCLK

REN Receiver Output Data

ENabled

BISTEN BIST ENable

Note: MUST set DS90UR241

ALL DIN[23:0] inputs Low or floating. Use in combination with BISTM pin.

BISTM

RAOFF

SLEW

BIST Mode

Don’t care if BISTEN=L.

BISTEN MUST be High

(enabled) for this pin to be functional.

RAndomizer OFF

SLEW rate control for ROUT[23:0] and RCLK

Input = L

Falling Edge

(Default)

Input = H

Rising Edge

Disabled Enabled

(Default)

Normal

Operating

Mode, BIST

BIST Mode

Enabled

Disabled

(Default)

Per Channel pass/fail;

RxOUT[23:0]

=H: pass;

RxOUT[23:0]

=H: fail

Randomizer

ON.

(Default)

Note:

DS90UR241

RAOFF MUST also be set Low.

(Default)

RxOUT[7:0]: binary error counting mode (up to

255 errors);

RxOUT[23:8]: normal operation

Randomizer

OFF.

Note:

DS90UR241

RAOFF MUST also be set High.

~2X slew rate,

~2X drive strength

S1

S2


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Output Monitor Pins for the De-serializer Board

JP3: Output Lock Monitor

Reference Description Output = L Output = H

Note:

DO NOT PUT A SHORTING

JUMPER IN JP3.

Unlocked PLL LOCKED

(LED2 will illuminate)

JP3

JP4: PASS Monitor

Reference

PASS

Description

Receiver BIST monitor

PASS flag

Note:

DO NOT PUT A SHORTING

JUMPER IN JP1.

Output = L Output = H

FAIL PASS

(LED1 will illuminate)

JP4


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JP1, JP2: USB Cable Assembly wire red and black

Reference Description VDD VSS OPEN

JP1

JP2

Red wire in USB cable thru

JP1 connector.

Jumper red wire to VSS recommended.

CAUTION:


Black wire in USB cable thru JP2 connector.

Jumper black wire to VSS recommended.

CAUTION:


Red wire tied to VDD

Black wire tied to VDD

Red wire tied to VSS

(Default)

Black wire tied to VSS

(Default)

Red wire floating

(not recommended)

Black wire floating

(not recommended)

JP1 and JP2 connections on connector J2


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De-serializer LVDS Pinout and LVCMOS by IDC Connector

The following two tables illustrate how the LVDS inputs are mapped to the mini USB connector J2 and the Rx outputs are mapped to the IDC connector J3. Note

– labels are also printed on the demo boards for both the LVDS inputs and TTL outputs.

LVDS INPUT

J2 pin no. name

1 RED

2 RIN+

3 RIN-

4 NC

5 BLK

LVCMOS OUTPUT

J3 pin no. name

1 ROUT0

3 ROUT1

5 ROUT2

7 ROUT3

9 ROUT4

25

27

29

31

33

35

37

11

13

15

17

19

21

23

39

41

43

45

47

49

ROUT5

ROUT6

ROUT7

ROUT8

ROUT9

ROUT10

ROUT11

RCLK

ROUT12

ROUT13

ROUT14

ROUT15

ROUT16

ROUT17

ROUT18

ROUT19

ROUT20

ROUT21

ROUT22

ROUT23 all even pins gnd


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BOM (Bill of Materials) De-serializer PCB:

DS90UR124 Rx USB Demo Board - Board Stackup Revised: Thursday, September 14, 2006

DS90UR124 Rx USB Demo Board Revision: 1

Bill Of Materials September 14,2006 18:28:58

Item Qty Reference Part

______________________________________________

0.1uF CAP/HDC-0402

CAP/HDC-0402

C13,C14,C15,C16,C17,C18,

C19,C20,C21,C22,C23,C24,

C25,C26,C27,C28,C29,C30,

C31,C42

2.2uF

22uF

0.1uF

3528-21_EIA

CAP/N

CAP/HDC-1206

C53,C54

C52,C55

C51,C56

11 1 J1

12 1 J2

16 1 LED2

R38,R39

21 1 U1

CAP/HDC-0603

CAP/HDC-0603

Header/3P mini_USB_surface_mount mini_USB_surface_mount mini USB 5pin_open mini USB 5pin

BANANA CON/BANANA-S

0402_orange_LED 0402

0603_green_LED 0603 (Super Thin)

RES/HDC-0402

RES/HDC-0805

DS90UR124

DIP-6

DIP-12

64 pin TQFP


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Typical Connection and Test Equipment

The following is a list of typical test equipment that may be used to generate signals for the TX inputs:

1) Digital Video Source – for generation of specific display timing such as Digital Video

Processor or Graphics Controller with digital RGB (LVCMOS) output.

2) Astro Systems VG-835 - This video generator may be used for video signal sources for 6-bit Digital TTL/RGB.

3) Any other signal / video generator that generates the correct input levels as specified in the datasheet.

4) Optional – Logic Analyzer or Oscilloscope

The following is a list of typically test equipment that may be used to monitor the output signals from the RX:

1) LCD Display Panel which supports digital RGB (LVCMOS) inputs.

2) National Semiconductor DS90UR241 Serializer (Tx)

3) Optional – Logic Analyzer or Oscilloscope

4) Any SCOPE with a bandwidth of at least 43 MHz for TTL and/or 2 GHz for looking at the differential signal.

LVDS signals may be easily measured with high impedance / high bandwidth differential probes such as the TEK P6330 differential probes.


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The picture below shows a typical test set up using a Graphics Controller and LCD

Panel.

Figure 2. Typical SERDES Setup of LCD Panel Application

The picture below shows a typical test set up using a generator and scope.

Figure 3. Typical SERDES Test Setup for Evaluation


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Troubleshooting

If the demo boards are not performing properly, use the following as a guide for quick solutions to potential problems. If the problem persists, please contact the local Sales

Representative for assistance.

QUICK CHECKS:

1. Check that Power and Ground are connected to both Tx AND Rx boards.

2. Check the supply voltage (typical 3.3V) and also current draw with both Tx and Rx boards. The Serializer board should draw about 55-65mA with clock and all data bits switching at 43MHz, (R

PRE

=9K

Ω). The De-serializer board should draw about

75-85mA with clock and all data bits switching at 43MHz, (minimum ROUT loading).

3. Verify input clock and input data signals meet requirements for VILmin, VILmax,

VIHmin, VIHmax, tset, thold), also verify that data is strobed on the selected rising/falling (RFB pin) edge of the clock.

4. Check that the Jumpers and Switches are set correctly.

5. Check that the cable is properly connected.

TROUBLESHOOTING CHART

Problem…

Solution…

There is only the output clock.

There is no output data.

Make sure the data is applied to the correct input pin.

Make sure data is valid at the input.

No output data and clock.

Power, ground, input data and input clock are connected correctly, but no outputs.

The devices are pulling more than 1A of current.

Make sure Power is on. Input data and clock are active and connected correctly.

Make sure that the cable is secured to both demo boards.

Check the Power Down pins of both Serializer and

De-serializer boards to make sure that the devices are enabled (/PD=Vcc) for operation. Also check

DEN on the Serializer board and REN on the

Deserializer board is set HIGH.

Check for shorts in the cables connecting the TX and

RX boards.

After powering up the demo boards, the power supply reads less than 3V when it is set to 3.3V.

Use a larger power supply that will provide enough current for the demo boards, a 500mA minimum power supply is recommended.


Date: 5/8/2008

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Note: Please note that the following references are supplied only as a courtesy to our valued customers. It is not intended to be an endorsement of any particular equipment or hardware supplier

.

Connector References

Hirose Electric Europe B.V.

Beech Avenue 46

1119 PV Schiphol-Rijk

The Netherlands

Phone: +31 20 655 7467, Fax: +31 20 655 7469 www.HiroseEurope.com

Cable References

Nissei Electric Co., LTD

1509 Okubo-Cho, Hamamatsu-City

Shizuoka-Pref, 432-8006 Japan

Phone: +81 53 485 4114, Fax: +81 53 485 6908 www.nissei-el.co.jp

Cable Recommendations

- For optimal performance, we recommend Shielded Twisted Pair (STP) 100

Ω differential impedance cable for high-speed data applications.

Equipment References

Astro Systems

425 S. Victory Blvd. Suite A

Burbank, CA 91502

Phone: (818) 848-7722 , Fax: (818) 848-7799 www.astro-systems.com

Digital Video Pattern Generator – Astro Systems VG-835 (or equivalent):

Extra Component References

TDK Corporation of America

1740 Technology Drive, Suite 510

San Jose, CA 95110

Phone: (408) 437-9585, Fax: (408) 437-9591 www.component.tdk.com

Optional EMI Filters – TDK Chip Beads (or equivalent)


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Appendix

Serializer (Tx) PCB Schematic:


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De-serializer (Rx) PCB Schematic:


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Serializer (Tx) PCB Layout:

TOP VIEW BOTTOMSIDE VIEW


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PRIMARY COMPONENT SIDE – LAYER 1 GROUND PLANE (VSS) – LAYER 2 POWER PLANE (VDD) – LAYER 3

SECONDARY COMP SIDE – LAYER 4 PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)


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PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)

PRIMARY COMP SIDE – SILKSCREEN (LAYER 1) SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)


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Serializer (Tx) PCB Stackup:


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Deserializer (Rx) PCB Layout:

TOP VIEW BOTTOMSIDE VIEW


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PRIMARY COMPONENT SIDE – LAYER 1 GROUND PLANE (VSS) – LAYER 2 POWER PLANE (VDD) – LAYER 3

SECONDARY COMP SIDE – LAYER 4

PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)


Date: 5/8/2008

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PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)

PRIMARY COMP SIDE – SILKSCREEN (LAYER 1) SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)


Date: 5/8/2008

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Deserializer (Rx) PCB Stackup:


Date: 5/8/2008

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Texas Instruments DS90UR241/DS90UR124 SERDES Evaluation Kit User guide

SERDES Demonstration Kit

User Manual

NSID: SERDESUR-43USB

Table of Contents

Introduction:

Contents of the Evaluation Kit:

SERDES Typical Application:

How to set up the Evaluation Kit:

A

Power Connection:

SERDES Serializer Board Description:

Configuration Settings for the Serializer Board

Serializer LVCMOS and LVDS Pinout by IDC Connector

BOM (Bill of Materials) Serializer PCB:

Rx SERDES De-serializer Board:

Configuration Settings for the De-serializer Board

Output Monitor Pins for the De-serializer Board

De-serializer LVDS Pinout and LVCMOS by IDC Connector

BOM (Bill of Materials) De-serializer PCB:

Typical Connection and Test Equipment

Troubleshooting

.

Connector References

Cable References

Cable Recommendations

Equipment References

Extra Component References

Appendix

Serializer (Tx) PCB Schematic:

De-serializer (Rx) PCB Schematic:

Serializer (Tx) PCB Layout:

Serializer (Tx) PCB Stackup:

Deserializer (Rx) PCB Layout:

Deserializer (Rx) PCB Stackup:

Related manuals

Table of contents

Texas Instruments DS90UR241/DS90UR124 SERDES Evaluation Kit User guide

SERDES Demonstration Kit

User Manual

NSID: SERDESUR-43USB

Table of Contents

Introduction:

Contents of the Evaluation Kit:

SERDES Typical Application:

How to set up the Evaluation Kit:

A

Power Connection:

SERDES Serializer Board Description:

Configuration Settings for the Serializer Board

Serializer LVCMOS and LVDS Pinout by IDC Connector

BOM (Bill of Materials) Serializer PCB:

Rx SERDES De-serializer Board:

Configuration Settings for the De-serializer Board

Output Monitor Pins for the De-serializer Board

De-serializer LVDS Pinout and LVCMOS by IDC Connector

BOM (Bill of Materials) De-serializer PCB:

Typical Connection and Test Equipment

Troubleshooting

.

Connector References

Cable References

Cable Recommendations

Equipment References

Extra Component References

Appendix

Serializer (Tx) PCB Schematic:

De-serializer (Rx) PCB Schematic:

Serializer (Tx) PCB Layout:

Serializer (Tx) PCB Stackup:

Deserializer (Rx) PCB Layout:

Deserializer (Rx) PCB Stackup:

Related manuals

Texas Instruments

FPD to SERDES (UR) Translator Chip DS99R421 Evaluation Kit

Texas Instruments

DS92LV3241/DS92LV3242 Demonstration Kit

Texas Instruments

DS92LV3241/3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer (Rev. D)

Table of contents