Cypress Semiconductor SL811HS Specifications

Cypress Semiconductor SL811HS Specifications
SL811HS
SL811HS
Embedded USB Host/Slave Controller
Cypress Semiconductor Corporation
Document #: 38-08008 Rev. *A
•
3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised March 14, 2002
SL811HS
TABLE OF CONTENTS
1.0 CONVENTIONS .............................................................................................................................. 4
2.0 DEFINITIONS .................................................................................................................................. 4
3.0 REFERENCES ................................................................................................................................ 4
4.0 INTRODUCTION ............................................................................................................................. 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Block Diagram ................................................................................................................................ 4
SL811HS Host or Slave Mode Selection [Master/Slave Mode] .................................................. 5
Features .......................................................................................................................................... 5
Data Port, Microprocessor Interface ............................................................................................ 6
Interrupt Controller ........................................................................................................................ 6
Buffer Memory ............................................................................................................................... 6
PLL Clock Generator ..................................................................................................................... 6
USB Transceiver ............................................................................................................................ 8
5.0 SL811HS REGISTERS ................................................................................................................... 8
5.1 Register Values on Power-up and Reset ..................................................................................... 9
5.2 USB Control Registers .................................................................................................................. 9
5.3 SL811HS Control Registers ........................................................................................................ 12
6.0 SL811HS AND SL811HST-AC PHYSICAL CONNECTIONS ...................................................... 16
6.1 SL811HS Physical Connections ................................................................................................. 16
6.2 SL811HST-AC Physical Connections ........................................................................................ 19
7.0 ELECTRICAL SPECIFICATIONS ................................................................................................. 22
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ........................................................................................................ 22
Recommended Operating Condition ........................................................................................ 22
External Clock Input Characteristics (X1) ................................................................................. 22
DC Characteristics ....................................................................................................................... 23
USB Host Transceiver Characteristics ...................................................................................... 23
Bus Interface Timing Requirements .......................................................................................... 24
8.0 PACKAGE DIAGRAMS
.............................................................................................................. 28
LIST OF FIGURES
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 6-1.
Figure 6-2.
SL811HS USB Host/Slave Controller Functional Block Diagram ................................ 5
Full-Speed 48-MHz Crystal Circuit .................................................................................. 7
Optional 12-MHz Crystal Circuit ...................................................................................... 7
SL811HS USB Host/Slave Controller—Pin Layout ...................................................... 16
SL811HST-AC USB Host/Slave Controller Pin Layout ................................................ 19
LIST OF TABLES
Table 6-1. SL811HS Pin Assignments and Definitions ................................................................... 17
Table 6-2. SL811HST-AC Pin Assignments and Definitions ........................................................... 20
Document #: 38-08008 Rev. *A
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SL811HS
License Agreement
Use of this document and the intellectual properties contained herein indicates acceptance of the following License Agreement.
If you do not accept the terms of this License Agreement, do not use this document, or the associated intellectual properties, or
any other material you received in association with this product, and return this document and the associated materials within
fifteen (15) days to Cypress Semiconductor Corporation or (CY) or CY’s authorized distributor from whom you purchased the
product.
1. You can only legally obtain CY’s intellectual properties contained in this document through CY or its authorized distributors.
2. You are granted a nontransferable license to use and to incorporate CY’s intellectual properties contained in this document
into your product. The product may be either for your own use or for sale.
3. You may not reverse-engineer the SL811HS or otherwise attempt to discover the designs of SL811HS.
4. You may not assign, distribute, sell, transfer or disclose CY’s intellectual properties contained in this document to any other
person or entity.
5. This license terminates if you fail to comply with any of the provisions of this Agreement. You agree upon termination to destroy
this document, stop using the intellectual properties contained in this document and any of its modification and incorporated
or merged portions in any form, and destroy any unused SL811HS chips.
Warranty Disclaimer and Limited Liability
Cypress (CY), hereafter referred to as the manufacturer, warrants that its products substantially conform to its specifications for
a period of ninety (90) days from delivery as evidenced by the shipment records. The manufacturer's sole obligation and liability
for breaching the foregoing warranty shall be to replace or correct the defective products so that it substantially conforms to its
specifications. Any modification of the products by anyone other than the manufacturer voids the foregoing warranty. No other
warranties are expressed and none shall be implied. The manufacturer makes no warrant for the use of its products. In order to
minimize risks associated with customer’s applications, adequate design and operating safeguards must be provided by the
customer to minimize inherent or procedural hazards. The manufacturer’s products are not designed, authorized, or warranted
suitable for use in life-support devices or systems or other critical applications. The manufacturer specifically excludes any implied
warranties of merchantability and fitness for a particular purpose unless prohibited by law. In no event shall the manufacturer's
liability to you for damages hereunder for any cause whatsoever exceed the amount paid by you for the products. In no event
will the manufacturer be liable for any loss of profits or other incidental or consequential damages arising out of the use or inability
to use the product even if the manufacturer have been advised of the possibility of such damages.
The manufacturer reserves the right to make changes at any time, without notice, to improve design or performance and supply
the best product possible. The manufacturer assumes no responsibility for any errors that may appear in its technical document
on the products nor does it make a commitment to update the information contained in its technical document. Nothing contained
in the technical documents of the products shall be construed as a recommendation to use any products in violation of existing
patents, copyrights or other rights of third parties. No license is granted by implication or otherwise under any patent, patent rights
or other rights, of the manufacturer.
Document #: 38-08008 Rev. *A
Page 3 of 29
SL811HS
1.0
Conventions
1,2,3,4
Numbers without annotations are decimals.
Dh, 1Fh, 39h
Hexadecimal numbers are followed by an “h.”
0101b, 010101b
Binary numbers are followed by a “b.”
bRequest, n
Words in italics indicate terms defined by USB Specification or by this Specification.
2.0
Definitions
USB
Universal Serial Bus
SL811HS
The SL811HS is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip.
This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package
(SL811HST-AC). Throughout this document, “SL811HS” refers to both packages unless otherwise
noted.
SL11
The SL11 is a Cypress USB Peripheral Device Controller, providing multiple functions on a single chip.
This part is offered in both a 28-pin PLCC package (SL11) and a 48-pin TQFP package (SL11T-AC).
Throughout this document, “SL11” refers to both packages unless otherwise noted.
Note: This chip does not include CPU.
Note: This chip does not include a CPU.
SL11H
The SL11H is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip. This
part is offered in both a 28-Pin PLCC package (SL11H) and a 48-Pin TQFP package (SL11HT-AC).
Throughout this document, “SL11H” refers to both packages unless otherwise noted.
Note: This chip does not include CPU.
LSB
Least Significant Bit
MSB
Most Significant Bit
R/W
Read/Write
PLL
Phase Lock Loop
RAM
Random Access Memory
SIE
Serial Interface Engine
ACK
Handshake packet indicates a positive acknowledgment.
NAK
Handshake packet indicating a negative acknowledgment
USBD
Universal Serial Bus Driver
SOF
Start of Frame is the first transaction in each frame. It allows endpoints to identify the start of the frame
and synchronize internal endpoint clocks to the host.
CRC
Cyclic Redundancy Check
HOST
The host computer system on which the USB Host Controller is installed
3.0
References
[Ref 1] USB Specification 1.1: http://www.usb.org.
4.0
Introduction
4.1
Block Diagram
The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB
peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of
buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.
The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers. The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.
The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support
to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally, the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.
The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages
operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
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SL811HS
Master/Slave
Controller
INTERRUPT
CONTROLLER
INTR
RAM
D+
D-
SERIAL
USB
INTERFACE
Root-HUB
XCVRS
ENGINE
BUFFERS
&
CONTROL
REGISTERS
PROCESSOR
CLOCK
GENERATOR
INTERFACE
nWR
nRD
nCS
nRST
D0-7
X1
X2
Figure 4-1. SL811HS USB Host/Slave Controller Functional Block Diagram
4.2
SL811HS Host or Slave Mode Selection [Master/Slave Mode]
SL811HS can work in two modes—host or slave. For slave-mode operation and specification, please refer to the SL811S
specification. This data sheet only covers host-mode operation.
4.3
Features
• The only USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface.
• Supports both full-speed (12 Mbps) and low-speed (1.5 Mbps) USB transfer
4.3.1
USB Specification Compliance
• Conforms to USB Specification 1.1
4.3.2
CPU Interface
• Operates as a single USB host or slave under software control
• Low-speed 1.5 Mbps, and full speed 12 Mbps, in both master and slave modes
• Automatic detection of either low- or full-speed devices
• 8-bit bidirectional data, port I/O (DMA supported in slave mode)
• On-chip SIE and USB transceivers
• On-chip single root HUB support
• 256-byte internal SRAM buffer, ping-pong operation
• Operates from 12- or 48-MHz crystal or oscillator (built-in DPLL)
• 5 V-tolerant interface
• Suspend/resume, wake up, and low-power modes are supported
• Auto-generation of SOF and CRC5/16
• Auto-address increment mode, saves memory Read/Write cycles
• Development kit including source code drivers is available
• Backward-compatible with SL11H, both pin and functionality
• 3.3V power source, 0.35 micron CMOS technology
• Available in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC).
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SL811HS
4.4
Data Port, Microprocessor Interface
The SL811HS microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interface
to external processors or controllers. The control lines, Chip Select, Read and Write input strobes and a single address line, A0,
along with the 8-bit data bus, support programmed I/O or memory mapped I/O designs.
Access to memory and control register space is a simple two step process, requiring an address Write with A0 set = “0,” followed
by a register/memory Read or Write cycle with address line A0 set = “1.”
In addition, DMA bidirectional interface in slave mode is available with handshake signals such as DREQ, ACK, WR, RD, CS and
INTR. Please refer to the SL811S spec.
The SL811HS Write or Read operation terminates when either nWR or nCS goes inactive. For devices interfacing to the SL811HS,
that deactivate the Chip Select nCS before the Write nWR, the data hold timing should be measured from the nCS and will be
the same value as specified. Thus, both Intel− and Motorola-type CPUs can work easily with the SL811HS without any external
glue logic requirements.
4.5
Interrupt Controller
The SL811HS interrupt controller provides a single output signal (INTRQ) that can be activated by a number of events that may
occur as result of USB activity. Control and status registers are provided to allow the user to select single or multiple events,
which will generate an interrupt (assert INTRQ), and lets the user view interrupt status. The interrupts can be cleared by writing
to the appropriate register (the Status Register at address 0x0d).
4.6
Buffer Memory
The SL811HS contains 256 bytes of internal buffer memory. The first 16 bytes of memory represent control and status registers
for programmed I/O operations. The remaining memory locations are used for data buffering (max. 240 Bytes).
Access to the registers and data memory is through an external microprocessor, 8-bit data bus, in either of two addressing modes,
indexed or, if used with multiplexed address/data bus interfaces, direct access. With indexed addressing, the address is first
written to the device with the A0 address line LOW, then the following cycle with A0 address line HIGH is directed to the specified
address. USB transactions are automatically routed to the memory buffer. Control registers are provided, so that pointers and
block sizes in buffer memory can be can set up.
4.6.1
Auto Address Increment Mode
The SL811HS supports auto-increment mode for Read or Write Cycles, A0 mode. In A0 mode, the Micro Controller sets up the
address only once. On any subsequent DATA Read or Write access, the internal address pointer will advance to the next DATA
location.
4.6.1.1 For example
Write 0x10 to SL811HS in address cycle (A0 is set LOW)
Write 0x55 to SL811HS in data cycle (A0 is set HIGH) -> Write 0x55 to location 0x10
Write 0xaa to SL811HS in data cycle (A0 is set HIGH) -> Write 0xaa to location 0x11
Write 0xbb to SL811HS in data cycle (A0 is set HIGH) -> Write 0xbb to location 0x12
The advantage of auto address increment mode is that it reduces the number of SL811HS memory Read/Write cycles required
to move data to/from the device. For example, transferring 64-bytes of data to/from SL811HS using auto increment mode, will
reduce the number of cycles to 1 Address Write and 64 Read/Write Data cycles, compared to 64 Address Writes and 64 Data
Cycles for Random Access.
4.7
PLL Clock Generator
Either a 12-MHz or a 48-MHz external crystal can be used with the SL811HS. Two pins, X1 and X2, are provided to connect a
low-cost crystal circuit to the device as shown in Figure 4-2 and Figure 4-3. If an external 48-MHz clock source is available in the
application, it can be used instead of the crystal circuit by connecting the source directly to the X1 input pin. When a clock is used,
the X2 pin is left unconnected.
Document #: 38-08008 Rev. *A
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SL811HS
X1
X2
Rf
1M
Rs
X1
100
48 MHz, series, 20-pF load
Cbk
0.01 µF
Cin
22 pF
Lin
2.2 µH
Cout
22 pF
Figure 4-2. Full-Speed 48-MHz Crystal Circuit
X1
X2
Rf
1M
Rs
100
X1
12 MHz , series, 20-pF load
Cin
Cout
22 pF
22 pF
Figure 4-3. Optional 12-MHz Crystal Circuit
Note:
1. CM (Clock Mode) pin of the SL811HS should be tied to GND when 48-MHz Xtal circuit or 48-MHz clock source is used.
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SL811HS
4.7.1
Typical Crystal Requirements
The following are examples of “typical requirements”. Please note that these specifications are generally found as standard crystal
values and are therefore less expensive than custom values. If crystals are used in series circuits, load capacitance is not
applicable. Load capacitance of parallel circuits is a requirement.
12-MHz Crystals:
Frequency Tolerance:
±100 ppm or better
Operating Temperature Range:
0°C to 70°C
Frequency:
12 MHz
Frequency Drift over Temperature:
± 50 ppm
ESR (Series Resistance):
60Ω
Load Capacitance:
10 pF min.
Shunt Capacitance:
7 pF max.
Drive Level:
0.1–0.5 mW
Operating Mode:
fundamental
48-MHz Crystals:
Frequency Tolerance:
±100 ppm or better
Operating Temperature Range:
0°C to 70°C
Frequency:
48 MHz
Frequency Drift over Temperature:
± 50 ppm
ESR (Series Resistance):
40 Ω
Load Capacitance:
10 pF min.
Shunt Capacitance:
7 pF max.
Drive Level:
0.1–0.5 mW
Operating Mode:
third overtone
4.8
USB Transceiver
The SL811HS has a built in transceiver that meets USB Specification 1.1. The transceiver is capable of transmitting and receiving
serial data at USB full speed (12 Mbits) and low speed (1.5 Mbits). The driver portion of the transceiver is differential while the
receiver section is comprised of a differential receiver and two single-ended receivers. Internally, the transceiver interfaces to the
Serial Interface Engine (SIE) logic. Externally, the transceiver connects to the physical layer of the USB.
5.0
SL811HS Registers
Operation of the SL811HS is controlled through 16 internal registers. A portion of the internal RAM is devoted to the control
register space, and access is through the microprocessor interface. The registers provide control and status information for
transactions on the USB, microprocessor interface, and interrupts.
Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS that enables
additional features not supported by the SL11H. For SL11H hardware backward compatibility, this register should not be
accessed.
The table below shows the memory map and register mapping of both the SL11H and SL811HS. The SL11H is shown for users
upgrading to the SL811HS.
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SL811HS
SL11H (hex)
Address
SL811HS (hex)
Address
USB-A Host Control Register
00H
00H
USB-A Host Base Address
01H
01H
USB-A Host Base Length
02H
02H
USB-A Host PID, Device Endpoint (Write)/USB Status (Read)
03H
03H
USB-A Host Device Address (Write)/Transfer Count (Read)
04H
04H
Control Register1
05H
05H
Interrupt Enable Register
06H
06 H
Reserved Register
Reserved
Reserved
USB-B Host Control Register
Reserved
08H
USB-B Host Base Address
Reserved
09H
USB-B Host Base Length
Reserved
0AH
USB-B Host PID, Device Endpoint (Write)/USB Status (Read)
Reserved
0BH
USB-B Host Device Address (Write)/Transfer Count (Read)
Reserved
0CH
Status Register
0DH
0DH
SOF Counter LOW (Write)/HW Revision Register (Read)
0EH
0E H
SOF Counter HIGH and Control Register2
Reserved
0F H
Memory Buffer
10H-FFH
10H-FFH
Register Name SL11H and SL811HS
The registers in the SL811HS are divided into two major groups. The first group is referred to as USB Control registers. These
registers enable and provide status for control of USB transactions and data flow. The second group of registers provides control
and status for all other operations.
5.1
Register Values on Power-up and Reset
The following registers initialize to zero on power-up and reset:
• USB-A/USB-B Host Control Register [00H, 08H] bit 0 only
• Control Register 1 [05H]
• USB Address Register [07H]
• Current Data Set/Hardware Revision/SOF Counter LOW Register [0EH]
All other registers power-up and reset in an unknown state and should be initialized by firmware.
5.2
USB Control Registers
Communication and data flow on the USB uses the SL811HS’s USB A-B Control Registers. The SL811HS can communicate with
any USB Device functions and any specific endpoints via the USBA or USBB register sets.
The USB A-B Host Control Registers can be used in a Ping-Pong arrangement to manage traffic on the USB. The USB Host
Control Register also provides a means to interrupt an external CPU or Micro Controller when one of the USB protocol transactions is completed. The table above shows the two sets of USB Host Control Registers, the “A” set and “B” set. The two register
sets allow for overlapped operation. When one set of parameters is being set up, the other is transferring. On completion of a
transfer to an endpoint, the next operation will be controlled by the other register set.
Note. On the SL11H, the USB-B set control registers are not used. The USB-B register set can be used only when SL811HS
mode is enabled by initializing register 0FH.
The SL811HS USB Host Control has two groups of five registers each, which map in the SL811HS memory space. These registers
are defined in the following tables.
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SL811HS
5.2.1
SL811HS Host Control Registers
SL11H (hex)
Address
SL811HS (hex)
Address
USB-A Host Control Register
00H
00H
USB-A Host Base Address
01H
01H
USB-A Host Base Length
02H
02H
USB-A Host PID, Device Endpoint (Write)/USB Status (Read)
03H
03H
USB-A Host Device Address (Write)/Transfer Count (Read)
04H
04H
USB-B Host Control Register
Reserved
08H
USB-B Host Base Address
Reserved
09H
USB-B Host Base Length
Reserved
0AH
USB-B Host PID, Device Endpoint (Write)/USB Status (Read)
Reserved
0BH
USB-B Host Device Address (Write)/Transfer Count (Read)
Reserved
0CH
Register Name SL11H and SL811H
5.2.2
USB-A/USB-B Host Control Registers [00H, 08H]
Bit Position
Bit Name
Function
0
Arm
1
Enable
2
Direction
3
Reserved
4
ISO
When set to “1” allows Isochronous mode for this endpoint.
5
SOF
“1” = Synchronize with the SOF transfer
6
Data Toggle Bit
7
Preamble
Allows enabled transfers when set = “1.” Cleared to “0” when transfer is complete.
When set = “1” allows transfers to this endpoint. When set “0” USB transactions are ignored.
If Enable = “1” and Arm = '0' the endpoint will return NAKs to USB transmissions.
When set = “1” transmit to Host. When “0” receive from Host.
“0” if DATA0, “1” if DATA1.
If set = “1” a preamble token is transmitted prior to transfer of low-speed packet. If set = “0,”
preamble generation is disabled.
• Bit 3 is reserved for future usage.
• The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted. When this bit set “1,” the next
enabled packet will be sent after next SOF. If set = “0” the next packet is sent immediately if the SIE is free.
• The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only used to send packets to a low-speed
device through a hub. To communicate to a full speed device, this bit is set to zero. For example, when SL811HS communicates
to a low-speed device via the HUB:
— SL811HS SIE should set to operate at 48 MHz, i.e., bit 5 of register 05H should be set = “0.”
— Bit 6 of register 0FH should be set = “0,” set correct polarity of DATA+ and DATA– state for Full Speed.
— Bit 7, Preamble Bit, should be set = “1” in Host Control register.
• When SL811HS communicates directly to low-speed device:
— SL811HS. Bit 5 of register 05H should be set = “1.”
— Bit 6 of register 0FH should be set = “1,” DATA+ and DATA– polarity for low speed.
— The state of bit 7 is ignored in this mode.
5.2.3
Example of SL811HS USB Packet Transfer
SL811HS memory set-up as shown:
03h-04h Register will contain PID and Device endpoint and Device Address.
10h-FFh USB Data as required.
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SL811HS
5.2.4
SOF Packet Generation
The SL811HS automatically computes CRC5 by hardware. No CRC or SOF is required to be generated by external firmware for
SL811HS.
5.2.5
USB-A/USB-B Host Base Address [01H, 09H]
The USB-A/USB-B Base Address is a Pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data OUT (Host to Device), the USB-A and USB-B can be set up prior to setting ARM on the USB-A or USB-B Host Control
register. See the software implementation example.
5.2.6
USB-A/USB-B Host Base Length [02H, 0AH]
The USB A/B host base register contains the maximum packet size to be transferred between the SL811HS and a slave USB
peripheral. Essentially, this designates the largest packet size that can be transferred by the SL811HS. Base Length designates
the size of data packet to be sent. For example, in Bulk mode the maximum packet length is 64 bytes. In ISO mode, the maximum
packet length is 1023, since the SL811HS only has an 8-bit length; the maximum packet size for the ISO mode using the SL811HS
is 255 – 16 bytes. When the Host Base Length register is set to zero, a Zero-Length packet will be transferred.
5.2.7
USB-A/USB-B Host PID, Device Endpoint (Write)/USB Status (Read) [03H, 0BH]
This register has two modes. When read, this register provides packet status and it contains information relative to the last packet
that has been received or transmitted. The register is defined as follows.
Bit Position
Bit Name
Function
0
ACK
Transmission Acknowledge
1
Error
Error detected in transmission
2
Time-out
Time-out occurred
3
Sequence
Sequence Bit. “0” if DATA0, “1” if DATA1
4
Setup
5
Overflow
6
NAK
Slave returns NAK
7
STALL
Slave set STALL bit
“1” indicates Setup Packet
Overflow condition - maximum length exceeded during receives
When written, this register provides the PID and Endpoint information to the USB SIE engine to be used in the next transaction.
All sixteen Endpoints can be addressed by the SL811HS.
D7
D6
D5
D4
D3
D2
D1
D0
PID3
PID2
PID1
PID0
EP3
EP2
EP1
EP0
PID3-0
4-bit PID Field (See Table Below)
EP3-0
4-bit Endpoint Value in Binary.
PID TYPE
Document #: 38-08008 Rev. *A
D7-D4
SETUP
1101 (D Hex)
IN
1001 (9 Hex)
OUT
0001 (1 Hex)
SOF
0101 (5 Hex)
PREAMBLE
1100 (C Hex)
NAK
1010 (A Hex)
STALL
1110 (E Hex)
DATA0
0011 (3 Hex)
DATA1
1011 (B Hex)
Page 11 of 29
SL811HS
5.2.8
USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [04H, 0CH]
This register has two functions. When read, this register contains the number of bytes left over (from “Length” field) after a packet
is transferred. If an overflow condition occurs, i.e., the received packet from slave USB device was greater than the Length field
specified, a bit is set in the Packet Status Register indicating the condition. When written, this register will contain the USB Device
Address to which the Host wishes to communicate.
5.3
D7
D6
D5
D4
D3
D2
D1
D0
0
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DA6-DA0
Device address, up to 127 devices can be addressed
DA7
Reserved bit should be set zero.
SL811HS Control Registers
Register Name SL11H and SL811H
SL11H (hex) Address
SL811HS (hex) Address
Control Register1
05H
05H
Interrupt Enable Register
06H
06 H
Reserved Register
07H
07 H
Status Register
0DH
0DH
SOF Counter LOW (Write)/HW Revision Register (Read)
0EH
0E H
SOF Counter HIGH and Control Register2
Reserved
0F H
Memory Buffer
10H-FFH
10H-FFH
5.3.1
Control Register 1, Address [05H]
The Control Register 05H enables/disables USB transfer operation with control bits defined as follows.
Bit
Bit Name
0
SOF ena/dis
1
Reserved
2
Reserved
3
USB Engine Reset
4
J-K state force
5
USB Speed
6
Suspend
7
Reserved
Function
“1” enable auto Hardware SOF generation, “0”= disable
USB Engine reset = “1.” Normal set “0”
See the table below
“0” set-up for full speed, “1” set-up LOW-SPEED
“1” enable, “0” = disable
• At power-up this register will be cleared to all zeros.
• In the SL811HS, bit 0 is used to enable HW SOF auto-generation (bit 0 was not used in the SL11H).
Document #: 38-08008 Rev. *A
Page 12 of 29
SL811HS
5.3.2
J-K Programming States [bits 3 and 4 of Control Register 05H]
The J-K force state control and USB Engine Reset bits can be used to generate USB reset condition on the USB. Forcing K-state
can be used for Peripheral device remote wake-up, Resume and other modes. These two bits are set to zero on power-up.
5.3.3
Bit 4
Bit 3
Function
0
0
Normal operating mode
0
1
Force USB Reset, D+ and D– are set LOW (SE0)
1
0
Force J-State, D+ set HIGH, D– set LOW[2]
1
1
Force K-State, D– set HIGH, D+ set LOW[3]
Low-speed/Full Speed Modes [bit 5 Control Register 05H]
The SL811HS is designed to communicate with either full or low-speed devices. At power-up bit 5 will be set LOW, i.e., for full
speed. There are two cases when communicating with a low-speed device. When a low-speed device is connected directly to
the SL811HS, bit 5 of Register 05H should be set to logic “1” and bit 6 of register 0FH, Output-Invert, needs to be set to “1” in
order to change the polarity of D+ and D–. When a low-speed device is connected via a HUB to SL811HS, bit 5 of Register 05H
should be set to logic “0” and bit 6 of register 0FH should be set to logic “0” in order to keep the polarity of D+ and D– for full
speed. In addition, make sure that bit 7 of USB-A/USB-B Host Control Registers [00H, 08H] is set to “1.”
5.3.4
Low-power Modes [bit 6 Control Register 05H]
When bit-6 (Suspend) is set to “1,” the power of the transmit transceiver will be turned off, the internal RAM will be in the suspend
mode, and the internal clocks will be disabled. Note. Any activity on the USB bus (i.e., K-State, etc.) will resume normal operation.
To resume normal operation from the CPU side, a data Write cycle (i.e., A0 set HIGH for a data Write cycle) should be done.
5.3.5
Interrupt Enable Register, Address [06H]
The SL811HS provides an Interrupt Request Output, which can be activated on a number of conditions. The Interrupt Enable
Register allows the user to select conditions that will result in an Interrupt being issued to an external CPU. A separate Interrupt
Status Register is provided. It can be polled in order to determine those conditions that initiated the interrupt. (See Interrupt Status
Register description.) When a bit is set to “1” the corresponding interrupt is enabled.
Bit Position
Bit Name
Function
0
USB-A
USB-A Done Interrupt
1
USB-B
USB-B Done Interrupt
2
Reserved
3
Reserved
4
SOF Timer
5
Inserted/Removed
6
Device Detect/Resume
1 = Enable Interrupt on 1-ms SOF Timer
Slave Insert/Remove Detection
Enable Device Detect/Resume Interrupt
• Bits 0–1 are used for the USB A/B controller interrupt.
• Bit 4 is used to enable/disable the SOF timer. To utilize this bit function, bit 0 of register 05H must be enabled and the SOF
counter registers 0EH and 0FH must be initialized.
• Bit 5 is used to enable/disable the device inserted/removed interrupt.
• When bit-6 of register 05H is set = “1,” bit 6 of this register enables the Resume Detect Interrupt. Otherwise, this bit is used
to enable Device detection status as defined in the Interrupt Status Register bit definitions.
Note:
2. Force K-State for low speed.
3. Force J-State for low speed.
Document #: 38-08008 Rev. *A
Page 13 of 29
SL811HS
5.3.6
USB Address Register, Reserved, Address [07H]
This register is reserved for the device USB Address in Slave operation. It should not be written by the user.
5.3.7
Interrupt Status Register, Address [0DH]
The ISR is a Read/Write register providing interrupt status. Interrupts can be cleared by writing to this register. To clear a specific
interrupt, the register is written with corresponding bit set to “1.”
Bit Position
Bit Name
Function
0
USB-A
USB-A Done Interrupt
1
USB-B
USB-B Done Interrupt
2
Reserved
3
Reserved
4
SOF timer
5
Insert/Remove
Slave Insert/Remove Detection
6
Device Detect/Resume
Device Detect/Resume Interrupt
7
D+
1 = Interrupt on 1-ms SOF Timer
Value of the Data+ Pin
• Bit 5 is provided to support USB cable Insertion/Removal for the SL811HS in Host Mode. This bit is set when a transition from
SE0 to IDLE (device inserted) or IDLE to SE0 (device removed) occurs on the bus.
• Bit 6 is shared between Device Detection status and Resume detection interrupt. When bit-6 of register 05H is set to one, this
bit will be the Resume detection Interrupt bit. Otherwise, this bit is used to indicate the presence of a Device, “1” = device “Not
present” and “0” = device “Present.” In this mode this bit should be checked along with bit 5 to determine whether a device
has been inserted or removed.
• Bit 7 provides continuous USB Data+ line status. Once it has been determined that a device has been inserted as described
above with bits 5 and 6, bit 7 can be used to detect if the inserted device is low- or full-speed.
5.3.8
Current Data Set Register/Hardware Revision/SOF Counter LOW, Address [0EH]
• This register has two modes: a Read from this register indicates the current SL811HS silicon revision.
Bit Position
Bit Name
Function
0
Reserved
Reserved for slave
1
Reserved
Reserved for slave
2
Reserved
Read will be zero
3
Reserved
Read will be zero
4–7
HW Revision
SL11H Read = 0H, SL811HS rev1.2 Read = 1H, SL811HS
rev1.5 Read = 2
• Writing to this register will set up auto generation of SOF to all connected peripherals. This counter is based on the 12-MHz
clock. To set up a 1-ms timer interval, the software must set up both SOF counter registers to the proper values.
Bit Position
Bit Name
0–7
SOF LOW Counter Register
Function
Write-only to set SOF LOW Counter Register, OEH
• Example. To set up SOF for 1-ms interval, SOF counter register 0EH should be set to E0H.
Document #: 38-08008 Rev. *A
Page 14 of 29
SL811HS
5.3.9
SOF Counter HIGH/Control2 Register, Address [0FH, READ/WRITE]
When writing to this register the bits definition are defined as follows.
Bit Position
Bit Name
Function
0–5
SOF HIGH Counter Register
Write a value or read it back to SOF HIGH Counter Register
6
SL811HS D+/D– Data Polarity
Swap
Write/Read, set “1” change polarity, “0” no change of polarity
7
SL811HS Master/Slave selection
Write/Read, “1” is master, else Slave
Note. Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS which
enables additional features not supported by the SL11H. For SL11H hardware backward compatibility, this register should not be
accessed.
The USB-B register set can be used when SL811HS full feature bit is enabled. Example. To set up for 1-ms SOF time:
The register 0FH contains the upper 6 bits of the SOF timer. Register 0EH contains the lower 8 bits of the SOF timer. The
timer is based on a 12-MHz clock and uses a counter, which counts down to zero from an initial value. To set the timer for 1
ms time, the register 0EH should be loaded with value E0H, register 0F, Bits 0–5 should be loaded with 2EH. To start the timer,
bit 0 of register 05H should be set to “1.” To load both HIGH and LOW registers with the proper values the user must follow
this sequence:
— Write E0H to register 0EH.
— Write 2EH to register 0FH, bits 0–5. Bits 6 and 7 should be set for appropriate function: polarity and Master/Slave.
— Enable bit 0 in register 05H.
Note. Any Write to the 0FH register will clear the internal frame counter. Register 0FH must be written at least once after power-up.
The internal frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which is
used to track the frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave
every millisecond in a SOF packet.
D7
D6
D5
D4
D3
D2
D1
D0
C13
C12
C11
C10
C9
C8
C7
C6
C13–C6
Top 8 bits of 14-bit SOF counter.
When read, this register will return the value of the SOF counter divided by 64. The software should use this register to determine
the available bandwidth in the current frame before initiating any USB transfer. In this way, the user will be able to avoid babble
conditions on the USB. For example, to determine the available bandwidth left in a frame:
Maximum number of clock ticks in 1-ms time frame is 12000(1 count per 12-MHz clock period, or approximately 84 ns.) The value
read back in Register 0FH is the (count × 64) × 84 ns = time remaining in current frame. USB bit time = one 12-MHz period.
Value of register 0FH
Available bit times left are between
BBH
12000 bits to 11968 (187 × 64) bits
BAH
11968 bits to 11904 (186 × 64) bits
Document #: 38-08008 Rev. *A
Page 15 of 29
SL811HS
6.0
SL811HS and SL811HST-AC Physical Connections
This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC).
6.1
SL811HS Physical Connections
6.1.1
SL811HS Pin Layout
Pins 2 and 3 should be No Connect in Host Mode. See Pin and Signal Description.
nRD
VDD1
NC*
A0
N C*
M/S
D7
26
4
3
1
27
28
D6
6
24
D5
7
23
D4
22
G nd
5
nCS
CM
VDD2
2
25
nW R
8
DATA +
9
DATA -
10
G nd
11
SL811HSH
21
28 PLCC
20
19
13
14
15
16
17
12
D3
D2
D1
18
VDD 1
INTR Q
X2
CLK/X 1
nRST
D0
G nd
Figure 6-1. SL811HS USB Host/Slave Controller—Pin Layout
6.1.2
28-Pin PLCC Mechanical Dimensions
Document #: 38-08008 Rev. *A
Page 16 of 29
SL811HS
6.1.3
SL811HS USB Host Controller Pins Description
The SL811HS package is a 28-pin PLCC. The device requires 3.3 VDC. Average typical current consumption is less then 20 mA
for 3.3V.
Table 6-1. SL811HS Pin Assignments and Definitions
Pin No.
Pin Type
Pin Name
Pin Description
1
IN
A0
A0 = “0.” Selects Address Pointer. Reg. Write Only. Selects Data Buffer or Register.
R/W.[4]
2
IN
nDACK
DMA Acknowledge. An active LOW input used to interface to an external DMA
controller. This works only in slave mode. In host mode, pin should be tied to Logic “1”
in Host Mode.
3
OUT
nDRQ
DMA Request. An active LOW output used with an external DMA controller. nDRQ and
nDACK form the handshake for DMA data transfers. In host mode, pin must be left
unconnected in Host Mode.
4
IN
nRD
Read Strobe Input. An active LOW input used with nCS to Read registers/data memory.
5
IN
nWR
Write Strobe Input. An active LOW input used with nCS to Write to registers/data
memory.
6
IN
nCS
Active LOW Chip Select. Used with nRD and nWD when accessing SL811HS.
7
IN
CM
Clock Mode. Select Internal 4 X Clock Multiplier. “1” enables 4X clock multiplier. “0”
Disables.[5]
8
VDD1
+3.3 VDC
9
BIDIR
DATA +
USB Differential Data Signal HIGH Side
10
BIDIR
DATA -
USB Differential Data Signal LOW Side
11
GND
USB GND
Ground Connection for USB
12
VDD
+3.3 VDC
SL811HS Device VDD Power[6]
13
IN
CLK/X1
14
OUT
X2
15
IN
nRST
SL811HS Device Active LOW Reset Input
16
OUT
INTRQ
Active HIGH Interrupt Request Output to External Controller
17
GND
GND
18
BIDIR
D0
Data 0. Microprocessor Data/(Address) Bus
19
BIDIR
D1
Data 1. Microprocessor Data/(Address) Bus
20
BIDIR
D2
Data 2. Microprocessor Data/(Address) Bus
21
BIDIR
D3
Data 3. Microprocessor Data/(Address) Bus
22
GND
GND
23
BIDIR
D4
Data 4. Microprocessor Data/(Address) Bus
24
BIDIR
D5
Data 5. Microprocessor Data/(Address) Bus
25
BIDIR
D6
Data 6. Microprocessor Data/(Address) Bus
26
BIDIR
D7
Data 7. Microprocessor Data/(Address) Bus
27
IN
M/S
Master/Slave Select. Host = “0,” Slave = “1”
28
VDD
+3.3 VDC
Power for USB Transceivers
12-/48-MHz Clock or External Crystal X1 Connection[7]
External Crystal X2 Connection
SL811HS Device Ground
SL811HS Device Ground
SL811HS Device VDD Power
Notes:
4. The A0 Address bit is used to access address or data registers in I/O-mapped or memory-mapped applications.
5. The CM Clock Multiplier pin should be tied HIGH for a 12-MHz clock source and tied to ground for a 48-MHz clock source. In SL11H, this pin was designated
as an ALE input pin.
6. VDD can be derived from the USB supply. The diagram below shows a simple method to provide 3.3V/30 mA. Another option is to use a Torex Semiconductor,
Ltd. 3.3V SMD regulator (part number XC62HR3302MR).
7. The X1/X2 clock requires external 12- or 48-MHz matching crystal or clock source.
Document #: 38-08008 Rev. *A
Page 17 of 29
SL811HS
The Diagram below illustrates a simple +3.3V voltage source.
98 6%
5 2KPV 1 = HQH U
Y1&7
* 1 '
6.1.4
99''
6DP SOH9''*HQHUDWRU
Package Markings (SL811HS)
YYWW = Date code
XXXX = Product code
X.X = Silicon revision number
Document #: 38-08008 Rev. *A
Page 18 of 29
SL811HS
6.2
SL811HST-AC Physical Connections
6.2.1
SL811HST-AC Pin Layout
[16]
NC
nRD
NC
NC
NC
NC
NC
D7
VDD
A0
M/SDD
NC
37
1
36
48
NC
NC
NC
NC
nWR
NC
nCS
D6
CM
D5
SL811HST
VDD1
Data+
D4
GND
Data-
D3
USBGnd
D2
NC
D1
NC
NC
NC
12
24
25
NC
13
NC
NC
nRST
GND
Clk/X1
VDD
D0
INTRQ
X2
NC
NC
NC
Figure 6-2. SL811HST-AC USB Host/Slave Controller Pin Layout
6.2.2
Mechanical Dimensions 48-Pin TQFP
Note:
8. NC. Indicates No Connection. NC Pins should be left unconnected.
Document #: 38-08008 Rev. *A
Page 19 of 29
SL811HS
6.2.3
SL811HST-AC USB Host Controller Pins Description
The SL811HST-AC is packaged in a 48-pin TQFP. The device requires a 3.3VDC power source. The SL811HST-AC requires an
external 12 or 48 MHz crystal or Clock.
Table 6-2. SL811HST-AC Pin Assignments and Definitions
Pin No.
Pin Type
Pin Name
Pin Description
1
NC
NC
NC
2
NC
NC
NC
3
IN
nWR
Write Strobe Input. An active LOW input used with nCS to Write to
registers/data memory.
4
IN
nCS
Active LOW SL811HST-AC Chip select. Used with nRD and nWr when
accessing SL811HT.
5
IN
CM
Clock Mode. Select 12-MHz/48-MHz Clock Source.[9]
6
VDD1
+3.3 VDC
7
BIDIR
DATA +
USB Differential Data Signal HIGH Side
8
BIDIR
DATA -
USB Differential Data Signal LOW Side
9
GND
USB GND
10
NC
NC
NC
11
NC
NC
NC
12
NC
NC
NC
13
NC
NC
NC
14
NC
NC
NC
15
VDD
+3.3 VDC
16
IN
CLK/X1
17
OUT
X2
18
IN
NRST
SL811HST-AC Device active low reset input
19
OUT
INTRQ
Active HIGH Interrupt Request output to external controller
20
GND
GND
21
BIDIR
D0
Data 0. Microprocessor Data/(Address) Bus.
22
NC
NC
NC
23
NC
NC
NC
24
NC
NC
NC
25
NC
NC
NC
26
NC
NC
NC
27
BIDIR
D1
Data 1. Microprocessor Data/(Address) Bus.
28
BIDIR
D2
Data 2. Microprocessor Data/(Address) Bus.
29
BIDIR
D3
Data 3. Microprocessor Data/(Address) Bus.
30
GND
GND
31
BIDIR
D4
Data 4. Microprocessor Data/(Address) Bus.
32
BIDIR
D5
Data 5. Microprocessor Data/(Address) Bus.
Power for USB Transceivers. VDD1 may be connected to VDD.
Ground Connection for USB
SL811HST-AC Device VDD Power[10]
Clock or External Crystal X1 connection[11]
External Crystal X2 connection
SL811HST-AC Device Ground
SL811HST-AC Device Ground
Notes:
9. The CM Clock Multiplier pin should be tied HIGH for a 12-MHz clock source and tied to ground for a 48-MHz clock source. In SL11H, this pin was designated
as ALE input pin.
10. VDD can be derived from the USB supply. See diagram.
11. The X1/X2 Clock requires external 12- or 48-MHz matching crystal or clock source.
Document #: 38-08008 Rev. *A
Page 20 of 29
SL811HS
Table 6-2. SL811HST-AC Pin Assignments and Definitions (continued)
Pin No.
Pin Type
Pin Name
Pin Description
33
BIDIR
D6
Data 6. Microprocessor Data/(Address) Bus.
34
NC
NC
NC
35
NC
NC
NC
36
NC
NC
NC
37
NC
NC
NC
38
NC
NC
NC
39
BIDIR
D7
Data 7. Microprocessor Data/(Address) Bus.
40
IN
M/S
Master/Slave Mode Select. “1” selects Slave. “0” = Master.
41
VDD
+3.3 VDC
42
IN
A0
43
IN
nDACK
DMA Acknowledge. An active LOW input used to interface to an
external DMA controller. DMA is enabled only in slave mode. In host
mode, pin should be tied HIGH (logic “1”) .
44
OUT
nDRQ
DMA Request. An active LOW output used with an external DMA
controller. nDRQ and nDACK form the handshake for DMA data
transfers. In host mode, pin must be left unconnected .
45
IN
NRD
Read Strobe Input. An active LOW input used with nCS to Read
registers/data memory.
46
NC
NC
NC
47
NC
NC
NC
48
NC
NC
NC
SL811HST-AC Device VDD Power.
A0 = “0.” Selects address pointer. Reg.A0 = “1.” Selects data buffer or
register.[12]
Notes:
12. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.
6.2.4
Package Markings (SL811HST-AC)
SL811HST
YYWW-X.X
XXXX
YYWW = Date code
XXXX = Product code
X.X = Silicon revision number
Document #: 38-08008 Rev. *A
Page 21 of 29
SL811HS
7.0
Electrical Specifications
7.1
Absolute Maximum Ratings
This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to
the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability.
Storage Temperature
–40°C to 125°C
Voltage on any pin with respect to ground
–0.3V to 6.0V
Power Supply Voltage (VDD)
4.0 V
Power Supply Voltage (VDD1)
4.0 V
Lead Temperature (10 seconds)
180°C
7.2
Recommended Operating Condition
Parameter
Min.
Typical
Max.
Power Supply Voltage, VDD
3.0V
3.3 V
3.45V
Power Supply Voltage, VDD1
3.0V
3.45V
Operating Temperature
0°C
65°C
Crystal Requirements,
(X1, X2)
Min.
Operating Temperature Range
Parallel Resonant Frequency
Typical
0°C
[13]
Max.
65°C
48 MHz
Frequency Drift over Temperature
±50 ppm
Accuracy of Adjustment
±30 ppm
Series Resistance
100 ohms
Shunt Capacitance
3 pF
Load Capacitance
20 pF
20 µW
Drive Level
Mode of Vibration Third Overtone
7.3
6 pF
5 mW
[14]
External Clock Input Characteristics (X1)
Parameter
Clock Input Voltage @ X1 (X2 Open)
Min.
Typical
Max.
1.5 V
[15]
Clock Frequency
48 MHz
Notes:
13. The SL811HS can use a 12-MHz Crystal Oscillator or 12-MHz Clock Source.
14. Fundamental mode for 12-MHz Crystal.
15. The SL811HS can use a 12-MHz Clock Source.
Document #: 38-08008 Rev. *A
Page 22 of 29
SL811HS
7.4
DC Characteristics
Parameter
Description
Min.
Typ.
Max.
VIL
Input Voltage LOW
–0.3 V
0.8V
VIH
Input Voltage HIGH (5V Tolerant I/O)
2.0 V
6.0V
VOL
Output Voltage LOW (IOL = 4 mA)
VOH
Output Voltage HIGH (IOH = –4 mA)
2.4 V
IOH
Output Current HIGH
4 mA
IOL
Output Current LOW
4 mA
ILL
Input Leakage
±1 µA
Input Capacitance
10 pF
CIN
ICC
[16]
0.4V
Supply Current (VDD) inc USB @FS
21 mA
25 mA
ICCsus1[17]
ICCsus2[18]
Supply Current (VDD) Suspend w/Clk & Pll Enb
4.2 mA
5 mA
Supply Current (VDD) Suspend no Clk & Pll Dis
50 µA
60 µA
IUSB
Supply Current (VDD1)
10 mA
IUSBSUS
Transceiver Supply Current in Suspend
10 µA
7.5
USB Host Transceiver Characteristics
Parameter
Description
Min.
Typ.[19]
Max.
VIHYS
Differential
Input Sensitivity (Data+, Data–)
0.2V
200 mV
VUSBIH
USB Input Voltage HIGH Driven
2.0
VUSBIL
USB Input Voltage LOW
0.8V
VUSBOH
USB Output Voltage HIGH
2.0V
VUSBOL
USB Output Voltage LOW
0.0V
0.3 V
ZUSBH[20]
ZUSBL[20]
Output Impedance HIGH STATE
36 Ohms
42 Ohms
Output Impedance LOW STATE
36 Ohms
42 Ohms
IUSB
Transceiver Supply p-p Current (3.3V)
10 mA
@ FS
Every VDD pin, including USB VDD, has to have a decoupling capacitor to ensure clean VDD (free of high-frequency noise) at the
chip input point (pin) itself.
The best way to do this is to connect a ceramic capacitor (0.1 µF, 6V) between the pin itself and a good ground. Capacitor leads
must be kept as short as possible. Use surface mount capacitors with the shortest traces possible (the use of a ground plane is
strongly recommended).
Notes:
16. ICC measurement includes USB Transceiver current (IUSB) operating at Full Speed.
17. ICCsus1 measured with 12-MHz Clock Input and Internal PLL enabled. Suspend set –(USB transceiver and internal Clocking disabled).
18. ICCsus2 measured with external Clock, PLL disabled, and Suspend set. For absolute minimum current consumption, ensure that all inputs to the device are at
static logic level.
19. All typical values are VDD = 3.3V and TAMB= 25°C.
20. =86%; impedance values includes an external resistor of 24 Ohms ± 1% (SL811HS revision 1.2 requires external resistor values of 33 Ohms ±1%).
Document #: 38-08008 Rev. *A
Page 23 of 29
SL811HS
7.6
Bus Interface Timing Requirements
7.6.1
I/O Write Cycle
twrhigh
twr
nWR
twasu
twahld
twdsu
twdhld
A0
Register or Memory
Address
D0-D7
twcsu
twdsu
twdhld
DATA
twshld
nCS
Tcscs See Note.
I/O Write Cycle to Register or Memory Buffer
Note: nCS an be held LOW for multiple Write cycles provided nWR is cycled.
Parameter
Description
Min.
tWR
Write pulse width
65 ns
tWCSU
Chip select set-up to nWR LOW
0 ns
tWSHLD
Chip select hold time
After nWR HIGH
0 ns
tWASU
A0 address set-up time
65 ns
tWAHLD
A0 address hold time
10 ns
tWDSU
Data to Write HIGH set-up time
60 ns
tWDHLD
Data hold time after Write HIGH
5 ns
tCSCS
nCS inactive to nCS* asserted
85 ns
tWRHIGH
NWR HIGH
85 ns
Typ.
Max.
Write Cycle Time for Auto Inc Mode Writes is 150 ns minimum.
Document #: 38-08008 Rev. *A
Page 24 of 29
SL811HS
7.6.2
I/O Read Cycle
twr
twrrdl
nWR
twahld
twasu
A0
trdp
nRD
twdhld
twdsu
Register or Memory
Address
D0-D7
tracc
trdhld
DATA
trcsu
trshld
nCS
Tcscs *Note
I/O Read Cycle from Register or Memory Buffer
Parameter
Description
Min.
tWR
Write pulse width
65 ns
tRD
Read pulse width
65 ns
tWCSU
Chip select set-up to nWR
tWASU
A0 address set-up time
65 ns
tWAHLD
A0 address hold time
10 ns
tWDSU
Data to Write HIGH set-up time
60 ns
tWDHLD
Data hold time after Write HIGH
5 ns
tRACC
Data valid after Read LOW
20 ns
tRDHLD
Data hold after Read HIGH
5 ns
tRCSU
Chip select LOW to Read LOW
0 ns
tRSHLD
NCS hold after Read HIGH
0 ns
TCSCS*
nCS inactive to nCS *asserted
85 ns
tWRRDL
nWR HIGH to nRD LOW
85ns
Typ.
Max.
0 ns
25 ns
Note. NCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is
150 ns minimum.
Document #: 38-08008 Rev. *A
Page 25 of 29
SL811HS
7.6.3
Reset Timing
treset
nRST
tioact
nRD or nWR
RESET TIMING
Parameter
Description
Min.
tRESET
nRst Pulse width
16 clocks
tIOACT
nRst HIGH to nRD or nWR active
16 clocks
Typ.
Max.
Note. Clock is 48-MHz nominal.
Document #: 38-08008 Rev. *A
Page 26 of 29
SL811HS
7.6.4
Clock Timing Specifications
tclk
tlow
CLK
thigh
tfall
trise
CLOCK TIMING
Parameter
Description
Min.
Typ.
20.0 ns
20.8 ns
Max.
tCLK
Clock Period (48 MHz)
tHIGH
Clock HIGH Time
9 ns
11 ns
tLOW
Clock LOW Time
9 ns
11 ns
tRISE
Clock rise Time
5.0 ns
tFALL
Clock fall Time
5.0 ns
Clock Duty Cycle
Document #: 38-08008 Rev. *A
45%
55%
Page 27 of 29
SL811HS
8.0
Package Diagrams
28-pin PLCC
48-pin TQFP
Intel is a registered trademark of Intel Corporation. Torex is a trademark of Torex Semiconductors, Ltd. SL811HS is a trademark
of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of
their respective holders.
Document #: 38-08008 Rev. *A
Page 28 of 29
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
SL811HS
Document Title: SL811HS USB Host/Slave Controllers Hardware Specification
Document Number: 38-08008
ECN NO.
Issue
Date
**
110850
12/14/01
BHA
Converted to Cypress format from ScanLogic
*A
112687
03/22/02
MUL
1) Changed power supply voltage to 4.0V in section 7.1
2) Changed value of twdsu in section 7.6.2
3) Changed max. power supply voltage to 3.45 V in section 7.2
4) Changed accuracy of adjustment in section 7.2
5) Changed bits 0 and 1 to reserved in section 5.3.8
6) Changed bit 2 to reserved in section 5.3.5 and 5.3.7
7) Changed bit 2 to reserved in section 5.3.1
8) Changed definition of bit 6 in section 5.3.5 & 5.3.7
9) Added section 5.1, Register Values on Power-up and Reset
10) Changed bit description notes in section 5.3.7
11) Changed note about series termination resistors in section 7.5
12) Changed example in section 5.3.9
13) Changed J-K Programming States table in section 5.3.2
14) Added and removed comments for low-power modes in section 5.3.4
15) Removed sections specific to slave operation and SL11H
16) Removed duplicate tables
17) General formatting changes to section headings
18) Fixed all part number references
19) Added comments to section 7.5 and new definitions to section 2.0
REV.
Document #: 38-08008 Rev. *A
Orig. of
Change
Description of Change
Page 29 of 29
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