Congatec conga QA3, QA3E Qseven modules User’s Guide

Qseven

®

conga-QA3/QA3E

Third Generation Intel

®

Atom™ and Intel

®

Celeron

®

SoC

User’s Guide

Revision 1.0

Revision History

Revision Date (yyyy.mm.dd) Author Changes

1.0

2015.10.16

AEM

• Merged the conga-QA30 with the conga-QA3E user’s guide, to create a single user’s guide. Revision 1.0 is the first revision for the combined user’s guide.

• Added note about USB overcurrent protection in section 5.5 “USB 2.0”, section 7.3 “xHCI & EHCI Port Mapping” and table 9 “USB Signal Description”.

2/88

Preface

This user’s guide provides information about the components, features, connector and BIOS Setup menus available on the conga-QA3/QA3E.

It is one of three documents that should be referred to when designing a Qseven be used include the following:

® application. The other reference documents that should

Qseven

®

Design Guide

Qseven

®

Specification

The links to these documents can be found on the congatec AG website at www.congatec.com

Disclaimer

The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice.

congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof.

Intended Audience

This user’s guide is intended for technically qualified personnel. It is not intended for general audiences.

Lead-Free Designs (RoHS)

All congatec AG designs are created from lead-free components and are completely RoHS compliant.

Electrostatic Sensitive Device

All congatec AG products are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a congatec AG product except at an electrostatic-free workstation. Additionally, do not ship or store congatec AG products near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original manufacturer’s packaging. Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty.

3/88

Symbols

The following symbols are used in this user’s guide:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note

Notes call attention to important information that should be observed.

Copyright Notice

Copyright © 2015, congatec AG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from congatec AG.

congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”.

Trademarks

Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property of their respective trademark holders. These trademark holders are not affiliated with congatec AG, our products, or our website.

4/88

Warranty congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited warranty

(“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time.

The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license agreements, which are available at www.congatec.com and/or upon request.

Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec’s option and expense.

Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.

Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to congatec’s direct customer only and is not assignable or transferable.

Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.

congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the product only.

ISO 9001

Certification congatec AG is certified to DIN EN ISO 9001:2008 standard.

C

ER

TIFICATIO

N

TM

Technical Support congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support department by email at [email protected]

5/88

Terminology

Term

PCIe

PCI Express Lane

TMDS

DVI

LPC

I²C Bus

SM Bus

SPI Bus

GbE

LVDS

DDC

N.C.

N.A.

T.B.D.

x1, x2, x4, x8, x16 eMMC

SD card

USB

SATA

HDA

DDI

DP

HDMI

Description

Peripheral Component Interface Express – next-generation high speed Serialized I/O bus

One PCI Express Lane is a set of 4 signals that contains two differential lines for

Transmitter and two differential lines for Receiver. Clocking information is embedded into the data stream.

x1 refers to one PCI Express Lane of basic bandwidth; x2 to a collection of two PCI Express Lanes; etc.. Also referred to as x1, x2, x4, x8, or x16 link.

Embedded Multi-media Controller

Secure Digital card is a non-volatile memory card format developed for use in portable devices.

Universal Serial Bus

Serial AT Attachment: serial-interface standard for hard disks

High Definition Audio

Digital Display Interface. DDI can operate as DisplayPort, HDMI or DVI.

DisplayPort is a VESA open digital communications interface.

High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-definition video, plus multi-channel digital audio on a single cable.

Transition Minimized Differential Signaling. TMDS is a signaling interface defined by Silicon Image that is used for DVI and HDMI.

Digital Visual Interface is a video interface standard developed by the Digital Display Working Group (DDWG).

Low Pin-Count is a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy device support into a single IC.

Inter-Integrated Circuit Bus is a simple two-wire bus with a software-defined protocol that was developed to provide the communications link between integrated circuits in a system.

System Management Bus is a popular derivative of the I²C-bus.

Serial Peripheral Interface is a synchronous serial data link standard that operates in full duplex mode.

Gigabit Ethernet

Low-Voltage Differential Signaling

Display Data Channel is an I²C bus interface between a display and a graphics adapter.

Not connected

Not available

To be determined

6/88

Contents

1 Introduction ............................................................................. 10

1.1 Qseven

1.2

1.3

®

Concept .................................................................... 10

conga-QA3 Options Information ............................................. 11

conga-QA3E Options Information ........................................... 13

2 Specifications ........................................................................... 14

2.5.2

2.5.3

2.5.4

2.5.5

2.5.6

2.5.7

2.5.8

2.5.9

2.1

2.2

2.3

2.4

2.4.1

2.4.2

2.5

2.5.1

2.5.10

2.6

2.6.1

2.7

Feature List .............................................................................. 14

Supported Operating Systems ................................................ 15

Mechanical Dimensions ........................................................... 15

Supply Voltage Standard Power .............................................. 16

Electrical Characteristics .......................................................... 16

Rise Time ................................................................................. 16

Power Consumption ................................................................ 17

conga-QA3 Intel

®

Atom™ E3845 Quad Core 1.91 GHz ......... 18 conga-QA3 Intel

conga-QA3 Intel

®

conga-QA3 Intel

®

Celeron

®

J1900 Quad Core 2.0/2.42 GHz.. 20

®

Atom™ E3827 Dual Core 1.75 GHz ........... 18

conga-QA3 Intel

®

Atom™ E3826 Dual Core 1.46 GHz ........... 19 conga-QA3 Intel

®

Atom™ E3825 Dual Core 1.33 GHz ........... 19 conga-QA3 Intel

®

Atom™ E3815 Single Core 1.46 GHz ........ 19

Celeron ® N2930 Quad Core 1.83/2.16 GHz 20 conga-QA3 Intel

®

Celeron

®

N2807 Dual Core 1.58/2.16 GHz 20

conga-QA3E Intel

®

Atom™ E3815 Single Core 1.46 GHz ...... 21 conga-QA3E Intel

®

Atom™ E3845 Quad Core 1.91 GHz ....... 21

Supply Voltage Battery Power ................................................. 21

CMOS Battery Power Consumption ........................................ 22

Environmental Specifications ................................................... 22

3 Block Diagram .......................................................................... 23

4 Heatspreader ........................................................................... 24

4.1

5

Heatspreader Dimensions ........................................................ 25

Connector Subsystems ............................................................ 26

5.1 PCI Express™ ........................................................................... 27

5.2 ExpressCard™ ......................................................................... 27

5.3 Gigabit Ethernet ...................................................................... 27

5.4

5.5

5.6

5.7

Serial ATA™ (SATA) .................................................................. 27

USB 2.0 .................................................................................... 27

USB 3.0 .................................................................................... 28

SD Card .................................................................................... 28

5.8 UART ........................................................................................ 28

5.9 High Definition Audio (HDA) ................................................... 28

Digital Display Interface ........................................................... 28 5.10

5.10.1 LVDS/eDP ................................................................................. 29

5.10.2 DisplayPort ............................................................................... 29

5.10.3 HDMI ........................................................................................ 30

5.10.4 DVI ........................................................................................... 30

5.11 LPC ........................................................................................... 30

5.12 SPI ............................................................................................ 30

5.13

5.14

5.15

5.16

I²C Bus ..................................................................................... 31

CAN Bus .................................................................................. 31

Power Control .......................................................................... 31

Power Management ................................................................. 32

6 Additional Features .................................................................. 33

6.3

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.4

6.5

6.1

6.1.1

6.1.2

6.2

Onboard Interfaces .................................................................. 33

MIPI-CSI 2.0 ............................................................................. 33 eMMC 4.5 ................................................................................ 33 congatec Board Controller (cBC) ............................................. 33

6.2.1

6.2.2

Board Information .................................................................... 34

Fan Control .............................................................................. 34

6.2.3 Power Loss Control .................................................................. 34

6.2.4 Watchdog ................................................................................ 34

Embedded BIOS ...................................................................... 34

CMOS Backup in Non Volatile Memory ................................... 34

OEM CMOS Default Settings and OEM BIOS Logo ............... 35

OEM BIOS Code ...................................................................... 35 congatec Battery Management Interface ................................ 35

API Support (CGOS/EAPI) ....................................................... 35

Suspend to RAM ...................................................................... 36

ECC Memory Support .............................................................. 36

7 conga Tech Notes .................................................................... 37

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7.1

7.1.1

Intel Bay Trail SoC Features ..................................................... 37

Processor Core ......................................................................... 37

7.1.1.1 Intel Virtualization Technology ................................................. 37

7.1.1.2 AHCI ........................................................................................ 38

7.1.1.3 IDE Mode (Native Vs. Legacy) ................................................. 38

7.1.1.4 Thermal Management ............................................................. 38

7.2

7.3

ACPI Suspend Modes and Resume Events .............................. 39

xHCI and EHCI Port Mapping .................................................. 40

8 Signal Descriptions and Pinout Tables ..................................... 41

9 System Resources .................................................................... 59

9.1

9.1.1

9.2

9.3

9.4

9.5

10

I/O Address Assignment .......................................................... 59

LPC Bus .................................................................................... 59

PCI Configuration Space Map ................................................. 60

PCI Interrupt Routing Map ....................................................... 61

I²C Bus ..................................................................................... 61

SM Bus ..................................................................................... 61

BIOS Setup Description ........................................................... 62

10.1

10.1.1

10.2

10.3

10.4

10.4.1

10.4.2

10.4.3

Entering the BIOS Setup Program. .......................................... 62

Boot Selection Popup .............................................................. 62

Setup Menu and Navigation .................................................... 62

Main Setup Screen ................................................................... 63

Advanced Setup ...................................................................... 64

Watchdog Submenu ................................................................ 65

Graphics Submenu ................................................................... 67

Hardware Health Monitoring Submenu ................................... 68

10.4.4

10.4.5

10.4.6

10.4.7

RTC Wake Submenu ................................................................ 68

Module Serial Ports Submenu ................................................. 68

ACPI Submenu ......................................................................... 69

Intel(R) Smart Connect Technology Submenu ......................... 69

10.4.8 Serial Port Console Redirection Submenu ............................... 70

10.4.8.1 Console Redirection Settings COM0 Submenu ....................... 70

10.4.8.2 Console Redirection Settings Out-of-Band Management

Submenu 71

10.4.9 CPU Configuration Submenu ................................................... 71

10.4.9.1 Socket 0 CPU Information Submenu ....................................... 72

10.4.9.2 CPU Thermal Configuration Submenu..................................... 72

10.4.10 PPM Configuration Submenu .................................................. 72

10.4.11 Thermal Configuration ............................................................. 73

10.4.12 IDE Configuration Submenu .................................................... 74

10.4.13 Miscellaneous Configuration Submenu ................................... 74

10.4.14 SCC Configuration Submenu ................................................... 75

10.4.15 Network Stack .......................................................................... 75

10.4.16 CSM Submenu ......................................................................... 75

10.4.17 SDIO Submenu ........................................................................ 76

10.4.18 Trusted Computing Submenu .................................................. 77

10.4.19 USB Submenu .......................................................................... 77

10.4.20 Platform Trust Technology ....................................................... 78

10.4.21 Security Configuration ............................................................. 78

10.4.22 SIO Submenu ........................................................................... 78

10.4.22.1 Serial Port 1 Submenu ............................................................. 79

10.4.22.2 Serial Port 2 Submenu ............................................................. 79

10.4.22.3 Parallel Port Submenu .............................................................. 79

10.4.22.4 PS2 Controller (KB&MS) Submenu .......................................... 80

10.4.23 Intel(R) Ethernet Connection I210 Submenu ........................... 80

10.4.23.1 NIC Configuration Submenu ................................................... 80

10.4.24 Driver Health Submenu ............................................................ 81

10.4.24.1 Intel(R) PRO/1000 Submenu .................................................... 81

10.5

10.5.1

10.5.2

Chipset Setup .......................................................................... 81

North Bridge Submenu ............................................................ 81

South Bridge Submenu ............................................................ 81

10.5.2.1 Azalia HD Audio ....................................................................... 82

10.5.2.2 USB Submenu .......................................................................... 83

10.5.2.3 PCI Express Configuration Submenu ....................................... 84

10.6

10.6.1

10.7

10.7.1

10.7.2

10.8

Boot Setup ............................................................................... 84

Boot Settings Configuration .................................................... 84

Security Setup .......................................................................... 86

Security Settings ...................................................................... 86

Hard Disk Security .................................................................... 86

Save & Exit Menu ..................................................................... 86

11

11.1

11.2

12

Additional BIOS Features ........................................................ 87

Supported Flash Devices ......................................................... 87

Updating the BIOS ................................................................... 87

Industry Specifications ............................................................. 88

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List of Tables

Table 1 Feature Summary ..................................................................... 14

Table 2 Display Combination ............................................................... 29

Table 3 Signal Tables Terminology Descriptions .................................. 41

Table 4 Edge Finger Pinout .................................................................. 42

Table 5 PCI Express Signal Descriptions .............................................. 46

Table 6 UART Signal Descriptions ........................................................ 47

Table 8 SATA Signal Descriptions ......................................................... 48

Table 9 USB Signal Descriptions ........................................................... 48

Table 10 SDIO Signal Descriptions ......................................................... 49

Table 11 HDA Signal Descriptions .......................................................... 50

Table 12 LVDS Signal Descriptions ......................................................... 51

Table 13 DisplayPort Signal Descriptions ............................................... 52

Table 14 HDMI/DVI Signal Descriptions ................................................. 53

Table 15 LPC Signal Descriptions ........................................................... 53

Table 16 SPI Interface Signal Descriptions ............................................. 54

Table 17 CAN Bus Signal Descriptions ................................................... 54

Table 18 Power and GND Signal Descriptions ....................................... 55

Table 19 Power Control Signal Descriptions .......................................... 55

Table 20 Power Management Signal Descriptions ................................. 55

Table 21 Miscellaneous Signal Descriptions ........................................... 56

Table 22 Manufacturing Signal Descriptions .......................................... 56

Table 23 Thermal Management Signal Descriptions .............................. 57

Table 24 Fan Control Signal Descriptions .............................................. 57

Table 25 Onboard Camera Interface Signal Descriptions ...................... 57

Table 26 PCI Configuration Space Map ................................................. 60

Table 27 PCI Interrupt Routing Map ....................................................... 61

9/88

1 Introduction

1.1 Qseven

®

Concept

The Qseven ® concept is an off-the-shelf, multi vendor, Single-Board-Computer that integrates all the core components of a common PC and is mounted onto an application specific carrier board. Qseven

®

modules have a standardized form factor of 70mm x 70mm and a specified pinout based on the high speed MXM system connector. The pinout remains the same regardless of the vendor. The Qseven

® interface and multiple USB ports.

module provides the functional requirements for an embedded application. These functions include, but are not limited to, graphics, sound, mass storage, network

A single ruggedized MXM connector provides the carrier board interface to carry all the I/O signals to and from the Qseven

MXM connector is a well known and proven high speed signal interface connector that is commonly used for high speed PCI Express graphics cards in notebooks.

®

module. This

Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a dense and optimized package, which results in a more reliable product while simplifying system integration.

The Qseven

Qseven

®

®

evaluation carrier board provides carrier board designers with a reference design platform and the opportunity to test all the

I/O interfaces available and then choose what are suitable for their application. Qseven

®

applications are scalable, which means once a carrier board has been created there is the ability to diversify the product range through the use of different performance class Qseven modules. Simply unplug one module and replace it with another, no need to redesign the carrier board.

®

This document describes the features available on the Qseven ® carrier board can be found on the congatec website.

evaluation carrier board. Additionally, the schematics for the Qseven ® evaluation

10/88

1.2 conga-QA3 Options Information

The conga-QA3 is available in various variants (commercial and industrial).This user’s guide describes all of these variants and the table below shows the different configurations available. Check for the Part No. that applies to your product. This will tell you what options described in this user’s guide are available on your particular module.

conga-QA3 (Commercial Variants)

Part-No

Processor

015100

Intel

®

Atom™ E3845

(Quad Core, 1.91 GHz)

015101

Intel

®

Atom™ E3827

(Dual Core, 1.75 GHz)

015102

Intel

®

Atom™ E3826


015103

Intel

®

Atom™ E3825


015104

Intel

®

Atom™ E3815

(Single Core, 1.46 GHz)

L2 Cache 2 MB

Onboard Memory 2GB DDR3L-1333 dual channel

Graphics Intel

®

HD Graphics

GFX Normal/Burst 542 / 792

LVDS

DDI eMMC

SD Card

Max. TDP

Single/Dual 18/24bit

DP / HDMI / DVI

4 GB

Yes

10 W

1 MB

2GB DDR3L-1333 dual channel

DP / HDMI / DVI

4 GB

Yes

8 W

1 MB


Intel

®

HD Graphics Intel

®

HD Graphics

542 / 792 533 / 667

DP / HDMI / DVI

4 GB

Yes

7 W

1 MB

2GB DDR3L-1066 single channel

Intel

4 GB

Yes

6 W

®

HD Graphics

533 / N/A

Single/Dual 18/24bit Single/Dual 18/24bit Single/Dual 18/24bit

DP / HDMI / DVI

512kB


Intel

®

HD Graphics

400 / N/A


DP / HDMI / DVI

4 GB

Yes

5 W

015105

Intel

®

Atom™ E3845


2 MB


Intel

®

HD Graphics

542 / 792


DP / HDMI / DVI

8 GB

Yes

10 W

Part-No.

Processor

015106

Intel ® Atom™ E3815


512kB L2 Cache

Onboard Memory 1GB DDR3L-1066 single channel

Graphics Intel

®

HD Graphics

GFX Normal/Burst 400 / N/A

LVDS Single/Dual 18/24bit

DDI eMMC

DP / HDMI / DVI

N/A

SD Card

Max. TDP / SDP

Yes

5 W

015107



2 MB


Intel

®

HD Graphics

542 / 792


DP / HDMI / DVI

N/A

Yes

10 W

015108



1 MB


Intel

®

HD Graphics

542 / 792


DP / HDMI / DVI

N/A

Yes

8 W

015109



2 MB


Intel

®

HD Graphics

542 / 792


DP / HDMI / DVI

N/A

Yes

10 W

015111

Intel ® Celeron ® J1900

(Quad Core, 2.0/2.42 GHz)

2 MB


Intel

®

HD Graphics

688 / 854


DP / HDMI / DVI

N/A

Yes

10 W

11/88

Part-No.

Processor

015112

Intel

®

Celeron

®

N2930

(Quad Core, 1.83/2.16 GHz)

L2 Cache 2 MB


Graphics Intel

®

HD Graphics


LVDS

DDI


DP / HDMI / DVI eMMC

SD Card

Max. TDP / SDP

N/A

Yes

7.5 / 4.5 W

015113

Intel

®

Celeron

®

N2807

(Dual Core, 1.58/2.16 GHz)

1 MB


Intel

®

HD Graphics

313 / 750


DP / HDMI / DVI

N/A

Yes

4.3 / 2.5 W

015130

Intel

®

Atom™ E3805


1 MB


None

N/A


DP / HDMI / DVI

4 GB

Yes

N/A

015131

Intel

®

Atom™ E3845


2 MB


Intel

®

HD Graphics

542 / 792


DP / HDMI / DVI

16 GB

Yes

10 W conga-QA3 (Industrial variants)

Part-No

Processor

015120

Intel

®

Atom™ E3845


2 MB

015121

Intel

®

Atom™ E3827


1 MB

015123

Intel

®

Atom™ E3825


1 MB

015124

Intel

®

Atom™ E3815


512kB L2 Cache


Graphics Intel

®

HD Graphics


Intel

®

HD Graphics


Intel

®

HD Graphics


Intel

®

HD Graphics



542 / 792 533 / N/A

Single/Dual 18/24bit Single/Dual 18/24bit

400 / N/A


DDI eMMC

SD Card

Max. TDP

DP / HDMI / DVI

4 GB

Yes

10 W

DP / HDMI / DVI

4 GB

Yes

8 W

DP / HDMI / DVI

4 GB

Yes

6 W

DP / HDMI / DVI

4 GB

Yes

5 W

015125

Intel

®

Atom™ E3845


2 MB

015126

Intel

®

Atom™ E3805


1 MB


Intel

®

HD Graphics


None

542 / 792 N/A

Single/Dual 18/24bit Single/Dual 18/24bit

DP / HDMI / DVI

8 GB

Yes

10 W

DP / HDMI / DVI

4 GB

Yes

N/A

12/88

1.3 conga-QA3E Options Information

The conga-QA3E is available in two variants. The table below shows the different configurations available. Check for the Part No. that applies to your product. This will tell you what options described in this user’s guide are available on your particular module.

conga-QA3E (Commercial Variants)

Part-No

Processor

018104

Intel

®

Atom™ E3815


512kB L2 Cache

Onboard Memory 2GB DDR3L-1066 single channel ECC

Graphics Intel

®

HD Graphics

GFX Normal/Burst 400 / N/A


DDI eMMC

DP / HDMI / DVI

4 GB (MLC)

SD Card

Max. TDP

Yes

5 W

018105

Intel

®

Atom™ E3845


2 MB

4GB DDR3L-1333 single channel ECC

Intel

®

HD Graphics

542 / 792


DP / HDMI / DVI

8 GB (MLC)

Yes

10 W

13/88

2 Specifications

2.1 Feature List

Table 1 Feature Summary

Form Factor

Based on Qseven

®

form factor specification revision 2.0

Processor

Memory

Intel

®

Atom™ E3845 /E3827 /E3826 /E3825 /E3815

Intel ® Celeron J1900 /N2930 /N2807

conga:QA3: Single or dual channel non-ECC DDR3L onboard memory interface with up to 8 GB and data rates up to 1333 MT/s. Variants equipped with Intel Atom E3815 and E3825 feature single channel memory interface.

conga:QA3E: Single channel ECC DDR3L onboard memory interface with up to 8 GB and data rates up to 1333 MT/s.

For more information, see section 1.2 “conga-QA3 Options Information” or section 1.3 “conga-QA3E Options Information”.

Integrated in SoC

Chipset

Onboard Storage eMMC 4.5 onboard flash up to 32 GB (optional only for variants equipped with Intel ® Atom™)

Audio

High Definition Audio (HDA) interface with support for multiple codecs

Ethernet

Gigabit Ethernet via the onboard Intel

®

Ethernet controller l210.

Graphics Options

Intel

®

HD Graphics with support for DirectX11, OpenGL 3.2, OpenCL 1.2, OpenGLES 2.0, full HW acceleration for decode/encode of MPEG2, H.264,

MVC and dual simultaneous display support

Peripheral

Interfaces

BIOS Features

Flat LVDS (Integrated flat panel interface with 25-112MHz single/dual-channel LVDS

Transmitter). Supports:

-

Single-channel LVDS interface: 1 x 18 bpp or 1 x 24 bpp.

-

Dual-channel LVDS interface : 2 x 18 bpp or 2 x 24 bpp.

-

VESA LVDS color mappings

-

Automatic Panel Detection via Embedded Panel Interface based on VESA EDID™ 1.3.

-

Resolution up to 1920x1200 in dual LVDS bus mode.

Optional eDP interface

(NOTE: conga-QA3/QA3E supports either eDP or LVDS. Both signals are not supported).

1x DDI (Digital Display Interface) with support for

1x DisplayPort 1.1. Multiplexed with HDMI/DVI ports.

Supports Hot-Plug detect.

1x HDMI 1.4 port. Multiplexed with DisplayPort (DP)/

DVI. Supports Hot-Plug detect

1x DVI ports. Multiplexed with HDMI/DP ports.

Supports Hot-Plug detect.

2x Serial ATA

® up to 3Gb/s

3x PCI Express

®

Gen2 links up to 5.0 GT/s per lane

USB Interfaces:

MIPI-CSI 2.0 (supported only on conga-QA3/QA3E revision B.x or newer)

UART

-

6x USB 2.0 or

-

1x USB 3.0 and 5x USB 2.0

1x SD/MMC

AMI Aptio ®

Auto Detection, Backlight Control, Flash Update)

SPI Bus

LPC Bus

I²C Bus, multimaster

UEFI 5.x firmware; 8 MByte serial SPI with congatec Embedded BIOS features (OEM Logo, OEM CMOS Defaults, LCD Control, Display

ACPI 5.0 compliant with battery support. Also supports Suspend to RAM (S3).

Power Mgmt.

congatec Board

Controller

Multi-stage watchdog, non-volatile user data storage, manufacturing and board information, board statistics, bios setup data backup, I²C bus (fast mode, 400 kHz, multi-master), power loss control

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2.2

2.3

Note

Some of the features mentioned in the above Feature Summary are optional. Check the article number of your module and compare it to the option information list on page 11 of this user’s guide to determine what options are available on your particular module.

Supported Operating Systems

The conga-QA3/QA3E supports the following operating systems:

• Microsoft

• Microsoft

®

Windows

®

Embedded Compact 7

• Microsoft

®

®

Windows

Windows

®

®

7

Embedded Standard 7

• Microsoft

®

Windows

®

8

• Microsoft

®

Windows

®

Embedded Standard 8

• Microsoft

®

Windows

®

10

• Linux (Timesys Fedora 18)

Note

For the installation of Windows 7/8 and WES7/8, congatec AG requires a minimum storage capacity of 16 GB. congatec will not offer support for systems with less than 16 GB storage space.

Mechanical Dimensions

• 70.0 mm x 70.0 mm @ (2 ¾” x 2 ¾”)

• The Qseven™ module, including the heatspreader plate, PCB thickness and bottom components, is up to approximately 12mm thick.

Heatspeader

Qseven Module PCB

2.00

Dimension is dependent on connector height used

6.00

1.20 ±0.1

All measurements are in millimeters

All dimensions without tolerance ±0.2mm

Carrier Board PCB

Rear View of Qseven Module

8.00

Dimension is dependent on connector height used

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2.4 Supply Voltage Standard Power

• 5V DC ± 5%

The dynamic range shall not exceed the static range.

5.25V

5.05V

5V

4.95V

4.75V

Absolute Maximum

Dynamic Range

Nominal Static Range

Absolute Minimum

2.4.1 Electrical Characteristics

Characteristics

5V

5V_SB

Voltage

Ripple

Current

Voltage

Ripple

± 5%

± 5%

Min.

-

4.75

4.75

Typ.

-

5.00

5.00

Max.

5.25

± 50

5.25

± 50

Units

Vdc mV

PP

Vdc mV

PP

Comment

0-20MHz

2.4.2 Rise Time

The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

Note

For information about the input power sequencing of the Qseven

®

module refer to the Qseven

®

specification.

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2.5 Power Consumption

The power consumption values listed in this document were measured under a controlled environment. The hardware used for testing includes a conga-QA3 module, conga-QEVAL, SATA drive, USB keyboard and USB mouse. The SATA drive, USB Keyboard, USB mouse were powered separately so that they do not influence the power consumption value that is measured for the module.

To ensure that only the power consumption of the CPU module is measured, the conga-QEVAL power consumption was determined before the measurement and subtracted from the overall power consumption value measured.

All recorded values were averaged over a 30 second time period. Cooling of the module was done by the module specific heatspreader and a fan cooled heatsink to measure the power consumption under normal thermal conditions

Each module was measured while running Windows 7 Professional 64Bit, Hyper Threading enabled, Speed Step enabled and Power Plan set to “Power Saver”. This setting ensures that core processors run in LFM (lowest frequency mode) with minimal core voltage during desktop idle.

The conga-QA3/QA3E power consumption values are for worst case operating conditions. The values were recorded with the following setup:

Windows 7

• Desktop Idle (power plan = Power Saver)

• 100% CPU workload (see note below, power plan = Power Saver)

• 100% CPU workload at approximately 100°C peak power consumption (power plan = Balanced)

• Suspend to RAM. Supply power for S3 mode is 5V. Desktop Idle

Note

A software tool was used to stress the CPU to 100% workload.

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Processor Information

The tables below provide additional information about the power consumption data for each of the conga-QA3/QA3E variants offered. The values are recorded at various operating mode

2.5.1 conga-QA3 Intel

®

Atom™ E3845 Quad Core 1.91 GHz

With 2GB onboard memory and 4GB eMMC (10W Max. TDP) conga-QA3 Art. No. 015100

Memory Size

Operating System

Power State

Power consumption (Amperes/Watts)

Intel

®

Atom™ E3845 Quad Core 1.91 GHz 2MB L2 Cache (22nm)

Layout Rev. QA30LA1 /BIOS Rev. QA32R004

2GB

Windows 7 (64 bit)

Desktop Idle 100% CPU

Workload [W]

100% CPU & 100%

GPU Workload [W]

0.63 A / 3.16 W 1.45 A / 7.23 W 2.21 A / 11.03 W

Max. Power Consumption

(Worst Case)

2.38 A / 11.90 W

Suspend to Ram (S3)

5V SB Input

0.08 A / 0.39 W


®

Atom™ E3827 Dual Core 1.75 GHz


Memory Size

Operating System

Power State


Intel

®

Atom™ E3827 Dual Core 1.75 GHz 1MB L2 Cache (22nm)


2GB

Windows 7 (64 bit)


Workload [W]

100% CPU & 100%

GPU Workload [W]

0.78 A / 3.92 W 1.10 A / 5.48 W 1.92 A / 9.59 W


(Worst Case)

2.04 A / 10.20 W

Suspend to Ram (S3)

5V SB Input

0.07 A / 0.34 W

18/88


®



Memory Size

Operating System

Power State


Intel

®



2GB

Windows 7 (64 bit)


Workload [W]

100% CPU & 100%

GPU Workload [W]

0.73 A / 3.67 W 0.95 A / 4.73 W 1.59 A / 7.95 W


(Worst Case)

1.60 A / 8.00 W

Suspend to Ram

(S3) 5V SB Input

0.07 A / 0.36 W


®



Memory Size

Operating System

Power State


Intel

®



2GB

Windows 7 (64 bit)


Workload [W]

100% CPU & 100%

GPU Workload [W]

0.38 A / 1.91 W 0.61 A / 3.07 W 1.00 A / 5.01 W


(Worst Case)

1.06 A / 5.30 W


®

Atom™ E3815 Single Core 1.46 GHz


Memory Size

Operating System

Power State


Intel

®

Atom™ E3815 Single Core 1.46 GHz 512KB L2 Cache (22nm)


2GB

Windows 7 (64 bit)


Workload [W]

100% CPU & 100%

GPU Workload [W]

0.37 A / 1.85 W 0.54 A / 2.71 W 0.79 A / 3.95 W


(Worst Case)

0.88 A / 4.40 W

Suspend to Ram (S3)

5V SB Input

0.09 A / 0.43 W

Suspend to Ram (S3) 5V

SB Input

0.07 A / 0.34 W

19/88


®

Celeron

®

J1900 Quad Core 2.0/2.42 GHz

With onboard 2GB memory (10W Max. TDP) conga-QA3 Art. No. 015111

Memory Size

Burst Freq.

Operating System

Power State


Intel

®

Celeron

®

J1900 Quad Core 2.0/2.42 GHz 2MB L2 Cache (22nm)

Layout Rev. QA30LA2 /BIOS Rev. QC32R004

2GB

2.42 GHz

Windows 7 (64 bit)


Workload [W]

100% CPU & 100%

GPU Workload [W]

0.77 A / 3.85 W 2.02 A / 10.10 W 3.01 A / 15.07 W


(Worst Case)

3.22 A / 16.10 W

Suspend to Ram (S3)

5V SB Input

0.07 A / 0.36 W


®

Celeron

®

N2930 Quad Core 1.83/2.16 GHz

With 2GB onboard memory (7.5W Max. TDP) conga-QA3 Art. No. 015112

Memory Size

Burst Freq.

Operating System

Power State


Intel

®

Celeron

®

N2930 Quad Core 1.83/2.16 GHz 2MB L2 Cache (22nm)


2GB

2.16 GHz

Windows 7 (64 bit)


Workload [W]

100% CPU & 100%

GPU Workload [W]

0.63 A / 3.17 W 1.55 A / 7.77 W 1.96 A / 9.80 W


(Worst Case)

2.22 A / 11.10 W

Suspend to Ram (S3)

5V SB Input

0.62 A / 0.31 W


®

Celeron

®

N2807 Dual Core 1.58/2.16 GHz

With onboard 2GB memory (4.3W Max. TDP) conga-QA3 Art. No. 015113

Memory Size

Burst Freq.

Operating System

Power State


Intel ® Celeron ® N2807 Dual Core 1.58/2.16 GHz 2MB L2 Cache (22nm)


2GB

2.16 GHz

Windows 7 (64 bit)

Desktop Idle

TBD

100% CPU

Workload [W]

TBD

100% CPU & 100%

GPU Workload [W]

TBD


(Worst Case)

TBD

Suspend to Ram (S3)

5V SB Input

TBD

20/88

2.5.9 conga-QA3E Intel

®

Atom™ E3815 Single Core 1.46 GHz


Memory Size

Operating System

Power State


Intel

®

Atom™ E3815 Single Core 1.46 GHz 512KB L2 Cache (22nm)


2GB

Windows 7 (64 bit)

Desktop Idle

TBD

100% CPU

Workload [W]

TBD

100% CPU & 100%

GPU Workload [W]

TBD


(Worst Case)

TBD

Suspend to Ram (S3) 5V

SB Input

TBD

2.5.10 conga-QA3E Intel

®

Atom™ E3845 Quad Core 1.91 GHz


Memory Size

Operating System

Power State

Intel

®

Atom™ E3845 Quad Core 1.91 GHz 2MB L2 Cache (22nm)


2GB

Windows 7 (64 bit)

Desktop Idle

TBD

100% CPU

Workload [W]

TBD

100% CPU & 100%

GPU Workload [W]

TBD


(Worst Case)

TBD

Suspend to Ram (S3)

5V SB Input

TBD


Note

All recorded power consumption values are approximate and only valid for the controlled environment described earlier. 100% workload refers to the CPU workload and not the maximum workload of the complete module. Power consumption results will vary depending on the workload of other components such as graphics engine, memory, etc.

2.6 Supply Voltage Battery Power

• 2.5V-3.6V DC

• Typical 3V DC

21/88

2.6.1 CMOS Battery Power Consumption

RTC @ 20ºC

Integrated in the SoC

Voltage

3V DC

Current

1.23

µA

The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime. You should measure the

CMOS battery power consumption in your customer specific application in worst case conditions - for example, during high temperature and high battery voltage. The self-discharge of the battery must also be considered when determining CMOS battery lifetime. For more information about calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_Lifetime.pdf, which can be found at www.congatec.com.

2.7 Environmental Specifications

Temperature (commercial variants)

Temperature (industrial variants)

Humidity

Caution

Operation: 0° to 60°C

Operation: -40° to 85°C

Operation: 10% to 90%

Storage: -20° to +80°C

Storage: -45° to +85°C

Storage: 5% to 95%

The above operating temperatures must be strictly adhered to at all times. The congatec heatspreader is only suitable for use within commercial temperature ranges (0º to 60ºC) . It is not designed to be used within industrial temperature ranges (-40º to 85ºC). When using a heatspreader with conga-QA3/QA3E commercial grade variants, the maximum operating temperature refers to any measurable spot on the heatspreader’s surface.

congatec AG strongly recommends that you use the appropriate congatec heatspreader on the conga-QA3/QA3E and within operating temperatures of 0º to 60ºC. If you use heatspreaders that are not specified for the conga-QA3/QA3E or use the conga-QA3/QA3E industrial variants, then it is your responsibility to ensure that all components found on the module operate within the component manufacturer’s specified temperature range

Humidity specifications are for non-condensing conditions.

22/88

3 Block Diagram

Qseven 2.0

Connector

230 Edge Finger

LVDS/eDP

LVDS/eDP eDP Assembly Option eDP to LVDS

NXP PTN3460

DP/TMDS

PCIe Port 0

PCIe Port 1

PCIe Port 2

PCIe Port 3 X

Ethernet

USB 3.0 Port 0

1x SuperSpeed

USB 2.0 Port 0..2

3x USB 2.0

3x USB 2.0

USB 2.0 Port 3..5

SATA Port 0

SATA Port 1

HDA I/F

2x SATA 3G

SM Bus

SD/MMC

UART

SPI Bus

CAN Bus

LPC Bus

4 bit SD card

X

PCIe to GBE

Intel l210

USB Hub

SPI Flash

*2)

RES

Fan Control

I2C Bus

SLP_BTN

LID_BTN

TX/RX BC eDP

DDI0

Intel Bay Trail SoC

COMPUTE UNIT

PROCESSOR CORE

Tri-gate 3-D 22nm Quad core SoC

1MB L2 cache shared by 2 cores

Core #1

Core #3

SSE4.2

AES AVX

Core #2

Core #4

SoC TRANSACTION ROUTER

DISPLAY & GRAPHICS

Interfaces

DisplayPort HDMI/DVI VGA LVDS

MPEG-2

H.264

Multimedia Features

WMV9

DivX

SVC

WMV

SAMU

MVC

DirectX 11 OpenGL 3.0 OpenGLES 2.0

OpenCL 1.2

SATA

INTEGRATED I/O

Integrated I/O Interfaces

USB 2.0

USB 3.0

PCIe

HD Audio

LPC Bus

SPI

GPIOs

PCU

LPC congatec

Board Controller

Memory

Channel 0 conga-QA3

4 On-module DDR3L

(Up to 4GB)

Memory

Channel 0

4 On-module DDR3L

(Up to 4GB)

1333 MT/s, non-ECC

MIPI CSI

*1)

Feature

Connector eMMC 4.5

SSD conga-QA3E

8 On-module DDR3L

(Up to 8GB)

1 On-module DDR3L

(ECC module)

1333 MT/s, ECC

NOTE:

The conga-MA3 supports up to 4 GB single channel or up to 8 GB dual channel non-ECC DDR3L-1333 MT/s.

The conga-MA3E supports up to 8 GB single channel

ECC DDR3L-1333 MT/s

*1)

MIPI CSI is only supported on conga-QA3/QA3E

hardware revision B.x or newer.

*2)

Build-Time Option (not dynamically selectable)

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4 Heatspreader

An important factor for each system integration is the thermal design. The heatspreader acts as a thermal coupling device to the module and is thermally coupled to the CPU via a thermal gap filler. On some modules, it may also be thermally coupled to other heat generating components with the use of additional thermal gap fillers.

Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated, it is not to be considered as a heatsink. It has been designed as a thermal interface between the module and the application specific thermal solution. The application specific thermal solution may use heatsinks with fans, and/or heat pipes, which can be attached to the heatspreader. Some thermal solutions may also require that the heatspreader is attached directly to the systems chassis thereby using the whole chassis as a heat dissipater.

Caution

congatec Qseven

®

heaspreaders have been specifically designed for use within commercial temperature ranges (0° to 60°C) only. Therefore, do not use the conga-QA3/QA3E heatspreaders in industrial temperature ranges (-40° to 85°C). Its use is at the risk of the end user.

It is the responsibility of the end user to design an optimized thermal solution that meets the needs of their application within the industrial environmental conditions it is required to operate in. Attention must be given to the mounting solution used to mount the heatspreader and module to the system carrier board. Do not use a threaded heatspreader together with threaded carrier board standoffs. The combination of the two threads may be staggered, which could lead to stripping or cross-threading of the threads in either the standoffs of the heatspreader or carrier board.

For applications that require a vertically mounted heatspreader, use only the heatspreaders that feature fixing post , to secure the thermal stacks. If a heatspreader without fixing post is used in vertically mounted application, the thermal stacks may move.

Additionally, the gap pad material used on all heatspreaders contains silicon oil that can seep out over time depending on the environmental conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap pad material manufacturer’s specification.

24/88

4.1 Heatspreader Dimensions

M2.5x8mm threaded standoff for threaded version or

Ø2.7x8mm non-threaded standoff for bore hole version.

Ø2.7x8mm non-threaded standoff for threaded and bore hole versions.

Note

All measurements are in millimeters. Torque specification for heatspreader screws is 0.3 Nm. Mechanical system assembly mounting shall follow the valid DIN/IS0 specifications. The cooling strip found on the conga-QA3/QA3E is connected directly to the ground plane when mounted in the conga-QEVAL evaluation carrier board. For more information about connecting the conga-QA3/QA3E’s PCB cooling plate to the carrier board ground plane, refer to the Qseven Design Guide.

Caution

When using the heatspreader in a high shock and/or vibration environment, congatec recommends the use of a thread-locking fluid on the heatspreader screws to ensure the above mentioned torque specification is maintained.

25/88

5 Connector Subsystems

The conga-QA3/QA3E is based on the Qseven

®

standard. It therefore has 115 edge fingers on the top and bottom side of the module that mate with the 230-pin card-edge MXM connector located on the carrier board. This connector is able to interface the available signals of the conga-QA3/QA3E with the carrier board peripherals.

1x DisplayPort

1x HDMI

1x DVI

1x LVDS

(up to 2x 24 bpp)

3x PCI Express Lanes

Gigabit Ethernet

(Connected via a x1 PCI Express Lane)

1x USB 3.0

6x USB 2.0

2x Serial ATA

UART

High Definition Audio eMMC

(onboard)

SD/MMC

SM Bus

SPI Bus

LPC Bus

I²C Bus

Fan Control

Watchdog

Power Control

Power Management

MIPI-CSI 2.0

(feature connector onboard)

26/88

5.1

5.2

5.3

5.4

5.5

PCI Express™

The conga-QA3/QA3E offers 3 PCI Express externally on the Edge finger. The lanes are Gen 2 compliant and offer support for full 5 Gb/s bandwidth in each direction per x1 link. Default configuration for the lanes is 3 x1 link. A 1 x2 + 1 x1 link configuration is also possible but requires a special/customized BIOS firmware. Contact congatec technical support for more information about this subject.

The PCI Express interface is based on the PCI Express Specification 2.0 with Gen 1 (2.5Gb/s) and Gen 2 (5 Gb/s) speed. For more information refer to the PCI Express pinout table in section 8 “Signal Descriptions and Pinout Tables.”.

ExpressCard™

The conga-QA3/QA3E does not support ExpressCard.

Gigabit Ethernet

The conga-QA3/QA3E offers a Gigabit Ethernet interface on the edge finger via the onboard Intel controller is connected to the Intel

®

®

I210 Gigabit Ethernet controller. This

Bay Trail SoC through the fourth PCI Express lane. The Ethernet interface consists of 4 pairs of low voltage differential pair signals designated from GBE0_MD0± to GBE0_MD3± plus control signals for link activity indicators. These signals can be used to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board.

Serial ATA™ (SATA)

The conga-QA3/QA3E offers 2 SATA interfaces on the edge finger via a SATA host controller integrated in the Intel

®

Bay Trail SoC. The SATA host controller supports indepedent DMA operation and data transfer rates of 1.5 Gb/s and 3.0 Gb/s. It also supports two modes of operation

- a legacy mode and AHCI mode. Software that uses legacy mode will not have AHCI capabilities. For more information, refer to section 10

“BIOS Setup Description”.

USB 2.0

The conga-QA3/QA3E offers 6 USB 2.0 interfaces on the Edge finger. These interfaces are provided by routing three of the four ports provided by the Bay Trail SoC directly to the edge finger. The fourth port provided by the SoC is routed to the edge finger via a USB hub, thereby providing additional three ports.

The EHCI host controller in the SoC supports these interfaces with high-speed, full-speed and low-speed USB signalling. The controller complies with USB standard 1.1 and 2.0.

27/88

5.6

Note

The USB overcurrent protection is disabled by default on USB ports 0 and 1 (native ports). To enable this function, you require a customized

BIOS. Contact congatec technical support department for more information.

USB 3.0

The conga-QA3/QA3E offers one USB 3.0 interface on the Edge finger. This interface is controlled by an xHCI host controller in the SoC. The host controller allows data transfers of up to 5 Gb/s and supports SuperSpeed, high-speed, full-speed and low-speed USB signalling. The USB

SuperSpeed signals should be paired with USB 2.0 port 0 on the carrier board. See section 7.3 for more information about xHCI and EHCI port mapping.

5.7

5.8

5.9

SD Card

The conga-QA3/QA3E offers a 4-bit SD interface for SD/MMC cards on the Edge finger. The SD card controller in the Storage Control Cluster of the SoC supports the SD interface with up to 832 Mb/s data rate using 4 parallel data lines.

Note

The conga-QA3/QA3E celeron variants do not offer SD card Interface.

UART

The conga-QA3/QA3E offers a UART interface on the edge connector. The UART signals are routed from the onboard SoC. For more information, see table 6 “UART Signal Description“

High Definition Audio (HDA)

The conga-QA3/QA3E provides an interface that supports the connection of HDA audio codecs.

5.10 Digital Display Interface

The Bay Trail SoC provides two DDI ports to enable eDP 1.3, DP 1.1a, DVI or HDMI 1.4a. One of the ports (DDI0) is routed directly to the edge finger for the support of eDP/DP/HDMI/DVI. The other port (DDI1) is routed to the edge finger via an eDP to LVDS bridge. This port supports

28/88

only LVDS by default. An optional eDP support on this port is possible but only as an assembly option

The SoC on the conga-QA3/QA3E supports High-bandwidth Digital Content Protection 1.4/2.1 (HDCP) for content protection over wired displays (HDMI, DisplayPort and Embedded DisplayPort). It also supports audio on DP and HDMI.

The conga-QA3/QA3E supports up to two independent displays. The display combination must be 1 DDI and 1 LVDS as shown in the table below:

Table 2 Display Combination

Display 1

(DDI 0)

HDMI

DP

DVI

Display 2

(DDI 1)

LVDS

LVDS

LVDS

Display 1

Max. Resolution

1920x1200 @60Hz

2560x1600 @60Hz

1920x1200 @60Hz

Display 2

Max. Resolution

1920x1200 @60Hz (dual LVDS mode)



5.10.1 LVDS/eDP

The conga-QA3/QA3E offers a single/dual channel LVDS/eDP interface on the edge finger. The interface is provided by routing the onboard

PTN3460 eDP to LVDS bridge to the DDI port 1 of the Bay Trail SoC. The bridge processes incoming DisplayPort stream, converts the DP protocol to LVDS protocol and transmits the processed stream in LVDS format.

The LVDS/eDP interface supports single and dual channel signalling with color depths of 18 bits or 24 bits per pixel and pixel clock frequency up to 112 MHz. It also supports automatic panel detection via Embedded Panel Interface based on VESA EDID™ 1.3, with resolution up to

1920x1200 in dual LVDS bus mode. The interface is designed to provide only LVDS signals. However, an assembly option exists for the support of eDP signals. For more information, contact congatec technical support.

5.10.2 DisplayPort

DisplayPort is an open, industry standard digital display interface, that has been developed within the Video Electronics Standards Association

(VESA). The DisplayPort specification defines a scalable digital display interface with optional audio and content protection capability. It defines a license-free, royalty-free, state-of-the-art digital audio/video interconnect, intended to be used primarily between a computer and its display monitor.

The DisplayPort interface is provided by DDI0 of the Bay Trail SoC and is shared with HDMI/DVI. The supported resolution is up to 2560x1600@60Hz.

Note

The conga-QA3/QA3E supports one DisplayPort display. See table 2 above for possible display combinations.

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5.10.3 HDMI

High-Definition Multimedia Interface (HDMI) is a licensable compact audio/video connector interface for transmitting uncompressed digital streams. HDMI encodes the video data into TMDS for digital transmission and is backward-compatible with the single-link Digital Visual

Interface (DVI) carrying digital video.

The HDMI is provided by DDI0 of the Bay Trail SoC and is shared with DisplayPort/DVI. The supported resolution is up to 1920x1200@60Hz.

Note

The conga-QA3/QA3E supports one HDMI display. See table 2 above for possible display combinations.

5.10.4 DVI

The DVI is similar to HDMI in the way it uses TMDS for transmitting data from transmitter to the receiver but unlike the HDMI, does not support audio and CEC.

Note

The conga-QA3/QA3E supports one DVI display. See table 2 above for possible display combinations.

5.11 LPC

The conga-QA3/QA3E offers the LPC (Low Pin Count) bus. The LPC bus corresponds approximately to a serialized ISA bus yet with a significantly reduced number of signals and functionality. Due to the software compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application specific carrier board using this bus. Only certain devices such as Super I/O or TPM 1.2 chips can be implemented on the carrier board.

Note

The conga-QA3/QA3E Atom variants operate at a frequency of 33 MHz while the Celeron variants at 25 MHz.

5.12 SPI

The conga-QA3/QA3E offers the SPI interface only for booting a BIOS from an SPI Flash device placed on the carrier board.

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5.13 I²C Bus

The conga-QA3/QA3E supports I2C bus. Thanks to the I2C host controller in the cBC, the I²C bus is multi-master capable and runs at fast mode.

5.14 CAN Bus

The conga-QA3/QA3E does not support CAN bus.

5.15 Power Control

The conga-QA3/QA3E supports ATX-style power supplies control. In order to do this the power supply must provide a constant source of VCC_5V_SB power. The AT-style power supply (5V only) is also supported. In this case, the conga-QA3’s pin PWRBTN# should be left unconnected, pin SUS_S3# should control the main power regulators on the carrier board (+3.3V...) and pins VCC_5V_SB should be connected to the 5V input power rail according to the Qseven specification.

PWGIN

PWGIN (pin 26) can be connected to an external power good circuit. This input is optional and should be left unconnected when not used.

Through the use of an internal monitor on the +5V input voltage and/or the internal power supplies, the conga-QA3/QA3E module is capable of generating its own power-on good.

SUS_S3#

The SUS_S3# (pin 18) signal is an active-low output that can be used to control the main 5V rail of the power supply for module and all other main power supplies on carrier board. In order to accomplish this, the signal must be inverted with an inverter/transistor that is supplied by standby voltage (ATX-style) or system input voltage (AT-style) and is located on the carrier board.

PWRBTN#

When using ATX-style power supplies PWRBTN# (pin 20) is used to connect to a momentary-contact, active-low debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to 3.3V_SB using a 10k resistor.

When PWRBTN# is asserted, it indicates that an operator wants to turn the power on or off. The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software.

Note

To initiate an ACPI event, the Bay Trail SoC expects a rising edge on the PWRBTN# signal.

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Power Supply Implementation Guidelines

5 volt input power is the sole operational power source for the conga-QA3/QA3E. The remaining necessary voltages are internally generated on the module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing a power supply for a conga-QA3/QA3E application:

• It has also been noticed that on some occasions, problems occur when using a 5V power supply that produces non monotonic voltage when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. This should be done during the power supply qualification phase therefore ensuring that the above mentioned problem doesn’t arise in the application. For more information about this issue visit www.formfactors.org and view page 25 figure 7 of the document “ATX12V Power Supply Design Guide V2.2”.

Inrush and Maximum Current Peaks on VCC_5V_SB and VCC

The inrush-current on the conga-QA3/QA3E VCC_5V_SB power rail (8ms soft-start) can go up as high as 0.4A for a maximum of 100µs. Sufficient decoupling capacitance must be implemented to ensure proper power-up sequencing.

The maximum peak-current on the conga-QA3/QA3E VCC (5V) power rail can be as high as 3.0A. This requires that the power supply be properly dimensioned.

Note

For more information about power control event signals refer to the Qseven

®

specification.

5.16 Power Management

ACPI 5.0 compliant with battery support. Also supports Suspend to RAM (S3). No support for legacy APM.

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6 Additional Features

6.1 Onboard Interfaces

6.1.1 MIPI-CSI 2.0

The conga-QA3/QA3E revision B.x and later offer an onboard camera interface via the feature connector. The interface supports up to two independent cameras - four data lanes for the first camera and one data lane for the second camera. Each lane operates at up to 1 GT/s depending on the camera resolution. It also supports up to 24 MP image capture @ 15fps, full HD 1080p60.

The MIPI-CSI-2 interfaces follow the CSI-2 specification as defined by the MIPI Alliance and support YUV420, YUV422, RGB444, RGB555,

RGB565, RGB888, JPEG and RAW 8/10/12/14. The MIPI interface is also compliant with the SGET Camera Feature Specification.

For the signal descriptions, see table 25 “Onboard Camera Interface Signal Descriptions“.

Note

The conga-QA3/QA3E celeron variants do not support MIPI-CSI 2.0.

6.1.2 eMMC 4.5

The conga-QA3/QA3E offers an optional eMMC 4.5 flash onboard the Intel Atom variants, with up to 32 GB capacity. The conga-QA3/QA3E celeron variants do not offer eMMC.

6.2 congatec Board Controller (cBC)

The conga-QA3/QA3E is equipped with a Texas Instruments Tiva™ TM4E1231H6ZRBI microcontroller. This onboard microcontroller plays an important role for most of the congatec BIOS features. It fully isolates some of the embedded features such as system monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power mode.

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6.2.1 Board Information

The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and firmware revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

6.2.2 Fan Control

The conga-QA3/QA3E has additional signals and functions to further improve system management. One of these signals is an output signal called FAN_PWMOUT that allows system fan control using a PWM (Pulse Width Modulation) output. Additionally, there is an input signal called

FAN_TACHOIN that provides the ability to monitor the system’s fan RPMs (revolutions per minute). This signal must receive two pulses per revolution in order to produce an accurate reading. For this reason, a two pulse per revolution fan or similar hardware solution is recommended.

6.2.3 Power Loss Control

The cBC has full control of the power-up of the module and therefore can be used to specify the behavior of the system after an AC power loss condition. Supported modes are “Always On”, “Remain Off” and “Last State”.

6.2.4 Watchdog

The conga-QA3/QA3E is equipped with a multi stage watchdog solution that can be triggered by software of external hardware. For more information about the watchdog feature, see the BIOS setup description in section 10.4.1 of this document and the application note

AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.

6.3 Embedded BIOS

The conga-QA3/QA3E is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI firmware. These are the most important embedded PC features:

6.3.1 CMOS Backup in Non Volatile Memory

A copy of the CMOS memory (SRAM) is stored in the BIOS flash device. This prevents the system from booting up with incorrect system configuration if the backup battery (RTC battery) fails. Additionally, it provides the ability to create systems that do not require a CMOS backup battery.

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6.3.2 OEM CMOS Default Settings and OEM BIOS Logo

This feature allows system designers to create and store their own CMOS default configuration and BIOS logo (splash screen) within the BIOS flash device. Customized BIOS development by congatec for these changes is no longer necessary because customers can easily do these changes by themselves using the congatec system utility CGUTIL.

6.3.3 OEM BIOS Code

With the congatec embedded BIOS it is even possible for system designers to add their own code to the BIOS POST process. Except for custom specific code, this feature can also be used to support Window 7 SLIC table, verb tables for HDA codecs, rare graphic modes and

Super I/O controllers.

For more information about customizing the congatec embedded BIOS, refer to the congatec system utility user’s guide (CGUTLm1x.pdf) and can be found on the congatec AG website at www.congatec.com or contact congatec technical support.

6.3.4 congatec Battery Management Interface

In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec AG defined an interface for the exchange of data between a CPU module (using an ACPI operating system) and a smart battery system. A system developed according to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI-capable operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...) without the need for additional modifications to the system BIOS.

The conga-QA3/QA3E BIOS fully supports this interface. For more information about this subject, visit the congatec website and view the following documents:

• congatec Battery Management Interface Specification

• Battery System Design Guide

• conga-SBM

3

User’s Guide

6.3.5 API Support (CGOS/EAPI)

In order to benefit from the above mentioned non-industry standard feature set, congatec provides an API that allows application software developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux and QNX.

The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules.

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6.4

6.5

All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software developers guide, which is available on the congatec website .

Other COM (Computer on Modules) vendors offer similar driver solutions for these kind of embedded PC features, which are by nature proprietary. All the API solutions that can be found on the market are not compatible to each other. As a result, writing application software that can run on more than one vendor’s COM is not so easy. Customers have to change their application software when switching to another

COM vendor.

EAPI (Embedded Application Programming Interface) is a programming interface defined by the PICMG that addresses this problem. With this unified API it is now possible to run the same application on all vendor’s COMs that offer EAPI driver support. Contact congatec technical support for more information about EAPI.

Suspend to RAM

The conga-QA3/QA3E supports Suspend to RAM.

ECC Memory Support

Error-Correcting Code (ECC) memory is a memory system that tests for and corrects errors automatically, very often without the operating system being aware of it, let alone the user. As data are written into memory, ECC circuitry generates checksums from the binary sequences in the bytes and stores them in an additional seven bits of memory for 32-bit data paths or eight bits for 64-bit paths. When data are retrieved from memory, the checksum is recomputed to determine if any of the data bits have been corrupted.

Note

The conga-QA3 does not support ECC memory. Only the conga-QA3E supports ECC memory. The ECC memory can detect and correct single bit errors. It can detect but not correct double bit errors.

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7 conga Tech Notes

The conga-QA3/QA3E has some technological features that require additional explanation. The following section will give the reader a better understanding of some of these features. This information will also help to gain a better understanding of the information found in the system resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.

7.1 Intel Bay Trail SoC Features

7.1.1 Processor Core

The Intel Bay Trail Soc features Single, Dual or Quad Out-of-Order Execution processor cores. The cores are sub-divided into dual-core modules with each module sharing a 1 MB L2 cache (512 KB per core). Some of the features supported by the core are:

• Intel 64 architecture

• Intel Streaming SIMD Extensions 4.1 and 4.2

• Support for Intel VT-x

• Thermal management support vial Intel Thermal Monitor

• Uses Power Aware Interrupt Routing

• Uses 22 nm process technology

Note

Intel Hyper-Threading technology is not supported (four cores execute four threads)

7.1.1.1 Intel Virtualization Technology

Intel

Intel

®

®

Virtualization Technology (Intel

®

VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel of platforms based on Intel architecture microprocessors and chipsets. Intel

®

®

VT comprises technology components to support virtualization

Virtualization Technology for IA-32, Intel

VT-x) added hardware support in the processor to improve the virtualization performance and robustness.

®

64 and Intel

®

Architecture

Note

congatec does not offer virtual machine monitor (VMM) software. All VMM software support questions and queries should be directed to the

VMM software vendor and not congatec technical support.

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7.1.1.2 AHCI

The Intel Bay Trail SoC provides hardware support for Advanced Host Controller Interface (AHCI), a programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices

(each device is treated as a master) and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-

Plug.

7.1.1.3 IDE Mode (Native Vs. Legacy)

Legacy Mode

When operating in legacy mode, the SATA controllers need two legacy IRQs (14 and 15) and are unable to share these IRQs with other devices.

This is because the SATA controllers emulate the primary and secondary legacy IDE controllers.

Native Mode

Native mode allows the SATA controllers to operate as true PCI devices and therefore do not need dedicated legacy resources. This means they can be configured anywhere within the system. When either SATA controller 1 or 2 runs in native mode it only requires one PCI interrupt for both channels and also has the ability to share this interrupt with other devices in the system. Setting “IDE Mode” in the BIOS setup program will automatically enable Native mode. See section 10.4.12 for more information about this. Running in native mode frees up interrupt resources (IRQs 14 and 15) and decreases the chance that there may be a shortage of interrupts when installing devices.

Note

If your operating system supports native mode then congatec AG recommends you enable it.

7.1.1.4 Thermal Management

ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands put on the CPU by the application.

The conga-QA3/QA3E ACPI thermal solution currently offers two different cooling policies.

• Passive Cooling

When the temperature in the thermal zone must be reduced, the operating system can decrease the power consumption of the processor by throttling the processor clock. One of the advantages of this cooling policy is that passive cooling devices (in this case the processor) do not produce any noise. Use the “passive cooling trip point” setup node in the BIOS setup program to determine the temperature threshold that

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7.2

the operating system will use to start or stop the passive cooling procedure.

• Critical Trip Point

If the temperature in the thermal zone reaches a critical point then the operating system will perform a system shut down in an orderly fashion in order to ensure that there is no damage done to the system as result of high temperatures. Use the “critical trip point” setup node in the

BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system.

Note

The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the appropriate trip points.

If passive cooling is activated and the processor temperature is above the trip point the processor clock is throttled. See section 12 of the

ACPI Specification 2.0 C for more information about passive cooling.

ACPI Suspend Modes and Resume Events

conga-QA3/QA3E supports S3 (STR= Suspend to RAM). For more information about S3 wake events see section 10.4.6 “ACPI Configuration

Submenu”.

S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by the following operating systems (S4_OS= Hibernate):

• Windows 7, Windows Vista, Windows XP and Linux

This table lists the “Wake Events” that resume the system from S3 unless otherwise stated in the “Conditions/Remarks” column:

Wake Event

Power Button

Onboard LAN Event

Conditions/Remarks

Wakes unconditionally from S3-S5.

Device driver must be configured for Wake On LAN support.

PCI Express WAKE#

PME#

USB Mouse/Keyboard Event

RTC Alarm

Wakes unconditionally from S3-S5.

Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On

PME# to Enabled in the Power setup menu.

When Standby mode is set to S3, USB Hardware must be powered by standby power source.

Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program).

In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer out of standby’.

Activate and configure Resume On RTC Alarm in the Power setup menu. Only available in S5.

Watchdog Power Button Event Wakes unconditionally from S3-S5.

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7.3 xHCI and EHCI Port Mapping

P4 P3

0 1

0 1

USB 1.x/2.0

Port 3

USB 1.x/2.0

Port 2

EHCI

P2

0 1

USB 1.x/2.0

Port 1

Bay Trail SoC

P1 P1-4 SSP1

xHCI

P5

0 1

USB 1.x/2.0

Port 0

USB 3.0

SS

P6

USB 2.0

HSIC 0

X

USB 2.0

HSIC 1

X

USB 2.0 HUB

Qseven connector

USB 2.0

Port1

USB 2.0

Port2

USB 2.0

Port3

USB 2.0

Port4

USB 2.0

Port5

USB 2.0

Port0

+

SuperSpeed

Port 0

USB 3.0 Port

5 x USB 2.0

(USB_P0± to USB_P5±)

1 x USB 3.0

(USB_P0±,

USB_SSRX0±,

USB_SSTX0±)

NOTE:

Possible USB configurations are:

(*) Up to 6x USB 2.0

(*) Up to 5x USB 2.0 and 1x USB 3.0

Note



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8 Signal Descriptions and Pinout Tables

The following section describes the signals found on Qseven

®

module’s edge fingers.

Table 2 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a pull-up or pull-down resistor has been used, if the field entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When

“#” is not present, the signal is asserted when at a high voltage level.

Note

Not all the signals described in this section are available on all conga-QA3/QA3E variants. Use the article number of the module and refer to the options table in section 1 to determine the options available on the module.

Table 3 Signal Tables Terminology Descriptions

I

Term

O

OC

OD

PP

I/O

P

NA

NC

PCIE

GB_LAN

USB

SATA

SPI

LVDS

TMDS

CMOS

Description

Input Pin

Output Pin

Open Collector

Open Drain

Push Pull

Bi-directional Input/Output Pin

Power Input

Not applicable

Not Connected

PCI Express differential pair signals. In compliance with the PCI Express Base Specification 2.0

Gigabit Ethernet Media Dependent Interface differential pair signals. In compliance with IEEE 802.3ab 1000Base-T Gigabit Ethernet Specification.

Universal Serial Bus differential pair signals. In compliance with the Universal Serial Bus Specification 2.0

Serial Advanced Technology Attachment differential pair signals. In compliance with the Serial ATA High Speed Serialized AT Attachment Specification 2.6.

Serial Peripheral Interface bus is a synchronous serial data link that operates in full duplex mode.

Low-Voltage Differential Signaling differential pair signals. In compliance with the LVDS Owner's Manual 4.0.

Transition Minimized Differential Signaling differential pair signals. In compliance with the Digital Visual Interface (DVI) Specification 1.0.

Logic input or output.

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Table 4 Edge Finger Pinout

Pin Signal

1 GND

3 GBE_MDI3-

5

7

GBE_MDI3+

GBE_LINK100#

9 GBE_MDI1-

11 GBE_MDI1+

13 GBE_LINK#

15 GBE_CTREF

17 WAKE#

19 SUS_STAT#

21 SLP_BTN#

23 GND

25 GND

27 BATLOW#

29 SATA0_TX+

31 SATA0_TX-

33 SATA_ACT#

35 SATA0_RX+

37 SATA0_RX-

39 GND

41 BIOS_DISABLE#

/BOOT_ALT#

43 SDIO_CD#

45 SDIO_CMD

47 SDIO_PWR#

49 SDIO_DAT0

51 SDIO_DAT2

53 SDIO_DAT4 (*)

55 SDIO_DAT6 (*)

57 GND

59 HDA_SYNC (**)

/ I2S_WS

61 HDA_RST#

/ I2S_RST#

63 HDA_BITCLK (**)

/ I2S_CLK

65 HDA_SDI (**)

/ I2S_SDI

Description

Power Ground

Gigabit Ethernet MDI3-

Gigabit Ethernet MDI3+

100 Mbps link speed



Gigabit Ethernet Link indicator

Reference voltage for GBE

External system wake event

Suspend status

Sleep button

Power Ground

Power Ground

Battery low input

Serial ATA Channel 0 TX+

Serial ATA Channel 0 TX-

Serial ATA Activity

Serial ATA Channel 0 RX+

Serial ATA Channel 0 RX-

Power Ground

BIOS Module disable

Boot Alternative Enable

SDIO Card Detect

SDIO Command/Response

SDIO Power Enable

SDIO Data Line 0

SDIO Data Line 2

SDIO Data Line 4

SDIO Data Line 6

Power Ground

HD Audio/AC’97 Synchronization.

Multiplexed with I2S Word Select from Codec

HD Audio/AC’97 Codec Reset. Multiplexed with I2S Codec Reset

HD Audio/AC’97 Serial Bit Clock. Multiplexed with I2S Serial Data Clock from Codec.

HD Audio/AC’97 Serial Data In. Multiplexed with I2S Serial Data Input from Codec

Pin Signal

2 GND

4 GBE_MDI2-

6

8

GBE_MDI2+

GBE_LINK1000#

10 GBE_MDI0-

12 GBE_MDI0+

14 GBE_ACT#

16 SUS_S5#

18 SUS_S3#

20 PWRBTN#

22 LID_BTN#

24 GND

26 PWGIN

28 RSTBTN#

30 SATA1_TX+

32 SATA1_TX-

34 GND

36 SATA1_RX+

38 SATA1_RX-

40 GND

42 SDIO_CLK

44 SDIO_LED

46 SDIO_WP

48 SDIO_DAT1

50 SDIO_DAT3

52 SDIO_DAT5 (*)

54 SDIO_DAT7 (*)

56 USB_DRIVE_VBUS (*)

58 GND

60 SMB_CLK

/ GP1_I2C_CLK

62 SMB_DAT

/ GP1_I2C_DAT

64 SMB_ALERT#

66 GP0_I2C_CLK

Description

Power Ground



1000 Mbps link speed



Gigabit Ethernet Activity indicator

S5 (Soft OFF) – shutdown state

S3 (Suspend to RAM) – SLP

Power button

LID button

Power Ground

Power good input

Reset button input

Serial ATA Channel 1 TX+

Serial ATA Channel 1 TX-

Power Ground

Serial ATA Channel 1 RX+

Serial ATA Channel 1 RX-

Power Ground

SDIO Clock Output

SDIO LED

SDIO Write Protect

SDIO Data Line 1

SDIO Data Line 3

SDIO Data Line 5

SDIO Data Line 7

USB power enable pin for USB Port 1

Power Ground

SMBus Clock line. Multiplexed with General

Purpose I²C bus #1 clock line

SMBus Data line. Multiplexed with General

Purpose I²C bus #1 data line.

SMBus Alert input

General Purpose I2C Bus No 0 clock line

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Pin Signal

67 HDA_SDO (**)

/ I2S_SDO

69 THRM#

71 THRMTRIP#

73 GND

75 USB_P7-

/ USB_SSTX0-

77 USB_P7+

/ USB_SSTX0+

79 USB_6_7_OC# (*)

81 USB_P5-

/ USB_SSTX1-

83 USB_P5+

/ USB_SSTX1+

85 USB_2_3_OC#

87 USB_P3-

89 USB_P3+

91 USB_VBUS (*)

93 USB_P1-

95 USB_P1+

97 GND

99 eDP0_TX0+

/ LVDS_A0+

101 eDP0_TX0-

/ LVDS_A0-

103 eDP0_TX1+

/ LVDS_A1+

105 eDP0_TX1-

/ LVDS_A1-

107 eDP0_TX2+

/ LVDS_A2+

109 eDP0_TX2-

/ LVDS_A2-

111 LVDS_PPEN

113 eDP0_TX3+

/ LVDS_A3+

115 eDP0_TX3-

/ LVDS_A3-

117 GND

119 eDP0_AUX+

/ LVDS_A_CLK+

Description

HD Audio/AC’97 Serial Data Out. Multiplexed with I2S Serial Data Output from Codec

Thermal Alarm active low

Thermal Trip indicates an overheating condition

Power Ground

USB Port 7 Differential Pair- . Multiplexed with

Superspeed USB transmit differential pair-

USB Port 7 Differential Pair+. Multiplexed with

Superspeed USB transmit differential pair+

Over current detect input 6/7 USB

USB Port 5 Differential Pair-

USB Port 5 Differential Pair+




USB VBUS pin



Power Ground eDP Primary Channel 0+

LVDS Primary channel 0+ eDP Primary channel 0-

LVDS Primary channel 0eDP Primary channel 1+


LVDS Primary channel 1- eDP Primary channel 2+


LVDS Primary channel 2-

LVDS Power enable eDP Primary channel 3+


LVDS Primary channel 3-

Power Ground eDP Primary Auxilliary channel+

LVDS Primary channel CLK+

Pin Signal

68 GP0_I2C_DAT

70 WDTRIG#

72 WDOUT

74 GND

76 USB_P6-

/ USB_SSRX0-

78 USB_P6+

/ USB_SSRX0+

80 USB_4_5_OC#

82 USB_P4-

/ USB_SSRX1-

84 USB_P4+

/ USB_SSRX1+

86 USB_0_1_OC#

88 USB_P2-

90 USB_P2+

92 USB_ID (*)

94 USB_P0-

96 USB_P0+

98 GND

100 eDP1_TX0+

/ LVDS_B0+

102 eDP1_TX0-

/ LVDS_B0-

104 eDP1_TX1+

/ LVDS_B1+

106 eDP1_TX1-

/ LVDS_B1-

108 eDP1_TX2+

/ LVDS_B2+

110 eDP1_TX2-

/ LVDS_B2-

112 LVDS_BLEN

114 eDP1_TX3+

/ LVDS_B3+

116 eDP1_TX3-

/ LVDS_B3-

118 GND

120 eDP1_AUX+

/ LVDS_B_CLK+

Description

General Purpose I2C Bus No 0 data line

Watchdog trigger signal

Watchdog event indicator

Power Ground

USB Port 6 Differential Pair-. Multiplexed with

Superspeed USB transmit differential pair-

USB Port 6 Differential Pair+. Multiplexed with

Superspeed USB transmit differential pair+







USB ID pin



Power Ground eDP Secondary channel 0+

LVDS Secondary channel 0+ eDP Secondary channel 0-

LVDS Secondary channel 0- eDP Secondary channel 1+


LVDS Secondary channel 1- eDP Secondary channel 2+


LVDS Secondary channel 2-

LVDS Backlight enable eDP Secondary channel 3+


LVDS Secondary channel 3-

Power Ground eDP Secondary Auxiliary channel CLK+

LVDS Secondary channel CLK+

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Pin Signal

121 eDP0_AUX-

/ LVDS_A_CLK-

Description eDP Primary Auxilliary channel-

LVDS Primary channel CLK-

123 LVDS_BLT_CTRL

/ GP_PWM_OUT0

125 LVDS_DID_DAT

/ GP_I2C_DAT

127 LVDS_DID_CLK

/ GP_I2C_CLK

129 CAN0_TX (*)

131 DP_LANE3+

/ TMDS_CLK+

PWM Backlight brightness

General Purpose PWM Output

DDC Display ID Data line

General Purpose I2C Data line

DDC Display ID Clock line

General Purpose I2C Clock line

CAN TX Output for CAN Bus Channel 0

DisplayPort differential pair line lane 3.

Multiplexed with TMDS differential pair clock+

133 DP_LANE3-

/ TMDS_CLK-

135 GND

137 DP_LANE1+

/ TMDS_LANE1+

DisplayPort differential pair line lane 3.

Multiplexed with TMDS differential pair clock-

Power Ground

DisplayPort differential pair line lane 1

Multiplexed with TMDS differential pair lane1

139 DP_LANE1-

/ TMDS_LANE1-

141 GND

DisplayPort differential pair line lane 1


Power Ground

143 DP_LANE2+ / TMDS_LANE0+ DisplayPort differential pair line lane 2

145 DP_LANE2- / TMDS_LANE0DisplayPort differential pair line lane 2

147 GND Power Ground

149 DP_LANE0+ / TMDS_LANE2+ DisplayPort differential pair line lane 0


151 DP_LANE0- / TMDS_LANE2DisplayPort differential pair line lane 0


153 DP_HDMI_HPD# Hot plug detection for HDMI

155 PCIE_CLK_REF+

157 PCIE_CLK_REF-

159 GND

161 PCIE3_TX+ (*)

163 PCIE3_TX- (*)

165 GND

167 PCIE2_TX+

169 PCIE2_TX-

171 UART0_TX (**)

173 PCIE1_TX+

175 PCIE1_TX-

177 UART0_RX (**)

179 PCIE0_TX+

181 PCIE0_TX-

PCI Express Reference Clock+

PCI Express Reference Clock-

Power Ground

PCI Express Channel 3 Output+

PCI Express Channel 3 Output-

Power Ground



Serial Data Transmitter



Serial Data Receiver



Pin Signal

122 eDP1_AUX-

/ LVDS_B_CLK-

124 GP_1-Wire_Bus (*)

Description eDP Secondary Auxiliary channel CLK-

LVDS Secondary channel CLK-

General Purpose 1-wire bus interface

126 eDP0_HPD# / LVDS_BLC_DAT (*) SSC clock chip data line. Can be used as eDP primary hotplug detect

128 eDP1_HPD# / LVDS_BLC_CLK (*) SSC clock chip clock line. Can be used as eDP secondary hotplug detect

130 CAN0_RX (*)

132 RSVD (Differential)

CAN RX Input for CAN Bus Channel 0

Reserved

134 RSVD (Differential)

136 GND

138 DP_AUX+

140 DP_AUX-

142 GND

144 RSVD (Differential Pair)

146 RSVD (Differential Pair)

148 GND

150 HDMI_CTRL_DAT

152 HDMI_CTRL_CLK

154 DP_HPD#

156 PCIE_WAKE# (**)

158 PCIE_RST#

160 GND

162 PCIE3_RX+ (*)

164 PCIE3_RX- (*)

166 GND

168 PCIE2_RX+

170 PCIE2_RX-

172 UART0_RTS# (**)

174 PCIE1_RX+

176 PCIE1_RX-

178 UART0_CTS# (**)

180 PCIE0_RX+

182 PCIE0_RX-

Reserved

Power Ground

DisplayPort auxiliary channel

DisplayPort auxiliary channel

Power Ground

Reserved

Reserved

Power Ground

DDC based control signal (data) for HDMI/DVI device.

DDC based control signal (clock) for HDMI/DVI device.

Hot plug detection for DP

PCI Express Wake event

Reset Signal for external devices

Power Ground

PCI Express Channel 3 Input+

PCI Express Channel 3 Input-

Power Ground



Handshake signal, ready to receive data



Handshake signal, ready to send data



44/88

Pin Signal

183 GND

185 LPC_AD0

187 LPC_AD2

189 LPC_CLK

191 SERIRQ (**)

193 VCC_RTC

195 FAN_TACHOIN

197 GND

199 SPI_MOSI (**)

201 SPI_MISO (**)

203 SPI_SCK (**)

205 VCC_5V_SB

207 MFG_NC0

209 MFG_NC1

211 VCC

213 VCC

215 VCC

217 VCC

219 VCC

221 VCC

223 VCC

225 VCC

227 VCC

229 VCC

Note

Description

Power Ground

LPC Interface Address Data 0


LPC Interface Clock

Serialized interrupt

3V backup cell input

Fan tachometer input

General Purpose Timer In

Power Ground

SPI Master serial output/Slave serial input

SPI Master serial input/Slave serial output signal

SPI Clock Output

+5VDC,Standby ±5%

Do not connect on carrier board


Power supply +5VDC ±5%










Pin Signal

184 GND

186 LPC_AD1

188 LPC_AD3

190 LPC_FRAME#

192 LPC_LDRQ# (*)

194 SPKR

/GP_PWM_OUT2

196 FAN_PWMOUT

198 GND

200 SPI_CS0# (**)

202 SPI_CS1# (*)

204 MFG_NC4

206 VCC_5V_SB

208 MFG_NC2

210 MFG_NC3

212 VCC

214 VCC

216 VCC

218 VCC

220 VCC

222 VCC

224 VCC

226 VCC

228 VCC

230 VCC

Description

Power Ground



LPC frame indicator

LPC DMA request

Output for audio enunciator


Fan speed control (PWM)


Power Ground

SPI Chip Select 0 Output

SPI Chip Select 1 Output


+5VDC Standby ±5%













The signals marked with asterisk symbol (*) are not supported on the conga-QA3/QA3E.

On Intel Bay Trail SoC, the signals marked with asterisks (**) have voltage levels that are different from the levels defined in the Qseven

Specification. To comply with the Qseven Specification, the signals are routed through bidirectional level shifters on the module.

The bidirectional level shifters by nature have limited driving strenght. congatec therefore recommends that you route these signals as short as possible.

45/88

Table 5 PCI Express Signal Descriptions

Signal

PCIE0_RX+

PCIE0_RX-

PCIE0_TX+

PCIE0_TX-

PCIE1_RX+

PCIE1_RX-

PCIE1_TX+

PCIE1_TX-

PCIE2_RX+

PCIE2_RX-

PCIE2_TX+

PCIE2_TX-

PCIE3_RX+

PCIE3_RX-

PCIE3_TX+

PCIE3_TX-

PCIE_CLK_REF+

PCIE_CLK_REF-

155

157

PCIE_WAKE# (**) 156

173

175

168

170

167

169

162

164

161

163

PCIE_RST#

Pin # Description

180

182

PCI Express channel 0, Receive Input differential pair.

I/O

I PCIE

PCI Express channel 0, Transmit Output differential pair.

O PCIE 179

181

174

176


I PCIE


O PCIE

158



PCI Express Reference Clock for Lanes 0 to 3.

PCI Express Wake Event: Sideband wake signal asserted by components requesting wakeup.

Reset Signal for external devices.

I PCIE


O PCIE

I PCIE


O PCIE

O PCIE

PU/PD

I 3.3VSB

PU 100k

3.3VSB

O 3.3V

Note

Comment

Supports PCI Express Base Specification, Revision 2.0


Supports PCI Express Base Specification, Revision 2.0.




Not connected

Not connected

On Intel Bay Trail SoC, the signal marked with asterisks (**) has a voltage level that is different from the level defined in the Qseven Specification.

To comply with the Qseven Specification, the signals are routed through bidirectional level shifters on the module.


46/88

Table 6 UART Signal Descriptions

Signal

UART0_TX (**)

UART0_RX (**)

Pin # Description

171 Serial Data Transmitter

177 Serial Data Reciever

I/O

O 3.3V

I 3.3VSB

PU/PD Comment

UART0_CTS# (**) 178 Handshake signal, ready to send data I 3.3VSB

PU 20k

3.3VSB

PU 20k

3.3VSB

UART0_RTS# (**) 172

Note

Handshake signal, ready to receive data O 3.3V




Table 7 Ethernet Signal Descriptions

Signal

GBE_MDI0+

GBE_MDI0-

GBE_MDI1+

GBE_MDI1-

GBE_MDI2+

GBE_MDI2-

GBE_MDI3+

GBE_MDI3-

GBE_CTREF

5

3

GBE_LINK# 13

GBE_LINK100# 7

GBE_LINK1000# 8

GBE_ACT# 14

6

4

11

9

Pin # Description

12

10

Media Dependent Interface (MDI) differential pair 0. The MDI can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is used for all modes.

15

Media Dependent Interface (MDI) differential pair 1. The MDI can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is used for all modes.

Media Dependent Interface (MDI) differential pair 2. The MDI can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is only used for 1000Mbit/sec Gigabit Ethernet mode.

Media Dependent Interface (MDI) differential pair 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. This signal pair is only used for 1000Mbit/sec Gigabit Ethernet mode.

Reference voltage for carrier board Ethernet magnetics center tap. The reference voltage is determined by the requirements of the module's PHY and may be as low as

0V and as high as 3.3V.

The reference voltage output should be current limited on the module. In a case in which the reference is shorted to ground, the current must be limited to 250mA or less.

Ethernet controller 0 link indicator, active low.

Ethernet controller 0 100Mbit/sec link indicator, active low.

Ethernet controller 0 1000Mbit/sec link indicator, active low.

Ethernet controller 0 activity indicator, active low.

I/O

I/O Analog

I/O Analog

I/O Analog

I/O Analog

REF

O 3.3VSB PP

O 3.3VSB PP

O 3.3VSB PP

O 3.3VSB PP

Note

PU/PD Comment

Twisted pair signals for external transformer.




Not connected

The conga-QA3/QA3E can drive GbE LEDs directly with up to 10mA.

47/88

Table 8 SATA Signal Descriptions

Signal

SATA0_RX+

SATA0_RX-

SATA0_TX+

SATA0_TX-

SATA1_RX+

SATA1_RX-

SATA1_TX+

SATA1_TX-

SATA_ACT#

30

32

33

29

31

36

38

Pin # Description

35

37

Serial ATA channel 0, Receive Input differential pair.

Serial ATA channel 0, Transmit Output differential pair.

Serial ATA channel 1, Receive Input differential pair.

Serial ATA channel 1, Transmit Output differential pair.

Serial ATA Led. Open collector output pin driven during SATA command activity.

Signal

USB_P0+

USB_P0-

USB_P1+

USB_P1-

USB_P2+

USB_P2-

USB_P3+

USB_P3-

USB_P4+

USB_P4-

USB_SSRX1+

USB_SSRX1-

USB_P5+

USB_P5-

USB_SSTX1+

USB_SSTX1-

USB_P6+

USB_P6-

USB_SSRX0+

USB_SSRX0-

USB_P7+

USB_P7-

USB_SSTX0+

USB_SSTX0-

Table 9 USB Signal Descriptions

95

93

90

88

89

87

84

82

Pin # Description

96

94

Universal Serial Bus Port 0 differential pair.


This port may be optionally used as USB client port.


83

81

78

76

77

75



Multiplexed with receive signal differential pairs for the

Superspeed USB data path.


Multiplexed with transmit signal differential pairs for the

Superspeed USB data path


Multiplexed with receive signal differential pairs for the



Multiplexed with transmit signal differential pairs for the


I/O

I SATA

O SATA

I SATA

O SATA

O 3.3V

PU/PD Comment

Supports Serial ATA specification, Revision 2.6




up to 10mA

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

O

I PCIE

PU/PD Comment

USB 2.0 compliant. Backwards compatible to USB 1.1

Can be used to form a USB 3.0 Port together with USB_SSRX0,

USB_SSTX0 signals.






O PCIE


AC coupled off module

Note:

This port has only Superspeed signals on the Qseven connector.


AC coupled on module.

Note:

This port has only Superspeed signals on the Qseven connector.

48/88

USB_0_1_OC# 86

USB_2_3_OC# 85

USB_4_5_OC# 80

USB_6_7_OC# 79

USB_ID

USB_VBUS#

92

91

Over current detect input 1. This pin is used to monitor the USB power over current of the USB Ports 0 and 1.




USB ID pin.

Configures the mode of the USB Port 1. Refer to the Qseven

Design guide for further details.

USB VBUS pin

5V tolerant

VBUS resistance to be placed on the module

VBUS capacitance to be placed on the carrier board

USB power enable pin for USB Port 1.

Enables the power for the USB-OTG port on the carrier

I 5V

Passive

Analog

O 3.3V

CMOS

I 3.3VSB

PU 20k

3.3VSB

I 3.3VSB

PU 20k

3.3VSB

I 3.3VSB

PU 20k

3.3VSB

I 3.3VSB

PU 10k

3.3VSB

O

Analog

Not supported

Not connected

Not connected

USB_DRIVE_

VBUS

Note

56 Not connected



Table 10 SDIO Signal Descriptions

Signal

SDIO_CD#

SDIO_CLK

SDIO_CMD

SDIO_LED

SDIO_WP

Pin # Description

43

42

45

44

SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.

I/O PU/PD Comment

I/O 3.3V

PU 10k

3.3V

O 3.3V

SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. This signal has maximum frequency of 48 MHz.

SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.

SDIO LED. Used to drive an external LED to indicate when transfers occur on the bus.

I/O 3.3V

OD/PP

O 3.3V

PU 20k

3.3V

Bay Trail SD Card controller does not provide any SDIO_LED signal. SDIO_

LED signal is therefore generated by a logic gate. LED blinking might differ from blinking behavior of other modules

46 SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.

I/O 3.3V

PU 10k

3.3V

49/88

SDIO_PWR#

SDIO_DAT0

SDIO_DAT1

SDIO_DAT2

SDIO_DAT3

SDIO_DAT4

SDIO_DAT5

SDIO_DAT6

SDIO_DAT7

Note

47

49

48

51

50

53

52

55

54

SDIO Power Enable. This signal is used to enable the power being supplied to a SD/

MMC card device.

SDIO Data lines. These signals operate in push-pull mode.

O 3.3V

I/O 3.3V

OD/PP

PU 10k

3.3V

PU 20k

3.3V

Only 4-bit SDIO interface.

SDIO_DAT[7:4] are not connected

The 20k pull-ups on the Data and CMD lines are internal Bay Trail pull-ups. The pull-ups are disabled once a high speed transfer is established.

Table 11 HDA Signal Descriptions

Signal

HDA_RST#

I2S_RST#

HDA_SYNC (**)

I2S_WS

HDA_BITCLK (**)

I2S_CLK

HDA_SDO (**)

I2S_SDO

HDA_SDI (**)

I2S_SDI

Note

Pin # Description

61

59

HD Audio Codec Reset.

Multiplexed with I2S Codec Reset.

HD Audio Serial Bus Synchronization.

Multiplexed with I2S Word Select from Codec.

63

67

65

HD Audio 24 MHz Serial Bit Clock from Codec.

Multiplexed with I2S Serial Data Clock from Codec.

HD Audio Serial Data Output to Codec.

Multiplexed with I2S Serial Data Output from Codec.

HD Audio Serial Data Input from Codec.

Multiplexed with I2S Serial Data Input from Codec.

I/O

O 3.3V

O 3.3V

O 3.3V

O 3.3V

I 3.3V

PU/PD Comment

PD 100k




50/88

Table 12 LVDS Signal Descriptions

Signal

LVDS_PPEN

LVDS_BLEN

LVDS_BLT_CTRL

/GP_PWM_OUT0

LVDS_A0+

LVDS_A0eDP0_TX0+ eDP0_TX0-

LVDS_A1+


LVDS_A2+


LVDS_A3+


LVDS_A_CLK+

LVDS_A_CLKeDP0_AUX+ eDP0_AUX-

LVDS_B0+

LVDS_B0eDP1_TX0+ eDP1_TX0-

LVDS_B1+


LVDS_B2+


LVDS_B3+


Pin # Description

111 Controls panel power enable.

112 Controls panel Backlight enable.

123

99

101

Primary functionality is to control the panel backlight brightness via pulse width modulation (PWM). When not in use for this primary purpose it can be used as General

Purpose PWM Output.

LVDS primary channel differential pair 0.

Display Port primary channel differential pair 0.

I/O

O 3.3V

O 3.3V

O 3.3V

O LVDS

103

105

O LVDS

107

109

113

115

119

121

100

102

104

106

108

110

114

116







LVDS primary channel differential pair clock lines.

Display Port primary auxiliary channel.

LVDS secondary channel differential pair 0.

Display Port secondary channel differential pair 0.







O LVDS

O LVDS

O LVDS

O LVDS

O LVDS

O LVDS

O LVDS

PU/PD Comment

PD 10k

PD 10k

51/88

LVDS_B_CLK+

LVDS_B_CLKeDP1_AUX+ eDP1_AUX-

LVDS_DID_CLK

/GP2_I2C_CLK

LVDS_DID_DAT

/GP2_I2C_DAT

LVDS_BLC_CLK eDP1_HPD#

LVDS_BLC_DAT eDP0_HPD#

120

122

127

125

128

126

LVDS secondary channel differential pair clock lines.

Display Port secondary auxiliary channel.

Primary functionality is DisplayID DDC clock line used for LVDS flat panel detection. If primary functionality is not used it can be as General Purpose I²C bus clock line.

Primary functionality DisplayID DDC data line used for LVDS flat panel detection. If primary functionality is not used it can be as General Purpose I²C bus data line.

Control clock signal for external SSC clock chip. If the primary functionality is not used, it can be used as an emedded

DisplayPort secondary Hotplug detection.

Control data signal for external SSC clock chip.

If the primary functionality is not used, it can be used as an emedded DisplayPort primary Hotplug detection.

O LVDS

I/O 3.3V

OD

I/O 3.3V

OD

I/O 3.3V

OD

I/O 3.3V

OD

PU 2.2k

3.3V

PU 2.2k

3.3V

PU 10k

3.3V

Not supported

PU 10k

3.3V

Not supported

Table 13 DisplayPort Signal Descriptions

Signal

DP_LANE3+

DP_LANE3-

DP_LANE2+

DP_LANE2-

DP_LANE1+

DP_LANE1-

DP_LANE0+

DP_LANE0-

DP_AUX+

DP_AUX-

DP_HPD#

Pin # Description

131

133

DisplayPort differential pair lines lane 3

(Shared with TMDS_CLK+ and TMDS_CLK-)

143

145

137

139

149

151

138

140

154


(Shared with TMDS_LANE0+ and TMDS_LANE0-)





Auxiliary channel used for link management and device control. Differential pair lines.

Hot plug detection signal that serves as an interrupt request.

I/O

O PCIE

O PCIE

O PCIE

O PCIE

I/O PCIE

I 3.3V

PU/PD Comment


PU 4.99k

1.8V




Supports open drain and PushPull driver. Onboard PU is protected with a diode

Note

The DisplayPort interface signals are shared with TMDS signals.

52/88

Table 14 HDMI/DVI Signal Descriptions

Signal

TMDS_CLK+

TMDS_CLK-

TMDS_LANE0+

TMDS_LANE0-

TMDS_LANE1+

TMDS_LANE1-

TMDS_LANE2+

TMDS_LANE2-

149

151

HDMI_CTRL_CLK 152

Pin # Description

131

133

TMDS differential pair clock lines.

(Shared with DP_LANE3- and DP_LANE3+)

143

145

137

139

TMDS differential pair lines lane 0.




HDMI_CTRL_DAT 150

DP_HDMI_HPD# 153

I/O

O TMDS

O TMDS

O TMDS

PU/PD Comment

Passive level shifter shall use PD 620R.





O TMDS Passive level shifter shall use PD 620R.

DDC based control signal (clock) for HDMI/DVI device. I/O 3.3V OD PU 4k 3.3V Level shifter FET and 2.2k PU to 5V shall be placed between module and HDMI/DVI connector.

DDC based control signal (data) for HDMI device.

I/O 3.3V OD PU 4k 3.3V Level shifter FET and 2.2k PU to 5V shall be placed between module and HDMI/DVI connector.

Hot plug active low detection signal that serves as an interrupt request.

I 3.3V

PU 4.99k

1.8V

Supports open drain and PushPull Driver. Onboard PU is protected with a diode

Note

The TMDS interface signals are shared with the DisplayPort signals.

Table 15 LPC Signal Descriptions

Signal

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3 188

LPC_FRAME# 190

Pin # Description

185 Multiplexed Command, Address and Data (LPC_AD[0..3])

186

187

LPC_LDRQ# 192

LPC_CLK 189

LPC frame indicates the start of a new cycle or the termination of a broken cycle.

LPC DMA request.

LPC clock

I/O

I/O 3.3V

PU/PD Comment

I/O 3.3V

I/O 3.3V PU 10k

I/O 3.3V

33 MHz on modules with Bay Trail-I SoC (Intel Atom E3800 series)

25 MHz on modules with Bay Trail-M/D SoC (Intel Celeron series)

SERIRQ (**)

Note

191 Serialized Interrupt.

I/O 3.3V

On Intel Bay Trail SoC, the signal marked with asterisks (**) has a voltage level that is different from the level defined in the Qseven Specification.

To comply with the Qseven Specification, the signals are routed through bidirectional level shifters on the module.

53/88


The conga-QA3/QA3E does not support GPIOs on the LPC interface.

Table 16 SPI Interface Signal Descriptions

Signal Pin # Description

SPI_MOSI (**) 199

I/O

Master serial output/Slave serial input signal. SPI serial output data from Qseven ® module to the SPI device. O 3.3VSB

SPI_MISO (**) 201 Master serial input/Slave serial output signal. SPI serial input data from the SPI device to Qseven

®

module.

I 3.3VSB

SPI_SCK (**)

SPI_CS0# (**)

SPI_CS1#

203

200

202

SPI clock output.

SPI chip select 0 output.

SPI Chip Select 1 signal is used as the second chip select when two devices are used. Do not use when only one SPI device is used.

O 3.3VSB

O 3.3VSB

O 3.3VSB

Note

PU/PD Comment

Not connected

The SPI interface is for external BIOS only.




Table 17 CAN Bus Signal Descriptions

Signal

CAN0_TX

CAN0_RX

Pin # Description

129 CAN (Controller Area Network) TX output for CAN Bus channel 0. In order to connect a CAN controller device to the Qseven

®

module’s CAN bus it is necessary to add transceiver hardware to the carrier board.

130 RX input for CAN Bus channel 0. In order to connect a CAN controller device to the Qseven

® module’s CAN bus it is necessary to add transceiver hardware to the carrier board.

I/O

O 3.3V

I 3.3V

PU/PD Comment

Not connected

Not connected

54/88

Table 18 Power and GND Signal Descriptions

Signal

VCC

VCC_RTC

GND

Pin #

211-230

VCC_5V_SB 205-206

193

1, 2, 23-25, 34, 39-40, 57-

58, 73-74, 97-98, 117-118,

135-136, 141-142, 147-148,

159-160, 165-166, 183-184,

197-198

Description

Power Supply +5VDC ±5%.

Standby Power Supply +5VDC ±5%.

3 V backup cell input. VCC_RTC should be connected to a 3V backup cell for

RTC operation and storage register non-volatility in the absence of system power. (VCC_RTC = 2.5 - 3.3 V).

Power Ground.

I/O PU/PD Comment

P

P

P

P

Table 19 Power Control Signal Descriptions

Signal

PWGIN

Pin # Description of Power Control signals

26 High active input for the Qseven

®

module indicates that power from the power supply is ready.

PWRBTN# 20 Power Button: Low active power button input. This signal is triggered on the falling edge.

I/O

I 5V

PU/PD

PU 1M 5V

I 3.3VSB PU 10k

3.3VSB

Comment

Table 20 Power Management Signal Descriptions

Signal

RSTBTN#

BATLOW#

WAKE#

SUS_S5# 16

SLP_BTN# 21

LID_BTN#

Pin # Description of Power Management signals

28 Reset button input. This input may be driven active low by an external circuitry to reset the Qseven

® module.

27

17

SUS_STAT# 19

SUS_S3# 18

22

Battery low input. This signal may be driven active low by external circuitry to signal that the system battery is low or may be used to signal some other external battery management event.

External system wake event. This may be driven active low by external circuitry to signal an external wake-up event.

Suspend Status: indicates that the system will be entering a low power state soon.

S3 State: This signal shuts off power to all runtime system components that are not maintained during

S3 (Suspend to Ram), S4 or S5 states.

The signal SUS_S3# is necessary in order to support the optional S3 cold power state.

S5 State: This signal indicates S4 or S5 (Soft Off) state.

Sleep button. Low active signal used by the ACPI operating system to transition the system into sleep state or to wake it up again. This signal is triggered on falling edge.

LID button. Low active signal used by the ACPI operating system to detect a LID switch and to bring system into sleep state or to wake it up again.

I/O PU/PD Comment

I 3.3VSB OD PU 10k

3.3VSB

I 3.3VSB

I 3.3VSB

O 3.3VSB

O 3.3VSB

O 3.3VSB

I 3.3VSB

I 3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

55/88

Table 21 Miscellaneous Signal Descriptions

Signal

WDTRIG#

WDOUT

GP0_I2C_CLK

GP0_I2C_DAT

GP1_SMB_CLK

GP1_SMB_DAT

SMB_ALERT#

SPKR

/GP_PWM_OUT2

194

BIOS_DISABLE#

/BOOT_ALT#

41

62

64

66

68

60

RSVD

GP_1-Wire_Bus

Pin #

70

72

132,134,144,

146,154

124

Description

Watchdog trigger signal. This signal restarts the watchdog timer of the Qseven ® module on the falling edge of a low active pulse.

Watchdog event indicator. High active output used for signaling a missing watchdog trigger. Will be deasserted by software, system reset or a system power down.

Clock line of I²C bus.

Data line of I²C bus.

Clock line of System Management Bus.

Data line of System Management Bus.

System Management Bus Alert input. This signal may be driven low by SMB devices to signal an event on the SM Bus.

Primary functionality is output for audio enunciator, the “speaker” in PC AT systems.

When not in use for this primary purpose it can be used as General Purpose PWM

Output.

Module BIOS disable input signal. Pull low to disable module’s onboard BIOS.

Allows off-module BIOS implementations. This signal can also be used to disable standard boot firmware flash device and enable an alternative boot firmware source, for example a bootloader.

Do not connect

General Purpose 1-Wire bus interface. Can be used for consumer electronics control bus (CEC) of HDMI.

I/O

I 3.3V

O 3.3V

I/O 3.3V OD PU 2.2k 3.3V

I/O 3.3V OD PU 2.2k 3.3V

I/O 3.3VSB

OD

PU 10k

3.3VSB

I/O 3.3VSB

OD

I/O 3.3VSB

OD

O 3.3V

I 3.3VSB

NC

I/O 3.3V

PU/PD

PU 10k 3.3V

PU 10k

3.3VSB

PU 10k 3.3V

PU 10k

3.3VSB

Comment

Not connected

Table 22 Manufacturing Signal Descriptions

Signal Pin # Description

MFG_NC0 207 This pin is reserved for manufacturing and debugging purposes. May be used as JTAG_TCK signal for boundary scan purposes during production or as a vendor specific control signal. When used as a vendor specific control signal the multiplexer must be controlled by the MFG_NC4 signal.

MFG_NC1 209

MFG_NC2 208

This pin is reserved for manufacturing and debugging purposes. May be used as JTAG_TDO signal for boundary scan purposes during production. May also be used, via a multiplexer, as a UART_TX signal to connect a simple UART for firmware and boot loader implementations. In this case the multiplexer must be controlled by the MFG_NC4 signal.

This pin is reserved for manufacturing and debugging purposes. May be used as JTAG_TDI signal for boundary scan purposes during production. May also be used, via a multiplexer, as a UART_RX signal to connect a simple

UART for firmware and boot loader implementations. In this case the multiplexer must be controlled by the

MFG_NC4 signal.

I/O PU/PD Comment

NA NA

NA

NA

NA

NA

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MFG_NC3 210

MFG_NC4 204

This pin is reserved for manufacturing and debugging purposes. May be used as JTAG_TMS signal for boundary scan purposes during production. May also be used, via a multiplexer, as vendor specific BOOT signal for firmware and boot loader implementations. In this case the multiplexer must be controlled by the

MFG_NC4 signal.

This pin is reserved for manufacturing and debugging purposes. May be used as JTAG_TRST# signal for boundary scan purposes during production. May also be used as control signal for a multiplexer circuit on the module enabling secondary function for MFG_NC0..3 ( JTAG / UART ). When MFG_NC4 is high active it is being used for JTAG purposes. When MFG_NC4 is low active it is being used for UART purposes.

NA

NA

NA

NA

Note

The carrier board must not drive the MFG_NC-pins or have pull-up or pull-down resistors implemented for these signals.

Table 23 Thermal Management Signal Descriptions

Signal

THRM#

Pin # Description

69 Thermal Alarm active low signal generated by the external hardware to indicate an over temperature situation. This signal can be used to initiate thermal throttling.

THRMTRIP# 71 Thermal Trip indicates an overheating condition of the processor. If 'THRMTRIP#' goes active the system immediately transitions to the S5 State (Soft Off).

I/O

I 3.3V

O 3.3V

PU/PD Comment

PU 6.7k

3.3V

Table 24 Fan Control Signal Descriptions

Signal

FAN_PWMOUT

FAN_TACHOIN

Pin # Description

196 Primary functionality is fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the Fan’s RPM based on the CPU’s die temperature. .

195 Primary functionality is fan tachometer input.

I/O

O 3.3V

I 3.3V

PU/PD Comment

PU 10k

3.3V

Table 25 Onboard Camera Interface Signal Descriptions

Signal

CAM_PWR

CAM_PWR

CAM0_CSI_D0+

CAM0_CSI_D0-

GND

CAM0_CSI_D1+

3

4

5

6

Pin # Description

1 3.3V +/- 5% supply voltage to power the camera device

2 3.3V +/- 5% supply voltage to power the camera device

CSI2 Camera 0 Data Lane 0+

CSI2 Camera 0 Data Lane 0-

CSI2 Camera 0 Data Lane 1+ I

I

I

I/O Type

3.3V O

3.3V O

Comment

Ground

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CAM0_CSI_D1-

GND

CAM0_CSI_D2+

CAM0_CSI_D2-

CAM0_RST#

CAM0_CSI_D3+

CAM0_CSI_D3-

12

13

GND 14

CAM0_CSI_CLK+ 15

CAM0_CSI_CLK-

GND

CAM0_I2C_CLK

CAM0_I2C_DAT

CAM0_ENA#

MCLK

20

21

16

17

18

19

7

8

9

10

11

CAM1_ENA#

CAM1_I2C_CLK

22

23

CAM1_I2C_DAT

GND

24

25

CAM1_CSI_CLK+ 26

CAM1_CSI_CLK-

GND

CAM1_CSI_D0+

CAM1_CSI_D0-

CAM1_RST#

CAM1_CSI_D1+

CAM1_CSI_D1-

GND

CAM0_GPIO

CAM1_GPIO

31

32

33

34

27

28

29

30

35

36




Camera 0 Reset (low active)



CSI2 Camera 0 Differential Clock+ (Strobe)

CSI2 Camera 0 Differential Clock- (Strobe)

Camera 0 Control Interface, CLK. (I²C like interface)

Camera 0 Control Interface, DATA. (I²C like interface)

Camera 0 Enable (low active)

Master Clock.

May be used by Cameras to drive it’s internal PLL Frequency range: 6...27 MHz

Camera 1 Enable (low active)

Camera 1 Control Interface, CLK. (I²C like interface)

Camera 1 Control Interface, DATA. (I²C like interface)

CSI2 Camera 1 Differential Clock+ (Strobe)

CSI2 Camera 1 Differential Clock- (Strobe)



Camera 1 Reset (low active)



GPIO for Camera 0

GPIO for Camera 1

I

Ground

I

I

I

I

CMOS 1.8V

Ground

I

I

CMOS 1.8V OD

CMOS 1.8V OD

CMOS 1.8V

CMOS 1.8V O

Ground

I

I

CMOS 1.8V

CMOS 1.8V OD

CMOS 1.8V OD

Ground

Ground

I

I

I

I

CMOS 1.8V

Ground

CMOS 1.8V

CMOS 1.8V

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9 System Resources

9.1 I/O Address Assignment

The I/O address assignment of the conga-QA3/QA3E module is functionally identical with a standard PC/AT. The BIOS assigns PCI and PCI

Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume I/O resources in that area.

9.1.1 LPC Bus

On the conga-QA3/QA3E the Platform Controller Hub (PCH) acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to the PCH and the LPC Bus. Some fixed I/O space ranges seen by the processor are:

Device

8259 Master

8254s

Ps2 Control

NMI Controller

RTC

Port 80h

Init Register

8259 Master

PCU UART

Reset Control

Active Power Management

IO Address

20h-21h, 24h-25h, 28h-29h, 2Ch-2Dh, 30h-31h, 34h-35h, 38h-39h, 3Ch-3Dh

40h-43h, 50h-53h

60h, 64h

61h, 63h, 65h, 67h

70h-77h

80h-83h

92h

A0h- A1h, A4h-A5h, A8h-A9h, Ach-ADh, B0h-B1h, B4h-B5h, B8h-B9h, Bch-BDh, 4D0h-4D1h

3F8h-3FFh

CF9h

B2h-B3h

Some of these ranges are used by a Super I/O if implemented on the carrier board or are occupied by the Qseven on-module UARTs if these are enabled in the setup. If you require additional LPC Bus resources other than those mentioned above, or more information about this subject, contact congatec technical support for assistance.

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9.2 PCI Configuration Space Map

Table 26 PCI Configuration Space Map

Bus Number

(hex)

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

04h

Note

Device Number

(hex)

00h

02h

12h

13h

14h

17h

1Ah

1Bh

1Ch

1Ch

1Ch

1Ch

1Dh

1Fh

1Fh

00h

Function Number

(hex)

00h

00h

00h

00h

00h

01h

00h

00h

00h

01h

02h

03h

00h

00h

03h

00h

Description

SoC Transaction Router

Graphics and Display

SD Port

SATA AHCI/IDE Controller

XHCI USB eMMC 4.5 Port

Trusted Execution Engine

HD Audio

PCI Express Root Port 0




EHCI USB

LPC: Bridge to Intel Legacy Port

SMBus Port

Intel I210 Ethernet Network

1. The PCI Express Ports are visible only if they are set to “Enabled” in the BIOS setup program and a device attached to the corresponding

PCI Express port on the carrier board.

2. The above table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board. The given bus numbers will change based on the actual configuration of the hardware.

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9.3

9.4

9.5

PCI Interrupt Routing Map

Table 27 PCI Interrupt Routing Map

D

E

F

G

H

A

B

C

PIRQ PCI BUS

INT Line ¹

INTA

INTB

INTC

INTD

17

18

19

20

21

22

23

APIC

Mode

IRQ

16

Graphic SD

Card x x

Note

SATA XHCI eMMC

4.5

Port x x x

TXE HD

Audio x x

PCI-EX

Root

Port 0 x

PCI-EX

Root

Port 1

PCI-EX

Root

Port 2 x x

PCI-EX

Root

Port 3

EHCI

USB x x

SMBus Port I210

Ethernet

Network x ² x x ³ x

4 x 5

1

These interrupt lines are virtual (message based).

2

Interrupt used by single function PCI Express devices (INTA).

3

Interrupt used by multifunction PCI Express devices (INTB).

4

Interrupt used by multifunction PCI Express devices (INTC).

5

Interrupt used by multifunction PCI Express devices (INTD).

I²C Bus

There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

SM Bus

System Management (SM) bus signals are connected to the Intel

®

Bay Trail SoC and the SM bus is not intended to be used by off-board nonsystem management devices. For more information about this subject contact congatec technical support.

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10 BIOS Setup Description

The following section describes the BIOS setup program. The BIOS setup program can be used to view and change the BIOS settings for the module. Only experienced users should change the default BIOS settings.

10.1 Entering the BIOS Setup Program.

The BIOS setup program can be accessed by pressing the <DEL> or <F2> key during POST.

10.1.1 Boot Selection Popup

Press the <F11> key during POST to access the Boot Selection Popup menu. A selection menu displays immediately after POST, allowing the operator to select either the boot device that should be used or an option to enter the BIOS setup program.

10.2 Setup Menu and Navigation

The congatec BIOS setup screen is composed of the menu bar, left frame and right frame. The menu bar is shown below:

Main Advanced Chipset Boot Security Save & Exit

The left frame displays all the options that can be configured in the selected menu. Grayed-out options cannot be configured. Only the blue options can be configured. When an option is selected, it is highlighted in white.

The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options and the possible impacts when changing the selected option in the left frame.

Note

Entries in the option column that are displayed in bold indicate BIOS default values.

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The setup program uses a key-based navigation system. Most of the keys can be used at any time while in setup. The table below explains the supported keys:

Key

← → Left/Right

↑ ↓ Up/Down

+ - Plus/Minus

Tab

F1

F2

F9

F10

ESC

ENTER

Description

Select a setup menu (e.g. Main, Boot, Exit).

Select a setup item or sub menu.

Change the field value of a particular setup item.

Select setup fields (e.g. in date and time).

Display General Help screen.

Load previous settings.

Load optimal default settings.

Save changes and exit setup.

Discard changes and exit setup.

Display options of a particular setup item or enter submenu.

10.3 Main Setup Screen

When you first enter the BIOS setup, you will see the main setup screen. The main setup screen reports BIOS, processor, memory and board information and is for configuring the system date and time. You can always return to the main setup screen by selecting the ‘Main’ tab.

Feature

Main BIOS Version

OEM BIOS Version

Build Date

Product Revision

Serial Number

BC Firmware Revision

MAC Address

Boot Counter

Microcode Patch

Baytrail SoC

Total Memory

System Date

System Time

Options

No option

Description

Displays the main BIOS version.

No option

No option

No option

No option

No option

No option

No option

Displays the additional OEM BIOS version.

Displays the date the BIOS was built.

Displays the hardware revision of the board.

Displays the serial number of the board.

Displays the firmware revision of the congatec board controller.

Displays the MAC address of the onboard Ethernet controller.

Displays the number of boot-ups. (max. 16777215).

No option

No option

No option

Day of week, month/ day/year

Displays the microcode patch loaded for the onboard CPU

B3 Stepping

Total amount of low voltage DDR3 present on the system

Specifies the current system date

Note: The date is in month/day/year format.

Hour:Minute:Second Specifies the current system time.

Note: The time is in 24 hour format.

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10.4 Advanced Setup

Select the advanced tab from the setup menu to enter the advanced BIOS setup screen. The menu is used for setting advanced features and only features described within this user’s guide are listed.

Main Advanced

Watchdog

Graphics

Hardware Health Monitoring

RTC Wake

Module Serial Ports

ACPI

Intel(R) Smart Connect Technology

Serial Port Console Redirection

CPU Configuration

PPM Configuration

Thermal Configuration

IDE Configuration

Miscellaneous Configuration

SCC Configuration

Network Stack

CSM

SDIO

Trusted Computing

USB

Platform Trust Technology

Security Configuration

Chipset Boot Security Save & Exit

Intel(R) I210 Gigabit Network

SIO

Driver Health

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10.4.1 Watchdog Submenu

Feature

POST Watchdog

Options

Disabled

30sec

1min

2min

5min

10min

30min

Stop Watchdog for

User Interaction

No

Yes

Runtime Watchdog Disabled

One-time Trigger

Single Event

Repeated Event

Delay

Event 1

Event 2

Event 3

Disabled

10sec

30sec

1min

2min

5min

10min

30min

ACPI Event

Reset

Power Button

Disabled

ACPI Event

Reset

Power Button

Disabled

ACPI Event

Reset

Power Button

Description

Select the timeout value for the POST watchdog.

The watchdog is only active during the power-on-self-test of the system and provides a facility to prevent errors during boot up by performing a reset.

Select whether the POST watchdog should be stopped during the popup of the boot selection menu or while waiting for setup password insertion.

Select the operating mode of the runtime watchdog. This watchdog will be initialized just before the operating system starts booting.

If set to ‘One-time Trigger’ the watchdog will be disabled after the first trigger.

If set to ‘Single Event’, every stage will be executed only once, then the watchdog will be disabled.

If set to ‘Repeated Event’ the last stage will be executed repeatedly until a reset occurs.

Select the delay time before the runtime watchdog becomes active. This ensures that an operating system has enough time to load.

Select the type of event that will be generated when timeout 1 is reached. For more information about ACPI Event, see note below.

Select the type of event that will be generated when timeout 2 is reached.

Select the type of event that will be generated when timeout 3 is reached.

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Feature

Timeout 1

Timeout 2

Timeout 3

Watchdog ACPI

Event

Note

Options

1sec

2sec

5sec

10sec

30sec

1min

2min

5min

10min

30min

See above

See above

Shutdown

Restart

Description

Select the timeout value for the first stage watchdog event.

Select the timeout value for the second stage watchdog event.

Select the timeout value for the third stage watchdog event.

Select the operating system event that is initiated by the watchdog ACPI event. These options perform a critical but orderly operating system shutdown or restart.

In ACPI mode, it is not possible for a “Watchdog ACPI Event” handler to directly restart or shutdown the OS. For this reason the congatec

BIOS will do one of the following:

For Shutdown: An over temperature notification is executed. This causes the OS to shut down in an orderly fashion.

For Restart: An ACPI fatal error is reported to the OS.

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10.4.2 Graphics Submenu

Feature

Boot Display Device

PWM Inverter Polarity

Backlight Setting

Force LVDS Backlight

Inhibit Backlight

Options

VBIOS Default

Active LFP No LVDS

LVDS

Always Try Auto Panel Detect No

Yes

Local Flat Panel Type

Auto

VGA 640x480 1x18 (002h)

VGA 640x480 1x18 (013h)

WVGA 800x480 1x24 (01Bh)

SVGA 800x600 1x18 (01Ah)

XGA 1024x768 1x18 (006h)

XGA 1024x768 2x18 (007h)

XGA 1024x768 1x24 (008h)

XGA 1024x768 2x24 (012h)

WXGA 1280x768 1x24 (01Ch)

SXGA 1280x1024 2x24 (00Ah)

SXGA 1280x1024 2x24 (018h)

UXGA 1600x1200 2x24 (00Ch)

HD 1920x1080 2x24 (01Dh)

WUXGA 1920x1200 2x18 (015h)

WUXGA 1920x1200 2x24 (00Dh)

Customized EDID™ 1



Backlight Inverter Type None

PWM

I2C

PWM Inverter Frequency (Hz) 200 - 40000

Normal

Inverted

0%, 10%, 25%, 40%, 50%, 60%,

75%, 90%, 100%

No

Yes

No

Permanent

Until End Of POST

Description

Select the active local flat panel configuration.

If set to ‘Yes’ the BIOS will first look for an EDID data set in an external EEPROM to configure the Local Flat

Panel. If no external EDID data set is found, the data set selected under ‘Local Flat Panel Type’ will then be used as a fallback data set.

Select a predefined LFP type or choose Auto to let the BIOS automatically detect and configure the attached

LVDS panel.

Auto detection is performed by reading an EDID data set via the video I²C bus.

The number in brackets specifies the congatec internal number of the respective panel data set.

Note: Customized EDID™ utilizes an OEM defined EDID™ data set stored in the BIOS flash device.

Select the type of backlight inverter used.

PWM = Use IGD PWM signal.

I2C = Use I2C backlight inverter device connected to the video I²C bus.

Set the PWM inverter frequency in Hz.

Only visible if ‘Backlight Inverter Type’ is set to ‘PWM’.

Select PWM inverter polarity.

Only visible if ‘Backlight Inverter Type’ is set to ‘PWM’ .

Actual backlight value in percent of the maximum setting.

Force LVDS Enable and LVDS VDD Signals unconditionally

Decide whether the backlight on signal should be activated when the panel is activated or whether it should remain inhibited until the end of BIOS POST or permanently.

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Feature

Digital Display Interface 1

(DDI1)

Options

Disabled

DisplayPort

HDMI/DVI

Auto

Description

Select the output type of the digital display interface.

10.4.3 Hardware Health Monitoring Submenu

Feature

CPU Temperature

CPU Fan Speed

Options

No option

No option

Description

Displays the actual CPU Temperature in °C.

Displays the actual CPU Fan Speed in RPM.

10.4.4 RTC Wake Submenu

Feature

Wake System At Fixed Time

Wake up hour

Wake up minute

Wake up second

Options

Disabled

Enabled

10.4.5 Module Serial Ports Submenu

Feature

Serial Port 0

Serial Port 1

Options

Disabled

Enabled

Disabled

Enabled

Description

Enable system to wake from S5 using RTC alarm.

Specify wake up hour. For example, enter “3” for 3am and “15” for 3pm.

Specify wake up minute.

Specify wake up second.

Description

Enable or disable module serial port 0.

Enable or disable module serial port 1.

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10.4.6 ACPI Submenu

Feature

Enable ACPI Auto

Configuration

Enable Hibernation

ACPI Sleep State

Lock Legacy Resources

LID Support

Sleep Button Support

Options

Disabled

Enabled

Disabled

Enabled

Suspend Disabled

S3 (Suspend to RAM)

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Enable or disable BIOS ACPI Auto Configuration

Enable or disable system’s ability to hibernate (operating system S4 sleep state). This option may not be effective with some operating systems.

Select the state used for ACPI system sleep/suspend.

Enable or disable locking of legacy resources.

Activate ACPI LID button support

Activate ACPI sleep button support

10.4.7 Intel(R) Smart Connect Technology Submenu

Feature

ISCT Support

ISCT Notification Control

ISCT WLAN Power Control

ISCT WWAN Power Control

ISCT Sleep Duration Value

Format

ISCT RF Kill Switch Type

ISCT RTC Timer Support

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Duration in Seconds

Software

Hardware

Disabled

Enabled

Description

Enable or disable Intel(R) Smart Connection Support. When this setup node is set to Disabled, all the other

Nodes will not be visible.

Enable or Disable ISCT Notification Control.

Enable or Disable ISCT WLAN Power Control.

Enable or Disable ISCT WWAN Power Control

ISCT Sleep Duration in seconds.

Select ISCT RF Kill Switch Type

Enable ISCT RTC Timer

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10.4.8 Serial Port Console Redirection Submenu

Feature

COM0

Console Redirection

Options

Disabled

Enabled

►Console Redirection Settings submenu

Serial Port for Out-of-Band

Disabled

Management / EMS

Console Redirection

Enabled

►Console Redirection Settings Submenu

Description

Enable or disable serial port 0 console redirection.

Opens console redirection configuration sub menu.

Enable or disable Serial Port for Out-of-Band Management / Windows Emergency Management Services.

Opens console redirection configuration sub menu.

10.4.8.1 Console Redirection Settings COM0 Submenu

Feature

Terminal Type

Baudrate

Data Bits

Parity

Stop Bits

Flow Control

VT-UTF8 Combo Key Support

Recorder Mode

Resolution 100x31

Legacy OS Redirection

Resolution

Options

VT100

VT100+

VT-UTF8

ANSI

9600, 19200, 38400, 57600,

115200

7,

8

None

Even

Odd

Mark

Space

1

2

None

Hardware RTS/CTS

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

80x24

80x25

Description

Select terminal type.

Select baud rate.

Set number of data bits.

Select parity.

Set number of stop bits.

Select flow control.

Enable VT-UTF8 combination key support for ANSI/VT100 terminals

With recorder mode enabled, only text output will be sent over the terminal. This is helpful to capture and record terminal data.

Enable or disable extended terminal resolution.

Number of rows and columns supported for legacy OS redirection.

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Feature

Putty KeyPad

Options

VT100

LINUX

XTERMR6

SCO

ESCN

VT400

Description

Select Function Key and KeyPad on Putty.

10.4.8.2 Console Redirection Settings Out-of-Band Management Submenu

Feature

Terminal Type

Bits Per Second

Data Bits

Parity

Stop Bits

Options

VT100

VT100+

VT-UTF8

ANSI

9600, 19200, 38400, 57600,

115200

8

None

1

Description

Select terminal type.

Select baud rate.

Set number of data bits.

Select parity.

Set number of stop bits.

10.4.9 CPU Configuration Submenu

Feature Options

►Socket 0 CPU Information

Submenu

►CPU Thermal Configuration

Submenu

CPU Speed

64-bit

Active Processor Cores

Limit CPUID Maximum

No option

No option

All

1

Disabled

Enabled

Execute Disable Bit

Hardware Prefetcher

Disabled

Enabled

Disabled

Enabled

Description

Socket specific CPU information

CPU thermal configuration options

Displays the CPU clock frequency

Displays whether 64-bit is supported.

Set the number of cores to be enabled.

When enabled, the processor limits the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value.

When disabled, the processor returns the actual maximum CPUID input value of the processor when queried.

Limiting the CPUID input value may be required for older operating systems that cannot handle the extra CPUID information returned when using the full CPUID input value.

Enable or disable the Execute Disable Bit (XD) of the processor. With the XD bit set to enabled, certain classes of malicious buffer overflow attacks can be prevented when combined with a supporting OS.

Enable or disable the Mid Level Cache (MLC) streamer prefetcher.

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Feature Options

Adjacent Cache Line Prefetch Disabled

Enabled

Intel Virtualization Technology Disabled

Enabled

Power Technology Disable

Energy Efficient

Custom

Description

Enable or disable prefetching of adjacent cache lines.

Enable or disable support for the Intel virtualization technology.

Configure the power technology schema for the CPU

10.4.9.1 Socket 0 CPU Information Submenu

Feature

CPU Name

CPU Signature

Microcode Patch

Max. CPU Speed

Min. CPU Speed

Processor Cores

Intel HT Technology

Intel VT-x Technology

L1 Data Cache

L1 Code Cache

L2 Cache

L3 Cache

Options

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

Description

Displays socket specific CPU name

Displays CPU signature number

Displays the CPU microcode patch number

Displays the maximal CPU clock frequency

Displays the minimal CPU clock frequency

Displays the number of CPU core on Socket CPU

Displays the Intel HT Technology support information.

Displays the Intel VT-x Technology support information

Displays the Socket L1 data cache information

Displays the Socket L1 code cache information



10.4.9.2 CPU Thermal Configuration Submenu

Feature

DTS

Options

Enabled

Disabled

Description

Enable or Disable CPU Digital Thermal Sensor (DTS).

DTS is used on ACPI functions to read the CPU temperature. This value is read from MSR.

10.4.10 PPM Configuration Submenu

Feature

EIST

CPU C state Report

Options

Disabled

Enabled

Disabled

Enabled

Description

Enable or disable Enhanced Intel SpeedStep Technology (EIST).

Enable/Disable CPU state Report to Operating System.

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Feature

Enhanced CPU C-state

Max CPU C state

SOix

Options

Disabled

Enabled

C7

C6

C1

Disabled

Enabled

Description

Enable/Disable enhanced CPU C states

Maximal CPU C state supported by the CPU

Enable/Disable CPU SOix state support

10.4.11 Thermal Configuration

Feature

Critical Trip Point

Passive Trip Point 90 C

87 C

85 C

79 C

71 C

63 C

55 C

47 C

39 C

31 C

23 C

15 C

Options

55 C

47 C

39 C

31 C

23 C

15 C

90 C

87 C

85 C

79 C

71 C

63 C

Description

Temperature of the ACPI critical Trip Point in which the OS will shut the system off.

Temperature of the ACPI passive Trip Point in which the OS will begin throttling the processor.

Note

The conga-QA3/QA3E does not support active trip point.

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10.4.12 IDE Configuration Submenu

Feature

Serial-ATA (SATA)

SATA Test Mode

SATA Speed Support

SATA ODD Port

SATA Mode

Serial-ATA Port 0

SATA Port 0 Hot Plug

Serial-ATA Port 1

SATA Port 1 Hot Plug

SATA Port 0 Information

SATA Port 1 Information

Options

Enabled

Disabled

Enabled

Disabled

Gen1

Gen2

Port 0 ODD

Port 1 ODD

No ODD

IDE Mode

AHCI Mode

Enabled

Disabled

Disabled

Enabled

Enabled

Disabled

Disabled

Enabled

No Option

No Option

Description

Enable or disable the onboard SATA controller.

Should be set to Disabled.

Test Mode is used just for verification measurements.

Indicates the maximum speed the SATA controller can support.

Configure which SATA Port is ODD.

Configure SATA Port Mode

Enable or disable the SATA Port 0.

Select hot plug support for SATA Port 0.

Not possible in Native IDE mode.

Enable or disable the SATA Port 1.

Select hot plug support for SATA Port 1.

Not possible in Native IDE mode.

Displays Information of device detected on SATA Port 0.

Displays Information of device detected on SATA Port 1.

10.4.13 Miscellaneous Configuration Submenu

Feature

High Precision Timer

Options

Enabled

Disabled

Boot Timer with HPET Timer Enabled

Disabled

PCI Express Dynamic Clock

Gating

Enabled

Disabled

Description

Enable or disable the high precision event timer.

Allow boot timer calculation with the high precision event timer.

Enable dynamic clock gating.

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10.4.14 SCC Configuration Submenu

Feature

SCC Device Mode

Options

ACPI Mode

PCI Mode

SCC eMMC Support

SCC 4.5 DDR50 eMMC Support

Enabled

Disabled

SCC 4.5 HS200 eMMC Support Enabled

Disabled

eMMC Secure Erase

Enable eMMC 4.5 Support

Enable eMMC 4.41 Support

eMMC AUTO MODE

Disable

SCC SD Card Support

SDR25 Support for SD Card

DDR50 Support for SD Card

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Description

Configure the storage control cluster working mode.

Enable SCC eMMC support and configure eMMC mode.

Enable DDR50 eMMC support.

Enable DDR50 eMMC support.

Enable eMMC secure erase support.

Enable storage control cluster SD Card support

Enable SDR25 Support for SD Card

Enable DDR50 Support for SD Card

10.4.15 Network Stack

Feature

Network Stack

Ipv4 PXE Support

Ipv6 PXE Support

PXE boot wait time

Options

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

0-5

Description

Enable or disable the UEFI network stack.

Enable Ipv4 PXE boot support. If disabled IPV4 PXE boot option will not be created.

Enable Ipv6 PXE boot support. If disabled IPV6 PXE boot option will not be created.

Wait time to press ESC to abort PXE Boot

10.4.16 CSM Submenu

Feature

Launch CSM

CSM16 Module Version

Gate A20 Active

Options

Enabled

Disabled

No option

Upon Request

Always

Description

Enable the Compatibility Support Module.

Display CSM Module Version number.

Configure legacy Gate A behavior.

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Feature

Option ROM Messages

INT19 Trap Response

Boot Option Filter

Network

Storage

Video

Other PCI Devices

Options

Force BIOS

Keep Current

Immediate

Postponed

UEFI and Legacy

Legacy Only

UEFI Only

Do not launch

UEFI only

Legacy only

Do not launch

UEFI only

Legacy only

Do not launch

UEFI only

Legacy only

UEFI only

Legacy only

Description

Enable Option ROM message

Define BIOS reaction on INT19 trapping by Option ROM:

Immediate executes the trap right away.

Postpone executes the trap during legacy boot.

Controls which devices / boot loaders the system should boot to.

Controls the execution of UEFI and legacy Network option ROMs.

Controls the execution of UEFI and legacy Storage option ROMs.

Controls the execution of UEFI and legacy Video option ROMs

Controls the execution of UEFI and legacy option ROMs for any other PCI device different to Network, Video and Storage.

10.4.17 SDIO Submenu

Feature

SDIO Access Mode

Options

Auto

DMA

PIO

Description

Controls the SDIO Access mode to the device.

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10.4.18 Trusted Computing Submenu

Feature

Security Device Support

User Confirmation

TPM State

Pending operation

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

None

Enable Take Ownership

Disable Take Ownership

TPM Clear

Description

Enable or disable TPM support. System reset is required after change.

Enable or disable user confirmation requests for certain transactions.

Enable or disable TPM chip.

Note: System might restart several times during POST to acquire target state.

Perform selected TPM chip operation.

Note: System might restart several times during POST to perform selected operation.

10.4.19 USB Submenu

Feature

USB Module Version

USB Devices

Options

No option

No option xHCI Hand-off

EHCI Hand-off

USB Mass Storage

Driver Support

Enabled

Disabled

Disabled

Enabled

Disabled

Enabled

Device Reset Timeout 10 sec

20 sec

30 sec

40 sec

USB Transfer Timeout 1 sec

5 sec

10 sec

20 sec

Device Power -Up Delay

Selection

Auto

Manual

Device Power -Up Delay

Value

0-40

Default : 5

Description

Displays the version of the USB module.

Displays the detected USB devices.

This is a workaround for OSes without xHCI hand-off support. The xHCI ownership change should be claimed by xHCI OS driver.

This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by EHCI OS driver.

Enable Mass Storage Driver Support.

USB legacy mass storage device start unit command timeout.

The timeout value for control, bulk, and interrupt transfers.

Define maximum time a USB device might need before it properly reports itself to the host controller. Auto selects a default value which is 100ms for a root port or derived from the hub descriptor for a hub port.

Actual power-up delay value in seconds.

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10.4.20 Platform Trust Technology

Feature fTPM

Options

Disabled

Enabled

10.4.21 Security Configuration

Feature

TXE

TXE HMRFPO

TXE Firmware Update

TXE EOP Message

TXE Unconfiguration Perform

Intel(R) Anti-Theft Technology

Configuration

Intel(R) AT

Intel(R) AT Platform PBA

Intel(R) AT Suspend Mode

Options

Enabled

Disabled

Enable

Disable

Enabled

Disabled

Enabled

Disabled

No option

No option

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Description

Enable Trusted Platform Module support.

Description

Enable Trusted Execution Engine.

Enable Host ME Region Flash Protection Overwrite.

Enable Firmware update.

Enable TXE End of Post Message.

Execute a TXE unconfiguration command

Enable Anti-Theft technology.

Enable Anti-Theft Platform Pre-boot Authentication.

Enable Anti-Theft Suspend Mode.

10.4.22 SIO Submenu

Feature

AMI SIO Driver Version

►Serial Port 1

►Serial Port 2

►Parallel Port

►PS2 Controller

(KB&MS)

Note

Options

No option

No option

No option

No Option

Description

Serial Port 1 Submenu

Serial Port 2 Submenu

Parallel Port Submenu

PS2 configuration Submenu

This setup menu is only available if an external Winbond W83627 Super I/O has been implemented on the carrier board.

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10.4.22.1 Serial Port 1 Submenu

Feature

Use this Device

Options

Enabled

Disabled

Logical Device Settings No option

Possible

Use Automatic Settings

IO=3F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=2F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=3F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=3E8; IRQ=3,4,5,7,9,10,11, 12; DMA;

Description

Enable Logical Device.

Show current Logical Device Settings.

Serial Port 1 configuration options.

10.4.22.2 Serial Port 2 Submenu

Feature

Use this Device

Options

Enabled

Disabled


Possible


IO=3F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=2F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=3F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=3E8; IRQ=3,4,5,7,9,10,11, 12; DMA;

Description



Serial Port 2 configuration options.

10.4.22.3 Parallel Port Submenu

Feature

Use this Device

Options

Enabled

Disabled


Possible


IO=3F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=2F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=3F8; IRQ=3,4,5,7,9,10,11, 12; DMA;

IO=3E8; IRQ=3,4,5,7,9,10,11, 12; DMA;

Description



Parallel Port configuration options.

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10.4.22.4 PS2 Controller (KB&MS) Submenu

Feature

Use this Device

Options

Enabled

Disabled


Possible


IO=60h; IO=64h; IRQ=1;

Description



PS2 configuration options.

10.4.23 Intel(R) Ethernet Connection I210 Submenu

At this submenu additionally to its title the MAC address is displayed at the end of the title.

Feature

► NIC Configuration

Blink LEDs

UEFI Driver

Adapter PBA

Chip Type

PCI Device ID

Bus:Device:Function

Link Status

MAC Address

Options submenu

0-15

Default : 0

No option

No option

No option

No option

No option

No option

No option

Description

Opens the NIC Configuration submenu.

The Ethernet LEDs will blink so many seconds long as entered.

Displays the UEFI Driver version.

Displays the Adapter PBA.

Displays the type of the Chip in which the Ethernet controller is integrated.

Displays the PCI Device ID of the Ethernet controller.

Displays the PCI Bus:Device:Function number of the Ethernet controller.

Displays the Link Status.

Displays the MAC Address.

10.4.23.1 NIC Configuration Submenu

Feature

Link Speed

Wake on LAN

Options

Auto Negotiated

10 Mbps Half

10 Mbps Full

100 Mbps Half

100 Mbps Full

Disabled

Enabled

Description

Specifies the port speed used for the selected boot protocol.

Enables Wake on LAN (WOL) feature

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10.4.24 Driver Health Submenu

Feature

► Intel(R) PRO/1000

Options

No option

10.4.24.1 Intel(R) PRO/1000 Submenu

Feature

Controller Information

Options

No option

Description

Provides Health Status for the drivers/Controllers connected to the System

Description

Provides Health Status of the controller

10.5 Chipset Setup

Select the Boot tab from the setup menu to enter the Boot setup screen.

10.5.1 North Bridge Submenu

Feature

Memory Information

Total Memory

Memory Slot 0

Memory Slot 1

Options

No option

No option

No option

10.5.2 South Bridge Submenu

Feature

►Azalia HD Audio

► USB

► PCI Express Configuration

High Precision Timer

Restore AC Power Loss

Serial IRQ

Options

Submenu

Submenu

Submenu

Enabled

Disabled

Power Off

Power On

Last State

Quiet

Continuous

Description

Total amount of memory detected by the system

Memory detected by the system on Slot 0

Memory detected by the system on Slot 1

Description

Azalia HD Audio Submenu.

USB Submenu.

PCI Express Configuration Submenu.

Enable High Precision Event Timer.

Configure the State of the system after a Power Loss when running in AT Mode

Configure IRQ Serial Mode

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Feature

SB CRID

Global SMI Lock

BIOS Read/Write Protection

Options

Revision ID

CRID 0

CRID 1

CRID 2

Enabled

Disabled

Enabled

Disabled

10.5.2.1 Azalia HD Audio

Feature

LPE Audio Support

Audio Controller

Options

Disable

LPE Audio PCI Mode

LPE Audio ACPI Mode

Enabled

Disabled

Azalia Vci Enable

Enabled

Disabled

Azalia Docking Support Enable Enable

Disable

Azalia PME Enable

Azalia HDMI Codec

HDMI Port B

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

HDMI Port C Enabled

Disabled

Description

Select the Revision ID showed on the PCI configuration space.

Enable or Disable SMI Lock

Enable BIOS SPI Region read/write protection.

Description

Enable LPE Audio Support.

Enable Audio Controller.

Enable Azalia Vci.

Enable Azalia Docking support.

Enable Azalia PME support.

Enable Azalia HDMI Codec

Enable HDMI Port B Audio.

Enable HDMI Port C Audio.

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10.5.2.2 USB Submenu

Feature

USB OTG Support

USB VBUS

XHCI Mode

Options

Disabled

Enabled

On

Off

Enabled

Disabled

Auto

Smart Auto

USB2 Link Power

Management

USB 2.0(EHCI) Support

USB Per Port Control

USB Port 0

USB Port 1

USB Port 2

USB Port 3

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Enable USB OTG support.

VBUS should be On in Host Mode and it should be Off in OTG device Mode.

USB3.0 mode support on USB0, USB1, USB2 and USB3 ports

Disabled – USB ports will function in USB2.0 mode only. No USB3.0 OS driver required. The USB ports will be routed to EHCI1 controller.

Enabled – USB ports will function correctly in BIOS but the ports on which the USB3.0 mode is enabled (see USB0 port USB3.0 item) will not function at all under OS if the USB3.0 OS driver is not installed. USB ports will not function in pre-OS time if USB3.0 Support in BIOS is disabled (see the USB3.0 Support in BIOS item).

Auto – USB ports are initially set to operate in USB2.0 Mode and the USB3.0 OS driver (if available) will switch them USB3.0 mode. If USB3.0 OS driver is not available than the ports will function correctly but they will operate in

USB2.0 mode.

Smart Auto – The BIOS will store the USB mode set by the OS and at next boot the BIOS will set this previously used mode. At G3 boot (first boot after mechanical disconnection of the power supply) the USB ports will function identically as in Auto mode. This mode is not available when Disabled is selected at USB3.0 Support in BIOS item.

Enable USB2 Link Power Management

Control USB EHCI (USB 2.0) functions.

Control each of the USB ports (0-3).

Enable Port 0

Enable Port 1

Enable Port 2

Enable Port 3

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10.5.2.3 PCI Express Configuration Submenu

Feature

PCIe noncompliance Card

PCI Express Port 0

Speed

PCI Express Port 1

Speed

PCI Express Port 2

Speed

PCI Express Port 3

Speed

Options

Not Supported

Supported

Disabled

Enabled

Auto

Gen 2

Gen 1

Disabled

Enabled

Auto

Gen 2

Gen 1

Disabled

Enabled

Auto

Gen 2

Gen 1

Disabled

Enabled

Auto

Gen 2

Gen 1

Description

Enable PCIe 1.0 Device Support

Enable PCIe Port 0.

Configure PCIe Port 0 Speed.

This feature is visible only if PCIe noncompliance card option is set to “Not Supported”. If the option is set to

“supported”, then the speed defaults to Gen 1.

Enable PCIe Port 1.




Enable PCIe Port 2.




Enable PCIe Port 3.




10.6 Boot Setup

Select the Boot tab from the setup menu to enter the Boot setup screen.

10.6.1 Boot Settings Configuration

Feature Options

Setup Prompt Timeout

1

0 - 65535

Bootup NumLock State On

Off

Quiet Boot

Disabled

Enabled

Description

Number of seconds to wait for setup activation key.

0 means no wait for fastest boot (not recommended), 65535 means infinite wait.

Select the keyboard numlock state.

Disabled displays normal POST diagnostic messages.

Enabled displays OEM logo instead of POST messages.

Note: The default OEM logo is a dark screen.

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Feature

Enter Setup If No Boot

Device

Options

No

Yes

Enable Popup Boot

Menu

No

Yes

Boot Priority Selection Device Based

Type Based

Power Loss Control

Remain Off

Turn On

Last State

Description

Select whether the setup menu should be started if no boot device is connected.

Select whether the popup boot menu can be started.

Select between device and type based boot priority lists. The “Device Based” boot priority list allows you to select from a list of currently detected devices only. The “Type Based” boot priority list allows you to select device types, even if a respective device is not yet present. Moreover, the “Device Based” boot priority list might change dynamically in cases when devices are physically removed or added to the system. The “Type Based” boot menu is static and can only be changed by the user.

Specifies the mode of operation if an AC power loss occurs.

Remain Off keeps the power off until the power button is pressed.

Turn On restores power to the computer.

Last State restores the previous power state before power loss occurred.

Note: Only works with an ATX type power supply.

Determines the behavior of an AT-powered system after a shutdown.

Define system state after shutdown when a battery system is present.

Enable or disable boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS / legacy boot options.

AT Shutdown Mode

System Off Mode

Fast Boot

System Reboot

Hot S5

G3/Mech Off

S5/Soft Off

Disabled

Enabled

Note

1. The term ‘AC power loss’ stands for the state when the module looses the standby voltage on the 5V_SB pins. On congatec modules, the standby voltage is continuously monitored after the system is turned off. If within 30 seconds the standby voltage is no longer detected, then this is considered an AC power loss condition. If the standby voltage remains stable for 30 seconds, then it is assumed that the system was switched off properly.

2. Inexpensive ATX power supplies often have problems with short AC power sags. When using these ATX power supplies it is possible that the system turns off but does not switch back on, even when the PS_ON# signal is asserted correctly by the module. In this case, the internal circuitry of the ATX power supply has become confused. Usually another AC power off/on cycle is necessary to recover from this situation.

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10.7 Security Setup

Select the Security tab from the setup menu to enter the Security setup screen.

10.7.1 Security Settings

Feature

Administrator Password

Options

Enter password

HDD Security Configuration

List of all detected hard disks supporting the security feature set

Select device to open device security configuration submenu

Description

Specifies the setup administrator password.

10.7.2 Hard Disk Security

This feature enables the users to set, reset or disable passwords for each hard drive in Setup without rebooting. If the user enables password support, a power cycle must occur for the hard drive to lock using the new password. Both user and master password can be set independently however the drive will only lock if a user password is installed.

10.8 Save & Exit Menu

Select the Save & Exit tab from the setup menu to enter the Save & Exit setup screen. You can display a Save & Exit screen option by highlighting it using the <Arrow> keys.

Feature

Save Changes and Exit

Discard Changes and Exit

Save Changes and Reset

Description

Exit setup menu after saving the changes. The system is only reset if settings have been changed.

Exit setup menu without saving any changes.

Save changes and reset the system.

Discard Changes and Reset Reset the system without saving any changes.

Save Options

Save Changes

Discard Changes

Restore Defaults

Save changes made so far to any of the setup options. Stay in setup menu.

Discard changes made so far to any of the setup options. Stay in setup menu.

Restore default values for all the setup options.

Boot Override

List of all boot devices currently detected

Select device to leave setup menu and boot from the selected device.

Only visible and active if Boot Priority Selection setup node is set to “Device Based”.

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11 Additional BIOS Features

The conga-QA3/QA3E uses a congatec/AMI AptioEFI that is stored in an onboard Flash Rom chip and can be updated using the congatec

System Utility (version 1.5.0 and later), which is available in a DOS based command line, Win32 command line, Win32 GUI, and Linux version.

The BIOS displays a message during POST and on the main setup screen identifying the BIOS project name and a revision code. The initial production BIOS is identified as QA31R1xx, QA32R1xx, QC31R1xx and QC32R1xx where:

• QA31 is the BIOS for modules with Intel Atom Single Channel Memory SoC

• QA32 is the BIOS for modules with Intel Atom Dual Channel Memory SoC

• QC31 is the BIOS for modules with Intel Celeron Single Channel Memory SoC

• QC32 is the BIOS for modules with Intel Celeron Dual Channel Memory SoC

• QA3E is the BIOS for modules with ECC memory

• R is the identifier for a BIOS ROM file, 1 is the so called feature number and xx is the major and minor revision number.

The binary size of QA31, QA32, QC31, QC32 and QA3E BIOS is 8MB.

11.1 Supported Flash Devices

The conga-QA3/QA3E supports the following flash devices:

• Winbond W25Q64CVSSIG (8MB)

The flash device listed above is tested and can be used on the carrier board for external BIOS support. For more information about external

BIOS support, refer to the Application Note AN7_External_BIOS_Update.pdf on the congatec website at http://www.congatec.com.

11.2 Updating the BIOS

BIOS updates are often used by OEMs to correct platform issues discovered after the board has been shipped or when new features are added to the BIOS.

For more information about “Updating the BIOS” refer to the user’s guide for the congatec System Utility, which is called CGUTLm1x.pdf and can be found on the congatec AG website at www.congatec.com.

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12 Industry Specifications

The list below provides links to industry specifications that apply to congatec AG modules.

Specification

Qseven

®

Specification

Qseven

®

Design Guide

Low Pin Count Interface Specification, Revision 1.0 (LPC)

Universal Serial Bus (USB) Specification, Revision 2.0

Serial ATA Specification, Revision 1.0a

PCI Express Base Specification, Revision 2.0

Link http://www.qseven-standard.org/ http://www.qseven-standard.org/ http://developer.intel.com/design/chipsets/industry/lpc.

htm http://www.usb.org/home http://www.serialata.org

http://www.pcisig.com/specifications

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Congatec conga QA3, QA3E Qseven modules User’s Guide

Assistant Bot

®

Third Generation Intel

Atom™ and Intel

Celeron

SoC

User’s Guide

Revision 1.0

Revision History

Preface

Contents

List of Tables

1 Introduction

1.1 Qseven

Concept

1.2 conga-QA3 Options Information

1.3 conga-QA3E Options Information

2 Specifications

2.1 Feature List

2.2

2.3

Supported Operating Systems

Mechanical Dimensions

Rear View of Qseven Module

2.4 Supply Voltage Standard Power

2.5 Power Consumption

2.6 Supply Voltage Battery Power

2.7 Environmental Specifications

3 Block Diagram

Intel Bay Trail SoC

4 Heatspreader

4.1 Heatspreader Dimensions

5 Connector Subsystems

1x DisplayPort

1x HDMI

1x DVI

1x LVDS

3x PCI Express Lanes

Gigabit Ethernet

1x USB 3.0

6x USB 2.0

2x Serial ATA

UART

High Definition Audio eMMC

SD/MMC

SM Bus

SPI Bus

LPC Bus

I²C Bus

Fan Control

Watchdog

Power Control

Power Management

MIPI-CSI 2.0

5.1

5.2

5.3

5.4

5.5

PCI Express™

ExpressCard™

Gigabit Ethernet

Serial ATA™ (SATA)

USB 2.0

5.6

USB 3.0

5.7

5.8

5.9

SD Card

UART

High Definition Audio (HDA)

5.10 Digital Display Interface

5.11 LPC

5.12 SPI

5.13 I²C Bus

5.14 CAN Bus

5.15 Power Control

5.16 Power Management