RL78/G12

Self-Programming (Received Data via IIC) CC-RL

R01AN3025EJ0100

Rev. 1.00

Oct. 20, 2015

Introduction

This application note gives the outline of flash memory reprogramming using a self-programming technique. In this application note, flash memory is reprogrammed using the flash memory self-programming library Type01. The reprogramming data is received via IIC.

The sample program described in this application note limits the target of reprogramming to the boot area. For details on the procedures for performing self-programming and for reprogramming the entire area of code flash memory, refer to RL78/G13 Microcontroller Flash Memory Self-Programming Execution (R01AN0718E) Application Note.

Target Device

RL78/G12

When applying the sample program covered in this application note to another microcomputer, modify the program according to the specifications for the target microcomputer and conduct an extensive evaluation of the modified program.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 1 of 48

Contents

1.

Specifications ...................................................................................................................................... 4

1.1

Outline of the Flash Memory Self-Programming Library ......................................................................... 4

1.2

Code Flash Memory ............................................................................................................................. 5

1.3

Flash Memory Self-Programming ......................................................................................................... 7

1.3.1 Flash Memory Reprogramming ........................................................................................................ 8

1.3.2 Flash Shield Window ....................................................................................................................... 9

1.4

Operation Check Conditions ............................................................................................................... 10

1.5

How to Get the Flash Memory Self-Programming Library..................................................................... 10

2.

Related Application Notes .................................................................................................................. 11

3.

Description of the Hardware ............................................................................................................... 12

3.1

Hardware Configuration Example ....................................................................................................... 12

3.2

List of Pins to be Used ....................................................................................................................... 13

4.

Description of the Software ................................................................................................................ 14

4.1

Communication Specifications ............................................................................................................ 14

4.1.1 START Command ......................................................................................................................... 14

4.1.2 WRITE Command ......................................................................................................................... 14

4.1.3 END Command ............................................................................................................................. 14

4.1.4 Communication Sequence .............................................................................................................. 15

4.2

Operation Outline ............................................................................................................................ 16

4.3

File Configuration .............................................................................................................................. 19

4.4

List of Option Byte Settings ................................................................................................................ 20

4.5

Link Option ....................................................................................................................................... 21

4.6

List of Constants ................................................................................................................................ 22

4.7

List of Variables ................................................................................................................................ 23

4.8

List of Functions (Subroutines) ........................................................................................................... 23

4.9

Function Specifications ...................................................................................................................... 24

4.10

Flowcharts ........................................................................................................................................ 27

4.10.1 Initialization Function .................................................................................................................. 28

4.10.2 I/O Port Initial Setup .................................................................................................................... 29

4.10.3 CPU Clock Setup ......................................................................................................................... 30

4.10.4 Serial Interface (IICA) Initial Setup ............................................................................................... 31

4.10.5 Timer Array Unit 0 (TAU0) Initial Setup ....................................................................................... 32

4.10.6 Main Processing .......................................................................................................................... 33

4.10.7 LED blinking Start ....................................................................................................................... 35

4.10.8 TAU0 channel 0 operation start .................................................................................................... 35

4.10.9 TAU0 channel 0 operation stop ..................................................................................................... 36

4.10.10 TAU0 channel 0 interrupt ........................................................................................................... 36

4.10.11 IICA0 interrupt .......................................................................................................................... 37

4.10.12 Checking the Direction of Data Transfer via IICA0 ...................................................................... 37

4.10.13 Data Reception via IICA0 ........................................................................................................... 38

4.10.14 Clear IICA reception interrupt flag .............................................................................................. 41

4.10.15 Receive Packet Analysis ............................................................................................................. 42

4.10.16 Flash Memory Self-Programming Execution ................................................................................ 43

4.10.17 Flash Memory Self-Programming Initialization ............................................................................ 44

4.10.18 Flash Memory Reprogramming Execution ................................................................................... 46

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 2 of 48

5.

Sample Code ..................................................................................................................................... 48

6.

Documents for Reference ................................................................................................................... 48

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 3 of 48

1.

Specifications

This application note explains a sample program that performs flash memory reprogramming using a self-programming library.

The sample program reads values from the code flash memory area ranging from addresses 0x3BFC to 0x3BFF and sets the flashing period of the LEDs. Subsequently, the sample program receives data (4 bytes) from the sending side and carries out self-programming to rewrite the values stored in the code flash memory addresses 0x3BFC to 0x3BFF with the received data. When the rewrite is completed, the sample program reads values from the code flash memory addresses 0x3BFC to 0x3BFF again and resets the flashing period of the LEDs with the read value.

Table 1.1 lists the peripheral functions to be used and their uses.

Table 1.1 Peripheral Functions to be Used and their Uses

Peripheral Function

Serial interface IICA

Port I/O

Receives data via IIC.

Displays text on the LCD.

Turns on and off the LED.

Use

1.1

Outline of the Flash Memory Self-Programming Library

The flash memory self-programming library is a software product that is used to reprogram the data in the code flash memory using the firmware installed on the RL78 microcontroller.

The contents of the code flash memory can be reprogrammed by calling the flash memory self-programming library from a user program.

To do flash memory self-programming, it is necessary for the user program to perform initialization for flash memory self -programming and to execute the C or assembler functions that correspond to the library functions to be used.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 4 of 48

1.2

Code Flash Memory

The configuration of the RL78/G12 (R5F1026A) code flash memory is shown below.

03FFFH

Program area

00FFFH

000CEH

000CDH

000C4H

000C3H

000C0H

000BFH

00080H

0007FH

00000H

On-chip debug security ID area

10 bytes

Option byte area

4 bytes

CALLTtable area

64 bytes

Vector table area

128 bytes

Boot cluster 0

Figure 1.1 Code Flash Memory Configuration

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 5 of 48

The features of the RL78/G12 code flash memory are summarized below.

Table 1.2 Features of the Code Flash Memory

Minimum unit of erasure and verification

Item Description

1 block (1024 bytes)

Minimum unit of programming

Security functions

1 word (4 bytes)

Block erasure, programming, and boot area reprogramming protection are supported.

(They are enabled at shipment)

It is possible to disable reprogramming and erasure outside the specified window only at flash memory self-programming time using the flash shield window.

Security settings programmable using the flash memory self-programming library

Caution: The boot area reprogramming protection setting and the security settings for outside the flash shield window are disabled during flash memory self-programming.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 6 of 48

1.3

Flash Memory Self-Programming

The RL78/G12 is provided with a library for flash memory self-programming. Flash memory self-programming is accomplished by calling functions of the flash memory self-programming library from the reprogramming program.

The code flash memory cannot be referenced while flash memory self-programming is in progress. When the user program needs to be run, it is necessary to relocate part of the segments for the flash memory self-programming library and the reprogramming program in RAM when erasing or reprogramming the code flash memory or making settings for the security flags.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 7 of 48

1.3.1 Flash Memory Reprogramming

This subsection describes the outline image of reprogramming using the flash memory self-programming technique.

The program that performs flash memory self-programming is placed in boot cluster 0.

The sample program covered in this application note limits the target of reprogramming to the boot area. For details on the procedures for perform self-programming and for reprogramming the entire area of code flash memory, refer to

RL78/G13 Microcontroller Flash Memory Self-Programming Execution (R01AN0718E) Application Note.

(1) Erasing the block to be reprogrammed

03FFFH

User program

01000H

00FFFH

00000H

Erase

Boot program

(2) Writing and verifying the block to be reprogrammed

03FFFH

User program

Boot cluster 0

01000H

00FFFH

00000H write

Boot program

Boot cluster 0

(3) Repeat the cycle of erasing, writing, and verifying the block up to the last block.

03FFFH

New user program

01000H

00FFFH

00000H

Boot program

Boot cluster 0

Figure 1.2 Outline of Flash Memory Reprogramming (1/2)

RL78/G12 does not have the boot swap function. Do not make factors that prevent reprogramming, such as shutting down of the power supply or external reset signal, while the boot area is being updated. If reprogramming is prevented on the way, restarting the program by reset or reprogramming may be unavailable ever because of its broken data.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 8 of 48

1.3.2 Flash Shield Window

The flash shield window is one of security mechanisms used for flash memory self-programming. It disables the write and erase operations on the areas outside the designated window only during flash memory self-programming.

The figure below shows the outline image of the flash shield window on the area of which the start block is 08H and the end block is 1FH.

03FFFH

02C00H

02BFFH

01000H

00FFFH

00000H

Block 0FH

・

・

Block 0AH (end block)・

・

Block 04H (start block)

Bloc 03H

・

・

Block 00H

Flash shield range

(programming disabled)

Window range

(programming enabled)

Flash shield range

(programming disabled)

Figure 1.3 Outline of the Flash Shield Window

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 9 of 48

1.4

Operation Check Conditions

The sample code described in this application note has been checked under the conditions listed in the table below.

Table 1.3 Operation Check Conditions

Item Description

Microcontroller used RL78/G12 (R5F1026A)

Operating frequency

Operating voltage

 High-speed on-chip oscillator (HOCO) clock: 32 MHz

 CPU/peripheral hardware clock: 32 MHz

5.0 V (Operation is possible over a voltage range of 2.9 V to 5.5 V.)

Integrated development environment

(CS+)

LVD operation (V

LVD

): Reset mode which uses 2.81 V (2.76 V to 2.87

V)

CS+ for CC V3.01.00 from Renesas Electronics Corp.

Assembler (CS+)

Integrated development environment (e 2 studio)

Assembler (e

2

studio)

Board to be used

Flash memory self-programming library

(Type, Ver)

CC-RL V1.01.00 from Renesas Electronics Corp. e 2 studio V4.0.2.008 from Renesas Electronics Corp.

CC-RL V1.01.00 from Renesas Electronics Corp.

RL78/G12 target board (QB-R5F1026A-TB)

FSLRL78 Type01, Ver 2.21 Note

Note: Use and evaluate the latest version.

1.5

How to Get the Flash Memory Self-Programming Library

The flash memory self-programming library can be obtained from the following URL: http://www.renesas.com/products/tools/flash_prom_programming/flash_libraries/index.jsp

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 10 of 48

2.

Related Application Notes

The application notes that are related to this application note are listed below for reference.

 RL78/G12 Initialization (R01AN2582E) Application Note

 RL78/G12 Serial Interface IICA (for Master Transmission/Reception) (R01AN2987E) Application Note

 RL78/G12 Serial Interface IICA (for Slave Transmission/Reception) (R01AN2988E) Application Note

 RL78/G13 Microcontroller Flash Memory Self-Programming Execution (R01AN0718E) Application Note.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 11 of 48

3.

Description of the Hardware

3.1

Hardware Configuration Example

Figure 3.1 shows an example of the hardware configuration used for this application note.

V

DD

For on-chip debugger

QB-R5F1026A-TB

V

DD

V

SS

RL78/G12

P40/TOOL

P13

P14

P60/SCLA0

P61/SDAA0

V

DD

V

DD

LED1

LED2

Sending side

(sending reprogramming

Data)

Figure3.1 Hardware Configuration

Cautions: 1. The purpose of this circuit is only to provide the connection outline and the circuit is simplified accordingly. When designing and implementing an actual circuit, provide proper pin treatment and make sure that the hardware's electrical specifications are met (connect the input-only ports separately to V

DD

or V

SS

via a resistor).

must be held at not lower than the reset release voltage (V

LVD

) that is specified as LVD.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 12 of 48

3.2

List of Pins to be Used

Table 3.1 lists pins to be used and their functions.

Pin name

Table 3.1 Pins to be Used and their Functions

I/O Function

P60

P61

Input/Output IICA0 serial clock I/O pin

Input/Output IICA0 serial data transmission/reception pin

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 13 of 48

4.

Description of the Software

4.1

Communication Specifications

The sample program covered in this application note receives data via the IIC bus for flash memory self-programming. The sending side sends three commands, i.e., the START, WRITE, and END commands. The sample program takes actions according to the command it received. If the command terminates normally, the sample program releases the IIC bus from the wait state and receives the next command. If the command terminates abnormally, the sample program turns on LED1 and LED2 with the IIC bus placed in the wait state and suppresses the execution of the subsequent operations. This section describes the necessary IIC communication settings and the specifications for the commands.

Table 4.1 IIC Communication Settings

Local address

Operation mode

0xA0

Standard (100 KHz)

4.1.1 START Command

When the sample program receives the START command, it places the IIC bus in the wait state and performs initialization processing for flash memory self-programming. When the command terminates normally, the program releases the IIC bus from the wait state. In the case of an abnormal termination, the sample program displays

"ERROR!" on the LCD and suppresses the execution of the subsequent operations.

START code

(0x01)

Data length

(0x0002)

Command

(0x02)

Data

(None)

Checksum

(1 byte)

4.1.2 WRITE Command

When the sample program receives the WRITE command, it places the IIC bus in the wait state, writes the data it received into flash memory, and performs verify processing each time it completes the write of one block. The sample program releases the IIC bus from the wait state on normal termination of the command. In the case of an abnormal termination, the sample program displays "ERROR!" on the LCD and suppresses the execution of the subsequent operations.

START code

(0x01)

Data length

(0x0102)

Command

(0x03)

Data

(256 bytes)

Checksum

(1 byte)

4.1.3 END Command

When the sample program receives the END command, it places the IIC bus in the wait state and performs verify processing on the block that is currently being written. If the verification terminates normally, the program inverts the state of the boot flag, then generates a reset for boot swapping. In the case of an abnormal termination, the sample program displays "ERROR!" on the LCD and suppresses the execution of the subsequent operations.

START code

(0x01)

Data length

(0x0002)

Command

(0x04)

* The checksum is the sum of the command and data fields in units of bytes.

Data

(None)

Checksum

(1 byte)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 14 of 48

4.1.4 Communication Sequence

This sample program takes actions according to the sequence described below upon receipt of a command from the sending side.

(1) Sending side:

Sends the START command.

(2) Sample program:

Places the IIC bus in the wait state and turns on LED1 which indicates that flash memory is being accessed. The program then performs initialization for flash memory self-programming and releases the IIC bus from the wait state upon normal termination.

(3) Sending side:

Sends the WRITE command and data (4 bytes).

(4) Sample program:

Places the IIC bus in the wait state and writes the data (4byte) it received into the code flash memory. The write address starts at 0x3BFC and ends at 0x3BFF. When all of these steps terminate normally, the sample program releases the IIC bus from the wait state.

(5) Sending side:

(6) Sample program:

Performs verify processing on the block that is currently subjected to reprogramming with the IIC bus placed in the wait state and turns off LED2 to indicate that flash memory is not being accessed.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 15 of 48

4.2

Operation Outline

This application note explains a sample program that performs flash memory reprogramming using a self-programming library.

The sample program reads values from the code flash memory addresses 0x3BFC to 0x3BFF and sets the flashing interval of LED1 with the read value. Subsequently, the program receives data (4 bytes) from the sending side and carries out self-programming to rewrite the values that are stored in code flash memory addresses

0x3BFC to 0x3BFF with the received data. When reprogramming is completed, the sample program reads again the values that are stored in code flash memory addresses 0x3BFC to 0x3BFF and sets the flashing interval of

LED1 with the read value.

LED1 flashes at the interval that is equal to the average value of the data (4 bytes) received from the sending side (sum of byte values stored in code flash memory addresses 0x3BFC to 0x3BFF divided by 4)

 10 [ms]. For example, if address 0x3BFC contains a value of "15," address 0x3BFD contains "150," address 0x3BFE contains

"100," and address 0x3BFF contains "200," according to the calculation (15 + 150 + 100 + 200) / 4 * 10 = 1162.5,

LED1 flashes at intervals of 1162.5 [ms].

LED2 indicates that flash memory is being accessed when it is on.

(1) Sets up the I/O port

<Setting conditions>

 LED on/off control ports (LED1 and LED2): Sets P13 and P14 for output.

(2) Sets up the serial interface IICA

<Setting conditions>

 Sets the operation mode to standard.

 Sets the transfer clock to 100 kHz.

 Sets the local address to 0xA0.

 Sets up interrupts so that an interrupt occurs on every ninth clock.

 Disables interrupt requests to be generated on detection of the stop condition.

 Sets the P60/KR4/SCLA0 pin as transfer clock I/O pin and the P61/KR5/SDAA0 pin as pin for data transmission/reception.

(3) Initializes the TAU0 channel 0

<Setting conditions>

 Sets operation clock 0 (CK00) of the TAU0 to 23.44 [KHz], operation clock 1 (CK01) to 24

[MHz], operation clock 2 (CK02) to 12 [MHz], and operation clock 3 (CK03) to 93.75 [KHz].







Sets the operation clock to operation clock 0 (CK00).

Enables only software trigger start as the start trigger.

Sets the operation mode to the interval timer mode in which no timer interrupt occurs at the beginning of counting.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 16 of 48

(5) Reads values from code flash memory addresses 0x3BFC to 0x3BFF, calculates an average of the values in addresses 0x3BFC to 0x3BFF, and turns on LED1.

(6) If the read values are greater than 0, sets the interval time of the TAU0 channel 0 to the average value of values in addresses 0x3BFC to 0x3BFF

 10 [ms] and starts the TAU0 channel 0.

(7) Enters the HALT mode and waits for data from the sending side. The program enters the HALT mode again if it returns from the HALT mode upon a TAU0 channel 0 interrupt request.

(8) Switches into the normal operation mode from the HALT mode upon an IICA transmission end interrupt request.

(10) Upon receipt of an address and transfer direction information from the sending side, places the

IIC bus in the wait state and checks the transfer direction.

 When the master sends data to the slave, it clears the receive end interrupt request flag and releases the IIC bus from the wait state.

 When the master receives data from the salve, it turns on LED1 and LED2 and suppresses the execution of the subsequent operations.

(11) If the LED is flashing, this is stopped by stopping the operation of channel 0 in TAU0.

(12) Upon receipt of a START command (0x02) from the sending side, places the IIC bus in the wait state and performs initialization for self-programming.

 Sets P14 to the low level to turn on LED2, indicating that flash memory is being accessed.

 Calls the FSL_Init function to initialize the flash memory self-programming environment and makes the following settings:

Voltage mode: Full-speed mode

CPU operating frequency: 24 [MHz]

Status check mode: Status check internal mode

 Calls the FSL_Open function to start flash memory self-programming (starting the flash memory environment).

 Calls the FSL_PrepareFunctions function to make available the flash memory functions (standard reprogramming functions) that are necessary for the RAM executive.

 Calls the FSL_GetFlashShieldWindow function to get the start and end blocks of the flash shield window.

 If the start block of the flash shield window is a block other than block 0 or if the end block is a block other than block 15, calls the FSL_SetFlashShieldWindow function to set the start block of the flash shield window to block 0 and the end block to block 15.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 17 of 48

(13) Releases the IIC bus from the wait state and notifies the sending side of the transmission-enabled state.

(14) Receives the WRITE command (0x03) and reprogramming data (4 bytes).

(15) Places the IIC bus in the wait state and computes the reprogramming target block from the write destination address.

(16) Calls the FSL_BlankCheck function to check whether the reprogramming target block has already been reprogrammed.

(17) If the reprogramming target block is reprogrammed, calls the FSL_Erase function to erase the reprogramming target block.

(18) Calls the FSL_Write function to write the received data at the write destination address.

(19) Releases the IIC bus from the wait state and notifies the sending side of the transmission-enabled state.

(20) Receives an END command (0x04).

(21) Calls the FSL_IVerify function to verify the reprogramming target block.

(22) Calls the FSL_IVerify function to verify the reprogramming target block.

(23) Releases the IIC bus from the wait state and notifies the sending side of the transmission-enabled state.

(24) Returns to step (4).

Caution When flash memory self-programming could not be terminated normally (error occurring during processing), the sample program turns on LED1 and LED2 and suppresses the execution of the subsequent operations.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 18 of 48

4.3

File Configuration

Table 4.2 shows the file structure. Flash Self-Programming Library (FSLRL78 Type01, Ver2.21) other than the file attached to, and then described the added files to the project.

File Name

Table 4.2 List of Additional Functions and Files

Outline Remarks r_init.asm Initial setting module

Setting the option byte main

SLEDBLINK

IINTTM00

IINTIICA0

SCHKDIRIICA0

SRECVIICA0

SCLRIICAFLAG

SPACKETANALYZE

SFSLEXECUTE

SFSLINIT

SFSLWRITEEXECUTE

Subroutine:

SINIPORT

SINICLK

SSTARTIICA0

SINITAU

SSTARTINTV0

SSTOPINTV0 opt.asm

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 19 of 48

4.4

List of Option Byte Settings

Table 5.3 summarizes the settings of the option bytes.

Table 4.3 Option Byte Settings

Address Setting

000C0H/010C0H 01101111B Disables the watchdog timer.

000C1H/010C1H

000C2H/010C2H

000C3H/010C3H

01111111B

11100000B

10000101B

HS mode, HOCO: 24MHz

Enables the on-chip debugger

Description

(Stops counting after the release from the reset status.)

LVD reset mode 2.81 V (2.76 V to 2.87 V)

The option bytes of the RL78/G12 comprise the user option bytes (000C0H to 000C2H) and on-chip debug option byte

(000C3H).

The option bytes are automatically referenced, and the specified settings are configured at power-on time or the reset is released.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 20 of 48

4.5

Link Option

The –start option, which is one of the link options, is provided for allocating the Flash Self-Programming Library

Type01 to a ROM area.

Use the –start option to specify all sections for which settings are required by the Flash Self-Programming Library

Type01.

Caution: For details on the link option procedures, refer to RL78 Compiler CC-RL User’s Manual (R20UT3123E).

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 21 of 48

4.6

List of Constants

Table 4.4 lists constants for the sample program.

Constant Setting

Description

Table 4.4 Constants for the Sample Program

Constant Setting Description Constant Setting Description

Transfer speed in units of kbps (100 kbps (normal mode))

FHOCO

OPCLK

24

FHOCO/2

HOCO oscillation frequency in units of MHz (24 MHz)

IICA operation clock in units of MHz (12 MHz)

DIICWL

RISETIME

FALLTIME

WIDTHHIGH

DIICWH

( 47 * OPCLK + 9 )/10

100

100

5300 - (RISETIME +

FALLTIME)

(WIDTHHIGH * OPCLK +

999)/1000

Value set in IICWL0 register (57)

Signal rise time (100 ns)

Signal fall time (100 ns)

SCLA0 high-level width (5100 ns)

Value set in IICWH0 register (62)

BUFSIZE 9 Data buffer size

NORMAL_END 0x00

START_CMD 0x02 command

WRITE_CMD 0x03 command

FULL_SPEED_MOD

E

0x00 Argument to flash memory self-programming library initialization function: Set operation mode to full-speed mode.

FREQUENCY_24M 0x18 initialization function:

RL78/G12's operating frequency = 24 MHz

INTERNAL_MODE 0x01 initialization function: Turn on status check internal mode.

START_BLOCK_NU

M

0x00 Start block number of flash shield window

Note Change the target address in the range of 0x3800 to 0x3BFC.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 22 of 48

4.7

List of Variables

Table 4.5 shows the global variables.

Type

8 bits

 9 arrays

8 bits

 2 arrays

16 bits

8 bits

8 bits

8 bits

8 bits

8 bits

8 bits

8 bits

 8 arrays

Variable Name

RRCVBUF

Table 4.5 Global Variables

Buffer for data

Contents

RLEN

RRCVLG

Buffer for receiving the data length

Size of receive data

RINTIICFLAG IICA receive interrupt flag

RRECVSTATUS IICA receive status

RLENCOUNT Data length counter

RDATACOUNT Data counter

RRECVDATA 1 byte of received data

RREADAVE Average of the values in code flash memory at addresses 0x3BFC to

0x3BFF

RARG Array for use as FSL subroutine parameter

Function Used main

SRECVIICA0

SPACKETANALYZE

SRECVIICA0

SRECVIICA0

SPACKETANALYZE main,

IINTIICA0,

SCLRIICAFLAG

SRECVIICA0

SRECVIICA0

SRECVIICA0

SRECVIICA0 main,

SLEDBLINK

SFSLINIT,

SFSLWRITEEXECUT

E

4.8

List of Functions (Subroutines)

Table 4.6 summarizes the functions (subroutines).

Table 4.6 List of Functions (Subroutines)

SINIPORT

Function name

SSTARTIICA0

SINITAU

SLEDBLINK

SSTARTINTV0

SSTOPINTV0

IINTTM00

Outline

Makes initial settings of the ports.

Makes initial settings of IICA0 and puts it in communication standby state.

Makes initial settings of TAU.

Makes the LEDs flash.

Starts the timer counting operation of TAU0.

Stops the timer counting operation of TAU0.

Executes interrupt processing of TAU0.

SCHKDIRIICA0

SRECVIICA0

SCLRIICAFLAG

SPACKETANALYZE

SFSLEXECUTE

SFSLINIT

Checks direction of communication via IICA0.

Receives data via IICA0.

Clears IICA0 receive end interrupt flag and IICA0 receive error interrupt flag.

Analyzes receive data.

Executes flash memory self-programming.

Executes initialization for flash memory self-programming.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 23 of 48

4.9

Function Specifications

This section describes the specifications for the functions that are used in the sample program.

[Function Name] SINIPORT

Synopsis

Make initial settings of the I/O ports.

Explanation

This function sets P13 and P14 for output.

Arguments None

Return Value None

Remarks None

[Function Name] SSTARTIICA0

Synopsis

Explanation

Make initial settings of IICA0.

This function Initializes IICA0 to 0xA0 which is the slave address in the normal mode.

Arguments None

Return Value None

Remarks None

[Function Name] IINTIICA0

Synopsis

Explanation

Arguments None

Return Value

IICA0 interrupt processing

This function performs a routine which accepts and processes INTIICA0. Subroutine

SINTIICA0 processes communication.

None

Remarks None

[ Function Name ] SCHKDIRIICA0

Synopsis

Explanation

Check direction of data transfer via IICA0.

This function checks the direction in which data is being transferred.

Arguments None

Return Value C register

 Normal termination: NORMAL_END

 Transfer direction error (transfer direction is from slave to master): ERROR

Remarks None

[Function Name] SRECVIICA0

Synopsis

Receive data via IICA0.

Explanation

This function stores the receive data in the receive buffer (RRCVBUF) and the receive data length [bytes] in RRCVLG.

Arguments None

Return Value C register

 Normal termination: NORMAL_END



Abnormal termination: ERROR

Remarks None

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 24 of 48

[Function Name] SCLRIICAFLAG

Synopsis

Explanation

Clear IICA0 receive interrupt flag.

This function clears the IICA0 receive end interrupt flag (RINTIICFLAG).

Arguments None

Return Value None

Remarks None

[Function Name] SPACKETANALYZE

Synopsis

Analyze receive data.

Explanation

This function checks the parameters of the command received, and computes and compares the checksum to check whether the received data is correct.

Arguments None

Return Value C register



START command received: START_CMD

 WRITE command received: WRITE_CMD



END command received: END_CMD

 Abnormal termination: ERROR

Remarks None

[Function Name] SINITAU

Synopsis

Explanation

Make initial settings of TAU0.

This function makes initial settings of TAU0.

Arguments None

Return Value None

Remarks None

[Function Name] IINTTM00

Synopsis

Explanation

TAU0 channel 0 interrupt

This function inverts the state (ON/OFF) of LED1.

Arguments None

Return Value None

Remarks None

[Function Name] SSTARTINTV0

Synopsis

Explanation

Start TAU0 channel 0.

This function starts the TAU0 channel 0.

Arguments None

Return Value None

Remarks None

[ Function Name ] SSTOPINTV0

Synopsis

Explanation

Stop TAU0 channel 0.

This function stops the TAU0 channel 0.

Arguments None

Return Value None

Remarks None

[Function Name] SLEDBLINK

Synopsis

Explanation

Start LED flashing.

This function sets the LED1 flashing interval to the value of RREADAVE

 10 [ms]

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 25 of 48

and starts flashing LED1.

Arguments None

Return Value None

Remarks None

[ Function Name ] SFSLEXECUTE

Synopsis

Execute flash memory self-programming.

Explanation

This function executes flash memory self-programming.

Arguments None

Return Value C register

 Normal termination: FSL_OK

 Parameter error: FSL_ERR_PARAMETER

 Erase error: FSL_ERR_ERASE

 Internal verify error: FSL_ERR_IVERIFY

 Write error: FSL_ERR_WRITE

 Flow error: FSL_ERR_FLOW

Remarks None

[Function Name] SFSLINIT

Synopsis

Explanation

Execute initialization for flash memory self-programming.

This function executes initialization prior to flash memory self-programming.

Arguments None

Return Value A register

 Normal termination: FSL_OK

 Parameter error: FSL_ERR_PARAMETER

 Erase error: FSL_ERR_ERASE

 Internal verify error: FSL_ERR_IVERIFY

 Write error: FSL_ERR_WRITE

 Flow error: FSL_ERR_FLOW

Remarks None

[ Function Name ] SFSLWRITEEXECUTE

Synopsis

Execute flash memory reprogramming.

Explanation

This function executes flash memory reprogramming.

Arguments None

Return Value C register

 Normal termination: NORMAL_END

 Abnormal termination: ERROR

Remarks None

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 26 of 48

4.10

Flowcharts

Figure 4.1 shows the overall flow of the sample program described in this application note.

Start

CPU Initialization function

RESET_START

The option bytes are referenced before the initialization function is called.

End

Figure 4.1 Overall Flow

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 27 of 48

4.10.1 Initialization Function

Figure 4.2 shows the flowchart for the initialization function.

RESET_START

Set up ES register

Set up stack pointer

Set up stack redirection

Set up I/O ports

SINIPORT

ES register ← 00H (for table reference)

Secure 96H bytes as a stack area.

PIOR register ← 00H

P13 bit ← 1B

P14 bit ← 1B

P6 register ← 00H: Set output latch to 0

PM6 register ← FFH: Leave P60 and P61 as

Set up clock generation circuit

SINICLK

Set up TAU0

SINITAU

Serial interface (IICA) initial setup

SSTARTIICA0

Call main routine main

Select HOCO (24 MHz) as an operation clock.

HALT

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Figure 4.2 Initialization Function

Page 28 of 48

4.10.2 I/O Port Initial Setup

Figure 4.3 shows the flowchart for I/O port initial setup.

SINIPORT

Set pins which are alternative to analog input to digital-i/o.

ADPC register←00000001B

PMC register’s each bit ← 0B

Set up 13, P14 for output

Set ports except P61and P60 output mode

P1 register ← 18H

PMC1 register ← E0H

PM1 register ← E0H

Keep P61 (SDAA0) and P60 (SCLA0) input mode, and set each of the other ports output mode if it can be.

Set up unused port Note

RET

Figure 4.3 I/O Port Initial Setup

Note: Refer to the section entitled "Flowcharts" in RL78/G12 Initialization (R01AN2582E) Application Note for the configuration of the unused ports.

Caution: Provide proper treatment for unused pins so that their electrical specifications are observed. Connect each of any unused input-only ports to V

DD

or V

SS

via a separate resistor.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 29 of 48

4.10.3 CPU Clock Setup

Figure 4.4 shows the flowchart for CPU clock setup.

SINICLK

Set up high-speed system clock

CMC register ← 00H：

High-speed system clock: input port mode

MSTOP bit ← 1B

Set up Operation speed mode control register (OSMC)

WUTMMCK0 bit ← stop 1B: interval timer clock

Select CPU/peripheral hardware clock

(f

CLK

)

MCM0 bit ← 0B: choose HOCO clock (f

IH

) as the main system clock (f

MAIN

).

Select frequency of HOCO

HOCODIV2-0 bits ← 000B: Set 24MHz as HOCO frequency.

RET

Figure 4.4 CPU Clock Setup

Caution: For details on the procedure for setting up the CPU clock (R_CGC_Create ()), refer to the section entitled

"Flowcharts" in RL78/G12 Initialization (R01AN2582E) Application Note.

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 30 of 48

4.10.4 Serial Interface (IICA) Initial Setup

Figure 4.5 shows the flowchart for serial interface (IICA) setup.

SSTARTIICA0

Supply clock signals to IICA0

IICA0EN bit

 1B

Deactivate IICA0

Disable IICA0 interrupts

IICCTL00 register

IICE0 bit

 0B

IICAMK0 bit

 0B

IICAIF0 bit

 0B

Clear IICA0 interrupt request flag

Set up IICA0

 Operation mode: Standard mode

 Set IICA low-level width

 Set IICA high-level width

 Select f

CLK

/2 as operation clock

 Set local address to A0H

 Allow generation of a start condition without detecting stop condition after enabling operation (IICE0 = 1)

 Disable communication reservation function

 Prevent interrupt request from being generated by stop condition detection

 Generate interrupt request upon falling edge of ninth clock signal

 Enable acknowledgment

Pull data line low during duration of ninth clock signal

IICCTL01 register

SMC0 bit

 0B

IICWL0 register

 39H

IICWH0 register

 3EH

IICCTL01 register

PRS0 bit

 1B

SVA0 register

 A0H

IICF0 register

STCEN0 bit

 1B

IICRSV0 bit

 1B

IICCTL00 register

SPIE0 bit

 0B

WTIM0 bit

 1B

ACKE0 bit

 1B

Enable IICA0 interrupts

IICAMK0 bit

 0

Enable IICA0

Release data line and clock line

Set up IICA0 pin

IICCTL00 register

IICE0 bit

 1

IICCTL00 register

LREL0 bit

 1

PM6 register

PM60 bit

 0

PM61 bit

 0

RET

Figure 4.5 Serial Interface (IICA) Initial Setup

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 31 of 48

4.10.5 Timer Array Unit 0 (TAU0) Initial Setup

Figure 4.6 shows the flowchart for timer array unit 0 (TAU0) initial setup.

SINITAU

Supply clock to TAU0

TAU0EN bit ← 1B：start supplying clock.

Operation clock setting for TAU0

Operation clock 0(CK00)：23.44KHz

Operation clock 1(CK01)：24MHz

Operation clock 2(CK02)：12MHz

Operation clock 3(CK03)：93.75KHz

TPS0 register ← 000AH

Disable TAU0 channel 0

TT00 bit ← 1B：Stop operation of TAU0 channel 0

Disable interrupts of all channels of

TAU0

Clear interrupt request flags of all channels of TAU0

TMMK0n bit ← 1B

TMMK01H bit ← 1B

TMMK03H bit ← 1B n: 0-1

TMIF0n bit ← 1B

TMIF01H bit ← 1B

TMIF03H bit ← 1B n: 0-1

Operation setup for TAU0 channel 0

- Operation clock: CK00

- Trigger: software trigger

- Operation mode: interval timer

- Interval timer: 2.55s

- No interrupt when count starts.

TMR00 register ← 0000H

TDR00 register ←E975H

TO0 register

TO00 bit ← 0B

TOE0 register

TOE00 bit ← 0B

RET

Figure 4.6 Timer Array Unit 0 (TAU0) Initial Setup

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 32 of 48

4.10.6 Main Processing

Figure 4.7 shows the flowchart for main processing (1/2). Figure 4.8 shows the flowchart for main processing (2/2).

B main

Disable Interrupt

Clear data buffer

Clear IICA reception flag

SCLRIICAFLAG

IE←0

Initialize data buffer (RRCVBUF) to 00H

RINTIICFLAG ← 0

Enable Vector interrupt

Read data from Code flash (address

0x3BFC - 0x3BFF)

IE←1

Average read values light on LED1

RREADAVE ← average of values in address (0x3BFC -

0x3BFF)

P1.3 ← LED_ON

Average of read values from code flash >= 1

Yes

LED blinking start

SLEDBLINK

No (branch if RREADAVE=0)

TDR00 ← RREADAVE * 234

TAU0 channel 0 operation starts.

IIC0 reception complete interrupt is occurred?

Yes

Disenable vector interrupt

A

No (branch if RINTIICFLAG=0)

IE←0 switch to HALT mode

Resume from HALT by IIC reception interrupt request or TAU0 channel 0 interrupt request.

IIC reception complete interrupt sets

RINTIICFLAG "1"

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Figure 4.7 Main Processing (1/2)

Page 33 of 48

A

Check IICA0 data’s direction of transfer

SCHKDIRIICA0

Is the direction master → slave?

Yes

IICA0 data reception¥

SRECVIICA0

Clear IICA reception flag

SCLRIICAFLAG

C ← NORMAL_END / ERROR

No (branch if C is except NORMAL_END)

RRCVBUF ← receive data

RRCVLG ← length of receive data

C ← NORMAL_END / ERROR

RINTIICFLAG ← 0

LED is blinking?

Yes

TAU0 channel 0 operation stops

SSTOPINTV0

Data reception ends normally?

Yes analyze received packet

SPACKETANALYZE

No (branch if RREADAVE is 0)

No (branch if C is except

NORMAL_END)

C ←START_CMD / WRITE_CMD /

END_CMD / ERROR

No (branch if C is except

START_CMD)

START command reception?

Yes

Run Flash self programming

SFSLEXECUTE

C ← NORMAL_END /

Flash self programming ends normally?

Yes

B

No (branch if C is except

NORML_END)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Figure 4.8 Main Processing (2/2)

Light on LED1

Light on LED2

P1.3 ← LED_OFF

P1.4 ← LED_OFF

Page 34 of 48

4.10.7 LED blinking Start

Figure 4.9 shows the flowchart for starting LED blinking process.

SLEDBLINK

Set up interval time of TAU0 channel 0

TDR00 register ← RREADAVE * 234

TAU0 channel 0’s operation starts SSTARTINTV0

RET

Figure 4.9 LED blinking start

4.10.8 TAU0 channel 0 operation start

Figure 4.10 shows the flowchart for TAU0 channel 0 operation start process.

SSTARTINTV0

Clear interrupt request flag of

TAU0 channel 0

TMIF00 bit ← 0B

Enable interrupt of TAU0 channel 0

TMMK00 bit ← 0B

Start operation of TAU0 channel 0

TS0 register

TS00 bit ← 1B

RET

Figure 4.10 TAU0 channel 0 operation start

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 35 of 48

4.10.9 TAU0 channel 0 operation stop

Figure 4.11 shows the flowchart for TAU0 channel 0 operation stop process.

SSTOPINTV0

TAU0 channel 0 operation stop

TT00 bit ← 1B

Disable interrupt of TAU0 channel 0

TMMK00 bit ← 1B

Clear INTM00 interrupt request flag

TMIF00 bit ← 0B

RET

Figure 4.11 TAU0 channel 0 operation stop

4.10.10 TAU0 channel 0 interrupt

Figure 4.12 shows the flowchart of TAU0 channel 0 interrupt process.

IINTTM00

P1.3 ← P1.3 ^ 1

Invert the state of LED1.

RET

Figure 4.12 TAU0 channel 0 interrupt

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 36 of 48

4.10.11 IICA0 interrupt

Figure 4.13 shows the flowchart of IICA0 interrupt process.

IINTIICA0

Set the IICA0 reception complete

interrupt flag

RINTIICFLAG ← 1

RETI

Figure 4.13 IICA0 interrupt

4.10.12 Checking the Direction of Data Transfer via IICA0

Figure 4.14 shows the flowchart for checking the direction of data transfer via IICA0.

SCHKDIRIICA0

No (Branch if TRC0 bit is 1)

Is transfer direction in receive state?

Yes

Clear IICA transfer interrupt request flag IICAIF0 bit

 0 Set return value to normal termination

C

 ERROR

Release IIC bus from wait state

WREL0 bit

 1

Set return value to normal termination

C

 NORMAL_END return (ret)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Figure 4.14 Checking the Direction of Data Transfer via IICA0

Page 37 of 48

4.10.13 Data Reception via IICA0

Figure 4.15 shows the flowchart for data reception via the IICA0 (1/3). Figure4.16 shows the flowchart for data reception via the IICA0 (2/3). Figure 4.17 shows the flowchart for data reception via the IICA0 (3/3).

SRECVIICA0

Set return value to normal termination

C

 NORMAL_END

Initialize receive status to

NO_RECEIVE

Initialize data length receive counter

Initialize data receive counter

Initialize receive data length

RRECVSTATUS ← NO_RECEIVE

RLENCOUNT ← 0

RDATACOUNT ← 0

RRCVLG ← FFFFH

G

IICA0 transfer end interrupt request present?

Yes

Read receive data

No (Branch if IICAIF0 bit is set to 0)

RRECVDATA  IICA0 register

Receive status?

Branch according to value of rxstatus

D

NO_RECEIVE

Start code received?

No (Branch if rxdata is not

START_CODE)

Yes

Change receive status rxstatus

 START_CODE

Set return value to abnormal termination

C

 ERROR

E

Figure 4.15 Data Reception via IICA0 (1/3)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 38 of 48

D

START_CODE

Store receive data

RLEN[RLENCOUNT] ← RRECVDATA

Update counter

RLENCOUNT++

No (Branch if RLENCOUNT is not 2)

Data length reception complete?

Yes

Change receive status

RRECVSTATUS

 PACKET_SIZE

Store data length

RRCVLG ←

RLEN[0]<<8 | RLEN[1]

PACKET_SIZE

Store receive data

RRCVBUF [RDATACOUNT] ←

RRECVDATA

Update pointer and counter

RDATACOUNT ++ default

E

F

Figure 4.16 Data Reception via IICA0 (2/3)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 39 of 48

F

Clear transfer end interrupt request flag

IICAIF0 bit

 0

Except last byte?

Yes

Release IIC bus wait state

No (Branch if RDATACOUNT is RRCVLG)

WREL0 bit

 1

All data bytes received?

No (Branch if RDATACOUNT is not

RRCVLG and C is not ERROR).

Yes

RET

G

Figure 4.17 Data Reception via IICA0 (3/3)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 40 of 48

4.10.14 Clear IICA reception interrupt flag

Figure 5.18 shows the flowchart for clearing the IICA0 reception interrupt flag.

SCLRIICAFLAG

IICA0 reception end interrupt flag

RINTIICFLAG ← 0B

RET

Figure 4.18 Clearing the IICA0 reception interrupt flag

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 41 of 48

4.10.15 Receive Packet Analysis

Figure 4.19 shows the flowchart for receive packet analysis.

SPACKETANALYZE

Initialize loop counter

Initialize checksum

B ← 0

D ← RRCVLG

C ← 00H

No (branch if D != 0)

Checksum computation complete?

Yes

Add to checksum

C ← C + RRCVBUF [B]

Update loop count

B++

No (branch if RRCVBUF [B] != C)

Checksum match?

Yes

Set return value to received command

C ←RRCVBUF [0]

No (Branch if rxbuf[0] is not START, or not WRITE, or not END)

Received command normal?

Yes

Set return value to abnormal termination

C

 ERROR

RET

Figure 4.19 Receive Packet Analysis

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 42 of 48

4.10.16 Flash Memory Self-Programming Execution

Figure 4.20 shows the flowchart for flash memory self-programming execution.

SFSLEXECUTE

Turn on LED2

P1.4 ← LED_ON

Flash memory self-programming initialization

SFSLINIT

Initialization terminated normally?

Yes

A ← FSL_OK /

FSL_ERR_PARAMETER /

FSL_ERR_ERASE /

FSL_ERR_IVERIFY /

FSL_ERR_WRITE /

FSL_ERR_FLOW

No (Branch if C is not FSL_OK)

Execute data write

SFSLWRITEEXECUTE

C ← NORMAL_END / ERROR

Turn off LED2

P1.4 ← LED_OFF

RET

Figure 4.20 Flash Memory Self-Programming Execution

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 43 of 48

4.10.17 Flash Memory Self-Programming Initialization

Figure 4.21 shows the flowchart for flash memory self-programming initialization (1/2). Figure 4.22 shows the flowchart for flash memory self-programming initialization (2/2).

SFSLINIT

Set up arguments

HL ← #RARG

[HL+0] ← voltage mode: full speed mode

[HL+1] ← CPU operation frequency: 32[MHz]

[HL+2] ← status check mode : status check internal mode

DE ← HL

A ← FSL_OK / FSL_ERR_PARAMETER

Flash memory self-programming environment initialization

FSL_Init()

Initialization terminated normally?

No (Branch if A is not FSL_OK)

Yes

Declare start of flash memory self-programming

FSL_Open

Prepare for use of flash memory functions (standard reprogramming functions)

FSL_PrepareFunctions

Prepare for use of flash memory functions (extended functions)

FSL_PrepareExtFunctions

HL ← #RARG

Set up arguments

Get flash shield window start/end block numbers

FSL_GetFlashShieldWindow()

A ← FSL_OK / FSL_ERR_FLOW

Block number retrieval successful?

No (Branch if A is not FLS_OK)

Yes

H

Figure 4.21 Flash Memory Self-Programming Initialization (1/2)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

I

Page 44 of 48

H

All blocks programmable?

No (Branch if AX[0] is not START_BLOCK_NUM, or

AX[2] is not END_BLOCK_NUM.)

Yes

Set up arguments

HL ← #RARG

[HL+0] ←START_BLOCK_NUM

[HL+2] ←END_BLOCK_NUM

AX ← HL

Flash shield window setup

FSL_SetFlashShieldWindow

Set to:

Start block: 0

End block: 63

A

 FSL_OK / FSL_ERR_PARAMETER /

FSL_ERR_ERASE / FSL_ERR_IVERIFY /

FSL_ERR_WRITE / FSL_ERR_FLOW

I return (ret)

Figure 4.22 Flash Memory Self-Programming Initialization (2/2)

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 45 of 48

4.10.18 Flash Memory Reprogramming Execution

Figure 4.23 shows the flowchart for flash memory reprogramming execution (1/2). Figure 4.24 shows the flowchart for flash memory reprogramming execution (2/2).

SFSLWRITEEXECUTE

Release IICA0 bus wait state

IICA0 data reception

SRECVIICA0

Data reception successful?

Yes

Argument setting

WREL0 bit ← 1B

C ← NORMAL_END / ERROR

No (branch if C is not NORMAL_END)

AX ← WRITEBLOCK

Blank check on specified block

FSL_BlankCheck

A ← FSL_OK / FSL_ERR_PARAMTER

/

FSL_ERR_BLANKCHECK /

Blank check error OK?

No (branch if A is FSL_ERR_BLANKCHECK)

Yes

Argument setting

AX ← WRITEBLOCK

Erase specified block

FSL_Erase

A ← FSL_OK /

FSL_ERR_PARAMTER /

FSL_ERR_PROTECTION /

FSL_ERR_ERASE /

FSL ERR FLOW

No (branch if A is not FSL_OK) normal termination？

Yes

Receive packet analysis

SPACKETANALYZE

C ← START_CMD / WRITE_CMD /

END_CMD / ERROR

WRITE command received?

Yes

H

No (branch if C is not WRITE_CMD)

I

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Figure 4.23 Flash Memory Reprogramming Execution (1/2)

Page 46 of 48

H

Argument setting

Write to specified address

FSL_Write

I

Write to specified address successful?

Yes

Release IICA0 bus wait state

IICA0 data reception

SRECVIICA0 data reception terminate normally?

Yes

Receive packet analysis

SPACKETANALYZE

HL ← #RARG

[HL+0] ← RRCVBUF + 1

[HL+2] ← WRITEADDR

[HL+4] ← 0000H

[HL+6] ← WRITESIZE

AX ← HL

A ← FSL_OK /

FSL_ERR_PARAMTER /

FSL_ERR_PROTECTION /

FSL_ERR_WRITE /

FSL_ERR_FLOW

No (branch if A is not FSL_OK)

WREL0 bit ← 1B

C ← NORMAL END /

No (branch if C is not NORMAL_END)

C ← START_CMD / WRITE_CMD /

END_CMD / ERROR

No (branch if C is not END_CMD)

End command received?

Yes

Argument setting

AX ← WRITEBLOCK

Verify specified block

FSL_IVerify

A ← FSL_OK /

FSL_ERR_PARAMETER

/

FSL_ERR_IVERIFY /

No (branch if A is not FSL_OK) Verification successful?

Yes

Set return value to NORMAL

C ← NORMAL_END

Set return value to ERROR

C ← ERROR

Release IICA0 bus wait state

WREL0 bit ← 1B

RET

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Figure 4.24 Flash Memory Reprogramming Execution (2/2)

Page 47 of 48

5.

Sample Code

The sample code is available on the Renesas Electronics Website.

6.

Documents for Reference

RL78/G12 User's Manual: Hardware (R01UH0200E)

RL78 Family User's Manual: Software (R01US0015E)

(The latest versions of the documents are available on the Renesas Electronics Website.)

Technical Updates/Technical Brochures

(The latest versions of the documents are available on the Renesas Electronics Website.)

Website and Support

Renesas Electronics Website

 http://www.renesas.com/index.jsp

Inquiries

 http://www.renesas.com/contact/

R01AN3025EJ0100 Rev. 1.00

Oct. 20, 2015

Page 48 of 48

1.00

Revision Record

Rev. Date

Oct. 20, 2015

RL78/G12 Self-Programming (Received Data via IIC) CC-RL

—

Description

Page Summary

First edition issued

All trademarks and registered trademarks are the property of their respective owners.

A-1

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas.

For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Handling of Unused Pins

Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual.

¾ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

¾ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

¾ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become stable.

When switching the clock signal during program execution, wait until the target clock signal has stabilized.

¾ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal.

Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems.

¾ The characteristics of Microprocessing unit or Microcontroller unit products in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

Notice

1.

Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2.

Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3.

Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4.

You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5.

Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6.

You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7.

Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8.

Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

9.

Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3

Tel: +1-905-237-2004

Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-6503-0, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333

Tel: +86-21-2226-0888, Fax: +86-21-2226-0999

Renesas Electronics Hong Kong Limited

Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2265-6688, Fax: +852 2886-9022

Renesas Electronics Taiwan Co., Ltd.

13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300

Renesas Electronics Malaysia Sdn.Bhd.

Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics India Pvt. Ltd.

No.777C, 100 Feet Road, HALII Stage, Indiranagar, Bangalore, India

Tel: +91-80-67208700, Fax: +91-80-67208777

Renesas Electronics Korea Co., Ltd.

12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com

© 2015 Renesas Electronics Corporation. All rights reserved.

Colophon 5.0