RL78/G1F Datasheet - Renesas Electronics

RL78/G1F Datasheet - Renesas Electronics
Datasheet
R01DS0246EJ0100
Rev. 1.00
Apr 06, 2015
RL78/G1F
RENESAS MCU
1. OUTLINE
1.1
Features
Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 5.5 V which
can operate a 1.8 V device at a low voltage
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high speed (0.03125 s: @ 32 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (30.5
s: @ 32.768 kHz operation with subsystem clock)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register  8)  4 banks
• On-chip RAM: 5.5 KB
Event link controller (ELC)
• Event signals of 22 types can be linked to the specified
peripheral function.
Serial interfaces
•
•
•
•
CSI: 3 to 6 channels
UART/UART (LIN-bus supported): 3 channels
I2C/simplified I2C: 3 to 6 channels
IrDA: 1 channel
Timer
• 16-bit timer: 9 channels
(Timer Array Unit (TAU): 4 channels, Timer RJ: 1
channel, Timer RD: 2 channels (with PWMOPA),
Timer RG: 1 channel, Timer RX: 1 channel)
• 12-bit interval timer: 1 channel
• Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel (operable with the dedicated
low-speed on-chip oscillator)
Code flash memory
• Code flash memory: 32/64 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield
window function)
Data flash memory
• Data flash memory: 4 KB
• Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the
data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
• Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and
1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to
+85°C)
A/D converter
• 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
• Analog input: 8 to 17 channels
• Internal reference voltage (1.45 V) and temperature
sensor
D/A converter
•
•
•
•
8-bit resolution D/A converter (VDD = 1.6 to 5.5 V)
Analog output: 1 or 2 channels
Output voltage: 0 V to VDD
Real-time output function
Comparator
• 2 channels (pin selector is provided for 1 channel)
<R> • Incorporates a function for the output of a timer window
in combination with the timer array unit.
• The external reference voltage or internal reference
voltage can be selected as the reference voltage.
Programmable gain amplifier (PGA)
• 1 channel
I/O port
Operating ambient temperature
• TA = 40 to +85°C (A: Consumer applications)
• TA = 40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 14 levels)
Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
• I/O port: 20 to 58 (N-ch open drain I/O [withstand
voltage of 6 V]: 2 to 4, N-ch open drain I/O [VDD
withstand voltage/EVDD withstand voltage]: 10 to 16)
• Can be set to N-ch open drain, TTL input buffer, and onchip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5/3
V device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
Remark
The functions mounted depend on the
product. See 1.6 Outline of Functions.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 1 of 140
RL78/G1F
1. OUTLINE
ROM, RAM capacities
RL78/G1F
Flash ROM
64 KB
32 KB
Note
Data flash
4 KB
4 KB
RAM
24 pins
32 pins
36 pins
48 pins
64 pins
5.5 KB
Note
R5F11B7E
R5F11BBE
R5F11BCE
R5F11BGE
R5F11BLE
5.5 KB
Note
R5F11B7C
R5F11BBC
R5F11BCC
R5F11BGC
R5F11BLC
This is about 4.5 KB when performing self-programming and rewriting the data flash memory (For details, see CHAPTER
3 CPU ARCHITECTURE in the RL78/G1F User’s Manual).
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 2 of 140
RL78/G1F
1.2
1. OUTLINE
Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1F
Part No. R 5 F 1 1 B L E A x x x F B # 3 0
Packaging specification
#U0: Tray (HWQFN, WFLGA, FLGA)
#30: Tray (LFQFP, LQFP)
#W0: Embossed Tape (HWQFN, WFLGA, FLGA)
#50: Embossed Tape (LFQFP, LQFP)
Package type:
FP: LQFP, 0.80 mm pitch
FB: LFQFP, 0.50 mm pitch
NA:HWQFN, 0.50 mm pitch
LA: WFLGA, 0.50 mm pitch
ROM number (Omitted with blank products)
Fields of application:
A: Consumer applications, TA = -40 to +85C
G: Industrial applications, TA = -40 to +105C
ROM capacity:
C: 32 KB
E: 64 KB
Pin count:
7: 24-pin
B: 32-pin
C: 36-pin
G: 48-pin
L: 64-pin
RL78/G1F
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 3 of 140
RL78/G1F
Pin
count
24 pins
32 pins
36 pins
48 pins
64 pins
1. OUTLINE
Package
Caution
Ordering Part Number
24-pin plastic HWQFN
A
R5F11B7CANA#U0, R5F11B7EANA#U0, R5F11B7CANA#W0, R5F11B7EANA#W0
(4 × 4, 0.5 mm pitch)
G
R5F11B7CGNA#U0, R5F11B7EGNA#U0, R5F11B7CGNA#W0, R5F11B7EGNA#W0
32-pin plastic LQFP
A
R5F11BBCAFP#30, R5F11BBEAFP#30, R5F11BBCAFP#50, R5F11BBEAFP#50
(7 × 7, 0.8 mm pitch)
G
R5F11BBCGFP#30, R5F11BBEGFP#30, R5F11BBCGFP#50, R5F11BBEGFP#50
36-pin plastic WFLGA
A
R5F11BCCALA#U0, R5F11BCEALA#U0, R5F11BCCALA#W0, R5F11BCEALA#W0
(4 × 4 mm, 0.5 mm pitch)
G
R5F11BCCGLA#U0, R5F11BCEGLA#U0, R5F11BCCGLA#W0, R5F11BCEGLA#W0
48-pin plastic LFQFP
A
R5F11BGCAFB#30, R5F11BGEAFB#30, R5F11BGCAFB#50, R5F11BGEAFB#50
(7 × 7 mm, 0.5 mm pitch)
G
R5F11BGCGFB#30, R5F11BGEGFB#30, R5F11BGCGFB#50, R5F11BGEGFB#50
64-pin plastic LFQFP
A
R5F11BLCAFB#30, R5F11BLEAFB#30, R5F11BLCAFB#50, R5F11BLEAFB#50
G
R5F11BLCGFB#30, R5F11BLEGFB#30, R5F11BLCGFB#50, R5F11BLEGFB#50
(10 × 10 mm, 0.5 mm pitch)
Note
Fields of
ApplicationNote
For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1F.
The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 4 of 140
RL78/G1F
1.3
1. OUTLINE
Pin Configuration (Top View)
1.3.1
24-pin products
P147/ANI18/VCOUT1/IVREF0
P10/ANI20/SCK11/SCL11/TRDIOD1/(TxD2)
P11/ANI21/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/INTP5/VCOUT0
P13/TxD2/SO20/TRDIOA1/(TRDIOC0)/IrTxD/TI03/TO03
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)/IrRxD
• 24-pin plastic HWQFN (4  4 mm, 0.5 mm pitch)
exposed die pad
18 17 16 15 14 13
P22/ANI2/ANO0/PGA I/IVCMP0
P21/ANI1/AV REFM/IVCMP13
P20/ANI0/AV REFP/INTP11/IVCMP12
P01/ANI16/TO00/RxD1/TRG CL KB/TRJIO0/(IrRxD)/INTP10/SCLA0/IVCMP11
P00/ANI17/TI00/TxD1/TRG CL KA/(TRJO0)/(IrTxD)/INTP8/SDAA0/IVCMP10
P40/TOOL0
19
20
21
22
23
24
12
11
10
9
8
7
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRG IO B/(TRDIOD1)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRG IO A/(TRJO0)/(TRDIOC1)
P72/PCLBUZ0/INTP4/SCK00/SCL00/TRJO0/(TxD1)/(VCOUT1)
P73/INTP3/SSI00/(TRJIO0)/(RxD1)/(VCOUT0)
VDD
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
1 2 3 4 5 6
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 5 of 140
RL78/G1F
1.3.2
1. OUTLINE
32-pin products
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
1 2 3 4 5 6 7 8
P51/INTP2/SO00/TxD0/TOOLTxD/TRG IO B/(TRDIOD1)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRG IO A/(TRJO0)/(TRDIOC1)
P30/INTP3/SCK00/SCL00/TRJO0/(TRDIOB1)
P70/INTP6/(VCOUT1)
P72/INTP7/(TxD1)
P73/(RxD1)/(VCOUT0)
P74/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)/VCOUT1/SCLA0
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P147/ANI18/IVREF0
P23/ANI3/ANO1/PGA GND
P22/ANI2/ANO0/PGA I/IVCMP0
P21/ANI1/AV REFM/IVCMP13
P20/ANI0/AV REFP/INTP11/IVCMP12
P01/ANI16/TO00/RxD1/TRG CL KB/(TRJIO0)/INTP10/IVCMP11
P00/ANI17/TI00/TxD1/TRG CL KA/(TRJO0)/INTP8/IVCMP10
P120/ANI19/VCOUT0
P14/ANI24/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)/IrRxD
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/(RxD0)/(TRDIOA1)
P17/TI02/TO02/TRDIOA0/TRDCLK/(TxD0)/(TRDIOD0)
P10/ANI20/SCK11/SCL11/TRDIOD1/(TxD2)
P11/ANI21/SI11/SDA11/TRDIOC1
P12/ANI22/SO11/TRDIOB1
P13/ANI23/TxD2/SO20/TRDIOA1/IrTxD
• 32-pin plastic LQFP (7  7 mm, 0.8 mm pitch)
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 6 of 140
RL78/G1F
1. OUTLINE
1.3.3
36-pin products
• 36-pin plastic WFLGA (4 × 4 mm, 0.5 mm pitch)
Top View
Bottom View
6
5
4
3
2
1
A
B
C
D
E
F
F
E
D
C
B
A
INDEX MARK
A
6
5
B
C
D
F
EVDD0
VDD
P121/X1
P122/X2/EXCLK
P137/INTP0
P40/TOOL0
P61/SDAA0
P60/SCLA0
VSS
REGC
RESET
P124/XT2/
EXCLKS
5
P20/ANI0/
P21/ANI1/
P01/ANI16/TO00/ P123/XT1
AVREFP/IVCMP12/ AVREFM/IVCMP13 RxD1/TRGCLKB/
INTP11
TRJIO0/INTP10/
IVCMP11
4
4
P31/TI03/TO03/
P14/ANI24/RxD2/
INTP4/PCLBUZ0/ SI20/SDA20/
SSI00/(TRJIO0)/ TRDIOD0/
(SCLA0)/IrRxD
VCOUT1
3
P50/INTP1/SI00/
RxD0/TOOLRxD/
SDA00/TRGIOA/
(TRJO0)/
(TRDIOC1)
P70/INTP6/
(VCOUT0)/
(VCOUT1)
P15/PCLBUZ1/
SCK20/SCL20/
TRDIOB0/
(SDAA0)
2
P30/INTP3/
RTC1HZ/SCK00/
SCL00/TRJO0/
(TRDIOB1)
P16/TI01/TO01/
INTP5/TRDIOC0/
(RxD0)/
(TRDIOA1)
P12/ANI22/SO11/ P11/ANI21/SI11/
TRDIOB1
SDA11/TRDIOC1
1
E
P51/INTP2/SO00/ P17/TI02/TO02/
TxD0/TOOLTxD/ TRDIOA0/
P13/ANI23/TxD2/
SO20/TRDIOA1/
TRGIOB/
TRDCLK0/(TxD0)/ IrTxD
(TRDIOD1)
(TRDIOD0)
A
B
P23/ANI3/ANO1/
PGAGND
P10/ANI20/
SCK11/SCL11/
TRDIOD1/(TxD2)
C
D
P00/ANI17/TI00/
TxD1/TRGCLKA/
(TRJO0)/INTP8/
IVCMP10
P120/ANI19/
VCOUT0
P24/ANI4
P22/ANI2/ANO0/
PGAI/IVCMP0
P147/ANI18/
IVREF0
E
6
3
2
P25/ANI5
1
F
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make VDD pin the potential that is higher than EVDD0 pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
Remark 3. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD and EVDD0 pins.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 7 of 140
RL78/G1F
1.3.4
1. OUTLINE
48-pin products
P40/TOOL0
RESET
P124/XT2/EXCLK S
P26/ANI6
P27/ANI7
P24/ANI4
P25/ANI5
P22/ANI2/ANO0/PGA I/IVCMP0
P23/ANI3/ANO1/PGA GND
22
21
40
41
P123/XT1
P137/INTP0
P122/X2/EXCLK
42
43
44
P121/X1
REGC
45
46
VSS
VDD
47
48
20
19
18
17
16
P60/SCLA0
3 4 5 6
P61/SDAA0
P62/SSI00
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)/VCOUT1
1 2
Caution
P20/ANI0/AV REFP/IVCMP12/INTP11
P21/ANI1/AV REFM/IVCMP13
36 35 34 33 32 31 30 29 28 27 26 25
24
23
37
38
39
15
14
13
7 8 9 10 11 12
P147/ANI18/IVREF0
P146
P10/ANI20/SCK11/SCL11/TRDIOD1/(TxD2)
P11/ANI21/SI11/SDA11/TRDIOC1
P12/ANI22/SO11/TRDIOB1
P13/ANI23/TxD2/SO20/TRDIOA1/IrTxD
P14/ANI24/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)/IrRxD
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/(RxD0)/(TRDIOA1)
P17/TI02/TO02/TRDIOA0/TRDCLK/(TxD0)/(TRDIOD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRG IO B/(TRDIOD1)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRG IO A/(TRJO0)/(TRDIOC1)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/SI01/SDA01
P73/KR3/SO01/(RxD1)
P72/KR2/SO21/(TxD1)
P71/KR1/SI21/SDA21/(VCOUT0)
P70/KR0/SCK21/SCL21/(VCOUT1)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0/(TRDIOB1)
P120/ANI19/VCOUT0
P41/(TRJIO0)
P00/ANI17/TI00/TxD1/TRG CL KA/(TRJO0)/INTP8/IVCMP10
P01/ANI16/TO00/RxD1/TRG CL KB/TRJIO0/INTP10/IVCMP11
P130
P140/PCLBUZ0/INTP6
• 48-pin plastic LFQFP (7  7 mm, 0.5 mm pitch)
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
R01DS0246EJ0100 Rev. 1.00
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Page 8 of 140
RL78/G1F
1.3.5
1. OUTLINE
64-pin products
P147/ANI18/IVREF0
P146
P10/ANI20/SCK11/SCL11/TRDIOD1
P11/ANI21/SI11/SDA11/TRDIOC1
P12/ANI22/SO11/TRDIOB1/(INTP5)
P13/ANI23/TxD2/SO20/TRDIOA1/IrTxD
P14/ANI24/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)/IrRxD
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/(SI00)/(RxD0)/(TRDIOA1)
P17/TI02/TO02/TRDIOA0/TRDCLK/(SO00)/(TxD0)/(TRDIOD0)
P55/(PCLBUZ1)/(SCK00)/(INTP4)
P54/(INTP3)
P53/(INTP2)
P52/(INTP1)
P51/INTP2/SO00/TxD0/TOOLTxD/TRG IO B/(TRDIOD1)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRG IO A/(TRJO0)/(TRDIOC1)
• 64-pin plastic LFQFP (10  10 mm, 0.5 mm pitch)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
60
61
62
63
64
22
21
20
19
18
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0/(TRDIOB1)
P05/(INTP10)
P06/(INTP11)/(TRJIO0)
P70/KR0/SCK21/SCL21/(VCOUT1)
P71/KR1/SI21/SDA21/(VCOUT0)
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RxD2)
P77/KR7/INTP11/(TxD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)/VCOUT1
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
P120/ANI19/VCOUT0
P43/(INTP9)
P42/(INTP8)
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLK S
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EV SS0
VDD
EV DD0
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1/PGA GND
P22/ANI2/ANO0/PGA I/IVCMP0
P21/ANI1/AV REFM/IVCMP13
P20/ANI0/AV REFP/IVCMP12/(INTP11)
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10/IVCMP11
P02/ANI17/SO10/TxD1/IVCMP10
P01/TO00/TRG CL KB/TRJIO0/(INTP10)
P00/TI00/TRG CL KA/(TRJO0)/(INTP8)
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
Caution 1. Make EVSS0 pin the same potential as VSS pin.
Caution 2. Make VDD pin the potential that is higher than EVDD0 pin.
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the V SS and EV SS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
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Page 9 of 140
RL78/G1F
1.4
<R>
1. OUTLINE
Pin Identification
ANI0 to ANI7:
Analog input
PGAI:
PGA input
ANI16 to ANI24:
Analog input
PGAGND:
PGA input
ANO0, ANO1:
Analog output
RTC1HZ:
Real-time clock correction
AVREFM:
Analog reference voltage
clock (1 Hz) output
minus
RxD0 to RxD2:
Receive data
Analog reference voltage
SCK00, SCK01, SCK10:
Serial clock input/output
plus
SCK11, SCK20, SCK21:
Serial clock input/output
EVDD0:
Power supply for port
SCLA0:
Serial clock input/output
EVSS0:
Ground for port
SCL00, SCL01, SCL10, SCL11: Serial clock output
EXCLK:
External clock input
SCL20,SCL21:
Serial clock output
(main system clock)
SDAA0:
Serial data input/output
External clock input
SDA00, SDA01, SDA10:
Serial data input/output
(subsystem clock)
SDA11, SDA20, SDA21:
Serial data input/output
INTP0 to INTP11:
External interrupt input
SI00, SI01, SI10, SI11:
Serial data input
IrRxD:
Receive Data for IrDA
SI20, SI21:
Serial data input
IrTxD:
Transmit Data for IrDA
SO00, SO01, SO10:
Serial data output
IVCMP0:
Comparator 0 input
SO11, SO20, SO21:
Serial data output
AVREFP:
EXCLKS:
IVCMP10 to IVCMP13: Comparator 1 input /
IVREF0:
SSI00:
Serial interface chip select input
reference input
TI00 to TI03:
Timer input
Comparator 0 reference
TO00 to TO03:
Timer output
input
TRJO0:
Timer output
KR0 to KR7:
Key return
TOOL0:
Data input/output for tool
P00 to P06:
Port 0
TOOLRxD, TOOLTxD:
Data input/output for external device
P10 to P17:
Port 1
TRDCLK, TRGCLKA:
Timer external input clock
P20 to P27:
Port 2
TRGCLKB:
Timer external Input clock
P30, P31:
Port 3
TRDIOA0, TRDIOB0:
Timer input/output
P40 to P43:
Port 4
TRDIOC0, TRDIOD0:
Timer input/output
P50 to P55:
Port 5
TRDIOA1, TRDIOB1:
Timer input/output
P60 to P63:
Port 6
TRDIOC1, TRDIOD1:
Timer input/output
P70 to P77:
Port 7
TRGIOA, TRGIOB, TRJIO0:
Timer input/output
P120 to P124:
Port 12
TxD0 to TxD2:
Transmit data
P130, P137
Port 13
VCOUT0, VCOUT1:
Comparator output
P140, P141, P146,
Port 14
VDD:
Power supply
P147:
PCLBUZ0, PCLBUZ1:
VSS:
Ground
Programmable clock output/
X1, X2:
Crystal oscillator (main system clock)
buzzer output
XT1, XT2:
Crystal oscillator (subsystem clock)
REGC:
Regulator capacitance
RESET:
Reset
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Page 10 of 140
RL78/G1F
1. OUTLINE
1.5
Block Diagram
TIMER ARRAY
UNIT (4ch)
TI00
TO00
ch0
TI01/TO01
ch1
TI02/TO02
ch2
TI03/TO03
RxD0 (LINSEL)
ch3
2
TRGIOA,
TRGIOB
2
TRGCLKA,
TRGCLKB
TIMER RG
TRDIOA0/TRDCLK
TRDIOB0, TRDIOC0, TRDIOD0
3
PORT 0
7
P00 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
4
P40 to P43
PORT 5
6
P50 to P55
PORT 6
4
P60 to P63
PORT 7
8
P70 to P77
4
P120
P121 to P124
PWMOPA
TRJIO0
TRDIOA1 to TRDIOD1 1 4
TIMER RJ
TRJO00
TIMER RD (2ch)
WINDOW
WATCHDOG
TIMER
ch0
PORT 12
P130
PORT 13
ch1
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
PORT 14
P137
4
P140, P141,
P146, P147
TIMER RX
INTCMP1
SERIAL ARRAY
UNIT0 (4ch)
RxD0
TxD0
UART0
LINSEL
RxD1
TxD1
UART1
SCK00
SI00
SO00
SSI00
CSI00
SCK01
SI01
SO01
CSI01
SCK10
SI10
SO10
CSI10
SCK11
SI11
SO11
CSI11
SCL00
SDA00
IIC00
SCL01
SDA01
IIC01
SCL10
SDA10
IIC10
REAL-TIME
CLOCK
RTC1HZ
POWER ON RESET/
VOLTAGE
DETECTOR
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULTIPLYACCUMULATOR
RESET CONTROL
DATA FLASH MEMORY
ON-CHIP DEBUG
TOOL0
SYSTEM
CONTROL
RESET
X1
X2/EXCLK
HIGH-SPEED
ON-CHIP
OSCILLATOR
IIC11
VOLTAGE
REGULATOR
VDD,
VSS, TOOLRxD,
EVDD0 EVSS0 TOOLTxD
INTERRUPT
CONTROL
SDAA0
SERIAL
INTERFACE IICA0
SCLA0
A/D CONVERTER
RxD2/IrRxD
TxD2/IrTxD
SCK20
SI20
SO20
SCK21
SI21
SO21
2
CLOCK OUTPUT
CONTROL
PCLBUZ0,
PCLBUZ1
PROGRAMMABLE
GAIN AMPLIFIER
UART2 (IrDA)
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
SCL21
SDA21
IIC21
D/A CONVERTER
KR0 to KR7
RxD0 (LINSEL)
INTP0
11
INTP1 to
INTP11
8
ANI0 to ANI7
9
ANI16 to ANI24
PGAI
PGAGND
COMPARATOR0
VCOUT0
IVCMP0
IVREF0
COMPARATOR1
VCOUT1
IVCMP10
IVCMP11
IVCMP12
IVCMP13
CSI21
IIC20
8
COMPARATOR
(2ch)
CSI20
SCL20
SDA20
REGC
AVREFP
AVREFM
BUZZER OUTPUT
SERIAL ARRAY
UNIT1 (2ch)
XT1
XT2/EXCLKS
RAM
KEY RETURN
SCL11
SDA11
Remark
POR/LVD
CONTROL
ANO0
ANO1
Block diagram of 64-pin products is shown as an example. For difference of the block diagram other than 64-pin
products, refer to 1.6 Outline of Functions.
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Page 11 of 140
RL78/G1F
1.6
1. OUTLINE
Outline of Functions
Caution
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H.
(1/2)
24-pin
32-pin
36-pin
48-pin
64-pin
R5F11B7x
(x = C, E)
R5F11BBx
(x = C, E)
R5F11BCx
(x = C, E)
R5F11BGx
(x = C, E)
R5F11BLx
(x = C, E)
Code flash memory (KB)
32, 64
32, 64
32, 64
32, 64
32, 64
Data flash memory (KB)
4
4
4
4
4
Item
RAM (KB)
5.5
Address space
Note
5.5
Note
5.5
Note
5.5
Note
5.5 Note
1 MB
Main system
High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (high-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 2.7 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 1.8 V)
High-speed on-chip
HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
oscillator clock (fIH)
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode:
1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
—
XT1 (crystal) oscillation, external subsystem clock input
(EXCLKS) 32.768 kHz
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits  32 registers (8 bits  8 registers  4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
—
Instruction set
I/O port
•
•
•
•
•
Total
CMOS I/O
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits  8 bits, 16 bits  16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits  16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
20
28
31
44
58
17
(N-ch O.D. output
[VDD withstand
voltage]: 10)
25
(N-ch O.D. output
[VDD withstand
voltage]: 12)
24
(N-ch O.D. output
[VDD withstand
voltage]: 10)
34
(N-ch O.D. output
[VDD withstand
voltage]: 12)
48
(N-ch O.D. output
[VDD withstand
voltage]: 12)
CMOS input
3
3
5
5
5
CMOS output
—
—
—
1
1
N-ch open-drain I/O (6
—
—
2
4
4
V tolerance)
Timer
16-bit timer
9 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels (with PWMOPA), Timer RX: 1 channel,
Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
1 channel
Timer output
Timer outputs:
Timer outputs:
13 channels
16 channels
PWM outputs:
PWM outputs:
8 channels
RTC output
9 channels
—
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note
This is about 4.5 KB when the self-programming function and data flash function are used (For details, see CHAPTER 3
in the RL78/G1F User’s Manual).
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Page 12 of 140
RL78/G1F
1. OUTLINE
(2/2)
Item
24-pin
32-pin
36-pin
48-pin
64-pin
R5F11B7x
(x = C, E)
R5F11BBx
(x = C, E)
R5F11BCx
(x = C, E)
R5F11BGx
(x = C, E)
R5F11BLx
(x = C, E)
2
2
2
2
2
17 channels
17 channels
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
8/10-bit resolution A/D converter
8 channels
8-bit D/A converter
1 channel
13 channels
15 channels
2 channels
Comparator
2 channels
Programmable gain amplifier (PGA)
1 channel
Serial interface
[24-pin, 32-pin, 36-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
[48-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C:2 channels
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[64-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
<R>
I2C bus
1 channel
1 channel
1 channel
1 channel
1 channel
Data transfer controller (DTC)
30 sources
32 sources
31 sources
32 sources
33 sources
21
21
21
22
22
Event link controller
(ELC)
Event input
9
10
10
10
10
Internal
25
25
25
25
25
External
9
11
10
12
13
—
—
—
6
8
Event trigger output
Vectored interrupt
sources
Key interrupt
Reset
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
1.51 ±0.04 V (TA = 40 to +85°C)
1.51 ±0.06 V (TA = 40 to +105°C)
• Power-down-reset: 1.50 ±0.04 V (TA = 40 to +85°C)
1.50 ±0.06 V (TA = 40 to +105°C)
Voltage detector
[TA = 40 to +85°C]
• Power-on-reset:
• Rising edge: 1.67 ±0.03 V to 4.00 ±0.08 V (14 stages)
• Falling edge: 1.63 ±0.03 V to 3.98 ±0.08 V (14 stages)
[TA = 40 to +105°C (G: Industrial applications)]
• Rising edge: 2.61 ±0.1 V to 4.06 ±0.16 V (8 stages)
• Falling edge: 2.55 ±0.1 V to 3.98 ±0.15 V (8 stages)
On-chip debug function
Power supply voltage
Provided
VDD = 1.6 to 5.5 V (TA = 40 to +85°C)
VDD = 2.4 to 5.5 V (TA = 40 to +105°C)
Operating ambient temperature
Note
TA = 40 to +85°C (A: Consumer applications), TA = 40 to +105°C (Industrial applications),
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
This chapter describes the following electrical specifications.
Target products A: Consumer applications TA = −40 to +85°C
R5F11BxxAxx
G: Industrial applications when TA = −40 to +105°C products is used in the range of TA = −40 to +85°C
R5F11BxxGxx
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. With products not provided with an EVDD0, EVSS0 pin, replace EVDD0 with VDD, or replace EVSS0 with
VSS.
Caution 3. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/G1F User’s Manual.
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Page 14 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Parameter
Supply voltage
(1/2)
Symbols
Conditions
VDD
EVDD0
REGC pin input voltage
VIREGC
REGC
Ratings
Unit
-0.5 to +6.5
V
-0.5 to +6.5
V
-0.3 to +2.8
V
and -0.3 to VDD +0.3 Note 1
Input voltage
Output voltage
Analog input voltage
VI1
P00 to P06, P10 to P17, P30, P31,
P40 to P43, P50 to P55, P70 to P77, P120,
P140, P141, P146, P147
VI2
P60 to P63 (N-ch open-drain)
VI3
P20 to P27, P121 to P124, P137,
EXCLK, EXCLKS, RESET
VO1
P00 to P06, P10 to P17, P30, P31,
P40 to P43, P50 to P55, P60 to P63,
P70 to P77, P120, P130, P140, P141,
P146, P147
VO2
P20 to P27
VAI1
ANI16 to ANI24
-0.3 to EVDD0 +0.3
and -0.3 to VDD +0.3
V
Note 2
-0.3 to +6.5
V
-0.3 to VDD +0.3 Note 2
V
-0.3 to EVDD0 +0.3
V
and -0.3 to VDD +0.3 Note 2
-0.3 to VDD +0.3 Note 2
-0.3 to EVDD0 +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3
VAI2
ANI0 to ANI7
-0.3 to VDD +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3
V
V
V
Note 1.
Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2.
Must be 6.5 V or lower.
Note 3.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
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Page 15 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Absolute Maximum Ratings
Parameter
Output current, high
(2/2)
Symbols
IOH1
IOH2
Conditions
Per pin
P00 to P06, P10 to P17, P30, P31, P40 to P43,
P50 to P55, P70 to P77, P120, P130, P140, P141,
P146, P147
Ratings
Unit
-40
mA
Total of all P00 to P04, P40 to P43,P120, P130, P140, P141
pins
P05, P06, P10 to P17, P30, P31, P50 to P55, P70
-170 mA
to P77, P146, P147
-70
mA
-100
mA
Per pin
-0.5
mA
-2
mA
P00 to P06, P10 to P17, P30, P31, P40-P43, P50
to P55, P60 to P63, P70 to P77, P120, P130,
P140, P141, P146, P147
40
mA
Total of all P00 to P04, P40 to P47, P120, P130, P140, P141
pins
P05, P06, P10 to P17, P30, P31, P50 to P55,
170 mA
P70 to P77, P146, P147
70
mA
100
mA
1
mA
5
mA
-40 to +85
C
-65 to +150
C
P20 to P27
Total of all
pins
Output current, low
IOL1
IOL2
Per pin
Per pin
P20 to P27
Total of all
pins
Operating ambient
temperature
TA
Storage temperature
Tstg
Caution
In normal operation mode
In flash memory programming mode
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Apr 06, 2015
Page 16 of 140
RL78/G1F
2.2
2.2.1
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Oscillator Characteristics
X1, XT1 characteristics
(TA = -40 to +85°C, 1.6 V  EVDD0 = VDD  5.5 V, VSS = 0 V)
Resonator
X1 clock oscillation frequency
Resonator
(fX) Note
XT1 clock oscillation frequency (fXT) Note
Ceramic resonator/
crystal resonator
Conditions
MIN.
MAX.
Unit
2.7 V VDD 5.5 V
1.0
20.0
MHz
2.4 V VDD <2.7 V
1.0
16.0
1.8 V VDD < 2.4 V
1.0
8.0
1.6 V VDD < 1.8 V
1.0
4.0
Crystal resonator
TYP.
32
32.768
35
kHz
Note
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution
Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark
2.2.2
When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G1F User’s Manual.
On-chip oscillator characteristics
(TA = -40 to +85°C, 1.6 V  EVDD0 = VDD  5.5 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator clock frequency fIH
Notes 1, 2
High-speed on-chip oscillator clock frequency
Conditions
MAX.
Unit
2.7 V VDD 5.5 V
1
32
MHz
2.4 V VDD <2.7 V
1
16
MHz
1.8 V VDD < 2.4 V
1
8
MHz
1.6 V VDD < 1.8 V
1
4
MHz
TA = -20 to +85°C 1.8 V  VDD  5.5 V
-1
1
%
1.6 V  VDD < 1.8 V
-5
5
%
1.8 V  VDD < 5.5 V
-1.5
1.5
%
1.6 V  VDD < 1.8 V
-5.5
accuracy
TA = -40 to -20°C
MIN.
Low-speed on-chip oscillator clock frequency fIL
Low-speed on-chip oscillator clock frequency
accuracy
TYP.
5.5
15
-15
%
kHz
+15
%
Note 1.
High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
Note 2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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Apr 06, 2015
Page 17 of 140
RL78/G1F
2.3
2.3.1
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
DC Characteristics
Pin characteristics
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Output current, high
Symbol
Note 1
IOH1
Conditions
(1/5)
MIN.
TYP.
Per pin for P00 to P06,
P10 to P17, P30, P31,
P40 to P47, P50 to P55,
P70 to P77, P120, P130, P140,
MAX.
Unit
-10.0
mA
Note 2
P141, P146, P147
Total of P00 to P04, P40 to P43,
P120, P130, P140, P141
(When duty  70% Note 3)
Total of P05, P06, P10 to P17,
P30, P31, P50 to P53,
P70 to P77, P146, P147
(When duty  70% Note 3)
4.0 V  EVDD0  5.5 V
-55.0
mA
2.7 V  EVDD0 < 4.0 V
-10.0
mA
1.8 V  EVDD0 < 2.7 V
-5.0
mA
1.6 V  EVDD0 < 1.8 V
-2.5
mA
4.0 V  EVDD0  5.5 V
-80.0
mA
2.7 V  EVDD0 < 4.0 V
-19.0
mA
1.8 V  EVDD0 < 2.7 V
-10.0
mA
1.6 V  EVDD0 < 1.8 V
-5.0
mA
Total of all pins
-135.0
(When duty  70% Note 3)
IOH2
Note 4
Per pin for P20 to P27
-0.1
mA
mA
Note 2
Total of all pins
1.6 V  VDD  5.5 V
-1.5
mA
(When duty  70% Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, VDD pins to an
output pin.
Note 2.
Do not exceed the total current value.
Note 3.
Specification under conditions where the duty factor  70%.
The output current value that has changed to the duty factor  70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example>
Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01)  -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Note 4.
Caution
The applied current for the products for industrial application (R5F11BxxGxx) is -100 mA.
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43, P50 to P55, P71, P74 do not output high level in N-ch opendrain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Apr 06, 2015
Page 18 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Output current, low Note 1
Symbol
IOL1
(2/5)
Conditions
MIN.
TYP.
Per pin for P00 to P06, P10 to
P17, P30, P31, P40 to P43, P50
to P55, P70 to P77,P120, P130,
P140, P141, P146, P147
MAX.
Unit
20.0
mA
Note 2
Per pin for P60 to P63
15.0
mA
Note 2
Total of P00 to P04, P40 to P43,
P120, P130, P140, P141
(When duty  70% Note 3)
Total of P05, P06, P10 to P17,
P30, P31, P50 to P55, P60 to
P63, P70 to P77, P146, P147
(When duty  70% Note 3)
4.0 V  EVDD0  5.5 V
70.0
mA
2.7 V  EVDD0 < 4.0 V
15.0
mA
1.8 V  EVDD0 < 2.7 V
9.0
mA
1.6 V  EVDD0 < 1.8 V
4.5
mA
4.0 V  EVDD0  5.5 V
80.0
mA
2.7 V  EVDD0 < 4.0 V
35.0
mA
1.8 V  EVDD0 < 2.7 V
20.0
mA
1.6 V  EVDD0 < 1.8 V
10.0
mA
150.0
mA
0.4
mA
Total of all pins
(When duty  70% Note 3)
IOL2
Per pin for P20 to P27
Note 2
Total of all pins
1.6 V  VDD  5.5 V
5.0
mA
(When duty  70% Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0 and
VSS pins.
Note 2.
Do not exceed the total current value.
Note 3.
Specification under conditions where the duty factor  70%.
The output current value that has changed to the duty factor  70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example>
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Input voltage, high
Input voltage, low
Caution
Symbol
Conditions
(3/5)
MIN.
Normal input buffer
TYP.
MAX.
Unit
0.8 EVDD0
EVDD0
V
VIH1
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55,
P70 to P77, P120, P140, P141,
P146, P147
VIH2
P01, P03, P04, P10, P14 to P17, TTL input buffer
P30, P43, P50, P53 to P55,
4.0 V  EVDD0  5.5 V
2.2
EVDD0
V
TTL input buffer
3.3 V  EVDD0 < 4.0 V
2.0
EVDD0
V
TTL input buffer
1.6 V  EVDD0 < 3.3 V
1.5
EVDD0
V
0.7 VDD
VDD
V
0.7 EVDD0
6.0
V
0.8 VDD
VDD
V
0
0.2 EVDD0
V
VIH3
P20 to P27 (when P20 is used as a port pin)
VIH4
P60 to P63
VIH5
P121 to P123, P137, EXCLK, EXCLKS, RESET (when
P20 is used as INTP11 pin)
VIL1
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55,
P70 to P77, P120, P140, P141,
P146, P147
VIL2
P01, P03, P04, P10, P14 to P17, TTL input buffer
P30, P43, P50, P53 to P55,
4.0 V  EVDD0  5.5 V
0
0.8
V
TTL input buffer
3.3 V  EVDD0 < 4.0 V
0
0.5
V
TTL input buffer
1.6 V  EVDD0 < 3.3 V
0
0.32
V
Normal input buffer
VIL3
P20 to P27 (when P20 is used as a port pin)
0
0.3 VDD
V
VIL4
P60 to P63
0
0.3 EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET (when
P20 is used as INTP11 pin)
0
0.2 VDD
V
The maximum value of VIH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43, P50 to P55, P71, P74 is
EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Apr 06, 2015
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Output voltage, high
Symbol
VOH1
Conditions
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55,
P70 to P77, P120, P130, P140,
P141, P146, P147
4.0 V  EVDD0  5.5 V,
(4/5)
MIN.
TYP.
MAX.
Unit
EVDD0 - 1.5
V
4.0 V  EVDD0  5.5 V,
IOH1 = -3.0 mA
EVDD0 - 0.7
V
2.7 V  EVDD0  5.5 V,
IOH1 = -2.0 mA
EVDD0 - 0.6
V
1.8 V  EVDD0  5.5 V,
IOH1 = -1.5 mA
EVDD0 - 0.5
V
1.6 V  EVDD0 < 1.8 V,
EVDD0 - 0.5
V
VDD - 0.5
V
IOH1 = -10.0 mA
IOH1 = -1.0 mA
Output voltage, low
Caution
VOH2
P20 to P27
1.6 V  VDD  5.5 V,
IOH2 = -100 A
VOL1
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55,
P70 to P77, P120, P130, P140,
P141, P146, P147
4.0 V  EVDD0  5.5 V,
1.3
V
4.0 V  EVDD0  5.5 V,
IOL1 = 8.5 mA
0.7
V
2.7 V  EVDD0  5.5 V,
IOL1 = 3.0 mA
0.6
V
2.7 V  EVDD0  5.5 V,
IOL1 = 1.5 mA
0.4
V
1.8 V  EVDD0  5.5 V,
IOL1 = 0.6 mA
0.4
V
1.6 V  EVDD0  5.5 V,
IOL1 = 0.3 mA
0.4
V
IOL1 = 20.0 mA
VOL2
P20 to P27
1.6 V  VDD  5.5 V,
IOL2 = 400 A
0.4
V
VOL3
P60 to P63
4.0 V  EVDD0  5.5 V,
IOL3 = 15.0 mA
2.0
V
4.0 V  EVDD0  5.5 V,
IOL3 = 5.0 mA
0.4
V
2.7 V  EVDD0  5.5 V,
IOL3 = 3.0 mA
0.4
V
1.8 V  EVDD0  5.5 V,
IOL3 = 2.0 mA
0.4
V
1.6 V  EVDD0  5.5 V,
IOL3 = 1.0 mA
0.4
V
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43, P50 to P55, P71, P74 do not output high level in N-ch opendrain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Apr 06, 2015
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Input leakage
current, high
Input leakage
current, low
On-chip pull-up
resistance
Remark
Symbol
(5/5)
Conditions
MIN.
TYP.
MAX.
Unit
ILIH1
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55, P70
to P77, P120, P140, P141, P146,
P147
VI = EVDD0
1
A
ILIH2
P20 to P27, P137, RESET
VI = VDD
1
A
ILIH3
P121 to P124
(X1, X2, EXCLK, XT1, XT2,
EXCLKS)
VI = VDD
In input port or
external clock
input
1
A
In resonator
connection
10
A
ILIL1
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55, P70
to P77, P120, P140, P141, P146,
P147
VI = EVSS0
-1
A
ILIL2
P20 to P27, P137, RESET
VI = VSS
-1
A
ILIL3
P121 to P124
(X1, X2, EXCLK, XT1, XT2,
EXCLKS)
VI = VSS
In input port or
external clock
input
-1
A
In resonator
connection
-10
A
100
k
RU
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55, P70
to P77, P120, P140, P141, P146,
P147
VI = EVSS0, In input port
10
20
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/G1F
2.3.2
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Supply current characteristics
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Supply
current
Symbol
IDD1
(1/2)
Conditions
Operating HS (high-speed main)
mode
mode Note 5
MIN.
fHOCO = 64 MHz,
fIH = 32 MHz Note 3
Basic
operation
TYP.
VDD = 5.0 V
2.4
VDD = 3.0 V
2.4
MAX.
Unit
mA
Note 1
fHOCO = 32 MHz,
fIH = 32 MHz Note 3
HS (high-speed main)
fHOCO = 64 MHz,
mode Note 5
fIH = 32 MHz Note 3
fHOCO = 32 MHz,
fIH = 32 MHz Note 3
fHOCO = 48 MHz,
fIH = 24 MHz Note 3
fHOCO = 24 MHz,
fIH = 24 MHz Note 3
fHOCO = 16 MHz,
fIH = 16 MHz Note 3
LS (low-speed main)
fHOCO = 8 MHz,
mode Note 5
fIH = 8 MHz Note 3
Basic
operation
VDD = 5.0 V
2.1
VDD = 3.0 V
2.1
Normal
operation
VDD = 5.0 V
5.2
8.7
VDD = 3.0 V
5.2
8.7
Normal
operation
VDD = 5.0 V
4.8
8.1
VDD = 3.0 V
4.8
8.1
Normal
operation
VDD = 5.0 V
4.1
6.9
VDD = 3.0 V
4.1
6.9
Normal
operation
VDD = 5.0 V
3.8
6.3
VDD = 3.0 V
3.8
6.3
Normal
operation
VDD = 5.0 V
2.8
4.6
VDD = 3.0 V
2.8
4.6
Normal
operation
VDD = 3.0 V
1.3
2.1
VDD = 2.0 V
1.3
2.1
VDD = 3.0 V
1.3
1.9
VDD = 2.0 V
1.3
1.9
LV (low-voltage main)
fHOCO = 4 MHz,
mode Note 5
fIH = 4 MHz Note 3
Normal
operation
HS (high-speed main)
fMX = 20 MHz Note 2,
VDD = 5.0 V
Normal
operation
Square wave input
3.3
5.3
Resonator connection
3.5
5.5
fMX = 20 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
3.3
5.3
Resonator connection
3.5
5.5
fMX = 10 MHz Note 2,
VDD = 5.0 V
Normal
operation
Square wave input
fMX = 10 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
fMX = 8 MHz Note 2,
VDD = 3.0 V
Normal
operation
fMX = 8 MHz Note 2,
VDD = 2.0 V
Normal
operation
mode Note 5
LS (low-speed main)
mode Note 5
Subsystem clock
operation
Resonator connection
2
3.1
2.1
3.2
2
3.1
2.1
3.2
Square wave input
1.2
1.9
Resonator connection
1.2
2
Square wave input
1.2
1.9
Resonator connection
1.2
2
Normal
operation
Square wave input
4.7
6.1
Resonator connection
4.7
6.1
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +25°C
Square wave input
4.7
6.1
Resonator connection
4.7
6.1
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +50°C
Square wave input
4.8
6.7
Resonator connection
4.8
6.7
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +70°C
Square wave input
4.8
7.5
Resonator connection
4.8
7.5
Normal
operation
Square wave input
5.4
8.9
Resonator connection
5.4
8.9
fSUB = 32.768 kHz
TA = -40°C
fSUB = 32.768 kHz
TA = +85°C
Note 4
Note 4
Resonator connection
mA
mA
mA
mA
mA
A
(Notes and Remarks are listed on the next page.)
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RL78/G1F
Note 1.
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3.
When high-speed system clock and subsystem clock are stopped.
Note 4.
When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog
timer.
Note 5.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V  VDD  5.5 [email protected] MHz to 32 MHz
LS (low-speed main) mode:
2.4 V  VDD  5.5 [email protected] MHz to 16 MHz
1.8 V  VDD  5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V  VDD  5.5 [email protected] MHz to 4 MHz
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply current IDD2
Note 1
(2/2)
Conditions
HALT mode
Note 2
TYP.
MAX.
Unit
HS (high-speed main) fHOCO = 64 MHz,
VDD = 5.0 V
MIN.
0.8
3.09
mA
mode Note 7
VDD = 3.0 V
0.8
3.09
fHOCO = 32 MHz,
VDD = 5.0 V
0.54
2.4
fIH = 32 MHz Note 4
VDD = 3.0 V
0.54
2.4
fHOCO = 48 MHz,
VDD = 5.0 V
0.62
2.4
fIH = 24 MHz Note 4
VDD = 3.0 V
0.62
2.4
fHOCO = 24 MHz,
VDD = 5.0 V
0.44
1.83
fIH = 24 MHz Note 4
VDD = 3.0 V
0.44
1.83
fHOCO = 16 MHz,
VDD = 5.0 V
0.4
1.38
fIH = 16 MHz Note 4
VDD = 3.0 V
0.4
1.38
LS (low-speed main)
fHOCO = 8 MHz,
VDD = 3.0 V
260
790
mode Note 7
fIH = 8 MHz Note 4
VDD = 2.0 V
260
790
LV (low-voltage main) fHOCO = 4 MHz,
VDD = 3.0 V
420
830
mode Note 7
VDD = 2.0 V
420
830
fIH = 32 MHz Note 4
fIH = 4 MHz Note 4
HS (high-speed main) fMX = 20 MHz Note 3,
VDD = 5.0 V
mode Note 7
fMX = 20 MHz Note 3,
VDD = 3.0 V
Square wave input
0.28
1.55
Resonator connection
0.49
1.74
0.86
0.3
0.93
Square wave input
0.19
0.86
Resonator connection
0.3
0.93
Square wave input
95
640
Resonator connection
145
680
Square wave input
95
640
Resonator connection
145
680
Square wave input
0.25
0.57
Resonator connection
0.44
0.76
fSUB = 32.768 kHz Note 5, Square wave input
TA = +25°C
Resonator connection
0.3
0.57
0.49
0.76
Square wave input
0.36
1.17
Resonator connection
0.59
1.36
fSUB = 32.768 kHz Note 5, Square wave input
TA = +70°C
Resonator connection
0.49
1.97
0.72
2.16
Square wave input
0.97
3.37
Resonator connection
1.16
3.56
TA = -40°C
0.18
0.51
TA = +25°C
0.24
0.51
TA = +50°C
0.29
1.1
TA = +70°C
0.41
1.9
TA = +85°C
0.9
3.3
mode Note 7
fMX = 8 MHz
VDD = 3.0 V
Note 3,
fMX = 8 MHz Note 3,
VDD = 2.0 V
Subsystem clock
operation
fSUB = 32.768 kHz
TA = -40°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
TA = +85°C
Note 8
1.74
0.19
LS (low-speed main)
Note 6
1.55
0.49
Square wave input
Note 3,
fMX = 10 MHz Note 3,
VDD = 3.0 V
STOP mode
0.28
Resonator connection
fMX = 10 MHz
VDD = 5.0 V
IDD3
Square wave input
Resonator connection
Note 5,
Note 5,
Note 5,
A
A
mA
A
A
A
(Notes and Remarks are listed on the next page.)
R01DS0246EJ0100 Rev. 1.00
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RL78/G1F
Note 1.
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2.
During HALT instruction execution by flash memory.
Note 3.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4.
When high-speed system clock and subsystem clock are stopped.
Note 5.
When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current
flowing into the 12-bit interval timer and watchdog timer.
Note 6.
Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
Note 7.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V  VDD  5.5 [email protected] MHz to 32 MHz
Note 8.
LS (low-speed main) mode:
2.4 V  VDD  5.5 [email protected] MHz to 16 MHz
1.8 V  VDD  5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V  VDD  5.5 [email protected] MHz to 4 MHz
Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 26 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Low-speed on-chip
oscillator operating current
IFIL Note 1
0.2
A
RTC operating current
IRTC Notes 1, 2, 3
0.02
A
12-bit interval timer
operating current
IIT Notes 1, 2, 4
0.02
A
Watchdog timer operating
current
IWDT Notes 1, 2, 5
fIL = 15 kHz
0.22
A
A/D converter operating
current
IADC Notes 1, 6
When conversion at maximum
speed
Normal mode,
AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode,
AVREFP = VDD = 3.0 V
0.5
0.7
mA
A/D converter reference
voltage current
IADREF Note 1
75
A
Temperature sensor
operating current
ITMPS Note 1
75
A
D/A converter operating
current
IDAC Notes 1, 11
PGA operating current
Comparator operating
current
Per D/A converter channel
1.5
mA
480
700
A
When the internal reference
voltage is not in use
50
100
A
When the internal reference
voltage is in use
60
110
A
Operation
ICMP Notes 1, 12
Operation (per comparator
channel, constant current for
comparator included)
A
LVD operating current
ILVD Notes 1, 7
0.08
Self-programming operating
current
IFSP Notes 1, 9
2.5
12.2
mA
BGO operating current
IBGO Notes 1, 8
2.5
12.2
mA
SNOOZE operating current
ISNOZ Note 1
The mode is performed Note 10
0.5
0.6
mA
The A/D conversion
operations are performed,
Low voltage mode,
AVREFP = VDD = 3.0 V
1.2
1.44
CSI/UART operation
0.7
0.84
DTC operation
3.1
ADC operation
Note 1.
Current flowing to VDD.
Note 2.
When high speed on-chip oscillator and high-speed system clock are stopped.
Note 3.
Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock.
Note 4.
Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 5.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in
operation.
Note 6.
Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7.
Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8.
Current flowing during programming of the data flash.
Note 9.
Current flowing during self-programming.
Note 10.
For shift time to the SNOOZE mode, see 26.3.3 SNOOZE mode in the RL78/G1F User’s Manual.
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Note 11.
Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDAC when the D/A converter operates in an operation mode or the HALT mode.
Note 12.
Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25°C
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2.4
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
AC Characteristics
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Instruction cycle
(minimum instruction
execution time)
Symbol
TCY
Conditions
Main system
clock (fMAIN)
MIN.
HS (high-speed main) 2.7 V  VDD  5.5 V
mode
2.4 V  VDD < 2.7 V
s
1
s
1
s
LV (low-voltage main) 1.6 V  VDD  5.5 V
mode
0.25
1
s
1.8 V  VDD  5.5 V
28.5
31.3
s
0.03125
1
s
0.0625
1
s
0.125
1
s
0.25
1
s
2.7 V  VDD  5.5 V
1.0
20.0
MHz
2.4 V  VDD  2.7 V
1.0
16.0
MHz
1.8 V  VDD < 2.4 V
1.0
8.0
MHz
1.6 V  VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
tEXH,
2.7 V  VDD  5.5 V
24
ns
tEXL
2.4 V  VDD  2.7 V
30
ns
1.8 V  VDD < 2.4 V
60
ns
1.6 V  VDD < 1.8 V
120
ns
13.7
s
1/fMCK + 10
ns
fEX
fEXS
tEXHS,
tEXLS
TI00 to TI03 input
high-level width, lowlevel width
tTIH, tTIL
Timer RJ input cycle
fC
Note
1
0.125
LV (low-voltage main) 1.8 V  VDD  5.5 V
mode
Timer RJ input highlevel width, low-level
width
0.03125
Unit
0.0625
LS (low-speed main)
mode
HS (high-speed main) 2.7 V  VDD  5.5 V
In the selfprogramming mode
2.4 V  VDD < 2.7 V
mode
LS (low-speed main) 1.8 V  VDD  5.5 V
mode
External system clock
input high-level width,
low-level width
TYP. MAX.
1.8 V  VDD  5.5 V
operation
Subsystem clock (fSUB) operation
External system clock
frequency
(1/2)
30.5
Note
tTJIH,
TRJIO
TRJIO
tTJIL
2.7 V  EVDD0  5.5 V
100
ns
1.8 V  EVDD0 < 2.7 V
300
ns
1.6 V  EVDD0 < 1.8 V
500
ns
2.7 V  EVDD0  5.5 V
40
ns
1.8 V  EVDD0 < 2.7 V
120
ns
1.6 V  EVDD0 < 1.8 V
200
ns
The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V  EVDD0 < 2.7 V: MIN. 125 ns
1.6 V  EVDD0 < 1.8 V: MIN. 250 ns
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel
number (n = 0 to 3))
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Symbol
Conditions
Timer RD input high-level
width, low-level width
tTDIH,
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1
Timer RD forced cutoff signal
input low-level width
tTDSIL
P130/INTP0
Timer RG input high-level
width, low-level width
TO00 to TO03,
TRJIO0, TRJO0,
tTGIH,
TRGIOA, TRGIOB
MIN.
TYP.
MAX.
Unit
3/fCLK
ns
1
s
1/fCLK + 1
2.5/fCLK
ns
tTGIL
fTO
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA, TRGIOB
output frequency
PCLBUZ0, PCLBUZ1 output
frequency
2MHz < fCLK  32 MHz
fCLK  2 MHz
(2/2)
fPCL
4.0 V  EVDD0  5.5 V
16
MHz
2.7 V  EVDD0 < 4.0 V
8
MHz
1.8 V  EVDD0 < 2.7 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
LS (low-speed main) mode
1.8 V  EVDD0  5.5 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
LV (low-voltage main) mode
1.6 V  EVDD0  5.5 V
2
MHz
HS (high-speed main) mode
4.0 V  EVDD0  5.5 V
16
MHz
2.7 V  EVDD0 < 4.0 V
8
MHz
1.8 V  EVDD0 < 2.7 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
1.8 V  EVDD0  5.5 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
HS (high-speed main) mode
LS (low-speed main) mode
LV (low-voltage main) mode
1.8 V  EVDD0  5.5 V
4
MHz
1.6 V  EVDD0 < 1.8 V
2
MHz
Interrupt input high-level
width, low-level width
tINTH,
INTP0
1.6 V  VDD  5.5 V
1
s
tINTL
INTP1 to INTP11
1.6 V  EVDD0  5.5 V
1
s
Key interrupt input low-level
width
tKR
KR0 to KR7
1.8 V  EVDD0  5.5 V
250
ns
1.6 V  EVDD0 < 1.8 V
1
s
RESET low-level width
tRSL
10
s
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [μs]
When the high-speed on-chip oscillator clock is selected
During self-programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
TCY vs VDD (LS (low-speed main) mode)
10
When the high-speed on-chip oscillator clock is selected
1.0
Cycle time TCY [μs]
During self-programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
3.0
5.0 5.5 6.0
4.0
Supply voltage VDD [V]
TCY vs VDD (LV (low-voltage main) mode)
10
Cycle time TCY [μs]
1.0
When the high-speed on-chip oscillator clock is selected
During self-programming
When high-speed system clock is selected
0.25
0.1
0.01
0
1.0
2.0
3.0
4.0
1.6 1.8
5.0
6.0
5.5
Supply voltage VDD [V]
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
AC Timing Test Points
V IH /V OH
V IH /V OH
Test points
V IL/V OL
V IL/V OL
External System Clock Timing
1/fEX
1/fEXS
tEXL
tEXLS
tEXH
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
tTIH
TI00 to TI03, TI10 to TI13
1/fTO
TO00 to TO03, TO10 to TO13,
TRJIO0, TRJO0,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA, TRGIOB
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
tTJIH
tTJIL
TRJIO
tTDIH
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1
tTDSIL
INTP0
tTGIL
tTGIH
TRGIOA, TRGIOB
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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2.5
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Peripheral Functions Characteristics
AC Timing Test Points
V IH /V OH
V IH /V OH
Test points
V IL/V OL
V IL/V OL
2.5.1
Serial array unit
(1) During communication at same potential (UART mode)
(TA = -40 to +85°C, 1.6 V  EVDD0  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
Transfer rate
Note 1
2.4 V  EVDD0  5.5 V
MAX.
LS (low-speed main)
Mode
MIN.
MAX.
LV (low-voltage main)
Unit
Mode
MIN.
MAX.
fMCK/6 Note 2
fMCK/6
fMCK/6
bps
5.3
1.3
0.6
Mbps
fMCK/6 Note 2
fMCK/6
fMCK/6
bps
5.3
1.3
0.6
Mbps
fMCK/6 Note 2
fMCK/6 Note 2
fMCK/6
bps
5.3
1.3
0.6
Mbps
—
fMCK/6 Note 2
fMCK/6
bps
—
1.3
0.6
Mbps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.8 V  EVDD0  5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.7 V  EVDD0  5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.6 V  EVDD0  5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
Note 1.
Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2.
The following conditions are required for low voltage interface when EVDD0  VDD.
2.4 V  EVDD0  2.7 V: MAX. 2.6 Mbps
1.8 V  EVDD0  2.4 V: MAX. 1.3 Mbps
1.6 V  EVDD0  1.8 V: MAX. 0.6 Mbps
Note 3.
Caution
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V  VDD  5.5 V)
LS (low-speed main) mode:
16 MHz (2.4 V  VDD  5.5 V)
8 MHz (1.8 V  VDD  5.5 V)
LV (low-voltage main) mode:
4 MHz (1.6 V  VDD  5.5 V)
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
UART mode connection diagram (during communication at same potential)
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remark 1. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) mode
MIN.
4.0 V  EVDD0  5.5 V
MAX.
LS (low-speed
main) mode
MIN.
LV (low-voltage
main) mode
MAX.
MIN.
Unit
MAX.
SCKp cycle time
tKCY1
tKCY1  2/fCLK
83.3
SCKp high-/low-level
width
tKH1,
tKL1
4.0 V  EVDD0  5.5 V
tKCY1/2 - 7
2.7 V  EVDD0  5.5 V
tKCY1/2 - 10
tKCY1/2 - 50
tKCY1/2 - 50
ns
SIp setup time (to SCKp↑)
tSIK1
4.0 V  EVDD0  5.5 V
23
110
110
ns
2.7 V  EVDD0  5.5 V
33
110
110
ns
tKSI1
2.7 V  EVDD0  5.5 V
10
10
10
ns
tKSO1
C = 20 pF Note 4
2.7 V  EVDD0  5.5 V
Note 1
SIp hold time (from
62.5
250
500
ns
250
500
ns
tKCY1/2 - 50
tKCY1/2 - 50
ns
SCKp↑) Note 2
Delay time from SCKp↓ to
10
10
10
ns
SOp output Note 3
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
Note 1.
Note 2.
Note 3.
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) mode
MIN.
SCKp cycle time
SCKp high-/low-level
width
SIp setup time
tKCY1
tKH1,
tKL1
tSIK1
(to SCKp↑) Note 1
SIp hold time
tKSI1
(from SCKp↑) Note 2
Delay time from
SCKp↓ to SOp output
Note 3
tKSO1
MAX.
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage
main) mode
MIN.
Unit
MAX.
2.7 V  EVDD0  5.5 V
125
500
1000
ns
2.4 V  EVDD0  5.5 V
250
500
1000
ns
1.8 V  EVDD0  5.5 V
500
500
1000
ns
1.7 V  EVDD0  5.5 V
1000
1000
1000
ns
1.6 V  EVDD0  5.5 V
—
1000
1000
ns
4.0 V  EVDD0  5.5 V
tKCY1/2 - 12
tKCY1/2 - 50
tKCY1/2 - 50
ns
2.7 V  EVDD0  5.5 V
tKCY1/2 - 18
tKCY1/2 - 50
tKCY1/2 - 50
ns
2.4 V  EVDD0  5.5 V
tKCY1/2 - 38
tKCY1/2 - 50
tKCY1/2 - 50
ns
1.8 V  EVDD0  5.5 V
tKCY1/2 - 50
tKCY1/2 - 50
tKCY1/2 - 50
ns
1.7 V  EVDD0  5.5 V
tKCY1/2 - 100
tKCY1/2 - 100
tKCY1/2 - 100
ns
1.6 V  EVDD0  5.5 V
—
tKCY1/2 - 100
tKCY1/2 - 100
ns
4.0 V  EVDD0  5.5 V
44
110
110
ns
2.7 V  EVDD0  5.5 V
44
110
110
ns
2.4 V  EVDD0  5.5 V
75
110
110
ns
1.8 V  EVDD0  5.5 V
110
110
110
ns
1.7 V  EVDD0  5.5 V
220
220
220
ns
1.6 V  EVDD0  5.5 V
—
220
220
ns
1.7 V  EVDD0  5.5 V
19
19
19
ns
1.6 V  EVDD0  5.5 V
—
19
19
ns
tKCY1  4/fCLK
1.7 V  EVDD0  5.5 V
C = 30 pF Note 4
25
25
25
ns
1.6 V  EVDD0  5.5 V
C = 30 pF Note 4
—
25
25
ns
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
Note 1.
Note 2.
Note 3.
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 , 5, 7)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
tKCY2
SCKp cycle
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
tKSI2
Note 2
Delay time
from SCKp↓ to
SOp output
tKSO2
Note 2.
Note 3.
Note 4.
Note 5.
Caution
MAX.
MIN.
Unit
MAX.
8/fMCK
—
—
ns
fMCK  20 MHz
6/fMCK
6/fMCK
ns
2.7 V  EVDD0  5.5 V 16 MHz  fMCK
8/fMCK
—
—
ns
6/fMCK
6/fMCK
6/fMCK
ns
2.4 V  EVDD0  5.5 V
6/fMCK
and 500
6/fMCK
and 500
6/fMCK
and 500
ns
1.8 V  EVDD0  5.5 V
6/fMCK
and 750
6/fMCK
and 750
6/fMCK
and 750
ns
1.7 V  EVDD0  5.5 V
6/fMCK
and 1500
6/fMCK
and 1500
6/fMCK
and 1500
ns
1.6 V  EVDD0  5.5 V
—
6/fMCK
and 1500
6/fMCK
and 1500
ns
4.0 V  EVDD0  5.5 V
tKCY2/2 - 7
tKCY2/2 - 7
tKCY2/2 - 7
ns
2.7 V  EVDD0  5.5 V
tKCY2/2 - 8
tKCY2/2 - 8
tKCY2/2 - 8
ns
1.8 V  EVDD0  5.5 V
tKCY2/2 - 18
tKCY2/2 - 18
tKCY2/2 - 18
ns
1.7 V  EVDD0  5.5 V
tKCY2/2 - 66
tKCY2/2 - 66
tKCY2/2 - 66
ns
1.6 V  EVDD0  5.5 V
—
tKCY2/2 - 66
tKCY2/2 - 66
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 20
1/fMCK + 30
1/fMCK + 30
ns
1.8 V  EVDD0  5.5 V
1/fMCK + 30
1/fMCK + 30
1/fMCK + 30
ns
1.7 V  EVDD0  5.5 V
1/fMCK + 40
1/fMCK + 40
1/fMCK + 40
ns
1.6 V  EVDD0  5.5 V
—
1/fMCK + 40
1/fMCK + 40
ns
1.8 V  EVDD0  5.5 V
1/fMCK + 31
1/fMCK + 31
1/fMCK + 31
ns
1.7 V  EVDD0  5.5 V
1/fMCK + 250
1/fMCK + 250
1/fMCK + 250
ns
1.6 V  EVDD0  5.5 V
—
C = 30 pF Note 4
Note 3
Note 1.
MIN.
LV (low-voltage main)
mode
6/fMCK
fMCK  16 MHz
tKH2,
tKL2
MAX.
LS (low-speed main)
mode
4.0 V  EVDD0  5.5 V 20 MHz  fMCK
time Note 5
SCKp high-/
low-level width
(1/2)
HS (high-speed main)
mode
1/fMCK + 250
1/fMCK + 250
ns
2.7 V  EVDD0  5.5 V
2/fMCK
+ 44
2/fMCK
+ 110
2/fMCK
+ 110
ns
2.4 V  EVDD0  5.5 V
2/fMCK
+ 75
2/fMCK
+ 110
2/fMCK
+ 110
ns
1.8 V  EVDD0  5.5 V
2/fMCK
+ 100
2/fMCK
+ 110
2/fMCK
+ 110
ns
1.7 V  EVDD0  5.5 V
2/fMCK
+ 220
2/fMCK
+ 220
2/fMCK
+ 220
ns
1.6 V  EVDD0  5.5 V
—
2/fMCK
+ 220
2/fMCK
+ 220
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output lines.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3, 5, 7)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
SSI00 setup time
SSI00 hold time
Caution
tSSIK
tKSSI
MAX.
(2/2)
LS (low-speed main)
mode
MIN.
LV (low-voltage main)
mode
MAX.
MIN.
Unit
MAX.
DAPmn = 0 2.7 V  EVDD0  5.5 V
120
120
120
ns
1.8 V  EVDD0  5.5 V
200
200
200
ns
1.7 V  EVDD0  5.5 V
400
400
400
ns
1.6 V  EVDD0  5.5 V
—
400
400
ns
DAPmn = 1 2.7 V  EVDD0  5.5 V
1/fMCK + 120
1/fMCK + 120
1/fMCK + 120
ns
1.8 V  EVDD0  5.5 V
1/fMCK + 200
1/fMCK + 200
1/fMCK + 200
ns
1.7 V  EVDD0  5.5 V
1/fMCK + 400
1/fMCK + 400
1/fMCK + 400
ns
1.6 V  EVDD0  5.5 V
—
1/fMCK + 400
1/fMCK + 400
ns
DAPmn = 0 2.7 V  EVDD0  5.5 V
1/fMCK + 120
1/fMCK + 120
1/fMCK + 120
ns
1.8 V  EVDD0  5.5 V
1/fMCK + 200
1/fMCK + 200
1/fMCK + 200
ns
1.7 V  EVDD0  5.5 V
1/fMCK + 400
1/fMCK + 400
1/fMCK + 400
ns
1.6 V  EVDD0  5.5 V
—
1/fMCK + 400
1/fMCK + 400
ns
DAPmn = 1 2.7 V  EVDD0  5.5 V
120
120
120
ns
1.8 V  EVDD0  5.5 V
200
200
200
ns
1.7 V  EVDD0  5.5 V
400
400
400
ns
1.6 V  EVDD0  5.5 V
—
400
400
ns
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78 microcontroller SIp
SOp
SCK
SO
User's device
SI
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
SCK00
SI00
RL78 microcontroller
SO00
SSI00
SCK
SO
User's device
SI
SSO
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
tKSSI
tSSIK
SSI00
(CSI00 only)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
tSSIK
tKSSI
SSI00
(CSI00 only)
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
HS (high-speed main)
mode
(1/2)
Parameter
Symbol
Conditions
SCLr clock frequency
fSCL
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
1000 Note 1
400 Note 1
400 Note 1
kHz
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
400 Note 1
400 Note 1
400 Note 1
kHz
1.8 V  EVDD0  2.7 V,
Cb = 100 pF, Rb = 5 k
300 Note 1
300 Note 1
300 Note 1
kHz
1.7 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
250 Note 1
250 Note 1
250 Note 1
kHz
1.6 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
—
250 Note 1
250 Note 1
kHz
MIN.
Hold time
when SCLr = “L”
Hold time
when SCLr = “H”
tLOW
tHIGH
MAX.
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
475
1150
1150
ns
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1150
1150
1150
ns
1.8 V  EVDD0  2.7 V,
Cb = 100 pF, Rb = 5 k
1550
1550
1550
ns
1.7 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
1850
1850
1850
ns
1.6 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
—
1850
1850
ns
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
475
1150
1150
ns
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1150
1150
1150
ns
1.8 V  EVDD0  2.7 V,
Cb = 100 pF, Rb = 5 k
1550
1550
1550
ns
1.7 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
1850
1850
1850
ns
1.6 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
—
1850
1850
ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
HS (high-speed main)
mode
Symbol
Conditions
tSU: DAT
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 85 Note 2
1/fMCK + 145 Note 2
1/fMCK + 145 Note 2
ns
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1/fMCK + 145 Note 2
1/fMCK + 145 Note 2
1/fMCK + 145 Note 2
ns
1.8 V  EVDD0  2.7 V,
Cb = 100 pF, Rb = 5 k
1/fMCK + 230 Note 2
1/fMCK + 230 Note 2
1/fMCK + 230 Note 2
ns
1.7 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
1/fMCK + 290 Note 2
1/fMCK + 290 Note 2
1/fMCK + 290 Note 2
ns
1.6 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
—
1/fMCK + 290 Note 2
1/fMCK + 290 Note 2
ns
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
0
305
0
305
0
305
ns
1.8 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
0
355
0
355
0
355
ns
1.8 V  EVDD0  2.7 V,
Cb = 100 pF, Rb = 5 k
0
405
0
405
0
405
ns
1.7 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
0
405
0
405
0
405
ns
0
405
0
405
ns
MIN.
Data setup time
(reception)
Data hold time
(transmission)
(2/2)
tHD: DAT
1.6 V  EVDD0  1.8 V,
Cb = 100 pF, Rb = 5 k
MAX.
LS (low-speed main)
mode
MIN.
—
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
Note 2.
The value must also be equal to or less than fMCK/4.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
Note 1.
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SDAr pin and the normal output mode for
the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDA
SDAr
RL78 microcontroller
User’s device
SCL
SCLr
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1, 3, 5, 7),
h: POM number (h = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10, 11)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
Transfer
rate
reception
4.0 V  EVDD0  5.5 V,
(1/2)
LS (low-speed main)
mode
MAX.
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
fMCK/6 Note 1
fMCK/6 Note 1
fMCK/6 Note 1
bps
5.3
1.3
0.6
Mbps
fMCK/6 Note 1
fMCK/6 Note 1
fMCK/6 Note 1
bps
5.3
1.3
0.6
Mbps
bps
2.7 V  Vb  4.0 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 4
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 4
1.8 V  EVDD0  3.3 V,
1.6 V  Vb  2.0 V
Theoretical value of the
maximum transfer rate
fMCK/6
fMCK/6
fMCK/6
Notes 1, 2, 3
Notes 1, 2
Notes 1, 2
5.3
1.3
0.6
Mbps
fMCK = fCLK Note 4
Note 1.
Note 2.
Note 3.
Note 4.
Caution
Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Use it with EVDD0  Vb.
The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V  EVDD0  2.7 V: MAX. 2.6 Mbps
1.8 V  EVDD0  2.4 V: MAX. 1.3 Mbps
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V  VDD  5.5 V)
16 MHz (2.4 V  VDD  5.5 V)
LS (low-speed main) mode:
8 MHz (1.8 V  VDD  5.5 V)
LV (low-voltage main) mode:
4 MHz (1.6 V  VDD  5.5 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remark 1. Vb [V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11)
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
Transfer
rate
transmission
4.0 V  EVDD0  5.5 V,
MAX.
(2/2)
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
Note 1
Note 1
Note 1
bps
2.8 Note 2
2.8 Note 2
2.8 Note 2
Mbps
Note 3
Note 3
Note 3
bps
1.2 Note 4
1.2 Note 4
1.2 Note 4
Mbps
Notes 5, 6
Notes 5, 6
Notes 5, 6
bps
0.43 Note 7
0.43 Note 7
0.43 Note 7
Mbps
2.7 V  Vb  4.0 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 1.4 k,
Vb = 2.7 V
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 k,
Vb = 2.3 V
1.8 V  EVDD0  3.3 V,
1.6 V  Vb  2.0 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 5.5 k,
Vb = 1.6 V
Note 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V  EVDD0  5.5 V and 2.7 V  Vb  4.0 V
1
Maximum transfer rate =
[bps]
2.2
{-Cb  Rb  In (1 )}  3
Vb
1
Transfer rate  2
- {-Cb  Rb  In (1 -
2.2
)}
Vb
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
Note 3.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.7 V  EVDD0 < 4.0 V and 2.3 V  Vb  2.7 V
1
[bps]
Maximum transfer rate =
{-Cb  Rb  In (1 -
2.0
)}  3
Vb
1
Transfer rate  2
- {-Cb  Rb  In (1 -
2.0
)}
Vb
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 4.
Note 5.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Use it with EVDD0  Vb.
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RL78/G1F
Note 6.
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 1.8 V  EVDD0 < 3.3 V and 1.6 V  Vb  2.0 V
1
[bps]
Maximum transfer rate =
{-Cb  Rb  In (1 -
1.5
)}  3
Vb
1
Transfer rate  2
- {-Cb  Rb  In (1 -
1.5
)}
Vb
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 7.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
Rx
TxDq
RL78 microcontroller
User’s device
Tx
RxDq
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) mode
MIN.
SCKp cycle time
tKCY1
tKCY1  2/fCLK
4.0 V  EVDD0  5.5 V,
(1/2)
MAX.
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage
main) mode
MIN.
Unit
MAX.
200
1150
1150
ns
300
1150
1150
ns
tKCY1/2 - 50
tKCY1/2 - 50
tKCY1/2 - 50
ns
tKCY1/2 - 120
tKCY1/2 - 120
tKCY1/2 - 120
ns
tKCY1/2 - 7
tKCY1/2 - 50
tKCY1/2 - 50
ns
tKCY1/2 - 10
tKCY1/2 - 50
tKCY1/2 - 50
ns
58
479
479
ns
121
479
479
ns
10
10
10
ns
10
10
10
ns
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SCKp high-level
width
tKH1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SCKp low-level
width
tKL1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp setup time
tSIK1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
(to SCKp↑) Note 1
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp hold time
tKSI1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
(from SCKp↑) Note 1
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from
SCKpto SOp
output Note 1
tKSO1
4.0 V  EVDD0  5.5 V,
60
60
60
ns
130
130
130
ns
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
(Notes, Caution, and Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
tSIK1
SIp setup time
4.0 V  EVDD0  5.5 V,
MAX.
(2/2)
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
23
110
110
ns
33
110
110
ns
10
10
10
ns
10
10
10
ns
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
(to SCKp) Note 2
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp hold time
tKSI1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
(from SCKp) Note 2
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp↑
tKSO1
to SOp output Note 2
4.0 V  EVDD0  5.5 V,
10
10
10
ns
10
10
10
ns
2.7 V  Vb  4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V,
Cb = 20 pF, Rb = 2.7 k
Note 1.
Note 2.
Caution
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number
(mn = 00))
Remark 4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) mode
MIN.
SCKp cycle time
tKCY1
tKCY1  4/fCLK
(1/3)
MAX.
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage
main) mode
MIN.
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
300
1150
1150
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
500
1150
1150
ns
1.8 V  EVDD0 < 3.3 V,
1150
1150
1150
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 75
tKCY1/2 - 75
tKCY1/2 - 75
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 170
tKCY1/2 - 170
tKCY1/2 - 170
ns
1.8 V  EVDD0 < 3.3 V,
tKCY1/2 - 458
tKCY1/2 - 458
tKCY1/2 - 458
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 12
tKCY1/2 - 50
tKCY1/2 - 50
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 18
tKCY1/2 - 50
tKCY1/2 - 50
ns
1.8 V  EVDD0 < 3.3 V,
tKCY1/2 - 50
tKCY1/2 - 50
tKCY1/2 - 50
ns
1.6 V  Vb  2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
SCKp high-level
width
tKH1
1.6 V  Vb  2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
SCKp low-level
width
tKL1
1.6 V  Vb  2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
Note
Caution
Use it with EVDD0  Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
(Remarks are listed two pages after the next page.)
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
SIp setup time
tSIK1
(to SCKp↑) Note 1
MAX.
(2/3)
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
81
479
479
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
177
479
479
ns
1.8 V  EVDD0 < 3.3 V,
479
479
479
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
19
19
19
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
19
19
19
ns
1.8 V  EVDD0 < 3.3 V,
19
19
19
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
(from SCKp↑) Note 1
1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp↓
tKSO1
to SOp output Note 1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
100
100
100
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
195
195
195
ns
1.8 V  EVDD0 < 3.3 V,
483
483
483
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
Note 1.
Note 2.
Caution
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Use it with EVDD0  Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
(Remarks are listed on the page after the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
SIp setup time
tSIK1
(to SCKp↓) Note 1
MAX.
(3/3)
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
44
110
110
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
44
110
110
ns
1.8 V  EVDD0 < 3.3 V,
110
110
110
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
19
19
19
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
19
19
19
ns
1.8 V  EVDD0 < 3.3 V,
19
19
19
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
(from SCKp↓) Note 1
1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp↑
tKSO1
to SOp output Note 1
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
25
25
25
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
25
25
25
ns
1.8 V  EVDD0 < 3.3 V,
25
25
25
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
Note 1.
Note 2.
Caution
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Use it with EVDD0  Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0246EJ0100 Rev. 1.00
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
Rb
SCKp
RL78 microcontroller
Rb
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
Remark 4. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 2. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY2
Note 1
Conditions
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V
1.8 V  EVDD0  3.3 V,
1.6 V  Vb  2.0 V
SIp setup time
tKH2,
tKL2
tSIK2
LV (low-voltage
main) mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
24 MHz  fMCK
14/fMCK
—
—
ns
20 MHz  fMCK  24 MHz
12/fMCK
—
—
ns
8 MHz  fMCK  20 MHz
10/fMCK
—
—
ns
4 MHz  fMCK  8 MHz
8/fMCK
16/fMCK
—
ns
fMCK  4 MHz
6/fMCK
10/fMCK
10/fMCK
ns
24 MHz  fMCK
20/fMCK
—
—
ns
20 MHz  fMCK  24 MHz
16/fMCK
—
—
ns
16 MHz  fMCK  20 MHz
14/fMCK
—
—
ns
8 MHz  fMCK  16 MHz
12/fMCK
—
—
ns
4 MHz  fMCK  8 MHz
8/fMCK
16/fMCK
—
ns
fMCK  4 MHz
6/fMCK
10/fMCK
10/fMCK
ns
24 MHz  fMCK
48/fMCK
—
—
ns
36/fMCK
—
—
ns
16 MHz  fMCK  20 MHz
32/fMCK
—
—
ns
8 MHz  fMCK  16 MHz
26/fMCK
—
—
ns
4 MHz  fMCK  8 MHz
16/fMCK
16/fMCK
—
ns
fMCK  4 MHz
10/fMCK
10/fMCK
10/fMCK
ns
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V
tKCY2/2
- 12
tKCY2/2
- 50
tKCY2/2
- 50
ns
2.7 V  EVDD0  4.0 V, 2.3 V  Vb  2.7 V
tKCY2/2
- 18
tKCY2/2
- 50
tKCY2/2
- 50
ns
1.8 V  EVDD0  3.3 V, 1.6 V  Vb  2.0 V Note 2
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2
- 50
ns
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
2.7 V  EVDD0  4.0 V, 2.3 V  Vb  2.7 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
1.8 V  EVDD0  3.3 V, 1.6 V  Vb  2.0 V Note 2
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
(to SCKp↑) Note 3
SIp hold time
LS (low-speed
main) mode
20 MHz  fMCK  24 MHz
Note 2
SCKp high-/
low-level width
HS (high-speed
main) mode
tKSI2
(from SCKp↑)
Note 4
Delay time from
SCKp to SOp
output Note 5
tKSO2
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
2/fMCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V  EVDD0  4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V  EVDD0  3.3 V, 1.6 V  Vb  2.0 V Note 2,
Cb = 30 pF, Rv = 5.5 k
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
(Notes, Cautions, and Remarks are listed on the next page.)
R01DS0246EJ0100 Rev. 1.00
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RL78/G1F
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Caution
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Use it with EVDD0  Vb.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and SCKp pin, and the N-ch open drain output (VDD tolerance (for the
48-, 32-, 24-pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10))
Remark 4. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 2. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 60 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
SCLr clock frequency
fSCL
MAX.
(1/2)
LS (low-speed main)
mode
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
1000 Note 1
300 Note 1
300 Note 1
kHz
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
1000 Note 1
300 Note 1
300 Note 1
kHz
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
400 Note 1
300 Note 1
300 Note 1
kHz
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
400 Note 1
300 Note 1
300 Note 1
kHz
1.8 V  EVDD0 < 3.3 V,
300 Note 1
300 Note 1
300 Note 1
kHz
1.6 V  Vb  2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr = “L”
tLOW
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
475
1550
1550
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
475
1550
1550
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
1150
1550
1550
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
1150
1550
1550
ns
1.8 V  EVDD0 < 3.3 V,
1550
1550
1550
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
245
610
610
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
200
610
610
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
675
610
610
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
600
610
610
ns
1.8 V  EVDD0 < 3.3 V,
610
610
610
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr = “H”
tHIGH
1.6 V  Vb  2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
R01DS0246EJ0100 Rev. 1.00
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
Data setup time
(reception)
tSU:DAT
(2/2)
LS (low-speed main)
mode
MAX.
MIN.
MAX.
LV (low-voltage main)
mode
MIN.
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 135 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 135 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
1.8 V  EVDD0 < 3.3 V,
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
Data hold time
(transmission)
tHD:DAT
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
0
305
0
305
0
305
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
0
305
0
305
0
305
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
0
355
0
355
0
355
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
0
355
0
355
0
355
ns
1.8 V  EVDD0 < 3.3 V,
0
405
0
405
0
405
ns
1.6 V  Vb  2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
Note 3.
The value must also be equal to or less than fMCK/4.
Use it with EVDD0  Vb.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin products)/EVDD
Note 1.
Note 2.
tolerance (for the 64-, 36-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (for
the 48-, 32-, 24-pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SCLr pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20), g: PIM, POM number (g = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 00, 01, 02, 10)
R01DS0246EJ0100 Rev. 1.00
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RL78/G1F
2.5.2
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Serial interface IICA
(1) I2C standard mode
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
SCLA0 clock
frequency
Symbol
fSCL
Conditions
Standard mode:
fCLK  1 MHz
HS (high-speed main)
mode
tSU: STA
tHD: STA
tLOW
MAX.
MIN.
MAX.
MIN.
MAX.
100
0
100
0
100
kHz
1.8 V  EVDD0  5.5 V
0
100
0
100
0
100
kHz
1.7 V  EVDD0  5.5 V
0
100
0
100
0
100
kHz
0
100
0
100
kHz
—
2.7 V  EVDD0  5.5 V
4.7
4.7
4.7
s
1.8 V  EVDD0  5.5 V
4.7
4.7
4.7
s
1.7 V  EVDD0  5.5 V
4.7
4.7
4.7
s
4.7
4.7
s
2.7 V  EVDD0  5.5 V
4.0
4.0
4.0
s
1.8 V  EVDD0  5.5 V
4.0
4.0
4.0
s
1.7 V  EVDD0  5.5 V
4.0
4.0
4.0
s
—
4.0
4.0
s
2.7 V  EVDD0  5.5 V
4.7
4.7
4.7
s
1.8 V  EVDD0  5.5 V
4.7
4.7
4.7
s
1.7 V  EVDD0  5.5 V
4.7
4.7
4.7
s
—
1.6 V  EVDD0  5.5 V
Hold time when
SCLA0 = “H”
tHIGH
Unit
0
1.6 V  EVDD0  5.5 V
Hold time when
SCLA0 = “L”
LV (low-voltage main)
mode
MIN.
1.6 V  EVDD0  5.5 V
Hold time Note 1
LS (low-speed main)
mode
2.7 V  EVDD0  5.5 V
1.6 V  EVDD0  5.5 V
Setup time of
restart condition
(1/2)
4.7
4.7
s
2.7 V  EVDD0  5.5 V
4.0
4.0
4.0
s
1.8 V  EVDD0  5.5 V
4.0
4.0
4.0
s
1.7 V  EVDD0  5.5 V
4.0
4.0
4.0
s
4.0
4.0
s
1.6 V  EVDD0  5.5 V
—
—
(Notes, Caution, and Remark are listed on the next page.)
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(1) I2C standard mode
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
MIN.
Data setup time (reception)
tSU: DAT
tHD: DAT
Note 2
tSU: STO
tBUF
Note 2.
Caution
MIN.
MAX.
250
ns
1.8 V  EVDD0  5.5 V
250
250
250
ns
1.7 V  EVDD0  5.5 V
250
250
250
ns
—
250
250
ns
2.7 V  EVDD0  5.5 V
0
3.45
0
3.45
0
3.45
s
1.8 V  EVDD0  5.5 V
0
3.45
0
3.45
0
3.45
s
1.7 V  EVDD0  5.5 V
0
3.45
0
3.45
0
3.45
s
0
3.45
0
3.45
s
—
2.7 V  EVDD0  5.5 V
4.0
4.0
4.0
s
1.8 V  EVDD0  5.5 V
4.0
4.0
4.0
s
1.7 V  EVDD0  5.5 V
4.0
4.0
4.0
s
4.0
4.0
s
2.7 V  EVDD0  5.5 V
4.7
4.7
4.7
s
1.8 V  EVDD0  5.5 V
4.7
4.7
4.7
s
1.7 V  EVDD0  5.5 V
4.7
4.7
4.7
s
4.7
4.7
s
1.6 V  EVDD0  5.5 V
Note 1.
MAX.
Unit
250
1.6 V  EVDD0  5.5 V
Bus-free time
MIN.
LV (low-voltage main)
mode
250
1.6 V  EVDD0  5.5 V
Setup time of stop condition
LS (low-speed main)
mode
2.7 V  EVDD0  5.5 V
1.6 V  EVDD0  5.5 V
Data hold time (transmission)
MAX.
(2/2)
—
—
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(2) I2C fast mode
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
2.7 V  EVDD0  5.5 V
HS (high-speed
main) mode
LS (low-speed
main) mode
LV (low-voltage
main) mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
0
400
0
400
0
400
kHz
0
400
0
400
0
400
kHz
SCLA0 clock frequency
fSCL
Fast mode:
fCLK  3.5 MHz
Setup time of restart
condition
tSU: STA
2.7 V  EVDD0  5.5 V
0.6
0.6
0.6
s
1.8 V  EVDD0  5.5 V
0.6
0.6
0.6
s
Hold time Note 1
tHD: STA
2.7 V  EVDD0  5.5 V
0.6
0.6
0.6
s
1.8 V  EVDD0  5.5 V
0.6
0.6
0.6
s
Hold time when SCLA0 = “L”
tLOW
2.7 V  EVDD0  5.5 V
1.3
1.3
1.3
s
1.8 V  EVDD0  5.5 V
1.3
1.3
1.3
s
2.7 V  EVDD0  5.5 V
0.6
0.6
0.6
s
Hold time when SCLA0 = “H” tHIGH
Data setup time (reception)
tSU: DAT
Data hold time (transmission)
tHD: DAT
Note 2
Setup time of stop condition
tSU: STO
Bus-free time
tBUF
Note 1.
Note 2.
Caution
1.8 V  EVDD0  5.5 V
1.8 V  EVDD0  5.5 V
0.6
0.6
0.6
s
2.7 V  EVDD0  5.5 V
100
100
100
ns
1.8 V  EVDD0  5.5 V
100
2.7 V  EVDD0  5.5 V
0
0.9
1.8 V  EVDD0  5.5 V
0
0.9
2.7 V  EVDD0  5.5 V
0.6
0.6
0.6
s
1.8 V  EVDD0  5.5 V
0.6
0.6
0.6
s
2.7 V  EVDD0  5.5 V
1.3
1.3
1.3
s
1.8 V  EVDD0  5.5 V
1.3
1.3
1.3
s
100
100
0
0.9
0
0.9
ns
0
0.9
s
0
0.9
s
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode: Cb = 320 pF, Rb = 1.1 k
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Page 66 of 140
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(3) I2C fast mode plus
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
2.7 V  EVDD0  5.5 V
SCLA0 clock frequency
fSCL
Fast mode plus:
fCLK  10 MHz
Setup time of restart
condition
tSU: STA
2.7 V  EVDD0  5.5 V
Hold time Note 1
tHD: STA
2.7 V  EVDD0  5.5 V
Hold time when SCLA0 = “L”
HS (high-speed
main) mode
LS (low-speed
main) mode
LV (low-voltage
main) mode
MIN.
MAX.
MIN.
MIN.
0
1000
MAX.
Unit
MAX.
—
—
kHz
0.26
—
—
s
0.26
—
—
s
tLOW
2.7 V  EVDD0  5.5 V
0.5
—
—
s
Hold time when SCLA0 = “H” tHIGH
2.7 V  EVDD0  5.5 V
0.26
—
—
s
Data setup time (reception)
tSU: DAT
2.7 V  EVDD0  5.5 V
50
Data hold time (transmission)
tHD: DAT
2.7 V  EVDD0  5.5 V
0
Setup time of stop condition
tSU: STO
2.7 V  EVDD0  5.5 V
0.26
Bus-free time
tBUF
2.7 V  EVDD0  5.5 V
0.5
0.45
—
—
ns
—
—
s
—
—
s
—
—
s
Note 2
Note 1.
Note 2.
Caution
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
tLOW
SCLAn
tHD: DAT
tHD: STA
tHIGH
tSU: STA
tHD: STA
tSU: STO
tSU: DAT
SDAAn
tBUF
Stop
condition
Remark
Start
condition
Restart
condition
Stop
condition
n = 0, 1
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RL78/G1F
2.6
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Analog Characteristics
2.6.1
A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Input channel
ANI0 to ANI7
Reference voltage (+) = AVREFP
Reference voltage (-) = AVREFM
Refer to 2.6.1 (1).
ANI16 to ANI24
Refer to 2.6.1 (2).
Internal reference voltage
Temperature sensor output voltage
Refer to 2.6.1 (1).
Reference voltage (+) = VDD
Reference voltage (-) = VSS
Refer to 2.6.1 (3).
Reference voltage (+) = VBGR
Reference voltage (-)= AVREFM
Refer to 2.6.1 (4).
—
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 to ANI7, internal reference voltage, and temperature sensor
output voltage
(TA = -40 to +85°C, 1.6 V  AVREFP  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-)
= AVREFM = 0 V)
Parameter
Resolution
Overall error
Symbol
Conditions
MIN.
RES
Note 1
Conversion time
AINL
tCONV
Full-scale error Notes 1, 2
Integral linearity error Note 1
Differential linearity error Note 1
Analog input voltage
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
EZS
EFS
ILE
DLE
VAIN
MAX.
Unit
10
bit
1.2
3.5
LSB
1.2
10-bit resolution
1.8 V  AVREFP  5.5 V
AVREFP = VDD Note 3
1.6 V  AVREFP  5.5 V Note 4
7.0
LSB
10-bit resolution
Target pin: ANI2 to ANI14
3.6 V  VDD  5.5 V
2.125
39
s
2.7 V  VDD  5.5 V
3.1875
39
s
1.8 V  VDD  5.5 V
17
39
s
1.6 V  VDD  5.5 V
57
95
s
2.375
39
s
3.5625
39
s
17
39
s
10-bit resolution
3.6 V  VDD  5.5 V
Target pin: Internal reference voltage, 2.7 V  VDD  5.5 V
and temperature sensor output voltage
2.4 V  VDD  5.5 V
(HS (high-speed main) mode)
Zero-scale error Notes 1, 2
TYP.
8
10-bit resolution
1.8 V  AVREFP  5.5 V
0.25
%FSR
AVREFP = VDD Note 3
1.6 V  AVREFP  5.5 V Note 4
0.50
%FSR
10-bit resolution
1.8 V  AVREFP  5.5 V
0.25
%FSR
AVREFP = VDD Note 3
1.6 V  AVREFP  5.5 V
0.50
%FSR
10-bit resolution
1.8 V  AVREFP  5.5 V
AVREFP = VDD Note 3
1.6 V  AVREFP  5.5 V
Note 4
2.5
LSB
Note 4
5.0
LSB
10-bit resolution
1.8 V  AVREFP  5.5 V
1.5
LSB
AVREFP = VDD Note 3
1.6 V  AVREFP  5.5 V Note 4
2.0
LSB
AVREFP
V
ANI2 to ANI7
0
Internal reference voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VBGR Note 5
V
Temperature sensor output voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VTMPS25 Note 5
V
Excludes quantization error (±1/2 LSB).
This value is indicated as a ratio (%FSR) to the full-scale value.
When AVREFP < VDD, the MAX. values are as follows.
Overall error:
Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error:
Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Values when the conversion time is set to 57 s (min.) and 95 s (max.).
Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
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RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI24
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, 1.6 V  AVREFP  VDD  5.5 V, VSS = EVSS0 = 0 V, Reference voltage
(+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall error Note 1
AINL
Conditions
tCONV
Zero-scale error Notes 1, 2
EZS
10-bit resolution
10-bit resolution
Target ANI pin: ANI16 to ANI24
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Full-scale error
Notes 1, 2
EFS
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Integral linearity error
Note 1
ILE
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Differential linearity error Note 1
DLE
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Analog input voltage
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
VAIN
TYP.
MAX.
Unit
10
bit
8
EVDD0  AVREFP = VDD Notes 3, 4
Conversion time
MIN.
ANI16 to ANI24
1.8 V  AVREFP  5.5 V
1.6 V  AVREFP  5.5 V
Note 5
1.2
5.0
LSB
1.2
8.5
LSB
39
s
3.6 V  VDD  5.5 V
2.125
2.7 V  VDD  5.5 V
3.1875
39
s
1.8 V  VDD  5.5 V
17
39
s
1.6 V  VDD  5.5 V
57
1.8 V  AVREFP  5.5 V
95
s
0.35
%FSR
1.6 V  AVREFP  5.5 V Note 5
0.60
%FSR
1.8 V  AVREFP  5.5 V
0.35
%FSR
1.6 V  AVREFP  5.5 V Note 5
0.60
%FSR
1.8 V  AVREFP  5.5 V
3.5
LSB
1.6 V  AVREFP  5.5 V Note 5
6.0
LSB
1.8 V  AVREFP  5.5 V
2.0
LSB
1.6 V  AVREFP  5.5 V Note 5
2.5
LSB
AVREFP
and
EVDD0
V
0
Excludes quantization error (±1/2 LSB).
This value is indicated as a ratio (%FSR) to the full-scale value.
When EVDD0  AVREFP  VDD, the MAX. values are as follows.
Overall error:
Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error:
Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
When AVREFP < EVDD0  VDD, the MAX. values are as follows.
Overall error:
Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error:
Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
When the conversion time is set to 57 s (min.) and 95 s (max.).
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Apr 06, 2015
Page 69 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0),
target pin: ANI0 to ANI17, ANI16 to ANI24, internal reference voltage, and temperature sensor output
voltage
(TA = -40 to +85°C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V, Reference voltage (+) = VDD, Reference
voltage (-) = VSS)
Parameter
Resolution
Overall error
Symbol
Conditions
MIN.
TYP.
MAX.
10
bit
1.8 V  VDD  5.5 V
1.2
7.0
LSB
1.6 V  VDD  5.5 V Note 3
1.2
10.5
LSB
RES
Note 1
Conversion time
AINL
tCONV
8
10-bit resolution
10-bit resolution
Target pin: ANI0 to ANI7, ANI16 to ANI24
10-bit resolution
Target pin: internal reference voltage, and
temperature sensor output voltage
(HS (high-speed main) mode)
Zero-scale error
Notes 1, 2
Full-scale error Notes 1, 2
EZS
EFS
10-bit resolution
10-bit resolution
3.6 V  VDD  5.5 V
2.125
39
s
2.7 V  VDD  5.5 V
3.1875
39
s
1.8 V  VDD  5.5 V
17
39
s
1.6 V  VDD  5.5 V
57
95
s
3.6 V  VDD  5.5 V
2.375
39
s
2.7 V  VDD  5.5 V
3.5625
39
s
2.4 V  VDD  5.5 V
17
39
s
1.8 V  VDD  5.5 V
0.60
%FSR
1.6 V  VDD  5.5 V Note 3
0.85
%FSR
1.8 V  VDD  5.5 V
0.60
%FSR
0.85
%FSR
4.0
LSB
1.6 V  VDD  5.5 V
Integral linearity error Note 1
ILE
10-bit resolution
Note 3.
Note 4.
LSB
LSB
2.5
LSB
VDD
V
EVDD0
V
1.8 V  VDD  5.5 V
10-bit resolution
VAIN
ANI0 to ANI7
0
ANI16 to ANI24
0
1.6 V  VDD  5.5 V Note 3
Analog input voltage
Note 2.
6.5
2.0
Note 3
DLE
Note 1
Note 1.
Note 3
1.8 V  VDD  5.5 V
1.6 V  VDD  5.5 V
Differential linearity error
Unit
Internal reference voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VBGR Note 4
V
Temperature sensor output voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VTMPS25 Note 4
V
Excludes quantization error (±1/2 LSB).
This value is indicated as a ratio (% FSR) to the full-scale value.
When the conversion time is set to 57 s (min.) and 95 s (max.).
Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
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Page 70 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 to ANI7, ANI16 to ANI24
(TA = -40 to +85°C, 2.4 V  VDD  5.5 V, 1.6 V  EVDD0  VDD, VSS = EVSS0 = 0 V, Reference voltage (+) = VBGR Note 3,
Reference voltage (-) = AVREFM = 0 V Note 4, HS (high-speed main) mode)
Parameter
Symbol
Conditions
Resolution
RES
Conversion time
tCONV
8-bit resolution
2.4 V  VDD  5.5 V
Zero-scale error Notes 1, 2
EZS
8-bit resolution
Integral linearity error Note 1
ILE
Differential linearity error Note 1
DLE
Analog input voltage
VAIN
Note 1.
Note 2.
Note 3.
Note 4.
MIN.
TYP.
MAX.
8
Unit
bit
39
s
2.4 V  VDD  5.5 V
0.60
% FSR
8-bit resolution
2.4 V  VDD  5.5 V
2.0
LSB
8-bit resolution
2.4 V  VDD  5.5 V
1.0
LSB
VBGR Note 3
V
17
0
Excludes quantization error (±1/2 LSB).
This value is indicated as a ratio (% FSR) to the full-scale value.
Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
When reference voltage (-) = VSS, the MAX. values are as follows.
Zero-scale error:
Add ±0.35%FSR to the MAX. value when reference voltage (-) = AVREFM.
Integral linearity error:
Add ±0.5 LSB to the MAX. value when reference voltage (-) = AVREFM.
Differential linearity error:
Add ±0.2 LSB to the MAX. value when reference voltage (-) = AVREFM.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 71 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2.6.2
Temperature sensor characteristics/internal reference voltage characteristic
(TA = -40 to +85°C, 2.4 V  VDD  5.5 V, VSS = EVSS0 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
temperature
Operation stabilization wait time
tAMP
2.6.3
TYP.
MAX.
1.05
1.38
Unit
V
1.45
1.5
V
mV/C
-3.6
s
5
D/A converter characteristics
(TA = -40 to +85°C, 1.6 V EVSS0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
bit
Resolution
RES
Overall error
AINL
Rload = 4 M
1.8 V  VDD  5.5 V
2.5
LSB
Rload = 8 M
1.8 V  VDD  5.5 V
2.5
LSB
Settling time
tSET
Cload = 20 pF
2.7 V  VDD  5.5 V
3
s
1.6 V  VDD < 2.7 V
6
s
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Page 72 of 140
RL78/G1F
2.6.4
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Comparator
(TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Input offset voltage
VIOCMP
Input voltage range
VICMP
Internal reference
voltage deviation
∆VIREF
Response Time
tCR, tCF
Conditions
MIN.
TYP.
MAX.
Unit
5
40
mV
VDD
V
CmRVM register value : 7FH to 80H (m = 0, 1)
0
2
LSB
Other than above
1
LSB
150
ns
VDD = 3.3 to 5.5 V
1
s
VDD = 2.7 to 3.3 V
3
s
20
s
Input amplitude±100mV
70
Operation stabilization tCMP
timeNote 1
CMPn = 0→1
Reference voltage
stabilization wait time
tVR
CVRE : 0→1Note 2
Operation current
ICMPDD
Separately, it is defined as the operation current of peripheral functions.
Note 1.
Time taken until the comparator satisfies the DC/AC characteristics after the comparator operation enable signal is
switched (CMPnEN = 0 → 1).
Note 2.
Enable comparator output (CnOE bit = 1; n = 0 to 1) after enabling operation of the internal reference voltage generator
(by setting the CVREm bit to 1; m = 0 to 1) and waiting for the operation stabilization time to elapse.
2.6.5
PGA
(TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Input offset voltage
VIOPGA
Input voltage range
VIPGA
Output voltage range
VIOHPGA
Conditions
MIN.
TYP.
0
<R>
SRRPGA
<R>
SRFPGA
Reference voltage
stabilization wait
timeNote 1
tPGA
Operation current
IPGADD
Note 1.
10
mV
0.9 
VDD/Gain
V
V
0.07  VDD
V
1
%
x16
1.5
%
x32
2
%
x4, x8
Slew rate
Unit
0.93  VDD
VIOLPGA
Gain error
MAX.
Rising
When Vin= 0.1VDD/gain
to 0.9VDD/gain.
10 to 90% of output
voltage amplitude
Falling
When Vin= 0.1VDD/gain
to 0.9VDD/gain.
90 to 10% of output
voltage amplitude
4.0 V ≤ VDD ≤ 5.5 V
3.5
V/μs
(Other than x32)
4.0 V ≤ VDD ≤ 5.5 V (x32)
3.0
2.7 V ≤ VDD ≤ 4.0V
0.5
4.0 V ≤ VDD ≤ 5.5 V
3.5
(Other than x32)
4.0 V ≤ VDD ≤ 5.5 V (x32)
3.0
2.7 V ≤ VDD ≤ 4.0V
0.5
x4, x8
5
μs
x16, x32
10
μs
Separately, it is defined as the operation current of peripheral functions.
Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA
operation has been enabled (PGAEN = 1).
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Page 73 of 140
RL78/G1F
2.6.6
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
POR circuit characteristics
(TA = -40 to +85°C, VSS = 0 V)
Parameter
Symbol
Power on/down reset threshold VPOR
VPDR
Minimum pulse width
Note 1.
Note 2.
Note 2
Conditions
Voltage threshold on VDD rising
Voltage threshold on VDD falling
Note 1
TPW
MIN.
TYP.
MAX.
Unit
1.47
1.51
1.55
V
1.46
1.50
1.54
V
s
300
However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics.
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 74 of 140
RL78/G1F
2.6.7
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
LVD circuit characteristics
(1) Reset Mode and Interrupt Mode
(TA = -40 to +85°C, VPDR  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Voltage
detection
threshold
Supply voltage level
Symbol
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
Detection delay time
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
tLW
MIN.
TYP.
MAX.
Unit
Rising edge
Conditions
3.98
4.06
4.14
V
Falling edge
3.90
3.98
4.06
V
Rising edge
3.68
3.75
3.82
V
Falling edge
3.60
3.67
3.74
V
Rising edge
3.07
3.13
3.19
V
Falling edge
3.00
3.06
3.12
V
Rising edge
2.96
3.02
3.08
V
Falling edge
2.90
2.96
3.02
V
Rising edge
2.86
2.92
2.97
V
Falling edge
2.80
2.86
2.91
V
Rising edge
2.76
2.81
2.87
V
Falling edge
2.70
2.75
2.81
V
Rising edge
2.66
2.71
2.76
V
Falling edge
2.60
2.65
2.70
V
Rising edge
2.56
2.61
2.66
V
Falling edge
2.50
2.55
2.60
V
Rising edge
2.45
2.50
2.55
V
Falling edge
2.40
2.45
2.50
V
Rising edge
2.05
2.09
2.13
V
Falling edge
2.00
2.04
2.08
V
Rising edge
1.94
1.98
2.02
V
Falling edge
1.90
1.94
1.98
V
Rising edge
1.84
1.88
1.91
V
Falling edge
1.80
1.84
1.87
V
Rising edge
1.74
1.77
1.81
V
Falling edge
1.70
1.73
1.77
V
Rising edge
1.64
1.67
1.70
V
Falling edge
1.60
1.63
1.66
V
s
300
300
s
Page 75 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(2) Interrupt & Reset Mode
(TA = -40 to +85°C, VPDR  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Voltage detection
threshold
VLVDA0
Conditions
LVIS1, LVIS0 = 1, 0
VLVDA1
LVIS1, LVIS0 = 0, 1
VLVDA2
LVIS1, LVIS0 = 0, 0
VLVDA3
VLVDB0
TYP.
MAX.
Unit
1.60
1.63
1.66
V
Rising release reset voltage
1.74
1.77
1.81
V
Falling interrupt voltage
1.70
1.73
1.77
V
Rising release reset voltage
1.84
1.88
1.91
V
Falling interrupt voltage
1.80
1.84
1.87
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
LVIS1, LVIS0 = 1, 0
VLVDB1
1.80
1.84
1.87
V
Rising release reset voltage
1.94
1.98
2.02
V
Falling interrupt voltage
1.90
1.94
1.98
V
2.05
2.09
2.13
V
VLVDB2
LVIS1, LVIS0 = 0, 1
Rising release reset voltage
Falling interrupt voltage
2.00
2.04
2.08
V
VLVDB3
LVIS1, LVIS0 = 0, 0
Rising release reset voltage
3.07
3.13
3.19
V
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
Rising release reset voltage
2.56
2.61
2.66
V
Falling interrupt voltage
2.50
2.55
2.60
V
Rising release reset voltage
2.66
2.71
2.76
V
Falling interrupt voltage
2.60
2.65
2.70
V
Rising release reset voltage
3.68
3.75
3.82
V
Falling interrupt voltage
3.60
3.67
3.74
V
2.70
2.75
2.81
V
2.86
2.92
2.97
V
VLVDC0
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0
VLVDC1
LVIS1, LVIS0 = 0, 1
VLVDC2
LVIS1, LVIS0 = 0, 0
VLVDC3
VLVDD0
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVDD1
LVIS1, LVIS0 = 1, 0
Rising release reset voltage
Falling interrupt voltage
2.80
2.86
2.91
V
VLVDD2
LVIS1, LVIS0 = 0, 1
Rising release reset voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
Rising release reset voltage
3.98
4.06
4.14
V
Falling interrupt voltage
3.90
3.98
4.06
V
VLVDD3
2.6.8
MIN.
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage
LVIS1, LVIS0 = 0, 0
Power supply voltage rising slope characteristics
(TA = -40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
SVDD
Conditions
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 2.4 AC Characteristics.
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Apr 06, 2015
Page 76 of 140
RL78/G1F
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2.7
RAM Data Retention Characteristics
(TA = -40 to +85°C, VSS = 0V))
Parameter
Data retention supply voltage
Symbol
Conditions
MIN.
VDDDR
1.46
TYP.
MAX.
Unit
5.5
V
Notes 1, 2
The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset
is effected, but RAM data is not retained when a POR reset is effected.
Enter STOP mode before the supply voltage falls below the recommended operating voltage.
Note 1.
Note 2.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8
Flash Memory Programming Characteristics
(TA = -40 to +85°C, 1.8 V  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
System clock frequency
fCLK
1.8 V  VDD  5.5 V
Number of code flash rewrites
Cerwr
Retained for 20 years
TA = 85°C
Number of data flash rewrites
Retained for 1 year
TA = 25°C
Notes 1, 2, 3
Retained for 5 years
TA = 85°C
100,000
Retained for 20 years
TA = 85°C
10,000
TYP.
1
MAX.
Unit
32
MHz
1,000
Times
Notes 1, 2, 3
Note 1.
Note 2.
Note 3.
2.9
1,000,000
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
When using flash memory programmer and Renesas Electronics self-programming library
These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Transfer rate
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Symbol
Conditions
During serial programming
MIN.
115,200
TYP.
MAX.
Unit
1,000,000 bps
Page 77 of 140
RL78/G1F
2.10
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Timing of Entry to Flash Memory Programming Modes
(TA = -40 to +85°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
How long from when an external reset ends until the
initial communication settings are specified
tSUINIT
POR and LVD reset must end
before the external reset ends.
How long from when the TOOL0 pin is placed at the
low level until an external reset ends
tSU
POR and LVD reset must end
before the external reset ends.
10
s
How long the TOOL0 pin must be kept at the low
level after an external reset ends
(excluding the processing time of the firmware to
control the flash memory)
tHD
POR and LVD reset must end
before the external reset ends.
1
ms
<1>
<2>
<3>
<4>
RESET
723 µs + tHD
00H reception
processing
(TOOLRxD, TOOLTxD mode)
time
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
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Page 78 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
This chapter describes the following electrical specifications.
Target products G: Industrial applications TA = −40 to +105°C
R5F11BxxGxx
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. With products not provided with an EVDD0, or EVSS0 pin, replace EVDD0 with VDD, or replace EVSS0
with VSS.
Caution 3. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/G1F User’s Manual.
Caution 4. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105°C.
Derating is the systematic reduction of load for the sake of improved reliability.
Remark
When the products “G: Industrial applications" is used in the range of TA = -40 to +85°C, see 2.
ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C).
R01DS0246EJ0100 Rev. 1.00
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Page 79 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Operation of products rated “G: Industrial applications (TA = -40 to + 105°C)” at ambient operating temperatures above
85°C differs from that of products rated “A: Consumer applications” in the ways listed below.
Parameter
A: Consumer applications
G: Industrial applications
Operating ambient temperature TA = -40 to +85°C
TA = -40 to +105°C
Operating mode
Operating voltage range
HS (high-speed main) mode only:
HS (high-speed main) mode:
2.7 V VDD 5.5 [email protected] MHz to 32 MHz
2.7 V VDD 5.5 [email protected] MHz to 32 MHz
2.4 V VDD 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
2.4 V VDD 5.5 [email protected] MHz to 16 MHz
1.8 V VDD 5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode:
2.4 V VDD 5.5 [email protected] MHz to 4 MHz
High-speed on-chip oscillator
clock accuracy
1.8 V VDD 5.5 V:
±1.0% @ TA = -20 to +85°C
±1.5% @ TA = -40 to -20°C
2.4 V VDD < 1.8 V:
±5.0% @ TA = -20 to +85°C
±5.5% @ TA = -40 to -20°C
2.4 V VDD 5.5 V:
±2.0% @ TA = +85 to +105°C
±1.0% @ TA = -20 to +85°C
±1.5% @ TA = -40 to -20°C
Serial array unit
UART
CSI: fCLK/2 (16 Mbps supported), fCLK/4
Simplified I2C communication
UART
CSI: fCLK/4
Simplified I2C communication
IICA
Standard mode
Fast mode
Fast mode plus
Standard mode
Fast mode
Voltage detector
• Rising: 1.67 V to 4.06 V (14 stages)
• Falling: 1.63 V to 3.98 V (14 stages)
• Rising: 2.61 V to 4.06 V (8 stages)
• Falling: 2.55 V to 3.98 V (8 stages)
Remark
The electrical characteristics of products rated “G: Industrial applications (TA = -40 to + 105°C)” at ambient
operating temperatures above 85°C differ from those of products “A: Consumer applications”. For details,
refer to 3.1 to 3.10.
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Page 80 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Parameter
Supply voltage
(1/2)
Symbols
Conditions
VDD
EVDD0
REGC pin input voltage
VIREGC
REGC
Ratings
Unit
-0.5 to +6.5
V
-0.5 to +6.5
V
-0.3 to +2.8
V
and -0.3 to VDD +0.3 Note 1
Input voltage
VI1
P00 to P06, P10 to P17, P30, P31,
P40 to P43, P50 to P55, P70 to P77, P120,
-0.3 to EVDD0 +0.3
and -0.3 to VDD +0.3
V
Note 2
P140, P141, P146, P147
VI2
P60 to P63 (N-ch open-drain)
VI3
P20 to P27, P121 to P124, P137,
-0.3 to +6.5
V
-0.3 to VDD +0.3 Note 2
V
-0.3 to EVDD0 +0.3
V
EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P06, P10 to P17, P30, P31,
P40 to P43, P50 to P55, P60 to P63,
and -0.3 to VDD +0.3 Note 2
P70 to P77, P120, P130, P140, P141,
P146, P147
Analog input voltage
VO2
P20 to P27
VAI1
ANI16 to ANI24
-0.3 to VDD +0.3 Note 2
-0.3 to EVDD0 +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3
VAI2
ANI0 to ANI7
-0.3 to VDD +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3
V
V
V
Note 1.
Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
Note 2.
Must be 6.5 V or lower.
Note 3.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
REGC pin. Do not use this pin with voltage applied to it.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
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Page 81 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Absolute Maximum Ratings
Parameter
Output current, high
(2/2)
Symbols
IOH1
Conditions
Ratings
Unit
-40
mA
Total of all P00 to P04, P40 to P43,P120, P130, P140, P141
-70
mA
pins
P05, P06, P10 to P17, P30, P31, P50 to P55, P70
-100
mA
-170 mA
to P77, P146, P147
Per pin
P20 to P27
-0.5
mA
-2
mA
40
mA
Total of all P00 to P04, P40 to P47, P120, P130, P140, P141
70
mA
pins
P05, P06, P10 to P17, P30, P31, P50 to P55,
100
mA
170 mA
P70 to P77, P146, P147
Per pin
P20 to P27
1
mA
5
mA
-40 to +105
C
-65 to +150
C
Per pin
P00 to P06, P10 to P17, P30, P31, P40 to P43,
P50 to P55, P70 to P77, P120, P130, P140, P141,
P146, P147
IOH2
Total of all
pins
Output current, low
IOL1
Per pin
P00 to P06, P10 to P17, P30, P31, P40-P43, P50
to P55, P60 to P63, P70 to P77, P120, P130,
P140, P141, P146, P147
IOL2
Total of all
pins
Operating ambient
TA
temperature
Storage temperature
Caution
In normal operation mode
In flash memory programming mode
Tstg
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0246EJ0100 Rev. 1.00
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Page 82 of 140
RL78/G1F
3.2
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Oscillator Characteristics
3.2.1
X1, XT1 characteristics
(TA = -40 to +105°C, 2.4 V  EVDD0 = VDD  5.5 V, VSS = 0 V)
Resonator
X1 clock oscillation frequency
Resonator
(fX) Note
XT1 clock oscillation frequency (fXT) Note
Note
Conditions
MIN.
MAX.
Unit
Ceramic resonator/
2.7 V VDD 5.5 V
1.0
20.0
MHz
crystal resonator
2.4 V VDD <2.7 V
1.0
16.0
Crystal resonator
TYP.
32
32.768
35
kHz
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution
Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark
3.2.2
When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G1F User’s Manual.
On-chip oscillator characteristics
(TA = -40 to +105°C, 2.4 V  EVDD0 = VDD  5.5 V, VSS = 0 V)
Oscillators
Parameters
Conditions
MIN.
TYP.
MAX.
Unit
32
MHz
2.7 V VDD 5.5 V
1
Notes 1, 2
2.4 V VDD <2.7 V
1
16
MHz
High-speed on-chip oscillator clock frequency
TA = +85 to +105°C
-2
2
%
accuracy
TA = -20 to +85°C
-1
1
%
TA = -40 to -20°C
-1.5
1.5
%
High-speed on-chip oscillator clock frequency
Low-speed on-chip oscillator clock frequency
Low-speed on-chip oscillator clock frequency
fIH
fIL
15
-15
kHz
+15
%
accuracy
Note 1.
High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of
the HOCODIV register.
Note 2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
R01DS0246EJ0100 Rev. 1.00
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Page 83 of 140
RL78/G1F
3.3
3.3.1
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
DC Characteristics
Pin characteristics
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Output current, high
Symbol
Note 1
IOH1
Conditions
(1/5)
MAX.
Unit
Per pin for P00 to P06,
MIN.
TYP.
-3.0
mA
P10 to P17, P30, P31,
Note 2
P40 to P47, P50 to P55,
P70 to P77, P120, P130, P140,
P141, P146, P147
Total of P00 to P04, P40 to P43,
4.0 V  EVDD0  5.5 V
-30.0
mA
P120, P130, P140, P141
2.7 V  EVDD0 < 4.0 V
-10.0
mA
(When duty  70% Note 3)
2.4 V  EVDD0 < 2.7 V
-5.0
mA
Total of P05, P06, P10 to P17,
4.0 V  EVDD0  5.5 V
-30.0
mA
P30, P31, P50 to P53,
2.7 V  EVDD0 < 4.0 V
-19.0
mA
P70 to P77, P146, P147
1.8 V  EVDD0 < 2.7 V
-10.0
mA
-60.0
mA
-0.1
mA
(When duty  70% Note 3)
Total of all pins
(When duty  70% Note 3)
IOH2
Per pin for P20 to P27
Note 2
2.4 V  VDD  5.5 V
Total of all pins
(When duty  70%
-1.5
mA
Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, VDD pins to an
Note 2.
Do not exceed the total current value.
output pin.
Note 3.
Specification under conditions where the duty factor  70%.
The output current value that has changed to the duty factor  70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example>
Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01)  -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43, P50 to P55, P71, P74 do not output high level in N-ch opendrain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Output current, low Note 1
Symbol
IOL1
Conditions
(2/5)
MIN.
TYP.
Per pin for P00 to P06, P10 to
P17, P30, P31, P40 to P43, P50
MAX.
Unit
8.5
mA
Note 2
to P55, P70 to P77,P120, P130,
P140, P141, P146, P147
Per pin for P60 to P63
15.0
mA
Note 2
Total of P00 to P04, P40 to P43,
4.0 V  EVDD0  5.5 V
40.0
mA
P120, P130, P140, P141
2.7 V  EVDD0 < 4.0 V
15.0
mA
2.4 V  EVDD0 < 1.8 V
9.0
mA
(When duty  70% Note 3)
4.0 V  EVDD0  5.5 V
40.0
mA
P30, P31, P50 to P55, P60 to
2.7 V  EVDD0 < 4.0 V
35.0
mA
P63, P70 to P77, P146, P147
2.4 V  EVDD0 < 1.8 V
20.0
mA
80.0
mA
0.4
mA
Total of P05, P06, P10 to P17,
(When duty  70% Note 3)
Total of all pins
(When duty  70% Note 3)
IOL2
Per pin for P20 to P27
Note 2
Total of all pins
2.4 V  VDD  5.5 V
5.0
mA
(When duty  70% Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0 and
VSS pins.
Note 2.
Note 3.
Do not exceed the total current value.
Specification under conditions where the duty factor  70%.
The output current value that has changed to the duty factor  70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example>
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Input voltage, high
Symbol
VIH1
Conditions
P00 to P06, P10 to P17, P30,
(3/5)
MIN.
Normal input buffer
TYP.
MAX.
Unit
0.8 EVDD0
EVDD0
V
2.2
EVDD0
V
2.0
EVDD0
V
1.5
EVDD0
V
0.7 VDD
VDD
V
0.7 EVDD0
6.0
V
0.8 VDD
VDD
V
0
0.2 EVDD0
V
0
0.8
V
0
0.5
V
0
0.32
V
P31, P40 to P43, P50 to P55,
P70 to P77, P120, P140, P141,
P146, P147
VIH2
P01, P03, P04, P10, P14 to P17, TTL input buffer
P30, P43, P50, P53 to P55,
4.0 V  EVDD0  5.5 V
TTL input buffer
3.3 V  EVDD0 < 4.0 V
TTL input buffer
2.4 V  EVDD0 < 3.3 V
VIH3
P20 to P27 (when P20 is used as a port pin)
VIH4
P60 to P63
VIH5
P121 to P123, P137, EXCLK, EXCLKS, RESET (when
P20 is used as INTP11 pin)
Input voltage, low
VIL1
P00 to P06, P10 to P17, P30,
Normal input buffer
P31, P40 to P43, P50 to P55,
P70 to P77, P120, P140, P141,
P146, P147
VIL2
P01, P03, P04, P10, P14 to P17, TTL input buffer
P30, P43, P50, P53 to P55,
4.0 V  EVDD0  5.5 V
TTL input buffer
3.3 V  EVDD0 < 4.0 V
TTL input buffer
2.4 V  EVDD0 < 3.3 V
VIL3
P20 to P27 (when P20 is used as a port pin)
0
0.3 VDD
V
VIL4
P60 to P63
0
0.3 EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET (when
0
0.2 VDD
V
P20 is used as INTP11 pin)
Caution
The maximum value of VIH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43, P50 to P55, P71, P74 is
EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Output voltage, high
Symbol
VOH1
Conditions
P00 to P06, P10 to P17, P30,
4.0 V  EVDD0  5.5 V,
P31, P40 to P43, P50 to P55,
IOH1 = -3.0 mA
P70 to P77, P120, P130, P140,
2.7 V  EVDD0  5.5 V,
P141, P146, P147
IOH1 = -2.0 mA
2.4 V  EVDD0 < 5.5 V,
(4/5)
MIN.
TYP.
MAX.
Unit
EVDD0 - 0.7
V
EVDD0 - 0.6
V
EVDD0 - 0.5
V
VDD - 0.5
V
IOH1 = -1.5 mA
VOH2
P20 to P27
2.4 V  VDD  5.5 V,
IOH2 = -100 A
Output voltage, low
VOL1
P00 to P06, P10 to P17, P30,
4.0 V  EVDD0  5.5 V,
P31, P40 to P43, P50 to P55,
IOL1 = 8.5 mA
P70 to P77, P120, P130, P140,
2.7 V  EVDD0  5.5 V,
P141, P146, P147
IOL1 = 3.0 mA
2.7 V  EVDD0  5.5 V,
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
IOL1 = 1.5 mA
2.4 V  EVDD0  5.5 V,
IOL1 = 0.6 mA
VOL2
P20 to P27
2.4 V  VDD  5.5 V,
IOL2 = 400 A
VOL3
P60 to P63
4.0 V  EVDD0  5.5 V,
IOL3 = 15.0 mA
4.0 V  EVDD0  5.5 V,
IOL3 = 5.0 mA
2.7 V  EVDD0  5.5 V,
IOL3 = 3.0 mA
2.4 V  EVDD0  5.5 V,
IOL3 = 2.0 mA
Caution
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43, P50 to P55, P71, P74 do not output high level in N-ch opendrain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Input leakage
Symbol
ILIH1
current, high
(5/5)
Conditions
P00 to P06, P10 to P17, P30,
MIN.
TYP.
MAX.
Unit
VI = EVDD0
1
A
1
A
1
A
10
A
VI = EVSS0
-1
A
-1
A
-1
A
-10
A
100
k
P31, P40 to P43, P50 to P55, P70
to P77, P120, P140, P141, P146,
P147
ILIH2
P20 to P27, P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, EXCLK, XT1, XT2,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
current, low
P00 to P06, P10 to P17, P30,
P31, P40 to P43, P50 to P55, P70
to P77, P120, P140, P141, P146,
P147
ILIL2
P20 to P27, P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, EXCLK, XT1, XT2,
external clock
EXCLKS)
input
In resonator
connection
On-chip pull-up
RU
resistance
P00 to P06, P10 to P17, P30,
VI = EVSS0, In input port
10
20
P31, P40 to P43, P50 to P55, P70
to P77, P120, P140, P141, P146,
P147
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3.3.2
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Supply current characteristics
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Supply
current
Conditions
Symbol
IDD1
(1/2)
Operating HS (high-speed main)
mode
mode Note 5
MIN.
fHOCO = 64 MHz,
fIH = 32 MHz Note 3
TYP.
Basic
operation
VDD = 5.0 V
2.4
VDD = 3.0 V
2.4
Basic
operation
VDD = 5.0 V
2.1
VDD = 3.0 V
2.1
MAX.
Unit
mA
Note 1
fHOCO = 32 MHz,
fIH = 32 MHz Note 3
HS (high-speed main)
fHOCO = 64 MHz,
mode Note 5
fIH = 32 MHz Note 3
fHOCO = 32 MHz,
fIH = 32 MHz Note 3
fHOCO = 48 MHz,
9.3
5.2
9.3
Normal
operation
VDD = 5.0 V
4.8
8.7
VDD = 3.0 V
4.8
8.7
4.1
7.3
VDD = 3.0 V
4.1
7.3
Normal
operation
VDD = 5.0 V
3.8
6.7
VDD = 3.0 V
3.8
6.7
VDD = 5.0 V
2.8
4.9
VDD = 3.0 V
2.8
4.9
Normal
operation
Square wave input
3.3
5.7
Resonator connection
3.5
5.8
fMX = 20 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
3.3
5.7
Resonator connection
3.5
5.8
Note 2,
Normal
operation
Square wave input
2.0
3.4
Resonator connection
2.1
3.5
Normal
operation
Square wave input
2.0
3.4
Resonator connection
2.1
3.5
Normal
operation
Square wave input
4.7
6.1
Resonator connection
4.7
6.1
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +25°C
Square wave input
4.7
6.1
Resonator connection
4.7
6.1
Normal
operation
Square wave input
4.8
6.7
Resonator connection
4.8
6.7
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +70°C
Square wave input
4.8
7.5
Resonator connection
4.8
7.5
Normal
operation
Square wave input
5.4
8.9
Resonator connection
5.4
8.9
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +105°C
Square wave input
7.2
21.0
Resonator connection
7.3
21.1
fHOCO = 24 MHz,
fHOCO = 16 MHz,
fIH = 16 MHz Note 3
fMX = 20 MHz
VDD = 5.0 V
fMX = 10 MHz
VDD = 5.0 V
Note 2,
fMX = 10 MHz Note 2,
VDD = 3.0 V
Subsystem clock
operation
5.2
VDD = 3.0 V
VDD = 5.0 V
fIH = 24 MHz Note 3
mode Note 5
VDD = 5.0 V
Normal
operation
fIH = 24 MHz Note 3
HS (high-speed main)
Normal
operation
fSUB = 32.768 kHz
TA = -40°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
TA = +85°C
Note 4
Note 4
Note 4
Normal
operation
mA
mA
A
(Notes and Remarks are listed on the next page.)
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Note 1.
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3.
When high-speed system clock and subsystem clock are stopped.
Note 4.
When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog
timer.
Note 5.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode:
2.7 V  VDD  5.5 [email protected] MHz to 32 MHz
2.4 V  VDD  5.5 [email protected] MHz to 16 MHz
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply current IDD2
Note 1
(2/2)
Conditions
HALT mode
Note 2
TYP.
MAX.
Unit
HS (high-speed main) fHOCO = 64 MHz,
VDD = 5.0 V
MIN.
0.80
4.36
mA
mode Note 7
fIH = 32 MHz Note 4
VDD = 3.0 V
0.80
4.36
fHOCO = 32 MHz,
VDD = 5.0 V
0.54
3.67
fIH = 32 MHz Note 4
VDD = 3.0 V
0.54
3.67
fHOCO = 48 MHz,
VDD = 5.0 V
0.62
3.42
fIH = 24 MHz Note 4
VDD = 3.0 V
0.62
3.42
fHOCO = 24 MHz,
VDD = 5.0 V
0.44
2.85
fIH = 24 MHz Note 4
VDD = 3.0 V
0.44
2.85
fHOCO = 16 MHz,
VDD = 5.0 V
0.40
2.08
fIH = 16 MHz Note 4
VDD = 3.0 V
0.40
2.08
Square wave input
0.28
2.45
Resonator connection
0.49
2.57
fMX = 20 MHz Note 3,
VDD = 3.0 V
Square wave input
0.28
2.45
Resonator connection
0.49
2.57
Note 3,
Square wave input
0.19
1.28
Resonator connection
0.30
1.36
Square wave input
0.19
1.28
Resonator connection
0.30
1.36
Square wave input
0.25
0.57
Resonator connection
0.44
0.76
fSUB = 32.768 kHz Note 5, Square wave input
TA = +25°C
Resonator connection
0.30
0.57
0.49
0.76
Square wave input
0.36
1.17
Resonator connection
0.59
1.36
fSUB = 32.768 kHz Note 5, Square wave input
TA = +70°C
Resonator connection
0.49
1.97
0.72
2.16
Square wave input
0.97
3.37
Resonator connection
1.16
3.56
fSUB = 32.768 kHz Note 5, Square wave input
TA = +105°C
Resonator connection
3.20
17.10
3.40
17.50
TA = -40°C
0.18
0.51
TA = +25°C
0.24
0.51
TA = +50°C
0.29
1.10
TA = +70°C
0.41
1.90
TA = +85°C
0.90
3.30
TA = +105°C
3.10
17.00
HS (high-speed main) fMX = 20 MHz
mode Note 7
VDD = 5.0 V
fMX = 10 MHz
VDD = 5.0 V
Note 3,
fMX = 10 MHz Note 3,
VDD = 3.0 V
Subsystem clock
operation
fSUB = 32.768 kHz
TA = -40°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
TA = +85°C
IDD3
STOP mode
Note 6
Note 8
Note 5,
Note 5,
Note 5,
mA
A
A
(Notes and Remarks are listed on the next page.)
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RL78/G1F
Note 1.
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2.
During HALT instruction execution by flash memory.
Note 3.
When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4.
When high-speed system clock and subsystem clock are stopped.
Note 5.
When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current
flowing into the 12-bit interval timer and watchdog timer.
Note 6.
Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
Note 7.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode:
2.7 V  VDD  5.5 [email protected] MHz to 32 MHz
2.4 V  VDD  5.5 [email protected] MHz to 16 MHz
Note 8.
Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
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RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Low-speed on-chip
oscillator operating current
IFIL Note 1
0.2
A
RTC operating current
IRTC Notes 1, 2, 3
0.02
A
12-bit interval timer
operating current
IIT Notes 1, 2, 4
0.02
A
Watchdog timer operating
current
IWDT Notes 1, 2, 5
fIL = 15 kHz
0.22
A
A/D converter operating
current
IADC Notes 1, 6
When conversion at maximum
speed
Normal mode,
AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode,
AVREFP = VDD = 3.0 V
0.5
0.7
mA
A/D converter reference
voltage current
IADREF Note 1
75
A
Temperature sensor
operating current
ITMPS Note 1
75
A
D/A converter operating
current
IDAC Notes 1, 11
PGA operating current
Comparator operating
current
Per D/A converter channel
1.5
mA
480
700
A
When the internal reference
voltage is not in use
50
100
A
When the internal reference
voltage is in use
60
110
A
Operation
ICMP Notes 1, 12
Operation (per comparator
channel, constant current for
comparator included)
A
LVD operating current
ILVD Notes 1, 7
0.08
Self-programming operating
current
IFSP Notes 1, 9
2.50
12.2
mA
BGO operating current
IBGO Notes 1, 8
2.50
12.2
mA
SNOOZE operating current
ISNOZ Note 1
The mode is performed Note 10
0.50
1.10
mA
The A/D conversion
operations are performed,
Low voltage mode,
AVREFP = VDD = 3.0 V
1.20
2.04
CSI/UART operation
0.70
1.54
DTC operation
3.10
ADC operation
Note 1.
Current flowing to VDD.
Note 2.
When high speed on-chip oscillator and high-speed system clock are stopped.
Note 3.
Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock.
Note 4.
Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 5.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in
operation.
Note 6.
Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7.
Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8.
Current flowing during programming of the data flash.
Note 9.
Current flowing during self-programming.
Note 10.
For shift time to the SNOOZE mode, see 26.3.3 SNOOZE mode in the RL78/G1F User’s Manual.
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RL78/G1F
Note 11.
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDAC when the D/A converter operates in an operation mode or the HALT mode.
Note 12.
Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25°C
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3.4
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
AC Characteristics
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Symbol
Conditions
MIN.
Main system
HS (high-speed main) 2.7 V  VDD  5.5 V
(minimum instruction
clock (fMAIN)
mode
execution time)
operation
Instruction cycle
TCY
2.4 V  VDD < 2.7 V
1
s
0.0625
1
s
s
s
0.0625
1
s
2.7 V  VDD  5.5 V
1.0
20.0
MHz
2.4 V  VDD  2.7 V
1.0
16.0
MHz
32
35
kHz
2.4 V  VDD < 2.7 V
mode
fEX
0.03125
1
HS (high-speed main) 2.7 V  VDD  5.5 V
programming mode
frequency
Unit
31.3
In the self-
2.4 V  VDD  5.5 V
TYP. MAX.
0.03125
Subsystem clock (fSUB) operation
External system clock
(1/2)
fEXS
28.5
30.5
External system clock
tEXH,
2.7 V  VDD  5.5 V
24
ns
input high-level width,
tEXL
2.4 V  VDD  2.7 V
30
ns
13.7
s
1/fMCK + 10
ns
low-level width
tEXHS,
tEXLS
TI00 to TI03 input
tTIH, tTIL
high-level width, low-
Note
level width
Timer RJ input cycle
fC
Timer RJ input high-
tTJIH,
level width, low-level
tTJIL
TRJIO
TRJIO
2.7 V  EVDD0  5.5 V
100
ns
2.4 V  EVDD0 < 2.7 V
300
ns
2.7 V  EVDD0  5.5 V
40
ns
120
ns
2.4 V  EVDD0 < 2.7 V
width
Note
The following conditions are required for low voltage interface when EVDD0 < VDD
2.4 V  EVDD0 < 2.7 V: MIN. 125 ns
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel
number (n = 0 to 3))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Items
Symbol
Conditions
Timer RD input high-level
tTDIH,
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
width, low-level width
tTDIL
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1
Timer RD forced cutoff signal
tTDSIL
P130/INTP0
input low-level width
2MHz < fCLK  32 MHz
fCLK  2 MHz
Timer RG input high-level
tTGIH,
width, low-level width
tTGIL
TO00 to TO03,
fTO
TRGIOA, TRGIOB
(2/2)
MIN.
TYP.
MAX.
Unit
3/fCLK
ns
1
s
1/fCLK + 1
2.5/fCLK
ns
4.0 V  EVDD0  5.5 V
16
MHz
TRJIO0, TRJO0,
2.7 V  EVDD0 < 4.0 V
8
MHz
TRDIOA0, TRDIOA1,
2.4 V  EVDD0 < 2.7 V
4
MHz
4.0 V  EVDD0  5.5 V
16
MHz
2.7 V  EVDD0 < 4.0 V
8
MHz
2.4 V  EVDD0 < 2.7 V
4
MHz
HS (high-speed main) mode
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA, TRGIOB
output frequency
PCLBUZ0, PCLBUZ1 output
fPCL
HS (high-speed main) mode
frequency
Interrupt input high-level
tINTH,
INTP0
2.4 V  VDD  5.5 V
1
s
width, low-level width
tINTL
INTP1 to INTP11
2.4 V  EVDD0  5.5 V
1
s
Key interrupt input low-level
tKR
KR0 to KR7
2.4 V  EVDD0  5.5 V
250
ns
10
s
width
RESET low-level width
tRSL
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [μs]
When the high-speed on-chip oscillator clock is selected
During self-programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
AC Timing Test Points
V IH /V OH
V IH /V OH
Test points
V IL/V OL
V IL/V OL
External System Clock Timing
1/fEX
1/fEXS
tEXL
tEXLS
tEXH
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
tTIH
TI00 to TI03, TI10 to TI13
1/fTO
TO00 to TO03, TO10 to TO13,
TRJIO0, TRJO0,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA, TRGIOB
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
tTJIH
tTJIL
TRJIO
tTDIH
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1
tTDSIL
INTP0
tTGIL
tTGIH
TRGIOA, TRGIOB
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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3.5
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Peripheral Functions Characteristics
AC Timing Test Points
V IH /V OH
V IH /V OH
Test points
V IL/V OL
V IL/V OL
3.5.1
Serial array unit
(1) During communication at same potential (UART mode)
(TA = -40 to +105°C, 2.4 V  EVDD0  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
Note 1
2.4 V  EVDD0  5.5 V
Theoretical value of the
Unit
MAX.
fMCK/12 Note 2
bps
2.6
Mbps
maximum transfer rate
fMCK = fCLK Note 3
Note 1.
Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2.
The following conditions are required for low voltage interface when EVDD0  VDD.
2.4 V  EVDD0  2.7 V: MAX.1.3 Mbps
Note 3.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V  VDD  5.5 V)
16 MHz (2.4 V  VDD  5.5 V)
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
UART mode connection diagram (during communication at same potential)
Rx
TxDq
RL78 microcontroller
User’s device
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remark 1. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
MIN.
2.7 V  EVDD0  5.5 V
Unit
MAX.
SCKp cycle time
tKCY1
tKCY1  2/fCLK
500
ns
SCKp high-/low-level width
tKH1,
tKL1
4.0 V  EVDD0  5.5 V
tKCY1/2 - 24
ns
2.7 V  EVDD0  5.5 V
tKCY1/2 - 36
ns
2.4 V  EVDD0  5.5 V
tKCY1/2 - 76
2.4 V  EVDD0  5.5 V
SIp setup time (to SCKp↑) Note 1
SIp hold time (from SCKp↑)
Note 2
Delay time from SCKp↓ to SOp output
tSIK1
250
ns
4.0 V  EVDD0  5.5 V
66
ns
2.7 V  EVDD0  5.5 V
66
ns
2.4 V  EVDD0  5.5 V
113
tKSI1
2.7 V  EVDD0  5.5 V
38
tKSO1
C = 20 pF Note 4
ns
50
ns
Note 3
Note 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 , 5, 7)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(1/2)
HS (high-speed main) mode
MIN.
SCKp cycle time
Note 5
tKCY2
4.0 V  EVDD0  5.5 V
SIp setup time
(to SCKp↑)
tKH2,
tKL2
tSIK2
Note 1
SIp hold time
MAX.
20 MHz  fMCK
16/fMCK
ns
fMCK  20 MHz
12/fMCK
ns
16 MHz  fMCK
16/fMCK
ns
fMCK  16 MHz
12/fMCK
ns
2.4 V  EVDD0  5.5 V
12/fMCK
and 1000
ns
4.0 V  EVDD0  5.5 V
tKCY2/2 - 14
ns
2.7 V  EVDD0  5.5 V
tKCY2/2 - 16
ns
2.4 V  EVDD0  5.5 V
1/fMCK + 36
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 40
ns
2.4 V  EVDD0  5.5 V
1/fMCK + 60
ns
1/fMCK + 62
ns
2.7 V  EVDD0  5.5 V
SCKp high-/
low-level width
Unit
tKSI2
(from SCKp↑) Note 2
Delay time from
SCKp↓ to SOp output
tKSO2
C = 30 pF Note 4
Note 3
Note 1.
2.7 V  EVDD0  5.5 V
2/fMCK + 66
ns
2.4 V  EVDD0  5.5 V
2/fMCK + 113
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
C is the load capacitance of the SOp output lines.
Note 5.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3, 5, 7)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
(2/2)
Conditions
HS (high-speed main) mode
MIN.
SSI00 setup time
tSSIK
DAPmn = 0
DAPmn = 1
SSI00 hold time
DAPmn = 0
tKSSI
DAPmn = 1
Caution
Unit
MAX.
2.7 V  EVDD0  5.5 V
240
ns
2.4 V  EVDD0  5.5 V
400
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 240
ns
2.4 V  EVDD0  5.5 V
1/fMCK + 400
ns
2.7 V  EVDD0  5.5 V
1/fMCK + 240
ns
2.4 V  EVDD0  5.5 V
1/fMCK + 400
ns
2.7 V  EVDD0  5.5 V
240
ns
2.4 V  EVDD0  5.5 V
400
ns
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78 microcontroller SIp
SOp
SCK
SO
User's device
SI
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
SCK00
SI00
RL78 microcontroller
SO00
SSI00
SCK
SO
User's device
SI
SSO
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
tKSSI
tSSIK
SSI00
(CSI00 only)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
tSSIK
tKSSI
SSI00
(CSI00 only)
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(4) During communication at same potential (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
MIN.
SCLr clock frequency
Hold time
when SCLr = “L”
Hold time
when SCLr = “H”
Data setup time (reception)
Data hold time (transmission)
fSCL
tLOW
tHIGH
tSU: DAT
tHD: DAT
Unit
MAX.
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1
kHz
2.4 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
100 Note 1
kHz
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
1200
ns
2.4 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
4600
ns
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
1200
ns
2.4 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
4600
ns
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 220 Note 2
ns
2.4 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
1/fMCK + 580 Note 2
ns
2.7 V  EVDD0  5.5 V,
Cb = 50 pF, Rb = 2.7 k
0
770
ns
2.4 V  EVDD0  5.5 V,
Cb = 100 pF, Rb = 3 k
0
1420
ns
Note 1.
The value must also be equal to or less than fMCK/4.
Note 2.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SDAr pin and the normal output mode for
the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1, 3, 5, 7),
h: POM number (h = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10, 11)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(1/2)
HS (high-speed main) mode
MIN.
Transfer rate
4.0 V  EVDD0  5.5 V,
reception
Unit
MAX.
fMCK/12 Note 1
bps
2.6
Mbps
fMCK/12 Note 1
bps
2.6
Mbps
fMCK/12
bps
2.7 V  Vb  4.0 V
Theoretical value of the maximum
transfer rate
fMCK = fCLK Note 3
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V
Theoretical value of the maximum
transfer rate
fMCK = fCLK Note 3
2.4 V  EVDD0  3.3 V,
1.6 V  Vb  2.0 V
Theoretical value of the maximum
transfer rate
Notes 1, 2
1.3
Mbps
fMCK = fCLK Note 3
Note 1.
Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2.
The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V  EVDD0  2.7 V: MAX. 2.6 Mbps
Note 3.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V  VDD  5.5 V)
1.8 V  EVDD0  2.4 V: MAX. 1.3 Mbps
16 MHz (2.4 V  VDD  5.5 V)
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remark 1. Vb [V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11)
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(2/2)
HS (high-speed main) mode
MIN.
Transfer rate
transmission
Unit
MAX.
4.0 V  EVDD0  5.5 V,
Note 1
bps
2.6 Note 2
Mbps
Note 3
bps
1.2 Note 4
Mbps
Note 5
bps
0.43 Note 6
Mbps
2.7 V  Vb  4.0 V
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 1.4 k,
Vb = 2.7 V
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 2.7 k,
Vb = 2.3 V
2.4 V  EVDD0  3.3 V,
1.6 V  Vb  2.0 V
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 5.5 k,
Vb = 1.6 V
Note 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V  EVDD0  5.5 V and 2.7 V  Vb  4.0 V
1
[bps]
Maximum transfer rate =
{-Cb  Rb  In (1 -
2.2
)}  3
Vb
1
Transfer rate  2
- {-Cb  Rb  In (1 -
2.2
)}
Vb
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Note 3.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.7 V  EVDD0 < 4.0 V and 2.3 V  Vb  2.7 V
1
[bps]
Maximum transfer rate =
2.0
)}  3
{-Cb  Rb  In (1 Vb
1
Transfer rate  2
- {-Cb  Rb  In (1 -
2.0
)}
Vb
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
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Note 5.
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.4 V  EVDD0 < 3.3 V and 1.6 V  Vb  2.0 V
1
[bps]
Maximum transfer rate =
{-Cb  Rb  In (1 -
1.5
)}  3
Vb
1
Transfer rate  2
- {-Cb  Rb  In (1 -
1.5
)}
Vb
 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
)  Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 6.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(6) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(1/3)
HS (high-speed main) mode
MIN.
SCKp cycle time
SCKp high-level width
SCKp low-level width
Caution
tKCY1
tKH1
tKL1
tKCY1  4/fCLK
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
600
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
1000
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
2300
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 150
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 340
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 916
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 24
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 36
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 100
ns
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
(Remarks are listed two pages after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +105°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(2/3)
HS (high-speed main) mode
MIN.
SIp setup time (to SCKp↑) Note
SIp hold time (from SCKp↑) Note
Delay time from SCKp↓ to SOp output Note
Note
Caution
tSIK1
tKSI1
tKSO1
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
162
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
354
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
958
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
38
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
38
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
38
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
200
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
390
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
966
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
(Remarks are listed on the page after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +105°C, 1.8 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(3/3)
HS (high-speed main) mode
MIN.
SIp setup time (to SCKp↓) Note
SIp hold time (from SCKp↓) Note
Delay time from SCKp↑ to SOp output Note
Note
Caution
tSIK1
tKSI1
tKSO1
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
88
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
88
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
220
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
38
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
38
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
38
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
50
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
50
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 30 pF, Rb = 5.5 k
50
ns
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin
products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode connection diagram (during communication at different potential
<Master>
Vb
Vb
Rb
SCKp
RL78 microcontroller
Rb
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
Remark 4. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 2. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
MIN.
SCKp cycle time Note 1
tKCY2
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V
2.7 V  EVDD0  4.0 V,
2.3 V  Vb  2.7 V
2.4 V  EVDD0  3.3 V,
1.6 V  Vb  2.0 V
24 MHz  fMCK
28/fMCK
ns
20 MHz  fMCK  24 MHz
24/fMCK
ns
8 MHz  fMCK  20 MHz
20/fMCK
ns
4 MHz  fMCK  8 MHz
16/fMCK
ns
fMCK  4 MHz
12/fMCK
ns
24 MHz  fMCK
40/fMCK
ns
20 MHz  fMCK  24 MHz
32/fMCK
ns
16 MHz  fMCK  20 MHz
28/fMCK
ns
8 MHz  fMCK  16 MHz
24/fMCK
ns
4 MHz  fMCK  8 MHz
16/fMCK
ns
fMCK  4 MHz
12/fMCK
ns
24 MHz  fMCK
96/fMCK
ns
20 MHz  fMCK  24 MHz
72/fMCK
ns
16 MHz  fMCK  20 MHz
64/fMCK
ns
8 MHz  fMCK  16 MHz
52/fMCK
ns
4 MHz  fMCK  8 MHz
32/fMCK
ns
20/fMCK
ns
tKCY2/2 - 24
ns
fMCK  4 MHz
SCKp high-/low-level
width
SIp setup time
tKH2, tKL2
tSIK2
(to SCKp↑) Note 2
SIp hold time
Unit
MAX.
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V
2.7 V  EVDD0  4.0 V, 2.3 V  Vb  2.7 V
tKCY2/2 - 36
ns
2.4 V  EVDD0  3.3 V, 1.6 V  Vb  2.0 V
tKCY2/2 - 100
ns
2.7 V  EVDD0  4.0 V, 2.3 V  Vb  2.7 V
1/fMCK + 40
ns
2.4 V  EVDD0  3.3 V, 1.6 V  Vb  2.0 V
1/fMCK + 60
ns
1/fMCK + 62
ns
tKSI2
(from SCKp↑) Note 3
Delay time from SCKp
tKSO2
to SOp output Note 4
4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
Cb = 30 pF, Rb = 1.4 k
2/fMCK + 240
ns
2.7 V  EVDD0  4.0 V, 2.3 V  Vb  2.7 V,
Cb = 30 pF, Rb = 2.7 k
2/fMCK + 428
ns
2.4 V  EVDD0  3.3 V, 1.6 V  Vb  2.0 V,
Cb = 30 pF, Rv = 5.5 k
2/fMCK + 1146
ns
(Notes and Remarks are listed on the next page.)
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Note 1.
Note 2.
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5.
Select the TTL input buffer for the SIp pin and SCKp pin, and the N-ch open drain output (VDD tolerance (for the
48, 32, 24-pin products)/EVDD tolerance (for the 64, 36-pin products)) mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10))
Remark 4. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3, 5, 7)
Remark 2. CSI01 of 48-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
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Apr 06, 2015
Page 120 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(1/2)
HS (high-speed main) mode
MIN.
SCLr clock frequency
Hold time when SCLr = “L”
Hold time when SCLr = “H”
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
fSCL
tLOW
tHIGH
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1
kHz
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1
kHz
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
100 Note 1
kHz
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
100 Note 1
kHz
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 100 pF, Rb = 5.5 k
100 Note 1
kHz
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
1200
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
1200
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
4600
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
4600
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 100 pF, Rb = 5.5 k
4650
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
620
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
500
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
2700
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
2400
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 100 pF, Rb = 5.5 k
1830
ns
Page 121 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
(2/2)
HS (high-speed main) mode
MIN.
Data setup time (reception)
Data hold time (transmission)
tSU:DAT
tHD:DAT
Unit
MAX.
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340 Note 2
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340 Note 2
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK + 760 Note 2
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK + 760 Note 2
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 100 pF, Rb = 5.5 k
1/fMCK + 570 Note 2
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 50 pF, Rb = 2.7 k
0
770
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 50 pF, Rb = 2.7 k
0
770
ns
4.0 V  EVDD0  5.5 V,
2.7 V  Vb  4.0 V,
Cb = 100 pF, Rb = 2.8 k
0
1420
ns
2.7 V  EVDD0 < 4.0 V,
2.3 V  Vb  2.7 V,
Cb = 100 pF, Rb = 2.7 k
0
1420
ns
2.4 V  EVDD0 < 3.3 V,
1.6 V  Vb  2.0 V,
Cb = 100 pF, Rb = 5.5 k
0
1215
ns
Note 1.
The value must also be equal to or less than fMCK/4.
Note 2.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin products)/EVDD
tolerance (for the 64-, 36-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (for
the 48-, 32-, 24-pin products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SCLr pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20), g: PIM, POM number (g = 0, 1, 3, 5, 7)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 00, 01, 02, 10)
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RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.5.2
Serial interface IICA
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
Standard mode
Fast mode: fCLK  3.5 MHz
Unit
Fast mode
MIN.
MAX.
MIN.
MAX.
—
—
0
400
kHz
0
100
—
—
kHz
SCLA0 clock frequency
fSCL
Setup time of restart condition
tSU: STA
4.7
0.6
s
Hold time Note 1
tHD: STA
4.0
0.6
s
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
s
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
s
Data setup time (reception)
tSU: DAT
250
Data hold time (transmission) Note 2
tHD: DAT
0
Setup time of stop condition
tSU: STO
4.0
0.6
s
Bus-free time
tBUF
4.7
1.3
s
Standard mode: fCLK  1 MHz
100
3.45
0
ns
0.9
s
Note 1.
The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2.
The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution
The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode:
Cb = 400 pF, Rb = 2.7 k
Fast mode:
Cb = 320 pF, Rb = 1.1 k
IICA serial transfer timing
tLOW
SCLAn
tHD: DAT
tHD: STA
tHIGH
tSU: STA
tHD: STA
tSU: STO
tSU: DAT
SDAAn
tBUF
Stop
condition
Remark
Start
condition
Restart
condition
Stop
condition
n = 0, 1
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3.6
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Analog Characteristics
3.6.1
A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (-) = AVREFM
Input channel
ANI0 to ANI7
Refer to 3.6.1 (1).
ANI16 to ANI24
Refer to 3.6.1 (2).
Internal reference voltage
Temperature sensor output voltage
Refer to 3.6.1 (1).
Reference voltage (+) = VDD
Reference voltage (-) = VSS
Refer to 3.6.1 (3).
Reference voltage (+) = VBGR
Reference voltage (-)= AVREFM
Refer to 3.6.1 (4).
—
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 to ANI7, internal reference voltage, and temperature sensor
output voltage
(TA = -40 to +105°C, 2.4 V  AVREFP  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (-) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall error Note 1
AINL
Conditions
MIN.
TYP.
MAX.
Unit
10
bit
3.5
LSB
8
10-bit resolution
2.4 V  AVREFP  5.5 V
1.2
AVREFP = VDD Note 3
Conversion time
Zero-scale error
tCONV
Notes 1, 2
EZS
10-bit resolution
Target pin: ANI2 to ANI14
3.6 V  VDD  5.5 V
2.125
39
s
2.7 V  VDD  5.5 V
3.1875
39
s
2.4 V  VDD  5.5 V
17
39
s
10-bit resolution
Target pin: Internal reference voltage,
and temperature sensor output
voltage (HS (high-speed main) mode)
3.6 V  VDD  5.5 V
2.375
39
s
2.7 V  VDD  5.5 V
3.5625
39
s
2.4 V  VDD  5.5 V
17
39
s
10-bit resolution
2.4 V  AVREFP  5.5 V
0.25
%FSR
2.4 V  AVREFP  5.5 V
0.25
%FSR
2.4 V  AVREFP  5.5 V
2.5
LSB
2.4 V  AVREFP  5.5 V
1.5
LSB
AVREFP
V
AVREFP = VDD Note 3
Full-scale error Notes 1, 2
EFS
10-bit resolution
AVREFP = VDD Note 3
Integral linearity error Note 1
ILE
10-bit resolution
AVREFP = VDD Note 3
Differential linearity error Note 1
DLE
10-bit resolution
AVREFP = VDD Note 3
Analog input voltage
VAIN
ANI2 to ANI7
0
Internal reference voltage output
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VBGR Note 4
V
Temperature sensor output voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VTMPS25 Note 4
V
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3.
When AVREFP < VDD, the MAX. values are as follows.
Overall error:
Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error:
Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4.
Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI24
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, 2.4 V  AVREFP  VDD  5.5 V,
VSS = EVSS0 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall error Note 1
AINL
Conditions
MIN.
TYP.
8
2.4 V  AVREFP  5.5 V
10-bit resolution
1.2
MAX.
Unit
10
bit
5.0
LSB
39
s
EVDD0  AVREFP = VDD Notes 3, 4
Conversion time
Zero-scale error
tCONV
Notes 1, 2
EZS
10-bit resolution
Target ANI pin: ANI16 to ANI20
10-bit resolution
3.6 V  VDD  5.5 V
2.125
2.7 V  VDD  5.5 V
3.1875
39
s
2.4 V  VDD  5.5 V
17
39
s
2.4 V  AVREFP  5.5 V
0.35
%FSR
2.4 V  AVREFP  5.5 V
0.35
%FSR
2.4 V  AVREFP  5.5 V
3.5
LSB
2.4 V  AVREFP  5.5 V
2.0
LSB
AVREFP
and
EVDD0
V
EVDD0  AVREFP = VDD Notes 3, 4
Full-scale error Notes 1, 2
EFS
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Integral linearity error Note 1
ILE
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Differential linearity error Note 1
DLE
10-bit resolution
EVDD0  AVREFP = VDD Notes 3, 4
Analog input voltage
VAIN
ANI16 to ANI24
0
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3.
When EVDD0  AVREFP  VDD, the MAX. values are as follows.
Overall error:
Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error:
Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4.
When AVREFP < EVDD0  VDD, the MAX. values are as follows.
Overall error:
Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error:
Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
R01DS0246EJ0100 Rev. 1.00
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0),
target pin: ANI0 to ANI7, ANI16 to ANI24, internal reference voltage, and temperature sensor output
voltage
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V, Reference voltage (+) = VDD, Reference
voltage (-) = VSS)
Parameter
Resolution
Overall error
Symbol
Conditions
MIN.
RES
Note 1
Conversion time
TYP.
MAX.
10
bit
1.2
7.0
LSB
8
Unit
AINL
10-bit resolution
2.4 V  VDD  5.5 V
tCONV
10-bit resolution
Target pin: ANI0 to ANI14, ANI16 to ANI20
3.6 V  VDD  5.5 V
2.125
39
s
2.7 V  VDD  5.5 V
3.1875
39
s
2.4 V  VDD  5.5 V
17
39
s
10-bit resolution
Target pin: internal reference voltage, and
temperature sensor output voltage
(HS (high-speed main) mode)
3.6 V  VDD  5.5 V
2.375
39
s
2.7 V  VDD  5.5 V
3.5625
39
s
2.4 V  VDD  5.5 V
17
39
s
EZS
10-bit resolution
2.4 V  VDD  5.5 V
0.60
%FSR
EFS
10-bit resolution
2.4 V  VDD  5.5 V
0.60
%FSR
Integral linearity error Note 1
ILE
10-bit resolution
2.4 V  VDD  5.5 V
4.0
LSB
Differential linearity error
DLE
10-bit resolution
2.4 V  VDD  5.5 V
2.0
LSB
Zero-scale error
Full-scale error
Notes 1, 2
Notes 1, 2
Note 1
Analog input voltage
VAIN
ANI0 to ANI7
0
VDD
V
ANI16 to ANI24
0
EVDD0
V
Internal reference voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VBGR Note 3
V
Temperature sensor output voltage
(2.4 V  VDD  5.5 V, HS (high-speed main) mode)
VTMPS25 Note 3
V
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3.
Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 to ANI7, ANI16 to ANI24
(TA = -40 to +105°C, 2.4 V  VDD  5.5 V, 2.4 V  EVDD0  VDD, VSS = EVSS0 = 0 V, Reference voltage (+) = VBGR Note 3,
Reference voltage (-) = AVREFM = 0 V Note 4, HS (high-speed main) mode)
Parameter
Symbol
Conditions
Resolution
RES
Conversion time
tCONV
8-bit resolution
2.4 V  VDD  5.5 V
Zero-scale error Notes 1, 2
EZS
8-bit resolution
Integral linearity error Note 1
ILE
Differential linearity error Note 1
DLE
Analog input voltage
VAIN
MIN.
TYP.
MAX.
8
bit
39
s
2.4 V  VDD  5.5 V
0.60
% FSR
8-bit resolution
2.4 V  VDD  5.5 V
2.0
LSB
8-bit resolution
2.4 V  VDD  5.5 V
1.0
LSB
VBGR Note 3
V
17
0
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3.
Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
Note 4.
When reference voltage (-) = VSS, the MAX. values are as follows.
Zero-scale error:
Add ±0.35%FSR to the MAX. value when reference voltage (-) = AVREFM.
Integral linearity error:
Add ±0.5 LSB to the MAX. value when reference voltage (-) = AVREFM.
Differential linearity error:
Add ±0.2 LSB to the MAX. value when reference voltage (-) = AVREFM.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Unit
Page 128 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.6.2
Temperature sensor characteristics/internal reference voltage characteristic
(TA = -40 to +105°C, 2.4 V  VDD  5.5 V, VSS = EVSS0 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
1.38
3.6.3
tAMP
MAX.
1.05
Unit
V
1.45
1.5
V
mV/C
-3.6
temperature
Operation stabilization wait time
TYP.
s
5
D/A converter characteristics
(TA = -40 to +105°C, 2.4 V EVSS0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
bit
Resolution
RES
Overall error
AINL
Rload = 4 M
2.4 V  VDD  5.5 V
2.5
LSB
Rload = 8 M
2.4 V  VDD  5.5 V
2.5
LSB
Settling time
tSET
Cload = 20 pF
2.7 V  VDD  5.5 V
3
s
2.4 V  VDD < 2.7 V
6
s
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 129 of 140
RL78/G1F
3.6.4
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Comparator
(TA = -40 to +105°C, 2.7 V  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Input offset voltage
VIOCMP
Input voltage range
VICMP
Internal reference
voltage deviation
∆VIREF
Response Time
tCR, tCF
Conditions
MIN.
MAX.
Unit
5
40
mV
VDD
V
CmRVM register value : 7FH to 80H (m = 0, 1)
0
2
LSB
Other than above
1
LSB
150
ns
VDD = 3.3 to 5.5 V
1
s
VDD = 2.7 to 3.3 V
3
s
20
s
Input amplitude±100mV
70
Operation stabilization tCMP
timeNote 1
CMPn = 0→1
Reference voltage
stabilization wait time
tVR
CVRE : 0→1Note 2
Operation current
ICMPDD
Separately, it is defined as the operation current of peripheral functions.
Note 1.
TYP.
Time taken until the comparator satisfies the DC/AC characteristics after the comparator operation enable signal is
switched (CMPnEN = 0 → 1).
Note 2.
3.6.5
Enable comparator output (CnOE bit = 1; n = 0 to 1) after enabling operation of the internal reference voltage generator
(by setting the CVREm bit to 1; m = 0 to 1) and waiting for the operation stabilization time to elapse.
PGA
(TA = -40 to +105°C, 2.7 V  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Input offset voltage
VIOPGA
Input voltage range
VIPGA
Output voltage range
VIOHPGA
Conditions
MIN.
TYP.
0
<R>
SRRPGA
<R>
SRFPGA
Reference voltage
stabilization wait
timeNote 1
tPGA
Operation current
IPGADD
Note 1.
10
mV
0.9 
VDD/Gain
V
V
0.07  VDD
V
1
%
x16
1.5
%
x32
2
%
x4, x8
Slew rate
Unit
0.93  VDD
VIOLPGA
Gain error
MAX.
Rising
When Vin= 0.1VDD/gain
to 0.9VDD/gain.
10 to 90% of output
voltage amplitude
Falling
When Vin= 0.1VDD/gain
to 0.9VDD/gain.
90 to 10% of output
voltage amplitude
4.0 V ≤ VDD ≤ 5.5 V
3.5
V/μs
(Other than x32)
4.0 V ≤ VDD ≤ 5.5 V (x32)
3.0
2.7 V ≤ VDD ≤ 4.0V
0.5
4.0 V ≤ VDD ≤ 5.5 V
3.5
(Other than x32)
4.0 V ≤ VDD ≤ 5.5 V (x32)
3.0
2.7 V ≤ VDD ≤ 4.0V
0.5
x4, x8
5
μs
x16, x32
10
μs
Separately, it is defined as the operation current of peripheral functions.
Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA
operation has been enabled (PGAEN = 1).
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 130 of 140
RL78/G1F
3.6.6
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
POR circuit characteristics
(TA = -40 to +105°C, VSS = 0 V)
Parameter
Symbol
Power on/down reset threshold VPOR
VPDR
Minimum pulse width
Note 1.
Note 2
Conditions
Voltage threshold on VDD rising
Voltage threshold on VDD falling
Note 1
TPW
MIN.
TYP.
MAX.
Unit
1.45
1.51
1.55
V
1.44
1.50
1.54
V
s
300
However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 3.4 AC Characteristics.
Note 2.
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 131 of 140
RL78/G1F
3.6.7
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
LVD circuit characteristics
(1) Reset Mode and Interrupt Mode
(TA = -40 to +105°C, VPDR  VDD  5.5 V, VSS = 0 V)
Parameter
Voltage detection
Supply voltage level
Symbol
VLVD0
threshold
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Minimum pulse width
Detection delay time
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
tLW
MIN.
TYP.
MAX.
Unit
Rising edge
Conditions
3.90
4.06
4.22
V
Falling edge
3.83
3.98
4.13
V
Rising edge
3.60
3.75
3.90
V
Falling edge
3.53
3.67
3.81
V
Rising edge
3.01
3.13
3.25
V
Falling edge
2.94
3.06
3.18
V
Rising edge
2.90
3.02
3.14
V
Falling edge
2.85
2.96
3.07
V
Rising edge
2.81
2.92
3.03
V
Falling edge
2.75
2.86
2.97
V
Rising edge
2.70
2.81
2.92
V
Falling edge
2.64
2.75
2.86
V
Rising edge
2.61
2.71
2.81
V
Falling edge
2.55
2.65
2.75
V
Rising edge
2.51
2.61
2.71
V
Falling edge
2.45
2.55
2.65
V
s
300
300
s
Page 132 of 140
RL78/G1F
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(2) Interrupt & Reset Mode
(TA = -40 to +105°C, VPDR  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Voltage detection
VLVDD0
threshold
VLVDD1
Conditions
LVIS1, LVIS0 = 1, 0
VLVDD2
LVIS1, LVIS0 = 0, 1
VLVDD3
3.6.8
MIN.
TYP.
MAX.
Unit
2.64
2.75
2.86
V
Rising release reset voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
Rising release reset voltage
2.90
3.02
3.14
V
Falling interrupt voltage
2.85
2.96
3.07
V
Rising release reset voltage
3.90
4.06
4.22
V
Falling interrupt voltage
3.83
3.98
4.13
V
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
LVIS1, LVIS0 = 0, 0
Power supply voltage rising slope characteristics
(TA = -40 to +105°C, VSS = 0 V)
Parameter
Symbol
Power supply voltage rising slope
Caution
Conditions
MIN.
TYP.
SVDD
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 3.4 AC Characteristics.
3.7
RAM Data Retention Characteristics
(TA = -40 to +105°C, VSS = 0V)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.44
TYP.
Notes 1, 2
MAX.
Unit
5.5
V
Note 1.
The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset
is effected, but RAM data is not retained when a POR reset is effected.
Note 2.
Enter STOP mode before the supply voltage falls below the recommended operating voltage.
STOP mode
Operation mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 133 of 140
RL78/G1F
3.8
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Flash Memory Programming Characteristics
(TA = -40 to +105°C, 2.4 V  VDD  5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
System clock frequency
fCLK
2.4 V  VDD  5.5 V
Number of code flash rewrites
Cerwr
Retained for 20 years
TA = 85°C
Number of data flash rewrites
Retained for 1 year
TA = 25°C
Notes 1, 2, 3
Retained for 5 years
TA = 85°C
100,000
Retained for 20 years
TA = 85°C
10,000
TYP.
1
MAX.
Unit
32
MHz
1,000
Times
Notes 1, 2, 3
1,000,000
Note 1.
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
Note 2.
When using flash memory programmer and Renesas Electronics self-programming library
Note 3.
These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
3.9
Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Transfer rate
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Symbol
Conditions
During serial programming
MIN.
115,200
TYP.
MAX.
Unit
1,000,000 bps
Page 134 of 140
RL78/G1F
3.10
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Timing of Entry to Flash Memory Programming Modes
(TA = -40 to +105°C, 2.4 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
How long from when an external reset ends until the
tSUINIT
initial communication settings are specified
Conditions
MIN.
POR and LVD reset must end
TYP.
MAX.
Unit
100
ms
before the external reset ends.
How long from when the TOOL0 pin is placed at the
tSU
low level until an external reset ends
POR and LVD reset must end
10
s
1
ms
before the external reset ends.
How long the TOOL0 pin must be kept at the low
tHD
level after an external reset ends
(excluding the processing time of the firmware to
POR and LVD reset must end
before the external reset ends.
control the flash memory)
<1>
<2>
<3>
<4>
RESET
723 µs + tHD
00H reception
processing
(TOOLRxD, TOOLTxD mode)
time
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 135 of 140
RL78/G1F
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1
24-pin products
R5F11B7CANA, R5F11B7EANA, R5F11B7CGNA, R5F11B7EGNA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN24-4x4-0.50
PWQN0024KE-A
P24K8-50-CAB-1
0.04
D
DETAIL OF A PART
E
S
A
A
S
y
S
(UNIT:mm)
ITEM
D2
A
EXPOSED DIE PAD
1
6
D
4.00 ± 0.05
E
4.00 ± 0.05
A
0.75 ± 0.05
b
+
0.25 − 0.05
0.07
e
7
24
Lp
B
DIMENSIONS
0.50
0.40 ± 0.10
x
0.05
y
0.05
E2
ITEM
19
12
18
EXPOSED
DIE PAD
VARIATIONS
13
D2
E2
MIN NOM MAX MIN NOM MAX
A 2.45 2.50 2.55 2.45 2.50 2.55
e
Lp
b
x
M
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 136 of 140
RL78/G1F
4.2
4. PACKAGE DRAWINGS
32-pin products
R5F11BBCAFP, R5F11BBEAFP, R5F11BBCGFP, R5F11BBEGFP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP32-7x7-0.80
PLQP0032GB-A
P32GA-80-GBT-1
0.2
HD
2
D
17
16
24
25
detail of lead end
1
E
c
HE
θ
32
8
1
L
9
e
(UNIT:mm)
3
b
x
M
A
A2
ITEM
D
DIMENSIONS
7.00±0.10
E
7.00±0.10
HD
9.00±0.20
HE
9.00±0.20
A
1.70 MAX.
A1
0.10±0.10
A2
y
A1
1.40
b
0.37±0.05
c
0.145 ±0.055
L
0.50±0.20
θ
0° to 8°
e
0.80
1.Dimensions “ 1” and “ 2” do not include mold flash.
x
0.20
2.Dimension “ 3” does not include trim offset.
y
0.10
NOTE
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
Page 137 of 140
RL78/G1F
4.3
4. PACKAGE DRAWINGS
36-pin products
R5F11BCCALA, R5F11BCEALA, R5F11BCCGLA, R5F11BCEGLA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-WFLGA36-4x4-0.50
PWLG0036KA-A
P36FC-50-AA4-2
0.023
32x b
S AB
e
ZE
w S A
M
A
ZD
D
x
6
5
B
4
E
3
2.90
2
C
INDEX MARK
y1
D
w S B
S
1
F
E D C B A
E
2.90
A
S
y
S
DETAIL C
DETAIL E
DETAIL D
R0.17± 0.05
0.70 ±0.05
0.55 ±0.05 R0.12 ±0.05
0.75
0.55
(UNIT:mm)
R0.17 ±0.05
0.70 ±0.05
R0.12 ±0.05 0.55 ±0.05
0.75
0.55
φb
(LAND PAD)
φ 0.34±0.05
(APERTURE OF
SOLDER RESIST)
0.55
0.75
0.55±0.05
0.70± 0.05
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
0.55
0.75
0.55±0.05
R0.275±0.05
R0.35±0.05
ITEM
D
DIMENSIONS
E
4.00±0.10
w
0.20
4.00±0.10
e
0.50
A
0.69±0.07
b
0.24±0.05
x
0.05
y
0.08
y1
0.20
ZD
0.75
ZE
0.75
0.70±0.05
Page 138 of 140
RL78/G1F
4.4
4. PACKAGE DRAWINGS
48-pin products
R5F11BGCAFB, R5F11BGEAFB, R5F11BGCGFB, R5F11BGEGFB
JEITA Package Code
P-LFQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
48
13
1
ZE
Terminal cross section
12
c
A
F
A2
Index mark
ZD
S
A1
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
*3
bp
Detail F
x
8.8
8.8
0
0.17
0.09
0°
L1
y S
Min
6.9
6.9
e
x
y
ZD
ZE
L
L1
0.35
Nom Max
7.0 7.1
7.0 7.1
1.4
9.0 9.2
9.0 9.2
1.7
0.1 0.2
0.22 0.27
0.20
0.145 0.20
0.125
8°
0.5
0.08
0.10
0.75
0.75
0.5 0.65
1.0
Page 139 of 140
RL78/G1F
4.5
4. PACKAGE DRAWINGS
64-pin products
R5F11BLCAFB, R5F11BLEAFB, R5F11BLCGFB, R5F11BLEGFB
JEITA Package Code
P-LFQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c1
Terminal cross section
ZE
17
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
16
Index mark
ZD
c
A
*3
A1
y S
e
A2
F
S
bp
L
x
L1
Detail F
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
Page 140 of 140
REVISION HISTORY
Rev.
Date
0.10
0.50
Jan 14, 2015
Description
Page
First Edition issued
3
Modification of description in Figure 1 - 1 Part Number, Memory Size, and
Package of RL78/G1F
10
Addition of description in 1.4 Pin Identification
11
Modification of description in 1.5 Block Diagram
Modification of description in 1.6 Outline of Functions
14
Addition of target products to the beginning
17
Modification of 2.2.2 On-chip oscillator characteristics
18
23, 25, 27
Addition of note 4 in 2.3.1 Pin characteristics
Modification of 2.3.2 Supply current characteristics
73
Modification of 2.6.4 Comparator
73
Modification of 2.6.5 PGA
77
Renamed to 2.7 RAM Data Retention Characteristics
79
Addition of target products to the beginning
83
Modification of 3.2.2 On-chip oscillator characteristics
87
Modification of “Output voltage, low”
89, 91, 93
Jan 14, 2015
Summary
—
12, 13
1.00
RL78/G1F Datasheet
Modification of 3.3.2 Supply current characteristics
130
Modification of 3.6.4 Comparator
130
Modification of 3.6.5 PGA
133
Renamed to 3.7 RAM Data Retention Characteristics
All
Modification of the unit symbol (PWMOP into PWMOPA)
1
Modification of descriptions in 1.1 Features
10
Modification of 1.4 Pin Identification
13
Modification of 1.6 Outline of Functions
73
Modification of 2.6.5 PGA
130
Modification of 3.6.5 PGA
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C-1
Notes for CMOS devices
(1) Voltage
application
wafeform at input
pin:
Waveform distortion due to input noise or a reflected wave may cause
malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through
the area between VIL (MAX) and VIH (MIN).
(2) Handling of
unused input pins:
Unconnected CMOS device inputs can be cause of malfunction. If an input pin
is unconnected, it is possible that an internal input level may be generated due
to noise, etc., causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or
low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an
output pin. All handling related to unused pins must be judged separately for
each device and according to related specifications governing the device.
(3) Precaution
against ESD:
A strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it when it has occurred. Environmental control must be adequate.
When it is dry, a humidifier should be used. It is recommended to avoid using
insulators that easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or
conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands.
Similar precautions need to be taken for PW boards with mounted
semiconductor devices.
(4) Status before
initialization:
Power-on does not necessarily define the initial status of a MOS device.
Immediately after the power source is turned ON, devices with reset functions
have not yet been initialized. Hence, power-on does not guarantee output pin
levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after
power-on for devices with reset functions.
(5) Power ON/OFF
sequence:
In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply
after switching on the internal power supply. When switching the power supply
off, as a rule, switch off the external power supply and then the internal power
supply. Use of the reverse power on/off sequences may result in the
application of an overvoltage to the internal elements of the device, causing
malfunction and degradation of internal elements due to the passage of an
abnormal current. The correct power on/off sequence must be judged
separately for each device and according to related specifications governing
the device.
(6) Input of signal
during power off
state:
Do not input signals or an I/O pull-up power supply while the device is not
powered. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that
passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each
device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
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Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
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Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2015 Renesas Electronics Corporation. All rights reserved.
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