Datasheet - STMicroelectronics

Datasheet - STMicroelectronics
STM8TL52x4 STM8TL53x4
8-bit ultra-low-power touch sensing microcontroller with
16 Kbyte Flash, ProxSense™, timers, USART, SPI, I2C
Datasheet - production data
Features
 Operating conditions
– Operating power supply: 1.65 V to 3.6 V
– Temperature range: –40 °C to 85 °C
 Low power features
– 4 low power modes: Wait, Active-halt with
AWU (1 µA), Active-halt with ProxSense™
(10 µA with scan every 200 ms),
Halt (0.4 µA)
– Dynamic power consumption: 150 µA/MHz
– Fast wakeup from Halt mode: 4.7 µs
– Ultra-low leakage per I/O: 50 nA
 Advanced STM8 Core
– Harvard architecture with 3-stage pipeline
– Max freq.16 MHz,16 CISC MIPS peak
 Memories
– Up to 16 Kbyte of Flash program including
up to 2 Kbyte of data EEPROM
– Error correction code (ECC)
– Flexible write and read protection modes
– In-application and in-circuit programming
– Data EEPROM capability
– 4 Kbyte of static RAM

Clock management
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
driving both the IWDG and the AWU
 Reset and supply management
– Ultra-low-power, ultra safe power-on reset/
power-down reset
 Interrupt management
– Nested interrupt controller with software
priority control
– Up to 22 external interrupt sources
5&1&0.
XMM
This is information on a product in full production.
433/0
 I/Os
– Up to 23 with 22 mappable on external
interrupt vectors
– I/Os with programmable input pull-ups, high
sink/source capability
 ProxSense™ patented acquisition technology
with up to 300 touch sensing channels (20
receiver/transmitter channels and 15
transmitter channels) supporting projected
capacitive acquisition method suitable for
proximity detection.
 Timers
– Two 16-bit general purpose timers (TIM2
and TIM3) with up and down counter and
two channels (used as IC, OC, PWM)
– One 8-bit timer (TIM4) with 7-bit prescaler
– Independent watchdog
– Window watchdog
– Auto-wakeup unit
– Beeper timer with 1, 2 or 4 kHz frequencies
 Communication interfaces
– SPI synchronous serial interface
– Fast I2C Multimaster/slave 400 kHz
– USART with fractional baud rate generator
 Development support
– Hardware single wire interface module
(SWIM)
– In-circuit emulation (ICE)
Table 1. Device summary
Reference
July 2015
5&1&0.
XMM
Part number
STM8TL52x4
STM8TL52F4, STM8TL52G4
STM8TL53x4
STM8TL53C4, STM8TL53F4, STM8TL53G4
DocID022344 Rev 7
1/84
www.st.com
Contents
STM8TL52x4 STM8TL53x4
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 13
3.4
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.1
Dual-mode voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.2
ProxSense voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9
System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.11
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.12
Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.13
General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.14
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.15
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.16
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.17
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.18
ProxSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.19
TouchSensing dedicated library available upon request . . . . . . . . . . . . . 17
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2/84
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Contents
7
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
9.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.4
10
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3.2
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3.3
Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 46
9.3.4
ProxSense Regulator Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3.6
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3.7
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3.8
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.3.9
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.1
ECOPACK®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3
UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.4
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.1
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.1.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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12.2
13
4/84
12.1.2
STM-STUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.1.3
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Legends/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8TL5xx4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ProxSense voltage regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Total current consumption in Halt mode and Active-halt mode
VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ProxSense peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
HSI_PXS oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Program memory endurance and retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Data memory endurance and retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, 
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DocID022344 Rev 7
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List of tables
Table 45.
6/84
STM8TL52x4 STM8TL53x4
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
STM8TL5xx4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8TL53 48-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM8TL53G4U6 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM8TL52G4U6 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM8TL53F4P6 TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM8TL52F4P6 TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
IDD(Wait) vs. VDD. fCPU = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typ. IDD(Halt) vs. VDD. fCPU = 2 MHz and 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical HSI accuracy vs. temperature, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Typical VIL and VIH vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typ. VOL at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Typ. VOL at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typ. VDD - VOH at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typ. VDD - VOH at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typ. VDD - VOH at VDD = 1.8 V (ProxSense TX ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typ. VDD - VOH at VDD = 1.8V (ProxSense RX ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
UFQFPN28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, 
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DocID022344 Rev 7
7/84
7
Introduction
1
STM8TL52x4 STM8TL53x4
Introduction
This datasheet provides the STM8TL52G4, STM8TL52F4, STM8TL53C4, STM8TL53G4
and STM8TL53F4 pinouts, ordering information, mechanical and electrical device
characteristics.
For complete information on the microcontroller memory, registers and peripherals, please
refer to the STM8TL5xxx reference manual (RM0312) and to the STM8TL5xxx Flash
programming manual (PM0212) for Flash memory related information. For information on
the debug module and SWIM (single wire interface module), refer to the STM8 SWIM
communication protocol and debug module user manual (UM0470). For information on the
STM8 core, refer to the STM8 CPU programming manual (PM0044).
All devices of the STM8TL5xxx product line provide the following benefits:





Note:
8/84
Advanced capacitive sensing
–
Patented ProxSense ™ acquisition peripheral, providing high-end acquisition,
filtering and environment adaptation
–
Outstanding signal-to-noise ratio for touch and proximity sensing
–
Up to 300 projected capacitive channels
Reduced system cost
–
Up to 16 Kbyte of low-density embedded Flash program memory including up to 
2 Kbyte of data EEPROM
–
High system integration level with internal clock oscillators and watchdogs
–
Smaller battery and cheaper power supplies
Low power consumption and advanced features
–
Up to 16 MIPS at 16 MHz CPU clock frequency
–
Less than 150 µA/MHz, 0.8 µA in Active-halt mode with AWU, and 0.3 µA in Halt
mode
–
Clock gated system and optimized power management
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals
–
Full documentation and a wide choice of development tools
Product longevity
–
Advanced core and peripherals made in a state-of-the-art technology
–
Product family operating from 1.65 V to 3.6 V supply
ProxSense ™ is a trademark of Azoteq (Pty) Ltd.
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
2
Description
Description
The STM8TL52x4 and STM8TL53x4 devices feature the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations. It uses a ProxSense charge
transfer capacitive acquisition method that is capable of near range proximity detection.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming. All
STM8TL52x4 and STM8TL53x4 microcontrollers feature low-power low-voltage singlesupply program Flash memory.
The STM8TL52x4 and STM8TL53x4 devices are based on a generic set of state-of-the-art
peripherals. The modular design of the peripheral set allows the same peripherals to be
found in different ST microcontroller families including 32-bit families. This makes any
transition to a different family very easy, and simplified even more by the use of a common
set of development tools.
DocID022344 Rev 7
9/84
25
Description
STM8TL52x4 STM8TL53x4
Table 2. Device features
Features
STM8TL52F4
STM8TL53F4
STM8TL52G4
Flash (Kbyte)
16
Data EEPROM
(Kbyte)
2
RAM (Kbyte)
4
Timers
Communi
cation
Interfaces
Basic
1 (8-bit)
General
purpose
2 (16-bit)
SPI
1
I2C
1
USART
1
GPIOs
12
STM8TL53G4
17
STM8TL53C4
23
ProxSense
Up to 12 touch
sensing
channels
(5 receiver/
transmitter
channels and 2
transmitter
channels)
Others
Window watchdog, independent watchdog, two 16-MHz and one 38-kHz internal RC, autowakeup counter, beeper
Up to 30 touch
sensing
channels
(5 receiver/
transmitter
channels and 6
transmitter
channels)
CPU frequency
Up to 25 touch
sensing
channels
(8 receiver/
transmitter
channels and 2
transmitter
channels)
1.65 to 3.6 V
Operating
temperature
-40 to +85 °C
10/84
Up to 300 touch
sensing
channels
(20 receiver/
transmitter
channels and 15
transmitter
channels)
16 MHz
Operating voltage
Packages
Up to 72 touch
sensing
channels
(8 receiver/
transmitter
channels and 9
transmitter
channels)
TSSOP20
UFQFPN28
DocID022344 Rev 7
UFQFPN48
STM8TL52x4 STM8TL53x4
Product overview
Figure 1. STM8TL5xx4 block diagram
#
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Legend:
AWU: Auto-wakeup unit
Int. RC: internal RC oscillator
I²C: Inter-integrated circuit multimaster interface
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous / asynchronous receiver / transmitter
IWDG: Independent watchdog
WWDG: Window watchdog
ProxSense™: capacitive sensing peripheral
DocID022344 Rev 7
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25
Product overview
3.1
STM8TL52x4 STM8TL53x4
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify - write type data manipulations

8-bit accumulator

24-bit program counter - 16 Mbyte linear memory space

16-bit stack pointer - access to a 64 Kbyte level stack

8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing

20 addressing modes

Indexed indirect addressing mode for lookup tables located anywhere in the address
space

Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
12/84

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
3.2
Product overview
Development tools
Development tools for the STM8 microcontrollers include:

The ST-Link very low-cost professional tool to debug and program

The STVD high-level language debugger including C compiler, assembler and
integrated development environment

The STVP Flash programming software

The STM-STUDIO real-time and non-intrusive graphical interface used to probe
application variables and data
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
3.3
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
3.4
Interrupt controller
The STM8TL5xx4 devices feature a nested vectored interrupt controller:
3.5

Nested interrupts with 3 software priority levels

22 interrupt vectors with hardware priority

Up to 22 external interrupt sources on 10 vectors

TRAP and RESET interrupts
Memory
The STM8TL5xx4 devices have the following main features:

4 Kbyte of RAM

The EEPROM is divided into two memory arrays (see the STM8TL5xxx reference
manual (RM0312) for details on the memory mapping):
–
16 Kbyte of low-density embedded Flash program including up to 2 Kbyte of data
EEPROM. Data EEPROM and Flash program areas can be write protected
independently by using the memory access security mechanism (MASS).
–
64 option bytes (one block) of which 5 bytes are already used for the device.
–
Error correction code is implemented on the EEPROM.
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25
Product overview
3.6
STM8TL52x4 STM8TL53x4
Low power modes
To minimize power consumption, the product features three MCU low power modes:

Wait mode: CPU clock stopped, selected peripherals at full clock speed.

Active-halt mode:

–
When wakeup time is programmed in the AWU unit, the CPU and peripheral
clocks are stopped. The RAM content is preserved.
–
When a ProxSense acquisition is ongoing, the wakeup is on ProxSense interrupts;
the CPU and the other peripheral clocks are stopped.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
Wakeup is triggered by an external interrupt.
The ProxSense peripheral can return to low power mode between each conversion. 
The ProxSense acquisition can be operated in Run, Wait and Active-halt modes.
3.7
Voltage regulators
The STM8TL5xx4 devices embed an internal voltage regulator for generating the 1.8 V
power supply for the core and peripherals and a second internal voltage regulator providing
a stable power supply (around 1.45V) for the ProxSense peripheral.
3.7.1
Dual-mode voltage regulator
This regulator has two different modes: main voltage regulator mode (MVR) and low power
voltage regulator mode (LPVR). When in Active-halt mode, the regulator remains in MVR if
ProxSense is active. When entering Halt or Active-halt modes, the system automatically
switches from the MVR to the LPVR in order to reduce current consumption unless
ProxSense is enabled.
3.7.2
ProxSense voltage regulator
This regulator provides a very stable voltage to power the ProxSense peripheral including
ProxSense pins in order to be independent of any power supply variations. This regulator is
switched on while the ProxSense peripheral is enabled (bit PXSEN = 1) and bit
LOW_POWER is set to ‘0’ in register PXS_CR1. Otherwise, when LOW_POWER is set to
‘1’, this regulator is only enabled during conversions (while CIPF = 1 and SYNCPF = 0).
3.8
Clock control
The STM8TL5xx4 embeds a robust clock controller. It is used to distribute the system clock
(SYSCLK) to the core and the peripherals and to manage clock gating for low power modes.
This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a
programmable prescaler.
In addition, a 38 kHz low speed internal RC oscillator is used by the Independent watchdog
(IWDG) and Auto-wakeup unit (AWU).
14/84
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
3.9
Product overview
System configuration controller
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM3 channels can be remapped.
3.10
Independent watchdog
The independent watchdog (IWDG) peripheral can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure.
3.11
Window watchdog
The window watchdog (WWDG) is based on a 7-bit downcounter that can be set as freerunning. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the main clock. It has an early warning interrupt capability and the counter can
be frozen in debug mode.
3.12
Auto-wakeup counter
The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.
3.13
General purpose and basic timers
STM8TL5xx4 devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one
8-bit basic timer (TIM4).
16-bit general purpose timers
The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable
prescaler. They perform a wide range of functions, including:

Timebase generation

Measuring the pulse lengths of input signals (input capture)

Generating output waveforms (output compare, PWM and One pulse mode)

Interrupt capability on various events (capture, compare, overflow, break, trigger)

Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer
overflow.
DocID022344 Rev 7
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25
Product overview
3.14
STM8TL52x4 STM8TL53x4
Beeper
STM8TL5xx4 devices include a beeper function used to generate a beep signal in the range
of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.
3.15
USART
The USART interface (USART) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.
3.16

1 Mbit/s full duplex SCI

SPI emulation

High precision baud rate generator

Single wire half duplex mode
SPI
The serial peripheral interface (SPI) provides half/ full duplex synchronous serial
communication with external devices.
3.17

Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave

Full duplex synchronous transfers

Simplex synchronous transfers on 2 lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

Hardware CRC calculation

Slave/master selection input pin
I2 C
The I2C bus interface (I2C) provides multi-master capability, and controls all I2C bus-specific
sequencing, protocol, arbitration and timing.
16/84

Master, slave and multi-master capability

Dual addressing mode capability

Standard mode up to 100 kHz and fast speed modes up to 400 kHz

7-bit and 10-bit addressing modes

Hardware CRC calculation
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
3.18
Product overview
ProxSense
The ProxSense peripheral uses a charge-transfer method to detect capacitance changes.

3.19
Up to 300 capacitive sensing channels composed of 15 transmitters and 20 receivers
with up to 10 Rx channels acquired in parallel

Fast acquisition with a typical scan time of 250 µs for 10 Rx channels

Configurable internal sampling capacitor (CS)

Electrode Parasitic Capacitance Compensation (EPCC) to ensure the best sensitivity in
all user environments

RF noise detection, allowing to reject corrupted samples

External trigger to de-synchronize the acquisition from known noise

Can be configured to return to low power mode between each conversion

Acquisition possible in Run, Wait and Active-halt modes
TouchSensing dedicated library available upon request

Complete C source code library with firmware examples (MISRA compliant)

Multifunction capability to combine capacitive sensing functions with traditional MCU
features

Compatible with proximity, touchkey, linear and rotary touch sensor implementation

Configuration of all ProxSense parameters

Extra filtering and calibration functions

TouchSensing user interface through firmware API for status reporting and application
configuration

Compliance with Cosmic, IAR and Raisonance C compilers
DocID022344 Rev 7
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25
Pin description
4
STM8TL52x4 STM8TL53x4
Pin description
966,2
9'',2
3'+63;6B7;7,0B&+
3'+63;6B7;7,0B&+
3'+63;6B7;7,0B&+
3'+63;6B7;7,0B&+
3%+63;6B7;7,0B75,*
3%+63;6B7;7,0B75,*
3%+63;6B7;
3%+63;6B7;
3%+63;6B7;
3%+63;6B7;
Figure 2. STM8TL53 48-pin UFQFPN package pinout
3'+63;6B7;
%((36:,0+63$
3'+63;6B7;
>7,0B&[email protected],B166+63$
3'+63;6B7;
>7,0B&[email protected]$57B&.63,B6&.+63$
3'+63;6B7;
,&B6'$86$57B7;63,B0,62+63$
3;6B5;E
,&B6&/86$57B5;63,B026,+63$
3;6B5;D
3;6B5;E
3;6B7;+63%
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8)4)31
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3;6B5;E
3;6B5;E
3;6B5;D
3;6B5;D
3;6B5;E
3;6B5;D
1567+63$
&/.B&&23;6B75,*+63$
3;6B5;E
3;6B5;E
3;6B5;D
3;6B5;D
3;6B5;E
966
3;6B5;D
3;6B95(*
3;6B5;E
069
1. HS corresponds to 20 mA high sink/source capability.
2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power
supply circuitry details in Section 9.3.2: Power supply on page 46 and the STM8TL5xxx reference manual
(RM0312), Section 6: Power supply.
18/84
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Pin description
3'+63;6B7;7,0B&+
3'+63;6B7;7,0B&+
3'+63;6B7;7,0B&+
3'+63;6B7;7,0B&+
3%+63;6B7;7,0B75,*
3$ +66:,0%((3
3$+663,B166>7,0B&[email protected]
Figure 3. STM8TL53G4U6 28-pin UFQFPN package pinout
>7,0B&[email protected] 86$57B&.63,B6&.+63$
3'+63;6B7;
,&B6'$86$57B7;63,B0,62+63$
3'+63;6B7;
3'+63;6B7;
,&B6&/86$57B5;63,B026,+63$
3'+63;6B7;
3;6B5;D
3;6B95(*
3;6B5;D
1567+63$
3;6B5;D
3;6B5;D
3;6B5;D
3;6B5;D
3;6B5;D
3;6B5;D
3;6B5),1+63$
966
8)4)31
&/.B&&23;6B75,*+63$
9''
069
1. HS corresponds to 20 mA high sink/source capability.
2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power
supply circuitry details in Section 9.3.2: Power supply on page 46 and the STM8TL5xxx reference manual
(RM0312), Section 6: Power supply.
DocID022344 Rev 7
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25
Pin description
STM8TL52x4 STM8TL53x4
3'+67,0B&+
3'+67,0B&+
3'+67,0B&+
3'+67,0B&+
3%+67,0B75,*
3$ +66:,0%((3
3$+663,B166>7,0B&[email protected]
Figure 4. STM8TL52G4U6 28-pin UFQFPN package pinout
>7,0B&[email protected] 86$57B&.63,B6&.+63$
3'+6
,&B6'$86$57B7;63,B0,62+63$
3'+6
,&B6&/86$57B5;63,B026,+63$
3'+63;6B7;
3'+63;6B7;
3;6B5;D
3;6B95(*
3;6B5;D
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3;6B5;D
3;6B5;D
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9''
069
1. HS corresponds to 20 mA high sink/source capability.
2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power
supply circuitry details in Section 9.3.2: Power supply on page 46 and the STM8TL5xxx reference manual
(RM0312) Section 6: Power supply.
20/84
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Pin description
Figure 5. STM8TL53F4P6 TSSOP20 20-pin package pinout
TIM3_TRIG/PXS_TX8/(HS)PB0
BEEP/SWIM/(HS)PA0
[TIM3_CH1]/SPI_NSS/(HS)PA1
[TIM3_CH2]/USART_CK/SPI_SCK/(HS)PA2
I2C_SDA/USART_TX/SPI_MISO/(HS)PA3
I2C_SCL/USART_RX/SPI_MOSI/(HS)PA4
VDD
VSS
PXS_VREG
NRST/(HS)PA5
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PD6(HS)/PXS_TX6/TIM3_CH1
PD5(HS)/PXS_TX5/TIM2_CH2
PD4(HS)/PXS_TX4/TIM2_CH1
PD1(HS)/PXS_TX1
PD0(HS)/PXS_TX0
PXS_RX7a
PXS_RX6a
PXS_RX2a
PXS_RX1a
PXS_RX0a
1. HS corresponds to 20 mA high sink/source capability.
2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power
supply circuitry details in Section 9.3.2: Power supply on page 46 and the STM8TL5xxx reference manual
(RM0312) Section 6: Power supply.
Figure 6. STM8TL52F4P6 TSSOP20 20-pin package pinout
TIM3_TRIG/(HS)PB0
BEEP/SWIM/(HS)PA0
[TIM3_CH1]/SPI_NSS/(HS)PA1
[TIM3_CH2]/USART_CK/SPI_SCK/(HS)PA2
I2C_SDA/USART_TX/SPI_MISO/(HS)PA3
I2C_SCL/USART_RX/SPI_MOSI/(HS)PA4
VDD
VSS
PXS_VREG
NRST/(HS)PA5
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PD6(HS)/TIM3_CH1
PD5(HS)/TIM2_CH2
PD4(HS)/TIM2_CH1
PD1(HS)/PXS_TX1
PD0(HS)/PXS_TX0
PXS_RX7a
PXS_RX6a
PXS_RX2a
PXS_RX1a
PXS_RX0a
1. HS corresponds to 20 mA high sink/source capability.
2. Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power
supply circuitry details in Section 9.3.2: Power supply on page 46 and the STM8TL5xxx reference manual
(RM0312) Section 6: Power supply.
DocID022344 Rev 7
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25
Pin description
STM8TL52x4 STM8TL53x4
Table 3. Legends/abbreviations
Type
Level
Port and control
configuration
Reset state
I = input, O = output, S = power supply
Input
FT = 5 V tolerant, TC = 3 V capable
Output
HS = high sink/source (20 mA)
Input
float = floating, wpu = weak pull-up
Output
T = true open drain, OD = open drain, PP = push-pull
Bold X (pin state after reset release). 
Unless otherwise specified, the pin state is the same during the reset phase
(i.e. “under reset”) and after internal reset release (i.e. at reset state).
Table 4. STM8TL5xx4 pin description
2
3
27
28
4
5
6
1
2
3
2
PA0(1)/SWIM/
BEEP
3
PA1/SPI_NSS/
[TIM3_CH1]
4
PA2/SPI_SCK/
USART_CK/
[TIM3_CH2](2)
5
PA3/SPI_MISO/
USART_TX/
I2C_SDA(2)
6
PA4/SPI_MOSI/
USART_RX/
I2C_SCL
High sink/source
OD
PP
I/O TC
X
X
X
HS
X
X
I/O TC
I/O FT
X
X
X
X
X
X
HS
HS
X
X
X
X
Main function
(after reset)
Ext. interrupt
PB6/ PXS_TX14
wpu
-
Alternate function
floating
-
Output
Level
TSSOP20
1
Pin name
Type
UFQFPN28
Input
UFQFPN48
Pin no.
Port B6
SWIM
Port A1
Default
ProxSense
transmit 14
-
Port A0(1)
-
SWIM input and
output
-
Beep output
-
SPI master/
slave select
Timer 3 channel
1
SPI clock
I/O FT
I/O FT
I/O FT
X
X
X
X
X
X
X
X
X
HS
HS
HS
X
X
X
X
X
X
Port A2
Port A3
Port A4
USART
synchronous
clock
22/84
4
7
VDD
S
-
-
-
-
-
-
DocID022344 Rev 7
-
Digital
power
supply
Timer 3 channel
2
SPI master in/
slave out
-
USART transmit
-
I2C
-
data
SPI master out/
slave in
-
USART receive
-
I
7
Remap
2C
clock
-
-
-
STM8TL52x4 STM8TL53x4
Pin description
Table 4. STM8TL5xx4 pin description (continued)
9
6
9
10
7
10 PA5/NRST(3)
11
8
PXS_VREG
PA6/ PXS_TRIG/
CLK_CCO
S
OD
PP
-
-
-
-
-
-
-
-
I/O TC
I/O FT
Main function
(after reset)
High sink/source
S
Ext. interrupt
VSS
wpu
8
Alternate function
floating
5
Output
Level
TSSOP20
8
Pin name
Type
UFQFPN28
Input
UFQFPN48
Pin no.
Digital
ground
-
-
-
-
-
-
-
-
-
-
HS
X
X
Reset
X
X
X
HS
X
X
Port A6
12
9
-
PA7/PXS_RFIN
I/O TC
Default
Remap
-
-
ProxSense
voltage
regulator
External
decoupling
capacitor
-
Port A5 (output
only)
-
ProxSense
external trigger
input
-
CLK clock
output
-
X
X
X
HS
X
X
Port A7
ProxSense
antenna input
-
13 10 11 PXS_RX0a
-
-
-
-
-
-
-
-
PXS_RX0a
ProxSense
receiver 0a
-
14
PXS_RX0b
-
-
-
-
-
-
-
-
PXS_RX0b
ProxSense
receiver 0b
-
15 11 12 PXS_RX1a
-
-
-
-
-
-
-
-
PXS_RX1a
ProxSense
receiver 1a
-
16
PXS_RX1b
-
-
-
-
-
-
-
-
PXS_RX1b
ProxSense
receiver 1b
-
17 12 13 PXS_RX2a
-
-
-
-
-
-
-
-
PXS_RX2a
ProxSense
receiver 2a
-
18
-
-
-
-
-
PXS_RX2b
-
-
-
-
-
-
-
-
PXS_RX
ProxSense
receiver 2b
-
19 13
-
PXS_RX3a
-
-
-
-
-
-
-
-
PXS_RX3a
ProxSense
receiver 3a
-
20
-
PXS_RX3b
-
-
-
-
-
-
-
-
PXS_RX3b
ProxSense
receiver 3b
-
21 14
-
PXS_RX4a
-
-
-
-
-
-
-
-
PXS_RX4a
ProxSense
receiver 4a
-
22
-
PXS_RX4b
-
-
-
-
-
-
-
-
PXS_RX4b
ProxSense
receiver 4b
-
-
-
-
DocID022344 Rev 7
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25
Pin description
STM8TL52x4 STM8TL53x4
Table 4. STM8TL5xx4 pin description (continued)
Alternate function
Ext. interrupt
High sink/source
OD
PP
-
-
-
-
-
-
-
-
PXS_RX5a
ProxSense
receiver 5a
-
24
-
PXS_RX5b
-
-
-
-
-
-
-
-
PXS_RX5b
ProxSense
receiver 5b
-
25 16 14 PXS_RX6a
-
-
-
-
-
-
-
-
PXS_RX6a
ProxSense
receiver 6a
-
26
PXS_RX6b
-
-
-
-
-
-
-
-
PXS_RX6b
ProxSense
receiver 6b
-
27 17 15 PXS_RX7a
-
-
-
-
-
-
-
-
PXS_RX7a
ProxSense
receiver 7a
-
28
-
-
PXS_RX7b
-
-
-
-
-
-
-
-
PXS_RX7b
ProxSense
receiver 7b
-
29
-
-
PXS_RX8a
-
-
-
-
-
-
-
-
PXS_RX8a
ProxSense
receiver 8a
-
30
-
-
PXS_RX8b
-
-
-
-
-
-
-
-
PXS_RX8b
ProxSense
receiver 8b
-
31
-
-
PXS_RX9a
-
-
-
-
-
-
-
-
PXS_RX9a
ProxSense
receiver 9a
-
32
-
-
PXS_RX9b
-
-
-
-
-
-
-
-
PXS_RX9b
ProxSense
receiver 9b
-
-
-
-
Pin name
Type
PXS_RX5a
TSSOP20
-
UFQFPN28
23 15
UFQFPN48
wpu
Main function
(after reset)
Output
floating
Input
Level
Pin no.
Default
Remap
33 18 16 PD0/PXS_TX0
I/O TC
X
X
X
HS
X
X
Port D0
ProxSense
transmitter 0
-
34 19 17 PD1/PXS_TX1
I/O TC
X
X
X
HS
X
X
Port D1
ProxSense
transmitter 1
-
35 20
-
PD2/PXS_TX2(4) I/O TC
X
X
X
HS
X
X
Port D2
ProxSense
transmitter 2(4)
-
36 21
-
PD3/PXS_TX3(4) I/O TC
X
X
X
HS
X
X
Port D3
ProxSense
transmitter 3(4)
-
37
-
-
VSSIO
S
-
-
-
-
-
-
-
IOs ground
-
-
38
-
-
VDDIO
S
-
-
-
-
-
-
-
IOs power
supply
-
-
PD4/PXS_TX4(4)
39 22 18
I/O TC
/ TIM2_CH1
24/84
X
X
X
HS
X
DocID022344 Rev 7
X
Port D4
ProxSense
transmitter 4(4)
-
Timer 2 channel 1
-
STM8TL52x4 STM8TL53x4
Pin description
Table 4. STM8TL5xx4 pin description (continued)
PD5/PXS_TX5(4)
I/O TC
40 23 19
/ TIM2_CH2
PD6/PXS_TX6(4)
I/O TC
41 24 20
/ TIM3_CH1
PD7/PXS_TX7(4)
I/O TC
/ TIM3_CH2
42 25
43 26
-
1
-
44
PB0/PXS_TX8(4)
/ TIM3_ETR
I/O TC
PB1(2)/PXS_TX9
/ TIM2_ETR
I/O TC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
HS
HS
HS
HS
X
X
X
X
X
X
X
X
X
X
Main function
(after reset)
Alternate function
PP
OD
High sink/source
Output
Ext. interrupt
wpu
floating
Level
Pin name
Type
Input
TSSOP20
UFQFPN28
UFQFPN48
Pin no.
Port D5
Port D6
Port D7
Port B0
Port B1
Default
Remap
ProxSense
transmitter 5(4)
-
Timer 2 channel 2
-
ProxSense
transmitter 6(4)
-
Timer 3 channel1
-
ProxSense
transmitter 7(4)
-
Timer 3 channel 2
-
ProxSense
transmitter 8(4)
-
Timer 3 external trigger
-
ProxSense
transmitter 9
-
Timer 2 external trigger
-
-
-
45
-
-
PB2/PXS_TX10
I/O TC
X
X
X
HS
X
X
Port B2
ProxSense
transmitter 10
-
46
-
-
PB3/PXS_TX11
I/O TC
X
X
X
HS
X
X
Port B3
ProxSense
transmitter 11
-
47
-
-
PB4/PXS_TX12
I/O TC
X
X
X
HS
X
X
Port B4
ProxSense
transmitter 12
-
48
-
-
PB5/PXS_TX13
I/O TC
X
X
X
HS
X
X
Port B5
ProxSense
transmitter 13
-
1. The PA0/SWIM pin is in input pull-up during the reset phase and after reset release.
2. A pull-up is applied to PA2, PA3 and PB1 during the reset phase. These three pins are input floating after reset release.
3. At power-up, the PA5/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA5), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA5
pin as general purpose output in the STM8TL5xxx reference manual (RM0312).
4. Not available for STM8TL52xx.
DocID022344 Rev 7
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25
Memory and register map
5
STM8TL52x4 STM8TL53x4
Memory and register map
Figure 7. Memory map
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1. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
26/84
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Memory and register map
Table 5. Flash and RAM boundary addresses
Memory area
Size
Start address
End address
RAM
4 Kbyte
0x00 0000
0x00 0FFF
Flash program memory
16 Kbyte
0x00 8000
0x00 BFFF
Table 6. I/O Port hardware register map
Register label
Register name
Reset
status
0x00 5000
PA_ODR
Port A data output latch register
0x00
0x00 5001
PA_IDR
Port A input pin value register
0xXX
PA_DDR
Port A data direction register
0x00
0x00 5003
PA_CR1
Port A control register 1
0x00
0x00 5004
PA_CR2
Port A control register 2
0x00
0x00 5005
PB_ODR
Port B data output latch register
0x00
0x00 5006
PB_IDR
Port B input pin value register
0xXX
PB_DDR
Port B data direction register
0x00
0x00 5008
PB_CR1
Port B control register 1
0x00
0x00 5009
PB_CR2
Port B control register 2
0x00
Address
0x00 5002
0x00 5007
Block
Port A
Port B
0x00 500A
to
0x00 500E
Reserved area (5 byte)
0x00 500F
PD_ODR
Port D data output latch register
0x00
0x00 5010
PD_IDR
Port D input pin value register
0xXX
PD_DDR
Port D data direction register
0x00
0x00 5012
PD_CR1
Port D control register 1
0x00
0x00 5013
PD_CR2
Port D control register 2
0x00
0x00 5011
Port D
DocID022344 Rev 7
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39
Memory and register map
STM8TL52x4 STM8TL53x4
Table 7. General hardware register map
Register label
Register name
Reset
status
0x00 5050
FLASH_CR1
Flash control register 1
0x00
0x00 5051
FLASH_CR2
Flash control register 2
0x00
FLASH _PUKR
Flash Program memory unprotection register
0x00
0x00 5053
FLASH _DUKR
Data EEPROM unprotection register
0x00
0x00 5054
FLASH _IAPSR
Flash in-application programming status register
0xX0
Address
0x00 5052
Block
Flash
0x00 5055
to
0x00 509D
0x00 509E
Reserved area (73 byte)
SYSCFG
SYSCFG_RMPCR1
0x00 509F
Remapping control register 1
0x00
Reserved area (1 byte)
0x00 50A0
EXTI_CR1
External interrupt control register 1
0x00
0x00 50A1
EXTI_CR2
External interrupt control register 2
0x00
EXTI_CR3
External interrupt control register 3
0x00
EXTI_SR1
External interrupt status register 1
0x00
0x00 50A4
EXTI_SR2
External interrupt status register 2
0x00
0x00 50A5
EXTI_CONF
External interrupt port select register
0x00
WFE_CR1
WFE control register 1
0x00
WFE_CR2
WFE control register 2
0x00
0x00 50A2
0x00 50A3
0x00 50A6
0x00 50A7
ITC-EXTI
WFE
0x00 50A8
to
0x00 50AF
0x00 50B0
0x00 50B1
Reserved area (8 byte)
RST
RST_CR
Reset control register
0x00
RST_SR
Reset status register
0x01 (1)
0x00 50B2
to
0x00 50BF
Reserved area (14 byte)
0x00 50C0
0x00 50C1
to
0x00 50C2
CLK_CKDIVR
Clock divider register
0x00
Reserved area (2 byte)
CLK
0x00 50C3
CLK_PCKENR1
Peripheral clock gating register 1
0x00
0x00 50C4
CLK_PCKENR2
Peripheral clock gating register 2
0x01
0x00 50C5
CLK_CCOR
Configurable clock control register
0x10
0x00 50C6
to
0x00 50D2
28/84
Reserved area (12 byte)
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Memory and register map
Table 7. General hardware register map (continued)
Address
0x00 50D3
0x00 50D4
Block
WWDG
Register label
Register name
WWDG_CR
WWDG control register
WWDG_WR
WWDG window register
0x00 50D5
to
0x00 50D7
IWDG
0x00 50E2
IWDG_KR
IWDG key register
0xXX
IWDG_PR
IWDG prescaler register
0x00
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 byte)
0x00 50F0
0x00 50F1
AWU
0x00 50F2
0x00 50F3
0x7F
Reserved area (11 byte)
0x00 50E0
0x00 50E1
Reset
status
BEEP
AWU_CSR
AWU control/status register
0x00
AWU_APR
AWU asynchronous prescaler buffer register
0x3F
AWU_TBR
AWU timebase selection register
0x00
BEEP_CSR
BEEP control/status register
0x1F
0x00 50F4
to
0x00 51FF
Reserved area (268 byte)
0x00 5200
SPI_CR1
SPI control register 1
0x00
0x00 5201
SPI_CR2
SPI control register 2
0x00
SPI_ICR
SPI interrupt control register
0x00
0x00 5203
SPI_SR
SPI status register
0x00
0x00 5204
SPI_DR
SPI data register
0x00
0x00 5202
0x00 5205
to
0x00 520F
SPI
Reserved area (11 byte)
DocID022344 Rev 7
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39
Memory and register map
STM8TL52x4 STM8TL53x4
Table 7. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5210
I2C_CR1
I2C control register 1
0x00
0x00 5211
I2C_CR2
I2C control register 2
0x00
0x00 5212
I2C_FREQR
I2C frequency register
0x00
0x00 5213
I2C_OAR1L
I2C own address register 1 low
0x00
0x00 5214
I2C_OAR1H
I2C own address register 1 high
0x00
0x00 5215
I2C_OAR2
I2C own address register 2
0x00
I2C_DR
I2C data register
0x00
I2C_SR1
I2C status register 1
0x00
0x00 5218
I2C_SR2
I2C status register 2
0x00
0x00 5219
I2C_SR3
I2C status register 3
0x00
0x00 521A
I2C_ITR
I2C interrupt control register
0x00
0x00 521B
I2C_CCRL
I2C Clock control register low
0x00
0x00 521C
I2C_CCRH
I2C Clock control register high
0x00
0x00 521D
I2C_TRISER
I2C TRISE register
0x00
Address
0x00 5216
0x00 5217
Block
I2C
0x00 521E
to
0x00 522F
Reserved area (18 byte)
0x00 5230
USART_SR
USART status register
0xC0
0x00 5231
USART_DR
USART data register
0xXX
0x00 5232
USART_BRR1
USART baud rate register 1
0x00
USART_BRR2
USART baud rate register 2
0x00
USART_CR1
USART control register 1
0x00
0x00 5235
USART_CR2
USART control register 2
0x00
0x00 5236
USART_CR3
USART control register 3
0x00
0x00 5237
USART_CR4
USART control register 4
0x00
0x00 5233
0x00 5234
0x00 5238
to
0x00 524F
30/84
USART
Reserved area (18 byte)
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Memory and register map
Table 7. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5250
TIM2_CR1
TIM2 control register 1
0x00
0x00 5251
TIM2_CR2
TIM2 control register 2
0x00
0x00 5252
TIM2_SMCR
TIM2 slave mode control register
0x00
0x00 5253
TIM2_ETR
TIM2 external trigger register
0x00
0x00 5254
TIM2_IER
TIM2 interrupt enable register
0x00
0x00 5255
TIM2_SR1
TIM2 status register 1
0x00
0x00 5256
TIM2_SR2
TIM2 status register 2
0x00
0x00 5257
TIM2_EGR
TIM2 event generation register
0x00
0x00 5258
TIM2_CCMR1
TIM2 capture/compare mode register 1
0x00
0x00 5259
TIM2_CCMR2
TIM2 capture/compare mode register 2
0x00
TIM2_CCER1
TIM2 capture/compare enable register 1
0x00
TIM2_CNTRH
TIM2 counter register high
0x00
0x00 525C
TIM2_CNTRL
TIM2 counter register low
0x00
0x00 525D
TIM2_PSCR
TIM2 prescaler register
0x00
0x00 525E
TIM2_ARRH
TIM2 auto-reload register high
0xFF
0x00 525F
TIM2_ARRL
TIM2 auto-reload register low
0xFF
0x00 5260
TIM2_CCR1H
TIM2 capture/compare register 1 high
0x00
0x00 5261
TIM2_CCR1L
TIM2 capture/compare register 1 low
0x00
0x00 5262
TIM2_CCR2H
TIM2 capture/compare register 2 high
0x00
0x00 5263
TIM2_CCR2L
TIM2 capture/compare register 2 low
0x00
0x00 5264
TIM2_BKR
TIM2 break register
0x00
0x00 5265
TIM2_OISR
TIM2 output idle state register
0x00
Address
0x00 525A
0x00 525B
0x00 5266
to
0x00 527F
Block
TIM2
Reserved area (26 byte)
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39
Memory and register map
STM8TL52x4 STM8TL53x4
Table 7. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5280
TIM3_CR1
TIM3 control register 1
0x00
0x00 5281
TIM3_CR2
TIM3 control register 2
0x00
0x00 5282
TIM3_SMCR
TIM3 slave mode control register
0x00
0x00 5283
TIM3_ETR
TIM3 external trigger register
0x00
0x00 5284
TIM3_IER
TIM3 interrupt enable register
0x00
0x00 5285
TIM3_SR1
TIM3 status register 1
0x00
0x00 5286
TIM3_SR2
TIM3 status register 2
0x00
0x00 5287
TIM3_EGR
TIM3 event generation register
0x00
0x00 5288
TIM3_CCMR1
TIM3 capture/compare mode register 1
0x00
0x00 5289
TIM3_CCMR2
TIM3 capture/compare mode register 2
0x00
TIM3_CCER1
TIM3 capture/compare enable register 1
0x00
TIM3_CNTRH
TIM3 counter register high
0x00
0x00 528C
TIM3_CNTRL
TIM3 counter register low
0x00
0x00 528D
TIM3_PSCR
TIM3 prescaler register
0x00
0x00 528E
TIM3_ARRH
TIM3 auto-reload register high
0xFF
0x00 528F
TIM3_ARRL
TIM3 auto-reload register low
0xFF
0x00 5290
TIM3_CCR1H
TIM3 capture/compare register 1 high
0x00
0x00 5291
TIM3_CCR1L
TIM3 capture/compare register 1 low
0x00
0x00 5292
TIM3_CCR2H
TIM3 capture/compare register 2 high
0x00
0x00 5293
TIM3_CCR2L
TIM3 capture/compare register 2 low
0x00
0x00 5294
TIM3_BKR
TIM3 break register
0x00
0x00 5295
TIM3_OISR
TIM3 output idle state register
0x00
Address
0x00 528A
0x00 528B
Block
TIM3
0x00 5296
to
0x00 52DF
Reserved area (74 byte)
0x00 52E0
TIM4_CR1
TIM4 control register 1
0x00
0x00 52E1
TIM4_CR2
TIM4 control register 2
0x00
0x00 52E2
TIM4_SMCR
TIM4 Slave mode control register
0x00
0x00 52E3
TIM4_IER
TIM4 interrupt enable register
0x00
TIM4_SR1
TIM4 Status register 1
0x00
0x00 52E5
TIM4_EGR
TIM4 event generation register
0x00
0x00 52E6
TIM4_CNTR
TIM4 counter register
0x00
0x00 52E7
TIM4_PSCR
TIM4 prescaler register
0x00
0x00 52E8
TIM4_ARR
TIM4 auto-reload register low
0xFF
0x00 52E4
32/84
TIM4
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Memory and register map
Table 7. General hardware register map (continued)
Address
Block
Register label
0x00 52E9
to
0x00 52FF
Register name
Reset
status
Reserved area (23 byte)
0x00 5300
PXS_CR1
ProxSense control register 1
0x00
0x00 5301
PXS_CR2
ProxSense control register 2
0x00
0x00 5302
PXS_CR3
ProxSense control register 3
0x04
0x00 5303
0x00 5304
0x00 5305
Reserved area (1 byte)
PXS
PXS_ISR
ProxSense interrupt and status register
0x00
Reserved area (1 byte)
0x00 5306
PXS_CKCR1
ProxSense clock control register 1
0x30
0x00 5307
PXS_CKCR2
ProxSense clock control register 2
0x11
0x00 5308
PXS_RXENRH
ProxSense receiver enable register high
0x00
0x00 5309
PXS_RXENRL
ProxSense receiver enable register low
0x00
0x00 5310
to
0x00 5311
Reserved area (2 byte)
0x00 530A
PXS_RXCR1H
ProxSense receiver control register 1 high
0x00
0x00 530B
PXS_RXCR1L
ProxSense receiver control register 1 low
0x00
0x00 530C
PXS_RXCR2H
ProxSense receiver control register 2 high
0x00
PXS_RXCR2L
ProxSense receiver control register 2 low
0x00
PXS_RXCR3H
ProxSense receiver control register 3 high
0x00
0x00 530F
PXS_RXCR3L
ProxSense receiver control register 3 low
0x00
0x00 5312
PXS_RXINSRH
ProxSense receiver inactive state register high
0x00
0x00 5313
PXS_RXINSRL
ProxSense receiver inactive state register low
0x00
0x00 530D
0x00 530E
PXS
0x00 5314
to
0x00 5315
0x00 5316
0x00 5317
0x00 5318
to
0x00 5319
Reserved area (2 byte)
PXS
PXS_TXENRH
ProxSense transmit enable register high
0x00
PXS_TXENRL
ProxSense transmit enable register low
0x00
Reserved area (2 byte)
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39
Memory and register map
STM8TL52x4 STM8TL53x4
Table 7. General hardware register map (continued)
Register label
Register name
Reset
status
0X00 531A
PXS_MAXRH
ProxSense maximum counter value register high
0xFF
0x00 531B
PXS_MAXRL
ProxSense maximum counter value register low
0xFF
0x00 531C
PXS_MAXENRH
ProxSense maximum counter enable register high
0x00
0x00 531D
PXS_MAXENRL
ProxSense maximum counter enable register low
0x00
0x00 531E
PXS_RXSRH
ProxSense receiver status register high
0x00
PXS_RXSRL
ProxSense receiver status register low
0x00
0x00 5320
PXS_RX0CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5321
PXS_RX0CNTRL
ProxSense counter register receiver channel low
0x00
0x00 5322
PXS_RX1CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5323
PXS_RX1CNTRL
ProxSense counter register receiver channel low
0x00
0x00 5324
PXS_RX2CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5325
PXS_RX2CNTRL
ProxSense counter register receiver channel low
0x00
0x00 5326
PXS_RX3CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5327
PXS_RX3CNTRL
ProxSense counter register receiver channel low
0x00
0x00 5328
PXS_RX4CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5329
PXS_RX4CNTRL
ProxSense counter register receiver channel low
0x00
0x00 532A
PXS_RX5CNTRH
ProxSense counter register receiver channel high
0x00
0x00 532B
PXS_RX5CNTRL
ProxSense counter register receiver channel low
0x00
PXS_RX6CNTRH
ProxSense counter register receiver channel high
0x00
0x00 532D
PXS_RX6CNTRL
ProxSense counter register receiver channel low
0x00
0x00 532E
PXS_RX7CNTRH
ProxSense counter register receiver channel high
0x00
0x00 532F
PXS_RX7CNTRL
ProxSense counter register receiver channel low
0x00
0x00 5330
PXS_RX8CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5331
PXS_RX8CNTRL
ProxSense counter register receiver channel low
0x00
0x00 5332
PXS_RX9CNTRH
ProxSense counter register receiver channel high
0x00
0x00 5333
PXS_RX9CNTRL
ProxSense counter register receiver channel low
0x00
Address
0x00 531F
0x00 532C
0x00 5334
to
0x00 533F
34/84
Block
PXS
PXS
Reserved area (12 byte)
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Memory and register map
Table 7. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5340
PXS_RX0CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5341
PXS_RX1CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5342
PXS_RX2CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5343
PXS_RX3CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5344
PXS_RX4CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5345
PXS_RX5CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5346
PXS_RX6CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5347
PXS_RX7CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5348
PXS_RX8CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
0x00 5349
PXS_RX9CSSELR
ProxSense receiver sampling capacitor
selection register
0x00
Address
Block
PXS
0x00 534A
to
0x00 534F
Reserved area (6 byte)
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39
Memory and register map
STM8TL52x4 STM8TL53x4
Table 7. General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5350
PXS_RX0EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5351
PXS_RX1EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5352
PXS_RX2EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5353
PXS_RX3EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5354
PXS_RX4EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5355
PXS_RX5EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5356
PXS_RX6EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5357
PXS_RX7EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5358
PXS_RX8EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
0x00 5359
PXS_RX9EPCCSELR
ProxSense receiver electrode parasitic
compensation capacitor selection register
0x00
Address
Block
PXS
0x00 535A
to
0x00 7EFF
Reserved area (11174 byte)
1. After power-on reset.
Table 8. CPU/SWIM/debug module/interrupt controller registers
Register label
Register name
Reset
status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
PCE
Program counter extended
0x00
0x00 7F02
PCH
Program counter high
0x80
0x00 7F03
PCL
Program counter low
0x00
0x00 7F04
XH
X index register high
0x00
XL
X index register low
0x00
0x00 7F06
YH
Y index register high
0x00
0x00 7F07
YL
Y index register low
0x00
0x00 7F08
SPH
Stack pointer high
0x05
0x00 7F09
SPL
Stack pointer low
0xFF
0x00 7F0A
CC
Condition code register
0x28
Address
0x00 7F05
36/84
Block
CPU
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Memory and register map
Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)
Address
Block
Register label
0x00 7F0B
to
0x00 7F5F
0x00 7F60
Register name
Reset
status
Reserved area (85 byte)
CFG
CFG_GCR
0x00 7F61
0x00 7F6F
Global configuration register
0x00
Reserved area (15 byte)
0x00 7F70
ITC_SPR1
Interrupt Software priority register 1
0xFF
0x00 7F71
ITC_SPR2
Interrupt Software priority register 2
0xFF
0x00 7F72
ITC_SPR3
Interrupt Software priority register 3
0xFF
ITC_SPR4
Interrupt Software priority register 4
0xFF
ITC_SPR5
Interrupt Software priority register 5
0xFF
0x00 7F75
ITC_SPR6
Interrupt Software priority register 6
0xFF
0x00 7F76
ITC_SPR7
Interrupt Software priority register 7
0xFF
0x00 7F77
ITC_SPR8
Interrupt Software priority register 8
0xFF
0x00 7F73
0x00 7F74
ITC-SPR
(1)
0x00 7F78
to
0x00 7F79
0x00 7F80
Reserved area (2 byte)
SWIM
SWIM_CSR
0x00 7F81
to
0x00 7F8F
SWIM control status register
0x00
Reserved area (15 byte)
0x00 7F90
DM_BK1RE
Breakpoint 1 register extended byte
0xFF
0x00 7F91
DM_BK1RH
Breakpoint 1 register high byte
0xFF
0x00 7F92
DM_BK1RL
Breakpoint 1 register low byte
0xFF
0x00 7F93
DM_BK2RE
Breakpoint 2 register extended byte
0xFF
0x00 7F94
DM_BK2RH
Breakpoint 2 register high byte
0xFF
DM_BK2RL
Breakpoint 2 register low byte
0xFF
0x00 7F96
DM_CR1
Debug module control register 1
0x00
0x00 7F97
DM_CR2
Debug module control register 2
0x00
0x00 7F98
DM_CSR1
Debug module control/status register 1
0x10
0x00 7F99
DM_CSR2
Debug module control/status register 2
0x00
0x00 7F9A
DM_ENFCTR
Enable function register
0xFF
0x00 7F95
DM
1. Refer to Table 7: General hardware register map on page 28 (addresses 0x00 50A0 to 0x00 50A5) for a list
of external interrupt registers.
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39
Interrupt vector mapping
6
STM8TL52x4 STM8TL53x4
Interrupt vector mapping
Table 9. Interrupt mapping
IRQ
No.
Source
block
RESET
TRAP
Description
Reset
Software interrupt
0
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)(1)
Vector
address
Yes
Yes
Yes
Yes
0x00 8000
-
-
-
-
0x00 8004
Reserved
1
FLASH
FLASH end of
programing/
write attempted to
protected page interrupt
2
PXS
End of conversion/First
conversion completed
3
4
Wakeup
from Halt
mode
0x00 8008
-
-
Yes
Yes
0x00 800C
-
Yes(2)
Yes
Yes
0x00 8010
0x00 8011
-0x00 8017
Reserved
AWU
Auto wakeup from Halt
5
-
Yes
Yes
Yes
Reserved
0x00 8018
0x00 801C
6
EXTIB
External interrupt port B
Yes
Yes
Yes
Yes
0x00 8020
7
EXTID
External interrupt port D
Yes
Yes
Yes
Yes
0x00 8024
8
EXTI0
External interrupt 0
Yes
Yes
Yes
Yes
0x00 8028
9
EXTI1
External interrupt 1
Yes
Yes
Yes
Yes
0x00 802C
10
EXTI2
External interrupt 2
Yes
Yes
Yes
Yes
0x00 8030
11
EXTI3
External interrupt 3
Yes
Yes
Yes
Yes
0x00 8034
12
EXTI4
External interrupt 4
Yes
Yes
Yes
Yes
0x00 8038
13
EXTI5
External interrupt 5
Yes
Yes
Yes
Yes
0x00 803C
14
EXTI6
External interrupt 6
Yes
Yes
Yes
Yes
0x00 8040
15
EXTI7
External interrupt 7
Yes
Yes
Yes
Yes
0x00 8044
16
Reserved
0x00 8048
17
Reserved
0x00 804C
-0x00 804F
18
Reserved
0x00 8050
19
TIM2
TIM2 update/overflow/
trigger/break interrupt
-
-
Yes
Yes
0x00 8054
20
TIM2
TIM2 capture/compare
interrupt
-
-
Yes
Yes
0x00 8058
21
TIM3
TIM3 update/overflow/
trigger/break interrupt
-
-
Yes
Yes
0x00 805C
38/84
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Interrupt vector mapping
Table 9. Interrupt mapping (continued)
IRQ
No.
Source
block
22
TIM3
Description
TIM3 capture/compare
interrupt
2324
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)(1)
Vector
address
-
-
Yes
Yes
0x00 8060
0x00 80640x00 806B
Reserved
25
TIM4
TIM4 update/overflow/
trigger interrupt
-
-
Yes
Yes
0x00 806C
26
SPI
SPI TX buffer empty/
RX buffer not empty/
error/wakeup interrupt
Yes
Yes
Yes
Yes
0x00 8070
USART
USART transmit data
register empty/
transmission complete
interrupt
-
-
Yes
Yes
0x00 8074
28
USART
USART received data
ready/overrun error/
idle line detected/parity
error/global error
interrupt
-
-
Yes
Yes
0x00 8078
29
I2C
Yes
Yes
Yes
Yes
0x00 807C
27
I2C interrupt(3)
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the
interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
2. ProxSense activated before executing HALT instruction.
3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
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39
Option byte
7
STM8TL52x4 STM8TL53x4
Option byte
Option byte contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated row of the memory.
All option byte can be modified only in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 10 for details on option byte addresses.
Refer to the STM8TL5xxx Flash programming manual (PM0212) and STM8 SWIM and
debug manual (UM0470) for information on SWIM programming procedures.
Table 10. Option byte
Addr.
Option name
Option
byte
No.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
0x4800
Read-out
protection (ROP)
OPT0
ROP[7:0]
0xAA
0x4801
-
-
Must be programmed to 0x00
0x00
0x4802
User Boot code
size (UBC)
OPT1
UBC[7:0]
0x00
0x4803
DATASIZE
OPT2
DATASIZE[7:0]
0x00
0x4807
PCODESIZE
OPT3
PCODESIZE[7:0]
0x00
0x4808
Window watchdog
and independent
window watchdog
OPT4
[3:0]
Reserved
WWDG WWDG IWDG IWDG
_HALT _HW _HALT _HW
0x00
Table 11. Option byte description
Option byte number
40/84
Description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Readout protection disabled (write access via SWIM protocol)
Refer to Read-out protection section in the STM8TL5xxx reference
manual (RM0312) for details.
OPT1
UBC[7:0] Size of the user boot code area
0x00: no UBC
0x01-0x02: UBC contains only the interrupt vectors.
0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is
available to store user boot code. Memory is write protected
...
0xFF: Page 0 to 254 reserved for UBC, memory is write protected
Refer to User boot area (UBC) section in the STM8TL5xxx reference
manual (RM0312) for more details.
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Option byte
Table 11. Option byte description (continued)
Option byte number
Description
OPT2
DATASIZE[7:0] Size of the data EEPROM area
0x00: no data EEPROM area
0x01: 1 page reserved for data storage from 0xBFC0 to 0xBFFF
0x02: 2 pages reserved for data storage from 0xBF80 to 0xBFFF
...
0x20: 32 pages reserved for data storage from 0xB800 to 0xBFFF
Refer to Data EEPROM (DATA) section in the STM8TL5xxx reference
manual (RM0312) for more details.
OPT3
PCODESIZE[7:0] Size of the proprietary code area
0x00: No proprietary code area
0x03: TRAP vector and page 2 (0x8080 to 0x80BF) reserved for the
proprietary code and read/write protected
...
0xFF: TRAP vector and page 2 to 254 (0x8080 to 0xBFBF) reserved for
the proprietary code and read/write protected
Refer to Proprietary code area (PCODE) section in the STM8TLxxxx
Programming Manual(PM0212) for more details.
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
OPT4
IWDG_HALT: Independent window watchdog reset on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt/Active-halt mode
1: Window watchdog continues running in Halt/Active-halt mode
Caution:
After a device reset, read access to the program memory is not guaranteed if address
0x4807 is not programmed to 0x00.
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41
Unique ID
8
STM8TL52x4 STM8TL53x4
Unique ID
STM8TL5xx4 devices feature a 96-bit unique device identifier which provides a reference
number that is unique for any device and in any context. The 96 bits of the identifier can
never be altered by the user.
The unique device identifier can be read in single byte and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:

For use as serial numbers

For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory

To activate secure boot processes
Table 12. Unique ID registers (96 bits)
Address
0x4925
0x4926
0x4927
Unique ID bits
7
6
5
4
3
U_ID[7:0]
X coordinate on
the wafer
U_ID[15:8]
U_ID[23:16]
0x4928
Y coordinate on
the wafer
0x4929
Wafer number
U_ID[39:32]
U_ID[31:24]
0x492A
U_ID[47:40]
0x492B
U_ID[55:48]
0x492C
U_ID[63:56]
0x492D
42/84
Content
description
Lot number
U_ID[71:64]
0x492E
U_ID[79:72]
0x492F
U_ID[87:80]
0x4930
U_ID[95:88]
DocID022344 Rev 7
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1
0
STM8TL52x4 STM8TL53x4
Electrical parameters
9
Electrical parameters
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
9.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature of TA= 25 °C and TA = TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
9.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given
only as design guidelines and are not tested.
9.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
9.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Figure 8. Pin loading conditions
STM8TL5xx4 PIN
50 pF
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Electrical parameters
9.1.5
STM8TL52x4 STM8TL53x4
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 9. Pin input voltage
STM8TL5xx4 PIN
VIN
9.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 13. Voltage characteristics
Symbol
Ratings
Min
Max
VDD- VSS
External supply voltage (including VDD and VDDIO)(1)
0.3
4.0
VSS0.3
PXS_VREG
(1.45)
Pins used as General
purpose I/O
VSS0.3
4.0
Pins used as transmitter
channel pins (PXS_Tx0 to
PXS_Tx15)
VSS0.3
PXS_VREG
1.45)
VSS0.3
4.0
Receiver channel pins (PXS_Rx0a...Rx9b)
VIN
(2)
Input voltage on 
PB0...7 and PD0...7(3)
Input voltage on any PA pins
VESD
Electrostatic discharge
voltage
Unit
V
see Absolute maximum ratings (electrical sensitivity) on
page 69
1. All power (VDD, VDDIO) and ground (VSS, VSSIO) pins must always be connected to the external power
supply.
2. VIN maximum must always be respected. Refer to Table 14. for maximum allowed injected current values.
3. Current injection on these pins is not allowed.
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STM8TL52x4 STM8TL53x4
Electrical parameters
Table 14. Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power line (source)
80
IVSS
Total current out of VSS ground line (sink)
80
Output current sunk by any other I/O and control pin
25
Output current source by any I/Os and control pin
25
IIO
IINJ(PIN)(1)
Injected current on PA pins
IINJ(PIN)
Injected current on PB pins
0
IINJ(PIN)
Injected current on PD pins
0
IINJ(PIN)(1)
(2)
±5
Total injected current (sum of all I/O and control pins)(2)
Unit
mA
±25
1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected.
2. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on characterization
with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 15. Thermal characteristics
Symbol
TSTG
Min
Unit
65 to +150
Storage temperature range
Maximum junction temperature
TJ
9.3
Ratings
150
°C
Operating conditions
Subject to general operating conditions for VDD and TA.
9.3.1
General operating conditions
Table 16. General operating conditions
Symbol
fMASTER(1)
VDD
PD
(2)
Parameter
Master clock frequency
Conditions
Min
Max
Unit
1.65 V VDD < 3.6 V
2
16
MHz
-
1.65
3.6
V
UQFPN48
-
625
UQFPN28
-
250
Standard operating voltage
Power dissipation at TA= 85
°C for suffix 2 devices
TSSOP20
mW
180
TA
Temperature range
1.65 V VDD 3.6 V
40
85
TJ
Junction temperature range
40 °C TA  85 °C
40
105
°C
1. fMASTER = fCPU.
2. To calculate PDmax(TA) use the formula given in thermal characteristics PDmax=(TJmax TA)/JA with TJmax
in this table and JA in table “Thermal characteristics”.
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Electrical parameters
9.3.2
STM8TL52x4 STM8TL53x4
Power supply
Figure 10. Power supply scheme
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1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These
capacitors must be placed as close as possible to, or below, the appropriate pins to ensure the correct
functionality of the device.
2. The 1µF capacitor must be connected to the VDD pin.
3. The 1µF ceramic capacitor connected to PXS_VREG must be low ESR (ESR  1).
9.3.3
Power-up / power-down operating conditions
Table 17. Operating conditions at power-up / power-down
Symbol
Parameter
tVDD
VDD rise time rate
tTEMP
Reset release delay
VPOR
VPDR
Conditions
VDD rising
Power on reset threshold
Power down reset threshold
1. Tested in production.
2. Data based on characterization results, not tested in production.
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Min.
Typ.
Max.
Unit
20
-
1300
µs/V
-
1
-
ms
1.44
(2)
1.30
(2)
-
(1)
V
(2)
V
1.65
1.60
STM8TL52x4 STM8TL53x4
9.3.4
Electrical parameters
ProxSense Regulator Voltage
Table 18. ProxSense voltage regulator characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Creg (1)
Voltage regulator
decoupling capacitance (2)
-
0.5
1
10
µF
Vreg
Regulated voltage during
acquisition
-
-
1.45
-
V
Typ.
Max.(3)
Unit
fMASTER = 2 MHz
0.4
0.6
fMASTER = 4 MHz
0.55
0.7
fMASTER = 8 MHz
0.9
1.2
fMASTER = 16 MHz
1.6
2.1(4)
fMASTER = 2 MHz
0.56
0.7
fMASTER = 4 MHz
0.88
1.8
fMASTER = 8 MHz
1.5
2.5
fMASTER = 16 MHz
2.8
3.5
1. The capacitor must be routed as close as PXS_VREG as possible (≤ 1cm)
2. Equivalent serial resistor ≤ 1Ω
9.3.5
Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:

All I/O pins in input mode with a static value at VDD or VSS (no load)

All peripherals are disabled except if explicitly mentioned
Subject to general operating conditions for VDD and TA.
Table 19. Total current consumption in Run mode (1)
Symbol
Parameter
Conditions(2)
Code executed from
RAM
Supply
IDD (Run) current in
Run mode
Code executed from
Flash
mA
1. Based on characterization results, unless otherwise specified.
2. All peripherals off, VDD from 1.65 V to 3.6 V, HSI internal RC oscillator, fCPU=fMASTER.
3. Maximum values are given for TA = 40 to 85 °C.
4. Tested in production.
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STM8TL52x4 STM8TL53x4
Figure 11. IDD(RUN) vs. VDD, fCPU = 16 MHz
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Table 20. Total current consumption in Wait mode(1)
Symbol
Parameter
Supply
IDD(Wait) current in
Wait mode
Typ.
Max.(2)
fMASTER = 2 MHz
260
400
fMASTER = 4 MHz
300
450
fMASTER = 8 MHz
380
600
fMASTER = 16 MHz
500
800
Conditions
CPU not clocked, 
all peripherals off,
HSI internal RC osc
1. Based on characterization results, unless otherwise specified.
2. Maximum values are given for TA = 40 to 85 °C.
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µA
STM8TL52x4 STM8TL53x4
Electrical parameters
Figure 12. IDD(Wait) vs. VDD. fCPU = 16 MHz
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STM8TL52x4 STM8TL53x4
Table 21. Total current consumption in Halt mode and Active-halt mode
VDD = 1.65 V to 3.6 V(1) (2)
Symbol
Parameter
Conditions
Typ.
Max.
Unit
IDD(AH)
Supply current in Active-halt
mode
LSI RC osc. TA = 40 °C to 25 °C
(at 38 kHz) T = 85 °C
A
1
2
A
1.4
3.2
A
fCPU = 16 MHz
2
-
mA
fCPU= 16 MHz
4
6.5
s
TA = 40 °C to 25 °C
0.4
1.2(4)
A
TA = 85 °C
1
2.5(4)
A
Supply current during
IDD(WUProx) wakeup time from Active halt
mode (using HSI)
tWU(AH)(3)
Wakeup time from Activehalt mode to Run mode
IDD(Halt)
Supply current in Halt mode
IDD(WUFH)
Supply current during
wakeup time from Halt mode
fCPU = 16 MHz
2
-
mA
tWU(Halt)
Wakeup time from Halt mode
to Run mode
fCPU = 16 MHz
4
6.5
s
1. TA = 40 to 85 °C, no floating I/O, unless otherwise specified.
2. Data based on characterization, not tested in production.
3. Measured from interrupt event to interrupt vector fetch. To get tWU for another CPU frequency use
tWU(FREQ) = tWU(16 MHz) + 1.5 (TFREQ-T16 MHz). The first word of interrupt routine is fetched 5 CPU
cycles after tWU.
4. Tested in production.
Figure 13. Typ. IDD(Halt) vs. VDD. fCPU = 2 MHz and 16 MHz
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Electrical parameters
Current consumption of on-chip peripherals
Measurement made for fMASTER = from 2 MHz to 16 MHz
Table 22. Peripheral current consumption
Symbol
Parameter
IDD(TIM2)
TIM2 supply current
IDD(TIM3)
TIM3 supply current(1)
IDD(TIM4)
Typ. VDD = 3.0 V
(1)
TIM4 timer supply current
Unit
9
9
(1)
(2)
4
IDD(USART)
USARTsupply current
IDD(SPI)
SPI supply current(2)
4
IDD(I²C)
I2C supply current(2)
4
7
µA/MHz
1. Data based on a differential IDD measurement between all peripherals off and a timer counter running at 
16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in
production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in
both cases. No I/O pin toggling. Not tested in production.
Current consumption with ProxSense peripherals
Measurement made for fMASTER = 16 MHz, fProxSense = 16 MHz, all other peripherals off and
under the following conditions:
PXS_RxiCSSELR (Sampling Capacitor) = 0x10
PXS_RxiEPCCSELR (Electrode Parasitic Capacitance Compensation) = 0x80
Capacitance between Tx and Rx of 10nF
Table 23. ProxSense peripheral current consumption(1)
Symbol
IDD(PXS)
ProxSense
transmitter
Tx
ProxSense
receiver
Rx
Typical
1
1
0.6
1
4
1.1
1
10
2.3
Unit
mA
1. Data based on characterization, not tested in production
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9.3.6
STM8TL52x4 STM8TL53x4
Clock and timing characteristics
Internal clock source
The parameters given in Table 24 are derived from tests performed under ambient
temperature and VDD supply voltage. They are subject to general operating conditions for
VDD and TA.
High speed internal RC oscillator
Table 24. HSI oscillator characteristics(1)
Symbol
Parameter
Frequency
fHSI
Min.
Typ.
Max.
Unit
-
16
-
MHz
VDD = 3.0 V, TA = 25 °C
1
-
1
%
1.65 V  VDD  3.6 V,
TA = -40 to 85°C
3
-
3
%
-
70
100
µA
VDD = 3.0 V
Accuracy of HSI
ACCHSI oscillator (factory
calibrated)
IDD(HSI)
Conditions
HSI oscillator power
consumption
1. VDD = 3V, TA = 40 to 125 °C, unless otherwise specified.
Figure 14. Typical HSI frequency vs. VDD
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Electrical parameters
Figure 15. Typical HSI accuracy vs. temperature, VDD = 3 V
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Table 25. HSI_PXS oscillator characteristics(1)
Symbol
fHSI_PXS
Parameter
Conditions
Frequency
VDD = 3.0 V
Min.
Typ.
Max.
Unit
-
16
-
MHz
1. VDD = 3V, TA = 40 to 85 °C, unless otherwise specified.
Low speed internal RC oscillator (LSI)
Table 26. LSI oscillator characteristics (1)
Symbol
fLSI
fdrift(LSI)
Parameter
Conditions
Frequency
LSI oscillator frequency
drift(2)
0 °C TA  85°C
Min.
Typ.
Max.
Unit
26
38
56
kHz
12
-
11
%
1. VDD = 1.65 V to 3.6 V, TA = 40 to 85°C unless otherwise specified.
2. For each individual part, this value is the frequency drift from the initial measured frequency.
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Figure 16. Typical LSI frequency vs. VDD
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9.3.7
Memory characteristics
TA = 40 to 85°C unless otherwise specified.
RAM characteristics
Table 27. RAM and hardware registers
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VRM
Data retention mode (1)
Halt mode (or Reset)
1.4
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
Flash memory characteristics
Table 28. Flash program memory
Symbol
VDD
tprog
Iprog
Conditions
Min.
Typ.
Max.(1)
Unit
fMASTER = 16 MHz
1.65
-
3.6
V
Programming time for 1 or 64 byte (block)
erase/write cycles (on programmed byte)
-
6
-
ms
Programming time for 1 to 64 byte (block)
write cycles (on erased byte)
-
3
-
ms
Parameter
Operating voltage 
(all modes, read/write/erase)
Programming/ erasing consumption
TA+25 °C, VDD = 3.0 V
-
TA+25 °C, VDD = 1.8 V
-
1. Data based on characterization results, not tested in production.
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-
mA
STM8TL52x4 STM8TL53x4
Electrical parameters
Table 29. Program memory endurance and retention
Parameter
Endurance
Data retention
Conditions
TA = –40 to 85°C
10 kcycles at TA = 85°c
Min.
Typ.
Max.
Unit
10(1)
-
-
kcycles
(1)
-
-
Years
30
1. Data based on characterization results, not tested in production.
Table 30. Data memory endurance and retention
Parameter
Endurance
Data retention
Conditions
TA = 40 to 85°C
300 kcycles at TA = 85°c
Min.
Typ.
Max.
Unit
300(1)(2)
-
-
kcycles
-
-
Years
(1)
30
1. Data based on characterization results, not tested in production.
2. Data based on characterization performed on the whole data memory (2 Kbyte).
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9.3.8
STM8TL52x4 STM8TL53x4
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 31. I/O static characteristics (1)
Symbol
Parameter
(2)
Conditions
Min.
Typ.
Max.
Unit
VIL
Input low level voltage
Standard I/Os
VSS0.3
-
0.3 x VDD
VIH
Input high level voltage(2)
Standard I/Os
0.70 x VDD
-
VDD+0.3
Vhys
Schmitt trigger voltage hysteresis(3)
Standard I/Os
-
200
-
VSS VIN  VDD
-
-
50
VSS VIN  Vreg Rx,
Tx I/Os
-
-
50
VIN VSS
30
45
60
k
-
-
5
-
pF
current(4)
Ilkg
Input leakage
RPU
Weak pull-up equivalent resistor(5)
CIO(6)
I/O pin capacitance
V
mV
nA
1. VDD = 3.0 V, TA = 40 to 85 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The maximum value may be exceeded if negative current is injected on adjacent pins.
5. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics.
6. Data guaranteed by Design, not tested in production.
Figure 17. Typical pull-up resistance RPU vs. VDD with VIN=VSS
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Electrical parameters
Figure 18. Typical VIL and VIH vs VDD
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STM8TL52x4 STM8TL53x4
Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 32. Output driving current (high sink ports)
I/O type
Symbol
VOL(1)
Parameter
Output low level voltage for an I/O pin
Standard
VOH(2)
ProxSense
I/O
Output high level voltage for an I/O pin
Conditions
Min.
Max.
IIO = +2 mA,
VDD = 1.8 V
-
0.45
IIO = +2 mA,
VDD = 3.0 V
-
0.45
IIO = +10 mA,
VDD = 3.0 V
-
0.7
IIO = 1 mA,
VDD = 1.8 V
VDD-0.45
-
IIO = 1 mA,
VDD = 3.0 V
VDD-0.45
-
IIO = 10 mA,
VDD = 3.0 V
VDD-0.7
-
Unit
V
VOH
Output high level voltage for PXS_TX
ProxSense I/O
IPXS_TX = 0.2 mA
VREG
-
VOH
Output high level voltage for PXS_RX
ProxSense I/O
IPXS_RX = 0.1 mA
VREG
-
1. The IIO current sunk must always respect the absolute maximum rating and the sum of IIO (I/O ports and control pins) must
not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating and the sum of IIO (I/O ports and control pins)
must not exceed IVDD.
Figure 19. Typ. VOL at VDD = 1.8 V (standard ports)
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Figure 20. Typ. VOL at VDD = 3.0 V (standard ports)
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Figure 21. Typ. VDD - VOH at VDD = 1.8 V (standard ports)
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STM8TL52x4 STM8TL53x4
Figure 22. Typ. VDD - VOH at VDD = 3.0 V (standard ports)
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Figure 23. Typ. VDD - VOH at VDD = 1.8 V (ProxSense TX ports)
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Figure 24. Typ. VDD - VOH at VDD = 1.8V (ProxSense RX ports)
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Electrical parameters
STM8TL52x4 STM8TL53x4
NRST pin
The NRST pin input driver is CMOS. A permanent pull-up is present which is the same as
RPU (see Table 31 on page 56).
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 33. NRST pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.(1)
Max.
-
VSS
-
0.8
-
1.4
-
VDD
NRST input low level voltage(1)
VIL(NRST)
VIH(NRST)
(1)
NRST input high level voltage
IOL = 2 mA
-
-
VDD0.8
NRST pull-up equivalent resistor(2)
-
30
45
60
VF(NRST)
NRST input filtered pulse(3)
-
-
-
50
tOP(NRST)
NRST output pulse width
-
20
-
-
-
300
-
-
VOL(NRST)
NRST output low level voltage
RPU(NRST)
VNF(NRST)
NRST input not filtered
pulse(3)
Unit
V
k
ns
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.
The reset network shown in Figure 26 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 33. Otherwise the reset is not taken into account internally.
Figure 25. Typical NRST pull-up resistance RPU vs. VDD
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STM8TL52x4 STM8TL53x4
Electrical parameters
Figure 26. Recommended NRST pin configuration
VDD
RPU
RSTIN
EXTERNAL
RESET
CIRCUIT
0.1F
Filter
INTERNAL RESET
STM8TL5xx4
The reset network shown in Figure 26 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 33. Otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the capacity of the external reset capacitor
can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the
external circuitry, the user must pay attention to the charge/discharge time of the external
capacitor to meet the reset timing conditions of the external devices. The minimum
recommended capacity is 10 nF.
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70
Electrical parameters
9.3.9
STM8TL52x4 STM8TL53x4
Communication interfaces
Serial peripheral interface (SPI)
The parameters given in Table 34 are derived from tests performed under ambient
temperature, fMASTER frequency and VDD supply voltage conditions summarized in
Section 9.3.1 on page 45, unless otherwise specified. Refer to I/O port characteristics for
more details on the input/output alternate function characteristics (NSS, SCK, MOSI,
MISO).
Table 34. SPI characteristics
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
Parameter
SPI clock frequency
SPI clock rise and fall time
Conditions(1)
Min.
Max.
Master mode
0
8
Slave mode
0
8
Capacitive load: C = 30 pF
-
30
tsu(NSS)(2)
NSS setup time
Slave mode
4 x tMASTER
-
th(NSS)(2)
NSS hold time
Slave mode
80
-
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
105
145
Master mode
30
-
Slave mode
3
-
Master mode
15
-
Slave mode
0
-
(2)
tw(SCKH)
tw(SCKL)(2)
SCK high and low time
tsu(MI) (2)
tsu(SI)(2)
Data input setup time
th(MI) (2)
th(SI)(2)
Data input hold time
ta(SO)(2)(3)
Data output access time
Slave mode
-
3x tMASTER
tdis(SO)(2)(4)
Data output disable time
Slave mode
30
-
(2)
Data output valid time
Slave mode (after enable edge)
-
60
tv(MO)(2)
Data output valid time
Master mode
(after enable edge)
-
20
Slave mode (after enable edge)
15
-
Master mode
(after enable edge)
1
-
tv(SO)
th(SO)(2)
th(MO)(2)
Data output hold time
1. Parameters are given by selecting 10MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in HiZ.
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Unit
MHz
ns
STM8TL52x4 STM8TL53x4
Electrical parameters
Figure 27. SPI timing diagram - slave mode and CPHA = 0
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Figure 28. SPI timing diagram - slave mode and CPHA = 1(1)
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical parameters
STM8TL52x4 STM8TL53x4
Figure 29. SPI timing diagram - master mode(1)
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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STM8TL52x4 STM8TL53x4
Electrical parameters
Inter IC control interface (I2C)
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise
specified.
The STM8TL5xx4 I2C interface meets the requirements of the Standard I2C communication
protocol described in the following table with the restrictions mentioned below.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 35. I2C characteristics
Standard mode I2C
Symbol
Parameter
Fast mode I2C(1)
Min(2)
Max (2)
Min (2)
Max (2)
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
-
(4)
(3)
Unit
s
900 (3)
th(SDA)
SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
START condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated START condition setup
time
4.7
-
0.6
-
tsu(STO)
STOP condition setup time
4.0
-
0.6
-
s
tw(STO:STA)
STOP to START condition time 
(bus free)
4.7
-
1.3
-
s
Cb
Capacitive load for each bus line
-
400
-
400
pF
0
0
ns
s
1. fSCK must be at least 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL).
Note:
For speeds around 200 kHz, achieved speed can have 5% tolerance.
For other speed ranges, achieved speed can have  2% tolerance.
The above variations depend on the accuracy of the external components used.
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Electrical parameters
STM8TL52x4 STM8TL53x4
Figure 30. Typical application with I2C bus and timing diagram 1)
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1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
9.3.10
EMC characteristics
Susceptibility tests are performed on a sample 36 basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).

ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
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STM8TL52x4 STM8TL53x4
Electrical parameters
Table 36. EMS data
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
UFQFPN48, VDD 3.3 V
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
UFQFPN48, VDD 3.3 V, fHSI
3B
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 37. EMI data (1)
Symbol
SEMI
Parameter
Peak level
Conditions
VDD 3.6 V,
TA +25 °C
Monitored frequency
band
Max vs. 16
MHz
0.1 MHz to 30 MHz
-5
30 MHz to 130 MHz
-5
130 MHz to 1 GHz
0
SAE EMI Level
1
Unit
dBV
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
Table 38. ESD absolute maximum ratings
Symbol
Ratings
VESD(HBM)
Electrostatic discharge voltage
(human body model)
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
Conditions
Maximum
value (1)
Unit
2000(2)
TA +25 °C
V
1000
1. Data based on characterization results, not tested in production.
2. Device sustained up to 3000 V during ESD trials.
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Electrical parameters
STM8TL52x4 STM8TL53x4
Static latch-up

LU: 3 complementary static tests are required on 6 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to application note AN1181.
Table 39. Electrical sensitivities
9.4
Symbol
Parameter
Class
LU
Static latch-up class
II
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 16: General operating conditions on page 45.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax x JA)
Where:

TAmax is the maximum ambient temperature in C

JA is the package junction-to-ambient thermal resistance in C/W

PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)

PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip
internal power.

PI/Omax represents the maximum power dissipation on output pins
where:
PI/Omax = (VOL*IOL) + ((VDDVOH)*IOH), 
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in
the application.
Table 40. Thermal characteristics(1)
Symbol
JA
Parameter
Value
Thermal resistance junction-ambient
UFQFPN 48 - 7 x 7 mm
32
Thermal resistance junction-ambient
UFQFPN 28 - 4 x 4 mm
80
Thermal resistance junction-ambient
TSSOP20
110
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
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Unit
°C/W
STM8TL52x4 STM8TL53x4
Package information
10
Package information
10.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:www.st.com.
ECOPACK® is an ST trademark.
10.2
UFQFPN48 package information
Figure 31. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DocID022344 Rev 7
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Package information
STM8TL52x4 STM8TL53x4
Table 41. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
D
6.900
7.000
7.100
0.2717
0.2756
0.2795
E
6.900
7.000
7.100
0.2717
0.2756
0.2795
D2
5.500
5.600
5.700
0.2165
0.2205
0.2244
E2
5.500
5.600
5.700
0.2165
0.2205
0.2244
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
T
-
0.152
-
-
0.0060
-
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
e
-
0.500
-
-
0.0197
-
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 32. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
1. Dimensions are expressed in millimeters.
72/84
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!"?&0?6
STM8TL52x4 STM8TL53x4
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 33. UFQFPN48 marking example (package top view)
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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID022344 Rev 7
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79
Package information
10.3
STM8TL52x4 STM8TL53x4
UFQFPN28 package information
Figure 34. UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
'HWDLO<
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1. Drawing is not to scale.
Table 42. UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data(1)
millimeters
inches
Symbol
74/84
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
-
0.000
0.050
-
0.0000
0.0020
D
3.900
4.000
4.100
0.1535
0.1575
0.1614
D1
2.900
3.000
3.100
0.1142
0.1181
0.1220
E
3.900
4.000
4.100
0.1535
0.1575
0.1614
E1
2.900
3.000
3.100
0.1142
0.1181
0.1220
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
L1
0.250
0.350
0.450
0.0098
0.0138
0.0177
T
-
0.152
-
-
0.0060
-
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
e
-
0.500
-
-
0.0197
-
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Package information
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 35. UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
!"?&0?6
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 36. UFQFPN28 marking example (package top view)
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1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
DocID022344 Rev 7
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79
Package information
STM8TL52x4 STM8TL53x4
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
10.4
TSSOP20 package information
Figure 37.TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
$
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1. Drawing is not to scale.
Table 43. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
inches(1)
millimeters
Symbol
76/84
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.200
-
-
0.0472
A1
0.050
-
0.150
0.0020
-
0.0059
A2
0.800
1.000
1.050
0.0315
0.0394
0.0413
b
0.190
-
0.300
0.0075
-
0.0118
c
0.090
-
0.200
0.0035
-
0.0079
D(2)
6.400
6.500
6.600
0.2520
0.2559
0.2598
E
6.200
6.400
6.600
0.2441
0.2520
0.2598
E1(3)
4.300
4.400
4.500
0.1693
0.1732
0.1772
e
-
0.650
-
-
0.0256
-
DocID022344 Rev 7
STM8TL52x4 STM8TL53x4
Package information
Table 43. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
-
8°
0°
-
8°
aaa
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 38. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
9!?&0?6
1. Dimensions are expressed in millimeters.
DocID022344 Rev 7
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Package information
STM8TL52x4 STM8TL53x4
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 39. TSSOP20 marking example (package top view)
3URGXFWLGHQWLILFDWLRQ
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'DWHFRGH
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3LQLGHQWLILHU
06Y9
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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11
Part numbering
Part numbering
Table 44. Ordering information scheme
STM8
Example:
T
L
5
3
G
4
U
6
TR
Device type
STM8 microcontroller family
Product type
T = Touch sensing
Device family
L = low-power
Sub-family type
5 = Projective capacitive sub-family
Peripheral set
2 = Light
3 = Basic
Pin count
C = 48 pins
G = 28 pins
F = 20 pins
Program memory size
4 = 16 Kbyte
Package type
U = UFQFPN
P = TSSOP
Temperature range
6 = -40 °C to +85 °C
Shipping
TR = Tape and Reel
Blank = Tray
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to
you.
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STM8 development tools
12
STM8TL52x4 STM8TL53x4
STM8 development tools
Development tools for the STM8 microcontrollers include the very low-cost debugger and
programmer tool ST-Link supported by a complete software tool package including C
compiler, assembler and integrated development environment with high-level language
debugger. In addition, the STM8 is to be supported by a complete range of tools including
starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.
12.1
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code
is available.
12.1.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST Visual Develop (STVD) – Full-featured integrated development environment from ST,
featuring

Seamless integration of C and ASM toolsets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
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12.1.2
STM8 development tools
STM-STUDIO
STM-STUDIO helps debug and diagnose STM8 and STM32 applications while they are
running by reading and displaying their variables in real-time. STM-STUDIO perfectly
complements traditional debugging tools to fine tune applications. It is well suited for
debugging applications which cannot be stopped, such as TouchSensing applications. Its
easy-to-use, graphical interface features:
12.1.3

Non-intrusive read on-the-fly variables from RAM while the application is running

Parse DWARF debugging information in the ELF application executable file

Possibility to log data into a file, and replay later (exhaustive record display, not realtime)

2 types of viewers:
–
Variable viewer: Real-time waveforms, oscilloscope-like graphs
–
TouchPoint viewer: Association of 2 variables, one on the X axis, one on the Y axis
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
12.2

Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code
is available. For more information, see www.cosmic-software.com.

IAR embedded workbench – The C compiler for STM8 which is included in the toolset
is free for up to 8Kbytes of code. For more information, see www.iar.com.

Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of
code. For more information, see www.raisonance.com.

STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows you to assemble and link your application source code.
Programming tools
During the development cycle, ST-Link provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
Table 45. Document revision history
Date
Revision
14-Oct-2011
1
Initial release
2
Added STM8TL52G4, STM8TL52F4, STM8TL53F4 part numbers
Added Figure 14, Figure 16, Figure 17, Figure 18, Figure 19,
Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25,
Figure 26
Updated Figure 31 and Table 41
Added TSSOP20 package
06-Aug-2013
3
Removed “STICE” references and edited the text in Section 3.2:
Development tools and Section 12: STM8 development tools.
In Table 7: General hardware register map:
– changed the Reset status from “0x00” to “0x01” on
“CLK_PCKENR2” row,
– split address block “0x00 5055 to 0x00 509F” into “0x00 5055 to
0x00 509D” with “Reserved, “0x00 509E” with “SYSCFG” and
“0x00 509F” with “Reserved”,
– added a footnote to RST_SR Reset status value,
– updated CLK_CCOR Reset status value to “0x10”.
Updated description of OPT0 in Table 11: Option byte description.
Updated VIN Max values in Table 13: Voltage characteristics.
Added Section 9.3.4: ProxSense Regulator Voltage.
Removed ACCHSI_PXS rows from Table 25: HSI_PXS oscillator
characteristics and removed former Figure 17 Typical HSI_PXS
frequency vs. VDD.
Added tprog and Iprog Max. values to Table 28: Flash program
memory.
Removed VOL row with Conditions IIO=+20 mA and VDD=3.0 V from
Table 31: I/O static characteristics.
Updated “ProxSense I/O” Conditions and Min. values in Table 32:
Output driving current (high sink ports).
Added Section 3.13: General purpose and basic timers.
07-Aug-2013
4
Updated OPT0 default value in Table 10: Option byte.
5
Updated:
– Figure 27: SPI timing diagram - slave mode and CPHA = 0,
– Section 10.2: UFQFPN48 package information,
– Section 10.3: UFQFPN28 package information,
– Section 10.4: TSSOP20 package information.
Added:
– Figure 33: UFQFPN48 marking example (package top view),
– Figure 36: UFQFPN28 marking example (package top view),
– Figure 39: TSSOP20 marking example (package top view).
04-Apr-2012
18-Mar-2015
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Revision history
Table 45. Document revision history (continued)
Date
Revision
Changes
28-May-2015
6
Updated Figure 27: SPI timing diagram - slave mode and CPHA = 0.
01-Jul-2015
7
Added the footnotes about “D” and E1” dimensions below Table 43:
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm
pitch, package mechanical data.
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