G 5 CONTROL DATA CORPORATION

G 5 CONTROL DATA CORPORATION
60472800
e 5) CONTROL DATA
CORPORATION
CDC * NETWORK PROCESSOR UNIT
2551-1
2551-2
2551-3
2551-4
2552-2
HARDWARE REFERENCE MANUAL
REVISION RECORD
REVISION
01 Preliminary edition
9/77
A Initial release
(04-28-78) |
B Revised to incorporate Engineering Change Orders 8050, 8062, 8130, 8039, 8240,
(12-15-78) 8216, and 8110. Editorial change only on page 1-5. Page 4-1 deleted.
C Revised to incorporate latest configuration changes and requests on comment sheet.
(04-15-80) | This edition obsoletes the previous revisions.
D Manual revised; includes Engineering Change Order 44344. Front Cover through vii,
(03-04-83) ix, x, 1-1 through 1-17, 2-2, and 2-12 are revised. Pages 1-18 through 1-20 are
| added. | | |
60472800
REVISION LETTERS I, O, Q, S, X AND Z ARE NOT USED
Address comments concerning this
manual to:
Control Data Corporation
Publications and Graphics Division
| o 4201 North Lexington Avenue
e 1977, 1978, 1980, 1983 | St. Paul, Minnesota 55112
by Control Data Corporation 1 ©
AU rights reserve а or use Comment Sheet in the back of
Printed in the United States of America | this manual.
LIST OF EFFECTIVE PAGES
New features, as well as changes, deletions, and additions to information in this manual, are indicated by bars in the margins or by a dot
near the page number if the entire page is affected. A bar by the page number indicates pagination rather than content has changed.
PAGE REV. - PAGE REV PAGE REV PAGE REV PAGE REV |
Front Cover - 3-12 C 4-35 C
Title Page - 3-13 C 4-36 C
ii D || 3-14 C 4-37 C
iii/iv D 3-15 C 4-38 C
v D 3-16 С 4-39 С
vi D 3-17 С 4-40 С
vii D 3-18 С 4-41 C
viii C 3-19 C 4-42 С
ix D 3-20 C 4-43 C
x D 3-21 C 4-44 C
1-1 D 3-22 C 4-45 C
1-2 D 3-23 C 4-46 C
1-3 D 3-24 C 4-47 С
1-4 D 3-25 С 4-48 C
1-5 D 3-26 C 4-49 C
1-6 D 3-27 C 4-50. С
1-7 D 3-28 С 4-51 C
1-8 D 3-29 С 4-52 С
1-9 D 3-30 С 4-53 C
1-10 D 3-31 C 4-54 С
1-11 D 3-32 C 4-55 C
1-12 D 3-33 С 4-56 С
1-13 D 113-34 C 4-57 C
1-14 D 3-35 C 4-58 С
1-15 D 3-36 с 4-59 С
1-16 D 4-1 С 4-60 C
1-17 D 4-2 С 4-61 C
1-18 D 4-3 С 4-62 С
1-19 D 4-4 С 4-63 C
1-20 D 4-5 с 4-64 С
2-1 С 4-6 С 4-65 С
2-2 D 4-7 C 4-66 C
2-3 С 4-8 C 5-1 C
2-4 C 4-9 С 5-2 С
2-5 C 4-10 С 5-3 Cc
2-6 С 4-11 C 5-4 C
2-7 С 4-12 C | 15-5 С
2-8 C 4-13 С 5-6 C
2-9 C 4-14 C 5-7 C
2-10 С 4-15 С 5-8 C
2-11 C 4-16 C A-1 C
2-12 D 4-17 C B-1 C
2-13 С 4-18 С B-2 C
2-14 С 4-19 C Comment
2-15 C 4-20 C Sheet D
2-16 С 4-21 С Back Cover -
2-17 С 4-22 C
2-18 С 1114-23 C
3-1 С 4-24 Cc
3-2 C 4-25 C
3-3 C 4-26 C
3-4 C 4-27 С.
3-5 C 4-28 С
3-6 С 4-29 C
3-7 С 4-30 С
3-8 С 4-31 C
3-9 С 14-32 [e
3-10 C {14-33 С
3-11 С. 4-34 С
60472800 D | iii/iv
PREFACE
This manual describes the physical, functional, operational, and programming
characteristics of the CDC® 2551-1, 2551-2, 2551-3, 2551-4, and 2552-2 Network
Processor Units (NPUs). The manual includes the various NPU configurations,
which are available to the user by addition of standard product options and
upgrade kits.
This manual is intended for use by customer, marketing, training, and
programming personnel. For an in-depth analysis of the product structure,
operation, and maintenance, refer to the NPU hardware maintenance manual.
The related publications listed below are available through CDC Literature and
Distribution Services, 308 North Dale Street, St. Paul, Minnesota 55103.
Publication Title Publication Number
Basic Microprogrammable Processor, |
Hardware Maintenance Manual 39451400
1714 Computer System, |
Reference Manual | 60364900
3000L Communications Coupler DY161-A, |
Hardware Reference/Maintenance Manual | 60470400
2552-1 6000 Coupler,
Hardware Maintenance Manual 60471900
Cyclic Encoder DY180-A, |
Hardware Maintenance Manual 60472600
2550-101 Emulation Controlware,
Reference Manual 60474000
2550-101 Installation Handbook 60474100
2551-1, 2551-2, 2551-3, 2551-4, 2552-2
Network Processor Unit Host Communications |
Processor 2550-2 Site Preparation Manual 74641200
Synchronous Communications Line
Adapter DUl138-A, DUl139-A, DUl140-A, |
Hardware Maintenance Manual ° 74700700
Asynchronous Communications Line
Adapter DUl137-A, Hardware Maintenance
Manual | 74700900
Communications Line Adapter,
Synchronous Data Link Control DY162-A,
Hardware Maintenance Manual | 74873290
60472800 D | | | | \
vi
Communications Coupler DK106-B,
Hardware Maintenance Manual 74873946
Network Processor Unit Equipment |
Cabinets, Hardware Maintenance Manual 74873971
System Autostart Module DY204-A, |
Hardware Maintenance Manual 74874450
Emulation Coupler DY159-A, XA226-A, |
Hardware Maintenance Manual 74879600
Tape Cassette Controller FA104-A,
Hardware Maintenance Manual 96711900
255X Host Communications Processor/
Network Processor Unit, Reference |
Manual, CCP Version 1.0 60470000
Transform with Micromemory DE402-A/
1700, Hardware Maintenance Manual 96728700
I/O TTY Controller CW212-a,
Hardware Maintenance Manual 96728900
MP17 Communications Processor,
Hardware Reference Manual 96768300
1700 Enhanced Processor with MOS
Memory and Interface AA109-A/B,
Hardware Maintenance Manual 96768600
AAl109-A/B (AAl35-A) Communications Controller о
Field Print Package | 60475150
WARNING
This equipment generates, uses and can radiate radio fre-
quency energy, and if not installed and used in accordance
„With the instructions manual, may cause interference to
radio communications. It has been tested and found to
comply with the limits for a Class A peripheral computing
device pursuant to Subpart J of Part 15 of the FCC rules,
which are designed to provide reasonable protection against
such interference when operated in a commercial environ-
ment. Operation of this equipment in a residential area
is likely to cause interference in which case the user, at
his own expense, will be required to take whatever measures
may be required to correct the interference.
60472800 D
CONTENTS
1. SYSTEM DESCRIPTION
Major Features
Network Communications System
Concepts
Physical Description
2551-1 NPU Equipment
2551-2 NPU Equipment
2551-3 NPU Equipment
2551-4 NPU Equipment.
Communications Processor
2552-2 NPU Equipment
Base Processor
Multiplex Processor
Cross-Control and Console
Switch
Communications Console
Communications Coupler
Multiplex Subsystem
Communications Line
Adapters
LOOp Multiplexer
Multiplex Loop Interface
Adapter
Maintenance Panel
Cassette Tape Drive
System Autostart Module
Power Supplies
Cabling
Air Blowers and Filter
Assemblies
Expansion Systems
Electromagnetic Interference
Protection
Functional Description
Processor
Coupler
Multiplex Subsystem
Operating Programs and
Diagnostics
Maintenance
Communications Software
Host Software |
Communications Control
Software |
Base System Software
Network Communications
Software
Interface Programs
Support Software
60472800 D
hh a ha ho ню к
|
FH © O OS Y 7 4 43 UT Un
1-20
2. FUNCTIONAL DESCRIPTION
NPU Main Data Paths
Basic Emulation Concepts
Interrupt System
Macrointerrupts
Microinterrupts
Status/Mode and
Interrupt Bits
Automatic Data Transfer
Mode
Multiplex Loop Interface
Adapter Interrupts
Real-Time-Clock
Interrupts
Interrupt Holding Registers
NPU Components Functional
Description
Single Processor
Microprocessor
Panel/Console Interface
1/0 Subsystem
Cyclic Encoder
Main Memory
Dual Processor
Console Switch
Processor Cross Control
Multiplex Subsystem
Multiplex Loop Interface
Adapter
Loop Multiplexer
Communications Line Adapter
Tape Cassette
System Autostart Module
Communications Coupler
3. OPERATING INSTRUCTIONS
Function Control Register
Control and Indicators
Maintenance Panel
Communications Console
I/O TTY Interface
Cyclic Encoder
"Loop Multiplexer
Multiplex Loop Interface
Adapter
Lo
|
WWW Ww Ww 19
ob Ede FH
La
|
>
UN
vii
Communications Line
Adapter |
Communications Coupler
Clock Adjustment
Clock Indicator
On-Line Switch
DIP Switch
Micromemory
Cassette Tape Controller
Equipment Switch Assembly
Control Functions Switch
Assembly
Cassette Tape Drive
Lid Interlock Switch
Side A/B Switch
Write Enable Switch
Console Switchbox
System Autostart Module
Start-Up Procedure
System Autostart Module
Operation
Operating Procedures
Master Clear
Display Contents
Clear Bit
Set Bit
Change Contents (Digit Mode)
Change Contents (Bit Mode)
Toggle Upper Indicator
Display Register Contents
(Display 0)
Display Register Contents
(Display 1)
Load A Register (Display 0)
Load A Register (Display 1)
Tape Cassette Autoload |
Host Computer Autoload
Start Processor
Stop Processor
Procedure Examples
Display Main Memor
Location |
Write Into Main Memory
Display P Register in
Repeat Mode
Operation in Step Mode
Load and Execute
Macroprogram
Hexadecimal/Decimal
Conversion
viii
— Emergency-Off Procedure
3-15 Checks and Adjustments
3-17 Shutdown Procedure
3-17
3-19
COMMUNICATIONS PROCESSOR
3-19 INSTRUCTIONS
3-19
3-19 Macroinstruction Formats and
3-22 Instructions
3-22 Basic Macroinstruction
Formats
3-23 Enhanced Macroinstruction
3-24 Formats
3-24 Storage Reference
3-24 Instruction Format
3-25 Storage Reference
3-25 Instructions
3-25 Register Reference
3-25 Instruction Format
Register Reference
3-25 Instructions
3-27 Enhanced Instructions
3-27 Type 2 Storage Reference
3-27 Instructions
3-28 Field Reference
3-28 Instructions
3-28 Type 2 Skip Instructions
3-29 Decrement and Repeat
3-29 Instructions
Type 2 Interregister
3-30 | Instructions
о Miscellaneous Instructions
3-30 Autodata Transfer
3-31 Macroinstruction Timing
3-31 Microprogramming Usage
3-32 Microinstruction Formats
3-32 Detailed Microinstruction
3-33 Coding
3-33 M Field (Bits 0 and 1)
3-33 F Field (Bits 2 Through 6)
Logical Operations
3-33 Arithmetic Operations
3-34 Shift Operations
Scale Operations
3-34 Microinstruction Timing
3-35 |
3-35 1/0 PROGRAMMING FORMATS
APPENDIXES
A-1 Mnemonics Listing
3-36
3-36
3-36
4-25
4-40
4-43
4-43
4-43
4-44
4-44
4-45
4-47
4-64
60472800 C
FIGURES
2551-1, 2551-2, 2551-3, and
2551-4 Network Processor
Unit Block Diagram 1-3
2552-2 Network Processor
Unit Block Diagram 1-4
Single Node System,
Block Diagram 1-6
Multinode System (One
Local and Three Remote
Nodes), Block Diagram 1-6
2551-1, 2551-2, 2551-3, and
2551-4 Network Processor
Unit Front and Side
Views 1-9
2552~2 Network Processor
Unit 1-10
NPU Simplified Block
Diagram 1-14
Communications Software
Overview 1-19
2551-1, 2551-2, 2551-3, and
2551-4 NPU Major
Functional Areas and
Data Paths 2-2
2552-2 NPU Major
Functional Areas and
Data Paths 2-2
Microprocessor Functional
Block Diagram 2-7
Maintenance Panel/Com-
munications Console
Interface Block Diagram
Communications Coupler
Interfaces Block
Diagram
Maintenance Panel Controls
and Indicators 3-7
Typical Teletypewriter
Keyboard and Controls
Typical Cathode Ray Tube
752 Conversational
Display Keyboard and
Controls
1/0 TTY Interface
Controls
Cyclic Encoder Indicator
Loop Multiplexer
Controls and Indicators
Multiplex Loop Interface
Adapter Output Loop
Interface Indicators
Communications Line
Adapter Controls
and Indicators
Communications Coupler
CYBER Interface Controls
and Indicators
60472800 D
3-10
2K RAM Micromemory Page
Select Switches |
8K RAM Micromemory Page
Selelct Switches ;
Cassette Tape Controller
— Controls
Cassette Tape Drive
Controls
System Autostart Module
Controls and Indicators
Storage Reference
Instruction Format
Register Reference
Instruction Format
Interregister Instruction
Format
Skip Instruction Format
Shift Instruction Format
ADT Table for Multiple
AQ Devices
Microinstruction Formats
Microinstruction
Classification
Calculation of
Microprogram Sequence
Execution Time
Communications Coupler
PPU Function Codes
Communications Coupler
Status Format
Communications Coupler
Input Switch Status
Format
Communications Coupler-
Processor Set/Sample
Instruction Format
Cassette Tape Controller
Control Functions
Format
Cassette Tape Controller
Motion Controis
Cassette Tape Controller
Status Response Format
Card Reader Controller
Director Function
Format
Card Reader Controller
Director Status 1
Format |
Card Reader Controller
Director Status 2
Format
Card Reader Controller
Data Transfer Command
Format
ix
Peripheral Controller
Self-Test Command
Format a
Line Printer Controller
Director Function
Format
NPU Functional
Characteristics
Interrupt Bit
Assignments
Function Control Register
Bit and Digit Functions
Function Control Register
Display Code
Definitions
Function Control Register
Bit Descriptions
Maintenance Panel Controls
and Indicators
Control Character Code/
Functions
Switch Settings for I/O
TTY Interface
Loop Multiplexer Switch
and Indicators
Communications Line
Adapter Switches and
Indicators
Switch Settings for
Communications Coupler
Synchronizer
Switch Setting for 2K
RAM Micromemory Page
Select Switches
Switch Settings for 8K
RAM Micromemory Page
Select Switches
5-14
5-7
5-15
5-7
TABLES
3-12
1-16 3-13
2-6 4-1
3-2 4-2
4-3
3-3
4-4
3-5
3-15 -10
-11
3-17 4-12
4-13
4-14
3-18 4-15
4-16
4-17
3-19 4-18
4-19
4-20
3-20 4-21
4-22
3-21
Line Printer Controller
Director Status
Response Format |
Line Printer Controller
Data Transfer Command
Format
Control Functions Switch
System Autostart Module
Controls and Indicators
Storage Reference |
Instruction Addressing
Interregister Instruction
Truth Table
Type 2 Storage Addressing
Relationships
Macroinstruction
Execution Times
M Field Operations
Logical Operations
Arithmetic Operations
Shift Operations
Scale Operations
A Input Operations
A' Input Operations
B Codes
B' Codes
D Code Transfers
D' Code Transfers
D" Code Transfers
DD" Codes
T Addressing Modes
T' Addressing Modes
S Field Codes
C Code Actions
Microinstruction
Execution Times
60472800 D
SYSTEM DESCRIPTION ]
This section contains a description of the 2551-1, 2551-2, 2551-3, 2551-4,
and 2552-2 NPUs and the major features and components of the systems. The
NPU is a medium-size digital data communications system that serves as a
front-end to a host computer and interfaces with a variety of terminal
devices. The NPU can serve a CDC® 6000, CYBER 170, CYBER 70, or a lover 3000
series host computer. Figures 1-1 and 1-2 are block diagrams of typical
2551-1, 2551-2, 2551-3, 2551-4, and 2552-2 NPU configurations.
NOTE
The 2552-2 NPU is no longer available as a CDC product.
However, information is retained herein, for reference
only.
MAJOR FEATURES
The 2551-1 NPU configuration contains the following features:
e Single-bay cabinet
e Single processor
° 32K words MOS memory (expandable to 128 words)
e Interfaces up to 32 comunications lines
e Expandable to 2551-2 configuration that provides interface with 32
additional communications lines
e Forms a front-end to a single CDC host computer when connected by
appropriate coupler
The 2551-2 configuration contains the following features:
e Single-bay cabinet
e Single processor
e 32K words MOS memory (expandable to 128 words)
e Interfaces up to 64 communications lines
eo Expandable to 128 lines with addition of a loop multiplexer expansion
cabinet that contains two loop multiplexer expansion chassis and
communications line adapters
e Forms a front-end to a single CDC host computer when connected by
appropriate coupler.
60472800 D - | 1-1
The 2551-3 NPU configuration contains the following features:
e Single-bay cabinet
e Single processor
e CYBER Coupler | |
e 64K words MOS memory (expandable to 128 words)
e Interfaces up to 32 communications lines
e Expandable to 2551-4 configuration that provides interface with 32
additional communications lines
e Forms a front-end to a single CDC host computer
The 2551-4 configuration contains the following features:
e Single-bay cabinet |
e Single processor
e CYBER Coupler
e 96K words MOS memory (expandable to 128 words)
e Interfaces up to 64 communications lines
e Expandable to 128 lines with addition of a loop multiplexer expansion
cabinet that contains two loop multiplexer expansion chassis and
communications line adapters
© Forms a front-end to a single CDC host computer
1-2 | -— 60472800 D
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60472800 D
The 2552-2 NPU configuration contains the following features:
e Double-bay cabinet
o Two processors
- Base processor contains 32K word MOS memory (expandable to 128K
words)
- Multiplex processor contains 16K words MOS memory (expandable but
usually not required)
e Interfaces up to 64 communications lines
e Expandable up to 128 lines with addition of two loop multiplexer
expansion chassis and communications line adapters
e Forms front-end to a single CDC host computer with one host coupler,
or two hosts with addition of a second host coupler
NETWORK COMMUNICATIONS SYSTEM CONCEPTS
The NPU operates as an integral part of a CDC network communications system
(NCS). This system provides for the vast majority of communications (message
handling) tasks to be handled at intermediate points between the message
source and destination. This is accomplished by NPUs, also called nodes,
which are designed to allow almost any combination of functions to be
attended by hardware common to all nodes.
The NPU acts as an intermediate communications handler or communications node
between a host computer and the user terminals. Figure 1-3 illustrates a
single node system. The NPU is limited to two host computers. The host
computer can have two or more NPU front-ends and can be extended by common
trunk lines linked to remote nodes, which act as message concentrators from
multiterminal interfaces to form a multinode system. See figure 1-4.
The network communications system concept allows open-ended linkage of the
host computer and front-end nodes and a variety of geographically distributed
remote NPUS. In the multinode system one host is designated to maintain
circuits that control the entire network communications process.
PHYSICAL DESCRIPTION
The following is a brief physical description of the major equipments in each
— NPU configuration. For a detailed physical description, refer to the
appropriate equipment maintenance manual. See preface. |
60472800 D О 1-5 |
TERMINALS
NPU
i
HOST (FRONT END) Р
| $
COMPUTER
i
Figure 1-3. Single Node System, Block Diagram
REMOTE
TERMINALS CONCENTRATORS TERMINALS
- Da.
NPU р
т S
|
H NPU Р
р | (FRONT END)
- т 0
HOST NPU р
COMPUTER p S ar
>
a
7 | (FRONT END) L
| .
| | | Р T
a NPU р
e .
. 5 >
e .
Figure 1-4. Multinode System (One Local and Three Remote Nodes) ,
Block Diagram
60472800 D
2551-1 NPU EQUIPMENT
The 2551-1 NPU (figure 1-5) consists of NPU cabinet assembly DW117-A,
processor AAl35-A, and 32K MOS Memory AT241-B. The DW117-A contains the
basic cabinet, loop multiplexer and CLA card cage, multiplex loop interface
adapter (MLIA), cyclic encoder, power supply, and associated signal and power
cabling. Also, a maintenance panel, power distribution box, cable enclosure
assembly, and two air blower and filter assemblies are included with the
cabinet. The processor is contained in the communications processor card
cage, which also provides the card slots for the 32K MOS memory, cyclic
encoder, and MLIA cards. One loop multiplexer card and from 1 to 16 CLA
cards can be located in the loop multiplexer and CLA card cage.
2551-2 NPU EQUIPMENT
The 2551-2 NPU (figure 1-5) contains the same components as the 2551-1 and
includes an additional loop multiplexer and CLA card cage. The NPU can
service up to 64 CLAs in the system; thus, the 2551-2 NPU has double the line
capacity of the 2551-1. The B version cabinet contains the same electro-
magnetic interference shielding as the 2551-1.
2551-3 NPU EQUIPMENT
The 2551-3 NPU (figure 1-5) consists of NPU cabinet assembly DWIl7-A,
processor AAl35-B, 64K MOS memory AT241-B, and CYBER coupler DK106-C. The
DW117-A contains the basic cabinet, loop multiplexer and CLA card cage,
multiplex loop interface adapter (MLIA), cyclic encoder, power supply, and
associated signal and power cabling. Also, a maintenance panel, power
distribution box, cable enclosure assembly, and two air blower and filter
assemblies are included with the cabinet. The processor is contained in the
communications processor card cage, which also provides the card slots in the
64K MOS memory, cyclic encoder, MLIA, and CYBER coupler cards. One loop
multiplexer card and from 1 to 16 CLA cards can be located in the loop
multiplexer and CLA card cage.
2551-4 NPU EQUIPMENT
The 2551-4 NPU (figure 1-5) contains the same components as the 2551-3 and
includes an additional loop multiplexer and CLA card cage. The NPU can
service up to 64 CLAs in the system; thus, the 2551-4 NPU has double the line
capacity of the 2551-3. The cabinet has EMI shielding.
60472800 D a 1-7
Communications Processor
The processor card cage used in 2551-1, 2551-2, 2551-3, and 2551-4 NPUs
contains the following functional elements:
Microprocessor
Main memory
Maintenance panel interface
Cyclic encoder |
Input/output Teletype interface
Tape cassette controller (optional)
Multiplex loop interface adapter
CYBER Coupler (2551-3 and 2551-4 only)
`
#
2552-2 NPU EQUIPMENT
The 2552-2 NPU contains two processor card cages mounted in a double-bay
cabinet. See figures 1-2 and 1-6. The base processor card cage is located
in bay 0 and the multiplex processor card cage is in bay 1. Each bay
contains identical cabinet wiring, power supplies, air blower and filter
assemblies, and tape cassette drives. The 2552-2 NPU contains two loop
multiplexers and communications line adapter card cages located in bay 0.
Two optional card cages can be installed in bay 1 to expand communications
line capacity up to 128 lines. В
Base Processor
The base processor card cage contains those elements required to perform the
main data storage and processing functions. It includes the 32K-word
memory. The base processor components are as follows:
Microprocessor
Main memory |
Maintenance panel interface
Cyclic encoder
Input/output TTY interface
Tape cassette controller
1-8 60472800 D
TAPE CASSETTE
DRIVE
SYSTEM
AUTOSTART
MODULE
= Figure 1-5.
60472800 D
2551-1, 2551-2, 2551-3, and 2551-4 Network
Processor Unit Front and Side Views |
E E 3 L J
= MAINTENANCE m
MAINTENANCE PANEL e
COMMUNICATIONS
PROCESSOR COMMUNICATIONS
PROCESSOR
CARD CAGE CARD CAGE
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AND FILTER 4 AND FILTER
ASSEMBLY {ASSEMBLY
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MULTIPLEXER MULTIPLEXER CABINET
AND CLA AND CLA Al POWER
CARD CAGE (2551-2 AND Vel SUPPLY
(2551-2 AND 2551-4 ONLY) (MOUNTED ON
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M-214
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PER NPU
| 1-10
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PROCESSOR
CARD CAGE
| IR BLOWER
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Pt
——
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| CASSETTE
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100 |
MULTIPLEXER
EXPANSION
UNITS
(OPTIONAL)
р AIR BLOWER
e AND FILTER
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FRONT VIEW 329
Figure 1-6. 2552-2 Network Processor Unit (Sheet 1 of 2)
60472800 D
BAY 0
BAY 1
E. [A = |
— MAINTENANCE == НГ MAINTENANCE
PANEL e PANEL
TN mor,
BASE MULTIPLEX _
; PROCESSOR PROCESSOR
CARD CAGE CARD CAGE
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8 CONSOLE 5 —
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MODULE > AU POWER SUPPLY | | aT | POWER SUPPLY
(MOUNTED ON (MOUNTED ON
=== RIGHT SIDE OF =+——--1 RIGHT SIDE OF
PANEL WHEN + = PANEL WHEN
VIEWED FROM | VIEWED FROM
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LOOP | LOOP
MULTIPLEXER CABLE MULTIPLEXER
AND CLA ENCLOSURE | expansion |
CARD CAGE ASSEMBLY | UNIT |
(B VERSION ONLY) (OPTIONAL) |
4+ CABINET AC . LA CABINET AC
[| DISTRIBUTION | e «TT | DISTRIBUTION
AIR BLOWER BOX 5] AIR BLOWER | BOX
AND FILTER AND FILTER
ASSEMBLY ASSEMBLY |
ZA oO Ya A
SIDE VIEW M-216
Figure 1-6. 2552-2 Network Processor Unit (Sheet 2 of 2)
60472800 D ° ВЕ 1-11 |
Multiplex Processor
The multiplex processor card cage contains the elements required to perform
the primary command processing functions and interfaces with the input and
output loops. This processor has only a l6K-word memory and includes the
multiplex loop interface adapter circuit cards. The multiplex processor
components are as follows: |
Microprocessor
Main memory
Maintenance panel interface
Cyclic encoder |
Input/output TTY interface
Tape cassette controller
Multiplex loop interface adapter
Cross-Control and Console Switch
The multiplex processor contains a cross-control module to generate
interrupts and a console switch, which allows the NPU operator to select
either the base or > MUltiplex processor.
COMMUNICATIONS CONSOLE
A communications console is required to operate the NPU and may be either a
teletype (TTY) or cathode-ray tube (CRT) conversational terminal. The
console is not supplied with the standard NPU but is selected according to
the user application. Among the CDC products, the user may select a 722-10,
752 Display Terminal, or a 1711- -4, -5 (KSR TTY), or a 1713-4, -5 (AST TTY)
terminal as the communications console. | o |
COMMUNICATIONS COUPLER
The communications couplers used in conjunction with the 2551-1, 2551-2,
2551-3, 2551-4, and 2552-2 NPU configurations can be one or two of the
following types: |
e CYBER communications coupler - to interface with CYBER series 70/170
or 6000 series host computers. |
e 6671/6676 emulation coupler - to interface with CYBER SERIES 70/170 or
6000 series host computers, permitting the NPU to emulate a 6671 or
6676 Data Set Controller. |
e 3000L coupler - to interface with 3000L series host computers
MULTIPLEX SUBSYSTEM
The multiplex subsystem consists of the communications line adapters, the
loop multiplexer, and the multiplex loop interface adapter.
1-12 | | 60472800 D
Communications Line Adapters
Each communications line adapter circuit card contains two complete,
independent circuits. The communications line adapter is installed in the
loop multiplexer and communications line adapter card cage. The card cage
accommodates up to 16 communications line adapter cards which can service a
maximum of 32 communications lines.
Loop Multiplexer
The loop multiplexer is located in the loop multiplexer and communications
line adapter card cage. Each loop multiplexer can accommodate 32
communications line adapters (16 communications line adapter cards) and can
be series-connected to a maximum of eight loop multiplexers per loop for up
to 254 communications line adapters. |
Multiplex Loop Interface Adapter
The multiplex loop interface adapter consists of three circuit cards located
in the communications processor card cage.
MAINTENANCE PANEL
A maintenance panel is located above the processor in each bay. See figures
“1-5 and 1-6. Controls and indicators on the panel can be used by the
operator to monitor the status of the system. |
CASSETTE TAPE DRIVE (OPTIONAL)
A cassette tape drive is mounted on the door of each cabinet bay. See
figures 1-5 and 1-6. The drive operates at a speed of 7.5 inches (190 mm)
per second and recording density is 800 bits per inch (31.5 bits per mm).
Rewind speed is approximately 50 inches (1270 mm) per second. The drive uses
Phillips style cassettes.
SYSTEM AUTOSTART MODULE
The system autostart module is an assembly attached to the bottom of the
cassette tape drive. See figures 1-5 and 1-6. |
POWER SUPPLIES
The NPU contains a power supply which provides -5 V dc, +5 V dc, -12 V dc and
+12 V dc outputs. In the 2551-1, 2551-2, 2551-3, and 2551-4 NPUs the power
supply is mounted internally on the right rear cabinet wall. See figure
1-5. In the 2552-2 NPU a power supply is mounted on the right rear cabinet
wall of each bay. See figure 1-6. | |
CABLING
Cabling for the NPU consists of signal cables and power cables. Refer to the
2550 series site preparation manual (see preface) for information on carling.
60472800 D | 1-13
AIR BLOWERS AND FILTER ASSEMBLIES
Two air blowers and filter assemblies are provided with the basic NPU, and
additional units are provided to accommodate extra processor and o
communications line extension units in the 2552-2 NPU. Refer to the 2550
series site preparation manual (see preface) for information on blower and
filter assemblies. = a | |
EXPANSION SYSTEMS
The NPU can be expanded for greater use by addition of optional standard
products and upgrade kits, such as host couplers and communications line
expansion units. | | |
ELECTROMAGNETIC INTERFERENCE PROTECTION
Electromagnetic compatibility measures are included in the NPU design.
However, the NPU should not be located in the area of influence by strong,
electromagnetic interferences (EMI) such as radar, X-ray equipment, radio
signals, and electrical equipment. EMI protection is provided in the NPU
cabinets (B version) by special shielding on the top and sides of the
cabinets. A cable enclosure assembly is included to ensure the CYBER cable
shields are grounded to the cabinet. Additional provisions for grounding
communications line. adapter cable shields consists of copper pressure strips
that contact the cable shields at the bottom entrance to the cabinets.
FUNCTIONAL DESCRIPTION
The major functional elements of the NPU are the processor and memory, the
coupler, and the multiplex subsystem. See figure 1-7. |
NETWORK PROCESSOR UNIT MULTIPLEX SUBSYSTEM
y
> MEMORY
4
Y
| 1-14
1
MULTIPLEX
LOOP
INTERFACE
EMPTY LOOP TRAINS
INPUT
LOOP
LOOP
DATA
DATA OR COMMANDS
MULTI-
PLEXERS
COMMUNICATIONS
LINE ADAPTERS
{CLAS}
Figure 1-7. NPU Simplified Block Diagram
г - - ==" - ADAPTER | r- -
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| HOST | COUPLER |le— PROCESSOR Lee Ni | ! TERMINALS |
{
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M-217
60472800 D
PROCESSOR
The processor, the primary element, contains firmware (microinstructions) and
‚software (macroinstructions) to control the coupler and multiplex Subsystem.
Specific parameters of the NPU are listed in table 1-1.
NOTE
Macroinstructions are compatible with the CDC 1700
instruction repertoire and are stored in the processor
main memory. Microinstructions control operation of the
processor and are stored in the processor micromemory.
The processor has a direct memory access channel to the host computer for
both input and output and for input only from the multiplex subsystem. The
internal data channel is controlled mostly by firmware microinstructions and
provides a high throughput of 10K characters per second between the multiplex
subsystem and the processor. This forms the main access path to and from the
processor and the multiplex subsystem.
COUPLER
The processor is linked to the host computer through the coupler which
provides data paths and synchronizing clocks between the computers. The
coupler provides the means for direct memory-to-memory transfers between the
host and the base processor at a 1-MHz character rate. It is controlled by
both host and NPU software commands. The coupler also enables the host to
start, clear, and stop the processor. In addition to single-word transfers,
the coupler provides block data transfers in either direction (e.g., downline
load, upline dump) plus the ability to store and retrieve data via the
standard buffer format. The coupler selected must be compatible with the
host computer.
MULTIPLEX SUBSYSTEM
The multiplex subsystem transfers digital information on input and output
loops between the processor and the terminals. The input and output loops
are two high-speed serial data transmission links. The multiplex feature
allows transmission of messages from many communications lines over one |
circuit by sampling data (up to 8 bits per byte) on each line and assembling
the data in a data train (loop cells). |
Data transferred to and from the loops via the multiplex loop interface
adapter are checked for accuracy by use of a cyclic redundancy checksum
generated by the cyclic encoder. The cyclic redundancy checksum characters
are used in error code generation and verification of both incoming and
outgoing data to the terminals.
The multiplex loop inter face adapter receives commands from the processor and
accepts or provides parallel data to a circulating buffer in the memory. The
input loop to the multiplex loop interface adapter carries input data and |
status as well as output data demand signals from the communications line
adapters to the memory. The output loop carries output data and supervision
commands to the communications line adapters.
60472800 D 1-15 |
TABLE 1-1. NPU FUNCTIONAL CHARACTERISTICS
Main Memory
Capacity: 2551-1 - 32K words (32 768) АТ241-В
(standard)
2551-2 - 32K words (32 768) AT241-B
2551-3 - (2) 32K words (32 768) AT241-B
2551-4 - (3) 32K words (32 768) AT241-B
2552-2 - 48K words (49 152) AT241-B and AT275-B
Maximum capacity can be extended to 131 072 (128K) words for all
configurations by the addition of CDC 2554-32 (AT241-B) 32K MOS memory.
expansion modules. If a 2554-16 (AT275-B) module is fitted, as in the
2552-2 configuration, it must be replaced by a 2554-32 (AT241-B) module.
Word length: 16 bits (plus a parity bit and protect bit)
Read-Access Time: 550 nanoseconds
Memory Addressing Modes: 8
Memory Word and Region Protection
“Memory Parity Protection
Direct Memory Access (4 users)
External CPU Access
Automatic Interfaced Refresh
Micromemory (2K RAM)
Capacity: 3K (3072) words (2K (2048) words read/write; 1K (1024) words
read only emulator) | |
Word Length: 32 bits
Read-Access Time: 168 nanoseconds
Micromemory (8K RAM)
Capacity: 8K (8192) words (7K (7168) words read/write:
1K (1024 words read-only emulator)
Word Length: 32 bits
Read-Access Time: 168 nanoseconds
e 1-16 | | 60472800 D
TABLE 1-1. NPU FUNCTIONAL CHARACTERISTICS (Contd)
Interrupts
Macrointerrupts: 16 (corresponds to CDC 1700 interrupts)
Microinterrupts: 16 (internal)
Registers: 256 words
Files: File 1, 256 words; File 2, 32 words
The loop multiplexer accepts input data in parallel from the communications
line adapters and serializes the data. The loop multiplexer also assembles
loop cells from the output loop and presents the data in parallel form to the
communications line adapters.
The communications line adapters provide the interface between the loop
multiplexer and the terminals with or without a modem. On input from the
terminals, the communications line adapters are serial-to-parallel
converters, assembling serial data at the signal rate of the terminal, and
transferring the data to the loop multiplexer in 8-bit bytes. On output, the
communications line adapters are parallel-to-serial converters, receiving the
data characters in bytes of 8 bits from the loop multiplexer and outputting
them serially at the signal rate of the terminal.
OPERATING PROGRAMS AND DIAGNOSTICS
NPU operating programs and diagnostic test programs are loaded from cassette
tapes. The cassette tape controller serves as the access path for all data
transfer between the tape drive and the processor. The cassette tape drive
can be used as a standard peripheral or as a deadstart device.
When the NPU is program loaded and placed on-line, the NPU operation is
initiated and controlled by the host. NPU operation is monitored by the host
and by internal checks within the NPU. Processor operation can be
interrupted at any time of error detection within the multiplex subsystem or
on command from the host. |
The system autostart module monitors the program status. If a program error
is detected, a system master clear is issued, and the program tape is
automatically reloaded. Then the system restarts and runs until another
error is detected and the reload cycle automatically repeats. If no error is
detected, the autostart reload operation remains inhibited.
The operator can access the NPU via the console (TTY or CRT) or by the
maintenance panel to perform all common computer control panel functions.
The panel interface card in the processor provides the interface between the
operator panels and the processor main bus and internal processor control
‘signals. Operations performed at the maintenance panel are local and those
performed at the console are remote.
60472800 D 1-17 |
The 2552-2 NPU with dual processors provides better response time and greatly
increased message handling capability to accommodate any user requirements.
See figure 1-2. In the dual processor configuration, the processors share
the NPU functions which allows different operations to be performed
simultaneously. The base processor performs host signal interface
operations, main data storage, and processing functions. The multiplex
processor performs the primary command functions to control the multiplex
subsystem operations. | |
MAINTENANCE
Maintenance and troubleshooting procedures for the NPU consist of a series of
diagnostic test procedures which are performed on-line and off-line. On-line
diagnostics are performed to determine whether the fault is with the vendor
equipment, such as communications drives, modems, and input power, or with
CDC equipment. |
The objective of the off-line diagnostics is to allow fault isolation for all
components. Fault detection is performed automatically by the diagnostic
test program. Fault isolation is performed by the operator observing the
results of the tests and determining, with the aid of charts, which circuit
card is at fault. |
COMMUNICATIONS SOFTWARE
The communications software is divided into three major groups as follows:
e Host Processor Network: Access Software
e 255X Network Processor Unit: Communications Control Software
e 255X Support Software
The following paragraphs briefly describe the various functions and
relationships of the software groups. See figure 1-8.
HOST SOFTWARE
The host operating system software controls the operations of a network
operating system. The network access software (also resident in the host)
serves as the interface between the host operating system software and the
communications control software resident in the NPU. The host applications
programs process messages passed to them and also pass messages to the
network to be distributed to terminals.
pias 60472800 D
COMMUNICATIONS CONTROL SOFTWARE
The communications control software consists of base system software, network
communications software,
follows:
and interface programs. Available programs are as
e Communications Control Program (CCP), NOS Version, used on CYBER 6000
and 70/170 computers.
e Communications Control INTERCOM (CCI), NOS/BE Version, used on CYBER
70/170 computer.
e Communications Control Master (CCM),
For detailed information on the communications control software,
applicable software reference manual.
Base System Software
used on 3000L computers.
refer to the
The base system software, which includes the multiplex subsystem, comprises
those elements of the communications control software that are required for
all system applications.
provide:
e NPU resource management
© Memory space management
HOST
COMMUNICATIONS
CONTROL SOFTWARE
e BASE SYSTEM SOFTWARE
e NETWORK COMMUNICATIONS
SOFTWARE
e INTERFACE PROGRAMS
“AVAILABLE ON CYBER 70/170 AND 6000 SYSTEMS ONLY.
Figure 1-8.
NPU
HOST
APPLICATIONS
PROGRAMS
HOST
OPERATING
SYSTEM
NETWORK
ACCESS
SOFTWARE
“SUPPORT SOFTWARE
CYBER CROSS SYSTEM
e 2550 SERIES PASCAL
COMPILER
e 2550 SERIÉS MACRO
ASSEMBLER
eo 2550 SERIES MICRO
ASSEMBLER
eo LIBRARY MAINTENANCE
PROGRAM
eo LINK EDITOR {LINKAGE
PHASE)
e LINK EDITOR (EDIT PHASE)
Communications Software Overview
e Control of the local NPU console
M-218
The base system software contains subroutines that
e Facilities to add line-dependent or terminal dependent logic at
various software levels.
o Multiplex subsystem elements operating with NPU hardware to establish
data and control paths for information exchange between the
communications lines and appropriate protocol handlers (terminal
interface program) within the NPU.
60472800 D
1-19 |
Network Communications Software
The network communications software accomplishes the following:
Network routing and service message processing to establish line and
terminal configuration.
Reports alarm conditions and error and traffic statistics.
Provides common support modules for terminal interface programs.
Interface Programs
The interface programs provide the logical interaction necessary to transmit
information to and from the NPU.
Host Interface Program (HIP) accomplishes block data transfers with
the host computer, monitors the host for failure and recovery, and
reports host status to the NPU.
Terminal Interface Programs (TIPs) provide the logic to control the
line and terminal protocol and to ensure orderly transmission (in
either direction) between the NPU and the connected terminal. These
programs transform data between terminal protocols and block protocols.
Link Interface Program (LIP) accomplishes data transfers between a
local and a remote NPU. A special protocol (CDCCP) is used for these
transfers. The LIPs are responsible for transforming data between
CDCCP and block protocols at both ends of the trunk.
SUPPORT SOFTWARE
The CCP support software (CYBER CROSS System) includes a PASCAL compiler, two
assemblers, and system generation programs for the development and maintenance
of CCP software. The CYBER CROSS System executes only on the CYBER 70/170
series computer systems and executes under control of NOS as an application
system.
Refer to applicable documents for information on support software on
the CYBER CROSS System.
| 1-20
60472800 D
FUNCTIONAL DESCRIPTION 2
This section contains a functional description of ‚the NPU subsystems and
components.
NPU MAIN DATA PATHS
The NPU receives input data from the modems and terminals, via the
communications line adapters and loop multiplexer, and transforms the input
data to a format compatible with the internal processing of the NPU. See
figures 2-1 and 2-2. The multiplex loop interface adapter controls the data
flow from the loop multiplexer and supplies data to the memory buffers under
firmware and internal interrupt control. The cyclic encoder generates a
cyclic redundancy checksum to verify accuracy of the data. The processor
removes all protocol and language-dependent characters of the modified input
data and provides storage and access to the data under firmware control. The
communications coupler interfaces the host and serves as a transmittal device
by moving NPU data in buffer format to the host memory. Conversely, the
coupler transports data from the host to the NPU and stores it in the
internal format used by the NPU processor. Data flow through the NPU from
the communications line adapters in the direction of the host is referred to
as inbound traffic. Data flow from the host through the NPU to the
communications line adapters is outbound traffic.
The tape cassette is used for autoloading NPU microprograms and diagnostic
test programs. The communications console allows operator remote control
over the display of the NPU processing data and commands. The console
normally is the primary NPU control, but may be used for maintenance or
troubleshooting of the NPU. During normal operation the NPU operates
unattended.
The maintenance panel gives the operator, programmer or maintenance personnel
direct control over the display of NPU processing and commands from the NPU.
The maintenance panel is used primarily for troubleshooting the NPU system or
examining elements of the operating program.
The dual processor NPU functions the same as the single processor NPU except
for expanded equipment and capabilities. In general, the main difference is
that the single processor functions are divided between two processors for
increased performance. In the following paragraphs the single processor
system and the dual processor system are described separately.
BASIC EMULATION CONCEPTS
The 1700 series of computers, including the 1704 described in appendix A,
consists of special-purpose hardware designed to perform the tasks indicated
by the repertoire of instructions. The 255X system contains a totally
different processor which responds to a series of instructions at the micro
level. Microcode is a basic and flexible form of control, exercising and
sequencing the flow between the various hardware elements and the operating
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Figure 2-1. 2551-1, 2551-2, 2551-3, and 2551-4 NPU Major Functional
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7 PLEXER
TAPE TAPE
CASSETTE COMMUNICATIONS CASSETTE
DRIVE DRIVE
M-220
Figure 2-2.
2552-2 NPU Major Functional Areas and Data Paths
60472800 D
modes of these same elements. Instructions used by the microprocessor are
stored as 32-bit words in the read/write and/or read-only portions of
micromemory. Real-time operations are accomplished by executing microcode
stored in the read/write portion of micromemory. These real-time operations
are concerned primarily with time-critical tasks, such as character traffic
on the communications lines,
Other, nonreal-time operations are written in 1700-style code stored in the
processor main memory. These are executed through emulation. By this means,
instructions are fetched from main memory one at a time, the various bit
structures in an instruction are analyzed for content, converted into one or
more microinstructions capable of performing the operation requested, and
executed. The operation then continues in this manner, producing the same
results as would be accomplished by the code executing in a 1700 series
machine. To permit this emulation, a firmware instruction repertoire is
included, stored in read/write memory. This emulation operation becomes
practical, even though several microinstructions are required for each
microinstruction (1700), because the microprocessor is significantly faster
and simpler. Since the repertoire of instructions to be emulated is
determined simply by the contents of a read-only memory, addition of a series
of instruction set enhancements becomes practical.
"INTERRUPT SYSTEM
While emulating the 1700 computer, the NPU microprocessor firmware (con-
trolware) program actually accesses, under microprogram control, all 32 of
the interrupts. As a byproduct of this processing, the 16 external
interrupts are made available to the macroinstruction while the 16 internal
interrupts are available only to the microinstruction, either within the
emulation controlware package or the special communications firmware. It is
more accurate to define the interrupts as macro- and microinterrupts rather
than external and internal interrupts, respectively.
MACROINTERRUPTS
Macrointerrupts are associated with external I/O devices and perform tradi-
tional tasks such as flagging end-of-operation status and fault conditions.
Microinterrupts, however, perform the important internal tasks of establish-
ing priorities and queuing up tasks and in general providing communication
and signaling between the various firmware/controlware routines. At the
microinstruction level, there is no executive or monitor or scheduler: these
functions must be performed by the microinterrupt priority and processing
system.
MICROINTERRUPTS
In general, the microinterrupt system responds to three groups of inter-
rupts: emulator interrupts, special firmware interrupts, and high-priority
data such as multiplex loop interface adapter microinterrupts of which two
are available at the microinterrupt level. Processing is typically split
into low- and high-priority tasks so that time-critical tasks are handled
immediately with subsequent processing set up for deferred processing in
response to a lower priority microinterrupt.
60472800 C | 2-3
Status/Mode and Interrupt Bits
The 1700 computers use interrupt registers in which pulse-tvpe interrupts are
stored until processed or cleared. Because of the emulation nature of
interrupt handling, the NPU processor uses a different approach. The
macrointerrupt and microinterrupt registers operate on a direct current
rather than pulse basis. An external device must hold the interrupt line
active until the interrupt has been serviced. The interrupt registers are
used to prevent the interrupt status from changing while they are being
interrogated. As such, the interrupt registers are clocked as a part of the
reading process. The signals are stored in the status mode register. The
bits of this register can be wired so that they can be set via external means
and cleared under program control.
Microprocessing is organized so that certain response time standards are
established for macrointerrupt response time. This is necessary since
activating a macrointerrupt does not interrupt the processor but merely sets
a bit in an interrupt register which can then be read and acted upon by the
microprogramming. Only through the action of the firmware/controlware is the
effect of the macrointerrupt felt. Because of this, two service standards
are provided:
e Emulation controlware examines the state of the interrupt line through
the mask during the read-next-instruction phase of each emulated
macroinstruction. When an active interrupt is found (and the
interrupt system enabled), normal macroprogram execution is delayed
and macrointerrupt instruction routines are executed.
e Special firmware routines are organized so that every 20 microseconds
(or less) the interrupt system is interrogated and, if an interrupt is
found, processing is delayed.
Users can expect an interrupt latency time of no more than 20 microseconds
(for the highest priority interrupt). This accommodates 56-kilobit
communications lines.
Besides storing events, status/mode bits also serve another special function
of driving special control lines for external I/O operation. Thus I/O
timing, such as strobing and handshaking, is driven under firmware/controlware
control rather than by dedicated hardware.
Automatic Data Transfer Mode
Devices capable of automatic data transfer mode operations require both
macrointerrupts and microinterrupts. Such devices include the tape cassette
and the optional card reader and line printer. Each time a character is
available and required during automatic data transfer operations, the
microinterrupt line is activated. (For circuit simplicity the macrointerrupt
line can also be raised, but the microinterrupt will be seen first by the
controlware and it is therefore the one upon which action will be taken.)
Thus, character transfer is handled at the microlevel.
Multiplex Loop Interface Adapter Interrupts
Owing to their time-critical nature, two multiplex loop interface adapter
interrupts are available as microinterrupts. However, these microinterrupts
2-4 | 60472800 C
are not available to macroprograms such as MSMP17/ODS diagnostics. Thus, to
provide for diagnosability, these two interrupts are parallel-wired as both
macrointerrupts and microinterrupts. The third multiplex loop interface
adapter is of routine priority and is available as a macrointerrupt only.
| Real-Time-Clock Interrupts
Every 3.3 milliseconds a real-time-clock microinterrupt occurs. Via program
control, this interrupt is counted down n times (n is a programmable limit).
Only when n microinterrupts have occurred is a macrointerrupt generated.
Thus, real-time-clock microinterrupts occur every 3.3 milliseconds and
real-time-clock macrointerrupts occur every 3.3 divided by n milliseconds.
Interrupt Holding Registers
The interrupt holding registers are designated as Il and I2. Register Il
provides internal microinterrupts; register I2 provides external
macrointerrupts. Each register contains 16 bits, and the bits are numbered
from left to right as follows:
Register Bit Numbers
Il 1100 to I115
I2 1200 to I215
The priority levels of the interrupt bits are in numerical order. Bit Il00
has the highest priority in register Il; bit I115 has the lowest priority.
Similarly, bit 1200 has the highest priority in register I2, and bit 1215 has
the lowest. The bit assignments for registers Il and I2 are listed in table
2-1.
NPU COMPONENTS FUNCTIONAL DESCRIPTION
SINGLE PROCESSOR
The single processor provides buffer storage for input and output data,
storage and execution of various firmware and software programs, and provides
the hardware interfaces for both the host computer and the multiplexing
subsystem. For a detailed functional description, refer to the Basic
Microprogrammable Processor Hardware Maintenance Manual (see preface).
The functional elements of the single processor are as follows:
Microprocessor
Panel/Console Interface
I/0 Subsystem
Cyclic Encoder
Main Memory
The main data paths for the single processor configuration are shown in
figure 2-1.
60472800 C 2-5
TABLE 2-1, INTERRUPT BIT ASSIGNMENTS
Register
Bit Function
1100 Multiplex Loop Interface Adapter
1101 | Communications Console (TTY or CRT)
1102 Multiplex Loop Interface Adapter
1103 (unassigned) |
1104 2571/2570 Line Printer Controller
1105 (unassigned)
1106 (unassigned)
1107 Tape Cassette Controller
1108 Real-Time Clock
1109 | (unassigned)
I110 (unassigned)
I111 | 2571/2572 Card Reader Controller
1112 1700 Emulator
1113 1700 Emulator
I114 1700 Emulator
T115 1700 Emulator
1200 Power Fail/Memory Parity
1201 Communications Console
1202 Multiplex Loop Interface Adapter
1203 Multiplex Subsystem Priority 3 (source is SM205)
1204 2571/2570 Line Printer Controller
1205 CYBER Coupler 2 (2558-1)
1206 CYBER Coupler .
1207 Tape Cassette Controller
1208 Real-Time Clock |
1209 1732/608-609 Mag Tape Controller (QSE)
1210 1740-1742 Line Printer Controller (QSE)
1211 2571/2572 Card Reader Controller
1212 Multiplex Loop Interface Adapter
1213 Multiplex Loop Interface Adapter
1214 (unassigned)
1215 Macro Breakpoint
Microprocessor
The microprocessor, the controlling element within the processor, is a
small-scale, stored-program, parallel-mode digital computer. See figure
2-3. The microprocessor utilizes firmware (microinstructions) stored in a
read-only memory (ROM) emulator to control the processing elements which
permits execution of the main program (macroinstructions) residing in main
memory. It also uses controlware (microinstructions) stored in a read-write
memory (micromemory) to control the multiplexing subsystem and communications
coupler. A direct memory access channel accepts both input and output data
traffic from the host computer plus input traffic from the multiplex
subsystem. An internal data channel serves as the main access path for the
multiplexing subsystem and the various peripherals. The internal data
channel handles data traffic unbuffered in both directions and operates under
microinstruction emulator control.
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60472800 C
The processor contains two separate read/write memory units which are
identified as main memory and micromemory. Micromemory, a part of the
microprocessor, has smaller capacity (typically 2K x 32), but faster access
and cycle times. Each micromemory location contains a 64-bit double-word.
The micromemory is a random access, semiconductor memory that contains an
alterable random access memory nonviolatable and nonalterable read-only
memory.
Main memory stores the macroinstruction program (and data); the emulator ROM
and/or the micromemory stores the microinstruction program. Macroinstructions
are read from main memory sequentially by a portion of the microprogram. The
macroinstruction is then decoded into a series of microoperations by a
combination hardware/controlware/firmware technique. The hardware portion of
the macroinstruction decode is called a transform; the controlware/firmware
portion is called an emulator (in the case of standard 1700-type instruc-
tions). The 1700 emulator consists of a series of fixed microinstructions
contained in the read-only memory (ROM). The transform/emulator process
causes the microprogram to form program branches, sets parameters, and
performs arithmetic and logical operations. |
A transformed/emulated enhanced 1700 language macroinstruction is performed
as if it were one or more standard stored microinstruction (s). Numerous
microinstructions may be required to execute one macroinstruction. Macro-
instructions can be decoded either with or without the use of a transform
feature; however, the use of transforms significantly reduces the number of
microinstructions required and increases overall performance.
Arithmetic operations are performed by the arithmetic and logical unit shown
in the left center portion of figure 2-3. The two inputs (A and B) are
connected to a variety of input sources (e.g., I, P, A, F, X, and OQ
registers, Files 1 and 2, bit generator, N/K register, transform, tristate
bus) via selectors S1 and S82, respectively. Arithmetic and logical unit
functions include addition, subtraction, shifting left or right (arithmetic
or logical) plus logical functions such as AND or NOT. Output of the
arithmetic and logical unit (as is, shifted right one bit, shifted left one
bit, or shifted left eight bits, depending on selector S3) then appears as
inputs to the designated general purpose registers (P, A, F, X, 0). Files 1
and 2 are addressed by registers K and N, respectively.
Control is exercised through microinstructions from the micromemory.
Addressing is controlled by a 4-bit page address, 8-bit memory address, and a
l-bit, upper/lower (T-bit) selector from the current microinstruction.
Operating modes are established by setting/clearing bits in the status mode
register. Bits in the status mode register are also used to control timing
of the internal data channel operations. Of the 32 machine interrupts, 16
are designated macro- (external) interrupts and are available to the
operating system program resident in main memory. The remaining interrupts
are designated micro- (internal) interrupts and are available to the
microprogram (firmware and/or controlware) for control of hardware elements
and for intercommunication between firmware and controlware. Interrupts are
selected via priority logic, read through an interrupt mask register set
under program control.
ARITHMETIC AND LOGICAL UNIT
The arithmetic and logical unit contains the A, F, I, P, Q, and S registers
and also provides S1, S2,and ALU look-ahead functions. The arithmetic and
2-8 | 60472800 C
logical unit includes File 1, consisting of 16 bits in each of 256 locations,
and File 2, which has 16 bits in each of 32 locations.
The arithmetic and logical unit provides the basic capabilities for
arithmetic and logical operations within the microprocessor. The unit
combines two input words: the A input (provided by S1) and the B input
(provided by S2). These two inputs are combined according to the function
code specified in the microinstruction; the result is delivered
simultaneously to the output of the arithmetic and logical unit for use by
any of the following:
A specified destination register
Status mode register
Mask register
Memory bus |
Maintenance panel
NOTE
All registers cannot provide inputs to both sides of the
arithmetic and logical unit, nor receive outputs from the
arithmetic and logical unit; see figure 2-3.
It is also possible for the microprocessor to ignore the output of the
arithmetic and logical unit during a given operation. The results of
arithmetic and logical unit operations, i.e., sign, zero, and magnitude, are
available to the test-bit logic for instruction sequencing.
Arithmetic operations can be performed using either one's or two's complement.
arithmetic; the desired mode is selected via the microprogram, which controls
the states of the applicable bits in the status mode register. The |
microprocessor operates in one's complement mode, but is converted to two's
complement by the emulation firmware. This creates a special situation for
processor access to main memory location of hexadecimal FFFF,
STATUS MODE INTERRUPT
The status mode interrupt function consists of two status mode registers, two
interrupt holding registers, two mask registers, two priority encoders, plus
associated selectors and other hardware elements. The two pairs of each
results from separate elements for the processing of macro and micro-
interrupts. Status mode registers contain 16 bits each. These bits are
divided into operating mode, event occurrence, and timing and control
functions. | |
Interrupt holding registers Il and I2 provide internal microinterrupts and
external macrointerrupts, respectively. Mask registers contain 16 bits
each. These bits correspond to the interrupt lines with the same number (100
thru 115, 200 thru 215). The function of the two priority encoders is to
look at interrupt lines (through the two mask registers) and produce a number
equal to the highest priority interrupt currently active. This interrupt is
then serviced by the processor. Microinterrupt processing takes priority
over macrointerrupt processing.
Real-Time Clock - A real-time clock, part of the I/0 subsystem, is designed
to appear as a 1700 peripheral to the macrolevel software. A microlevel
interrupt is generated 300 times per second (3.3 ms). Under program control,
a macrolevel interrupt can be obtained at the same rate as the microlevel
60472800 C | 2-9
‘interrupt. Alternatively, a count value can be programmed to reduce the
macrointerrupt rate by the count value. Two functions are available to the
macrolevel program: Enable Limit Interrupt and Disable Limit Interrupt. Two
status bits are also available to the macrolevel program: Limit Interrupt
and Lost Count.
The limit interrupt being received by a macrolevel program is dependent on
the appropriate mask register bit being set and the macrointerrupt enabled as
with all other 1700 peripherals.
Microlevel code is capable of receiving a data interrupt from the real-time
clock every 3-1/3 milliseconds (derived from a crystal oscillator). This
interrupt is enabled anytime that the corresponding mask bit is set. Refer
to information on real-time clock presented earlier in this section.
Parity - Each main memory word consists of 19 bits consisting of: 16 data
word bits, 1 data word parity bit, 1 protect bit, and 1 protect parity bit.
The memory parity error function is used to indicate that either a word or
protect parity error has occurred. A word parity error indicates that one of
the memory word bits is wrong or the word parity bit is wrong. Word parity
error has no effect on memory operation other than setting the parity error
line; it may, however, place the validity of the memory word(s) in question.
A protect parity error indicates that either the protect bit or the protect
parity bit is wrong. It is only operative when the protect system is enabled
by a switch on the maintenance panel.
TRANSFORM
The transform feature provides the microprogram with the capability of
selecting any of several pattern of bits from the data transmission paths of
the microprocessor. By this means, bit patterns from the enhanced micro-
program are rearranged and regrouped to resemble more closely the instruction
formats actually executed by the microprocessor. These bit patterns are used
to form micromemory addresses which sequence the microprogram. The bit
patterns are also used to set the contents of the K and N register, and the
upper 16 bits of the microinterrupt register. |
The 1700 transform provides the following functions: Selectors 5, 7, and 8;
IXT and IXT*, Transform, Encode; and Transform Micromemory. This function
contains memory protect violation logic, decimal correction logic, and a
delta field generator for the lower 8 bits of each data word.
Panel/Console Interface
All communications between the microprocessor and the maintenance panel are
routed through the panel interface. See figure 2-4. The communications
console serves as the operator's primary point of interface with the system.
Either a teletypewriter (TTY) or cathode ray tube (CRT) conversational
display (with optional hard copy printer) can be used as the communications
console, provided that the selected device has two-way, simultaneous, serial
(full-duplex), ASCII, odd-parity characteristics. The communications console
CRT interface is RS232-compatible; the TTY interface is a 20-milliampere |
current loop.
2-10 | 60472800 C
The communications console functions in either of two modes: panel or I/O.
A LOCAL/REMOTE switch on the maintenance panel designates whether the panel
or console is selected.
In the panel (local) mode, all communication between the console and the
microprocessor is routed only through the I/O subsystem, and the console
operates as a standard peripheral device. As such, it is under the program
control of the macroprogram (operational).
In the I/0 (remote) mode, the console essentially functions as a maintenance
panel; in this case, input from the console is routed through the I/0 TTY
interface to the panel interface, and then to the microprocessor. Output
from the microprocessor is routed via the panel interface, through the 1/0
TTY interface to the console. |
The maintenance panel LOCAL switch position only can be used to develop
microprocessor instructions, and it can direct execution of these
instructions by the microprocessor. Instructions are transferred directly to
the microinstruction registers. The panel provides a number of capabilities
such as register display, macro- or microbreakpoint.
1/O Subsystem
The I/0 subsystem includes a TTY interface and the I/0 control for both CDC
A/Q-type and NCR MO5-type operations of the internal data channel. Either a
ТТУ or CRT display can be attached provided that it functions as an
asynchronous current-mode or RS232-compatible device. A device having
similar functional characters but operating at TTL voltage levels, such as
the tape cassette (deadstart portion), can also be connected. Four ASCII
character rates up to 9600 bits per second can be accommodated.
In addition to the status mode bits that generate timing, operations of the
internal data channel are controlled by two registers. The D register
contains the data to be written on the internal data channel. The Y
register, loaded through the D register, contains address information.
Transfers can be either in or out, in A/Q or MO5 format, under program
control.
Cyclic Encoder -
The cyclic encoder is a special algorithm hardware unit with the primary
function of computing cyclic redundancy checksum and/or longitudinal
redundancy checksum characters. Operating under microinstruction control,
the encoder can use any of 16 preprogrammed polynomial of sixteenth degree or
less as a generator to compute a checksum on any message character of from 1
to 8 bits in length. |
OST “ - | PANEL INTERFACE | , MOE TENANCE
CONTROL SIGNALS ;
PANEL
MICROPROCESSOR 1/0 MODE y MODE SIGNALS
e 1/0 TTY < COMMUNICATIONS
> INTERFACE Ч CONSOLE
M-221
Figure 2-4. Maintenance Panel/Communications Console Interface
Block Diagram
60472800 C | 2-11
Cyclic redundancy checksum/longitudinal redundancy checksum polynomials are
stored in read-only memory on the cyclic encoder. The cyclic encoder
operates in a serial mode, computing a partial checksum for each message
character it receives, one bit at a time.
After a checksum is computed for either an inbound or outbound message
character, the results of the computation are accessible by the program until
another message character is issued to the cyclic encoder. After this time a
new checksum is available and the previous one is either destroyed (inbound)
or stored (outbound) in the cyclic encoder but is no longer accessible by the
program. Thus blocks of outbound data have the checksum precomputed on the
entire block prior to output; input data characters accumulate partial
checksums as the characters arrive, saving these partial checksums until the
enter block is received and the final checksum becomes available.
Information is transferred to the cyclic encoder from the output of selector
S1 in the microprocessor; and data is transferred out of the cyclic encoder
via the input bus to selector Sl. Transfer in both directions occurs under
microinstruction (firmware) control. The cyclic encoder occupies the areas
normally reserved for double precision arithmetic operation control and thus
uses some double precision operations for its control.
The cyclic encoder computes a checksum on an 8-bit message character in less
than 760 nanoseconds following execution of a load X* microinstruction.
Computation time decreases by 61 nanoseconds per bit for message characters
less than 8 bits.
Information is transferred to the cyclic encoder from selector Sl and stored
in one of two registers designated A* or X*. Both registers are loadable
only and cannot be used as utility registers because their outputs are not
available from the card.
Main Memory
The single processor NPU has a 32K-word (2551-1 and 2551-2), 64K-word
(2551-3), 96K-word (2551-4), main memory. The main memory modules comprise a
one-bank system; that is, the modules are interconnected to preclude | |
simultaneous read operations from two or more locations in main memory.
However, there are two ports for main memory, which provide independent data
and control paths to memory. These ports are identified as input/output
(I/0) and direct memory access. The I/O port serves as the normal access
path for the processor to main memory. The direct memory access port permits
concurrent operation of the memory and processor.
Within main memory, user requests are coordinated, processed, and controlled
by the memory management system. Six user requests can be accommodated:
processor (lowest priority), direct memory access (4), and refresh (highest
priority). The direct memory access is further subdivided by use of a
4-position scanner, thus enabling a total of six sources (including refresh)
to access the memory.
Each of the 64 row addresses must be accessed once every two milliseconds
(minimum) to maintain the data. These accesses are automatically inserted
approximately once every 30 microseconds. Refresh thus constitutes less than
two percent of the available memory cycle. |
2-12 60472800 D
Memory can be accessed by the processor in either full-cycle or split-cycle
mode. Selection of the mode to be used is determined by whether or not the
protect system is needed.
DUAL PROCESSOR
Two processors are employed in the dual processor NPU, each performing half
of the processing functions, thereby providing a significant performance
increase. The base processor functions the same as the processor in the
single processor NPU except that the multiplex loop interface function is
absent. The multiplex processor is also the same basic unit except that the
communications coupler function and protocol-dependent program functions are
absent. Data communications between the processors occurs via common memory
portions of the base processor main memory, accessible by either processor.
Main memory in the base processor is 32K words, expandable to 128K. The
multiplex processor requires only 16K of local memory, usually not expanded.
It performs the multiplex interface function. The major functional areas and
data paths for the two processors are shown in figure 2-2,
Operationally, the base processor interfaces with the host via the coupler
and the multiplex processor interfaces with the communications lines via the
multiplex subsystem. Control communication between the two processors is
achieved through two interface devices: a console switch and a processor
cross control module.
Console Switch
The console switch allows the system operator to communicate with either the
base or the multiplex processor with one console.
Processor Cross Control
The processor cross control interconnections provide the following functions:
e Cross-interrupt - permits a status mode bit generated by either a base
or multiplex processor to generate an interrupt in the other
processor, which in effect alerts the other processor of a common
operation or function to perform. The actual operation is determined
by reading the contents of a communications area in common memory.
o Remote start - consists of a status bit (pulse) generated by the level
transition of a base processor status mode bit. The status mode bit
going off generates a pulse that stops and clears the multiplex
processor. The status mode bit going on generates another pulse which
starts the multiplex processor. Generation of these pulses in effect
allows the multiplex processor to be controlled by the host computer
in the same manner as the base processor (via communications coupler
functions). _ | | |
e Coupled master clear - consists of a Master Clear command generated by
the base processor which clears both the base and multiplex
processors. The master clear function of the multiplex processor
operates conventionally in that a master clear is generated by
depressing the MASTER CLEAR switch on the multiplex processor
maintenance panel, by depressing the question mark (?) key on the
operator's console, or through a power-on master clear.
60472800 C | 2-13
MULTIPLEX SUBSYSTEM
The multiplex subsystem contains the hardware, firmware, and software
elements which provide the data and control paths for information flow
between communications lines and user program software in the processor. See
figures 2-1 and 2-2. Many of the line/protocol-dependent functions that were
performed by fixed hardware in previous systems are implemented in common
alterable firmware and software, allowing reduced development and recurring
hardware costs for each line and protocol that is added to the communications
system.
The purpose of the multiplex subsystem is to gather data from the various
terminal devices and deliver this data to the processor (multiplex processor
in the dual processor NPU), and to receive data from the processor for
distribution to the appropriate terminal devices. In performing this data
movement (e.g., from terminal to processor) all unique signal characteristics
not requiring knowledge of the meaning of the bits are stripped out. These
signal characteristics include: data rate, synchronous or asynchronous
transmission, parity or no parity, number of bits (5, 6, 7 or 8), and serial
or parallel form. All information arrives in memory in bit-parallel,
right-justified form. Control codes, error control, and other housekeeping
bits are removed.
Similarly, information from the processor is formatted and conditioned
sufficiently to permit transmission to any modem or local peripheral.
Differences that require knowing the meaning of the bit, such as protocol and
code type, are handled by software.
The heart of the multiplex subsystem comprises two high-speed digital data
circuits called multiplex loops, as shown in figure 2-1. The input loop
handles data enroute to the processor from the terminal devices. The output
loop handles traffic from the processor to the terminals. The loops also
resolve simultaneous input requests.
The multiplex subsystem is demand-driven. When action is required by a
terminal, a demand service request is generated and transmitted to the
processor via the input loop.
The primary functional elements of the mechanism are the communications line
adapters that accomplish character assembly/disassembly and terminal
interface; the input loop which transports data demands, data, and status
from the communications line adapters to the processor; the output loop which
transports data and control from the processor to the communications line
adapters; a multiplex loop interface adapter which controls the movement of
data demands, data, and supervision between the loops and the processor; and
the loop mulitplexers which provide access to the loops by the communications
line adapters.
‘Multiplex action on the input loop occurs when the multiplex loop interface
adapter issues a loop-end control signal. As the signal propagates around
the loop, each loop multiplexer in turn has an opportunity to put data and/or
supervision from the communications line adapters on the loop. Loop
multiplexers holding information from the communications line adapters |
monitor the loop for the loop end signal, place the information on the loop,
and replace the loop end signal. The multiplex loop interface adapter
transfers the information received on the input loop to buffer storage for
processing by the processor.
2-14 60472800 C
The multiplex loop interface adapter takes addressed information from buffer
storage under direction of the processor and transmits this information on
the output loop. The loop multiplexer receives the addressed information
blocks and presents the address to all communications line adapters. The
communications line adapter recognizes that its address has been selected and
allows the information to be transferred from the output loop to the
communications line adapter. |
Multiplex Loop Interface Adapter
The multiplex loop interface adapter provides the interface between the
processor and the multiplex loop.
The multiplex loop interface adapter performs limited editing and checking
functions on the input data and deposits the data directly into a large
circular buffer in main memory via the direct memory access channel.
The multiplex loop interface adapter receives output data demand signals from
the communications line adapters and forwards these to the processor as
high-priority interrupts. The multiplex loop interface adapter then receives
output data from the processor via the internal data channel and distributes
the data to the loop multiplexers. The multiplex loop interface adapter
provides first—-in, first-out buffering for input data, output data demand
signals, and output data.
Loop Multiplexer
The loop multiplexer is the interface between the communications line
adapters and the input and output loops. The loop multiplexer accepts data
in parallel from the preceding loop multiplexer or from the multiplex loop
interface adapter. When not synchronized to the data stream, the loop
multiplexer passes all information received to the next loop multiplexer or
to the multiplex loop interface adapter. The clock signal is reconstructed
to specification when passed sequentially to the next element in the system.
INPUT SECTION
The input section of the loop multiplexer receives contiguous loop cells from
the preceding loop multiplexer or from the multiplex loop interface adapter.
When not synchronized to the data stream, the loop multiplexer passes all
information received to the next loop multiplexer or to the multiplex loop
interface adapter. The clock signal is reconstructed to specification when
passed sequentially to the next element in the system. |
The loop multiplexer utilizes the unique combination of a loop end cell and a
subsequent empty cell to acquire synchronization. When synchronized, the
loop multiplexer accepts data from each communications line adapter that has
information for the system; the loop multiplexer then outputs this
information to the input loop, in a line frame. At each frame boundary, the
loop multiplexer examines the input loop for an empty cell. If the empty
cell is detected, the loop multiplexer places the next communications line
adapter frame on the loop. If an empty cell is not detected, the loop
multiplexer drops synchronization. |
All communications line adapters plug into a common bus and control-line
structure. Each communications line adapter has a unique address and may be
60472800 C | 2-15
inserted into any communications line adapter slot. Each communications line
adapter can inform the loop multiplexer, via one of 32 lines, that it has
information for the system. The loop multiplexer can inform each
communications line adapter, via one of 32 control lines, that it can place
information on the communications line adapter bus in response to strobe
signals. When a communications line adapter has been selected, the loop
multiplexer will accept information from that communications line adapter
until either an information-end signal from that communications line adapter
is received, or 16 cells have been processed. When one of the above occurs,
the loop multiplexer deselects that communications line adapter, and selects
another communications line adapter. When all communications line adapters
requesting access to the loop have been serviced, the loop multiplexer drops
synchronization.
OUTPUT SECTION
The output section of the loop multiplexer receives contiguous loop cells
from the preceding loop multiplexer or from the multiplex loop interface
adapter. The output section always passes all loop cells received to the
next loop multiplexer or to the multiplex loop interface adapter. The clock
signal is reconstructed to specification when passed sequentially to the next
element in the system. The loop multiplexer uses empty cells to synchronize
itself to the data stream. When synchronized, the loop multiplexer looks for
frame boundaries and passes loop cells within the frame to the communications
line adapters. The loop multiplexer checks the cyclic redundancy checksum
character received with each frame.
When the loop multiplexer has accepted the address of a frame, it presents
this address to all communications line adapters. The communications line
adapter with the corresponding address then connects itself to the output
bus. The selected communications line adapter accepts the information
directed to it until disconnected by the loop multiplexer. If a cyclic
redundancy checksum error is detected by the loop multiplexer, it is reported
to the communications line adapter prior to termination.
COMMUNICATIONS LINE ADAPTER
The function of the communications line adapter is to provide the interface
between the loop multiplexer and a terminal with or without a modem. On
input, the communications line adapter serves as a serial-to-parallel
converter assembling the serial data at the signaling rate of the terminal,
and transferring the data to the loop multiplexer in an 8-bit byte. On
output, the communications line adapter functions as a parallel-to-serial
converter receiving the data characters in bytes of 8 bits from the loop
multiplexer and outputting them serially at the signaling rate of the
terminal. | |
In order to minimize the number of communications line adapter types
required, the communications line adapter hardware is designed to accommodate
most circuit characteristics under software/ firmware control. Each circuit's
individual characteristics are handled, for the most part, by associated
software which detects the specifics and sets parameter registers within a
particular communications line adapter to handle them. Software-selected
elements include: circuit speed, code set, and mode of operation. For
synchronous circuits these elements also contain the synchronization
2-16 60472800 C
pattern(s), and for asynchronous circuits they contain different input and
output speeds, parity detect and generation, and number of stop bits per
character.
The only remaining circuit variables are whether the circuit is synchronous
or asynchronous, and if synchronous, the signal level standard to which the
circuit interfaces. The terms synchronous and asynchronous refer to the way
in which the data is transmitted: synchronously with a clock, or without
reference to a clock (but at a fixed rate and with synchronization elements
appended).
A number of types of communications line adapters, which have differing
functional and/or electrical interface characteristics, are available. Refer
to the Hardware Maintenance manuals for the functional descriptions of the
specific communications line adapter types selected. See preface.
TAPE CASSETTE
The tape cassette controller serves as the access path for all communications
between the tape drive and the processor. The controller provides input to,
and receives output from, the transport at a rate of 750 characters per
second (8-bit characters). This yields a data transfer rate of 6 kHz which
is compatible with the tape drive.
The cassette controller interfaces to the internal I/O, internal data channel
of the processor. The controller may be status- or interrupt-driven at the
macro level and data transfers may also take place in the auto-data transfer
mode at the micro level.
The cassette controller deadstart interface provides the means for the tape
cassette transport to begin reading data in response to an operator-initiated
command at the maintenance panel or the communications console. Only the
read function is performed in the deadstart mode of operation. The data is
ASCII, asynchronous, binary, serial-by-bit, at the 9600 baud rate.
Signal transfer between the controller and the tape drive is provided by a
cable which connects the backpanel directly behind the controller card to the
transport.
The tape cassette drive can be used as a program-load or data-capture
device. The tape drive is capable of both reading and writing on
Philips-type, magnetic tape, digital data cassettes. The tape drive contains
servomotors, servoamplifiers, read-write circuitry, read-after-write head,
and the necessary control circuits for processing data and controlling the
tape.
SYSTEM AUTOSTART MODULE
The system autostart module monitors the program status and reloads the
deadstart program tape any time the interval between the received programmed
reset pulses exceed 3 seconds. For further information refer to the system
autostart module manual (see preface).
60472800 C | | | 2-17
COMMUNICATIONS COUPLER
The primary purpose of the communications coupler is to provide a link
between the host computer and the processor. The coupler provides the means
for direct memory transfers between the host peripheral processing unit (PPU)
and the processor at a l-megahertz character rate. The coupler is controlled
by both host and processor software commands. The coupler also enables the
host to start, clear, and stop the processor.
As shown in figure 2-5, the communications coupler has three interfaces: the
host PPU data channel, the NPU internal data channel, and the NPU direct
memory access channel. Information can be transferred between any two
interfaces, and between any interface and various data and address registers
within the coupler.
Communications between processor and host is through two unidirectional,
sof tware-controlled, single-word register transfers. Although their
software-controlled nature makes them available for any purpose (the coupler
is basically a transparent device), standard usage is to send work requests,
status requests, etc., from the host via the orderword register. The host
fills this register; when full, the register interrupts the processor, which
then reads the register and takes action as directed by the resident
software. Information from the processor to the host uses the processor
status register (another free-form register); when full, the register sets a
bit in the coupler status word (which the host reads periodically). The host
then reads the processor status word.
HOST COMPUTER
PPU
DATA
CHANNEL
8BIT | 4
DATA | COAX
CHARAC- | CABLES
TERS Ÿ
COMMUNICATIONS
COUPLER host
INTERFACE
DMA “toc
INTERFACE INTERFACE
1 ;
DMA IDC
- BU
BUS | y BUS
COMMUNICATIONS PROCESSOR
M-222
Figure 2-5. Communications Coupler Interfaces Block Diagram
2-18 | | | 60472800 С
OPERATING INSTRUCTIONS 3
This section describes the use of the function control register in internal
communication, the control and indicator functions, and the start-up and
operating procedures,
FUNCTION CONTROL REGISTER
The function control register is the basic means of communication between the
microprocessor and the maintenance panel and communications console. It
replaces the traditional front panel switches with a series of software-
controlled switches and indicators capable of being set or read locally or
remotely.
The communications console and maintenance panel use the function control
register to provide the following basic functions:
Master clear
Halt memory operations
Start memory operations
Step mode
Run mode |
Display memory
Load memory
Display register
Load register
Stop, when condition met
The function control register stores and defines the functions that are to be
performed by the microprocessor. The contents of the function control
register can be displayed at the console or the maintenance panel in response
to an operator's command. The contents can then be changed by operator
commands from the console or maintenance panel. The maintenance panel
operation is local and the console is remote, but both provide the same level
of control.
The function control register is a 32-bit register which is divided into 8
groups of 4 bits each as shown in table 3-1. Bit 00 is the most significant
bit, and bit 31 is the least significant bit.
The machine status hexadecimal digits 6 and 7 (bits 24 thru 31) are set by
the processor and indicate machine status such as overflow, macro running,
micro running, main storage parity error, and protect fault. The machine
mode digits 2 thru 5 (bits 8 thru 23) of the function control register are
used to set such conditions as selective stop/on/off, and step/run mode. The
display digits 0 and 1 (bits 0 thru 7) determine which individual registers
of two groups of registers (identified in table 3-2) can be displayed or
modified.
60472800 C | 3-1
TABLE 3-1. FUNCTION CONTROL REGISTER BIT AND DIGIT FUNCTIONS
Bit Digit Digit
Number Bit Name Number Function
31 Over flow (LSB)
30 Protected Instruction 7
29 Protect Fault
28 Parity Error Machine
Status
27 Interrupt System Active |
26 ‘Auto Restart Enabled 6
25 Micro Running
: 24 Macro Running
23 Unde fined
22 Undefined 5
21 Enable Auto Display
20 Enable Console Echo
19 Enable Micromemory Write”
18 Multilevel Indirect Address Mode 4
17 Unde fined
16 Suppress Console Transmit Machine
Mode
15 у Macrobreakpoint
14 3
13 Breakpoint Interrupt
(Breakpoint Stop if Clear)
12 Micro Breakpoint, Step, Go, Stop
(Macro if Clear)
11 Step
10 Selective Stop 2
09 Selective Skip
08 Protect Switch
07 |
ое ( Display 1 (K Function) 1
04 | Display
03
02 Display 0 (L Function) 0
00 (MSB)
TA hard-wired function, not controllable by the function control
register.
Legend: LSB - Least significant bit
MSB - Most significant bit
60472800 C
TABLE 3-2. FUNCTION CONTROL REGISTER DISPLAY CODE DEFINITIONS
Code Display 1 (K Function) Display 0 (L Function)
0 0000 FCR — F2 (addressed by №)
1 0001 РТ. N (MSDs) T+
2 0010 I | К (LSDsS)t++
3 0011 X
4 0100 A | O
5 0101 MIR F | | о
6 0110 ВР/Р-МА F1 (addressed Бу К,
enabled by SM111)
7 0111 BP/P-MA (Display only) MEM |
8 1000 SM1
9 1001 M1 | RTJ
A 1010 SM2
B 1011 M2
C 1100 | MM
D 1101 A*
E 1110 X*
F 1111 Q*
t+ Used to address main memory; automatically incremented after each memory
reference a
TT Combined contents of these two registers are used to address
micromemory. K register is automatically incremented after each memory
reference. N register does not automatically increment.
NOTES
Bits 1416 and 1516 of the function control register (enable console
echo and enable auto display) are mutually exclusive; that is, the
operator may select one or the other, but not both simultaneously.
Unassigned display codes are undefined.
Selection of BP or P-MA causes both BP and P-MA to be displayed. BP
consists of the leftmost 16 bits and P-MA consists of the rightmost 16
bits. BP can be modified only if BP is selected; P-MA cannot be modified
in either case.
Selection of N or K causes both N and K to be displayed. N is the left 8
bits and K is the right 8 bits. However, when N is selected, only the N
register can be modified; when K is selected, only the K register can be
modified.
60472800 C
The machine status and machine mode bits are described in table 3-3. Note
that in the protected instruction (bit 30), a reply response is enabled for
all commands if the program protect line indicates the instruction is
protected. If the program protect line indicates that the instruction is
unprotected, then for each function and data transfer command, a reject is
generated; however, a status command is never rejected. A typical function
control register setting is 442008C0 (A/Q reference) or 712008C0 (main memory
reference). |
CONTROLS AND INDICATORS
Controls and indicators for monitoring and controlling the NPU functions are
used extensively throughout the NPU. Many are located on circuit cards and
some monitor operation of external devices such as the tape cassette drive.
Switches on the tape cassette drive monitor whether the lid is closed, which
side of cassette (A or B) is up, and the presence or absence of the write
enable plug for whichever track is positioned under the read/write head.
Main power circuit breakers on the cabinet are used during starting and
shutdown procedures in this section.
Multisection microswitches located on NPU circuit cards are preset at the
factory for normal operation. Replacement cards may require switch setting
changes. |
The maintenance panel and the communications console contain the majority of
the controls and indicators used to monitor and operate the NPU.
MAINTENANCE PANEL
The maintenance panel controls and indicators are shown in figure 3-1 and
described in tables 3-4 and 3-5.
COMMUNICATIONS CONSOLE
The communications console is the operator's primary point of interface with
the processor. Either a cathode ray tube (CRT) conversational display or a
teletypewriter (TTY) device is used as the console. Figure 3-2 presents the
controls and indicators (including keyboard) for a typical TTY, and figure
3-3 illustrates a typical CRT conversational display. For a complete
description of the controls and indicators for these units, refer to the
appropriate manual for the communications console selected for the system.
1/0 TTY INTERFACE
The I/O TTY interface, illustrated in figure 3-4, contains a 4-element switch
assembly. Each element is a 2-position switch. The switches are used to
select the desired baud rate as shown in table 3-6. They are set at the time
the NPU is installed and are not reset under operating conditions.
CYCLIC ENCODER
The cyclic encoder, illustrated in figure 3-5, contains a single, LED power
indicator which indicates the presence of +5 volts when lit. |
3-4 Ш 60472800 C
TABLE 3-3. FUNCTION CONTROL REGISTER BIT DESCRIPTIONS
Bit
Number
Bit Description
31
30
29
28
27
26
25
24
21
20
18
16
60472800 C
Overflow. Set when an overflow occurs during execution of an
arithmetic and logical unit.
Protected Instruction. Set when processor is executing a
protected instruction (protect bit is set).
Protect Fault. Set when attempt is made to access a protected
area in main memory from a nonprotected instruction (and
protect system is enabled).
Parity Error. Set when main memory interface logic detects a
parity error while reading data from main memory.
Interrupt System Active. Set when interrupt system is
available for use (regardless of contents of interrupt mask
register).
Auto-Restart Enabled. Set when automatic program restart is
desired after a power failure.
Micro Running. Set when emulator function (microprogram) is
operating in the microprocessor. When the emulator is halted,
bit is not set.
Macro Running. Set when a macroprogram is being executed in
microprocessor (bit 25 must also be set or macroprograms cannot
be executed).
Enable Auto Display. Set to allow viewing of a given register
(selected by digits 0 and 1) while the processor is running.
Auto display mode is used with the maintenance panel to verify
that certain registers are changing; it is not normally used
with the console.
Enable Console Echo. Set to allow viewing of data being
entered at communications console (as well as machine
responses); usually used with teletypewriter input to provide a
record of all messages; sometimes used with the CRT console and
almost never with the maintenance panel itself,
Multilevel Indirect Address Mode. Set when a maximum of 32K
words can be accessed in main memory and the most significant
bit denotes indirect addressing; when not set, 65K words can be
accessed. The 32K mode corresponds to CDC-1704 operation; the
65K mode corresponds to 1714, et al, operation and is the
commonly used mode.
Suppress Console Transmit. Set when operational mode
transmission from console to microprocessor is inhibited; when
set, maintenance mode transmission by the console is permitted.
TABLE 3-3. FUNCTION CONTROL REGISTER BIT DESCRIPTIONS (Contd)
Bit |
Number Bit Description
15, 14 Breakpoint. Used in combination to select three types of
breakpoint:
Bit 14 Bit 15
Breakpoint not selected
Instruction reference breakpoint
Store operand breakpoint
All references breakpoint
неее
HOMO
If bit 12 is set, these are all microbreakpoints or
macrobreakpoints. | |
13 Breakpoint Interrupt. When set and a breakpoint is reached,
program does not halt immediately, but halts upon reaching an
interrupt instruction.
12 Microbreakpoint, Step, Go, Stop. When set, the processor is
operating in the microbreakpoint, step, go, stop mode only;
when not set, processor is operating in macromode for these
functions.
11 Step. When set, program operates in a stepping mode; operator
triggers the execution of each instruction individually.
10 Selective Stop. When set, halt instructions cause instruction
execution to cease; when not set, halt instructions have no
effect on program execution.
9 Selective Skip. When set, program executions for skip switch
on are executed; when not set, program executions for skip
switch not on are executed.
8 Protect Switch. When set, it is possible to write into
| protected areas in main memory, if protect system is not
enabled, this switch has no effect. |
NOTE: | All of these actions occur because of controlware operation and
not because of any direct hardware control.
60472800 C | | 3-6
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TABLE 3-4. MAINTENANCE PANEL CONTROLS AND INDICATORS
Key No.
(Fig. 3-1) Panel Name Function
1 CASSETTE REWIND Actuates rewind mode of operation in
pushbutton switch drive.
2 CASSETTE READY Lights when tape cassette drive is
indicator light ready (cassette installed, door
closed, transport not rewinding, and
no cyclic redundancy checksum error).
A cassette must be ready to initiate
deadstart.
3 UPPER indicator Operates with the data display indica-
light tors. Lights when data display
represents contents of the upper bits
in a register. Primary use is display
of function control register. |
4 . Data Display Display contents of a selected regis-
indicator lights ter on panel; lights when bits 0 thru
(16) 15 (for 32-bit register) are being
| displayed; when not lit, bits 16 thru
31 are displayed. |
5 Data Entry push- Enter data in hexadecimal form.
button switches
(16)
6 Control Character Enter control characters H, I, J, K,
pushbut ton L, M, N, and the colon (:)
switches (8) | |
7. FAILURE PROC +5V Not used
indicator
8 FAILURE ALARM PNL Not used
indicator
9 SONIC ALARM TEST Not used
pushbutton switch |
10 SONIC ALARM Not used
ENABLE /DISABLE
toggle switch
11 REMOTE/LOCAL Selects either maintenance panel or
rocker switch
communications console as the point of
control for NPU. When set to LOCAL,
panel is enabled; when switch is set
to REMOTE, console is enabled. |
60472800 C
TABLE 3-4. MAINTENANCE PANEL CONTROLS AND INDICATORS (Contd)
Key No. |
(Fig. 3-1) Panel Name Function
12 CONTROL CODE Indicate last character entered via
13
14
15
16
17
.18
19
indicator light
(3 LEDS)
Function Control
Definition Table
decal
MASTER CLEAR
rocker switch
DEAD START ACTIVE
indicator light
DEAD START INI-
TIATE
pushbutton switch
REFRESH MC
pushbutton switch
— PROTECT SYSTEM
toggle switch
DM TIMER
indicator
the control character switches in the
control codes listed: a 1 denotes a
lighted LED. Once entered, a control
code remains set until replaced by
another controlor code or master clear.
Provides operator assistance infor-
mation of function control register
and control character.
Clears memory in processor and peri-
pheral controller. |
Indicates NPU ready to receive data
from a card reader or tape cassette
transport, and deadstart sequence in
process.
Actuates data reading by a card reader
or tape cassette transport; selection
of device determined by the ready
state of the peripherals. Only one
deadstart peripheral can be ready when
using this switch.
Not used
Normally in down position (system not
protected); in up position, designated
portions of memory are protected from
"overwrite during certain diagnostic
routines. |
Not used
60472800 C
TABLE 3-5. CONTROL CHARACTER CODE/FUNCTIONS
Character Display | Function
H | 000 When used alone (followed by a colon
(Master В terminator), halts program execution;
Cleared | | affects either macroprogram or microprogram
State) | execution, depending on setting of bit 12 of
function control register. When preceded by
a 2-digit number (followed by a colon
terminator), resets corresponding bit of
function control register.
I 001 When used alone (followed by a colon
| terminator), initiates program execution;
affects either macroprogram or microprogram
execution, depending on the setting of bit
12 of function control register. When
preceded by a 2-digit number (followed by a
colon terminator), sets corresponding bit of
function control register.
J | 010 When used alone (followed by a colon
terminator), changes state of UPPER
indicator, permitting upper and lower
portions of function control register, for
example, to be displayed. When preceded by
a 2-digit number (followed by a colon
terminator), causes 4 bits of function
control register referenced by first digit
(0 thru 5) to be replaced by value of second
digit.
K 011 When used alone (followed by a colon
terminator), displays contents of register
specified by Display 1 portion of function
control register. When preceded by a 4- or
8-hex digit number (followed by a colon
terminator), causes contents of register by
the function control register Display 1
character to be replaced by the specified
digits.
L 100 Operationally the same as K function except
| it is associated with Display 0.
3-10 60472800 C
TABLE 3-5. CONTROL CHARACTER CODE/FUNCTIONS (Contd)
Character Display Function
M 101 Not used.
N 110 | Not used.
ERROR 111 Can be used as indicator that a program
failed to load properly.
- Terminates all entries (when using console,
three terminating characters can be used:
colon, G, or @). The @ character also
switches control from panel mode to I/O mode.
NOTE
When main memory is displayed or entered, the register selected in
Display 1 is the main memory address. The Display 1 selection must be
the P register, which is incremented by 1 after the display. |
When micromemory is displayed or entered, K register is the least
significant 8 bits of the address, and N register provides for
remaining bits. K register is incremented by 1 after the display.
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3-14
TABLE 3-6. SWITCH SETTINGS FOR I/O TTY INTERFACE
Deadstart | Program Select 7?
1 | 2 3 4 Baud Rate
On ° Оп On On 110
Off Off On Off 300
Off On Off On 1200
Off Off Off Off 9600
t Input Device: Tape Cassette, 9600
TTI/O Console: TTY, 110; CRT, 110 to 9600
LOOP MULTIPLEXER
The loop multiplexer controls and indicators, located on the circuit card
handle, include a power switch and four LED indicators. See figure 3-6 and
table 3-7. An identification label holder allows each user to identify the
circuits connected to the communications line adapters by insertion of small
labels.
MULTIPLEX LOOP INTERFACE ADAPTER
All three of the circuit cards which comprise the multiplex loop interface
adapter contain LED indicators. The processor interface card and the input
loop interface card each contain a single LED indicator that indicates the
presence of +5 volts electrical power when lit. The output loop interface,
illustrated in figure 3-7, contains the following five LED indicators (the
‘numbered items below correspond to key numbers in figure 3-7):
1. Multiplex Loop Interface Adapter Running. When lit, this LED
indicates that the multiplex loop interface adapter is not reset.
2. Output On. When lit, this LED indicates the presence of data and
| clock signals on the output loop.
3. Input On. When lit, this LED indicates the presence of data and clock
signals on the input loop.
4. Input Busy. When lit, this LED indicates either the presence of loop
batches on the input loop or the absence of a valid restart loop end
following an error.
5. Power. When lit, this LED indicates the presence of +5 volts
electrical power.
COMMUNICATIONS LINE ADAPTER
Each synchronous and asynchronous communications line adapter contains four
LED indicators, two thumbwheel address switches, and an enable/disable toggle
switch. Two independent communications line adapters are mounted on one
circuit card; thus two sets of controls and indicators are mounted on the
card handle, as shown in figure 3-8.
60472800 C | 3-15
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Figure 3-6.
Loop Multiplexer Controls and Indicators
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п
Figure 3-7.
M-204
Multiplex Loop Interface Adapter Output
Loop Interface Indicators
ADDRESS LED
SWITCHES INDICATORS
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ENABLE/DISABLE ENABLE/DISABLE
SWITCH SWITCH
M-224
Figure 3-8. Communications Line Adapter Controls and Indicators
60472800 C
- M-208
TABLE 3-7. LOOP MULTIPLEXER SWITCH AND INDICATORS
Panel Marking Function
PWR ON/OFF Controls electrical power to the loop
toggle switch multiplexer. |
IN LOOP CLK When lit, indicates input loop clock signal
indicator light is receiving bit clocking from multiplex
loop interface adapter or from preceding
loop multiplexer.
IN LOOP DATA When lit, indicates input loop is receiving
indicator light data cells from multiplex loop interface
adapter or from preceding loop multiplexer.
OUT LOOP CLK When 1it, indicates output loop clock signal
indicator light is receiving bit clocking from multiplex loop
interface adapter or from preceding loop
multiplexer.
OUT LOOP DATA | When lit, indicates output loop is receiving
indicator loop data cells from multiplex loop interface
adapter or from preceding loop multiplexer.
NOTE
The synchronous data link control communications line
adapter is mounted one per circuit card. Therefore, only
one set of controls and indicators appear on the card
handle of this equipment.
Each address switch has 16 positions (hexadecimal); thus each pair of
switches (CLAl and CLA2) can be set to 256 different addresses. Each
communications line adapter in the NPU system must be set to a unique address
by means of the switches.
The names and functions of all communications line adapter (CLA) switches and
indicators are listed in table 3-8.
COMMUNICATIONS COUPLER
The CYBER interface (synchronizer) in the communications coupler, illustrated
in figure 3-9, contains a clock adjustment, a clock indicator, an on-line
switch, and a dual-inline package (DIP) switch.
Clock Adjustment
A potentiometer can be used to adjust the phase of the clock signal provided
by the host computer. This control is adjusted during NPU installation and
normally needs no readjustment.
60472800 C В 3-17
TABLE 3-8. COMMUNICATIONS LINE ADAPTER SWITCHES AND INDICATORS
Name
Function
Address switches
Modem indicator SD
Modem indicator RD
Modem indicator RTS
Modem indicator DCD
(synchronous CLA only)
CLA1/OFF toggle switch
Modem indicator DSR
(asynchronous CLA only)
Switch setting displayed in hexadecimal
code (00 to FF). Top switch is most signi-
ficant digit; bottom switch is least
significant digit.
Blinking, indicates CLA sending data to
modem
Blinking, indicates CLA receiving data from
modem
Lighted, indicates request-to-send signal
from CLA is active
Lighted, indicates data-carrier-detect
signal from modem is active
Enables or disables CLA ability to input to
the system
Lighted, indicates data-set-ready signal
from modem is active
i
|
=
CLOCK
и ADJUSTMENT
ТР
©
a po INDICATOR
cs |
DIP
SWITCH
\_ ON-LINE SWITCH
M33
Figure 3-9. Communications Coupler CYBER Interface Controls and Indicators
60472800
Clock Indicator
This LED indicator goes on to indicate that the on-line clock signal from the
host computer is available. The LED continues to indicate the availability
of the on-line clock, even if the switch is set to the off position. When
lit, this LED also indicates the presence of +5 volts electrical power.
On-Line Switch
This 2-position toggle switch is used to connect the NPU to the enabled host
data channel. When the switch is set to the up position, the NPU is
connected to the host channel. When the switch is in the down position, the
communication links with the host data channel are disabled. The switch is
in the on position except when off-line diagnostics are being run.
DIP Switch
This is an 8-element switch assembly, each element is a 2-position rocker
“switch. Switches 1, 2, and 3 are used to select an equipment code (address)
for the communications coupler; switches 4, 5, 6 and 7 are not used; and
switch 8 is used for parity. Table 3-9 lists the functions for these
switches. This switch assembly is set at the time the NPU is installed and
is not reset under normal conditions.
MICROMEMORY
The 2K RAM micromemory card (figure 3-10) contains a 4-element switch
assembly. Each element is a 2-position switch. The switch is used for
micromemory page selection as shown in table 3-10.
TABLE 3-9. SWITCH SETTINGS FOR COMMUNICATIONS COUPLER SYNCHRONIZER
Equipment
1 2 3 Code 8 Parity
On ~ Оп On 0
Off - On | On | 1 | | | |
a | Оп | Channel Parity Disabled
on Off | On 2 | В (6000, СУВЕЕ 70)
Off Off On 3
On On Off 4
Off On Off 5
| Off Channel Parity Enabled
On Off Off 6 (CYBER 170)
Off Off Off 7
The standard equipment code assignment is 7.
60472800 C В 3-19
> PAGE SELECT
SWITCH
ASSEMBL Y
M-203
Figure 3-10. 2K RAM Micromemory Page Select Switches
TABLE 3-10. SWITCH SETTINGS FOR 2K RAM MICROMEMORY PAGE SELECT SWITCHES
Switch Number N
| | Micromemory
(V1) 1 2 3 4 Pages
(V2) 4 3 2 1 | Selected
Top Bottom |
Off Off Off N/A | 0-3
Off On Off N/A 4-7
Оп Off Off N/A 8-11
On On Off N/A | 12-15
No other switch settings are used.
3-20 — | | 60472800 С
The two configurations of the micromemory are identified as Version 1 (V1)
and Version 2 (V2). For Version 1, the switches are numbered 1, 2, 3, 4 from
top to bottom. For Version 2, the switches are number 4, 3, 2, 1 from top to
bottom. (The terms top and bottom refer to the circuit card as normally
installed.) The switches are set at the time the NPU is installed and are
not reset under normal conditions.
The 8K RAM micromemory card (figure 3-11), contains two 4-element switch
assemblies. For normal operation, all of the switches should be in the OFF
position. In this mode all 8K of RAM can be accessed unconditionally. High
8K and low 8K can also be selected. See table 3-11. -
pel
$2
su
si
83
PAGE SELECT
SWITCH
ASSEMBLIES
— M-834
Figure 3-11. 8K RAM Micromemor y Page Select Switches
TABLE 3-11. SWITCH SETTINGS FOR 8K RAM MICROMEMORY PAGE SELECT SWITCHES
Switch
Si 52 Description
Off | X Unconditional 8K enable
„Оп Off Active high 8K enable
On On Active low 8K enable
60472800 C | 3-21
~~ CASSETTE TAPE CONTROLLER
The cassette tape controller (figure 3-12) contains an equipment switch
assembly and a control functions switch assembly.
Equipment Switch Assembly
This switch assembly consists of four segments; each segment is a 2-position
switch. The switches are used to set the equipment code (address) for the
cassette tape controller. The switches are set at the time the NPU is
installed and are not reset during normal operating conditions. Standard
equipment switch address is 716. |
=
N CONTROL
' FUNCTIONS
SWITCH
ASSEMBLY
!
—)
— |
En
EQUIPMENT
SWITCH
ASSEMBL Y
M-206
Figure 3-12. Cassette Tape Controller Controls
3-22 . | 60472800 C
Control Functions Switch Assembly
This switch assembly consists of four segments: segments 1, 2, 3, and 4.
Segments 2 and 4 are not used by the NPU. Each segment is a 2-position
switch. The control functions provided by the switches are listed in table
3-12. The switches are set at the time the NPU is installed and are not
reset during normal operating conditions.
AUTO-REWIND ENABLE SWITCH (Segment 1)
When this switch is on, the tape drive automatic-rewind feature is
operative. Thus, each time a cassette is inserted and the lid is closed, the
tape is automatically rewound to the beginning-of-tape hole. When this
switch is off, the automatic-rewind feature is not operative. However,
rewind function commands are always operative. |
In the inhibited position, the switch facilitates editing operations and
permits sequential loads of diagnostic overlays from more than one deadstart
device.
PROTECT SWITCH (Segment 3)
When this switch is in unprotected mode (off position), the controller
ignores the state of the program protect lines from the microprocessor and
accepts all I/0 instructions (function, status, and data transfer commands).
An unprotected controller never rejects a function, status, or data transfer
command. |
When the switch is in protected mode (on position), the controller monitors
the program protect line from the microprocessor. The controller's response
to the I/O instruction is then determined by the state of the program protect
line as follows: |
l. If the program protect line indicates that the I/O instruction is
unprotected, then for each function and data transfer command, the
controller generates a reject. However, a status command is never
rejected. | |
2. If the program protect line indicates that the I/O instruction is
protected, then for all commands (function, status, and data
transfers) a reply response is enabled by the protect condition. The
controller does not return a reply until all other conditions within
the controller indicate that it is permissible to do so.
TABLE 3-12. CONTROL FUNCTIONS SWITCH
Position ~~ Segment 1 | ~~ Segment 3
On - Auto-Rewind Enabled Protected Mode
Off Auto-Rewind Inhibited Unprotected Mode
60472800 C 3-23
CASSETTE TAPE DRIVE
The cassette tape drive contains the following controls: a lid interlock
switch, a side A/B switch, and a write enable switch. See figure 3-13.
Lid Interlock Switch
This is an interlock switch that is depressed by the drive lid when closed.
When the lid is open, all drive functions are disabled. Opening the lid is
the primary means for making the cassette Not Ready (refer to deadstart
operation).
Side A/B Switch
This switch senses a notch in the tape cassette to determine which side (A or
B) is up. Position of this switch is reported as a status bit. |
LIO
INTERLOCK
SWITCH
CARTRIDGE
M-251
Figure 3-13. Cassette Tape Drive Controls
3-24 | 60472800 C
Write Enable Switch
This switch senses the presence or absence of the write enable plug (at the
cassette) for whichever track is positioned under the read/write head.
CONSOLE SWITCHBOX
‚The console switchbox, shown in figure 1-2, allows the operator to select
between the base and multiplex processors in the 2552-2 NPU.
SYSTEM AUTOSTART MODULE
The controls and indicators for the system autostart module are shown in
figure 3-14. Table 3-13 describes the function of the controls and
indicators.
START-UP PROCEDURE
The NPU power is normally on all the time, except for motor-driven
peripherals which are turned on only as needed. The following procedure is
to be used when the NPU has been completely shut off (for example, following
an emergency shutdown):
l. Set main ac power circuit breakers at the rear of each cabinet bay to
the on position.
2. Set PWR switch on each loop multiplexer to ON.
3. Observe illumination of all LED indicators on communications line
adapters, loop multiplexers, and the maintenance panel.
SYSTEM AUTOSTART MODULE OPERATION
To intialize the NPU with the SAM-C tape, proceed as follows:
l. Set autostart module switch to DISABLE.
2. Press MASTER CLEAR switch on maintenance panel.
3. Insert SAM-C cassette, close lid, and wait for tape rewind and load
point. |
4. When CASSETTE READY indicator on maintenance panel lights, press
DEADSTART switch. The tape then starts and the system loads. |
5. Set autostart module switch to ENABLE when MONITOR RESET PULSE
indicator starts flashing.
6. CASSETTE READY indicator on maintenance panel remains lit. Tape has
rewound and returned to load point.
60472800 C | 3-25
— R
MONITO =
RESET
PULSE
mMFWpO-0
©
тот
AUTOSTART HISTORY _
LOAD RETRY PROGRAM POWER
ACTIVE LIMIT ERROR INTERRUPT
Figure 3-14.
— TABLE 3-13.
M-210
System Autostart Module Controls and Indicators
SYSTEM AUTOSTART MODULE CONTROLS AND INDICATORS
Panel Name
Function
MONITOR RESET PULSE
indicator
AUTOSTART DISABLE/
ENABLE toggle switch
AUTOSTART ENABLE
indicator
AUTOSTART LOAD ACTIVE
indicator
AUTOSTART RETRY LIMIT
indicator
HISTORY PROGRAM ERROR
indicator |
HISTORY POWER INT
indicator
When lit, indicates programmed reset pulses
are being received.
In DISABLE position, disables autostart mod-
ule; in ENABLE position, starts 3-second and
5-minute timers.
When lit, indicates autostart module is
enabled, tape is in cassette, programmed
reset pulses are being received and cas-
sette is at load point.
Indicates program is being loaded.
Indicates autoload module reloaded the pro-
gram repeatedly, until retry limit expired
and each reload was unsuccessful (no pro-
grammed pulses occurred).
Indicates interval between reset pulses has
exceeded 3 seconds.
Indicates system power was interrupted.
60472800 C
7.
9.
10.
11.
Autostart module indicators are as follows:
ENABLED — On
LOAD ACTIVE - Off
RETRY LIMIT - Off
RESET PULSES - Flashing
PROGRAM ERROR —- Off
POWER INT - Off
NOTE
PROGRAM ERROR, RETRY LIMIT and POWER INT indicators are
latched on. Set DISABLE/ENABLE switch to off then on
momentarily to reset these indicators. When the autostart
module is enabled and reload sequence begins, REWIND and
INITIATE LOAD switches on maintenance panel are inhibited.
To check recovery from a power failure, set cabinet ac power circuit
breaker to OFF momentarily. After recovery, set autostart module
switch to off momentarily to reset POWER INT indicator.
To change the tape at any time, even during a load sequence, open the
tape cassette lid.
Remove and install cassette tape and close lid.
Set autostart module switch to DISABLE momentarily to reset PROGRAM
ERROR indicator. |
OPERATING PROCEDURES
MASTER CLEAR
The NPU can be master-cleared by any of the following actions:
By depressing the question mark (?) key on the communications console.
By depressing the ESCAPE key on a teletypewriter, or if no ESCAPE key,
by depressing SHIFT, CONTROL, and K simultaneously.
By depressing MASTER CLEAR switch on the maintenance panel.
By receipt of an external master clear signal from the host computer.
By a power-on master clear.
DISPLAY CONTENTS
To display the contents of the function control register at any time, enter
on input device: |
60472800 C | 3-27
J77:
end of message symbol
dummy number (status portion of function control register, which
cannot be affected)
control function
Whenever a printout occurs, the initial symbol is the last control function
entered. When the same control function is required, it need not be
reentered. The stored value is changed by master clear (to 000) or error (to
CLEAR BIT
To clear a single bit position in the function control register, enter:
H14: |
Lend of message symbol
bit number (hexadecimal) to be cleared
control function
The updated function control register is displayed at the console.
SET BIT
To set a single bit position in the function control register, enter:
114:
Lena of message symbol
—bit number (hexadecimal) to be set
control function a
The updated function control register is displayed at the console.
CHANGE CONTENTS (DIGIT MODE)
To change the contents of a function control register in digit (016 thru 5)
mode, enter: SR
Jl4:
| а of message symbol
value (0-F) hexadecimal
specifies hexadecimal digit number
control £unction
3-28 | 60472800 C
The above entry specifies a function control register change is to be made in
the digit mode and updates function control register hexadecimal digit 1 to a
value of 416 (01005). To determine the meaning of the value, refer to |
table 3-2, where digit 1 is display 1, and a count code of 4 = A register.
The response to the console is the updated function control register value
(always displayed in 8 hexadecimal digits).
CHANGE CONTENTS (BIT MODE)
The operator cannot change the contents of function control register digits
616 and 7, as they are readouts of machine status. The digits 016 thru 5
can all be changed with the same command from the console, as follows:
a. ESCAPE key (or SHIFT/CTRL/K) (Panel Mode)
b. ? (Master Clear)
c. ESCAPE key (PANEL MODE)
d. To change digits 016 thru 5 together, enter digits as follows:
K710008xx:
end of message symbol
anything
enable console echo
default
¡gear
default
P register
main memory
control function
Default is the prior value of the function control register that is not to be
changed (in this case, zeros). The response to the console is the updated
function control register. | |
— TOGGLE UPPER INDICATOR
To toggle the UPPER indicator on the maintenance panel (alternately display
the upper and lower 16 bits of the function control register), enter the
following:
J:
Lena of message symbol
control function
60472800 C a | — 3-29
DISPLAY REGISTER CONTENTS (DISPLAY 0)
To display the contents of any of the registers defined in display 0 (see
table 3-2), use the following procedure (Assume the operator wants to display
the contents of K register at the console. ): |
1. Define in the function control register the element to be displayed.
The console input is:
702:
end of message symbol
specifies K register
pecifies display 0
control function
The above input specifies function control register change is in digit
mode and defines K register in display 0. The response to the console
is updated function control register.
2. Type a command from the console to dispaly 0:
L:
Lena of message symbol
control function
The response to the console is the present value of K register.
DISPLAY REGISTER CONTENTS (DISPLAY 1)
The operator can display the contents of any of the registers defined in
display 1 (see table 3-2) by using the following procedure (Assume the
operator wants to display the contents of P register at the console.):
1. Define in the function control register the element to be displayed.
The console input is: |
Jll:
end of message symbol
-specifies P register
specifies display 1
control function
The above input specifies function control register change is in the
digit mode and defines P register in display 1. The response to the
console is the updated function control register. | ВЕ
3-30 | 60472800 С
2. Type a command from the console to display 1:
K:
Lena of message symbol
control function
The response to the console is the present value of P register.
LOAD A REGISTER (DISPLAY 0)
The operator can load a value into any register defined in display 0 (see
table 3-2) by using the following procedure (Assume the operator wants to
load 14РЕ); into N register.): a | |
1. Define the element to be loaded.
Joi:
|! ena of message symbol
—specified N register
specifies display 0
—— — control function
2. Enter the update value.
L14FE:
—end of message symbol
update value in hexadecimal
control function
3. Verify that the new value has been transferred into desired register.
L: |
Lena of message symbol
control function
LOAD A REGISTER (DISPLAY 1)
The operator can load a value into any register defined in display 1 (see
table 3-2 by using the following procedure (Assume the operator wants to load
14FE16 into the breakpoint register.):
1. Define the element to be loaded:
60472800 C | 3-31
J16: °
-end of message symbol
specifies breakpoint register
specifies display 1
control function
2. Enter the update value.
K14FE:
end of message symbol
-update value in hexadecimal
control £unction
3. Verify that new value has been transferred into desired register.
K:
end of message symbol
control function
TAPE CASSETTE AUTOLOAD
1. Master clear the NPU using any of the methods previously described.
2. Insert tape cassette in tape drive and close 1lid securely. Tape drive
is enabled and tape moves to beginning-of-tape position. |
3. Press ESCAPE key on communications console.
4. Press DEADSTART switch on maintenance panel. Tape loads and processor
| starts.
NOTE
When loading a program, observe the value displayed in the
three CONTROL CODE indicators (figure 3-1). When all
three indicators are lit simultaneously, an error is
indicated. Frequently the final value of the CONTROL CODE
indicators is the error condition (all on) if an error was
sensed anywhere in the load operation. This applies
regardless of the type of autoload device used.
HOST COMPUTER AUTOLOAD
The host computer autoload is a software function that provides a DOWNLINE
LOAD command to the NPU. In order for this command to be received, the ON
LINE/OFF LINE switch on the communications coupler CYBER interface must be
set to ON LINE.
3-32 | 60472800 C
START PROCESSOR
The NPU can be started from the console by entering the following command:
I:
| of message symbol
-control function
If bit 0Cyg (12109) of the function control register is 0, both
microprograms and macroprograms begin running. If this bit is 1, only
microprograms begin running.
STOP PROCESSOR
The NPU can be stopped from the console by entering the following command:
Hs
Lend of message symbol
control function
If function control register bit О0С16 (1210) is 0, a macro stop occurs.
If this bit is 1, a micro stop occurs. | |
Halt the processor when inserting patches to programs being executed. If not
halted, patches may not enter the program as expected.
PROCEDURE EXAMPLES
The following paragraphs contain typical procedural sequences used in
operating the NPU. |
Display Main Memory Location
The contents of a specific location within main memory can be interrogated
and displayed by entering the following:
1. ESCAPE (Panel Mode)
2. ? (Master Clear)
3. ESCAPE (Panel Mode)
4. “Load function control register to define P register and main memory
K710000800:
Verify function control register update.
5. Load P with desired memory location
Kxxxx: = (xxxx—æ-P)
60472800 C 3-33
Display memory location
L:
Response to console is memory contents pointed to by the P register;
the P register is incremented.
Consecutive memory locations can be displayed each time the following -
is entered at the console:
response
response, etc.
Write Into Main Memory
Specific locations within main memory can be loaded by entering the following:
l.
2.
3.
4,
ESCAPE
?
ESCAPE
K71000800:, set up function control register
KXXXX:, (xxxx-—#P)
Lyyyy:, (yyyy—sloc xxxx)
The P register has automatically been incremented following the : from
the console.
The next memory location (xxxx +1) can now be loaded with a new value
by Lyyyy:, etc., without having to update P.
Display P Register in Repeat Mode
The P register can be displayed in the repeat mode by entering the following:
ESCAPE (Panel Mode)
? (Master Clear)
ESCAPE (Panel Mode)
K71000400: (Select P register, repeat mode)
K: (Display P contents)
Response is P register contents, repeatedly. This command is usually
used with local (maintenance panel) operations rather than console
mode when a TTY is used as the console device. |
To display the P register locally (to determine, for example, if the program
is running), enter the following: — | ;
3-34
60472800 C
LOCAL/REMOTE switch to local
K1ll: (selects P register)
J54: (sets repeat mode, resets console echo)
Response is P register contents, repeatedly. To exit this mode, enter:
J58: (sets console echo, resets repeat mode)
Operation in Step Mode
The processor can be placed in the step mode, and programs can be
single steps (individual instructions) by entering the following:
1.
2.
3.
4 .
5,
6 -
7.
executed in
ESCAPE (Panel Mode)
? (Master Clear)
ESCAPE (Panel Mode)
K71100800: (load function control register)
K1000: (1000—P register)
K: (display P contents)
Repeat K: to execute individual instructions sequentially through the
program. a |
Load and Execute Macroprogram
A program can be loaded into main memory and executed by entering the
following: |
1. ESCAPE (Panel Mode)
2. ? (Master Clear)
3. ESCAPE (Panel Mode)
4. K71000800: (load function control register; select P register,
memory; console echo) | | -
5. K1000: : (0B00 Loc 1000)
6. 1.0800: (0800 Loc 1000)
7. LOBOO: (0800 Loc 1001)
8. 10800: (0800 Loc 1002)
9. 10800: (0800 Loc 1003)
10. L18FB Loc 1004)
60472800 C
(18FB
11. K1000: (1000 Pp)
12. I:, execute program starting at location 1000
EMERGENCY-OFF PROCEDURE
1. Set the main ac power circuit breakers at the rear of each bay of the
NPU to the off position. В
2. Turn off all peripherals.
CHECKS AND ADJUSTMENTS
Operational checks are limited to observing the LED indicators on the circuit
cards and the maintenance panel to ensure the presence of all required
signals as described in controls and indicators portions of this section.
SHUTDOWN PROCEDURE
The following procedure is to be used should the operator desire to
completely shut down the NPU.
1. Depress MASTER CLEAR switch on maintenance panel.
2. Set PWR switches on all loop multiplexers and communications line
adapters to the off position.
3. Set main ac power circuit breakers at the rear of each cabinet bay of
the NPU to the off position. |
3-36 | 60472800 С
COMMUNICATIONS PROCESSOR INSTRUCTIONS 4
This section contains the format and instruction descriptions for
macroinstructions and microinstructions for the communications processor.
The macrolevel instructions set is compatible with the CDC 1700 instruction
repertoire and are stored in the main memory. Microinstructions that control
operation of the processor are stored in the micromemory. Information on
macro and microinstruction timing is also included in this section.
MACROINSTRUCTION FORMATS AND INSTRUCTIONS
The macroinstruction format consists of 16-bit words numbered right to left
as 0 to 15 with the leftmost bit (15) as the most significant bit.
MACROINSTRUCTION WORD
Bits 125 | 0
| J
The basic macroinstruction formats and enhanced instruction formats are
described below. о
BASIC MACROINSTRUCTION FORMATS
1. Storage Reference Instructions
2. Register Reference Instructions
e Interregister Instructions
e Skip Instructions
e Shift Instructions
NOTE
The latter three type instructions are subgroups of the
Register Reference Instructions.
ENHANCED MACROINSTRUCTION FORMATS
1. Type 2 Storage Reference Instruction
2. Field Reference Instruction
3. Decrement and Repeat Instructions
4. Type 2 Interregister Instructions
5. Miscellaneous Instructions
Load Micromemor y
Load Registers
Store Registers
Set/Sample Output or Input
Sample Position/Status.
Define Microinterrupt
60472800 C | - | 4-1
e Clear Breakpoint Interrupt
e Generate Character Parity Even
e Generate Character Parity Odd
® Scale Accumulator
e Load Upper Unprotected Bounds
e Load Lower Unprotected Bounds
e Execute Microsequence
A
6. utodata Transfer Instructions
STORAGE REFERENCE INSTRUCTION FORMAT
The storage reference instruction format, shown in figure 4-1, contains three
fields: instruction, address mode, and delta. The instruction field
contains the operation code. The address mode field contains flags for
indexing, indirect addressing, and relative addressing. The delta field is a
signed 8-bit address modifier where the most significant bit is the sign bit,
except where noted.
The following definitions apply to the description of addressing
modes:
1. Instruction Address - The address of the instruction being executed;
contents of P register.
2. Indirect Address - A storage location that contains an address rather
than an operand.
3. Base Address - The operand address after all indirect addressing but
before modification by the index registers. The base address is the
effective address when no indexing is specified.
4. Effective Address - The final address of the operand. At
certain
times the effective address equals the operand for read-operand type
instructions. See table 4-1.
5. Indexing - The computer has two index registers. Index register 1 is
the Q register. Index register 2 is storage location 00FF;g (the I
register). The base address can be modified by either or
both of the
index registers. If index register 1 flag is set, the contents of the
15 12 11 10 9 8 7 0
| F r ind | q i |
Instruction | | Delta (A)
Index Register 2 Flag
(I Register)
Index Register 1 Flag
(Q Register)
Indirect Address Flag
Relative Address Flag
Figure 4-1. Storage Reference Instruction Format
Address
Mode
60472800 C
60472800 C
TABLE 4-1. STORAGE REFERENCE INSTRUCTION ADDRESSING
Address
Binary | Of Next
Mode b11-b8 Hex | Delta Effective Address Instruction
Absolute 0000 0 #0 A P+1
Constant = P+1 P+2
Absolute 0001 1 #0 A+ (00FF) P+1
Constant = (P+1)+(00FF) Ÿ P+2
Absolute 0010 2 #0 А + (0) P+1
Constant = (p+1)+ (0) T P+2
Absolute 0011 3 #0 А+ (О) + (00FF) P+1
Constant | = (P+1) + (00FF) T P+2
Indirect 0100 4 #0 (A) P+1
Storage TT = (P+1) P+2
Indirect 0101 5 #0 (A) + (0OFF) P+1
Storage TT | = (P+1) + (00FF) P+2
Indirect 0110 6 #0 (A) + (Q) P+1
Storage TT | = (P+1)+(0) —P+2
Indirect 0111 7 #0 (A) +(Q)+ (00FF) P+1
Storage tt = (P+1) + (0) + (00FF) P+2
Relative 1000 8 #0 P+A P+1
16-bit Relative = P+1+(P+1) P+2
Relative 1001 9 #0 P+A+(00FF) P+1
16-bit Relative = P+1+(P+1)+(00FF) P+2
Relative 1010 A #0 P+A+ (0) P+1
16-bit Relative = P+1+(P+1)+(0) P+2
Relative 1011 B | #0 P+A+ (0) + (00FF) P+1
16-bit Relative = P+1+(P+1)+(Q)+(00FF) P+2
Relative Indirect | 1100 с #0 (Р+А) P+1
l6-bit Relative = (P+1+ (P+1)) P+2
Indirect tT
Relative Indirect 1101 D #0 ~ (P+A) + (00FF) P+1
16-bit Relative = (P+1+ (P+1)) + (00FF) — P+2
Indirect TT |
TABLE 4-1. STORAGE REFERENCE INSTRUCTION ADDRESSING (Contd)
| Address
Binary | | of Next
Mode 1 bl11-b8 Hex | Delta Effective Address Instruction
Relative Indirect 1110 E #0 (P+A) + (0) | P+1
16-bit Relative = (F+1+(P+1))+(0) P+2
Indirect ТТ
Relative Indirect | 1111 F £0 (P+A) + (Q) + (00FF) Р+1
16-bit Relative =0 (P+1+(P+1))+(Q)+(00FF) P+2
Indirect Tt
TEffective address = operand for read-operand type instruction.
TT Multilevel only in 32K mode.
Note: The 255X NPU normally does not use 32K mode.
Q register are added to the base address to form the effective
address. If the index register 2 flag is set, the contents of storage
location 0O0FF are added to the base address to form the effective
address. If both index register flags are set, the contents of Q are
added to the base address; then the contents of 00FFj;g are added to
the result to form the effective address. Indexing occurs after
completion of indirect addressing.
The computer uses the 16-bit one's complement adder during indexing
operations. Consequently, the index register contents are treated as signed
‘quantities (bit 15 is the sign bit).
The storage reference instructions have eight different types of addressing
modes: |
1. Absolute
. Constant
. Indirect
. Storage
. Relative
16-bit Relative
Relative Indirect
. 16-bit Relative Indirect
O av ia WE
The eight types of addressing modes can be established using the storage
reference instructions: |
1. Absolute (address mode bits are 0, 1, 2, or 3). Both relative and
indirect flags equal 0 and delta is not 0. The base address equals
delta. Delta has no sign bit. The contents of the index registers,
when specified, are added to the base address to form the effective
address.
4-4 ~~ 60472800 C
2. Constant (address mode bits are 0, 1, 2, or 3). Both relative and
indirect flags are 0 and delta is 0. Where the address mode bits are
0, P+ 1 is the effective address. Where the address mode bits are 1,
2, or 3, the contents of P + 1, plus the contents of one or both index
registers form the effective address. The effective address is taken
as the operand for read-operand type instructions.
3. Indirect (address mode bits are 5, 6, or 7). Relative address flag is
0, indirect flag is 1, and delta is not 0. The 8-bit value of delta
is an indirect address. Delta is a magnitude quantity for this
operation (no sign bit). |
4. Storage (address mode bits are 4, 5, 6, or 7). Relative address flag
equals 0, indirect flag is 1, and delta is 0. The contents of
location P + 1 are an indirect address. When the base address is
formed (indirect addressing complete), the contents of one or both
index registers, if specified, are added to form the effective address.
5. Relative (address mode bits are 8, 9, A, or B). The relative flag is
0, and delta is not 0. The base address is equal to the instruction
address, P, plus the value of delta with sign extended. The contents
of the index registers, when specified, are added to the base address
to form the effective address. The address referenced by this mode is
located forward or backward relative to the P in the program.
6. 16-bit Relative (address mode bits are 8, 9, A, or B). The relative
address flag is 1, the indirect address flag is 0, and delta is 0. If
no indexing is specified, the instruction address P + 1, plus the
contents of location P + 1, form the base address = effective
address. If indexing is specified, the contents of the specified
index registers are added to the base address to form the effective
address.
7. Relative Indirect (address mode bits are C, D, E, or F). Both
relative and indirect flags are 1. ТЕ delta is not 0, the value of
the instruction address, P, plus the value of delta with sign
extending is an indirect address. When in 32K mode (multilevel
indirect), bit 15 of the contents of this indirect address is 0, the
contents of this indirect address is the base address. If bit 15 of
the contents of the indirect address is set, the contents of the
indirect address is another indirect address. Indirect addressing
continues until bit 15 of the contents of the indirect address is 0.
The contents of the index registers, when specified, are then added to
the base address to form the effective address. When in the 65K mode
(single level indirect), all 16 bits of the indirect address is the
base address, regardless of whether bit 15 is set.
8. 16-bit Relative Indirect (address mode bits are C, D, E, or F). Both
relative and indirect flags are 1. In 65K mode, the contents of P + 1
+ (P + 1)! is the base address. 1( ) denotes contents of. Then
the contents of the index registers, when specified, are added to the
base address to form the effective address. In 32K mode, P + 1 + (P +
1) = base address if bit 15 of (P + 1) is 0; if 1, then P + 1 + (P +
1) forms an indirect address and the indirection continues until bit
15 is O. о
Table 4-1 shows all the addressing possibilities for storage reference
instructions that can be obtained through combinations of flag bits.
60472800 C N 4-5
STORAGE REFERENCE INSTRUCTIONS
15 12 11 8 7 0
| F | Address Mode |
The storage reference instructions areas are as follows:
1. Unconditional Jump | JMP
(F = 1)
Effective address specifies the location of the next instruction.
2. Multiply Integer MUI
(F = 2)
Multiply the contents of the storage location specified by the
contents of the A register. The 32-bit product replaces the contents
of Q and A with the most significant bits in the Q register. One's
complement arithmetic is used.
3. Divide Integer | DVI
(F = 3)
Divide the combined contents of the Q and A registers with the
contents of the effective address. The Q register contains the most
significant bits before execution. The quotient is in the A register
and the remainder in the Q register at the end of execution. The
overflow indicator is set if the magnitude of the quotient is greater
than the capacity of the A register. Once set, the overflow indicator
remains set until a skip on overflow instruction is executed.
4. Store © STQ
(F = 4)
Store the contents of the Q register in the storage location specified
by the effective address. The contents of Q are not changed.
5. Return Jump RTJ
(F = 5)
Replace the contents of the storage location specified by the effec-
tive address with the address of the next consecutive instruction.
The address stored in the effective address is either P + 1 or P + 2,
depending on the addressing mode of RTJ. The contents of P are then
replaced with the effective address + 1.
6. Store A STA
(F =6)
Store the contents of the A register in the storage location specified
by the effective address. The contents of A are not altered.
4-6 a 1 60472800 C
7. Store A, Parity to A SPA
(F = 7)
Store the contents of the A register in the storage location specified
by the effective address. Set the A register to 0001 if the parity
bit of the word stored in the effective address is set. If the parity
bit is not set, set the A register to 0000.
8. Add to A ADD
(F = 8)
Add the contents of the storage location specified by the effective
address to the contents of the A register. One's complement arith-
metic is used. The overflow indicator is set if the magnitude of the
sum is greater than the capacity of the A register. Once set, the
overflow indicator remains set until a skip on overflow instruction is
executed.
9. Subtract from A | SUB
(Е = 9)
Subtract the contents of the storage location spcified by the
effective address from the contents of the A register. One's
complement arithmetic is used. Operation of overflow is the same as
in ADD. |
10. AND with A
(F = A)
Form the logical product, bit by bit, of the contents of the storage
location specified by the effective address and the contents of the A
register. The result replaces the contents of A.
11. Exclusive OR with A
(F = B)
Form the logical difference (exclusive OR), bit by bit, of the
contents of the storage location specified by the effective address
and the contents of the A register. The results replace the contents
of A. |
Ly
12. Load A LDA
(F = C)
Load the A register with the contents of the storage location
specified by the effective address. The contents of the storage
location are not altered. | |
13. Replace Add One in Storage ~~ RAO
(F = D)
Add one to the contents of the storage location specified by the
effective address. The contents of A and Q are not changed. One's
complement arithmetic is used. Operation of overflow is the same as
in ADD. |
60472800 C ВЕ 4-7
14. Load Q 1 LDQ
(F = E) |
Load the Q register with the contents of the storage location
specified by the effective address. The contents of the storage
location are not altered.
15. Add to O | ADO
(F = F)
Add the contents of the storage location specified by the effective
address to contents of the Q register. One's complement arithmetic is
used. Operation of overflow is the same as in ADD.
REGISTER REFERENCE INSTRUCTION FORMAT
Register reference instructions use the address mode field for the operation
code. Register reference instructions are identified by zeros in the upper 4
bits of an instruction. See figure 4-2.
REGISTER REFERENCE INSTRUCTIONS
The register reference instructions are as follows:
l. Selective Stop SLS
(FL = 0) А = 0
Stops the machine if this instruction is executed when the STOP switch
is on. The instruction becomes a NOP when the switch is off.
2. Input to A | - INP
(Fl = 2)
Read one word from an external device into the A register. The word
in the Q register selects the sending device. If the device sends a
reply, the next instruction comes from P + 1. If the device sends an
external reject, the next instruction comes from P + 1 +4, where A is
an 8-bit signed number including sign. An internal reject causes the
next instruction to come from P +A.
3. Output from A | OUT
(F1 = 3)
Deliver one word from the A register to an external device. The word
in the Q register selects the receiving device. If the device sends a
reply, the next instruction comes from P + 1. If the device sends an
external reject, the next instruction comes from P + 1 +A, where A is
an 8-bit signed number including sign. An internal reject causes the
next instruction to come from P + A. |
4-8 a. 60472800 C
15 12 11 8 7 0
| 0 0 00 El A |
—— —~—
Instruction Modifier
Operation Code
Figure 4-2. Register Reference Instruction Format
4, Increase A INA
(F1 = 9) |
Replaces the contents of A with the sum of the initial contents of A
and delta. Delta is treated as a signed number with the sign extended
into the upper 8 bits. Operation of overflow is the same as in ADD.
5. Enter A
(F1 = A)
Replaces the contents of the A register with 8-bit delta, sign
extended.
6. No Operation ВЕ | NOP
(F1 = B) = 0
;
7. Enter © | ENQ |
rer
(F1 = C)
Replaces the contents of Q with the 8-bit delta, sign extended.
8. Increase Q | INQ
(F1 = D) |
Replaces the contents of Q with the sum of the initial contents of Q
and delta. Delta is treated as a signed number with the sign extended
into the upper 8 bits. Operation of overflow is the same as in ADD.
The following instructions are legal only when the PROGRAM PROTECT switch" is
Off or the instructions themselves are protected. If an instruction is
illegal, it becomes a Selective Stop and an interrupt on Program Protect
Fault is possible (if selected).
Switch ON: Selective Stop unless instruction is protected.
Switch OFF: Normal execution (no program protection).
9. Enable Interrupt — | | EIN
(FL = 4) = 0
Activates the interrupt system. The interrupt system must be active
and the mask bit set for an interrupt to be recognized.
t A software switch activated by setting a bit in the Function Control
register. See table 3-3. | |
60472800 С | | | 4-9
10.
11.
12.
13.
14.
Inhibit Interrupt IN
(F1 = 5) = 0 ,
Deactivates interrupt system.
Set Program Protect
(Fl = 6) = 0
Sets the program protect bit in the address specified by Q.
Clear Program Protect | СРВ
(F1 = 7) = 0
Clears the program protect bit in the address specified by 0.
Exit Interrupt State EXI
(Fl = E)
This instruction is used to exit from any interrupt state. Delta
defines the interrupt state from which the exit is taken. This
instruction reads the address, resets the overflow indicator, if
necessary, activates the interrupt system and jumps to the return
address.
Interregister Instructions
(Fl = 8)
These instructions cause data from certain combinations of origin
registers to be sent through the adder to some combination of
destination registers. Various operations, selected by the adder
control lines, are performed on the data as it passes through the
adder. See figure 4-3,
If M is the destination register and the instruction is not protected
and the program protect switch is set, this is a nonprotected
Selective Stop instruction. The program protect fault bit is set and
“interrupt occurs if selected.
The origin registers are considered as operands. There are two kinds
defined as follows:
a. Operand 1 can be one of the following:
(1) FFFF,5 (bit 5 = 0)
(2) The contents of A (bit 5 = 1)
b. Operand 2 can be one of the following:
(1) FFFF1g (bit 4 = 0 and bit 3 = 0)
(2) The contents of M (bit 4 = 0 and bit 3
1)
(3) The contents of Q (bit 4 1 and bit 3 0)
(4) The OR, bit-by-bit, of the contents of Q and M
(bit 4 = 1 and bit 3 = 1)
60472800 C
Adder Control pines ——
Operand 1
[operand 2
—e—
15 1413121110 9 8 7 6 5 4 3 2 1 0
o 0 0 0|1 0 0 olPIXRIAJO|MÍAlO м |
+ V sí % . A y
Operation Code
The
all
| L Destination Register
Origin Register
Exclusive OR
Logical Product
Figure 4-3. Interregister Instruction Format
following operations are possible (see table 4-2 for examples of
possible 4-bit operands):
a. LP 0 and XR = 0 - The data place in the destination register (s)
is the arithmetic sum of operand 1 and operand 2. The overflow
indicator operates the same as in ADD.
b. LP 1 and XR = 0 - The data placed in the destination register (s)
is the logical product-bit-by-bit, of operand 1 and operand 2.
c. LP 0 and XR = 1 - The data placed in the destination register (s)
is the exclusive OR, bit-by-bit, of operand 1 and operand 2.
TABLE 4-2. INTERREGISTER INSTRUCTION TRUTH TABLE
Operand - Operand LP=Q LP=1 LP=1 LP=0
1 2 LR=1 XR=0 XR=0 | XR=0
0 0 0 0 1 Arithmetic
0 1 1 0 1 Sum
1 0 1 0 1
1 1 0 1 0
(Exclusive (Logical (Complement
OR) Product) ‘Logical
| Product)
NOTES: 1. Register transfers can be accomplished with LP = 0, XR = 0,
and by making operand 1 or operand 2 equal to FFFFjg.
2. Magnitude comparisons without destroying either operand can
be done with LP = 0, XR = 0, no destination register selected,
and by testing the overflow indicator.
3. Complementing registers can be done with LP = 0, XR = 1, and
making either operand 1 or operand 2 equal to FFFFjg.
60472800 C
-11
>
!
d. LP =1 and XR = 1 - The data in the destination registers is the
complement of the logical product, bit-by-bit, of operand 1 and
operand 2. |
The Interregister instructions for the processor are as follows:
Mnemonic Description Bit 765434
SET Set to Ones | | 10000
CLR Clear to Zero 01000
TRA Transfer A | 00100
TRO Transfer Q 00010
TRM Transfer M 00001
TRB Transfer Q+M | 00011
TCA Transfer Complement A 01160
TCM Transfer Complement M 01001
TCO Transfer Complement O 01010
TCB Transfer Complement O+M 01011
AAM Transfer Arithmetic Sum A,M 00101
AAB Transfer Arithmetic Sum A,Q+M 00111
AAQ Transfer Arithmetic Sum A,Q 00110
EAM Transfer Exclusive OR A,M ВЕ | 01101
EAQ Transfer Exclusive OR A,0 01110
EAB Transfer Exclusive OR A,Q+M 01111
LAM Transfer Logical Product A,M 10101
LAQ Transfer Logical Product A,Q 10110
LAB Transfer Logical Product A,Q+M 10111
CAM Transfer Complement Logical Product A,M 11101
CAQ | Transfer Complement Logical Product A,Q 11110
CAB Transfer Complement Logical Product A,Q+M 11111
NOTE: The symbol + implies an OR.
15. Skip Instruction Skip
(FL = 1) | Instruction
Format for this instruction is shown in figure 4-4.
Skip instructions are identified when the address mode field is 1 and
the instruction mode field is 0. When the skip condition is met, the
contents of the skip count +1 are added to P to obtain the address of
the next instruction (e.g., when the skip condition is not met, the
address of the next instruction is P+1 (skip count ignored). The skip
count does not have a sign bit.
15 12 11 8 7 6 5 4 3 0
lo 0 0 0 0 0 0 1 | a
F Instruction —— , Skip Count
| F1 Sub-Instruction F2 Skip Instruction
Figure 4-4. Skip Instruction Format
4-12 | 60472800 C
The skip instructions of the processor are as follows:
SAZ Skip if A= +0 (F2 = 0) all bits zero
SAN Skip if A # +0 (F2 =1) not all bits zero
SAP Skip if A = positive (F2 = 2)
SAM Skip if A = negative (F2 = 3)
507 Skip if Q = +0 (F2 = 4) all bits zero
SON Skip if Q # +0 (F2 = 5) not all bits zero
SOP — Skip if 0= positive (F2 = 6)
SOM Skip if Q = negative (F2 = 7)
SWG Skip if SELECTIVE SKIP switch set (F2 = 8)
SWN Skip if SELECTIVE SKIP switch not set (F2 = 9)
SOV Skip on overflow (F2 = A)
. SNO Skip on no over flow (F2 = B)
SPE Skip on storage parity error (F2 = C)
SNP Skip on no storage parity error (F2 = D)
SPF Skip on Program Protect Fault (F2 = E)
SNF Skip on no program protect Fault (F2 = F)
The skip-on-overflow (SOV) instruction performs skip if an overflow
condition occurred. It clears the overflow indicator.
The skip-on-storage-parity-error (SPE) instruction performs skip if a
storage parity error occurred. It clears the storage parity error
signal and indicator.
The program protect fault is set by:
l. A nonprotected instruction attempting to write into a protected
address.
2. A protected instruction executed immediately following a nonprotected
instruction, except when an interrupt has caused the instruction
sequence.
3. Execution of any nonprotected instruction which attempts to alter the
interrupt system.
The program protect fault is cleared when an SPF or SNF is executed. The
program protect fault cannot be set if the program protect system is disabled.
60472800 C 4-13
This shifts A or Q, or QA, left or right for the number of places
specified by the 5-bit shift correct. The sign is extended on right
shifts. Left shifts are end around.
Format for the shift instruction is shown in figure 4-5.
Shift Instructions
Mnemonic Instruction Name
ARS A Right Shift
ARS Q Right Shift
LRS Long Right Shift (QA)
ALS A left Shift
LLS Long Left Shift
ENHANCED INSTRUCTIONS
This section describes enhanced instruction formats.
— Type 2 Storage Reference Instructions
15 12 11 8 7 6 5 3 2 0
Р | F= 0 F1 = 4 |r |i Ra | Rb |
P +1 | F4 F5 A |
|| 8
P+ 2 0 l6-bit address, if A= '
Lo o —o—
The type 2 storage reference instruction is identified by a A 0 of the
enable interrupt instruction (F = 0, F1 = 4). A type 2 instruction is made
up of 2 (and sometimes 3) words. The r, i, Ra, and A subsections provide
addressing modes; Rb specifies an operand. |
15 12 11 8 7 6 5 4 0
O O O OPI 1 1 1 |
1 = Shift Left ' Shift
0 = Shift Right Count
1 = Shift A
1 = Shift O
Figure 4-5. Shift Instruction Format
4-14 | “ 60472800 C
The F4 field determines the instruction (e.g., add, subtract, etc.); the F5
field determines the instruction mode and has the following definition:
F5 = 0 - word processing, register destination
F5 = 1 - word processing, memory destination
F5 = 2 - character processing, register destination
F5 = 3 - character processing, memory destination
NOTE
F5 is not used for subroutine jumps and subroutine exit.
The register/memory destination bit of F5 is not used for
compare instructions (see below).
The addressing mode fields contain four fields to determine the addressing:
1. Delta determines 8- or 16-bit addressing. If delta is zero, a third
word is required to specify a 16-bit address. |
2. Flag r is the relative address flag.
3. Flag i is the indirect address flag.
4, Register Ra is the index register.
The addressing modes are similar to type 1 storage instructions. Type 1
allows indexing by one or two registers (I and Q); while type 2 allows
indexing by any one of seven registers (1, 2, 3, 4, Q, A, or I). Table 4-3
specifies the addressing modes, the effective address, and the address of the
next instruction.
The addressing mode fields determine the effective address for operand A.
Register Rb and the instruction mode field (F5) determine the address for
operand B. Note that for character addressing, the effective address
(operand A and register Rb) are combined to ascertain the actual character
effective address (refer to character instructions). Operand B is always the
A register for character addressing.
NOTE
For character addressing, a selection of absolute (r is
zero), no indirect (i is zero), no index register (Ra is
zero), and no character register (Rb = 0) results in an
EIN instruction. | |
Unspecified combinations of F4, F5, and Rb are reserved for future expansion.
The following definitions apply to the description of addressing modes.
1. Instruction Address: The address of the instruction being executed,
also called P.
2. Indirect Address: A storage address that contains an address rather
than an operand. Note that there is no multilevel indirect addressing
for type 2 storage reference instructions.
3. Base Address: The operand address after all indirect addressing but
before modification by an index register. The base address is the
effective address if no indexing is specified.
60472800 C | | 4-15
TABLE 4-3. TYPE 2 STORAGE ADDRESSING RELATIONSHIPS
Addressing | Effective Address of Next
Mode Delta r i Ra Address (EA) Instruction
8-bit Absolute A #0 0 0 0 A | P+2
0 10 11 A +(1) P+2
0 0 2 A +(2) — P+2
10 0 3 ‚ А +(3) | P+2
0 0 4 A +(4) P+2
0 0 5 A +(0) P+2
0 0 6 А + (А) Р+2
0 0 7 A +(1) P+2
8-bit Absolute A #; 0 O 1 0 (A) P+2
Indirect 0 1 1 (А) + (1) P+2
0 1 2 (А) + (2) Р+2
0 1 3 (A) + (3) P+2
0 1 4 (A)+(4) P+2
0 1 5 (A)+(0) P+2
0 1 6 (A) + (А) . P+2
0 1 7 (A) + (I) P+2
8-bit Relative Ÿ A #0 |1 | 0 jO P+1+A P+2
1 0 1 P+1+A+ (1) P+2
1 0 2 P+1+A+ (2) P+2
1 0 3 P+1+A+(3) — P+2
1 0 4 P+1+A+ (4) P+2
1 0 5 P+1+A+ (0) P+2
1 0 6 P+1+A+ (A) P+2
1 0 7 P+1+A+ (I) P+2
8-bit Relative A # 0 1 1 0 (P+1+A) P+2
Indirect + 1 1 1 (P+1+A)+(1) | P+2
1 1 2 (P+1+A) + (2) P+2
1 1 3 (P+1+A) + (3) | P+2
111 (4 (Р+1+4) + (4) 0 Р+2
dl 1 5 (P+1+A) +(Q) - P+2
1 1 6 (P+1+A) + (A) P+2
1 1 7 (P+1+4A) + (I) P+2
Absolute А = 0 0 0 0 P+2 | a. P+3
Constant 0 0 1 P+2+ (1) | P+3
0 | O 2 Р+2+ (2) P+3
0 0 3 Р+2+ (3) P+3
0 0 4 Р+2+ (4) Р+3
0 0 5 Р+2+ (0) P+3
0 0 6 P+2+ (A) P+3
0 0 7 P+2+ (I) P+3
4-16 | | I ~~ 60472800 C
TABLE 4-3. TYPE 2 STORAGE ADDRESSING RELATIONSHIP (Contd)
Addressing Effective Address of Next
Mode Delta r i Ra Address (EA) Instruction
16-bit Absolute A= 0 0 1 0 (P+2) P+3
(Storage) 0 1 1 } (P+2)+(1) P+3
0 | 1 | 2 (P+2)+(2) P+3
0 1 3 (P+2)+ (3) P+3
0 1 4 (P+2)+ (4) P+3
0 1 5 (Р+2) + (0) Р+3
0 1 6 (P+2)+ (A) P+3
0 1 7 (P+2)+ (I) P+3
16-bit Relative A= 0 1 O 1 O P+2+ (P+2) P+3
1 O0 | 1 P+2+(P+2)+(1) P+3
1 0 2 P+2+(P+2)+(2) P+3
1 10 3 Р+2+ (Р+2) + (3) Р+3
1 0 | 4 P+2+(P+2)+(4) P+3
1 0 5 Р+2+ (Р+2) + (90) P+3
1 0 6 Р+2+ (Р+2) + (А) P+3
1 0 7 Р+2+ (Р+2) + (I) Р+3
16-bit Relative A= 0 1 1 0 (P+2+(P+2)) P+3
Indirect 1 1 1 (P+2+(P+2))+(1) P+3
1 1 2 (P+2+ (P+2))+ (2) P+3
1 1 3 (P+2+ (P+2)) + (3) P+3
1 1 4 (P+2+ (P+2)) + (4) P+3
1 1 5 (P+2+(P+2))+(0) P+3
1 1 6 (P+2+ (P+2)) + (A) P+3
1 1 7 (P+2+(P+2))+(I) P+3
TFor these addressing modes, delta is sign extended.
NOTE : ( ) denotes contents of. |
4. Effective Address:
The final address of the operand.
5. Indexing: If specified, the contents of register Ra is added to the
base address to form the effective address.
completion of addressing.
Indexing occurs after
The computer uses the 16-bit one's complement adder during indexing
operations.
signed quantities (bit 15 is the sign bit).
Consequently, the index register contents are treated as
6. Registers: Registers Ra and Rb are defined as follows:
60472800 C
Pal DO a OU юн
— Register
None
Value
IA VU NV | ©
Type 2 storage reference instructions (table 4-3) have the following eight
different types of addressing modes:
1. 8-Bit Absolute - (r is zero, 1 is zero, and delta is not zero.) The
base address equals delta. The sign bit of delta is not extended.
The contents of index register Ra, when specified, are added to the
base address to form the effective address.
2. 8-Bit Absolute Indirect - (r is zero, 1 15 one, and delta is not
zero.) The 8-bit value of delta is an indirect address. The sign bit
of delta is not extended. The contents of this address in low core
(addresses 0001 to 00FF) is the base address. The contents of index
register Ra, when specified, are added to the base address to form the
effective address.
3. 8-Bit relative - (r is one, i is zero, and delta is not zero.) The
base address is equal to the instruction address plus one, P + 1, plus
the value of delta with sign extended.
The contents of index register Ra (when specified) are added to the
base address to form the effective address.
If no indexing takes place, the addresses that can be referenced in
the 8-bit relative mode are restricted to the program area. Delta is
8 bits long, thus the computer references a location between P-7E16
and P + 8016 inclusive.
4. 8-Bit Relative Indirect - (г is one, i is one, and delta is not
zero.) The address of the second word of the instruction, P + 1, plus
the value of delta with sign extended is an indirect address. The
contents of this address is the base address. The contents of index
register. Ra, when specified, is added to the base address to form the
effective address. |
5. Absolute Constant - (r is zero, i is zero, and delta is zero.) The
address of the third word of instruction P + 2 is the base address.
The contents of index register Ra, when specified, are added to the
base address to form the effective address. Thus, when Ra is not
specified, the contents of P + 2 is the value of the operand.
Note that there is no immediate operand condition (i.e., indexing is
specified and the instruction is a read-operand type) as there is for
type 1 storage reference addressing.
6. 16-Bit Absolute - (Storage) (r is zero, i is one, and delta is zero.)
The base address equals the contents of P + 2. The contents of index
register Ra, when specified, are added to the base address to form the
effective address.
7. 16-Bit Relative - (r is one, i is zero, and delta is zero.) The base
address equals the contents of P + 2 pius P + 2. The contents of
index register Ra, when specified, are added to the base address to
form the effective address.
8. 16-Bit Relative Indirect - (r is one, i is one, and delta is zero.)
The address of the third word of the instruction, P + 2, plus the
contents of the third word of the instruction is an indirect address.
The contents of this address is the base address. The contents of the
index register Ra, when specified, are added to the base address to
form the effective address.
4-18 | | | 60472800 С
Instruction descriptions are as follows:
l.
Subroutine/Jump Exit SJE
(F4 = 5, F5 = 0, Rb = 0)
The contents of P are replaced with the effective address. This
instruction can be used as a jump or subroutine exit. For example, if
delta is one and Ra has been set up by a previous subroutine jump (see
below), control is returned following that subroutine jump.
Note that subroutine jumps save the address of the instruction, rather
than the next instruction, so the subroutine jump exit may be a
two-word instruction (delta non-zero) rather than three.
For example, the following program makes a subroutine jump at location
1000. Register A contains 1002 upon entry to the subroutine SUB.
Upon completion, the SUB exits to location 1003. |
1000 0446 — SJA+SUB
1001 5000
1002 2000 .
1003 | .
2000 .... SUB coe. 2. .
2020 0430 | — SJE-1,A
2021 5001
NOTE
Since Rb is 0, a selection of absolute (r is 0), no
indirect (i is 0), and no index register (Ra = 0) results
in an EIN instruction. |
Subroutine Jump ; о SJr
(F4 = 5, F5 = 0, Rb =1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Load register r with the address of the last word of this instruction
(i.e., P+1 for delta not zero; P+2 for delta zero). The contents of P
are then replaced with the effective address.
Add Register | | | ARr
(F4 = 8, F5 = 0, Rb = 1, 2, 3, 4, 5, 6, Or 7)
(r = 1, 2, 3, 4, A, Q, or 1)
Add (using one's complement arithmetic) the contents of the storage
location specified by the effective address to the contents of
register r. Operation on overflow is the same as for the ADD
instruction. The contents of storage are not altered.
60472800 € = a 4-19
Subtract Register — 1 SBr
(F4 = 9, F5 = 0, Rb = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Subtract (using one's complement arithmetic) the contents of the
storage location specified by the effective address from the contents
of register r. Operation on overflow is the same as for the ADD
instruction. The contents of storage are not altered.
AND Register | ANr
(F4 = A, FS = 0, Rb = 1, 2, 3, 4, 5, 6, Or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Form the logical product (AND), bit-by-bit, of the contents of the
storage location specified by the effective address and the contents
of register r. The result replaces the contents of register r. The
contents of storage are. not altered. |
AND Memory |
(F4 = A, F5 = 1, Rb = 1, 2, 3, 4, 5, 6, or 7)
(Y = 1, 2, 3, 4, Q, A, or I)
Form the logical product (AND), bit-by-bit, of the contents of the
storage location specified by the effective address and the contents
Of register r. The result replaces the contents of the storage
location specified by the effective address. The original contents of
the storage location (specified by the effective address) replace the
contents of register A. The contents of register r are not altered
unless r is the A register. Memory is locked until completion of the
instruction. This instruction is useful for communication between
processors via memory.
Load register LRr
(F4 = C, F5 = 0, Rb = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Load register r with the contents of the storage location specified by
the effective address. The contents of storage are not altered.
Store Register о SRr
(F4 = C, F5 = 1, Rb = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Store the contents of register r in the storage location specified by
the effective address. The contents of register r are not altered.
Load Character to A | LCA
(F4 = C, F5 = 2)
Load bits 0 through 7 of register A with a character from the storage
location specified by the sum of the effective address and bits 1
through 15 of register Rb. Register Rb bit 0 is zero specifies the
left character (bits 8 through 15) of the storage location; bit 0 = 1
specifies the right character (bits 0 through 7). Bits 8 through 15
of register A are not altered.
60472800
10. Store Character from A SCA
(F4 = C, F5 = 3)
Store the contents of bits 0 through 7 of register A into a character
of the storage location specified by the sum of the effective address
and bits 1 through 15 of register Rb. Bit 0 is zero of register Rb
specifies the left character (bits 8 through 15) of the storage
location; bit 0 is one specifies the right character (bits 0 through
7). The contents of register A and other storage characters are not
altered. :
11. OR Register | ORr
(4 D, F5 = 0, Rb = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, ©, А, or I)
Form the logical sum (inclusive OR), bit-by-bit, of the contents of
the storage location specified by the effective address and the
contents of register r., The result replaces the contents of register
r. The contents of storage are not altered.
12. OR Memory 1 ОМ:
(F4 = D, F5 = 1, Rb = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Form the logical sum (inclusive OR), bit-by-bit, of the contents of
the storage location specified by the effective address and the
contents of register r. The result replaces the contents of the
storage location specified by the effective address. The original
contents of the storage location (specified by the effective address)
replaces the contents of register A. The contents of register r are
not altered unless r is the A register. Memory is locked until
completion of the instruction. This instruction is useful for
communication between processors via memory.
13. Compare Register Equal CrE
(F4 = E, F5 = 5, Rb = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or 1)
If the contents of register r and the contents of the storage location
specified by the effective address are equal, bit-by-bit, skip one
location; otherwise, execute next instruction. The contents of
register r and storage are not altered.
14. Compare Character Equal CCE
(F4 = Е, F5 = 2)
If the contents of bits 0 through 7 of register A and the character of
the storage location specified by the sum of the effective address and
bits 1 through 15 of register Rb are equal, bit-by-bit, skip one
location; otherwise, execute the next instruction. Bit 0 is zero of
register Rb specifies the left character (bits 8 through 15) of the
storage location; bit 0 is one specifies the right character (bits 0
through 7). The contents of register A and storage are not altered.
Each compare instruction assumes that a one-word instruction follows
it. |
60472800 C | i | 4-21
Field Reference Instructions
These instructions are described in the following paragraphs.
15 12 11 8 7 6 5 3 2 0
F=0 Fl = 5 r i Ra F3a
P+ 1 FLDSTR FLDLTH-1 | А
Р + 2 | | 16-bit address, if A= 0 A
Field reference instructions are identified when the F field is zero, the Fl
field is five, and the r, i, Ra, and F3a fields are not all zero. (If these
fields are all zero, the instruction is an IIN.)
Field reference instructions contain four parts: operation field (F3a),
addressing mode fields (delta, г, 1, and Ra), FLDSTR, and FLDLTH-1 fields.
The F3a field determines the operation (e.g., load, store, etc.). The
addressing mode fields are defined exactly as the type 2 storage reference
instruction.
FLDSTR defines the starting bit of the field: FLDSTR = 0 means the field
starts at bit 0; FLDSTR = 15 means the field starts at bit 15. FLDLTH-1
defines the length of the field minus one: if FLDLTH-1 is zero the field is
one bit long; if FLDLTH-1 is 15, the field is 16 bits long. Note that if
FLDLTH-1 is zero the field reference instructions become bit reference
instructions.
A field starts at the bit specified by FLDSTR and includes FLDLTH contiguous
bits to the right of that bit. No field can cross a word boundary (i.e.,
FLDSTR-FLDLTH-1 must be greater than or equal to zero); e.d., if FLDSTR is
zero, the field length must be one bit long (FLDLTH-1 is zero).
Note that F3a = 0, F3a = 1, and FLDSTR-FLDLTH-1 1 are reserved for future
expansion.
1. Skip if Field Zero SFZ
- (F3a = 2) |
If the contents of the specified field of the storge location
identified in the effective address are zero (all bits are zero), skip
one location; if the contents are not zero execute the next |
instruction,
2. Skip if Field Not Zero | SFN
(F3a = 3)
If the contents of the specified field of the storage location field
identified in the effective address are not zero (not all bits are
zero), skip one location, if zero, execute the next instruction.
NOTE
Each skip field instruction assumes that a one-word
instruction follows it. |
>
!
22 60472800 С
3. Load Field | LFA
(F3a = 4) |
Load register A, right justified, with the contents of the specified
field of the storage location field identified in the effective
address. All other bits of register A are cleared to zero. The
contents of storage are not altered.
4. Store Field | | | SFA
(F3a = 5)
Store the contents of the field from register a, right justified, into
the specified field of the storage location identified in the |
effective address. All other storage bits are unchanged. Memory is
locked until completion of the instruction. The contents of A are not
altered.
5. Clear Field CLF
(F3a = 6) |
Clear the specified field of the storage location specified by the
effective address to all zeros. All other storage bits are
unchanged. Memory is locked until completion of the instruction.
6. Set Field SEF
(F3a = 7)
Set the specified field of the storage location identified in the
effective address to all ones. All other storage bits are unchanged.
Memory is locked until completion of the instruction.
Type 2 Skip Instruction
These skip instructions are in the following format:
15 12 11 8 7 Аз 0
| F = 0 F1 = 0 F2 SK |
Type 2 skip instructions are identified when the F and Fl fields are both
zero, and the F2 and SK fields are not both zero. (If these fields are both
zero, the instruction is an SLS.)
Type 2 skip instructions (similar to type 1 skips, e.g., SAZ) contain two
parts: operation field (F2) and skip count (SK). The F2 field determines
the operation (i.e., skip on register 1, 2, 3, or 4 if zero, nonzero,
positive, or negative). The skip count specifies how many locations to skip
if the skip condition is met.
When the skip condition is met, the skip count plus one is added to the P
register to obtain the address of the next instruction (e.g., when the skip
count is one, go to P + 2). When the skip condition is not met, the address
of the next instruction is P + 1 (skip count ignored). The skip count does
not have a sign bit.
60472800 C 4-23
Note from above that if F2 is 0 (SrZ), the skip count cannot be zero because
the instruction would be an SLS.
Instruction descriptions are as follows:
1. Skip if Register Zero SrZ SK
~~ (F2 = 0, 4, B, or C) (r = 4, 1, 2, or 3)
Skip if register r is a positive zero (all bits are zero).
2. Skip if Register Nonzero SrN SK
(F2 = 1, 5, 9 or D) (r = 4, 1, 2, or 3)
Skip if register r is not a positive zero (not all bits are zero).
3. Skip if Register Positive SrP SK
-Skip if register r is positive (bit 15 is zero).
4. Skip if Register Negative SrM SK |
(F2 = 3, 7, B, or F) (r = 4, 1, 2, Or 3)
Skip if register r is negative (bit 15 is one).
‘Decrement and Repeat Instructions
These instructions are in the following format:
15 12 11 8 7 5 4 3 0
| F= 0 FI = 6 Ra 0 SK |
Decrement and repeat instructions are specified when the F field is zero, the
Fl field is equal to six, bit 4 is zero, and the Ra and SK fields are both
not zero. (If these fields are both zero, the instruction is a SPB.)
Decrement and repeat instructions contain two parts: Register field (Ra) and
skip count (SK). The register field specifies which register is to be
decremented by one and checked for the skip condition. The skip count
specifies how many locations to repeat (go backwards) if the skip condition
is met.
When the skip condition is met, the skip count is subtracted from the P
register to obtain the address of the next instruction (e.g., when the skip
count is one, go to P-1). When the skip condition is not met, the address of
the next instruction is P + 1. The skip count does not have a sign bit.
Note that Ra = 0 and bit 4 = 1 are reserved for future expansion.
Instruction description is as follows:
4-24 60472800 C
1. Decrement and Repeat if Positive DrP SK
(Ra = 1, 2, 3, 4, 5, 6, or 7) (r = 1, 2, 3, 4, Q, A, or I)
Decrement by one the contents of register r. Operation on overflow is
the same as for the ADD instruction. Repeat (go backwards) SK
locations if the contents of register r are positive (bit 15 is zero);
if otherwise, execute the next instruction.
Type 2 Interregister Instructions
These instructions are in the following format.
15 12 11 8 7 5 4 32 0
| F= 0 Fl = 7 Ra F2a Rb |
Type 2 interregister instructions are identified when the F field is zero,
the Fl field is seven, and the F2a, Ra, and Rb fields are not all zero. (If
these fields are all zero, the instruction is CPB.)
Type 2 interregister instruction (similar to type 1 interregister, e.g., TRA
Q) contains three parts: operation field (F2a) and two register fields (Ra
and Rb). The F2a field determines the operation (e.g., transfer). The Ra
and Rb fields specify two operands. |
Note that F2a = 1, F2a = 2, F2a = 3, Ra = 0, and Rb = 0 are reserved for
future expansion.
Instruction description is as follows:
l. Transfer Register ~~ XFr R
(F2a = 0, Ra = 1, 2, 3, 4, 5, 6, or 7)
(r = 1, 2, 3, 4, Q, A, or I)
Transfer the contents of register r to register R.
Note that R = 1, 2, 3, 4, Q, A, or I, implies that Rb = 1, 2, 3, 4, 5,
6, or 7. |
Miscellaneous Instructions
Miscellaneous instructions are in the following format.
15 12 11 8 7 5 4 3 0
| ЕР = 0 Fl = B Ra 01 F3 |
Miscellaneous instructions are identified when the F field is zero, the Fl
field is a decimal 11 (hex B) and bit 4 is zero, and the Ra and F3 fields are
not both zero. (If these fields are both zero, the instruction is an NOP.)
All of the miscellaneous instructions are privileged instructions, i.e., they
cannot be executed by an unprotected program and cause a program protect
violation instead. :
60472800 € | 4-25
Miscellaneous instructions contain two parts: Operation field (F3) and
register field (Ra).
If Ra is not zero, the F3 operation field can select up to 16 miscellaneous
instructions with register Ra used to specify an operand. If Ra is zero, the
F3 operation field can select up to 15 more miscellaneous instructions
without any explicit operand specified. |
Instruction descriptions are as follows:
1. Load Mi cromemory |
(F3 = 1, Ra = 0)
Load a block of 32-bit micromemory words into read/write micromemory
from 16-bit main memory.
Initially, the Q register contains the number of 32-bit micromemory
words to be transferred (if Q is 0, no words are be transferred).
Register 1 contains the starting address of micromemory.
15 13 12 9 8 1 0
| 000 | Page Microaddress Эт,
a. Bits 13 thru 15 must be zero.
b. Bits 9 thru 12 specify the micropage.
c. Bits 1 thru 8 specify the micromemory address. |
d. Bit 0 specifies the upper (0) or lower (1) microinstruction.
Register 2 contains the starting address of main memory.
This instruction is interruptible after storing each 32-bit
micromemory word, and when registers 1, 2, and Q are
incremented/decremented to allow the restarting of the instruction
after any interruption. Therefore, upon completion of the
instruction, these registers do not contain their original values, but
do contain the following:
о + 0
R1 < (R1)i+(0)i
R2 «+ (R2)i+2*(0)i
Where i denotes the initial value before execution.
2. Load Registers | LRG
(F3 = 2, Ra = 0) |
Register 1, 2, 3, 4, Q, A, I, M, and the OVERFLOW indicator are loaded
with the contents of nine storage locations, beginning at a storage
location specified by the contents of the contents of the next
location, P + 1 as follows:
4-26 | | | 60472800 C
(((P+1))+1) + 1
(((P+1))+2) + 2
(((P+1))+3) + 3
(((P+1))+4) + 4
(((P+1))+5) =» Q
(((P+1))+6) + A
(((Р+1)) +7) + I
(((Р+1)) +8) + M
bit 15 of (((P+1))+9) + OVERFLOW
The contents of the storage location specified by the contents of the
next location are then decremented by a decimal 10, that is:
((P+1))-10 + (P+1)
Any data stored in location ((P + 1)) or bits 0. through 14 of location
((P + 1)) + 0 can be extracted before the execution of the LRG
instruction via the address (specified by the contents of the contents
of the next location).
The contents of the nine storage locations are not altered and the
next instruction is executed at location P + 2 (i.e., the LRG
instruction is a two-word instruction).
3. Store Registers | | | SRG
(F3 = 3, Ra = 0) '
The contents of the storage location specified by the contents of the
next location P + 1, is first incremented by a decimal 10, that is:
((P+1))+10 + (P+1)
Then the contents of registers 1, 2, 3, 4, Q, A, I, and M, and the
OVERFLOW indicator are stored in nine storage locations, beginning at
a storage location specified by the contents of the incremented
address as follows: |
( (P+1))+1
((P+1)) +2
{(P+1))+3
((P+1)) +4
((P+1)) +5
((P+1))+6
(I) ((P+1))+7
(M) ((P+1))+8
(OVERFLOW) bit is 15 of ((P+1))+9
(1)
(2)
(3)
(4)
(Q)
(A)
+ + + + + + + +
After the storing is completed, the OVERFLOW indicator is cleared.
Note that location ((P+1)) and bits 0 thru 14 of location ((P+1)+9 can
be used to store a program address, priority level, parameter address,
or other data after the execution of the SRG instruction via the
address (specified by the contents of the next location).
The contents of the registers are not altered and the next instruction
is executed at location P+2 (i.e., the SRG instruction is a two-word
instruction). |
60472800 C | 4-27
- Set/Sample Output or Input SIO
(F3 = 4, Ra = 0)
For output, one word from register A is set (output) to an external
device. The word in register Q selects the receiving device.
For input, one word from an external device is sampled (input) to
register A. The word in register Q selects the sending device.
This instruction permits transmission to/from MO5 peripheral devices.
The Q register is defined as follows:
15 11 10 9 7 6 4 3 1 0
EL 0 00 1 Port Pos Mode о |
a. Bits 11 thru 15 and bit 0 must be zero.
b. Bits 7 thru 10 contain the port number of the device, with bit 10
always a one. Port numbers are analogous to the AW 1/0 equipment
numbers and thus cannot conflict with them.
c. Bits 4, 5, and 6 designate the device's position on the port.
These bits can also be mode bits (see below) if some or all of the
position bits are not required.
d. Bits 1, 2, and 3 contain the mode in which the device is to
operate. Bit 3 is always the set/sample condition bit; if one,
one data word is set (output); if zero, one data word is sampled
(input).
Sample Position/Status SPS
(F3 = 5, Ra = 0)
Sample (input) to the A register the position and the status of a MO5
device, which has caused a macrointerrupt. The word in the Q register
selects the device. This instruction also provides for the clearing
of the MO5 generated macrointerrupt. The Q register is defined as
follows:
15 11 10 9 7 6 0.
00000 l Port 6000000 о |
a. Bits 0 thru 6 and 11 through 15 must be zero.
b. Bits 7 thru 10 contain the port number of the MO5 device, with bit
10 always a one. Port numbers are analogous to the AW I/O
equipment numbers and thus cannot conflict with them.
60472800 C
Upon completion of the instruction, the A register contains the
following:
15 12 11 8 7 5 4 2 1 0
| 0000 Status 000 Pos | O о|
a. Bits 0 and 1, 5, 6, and 7, and 12 thru 15 are zero.
b. Bits 2, 3, and 4 contain the device's position.
с. Bits 8 thru 11 contain the least significant 4 bits of the data
input lines. If these 4 bits of status information are
insufficient, the device's controller can provide for the transfer
of additional status bits via the SIO instruction.
6. Define Microinterrupt DMI
(F3 = 6, Ra = 0)
Defines the use of one of the 12 available microinterrupts. (The use
of microinterrupts 12 thru 15 are restricted for internal use.)
This instruction allows the enabling/disabling of a microinterrupt and
defining it for Autodata Transfer (ADT) or special usage.
The Q register selects and enables/disables the microinterrupt, which
is defined as follows: |
15 14 | 4 3. 0
| x 00000000000 Microinterrupt |
a. Bit 15 enables/disables the microinterrupt; if one, the
microinterrupt is enabled; if zero, the microinterrupt is
disabled; the A register is not utilized. Initially, all 12
microinterrupts are disabled. |
b. Bits 4 thru 14 must be zero.
c. Bits 0 thru 3 contain the microinterrupt number (0 thru 11). Note
that 12 thru 15 are not available for use and, if used, the
instruction is treated as an NOP. | | |
The A register defines the microinterrupt for ADT or special usage and
is defined as follows: |
15 14 0
| x ADT Table or Page Micromemory Address |
a. If bit 15 is a zero, ADT is selected and bits 0 thru 14 contain
the ADT Table Address. It must be within the lower 32K of main
memory. | |
60472800 С Е — 4-29
Four types of ADT Tables are possible for a particular
microinterrupt:
(1) Single AQ device
(2) Multi AQ devices
(3) Clock device
(4) Single or Multi MO5 devices
b. If bit 15 is a one, the special usage is selected and a jump is
made to the upper microinstruction of the page micromemory in bits
O thru 14, A section of micromemory is assumed to have been |
previously loaded, and it must process the microinterrupt properly
and return control to the current macroinstruction address (P) by
jumping to the lower microinstruction of micromemory address
3E16 in micropage zero. Registers P, A, Q, and all file 2
should not be altered, and return must be within 12.5 microseconds.
“NOTE
The processor microfunction SUB- must not be used.
Bits 0 thru 15 of the A register are defined as follows for this
special usage:
15 12 11 8 7
0
1000 | Page Micromemor y address |
a. Bit 15 must be one.
b. Bit 12 must be zero.
с. Bits 8 thru 11 specify the micropage.
d. Bits 0 thru 7 specify the micromemory address.
NOTE
Extreme caution should be exercised in using this option,
since it provides an escape from the 1700 emulation being
performed.
Clear Breakpoint Interrupt CBP
(F3 = 7, Ra = 0) | | |
Clear the processor macrobreakpoint interrupt. This interrupt occurs
when the following conditions are true. |
a. Macrobreakpoint (reference and/or storage) is externally selected.
b. Macrobreakpoint interrupt option is externally selected.
c. The MP recognizes a breakpoint condition and generates a
macrobreakpoint interrupt because of b.
The macroprogrammer then has the responsibility of clearing (CBP
instruction) and processing the interrupt. |
60472800 С
8. Generate Character Parity Even GPE
(F3 = 8), Ra = 0)
Set or clear bit 7 of the A register to cause the parity of bits 0
thru 7 to be even. The rest of the contents of the A register are not
altered. |
9. Generate Character Parity Odd GPO
(F3 = 9, Ra = 0)
Set or clear bit 7 of the A register to cause the parity of bits 0
thru 7 to be odd. The rest of the contents of the A register are not
altered.
10. Scale Accumulator | ASC
(F3 = A, Ra = 0)
The A register is shifted left (end-around) until bits 14 and 15 of
the A register are different. Upon completion of the instruction,
register contains the number of places that the A register was
shifted. (This number can range from zero through 1410.) If the A
register is + zero (0000 or FFFF), no shifting is done and register 1
contains minus zero (FFFF).
11. Load Upper Unprotected Bounds LUB R
(F3 = 0, Ra = 1, 2, 3, 4, 5, 6, Or 7) (R = 1, 2, 3, 4, Q, A, or 1)
Load the upper unprotected bounds register from the contents of
register R. |
12. Load Lower Unprotected Bounds LLB R
(F3 = 1, Ra = 1, 2, 3, 4, 5, 6, or 7) (R = 1, 2, 3, 4, Q, A, or I)
Load the lower unprotected bounds from the contents of register R.
13. Execute Microsequence EMS R
(F3 = 2, Ra = 1, 2, 3, 4, 5, 6, or 7) (R = 1, 2, 3, 4, Q, A, or I)
Transfer machine control to the upper microinstruction of the page/
micromemory address in bits 0 thru 15 of register R. A section of
micromemory is assumed to have been previously loaded and it should
return control to the next macroinstruction address (P + 1) by jumping
to the lower microinstruction of micromemory address E16 in
micropage Zero.
Registers P, A, Q, and all of file 2 should not be altered, and return
must be within 12.5 microseconds (or the microsequence must be
interruptible). Bits 0 thru 15 of register R are defined as follows:
12 11 8 7 0
po 000 Page Micromemory Address |
31
60472800 C 4
a. Bits 12 thru 15 must be zero.
b. Bits 8 thru 11 specify the micropage.
c. Bits 0 thru 7 specify the micromemory address.
NOTE
Extreme caution should be exercised in using this
instruction, since it provides escape from 1700 emulation.
Autodata Transfer
Autodata Transfer (ADT) provides for pseudo-direct memory transfers of data
blocks to or from a device. At the macrolevel, the transfer appears as
direct memory/storage access (DMA) transfer; however, at the microlevel, the
1700 emulator processes each data interrupt and inputs or outputs the next
datum in a singular fashion. Thus, ADT takes less time than input/out via
the INP, OUT, or SIO instructions but more time than a true DMA transfer.
To accomplish ADT for a particular device, perform the following:
1. The device and its controller must adhere to the Autodata Transfer
specifications.
2. The macroprogrammer must execute a DMI instruction. This command
specifies where the block of data is, how long it is, the direction
(input/output), and the device address. |
3. The ADT operation is then initiated by an INP, OUT, or SIO instruction
as specified by the particular device.
While the ADT operation is in progress, the emulator is executing
instructions. After each instruction is executed, interrupts are checked.
When the particular ADT microinterrupt becomes the highest active interrupt,
the next datum is input or output. After the interruption, the next
instruction is executed, except when another interrupt is active.
When the ADT operation is completed (or if there is an error), a macro-
interrupt is generated. The macroprogrammer can than disable the ADT
microinterrupt or initiate another ADT operation to or from the device.
The following defines the four types of ADT tables specified by DMI
instructions:
1. ADT Table for a Single AQ Device
15 14 13 12 11 10 7 6 0 Word
0 0 W/C 0 R/W Equip Station Director ВЕ 1
FWA-1 and CWA | 2
LWA Е 3
- Not used | 4
4-32 60472800 C
The ADT table for this type consists of four words:
a. In word 1, bits 12, 14, and 15 must be zero.
b. In word 1, bit 13 is zero if a word operation, is one if a
character operation. For word operation, data is transferred one
word at a time. Normally, a total of (CWA - FWA + 1) words are
transferred.
For character operation, data is transferred one character (8
bits) at a time. On input, the first character is stored in the
most significant half (bits 8 thru 15) of the current word
address; the second character in the least significant half (bits
0 thru 7). Subsequent pairs of characters are input in the same
fashion. For output, the first character is output from the most
significant half (bits 8 thru 15) of the current word address; the
second character from the least significant half (bits 0 thru 7).
Likewise, subsequent pairs of characters are output in the same
way. Normally, a total of 2 x (CWA - FWA + 1) characters are
transferred.
c. In word 1, bit 11 is zero if a read ADT operation and one if a
write ADT operation.
d. In word 1, bits 7 thru 10 contain the equipment number of the
device.
e. In word 1, bits 0 thru 6 contain the station/director bits of the
device to execute the ADT operation. The director bits should
specify a data (not a status/function) transfer.
f. Word 2 is initially set to the first word address - 1 (FWA-1) of
the data block to be transferred. This word is used as the
current word address (CWA) as the ADT operation is in progress and
points to the last data word read or stored. Each time a word (or
two characters if a character operation) is transferred, CWA is
incremented. Specifically, CWA can be used to ascertain whether
all the ADT operation was completed (i.e., if CWA = LWA, all the
data has been transferred). |
g. Word 3 contains the last word address (LWA) of the data block to
| be transferred.
h. Word 4 is not currently used and should be zero. It is reserved
for future use. -
2. ADT Table for Multiple AQ Devices. See figure 4-6.
The ADT table for this type consists of 1*4+4 words, where I is the
number of multiple AQ devices, up to 32, on one microinterrupt:
a. In word 1, bit 15, bits 11 thru 13, and bit 0 must be zero.
b. In word l, bits 14 and 1 must be one.
с. In word 1, bits 7 thru 10 contain the equipment number of the
device. | |
60472800 C a 4-33
H
©
=
Q
м
Qu
15 14 13 12 11 10 9 8 7 6 5 4 3 2
0 1 0 0 0 | Equip Max Station 1 0 1
T15|T1a|T13|T12|T11|T10|70 [Ts |T7 |T6 |T5 |Ta |T3 [T2 |T1 | To 2
T31|T30|T29| T28|T27|T26|T25|T24|T23| To2|T21 | To20o|Ti9| T18|T17|T16 3
Not used |
0 O 1W/C| 0 |R/W Equip Station Director 5
FWA-1 and CWA 6
LWA 7
Not used 8
e e
e | e
o e
0 | otw/c|o |R/W Equip Station Director I*4+1
FWA-1 and CWA 1*4+2
LWA T*4+3
Not used | I*4+4
Figure 4-6. ADT Table for Multiple AQ Devices
d. In word 1, bits 2 thru 6 contain the maximum station (or channel)
number. This is equivalent to the number of multiple AQ devices,
minus one, on a microinterrupt. Note that the station numbers
must be contiguous (i.e., 0 to I-1).
e. Words 2 and 3 contain termination bits for the 32 devices.
Initially, they must be all zero. When a macrointerrupt occurs,
one or more of these bits are set to one to indicate that one or
more ADT operations have terminated. Thus, if T5 is 1, the
seventh device has terminated its ADT operation. Note that after
receipt, the bit should be cleared via an instruction that locks
memory (e.g., a CLF instruction).
f. Word 4 is not currently used and should be zero. It is reserved
for future use. |
g. Words 5, 6, 7, and 8 (and also words I*4+1, I*4+2, I*4+3, and
I*4+4, where 2<I <32) are defined the same as a single AQ device
except bit 14 of the first word I*4+1 must be a one. (Refer to
ADT Table for a Single AQ Device). |
NOTE
The Standard 2550-2 does not contain any multiple AQ
devices.
4-34 60472800 C
3. ADT Table for the Clock
15 14 13 12 11 10 | 7 6 0 Word
1 0 0 | 0 0 Equip Station Director 1
Clock Counter 2
Clock Limit 3
Not used | 4
The ADT table for this type consists of four words:
a. In word 1, bit 15 must be one.
b. In word 1, bits 11 through 14 must be zero.
c. In word 1, bits 7 through 10 contain the equipment of the clock,
which is always one.
d. In word 1, bits 0 through 6 contain the station/director bits of
the clock, which is always equal to 7016. (Thus, word 1 should
be 80F016-) |
e. Word 2 is initially set to zero. Whenever the clock has been
enabled, the clock counter is incremented every 3-1/3 milliseconds.
£. Word 3 contains the clock limit, which is interpreted as a
multiple of 3-1/2 milliseconds. When the clock counter equals the
clock limit and the macroclock interrupt is enabled, the
macroclock interrupt occurs. Thus, if the clock limit is five,
the clock interrupt is 16-2/3 milliseconds, or 60 times a second.
To continue the process, the clock counter should be reset to
zero, or the limit counter should be incremented by its original
value (e.g., five). In the later method, the clock counter can
function as an elapsed time counter. Note that if the macroclock
interrupt is not answered, the clock limit. continues to be
incremented.
g. Word 4 is not currently used and should be zero. It is reserved
| for future use.
MACROINSTRUCTION TIMING
The execution times for each macroinstruction operation are listed in table
4-4,
MICROPROGRAMMING USAGE
In the NPU, two microprograms are co-resident. A 1700 emulator resides in
read-only memory and directs the, execution of macrocode 1700-type
instructions from main memory. Special microcode, loaded in read/write
memory, supports portions of the multiplex subsystem and other time-critical
functions. Communication between the routine is via internal interrupts.
60472800 C | 4-35
TABLE 4-4. MACROINSTRUCTION EXECUTION TIMES
| Execution
Mnemonic Definition (Microsec) Op Code
See Note |
AAB Transfer Arithmetic Sum A, Q, M 1.2 - 2.2 0 8 3 8-F
AAM Transfer Arithmetic Sum A, M 1.2 - 2.2 0 8 2 -
AAQ Transfer Arithmetic Sum A, Q 1.1 - 1.5 0 8 3 0-7
ADD ADD A 1.6 8 * A A
ADO ADD О 1.6 F|*| ATA
ALS A Left Shift 1.6+0.06N 10 IF | C/D | O-F
| | ilo 4 * *
AMr AND Memory A Ti =~ A
AND AND with A 1.5 A |* A A
0 4 * *
ANr AND Register A TO A A
a 0 4 * *
ARr Add Register 8 0 A A
ARS A Right Shift 1.6+0.06N |0 | F | 4/5 | O-F
ASC Accumulator Scale 0 B 0 A
CAB Transfer Complement Logical 1.7 2.2 0 8 F 8-F
Product A, Q + M
CAM Transfer Complement Logical 1.7 2.2 0 8 E 8-F
Product A, M
CAQ Transfer Complement Logical 1.1 1.5 0 8 F 0-7
Product A, Q
CBP Clear Breakpoint Interrupt 0 B 0 7
CE h t 1 0 2 - -
C Compare Character Equa. | 5 5 A A
. 0 5 + 6
CLF Clear Field IF E A A
CLR Clear to Zero | 1.1 1.5 0 8 4 0-7
CPB Clear Program Protect 1.6 0 7 ‚0 0
> 1 | LO 4 * *
CrE Compare. Register Equa E | 0 A A
DMI Define Microinterrupt 1.3 0 |B | O 6
2,4,6,8,
DrP Decrement and Repeat 0 6 | A,C,S,E
DVI Divide Integer 9.4 10.6 |3 * A A
EAB Transfer Exclusive OR A, Q, M 1.7- 2.2 Jo | 8 7 8-
EAM Transfer Exclusive OR A, M 1. 2.2 Jo | 8 6 8-
EAQ Transfer Exclusive OR A, Q 1. 2.2 (10 18 7 0-7
4-36 60472800
TABLE 4-4. MACROINSTRUCTION EXECUTION TIMES (Contd)
Execution |
Mnemonic Definition (Microsec) Op Code
See Note
EIN Enable Interrupt 1.4 0 4 0 0
EMS Execute Microsequence 0 B r,o 2
ENA Enter A 0.9 0 A A A
ENQ Enter O 0.9 0 C A A
EOR Exclusive OR with A 1.5 B * A A
EXI Exit Interrupt State 1.9 0 | E A A
GPE Generate Character Parity Even 0 B 0 8
GPO Generate Character Parity 0dd 0 B 0 9
IIN Inhibit Interrupt 1.4 0 5 0 0
INA Increase A 0. 0 9 A A
INP Input to A .8 - 9.9 0 2 А А
INQ Increase Q 0.9 0 D A A
IMP Jump .1 1 |* | A A
LAB Transfer Logical Product A, Q+M „7 = 2. 0 8 B -
LAM Transfer Logical Product A, M ‚1 - 1. 0 8 А 8-
ГАО Transfer Logical Product A, © 1.1 - 1.5 0 8 B -7
| | 0 4 * *
LCA Load Character to A { С > ZA A
LDA Load A 1.5 lc} + A A
LDQ Load Q 1.5 E * A A
LFA Load Field { 9 2. = 170
LLB Load Lower Unprotected Bounds 0 B 4,0 1
LLS Long Left Shift 2.2+0.06N | 0 | F | E/F |0-F
LMM Load Micromemory 0 B 0 1
LRG Load Register о | в 2
. 0 4 * *
LRr Load Register { с 0 A A
LRS Load Right Shift 2.2+0.06N | 0 | F | 6/7 |0-F
LUB Load Upper Unprotected Bounds 0 B r,o 0
MUI Multiply Integer 5.4 - 7-4 2 * A a
NOP No operation 1.1 0 | F | 0/1 | O-F
OMr OR Memory { 0 4 - ы
D | 1 A A
60472800 C 4-37
TABLE 4-4,
MACROINSTRUCTION EXECUTION TIMES (Contd)
Execution
Mnemonic Definition (Microsec) Op Code
See Note
. 0 4 * *
ORr OR register | D 1 A A
OUT Output from A 2.4 - 9.5 0 3 A
QLS Q Left Shift 1.9+0.06N 0 F A/B 0-F
ORS O Right Shift 1.9+0.06N 0 F 2/3 0-F
RAO Replace Add 1 in Storage 1.9 D * A A
RTJ Return Jump 1.6 5 | * A A
o _ 1.1
SAM Skip if A = - 1-2. 0 1 3 S
oa 1.1
SAN Skip if A # 0 1.4% 0 1 1 S
o 1.1
SAP Skip if À = + {1 Lal 0 1 2 S
SAZ Skip if A = +0 a | о |1 | © 6
1.4*
e 0 4 * *
SBr Subtract Register { 5 O x A
, rom à. То [а | * | «
SCA Store character from A С 3 A A
| . 0 5 * 7/F
SEF Set Field { * x = £
SET Set to l's 1.1 - 1.5 0 8 8 0-7
| 0 5 * 5/D
SFA Store Field 4 = = = =
a | 1.1 о | 5 * 3/B
SFN Skip if Field Not Zero da { = + = A
« . 1.1 0 5 * 2/A
SFZ Skip if Field Zero {1-14 { к, к, A А
SIO Set/Sample Output or Input | | 0 B 0 4
SJE brouti i 0 4 A ы
Su routine Jump Exit { 5 0 A A
SJ ‘Subroutine J о |< - -
r Su routine Jump { 5 О А x
1.3
|515 Select Stop 1.54% О 0 0 0
SNF Skip on No Program Protect Fault es 0 1 B S
О 1.1
SNO Skip on No Overflow 1.4% 0 1 F S
4-38 60472800 C
TABLE 4-4. MACROINSTRUCTION EXECUTION TIMES (Contd)
Execution
Mnemonic Definition (Microsec) Op Code
See Note
SNP Skip on No Storage Parity Error {1-14 0 1 D S
| 1.1
SOV Skip on Overflow 1.4% 0 1 A 5
SPA Store A, Parity to A 2.1 7 | * A
SPB Set Program Protect 1.6 6 0 0
SPE Skip on Storage Parity Error ae) 0 1 С 5
. 1.1
SPF Skip on Program Protect Fault 1.4% 0 1 E S
SPS Sample Position Status 0 B 0 5
som | skip if 0 = - tr oil 7 6
a 1.1
SON Skip if Q # +0 1.4% 5 5
_ © _ 1.1 |
SOP Skip if Q = + 1 ix | o lil 6 s
a 1.1 | |
502 Skip if Q = +0 1.4% 0 1 4 S
SRG Store Registers 0 B 0 3
srM | Skip if Register Negative a } o Jo] 37 | s
. . . 1.1 ‘| 1,5
SrN Skip if Register Non Zero E. } 0 0 9,D S
à . CL 1.1 2,6
SrP Skip if Register Positive free 0 0 A,E S
a 0 4 * *
SRr Store Registers | С 1 A A
a . 1.1 0,4
Srz Skip if Register Zero {1.4 0 0 8,C S
STA Store A 1.6 6 | * A A
STO Store Q 1.6 4 | * A A
SUB Subtract 1.6 9 | * A A
SWN Skip if Switch Not Set aa) 0 1 9 S
a | 1.1 -
SWS Skip if Switch Set 1.4 } 0 1 8 S
TCA Transfer Complement A 1.1 - 1.5 0 8 6 0-7
60472800 C 4-39
TABLE 4-4. MACROINSTRUCTION EXECUTION TIMES (Contd)
Execution
Mnemonic Definition (Microsec) | Op Code
See Note
TCB Transfer Complement Q + M | 1.2 - 1.7 0 | 8 5 8-F
TCM Transfer Complement M | 1.2 - 1.7 0 8 4 8-F
TCQ Transfer compiement Q l.1 - 1.5 0 8 5 0-7
TRA Transfer A - 1.1 - 1.5 0 8 A 0-7
TRB Transfer Q + M 1.2 - 1.7 0 8 9 8-F
ТЕМ Transfer M - 1.2 - 1.7 0 8 8 8-F
тво Transfer Q 1.1 - 1.5 0 8 9 0-7
XFr © Transfer Register’ 0 7 1-7,0,1-7
*If skip is taken
**Tf selective stop set
- NOTE: Add 550 ns (approx) per memory reference for each instruction:
CPU = 750 ns Read CPU/Exp Avg = 425 ns
850 ns Write Setup +155 ns
Avg = 800 ns 580 ns
Exp = 1145 ns Read
1305 ns Write
Avg = 1225 ns
MICROINSTRUCTION FORMATS
Microinstruction formats consist of 32-bit instruction words which are
divided into five main sections numbered left to right as bits 0 to 31. The
total microinstruction word appears as follows:
0 1 2 yy 15 16 18 19 23 24 31
M ALU Control T S e |
| x |
#4
Bits Function
0,1 Mode (M) field specifies format of S and C field and
seguencing mode to obtain next microinstruction pair.
2-15 - ALU control field specifies ALU operation, sources of
operands, and destination of result of operation.
16-18 Test (T) field specifies method of selecting which
microinstruction of next microinstruction pair to execute.
4-40 | 60472800 С
19-23 Special (S) field specifies subformat selection and special
| operation. |
24-31 Constant (C) or suboperation field specifies constants, or
other codes. |
The M field specifies one of three addressing modes to be used to obtain the
next microinstruction pair from micromemory and specifies the format to be
used in interpreting bits 19 through 31 of the microinstruction as follows:
Addressing Format for bits
M_ Mode 19 to 31
00 Return Format 1
01 Sequential Format 1
10 | Jump | Format 2
11 Sequential Format 3
Figure 4-7 shows all microinstruction formats. Note that format 1 and format
2 microinstructions have two subformats, which are selected by the value of
bit 19 (SF).
ALU CONTROL
À.
Bit 0 12 6 7 8 9 10 12 13 . 15/16 18
a " y ="
| M F A B | D T | |
| =. = ==
| | | : | |
| | ! ; !
| 1
| A | |
shift and | в | г > SC | |
Scale | | |
| | ` |
PP —— —]][—l]ln— o A |
| Г y
| y 19 20 2324 25 31
Г DE —]
TT] |
т ' |
0 0 R 0 5 T'" © Format
1
L
“EN : a Format
5 | K S | C | 3
Figure 4-7, Microinstruction Formats
1 lo J | 0 s NMA | Format
o — 2
1 0 J | 1 PAGE NMA | |
|3]
60472800 С | | | 4-41
The ALU control fields specify the sources of two operands on which an
arithmetic, logical shift, or scale operation is to be performed and specify
the destination of the result of the operation. For arithmetic and logical
operations, the ALU control fields consist of the ALU function (F), A source
(A), B source (B), and destination (D) fields, shown as follows:
Bit 2 6 7 9 10 12 13 15
[F [ A |B | D J
For shift and scale operations, the A and B fields are interpreted as follows:
Bit 2 6 7 8 9 10 11 12 13 15
S C
The F field specifies shift or scale operation. Bits 7 and 8 specify right
or left shifting. Bit 9 specifies whether the A register alone or the A and
Q registers together are to be shifted or scaled. Bit 10 is not used, and
bits 11 and 12 specify the shift control code. The D field contains a
no-operation code for shift and scale operations.
The T field is the conditional branch of the microinstruction and specifies
which microinstruction, upper or lower, of the next microinstruction pair to
execute. The test can be based on the result of the ALU operation of the
current microinstruction or on some other condition.
The codings in the S and C fields depend upon the contents of the M field.
The S and C fields are coded in three formats. Format 1 is specified when
the M field contains 00 (return mode) or 01 (sequential mode) as follows:
Bit 19 20 23 24 25 31
| | T |
E = |
Format 1
Bit 19 20 23 24 25 31
* T ||)
| 1 s/c т C
*If SM207 is set to a 1, the normal S field commands are disabled with С"
codes TMA/j, TMAK/j, GITMAK/j, GITMAK/xt, and TR/j.
The S field specifies operations such as main memory read or write |
operations; alternate codings to be used in the A, B, and D fields; etc. The
T/T' bit specifies that the code in the T field is to be interpreted as the
normal T code (T/T'=0) or as the alternate T' code (T/T'=1). Subformat
select bit 19 determines whether bits 25 through 31 are to be interpreted as
C' codes or as C" codes. The C' code can contain the constant for driving
the bit generator, additional information to control the main memory read or
write, or other operation. The C" codes are associated with transforms.
4-42 000 60472800 C
Format 2 is specified when the M field contains 10 (jump mode) as follows:
Bit 19 20 23 24 31
Por = E 7
Format 2 | |
Bit 19 20 23 24 31
| 1 PAGE NMA |
If a jump is specified to a microinstruction pair within the same micro-
instruction page, the subformat select bit is 0; bits 20 to 23 contain a
special operation code as in format 1. Bits 24 through 31 contain the
micromemory address of the next microinstruction address of the next
microinstruction pair. The subformat select bit is 1 when a jump is
specified to a different micromemory page; bits 20 through 31 contain the
complete micromemory address of the next microinstruction pair.
Format 3 is specified when the M field is 11 (sequential mode), as follows:
Bit 19 20 23 24 al
| wx 3 с |
This format allows one special operation to be performed as specified by the
S code and also causes the 8 bits of the C field to be transferred to the N
register (bit 19 15 1) or to the K register (bit 19 is 0).
Format 3
DETAILED MICROINSTRUCTION CODING
The following text describes the fields of the microinstruction words.
M Field (Bits O and 1)
The field defines the major operation taking place in the microinstruction
and specifies the type of sequencing to be used to obtain the next
instruction pair. The operations specified in the M field are listed in
table 4-5. | | ВЕ
—F Field (Bits 2 through 6)
The F field specifies the logical or arithmetic operation to be performed by
the ALU, or the shift or scale operations performed with the A and Q
registers.
The split adder option allows the main ALU to be split into two independent
adders. This split is activated by setting the adder split flag in the SM
register. The split blocks the carry between the two portions of the adder.
The upper portion of the adder always functions as a two's complement adder;
the lower portion can function as a one's complement or as a two's complement
adder, depending upon the state of the one's complement SM register flag
60472800 C 4-43
(32-bit processor only). In one's complement mode, the carryout of the lower
portion is used as the end-around carry bit. In two's complement mode, both
portions of the adder act as independent two's complement adders. The split
adder has no effect on logical operations because no carry is involved in
these operations.
Logical Operations
The logical operations perform bit-by-bit combinations of the A input and the
B input for delivery to the destination. The logical operations are
described in table 4-6.
Arthmetic Operations
The arithmetic operations (table 4-7) operate on single-precision (using the
main ALU).
The second option allows capture of the overflow condition in the SM register
(indicated by a T in the instruction mnemonic). If this is indicated, the
overflow test is performed by checking the sign of the two inputs to the ALU
and by setting a status/mode bit if the result is inconsistent. The SM
overflow bit is set to 1 when the overflow occurs; it must be set to 0 by a
microinstruction which sets the SM bit to 0. Two other optional SM bits
allow checking for binary or decimal arithmetic overflow.
TABLE 4-5. M FIELD OPERATIONS
M Code Mnemonic Operation
00 R Select next microinstruction pair from address
| contained in RTJ register. Use format 1 for special
operations.
ol S Select next microinstruction pair in current page from
address contained in MAC (normally next sequential
pair, unless suppressed by T field coding). Use
format 1 for special operations.
10 J A jump or page jump. Select next microinstruction
pair from address specified by bits 24 to 31 of this
microinstruction. Address is in current MM page if
bit 19 is 0 or from page specified in bits 20 through
23 if bit 19 is 1. Use format 2 for special
operations.
11 S Transfer bits 24 through 31 of this microinstruction
to N or K register as specified by bit 19 of this
microinstruction. “N register is specified if bit 19
is 1, and K register is specified if bit 19 is 0.
Select next microinstruction pair in current page from
address contained in MAC (normally next sequential
microinstruction pair). Use format 3 for special
operations. |
4-44 | | 60472800 С
TABLE 4-6. LOGICAL OPERATIONS
A input = 0 O 1 1, B input = 0 1 0 1
F Code Mnemonic Bit Result
01100 ZERO 0000
01110 A B 0001
01101 A -B 0010
01111 A 0011
01000 | -А В 0 100
01010 B 0101
01001 EOR 0110
01011 A+B 0111
00100 -A -B 1000
00110 -EOR 1 001
00101 -B 1010
00111 A+-B 1011
00000 -А 1100
00010 -A+B 1101
00001 -A+-B 1110
00011 ONE 1111
Shift Operations
The shift operations in the F field specify a shift of the A register or the
A/Q register of the main MP organization only; no shift is possible in the
double-precision registers from this command. The ALU is not used to perform
the shift but performs some operation based on its decoding of the F field
(which should be considered as unknown). The destination receives this
meaningless output unless a NOP is chosen for the destination of the D field.
The type of shift is determined by the coding in bits 7 through 12 of the
microinstruction, and the amount of the shift is determined by the number
contained in the N register. The operation examines the register, and, if it
is zero, the shift operation is terminated and the next microinstruction is
executed. The T field codes that can be used with a shift are U, L, KZU,
INTU, OVFL, K7L, and BTU. Other T codes cannot be used. |
If the N register is not zero, a shift of one bit position is taken as
specified, N is decremented by one, and the test for zero is repeated as
above.
“The shift conditions are:
e Shift A - Shift the A register only.
e Shift AQ - Shift the combined A and Q register. The Q register is
considered to be the least significant bits of the combined A/Q
register.
e Shift external (transform).
e Shift left or right.
60472800 C
e Enter 0 - Enter a zero in the vacated bit position at the end of the
register.
e Enter 1 - Enter a one in the vacated bit position at the end of the
register. |
e Extend sign - Extend the sign (for a right shift only).
e End-around carry - Enter the bit coming off the end of the register
into the vacated one position at the other end.
All shifts are performed with an F code of 11110. The type of shift is
determined by bits 7 through 12 of the microinstruction. The shifts are
defined in table 4-8.
TABLE 4-7.
ARITHMETIC OPERATIONS
Appli-
cable
F Code Notes Mnemonic Operation
10110 SUB Subtract B input from A input.
11000 ADD Add A and B inputs.
10101 SUBT Subtract with an overflow test.
11001 ADDT Add with an overflow test.
10110 1,3 SUB- Perform A-B-1. See applicable notes.
2,3 SUB-C A-B with force carry in. See applicable notes.
11010 3 ADD+ Perform A + B with force carry in. See
applicable notes.
10111 1,3 SUB-T Perform SUB- with an overflow test. Set
applicable notes.
2,3 SUB-TC Perform SUB-C with an overflow test. See
applicable notes. |
11011 3 ADD+T Perform ADD+ with an overflow test. See
applicable notes.
NOTES:
1. With this F code specified and when the system is in two's complement
mode,
this is the resultant arithmetic operation that occurs.
2. With this F code specified and when the system is in one's complement
mode, this is the resultant arithmetic operation that occurs.
3. If split adder mode is selected, this operation is performed on the
upper adder without a force carry.
60472800 C
TABLE 4-8. SHIFT OPERATIONS
Bit Code
7 89 11 12 Mnemonic | Operations
100 | 00 AROE A is right shifted (N) bits, with 0 entered as
most significant bit.
100 01 ARSE A is right shifted (N) bits, with sign extension.
100 10 AREA A is right shifted (N) bits, with end-around
carry.
0.10 00 — ALOE A is left shifted (N) bits, with 0 entered as
least significant bit.
010 } 01 ALLE A is left shifted (N) bits, with 1 entered as
| least significant bit. |
010 10 ALEA "A is left shifted (N) bits, with end-around
| | carry. | |
101 | 00 AQROE A/Q is right shifted (N) bits, with 0 entered as
most significant bit in A. |
101 01 AQRSE A/Q is right shifted (N) bits, with sign
| extension.
101 | 10 AQREA A/Q is right shifted (N) bits, with end-around
carry. |
011 00 AQLOE | A/Q is left shifted (N) bits, with 0 entered at
least significant bit in Q. ) |
011 | 10 AQLEA | A/Q is left shifted (N) bits, with end-around
| carry.
Scale Operations
The scale operations are similar to the shift operations but the stopping of
the shift is conditioned on bits 0 and 1 of A not being equal. (The scale
point is normally between bits 0 and 1 of the A register. A design option
allows the scale point to be specified between different bits in the A
register if necessary for efficient floating-point emulation.) The maximum
number of bits to scale is contained in the N register, and, on completion of
the scale, N is decremented by the number of shifts which were necessary to
scale the number. |
The scale operation is performed as follows:
l. Examine N; if it is zero, exit the microinstruction.
2. Examine bits 0 and 1 of the A register; if they differ, exit the
microinstruction. ©
60472800 C 4-47
3. Shift the A or A/Q register left by one bit position as specified in
the instruction.
4, Decrement the N register by one count and go to step 2.
NOTE
If the number that is being scaled is all zeros or all
ones (i.e., the number cannot be scaled), then when N=$FE
(after passing through N+0), the scale operation is
terminated. In order to avoid exiting the micro-
instruction before the scale operation is actually
completed, (N) should be at least equal to the number of
bits in the word to be scaled.
The scale operation is coded the same in bits 7 through 12 of the
microinstruction and allows the same left shift options as the shift
command. The same comments on exiting the shift and the usable T field codes
apply to the scale operation.
All scale operations are performed with an F code of 11111. The type of
shift for the scale is determined by bits 7 through 12 of the instruction.
The scales are given in table 4-9.
A Field (Bits 7.through 9)
The field specifies the input to S1 and thus to the A side of the ALU. The
eight A codes are expanded by eight A' codes by placing 1010 or O111 in the S
field.
The eight A inputs to S1 and to the A side of the ALU are indicated when the
S field is not 0111 or 1010; the eight A codes specify inputs from the files,
the registers, or main memory, according to table 4-10.
The eight A' inputs to S1 and to the A side of the ALU are indicated if the S
field is 0111 or 1010. The A' codes specify input from the SM registers or
Mask register. The A' codes are given in table 4-11.
TABLE 4-9. SCALE OPERATIONS
Bit Code
789 |11 12 | Mnemonic | Operations
O0 10 0 0 . SLOE A is scaled left, with 0 entered as least
| | | significant bit.
010 01 SLLE A is scaled left, with 1 entered as least
| significant bit.
0 10 10 SLEA A is scaled left, with end-around carry.
011 00 SDLOE A/Q is scaled left, with 0 entered as least
| significant bit in Q.
011 10 SDLEA A/Q is scaled left, with end-around carry.
4-48 | | 60472800 C
TABLE 4-10. A INPUT OPERATIONS
A Code
Mnemonic
Operation
0007
001
010
011
100
101
1101
111
F2
Fl
MEM
Use contents of file 2 register as A source
input. Current value of N register is used to
address register file 2. If value of N is
changed in current microinstruction, its initial
value is used to reference file register.
Use contents of P register as A source.
Use contents of I register as source.
Use contents of X register as source.
Use contents of A register as source.
>» >» » »
Use contents of F register as source.
Use contents of file 1 register (when it is
furnished) or external source as A source,
Current value of K register is used to address
register file 1. If value of K is changed in
current microinstruction, initial value of K is
used to reference file register. Note that file
l is available only as an option. -
Obtain data read from main memory and use it as
A source. If main memory command was not given
in the preceding microinstruction, all ones are
input to A source if B' source is not selected.
Restriction: This command is restricted to a
microinstruction with type A, B, or C execution
time.
RESTRICTION:
modified by a C'
instruction.
Value of addressing register (N or K) cannot have been
increment or decrement command in preceding micro-
In addition, whichever file is read during the current
microinstruction, this same file cannot have been written in the
preceding microinstruction. |
60472800 C
TABLE 4-11. A' INPUT OPERATIONS
A' Code Mnemonic Operation
000 SM1 | Use contents of SM register 1 as A source.
001 Ml Use contents of interrupt mask register 1 as A
source.
010 , 5M2 Use contents of SM register 2 as A source.
où M2 Use contents of interrupt mask register 2 as A
source input.
100 A*R8 | Use contents of double-precision A* register,
shifted right eight bits with end-around carry,
as A source. A* register remains unshifted.
101 A* Use contents of double-precision A* register as
A source.
110 x * Use contents of double-precision X* register as
A source.
111 o* Use contents of double-precision Q* register as
A source.
NOTE: Double-precision hardware has been replaced by the Cyclic Encoder
algorithm card and thus the starred instructions refer to the
Cyclic Encoder.
B Field (Bits 10 through 12)
The B field specifies the input to S2 and thus to the B side of the ALU. The
11 possible B codes are expanded by the seven B' codes when the S field
contains 1000. The N and K codes are controlled by bits 28 and 29 from the C
field. |
The eleven B inputs to S2 and thus to the В side of the ALU are indicated if
the S field is not 1000. Code 001 of the B field is expanded by the use of
‘bits 28 and 29 of the microinstruction for enabling the № ог К register to
S2. This use of bits 28 and 29 is independent of the other use of the C
field, and thus, by judicious use of commands in the C field, the input for
the N and K can be used in conjunction with commands or constants in the C
field. The codes for B inputs are given in table 4-12.
The B' inputs are specified in the B field when the S field contains 1000.
The codes and actions are given in table 4-13.
4-50 - | 60472800 С
TABLE 4-12.
B CODES
B Codes
28 29
Mnemonic
Operation
000"
001
001"
001
010
011
100
101
110
111
F2
Zero
N, K
BG
Fl
MEM
Use contents of file 2 register as B
source. Value of N register, before
instruction is executed, is used to address
register file 2. If value of N is changed
in current microinstruction its initial
value is used to reference file register,
B source is all zeros.
Use contents of N register as B source.
Since N is an 8-bit register, this source
uses N as the upper 8 bits and zeros as the
lower bits.
Use contents of N and K registers as B
source. These registers are combined, with
N register as the upper 8 bits of source
and K as the lower 8 bits.
Use contents of BG register as B source.
This register has only one bit set to 1,
and position of bit in BG register is
specified either on value in the N register
or by number in C field, depending on state
of controlling SM register bit.
Use contents of X register as B source.
Use contents of Q register as B source.
Use contents of F register as B source.
Similar to F2, but uses the contents of
file 1 register (when it is furnished)
addressed by (K) as B source. Note that
file 1 is available only as an option.
Obtains data read from main memory and uses
it as B source. If main memory Read
command was not given in the preceding
microinstruction, all one's are input to B
source if A' source not selected. This
command is restricted to a microinstruction
with type A, B, or C execution time.
Value of addressing register (N or K) cannot have been modified by a C'
increment or decrement command in preceding microinstruction. In
addition, whichever file is read during the current microinstruction,
this same file cannot have been written in the preceding microinstruction.
"In a 32-bit processor, the 16 most significant bits are always zeros. It
is the 16 least significant bits of the 32-bit B source that are
controlled with these codes. |
60472800 C
TABLE 4-13. B' CODES
B' Code Mnemonic Operation
000 OPEN
001 CRTJ Transfer the complement of the RTJ register to
the twelve LSB's of S2. Transfer 1's to the
four most significant bits of S2.
010 INRD Input data/status from I/O channel.
011 INRS Input to S2 I/O response signals.
100 MMU Transfer upper 16 bits of data from micromemory
to X register in 16-bit MP; 32-bit MP transfer
total 32-bit word. F field must make a
reference to B source. Address is specified by
transform or NK. D field must be an NOP.
101 | MMI, Same as above, but takes lower 16 bits of data
110 INTA Use contents of interrupt address encoder as B
Or source. The output of this encoder represents
111 the complement of the interrupt address of the
highest priority interrupt line active having
its corresponding mask bit set.
Restrictions: An INTU test command must be
given in the preceding microinstruction.
"This code is nonoperative in a 32-bit processor.
D Field (Bits 13 through 15)
The D field specifies the destination of information from the main organ- =
ization of the MP. There are four sources of this information as follows:
e An optionally shifted ALU output. This shifting occurs in the 53
shift network that connects the ALU output to the P, A, F, X, or Q
registers.
e The output of the ALU
e The A source
e The B source
All D destinations except the I register are optionally shiftable by S3 when
specified by a code in the C field or by the L8EA command in the S field, if
the alternate codings, D' or DD", are not specified. The I destination
differs from the others in that the output of the A source is the input to
the I register. The codes and their operations are given in table 4-14.
4-52 | | - | 60472800 С
TABLE 4-14. D CODE TRANSFERS
D Code Mnemonic Operation
000 NOP Do not transfer data to any destination.
001 P transfer output of S3 to P, AB!"
010 I Transfer output of S1 to I, AB
011 Q Transfer output of S3 to Q, AB
100 Fl Mpransfer output of S3 to F register, AB, and write
this data in file 1 (when it is furnished) at
address specified by K at completion of this
instruction fit
101 A Transfer output of S3 to A, АВТО
110 X Transfer output of S3 to X, АВ!"
111 F
Transfer output of S3 to F, Ag!
'If a D field command to load the AB is issued in the next micro-
instruction following the microinstruction with this command, the
transfer AB is-inhibited. |
The writing of data into the file 1 register takes place during the
first part of the next microinstruction and takes advantage of the
updated value of K from this microinstruction. Also, the next
microinstruction must not specify a read of file 1.
“TAB is the main memory address buffer register.
60472800 C
The D' destinations are specified by the D field if the S field is set to
+ 1001 or 1010. The codes and action are given in table 4-15. |
The D" destinations specified by the D field if the S field is set to 1011.
These destinations transfer data to the double-precision logic from S1. The
codes and actions are given in table 4-16.
The DD" option allows the performance of an operation on A, X, or F; this
changes the register but keeps a copy of the original register in a double-
precision register. This is another way of getting data to the double-
precision registers. The DD" option is specified when the S field contains
0001. Table 4-17 lists the DD" codes and their operations.
TABLE 4-15. D' CODE TRANSFERS
D' Code Mnemonic | Operation
000 IOD Transfer output of S3 to I/O data register.
001 IOA Transfer output of S3 via the I/O data register
to I/0 address register. Destroys contents of
I/0 data register.
010 MMU | Transfer output of S2 to upper 16 bits of
micromemory in 16-bit MP, or transfer output of
S2 to 32-bit word in micromemory in 32-bit MP.
011 MML Transfer output of S2 to lower 16 bits of
| micromemory location in 16 bit MP, or transfer
output of S2 to 32-bit word in micromemory in
32-bit MP.
100 M1 Transfer output of ALU to mask register 1.
101 SM1 Transfer output of ALU to mask register 1.
110 — M2 Transfer output of ALU to mask register 2.
111 SM2 Transfer output of ALU to SM register 2.
Note: Outputs to the mask and SM registers are direct from the ALU and
are not shiftable. |
4-54 60472800 С
TABLE 4-16. D" CODE TRANSFERS
D" Code Mnemonic Operation
000 NOP Do not transfer data to any destination.
001 A*LHW Transfer output of S1 to A* register, shifted
left one-half word, with end-around carry.
010 X*LHW Transfer output of S1 to X* register, shifted
left one-half word, with end-around carry.
011 Q*LHW Transfer output of S1 to Q* register, shifted
left one-half word, with end-around carry.
100 NOP Do not transfer data to any destination.
101 A* | Transfer output of S1 to A* register.
110 — X* | Transfer output of Sl to X* register.
111 Q* Transfer output of 51 to Q* register.
TABLE 4-17. DD" CODES
DD" Code | Mnemonic | | Operation
101 AA* Transfer output of S3 to A register, and transfer
| output of S1 to A* register.
110 XX * Transfer output of S3 to X register, and transfer
output of S1 to X* register.
111 FQ* Transfer output of S3 to F register, and transfer
output of Sl to Q* register.
T Field (Bits 16 through 18)
The purpose of the T field is to select the upper or lower microinstruction
of the next microinstruction pair to execute. The selection of the next
microinstruction can be a conditional selection or an unconditional
‘selection, depending on the T field code. This field is available to all
addressing modes in addition to I/O operations. A conditional selection can
test the ALU output, the value of certain registers, certain internal
conditions such as interrupts, and particular bits wired to the transform
card. The only exception to these uses of the T field is when micromemory
data is being read or written; in these cases, the T field is used as part of
the micromemory data reference address and the upper instruction in the next
sequential microinstruction pair is always selected. |
60472800 C | | | 4-55
The T field codes consist of two groups, T codes and T' codes. Similarly to
the A, B, and D fields that are extended by using the S field, the T field is
always extended in the following sense. Bit 24 of format 1 microinstructions
is either zero or one if T or T', respectively, is specified. The T' codes
are available only for the return and sequential addressing modes (format
1). The T/T
codes select the upper or lower portion of the next
microinstruction pair as the next microinstruction to execute. The T codes
are listed in table 4-18; the T' codes are listed in table 4-19.
TABLE 4-18. T ADDRESSING MODES
T Code
Mnemonic
Operation
000
000
010
011
100
101
110
111
L
KZU
NZU
INTU .
NU
21
Execute lower microinstruction of this microinstruction
pair as next microinstruction. This operation
overrides M field addressing mode.
Execute upper microinstruction of next microinstruction
pair.
Execute lower microinstruction of next microinstruction
pair.
If initial contents of K register is zero, execute
upper microinstruction of next microinstruction pair;
otherwise, execute lower microinstruction of next
microinstruction pair. If decrement K command is
included in same microinstruction, K contains all ones
on satisfying zero test.
If initial contents of N register is zero, execute
upper microinstruction of next microinstruction pair;
otherwise, execute lower microinstruction of the next
microinstruction pair. If decrement N command is
included in same microinstruction, N contains all ones
on satisfying zero test. |
If there is an interrupt and its corresponding
interrupt mask bit is set, execute upper
microinstruction of next microinstruction pair;
otherwise execute lower microinstruction of next
microinstruction pair.
If sign bit of ALU output is negative on completion of
this microinstruction, execute upper microinstruction
of next microinstruction pair; otherwise, execute lower
microinstruction of next microinstruction pair.
If output of ALU is zero on completion of this
instruction, execute lower microinstruction of next
microinstruction pair; otherwise, execute upper
microinstruction of next microinstruction pair.
"These T-field commands cannot be used in microinstruction with a C~field
INCK or INCN command, respectively.
60472800 C
TABLE 4-19. T' ADDRESSING MODES
T' Code
Mnemonic
Operation
000
001
010
011
100
101
110
111
*L
LOL
K7L
OVFL
BTU
LO*L
COL
2*L
Execute lower microinstruction of this micro-
instruction pair. This operation overrides M field
addressing mode.
If, at start of this microinstruction, least signifi-
cant bit of Q is 1, execute lower microinstruction of
next microinstruction pair. Otherwise, execute upper
microinstruction of next microinstruction pair.
If the LSB of K register is set, execute lower of next
microinstruction pair. If clear, execute upper
microinstruction of next microinstruction pair.
If overflow exists, execute lower microinstruction of
next microinstruction pair; if not, execute upper
microinstruction of next microinstruction pair.
Bit test. Lower order 5 bits in C field of this
microinstruction specify a setting of bit test
selector. If bit at this position is 1, execute upper
microinstruction of next microinstruction pair;
otherwise, execute lower microinstruction of next
microinstruction pair. |
Bit test is general-purpose testing facility that
allows wiring any bit of organization available on
machine's backpanel to bit test selector. This wiring
is defined on transform card. |
If, at start of this microinstruction, least
significant bit of Q* is 1, execute lower
microinstruction of next microinstruction pair;
otherwise, execute upper microinstruction of next
microinstruction pair.
Carry-out lower. If, as result of arithmetic
operation, there is carry-out of ALU, execute lower
microinstruction of next microinstruction pair.
Otherwise, execute upper microinstruction of next
microinstruction pair.
This instruction allows a test for carry-out of ALU
during multiple-precision arithmetic.
Same as ZL except ALU* is tested.
60472800 C
Subformat Select Bit (SF)
Bit 19 (SF) is used to select either variations in format 1 and format 2
decoding or the choice of addressing the N or K register in format 3.
S Field (Bits 20 through 23)
The S field of the microinstruction is used to specify a special command
(including alternate codings in the A, B, and D fields), in addition to page
or constant information (as required by the code in the C field). The S
codes specify actions which take place at the same time as the ALU operation
specified in the F, A, B, and D fields. The codes and operations are given
in table 4-20.
C Field (Bits 24 through 31)
The C field is used to specify an additional special operation, an address
for a jump, or a constant for setting the K or N register. Bit 24 in format
1 specifies the T field interpretation. The codes for this field are listed
in table 4-21.
TABLE 4-20. 5 FIELD CODES
S Code Mnemonic Operation
000C NOP No operation for S field.
0001 DD Alternate D field coding, DD".
0010 RPT If N register is not zero, selection of next
microinstruction pair is inhibited and current
microinstruction pair is next microinstruction pair. N
register is decremented by one. Normal T field
selection applies. If N register is zero, normal next
microinstruction pair is used.
0011 READ Read main memory command. Read word from main memory
at address contained in the address buffer (AB).
Instruction execution is delayed until a resume is
received from memory acknowledging command. |
Restrictions: AB must be loaded in a previous
microinstruction (D field command). If D field command
reloading AB is issued in same microinstruction as Read
command, the new data is not loaded into AB until
completion of read portion of cycle. A Read command
can only be given in a microinstruction with type A, B,
C, or D execution time. Memory data must be input to
system in following microinstruction with type A, B, or
C execution time only.
4-58 60472800 C
TABLE 4-20,
S FIELD CODES ( Contd)
S Code
Mnemonic
Operation
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
WRITE
L8EA
F2WR
AP
BP
DP
APDP
DPP
GATEI
HALT
RTJ
CLRNP
fon completion of this microinstruction.
Write main memory. Transmit output of S3 to main
memory as data to be written at address contained in
address buffer (AB). Instruction execution is delayed
until a resume is received from memory acknowledging
command. Data is stored in memory at completion of
this instruction.
Restrictions: AB must be loaded in a previous micro-
instruction (D field command). If D field command
reloading AB is issued in same micro microinstruction
as Write command, the new data is not loaded into AB
until completion of Write portion of cycle.
Output of ALU via S3 is shifted left 8 bits, end-around.
Write data contained in F register into file 2 at
address specified by contents of N register at |
beginning of current microinstruction. Actual writing
takes place during first part of instruction.
Alternate A field coding, A'.
Alternate B field coding, B'.
Alternate D field coding, D'.
Alternate A and D field coding, A'D'.
Alternate D field coding, D".
Gate output of Sl to I register.
If halt bit of SM register is 1, stop operation of MP
When start
signal is received, continue with next micro-
instruction specified by addressing mode and T field.
If halt bit is 0, continue with microinstruction
sequencing.
Transfer address of next sequential microinstruction
pair to RTJ register. This is done regardless of
actual addressing mode used in this instruction.
[Clear N register and page register.
60472800 C
TABLE 4-21. C CODE ACTIONS
C' Code
Mnemonic
Operation
00xxxxx
0100000
0100001
01000107
0100100
0100101
0100111!
0101000
Ollxxxx
1000101
1001101
1000100
1001100
. 1000000
1001000
4-60
WRCH/0
WRCH/1
WRCH/2
RMW
WRHWO
WRHW1
WRPB
GATEIXT
INCK
INCN
DECK
DECN
CLRK
CLRN
The following special operations, for format 1 have a
zero in bit 19 (SF) to specify C' codes (bit 25
through 31). Bit 24 specifies the T field
interpretation. a
XXXXX is a constant for use in driving the bit
generator or in any other commands using lower 5 bits
of instruction for control.
Write 8-bit character specified from output of S3 at
memory address specified by output of AB. See Write
command in S field for details o£ operation and
restrictions. Character 0 is bit 0 through 7 (MSBs);
character 1 is bits 8 through 15, etc. Character is
not repositioned in Write command. |
Read modify write - Perform a read of information
from main memory in same manner as Read instruction
in S field. Memory system performs a read cycle and
lockup before performing write cycle. Memory must be
forced to complete write cycle by issuing Write
instruction, using same address, before it responds
to any other read operations.
Write bit 0 through 15 (MSBs) from output of S3 at
memory address specified by output of AB. Bits 16
through 31 in memory are unchanged. See Write
command in S field for details of operation and
restrictions.
Write bits 16 through 31 (LSBs) from output of S3 at
memory address specified by output of AB. Bits 0
through 15 in memory are unchanged. See Write
command in S field for details of operation and
restrictions.
Write protect bit - See protect system discussion
(Appendix A). |
General purpose strobe at T4 time. In MP17, this
signal is used to gate IXT on 1700 transform module.
Increment number contained in K register by one.
Increment number contained in N register by one.
Decrement number contained in K register by one.
| Decrement number contained in N register by one.
Clear K register.
Clear N register.
60472800 C
TABLE 4-21. C CODE ACTIONS (Contd)
C' Code
Mnemonic
Operation
101 xxxx
110xxxx
1110000"
1110011"
1110010"
1110100"
1110101"
1110110"
11101117
The following special operations, for format 1, have a one in bit 19 (SF)
to specify the C" codes (bits 25 through 31). Bit 24 specifies the T
field interpretation. See discussion of transforms and transform module.
SETF/j
CLRF/j
ROLXN
RORIE
ROROE
RLOE
RL1E
RROE
RR1E
хххх is value of j, from 0 to 15. Set SM register
flag j to l.
xxxx is value of j, from 0 to 15. Clear SM register
flag j to 0. |
Destination register (P, A, F, or X) and Q register
are considered as one double-length register with Q
register as lower-order bits. Combined register is
shifted left one bit position with complement of ALU]
sign bit entered into lowest bit position of Q
register.
Shift combined destination and Q register right one
bit, and enter 1 in sign position of destination
register. This command is used in multiply
iteration. |
Shift combined destination and Q register right one
bit, and enter 0 in sign position of destination
register. This command is used in multiply
iteration.
Shift destination register left one bit, entering 0
in lowest bit position of the register. This
operation cannot be performed when Q is destination
register.
Shift destination register left one bit, entering 1
in lowest bit position. This operation cannot be
per formed when Q is destination register.
Shift destination register right one bit, entering 0
in sign position of register. This operation cannot
be performed when Q is destination register. |
Shift destination register right one bit, entering 1
in sign position. This operation cannot be
per formed when Q is destination register.
C" Code
000xxxx'
60472800 C
TMA/J
transform selector setting Jj.
XXXX = j with value 0 through 15. Obtain next
microinstruction pair from address specified by MA
TABLE 4-21. C CODE ACTIONS (Contd)
C" Code
Mnemonic
Operation
tri
00lxxxx
tit
0100xxx
tit
0101xxx
tit
011xxxx
100xxxx
The following two codes are used if the optional program protect
logic is included.
101ххх
110xxxx
4-62
TMAK/j
GITMAK/j
GITMAK/xt
TK/ Jj
TN/3
SUB
SLB
ххх = j, 0 through 15. Obtain next instruction pair
from address specified by MA transform selector
setting j. Also, set K register to value specified
Бу К transform selector setting j.
Gate output of main memory to IXT register (on
transform module) and perform TMAK/j operation.
Note that j = xxx with values of 0 through 7. This
command must be executed in the microinstruction
following a Read command. This command is
applicable only if transform module is configured
with IXT register.
Gate output of main memory to IXT Register (on
transform module) and perform a transform of the
upper 16 bits of MIR and select one of eight
transforms of MA from the decoded and encoded
microinstruction loaded into IXT. This command must
be executed in the microinstruction following a Read
command. This command is applicable only if
configuration includes the required specialized
transform module hardware.
XXXX = j, with values from 0 through 15. Set К
register to value specified by K transform selector
setting j.
XXXX = Jj, from 0 through 15. Set N register to
value specified by N transform selector setting j. .
Set upper bounds - transfer output of S3 to upper
bounds register in main memory interface.
Set lower bounds - transfer output of S3 to lower
bounds register in main memory interface.
60472800 C
TABLE 4-21. C CODE ACTIONS (Contd)
C Code Mnemonic | Operation
The following format 3 codings are for setting the K and N register;
this format has the M field bits 0 and 1 set to 11, while bit 19
selects the register.
Value K = value | When microinstruction bit 19 is 0, transfer C field
value (bits 24 through 31) to K register and execute
next sequential microinstruction pair.
Value N =
value | When microinstruction bit 19 is 1, transfer C field
| value (bits 24 through 31) to N register and execute
next sequential microinstruction pair.
The following format 2 codings in the C field are used to perform
a jump, specified if the M field (bit 0 and 1) is 10.
Number Number Number is address of next instruction pair. If page
jump is required (bit 19 is 1), S field contains
page setting instead of S field code.
"NOTE: Commands applicable to 32-bit processor only.
"RESTRICTION: This operatin cannot be performed when S field command
| (L8BEA) is selected. |
TI RESTRICTION: If SM 207 is set to 1 , S field commands are disabled.
60472800 C — | : 4-63
MICROINSTRUCTION TIMING
The basic microinstruction execution time is 168 nanoseconds. Some
microinstructions have longer execution times to allow certain operations to
be completed. The microinstructions have been grouped according to execution
times as A, B, C, D, E, F, and G as shown in table 4-22. | |
The classification of microinstructions is shown in figure 4-8. This figure
provides execution time by types for all legal combinations of microcommands
that extend the basic cycle time.
Exceptions to the execution times listed in figure 4-8 are:
1. The combination of one's complement arithmetic with an ADD+ or ADD+T
arithmetic operation is classified as a type B rather than a type C.
2. The MMU and MML B' commands are included under read/write micromemor y
operand commands; therefore, they are a type F rather than a type B.
3. A type G microinstruction followed by a microinstruction with a GITMAK
command (C field) has an additional execution time of 185 nanoseconds
(typical); thus the total execution time becomes 625 nanoseconds.
Analysis of a microprogram for execution time starts by classifying each of
the microinstructions as type A, B, C, D, E, F, or G. This is done by using
the microinstruction classification table or by examining the assembler
output listing. -
Each microinstruction with a main memory Read or Write command has a
440-nanosecond (typical) execution time regardless of the type of cycle
(assuming no DMA activity on main memory interface). However, type E and F
microinstructions cannot contain a main memory reference command. An
additional execution time of 185 nanoseconds (typical) is required on all
Read commands followed by a microinstruction containing a GITMAK command.
The total execution time required is then calculated from start of main
memory command to next main memory command. If the total time, starting with
a microinstruction with a Read or Write command and including all micro-
instructions up to the following Read or Write command is less than the
memory cycle time (600 nanoseconds), take 600 nanoseconds as the execution
time for that sequence. If the total time is greater than 60 nanoseconds,
the execution time for that sequence is the calculated time. See figure 4-9.
4-64 | | | 60472800 С
TABLE 4-22. MICROINSTRUCTION EXECUTION TIMES
Microinstruction Type Execution Time in Nanoseconds'
A 168
B 224
C 280
D | 336
E (shift or scale) 280 +56n (where n =
number of shifts)
F (micromemory read/ 448
write operand)
G (read/write main | 440 (typical)
memory)
'Execution times may vary +4% over temperature range (09 to 70°C) and
voltage +5%.
READ/WRITE MAIN MEMORY
READ/WRITE MICROMEMORY OPERAND
HFOOOOOOOOOOOOOOOOOO
© || © © © © © © © © © © О о о оО о
60472800 С
SHIFT OR SCALE
ONE'S COMPLEMENT ARITHMETIC
ADD OR SUBTRACT
TMA, TMAK, GITMAK
A', B', NU, ZL, COL, Z*L
INSTRUCTION TIME
X = O OR 1 (DON'T CARE CONDITION)
OOHFHFOOCOOCGCOOQOO OOCGCOGOGO
X OO © © нон НН он нон он оС © © © © © © ©
VE O SOHO Eo
>Я СБ | СО нон © | > © © а | © © -- -- © ©
о © © © || © Но © |- © | © |-н © -- © - ©
aMHHDABAAREAAAWAAWWS
. Figure 4-8. Microinstruction Classification
Instruction Type Time
G (MEM REF) 440
A 168 ses
С 280
G (MEM REF) 440—_
A | 168 608
G (MEM REF) 625 |
C (GIT MAK) 280 = 1129 (440 + 185 = 625)
B 224 |
G (MEM REF) 440 |
A 168 12
F 504
G (MEM REF)
Figure 4-9. Calculation of Microprogram Sequence Execution Time
60472800 C
1/0 PROGRAMMING FORMATS
This section contains I/0 programming formats for communicat
peripheral I/0 devices installed with the 255X NPU system.
through 5-15.
ions couplers and
See figures 5-1
11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 X X X X Clear Coupler
Equip 0 1 0 0 X X X X Clear Processor
Code 0 0 1 0 X X X X Stop Processor
(=7) 0 0 O 1 X x x x Start Processor
x x X X 0 0 0 O Input Memory Address
- | | Zero!
X X X X 0 c 0 1 Input Memory Address One!
X X X X 0 0 1 0
x x X X 0 0 1 1 Input Data
X X X X 0 1 0 0 Input Processor Status
X X X X 0 1 0 1 Input Coupler Status
X X X x 0 1 1 0 Input Order Wordt
x X X X 0 1 1 1 Input Program
X X X X 1 0 0 0 Output Memory Address 0
(upper byte)
X X X X 1 0 0 1 Output Memory Address 1
| (lower byte) | -
X X X X 1 0 1 0 | |
X X X X 1 O 1 1 -
X X X X 1 1 0 0: Output Data
X X X X 1 1 0 1 ‘Output Program
x x X X 1 1 1 0 Output Order Word
X X X X 1 1 1 1 |
‘Hardware Maintenance feature
Figure 5-1. Communications Coupler PPU Function
60472800 C
Codes
[15 14 13 12 11 10 9 8 7 6 5 4 т 2 1 ol
| | |
| |— Memory Parity Error!
| meme Protect Fault
LE Status Register Loaded
Memory Address Register Loaded
Reserved
Transmission Complete!
— Transfer Terminated by NPUT
— Transfer Terminated by PPUT
— Order Word Register Loaded!
— NPU Status Accepted!
— PPU Channel Timeoutt
—PPU Channel Parity Error (CYBER 170)
Available to NPU Only
— Chain Address ==i
—Alarmit
"¡Alarm Condition (all alarms generate NPU interrupt)
'NPU Interrupt Condition
NOTE: All nonalarm interrupt conditions except OWRL are cleared by input
coupler status command, clear coupler function, and clear coupler
command. OWRL interrupt condition is cleared by input OW command,
clear coupler function and command, and Master Clear. Alarm
interrupt conditions are cleared only by clear coupler functions and
commands and Master Clear.
Figure 5-2. Communications Coupler Status Format
[15 14 13 12[11 10 9 8] 7 0]
ULLI — |:
om: Data Channel Parity Switch
| L -Line Switch
Protect Switch
Coupler Busy
Equipment Code Bit 0 Switch
— Equipment Code Bit 1 Switch
—Equipment Code Bit 2 Switch
— Character Request
Figure 5-3. Communications Coupler Input Switch Status Format
60472800 C
|15 14 13 12 |11 10 9 в |7 6 5 4 |3 2 1 of
| 0 0 0 o0|0|1 E E|E |
= ———— ——
Not
Equipment Address Used
~~
First Coupler = 0 0 0 0 0 Input Memory Address
1100 ('C') Zero!
Standard 0 0 1 0 0 Input Memory Address
0 21 0 о O
Second Coupler = 0 1 1 0 0 Input First/Present
1101 ('D') Character Dis-
(Optional) placement
| 1 0 0 0 0 Input Processor
Status! |
1 0 1 0 0 Input Coupler Status
1 1 0 о O Input Order Word
1 1 1 0 O Input IO!
Sample <
(Read) 0 0 0 0 1 Input Last Word
From Data Channel!
O 0 1 0 1 Input FDMARO/FDMARI1!
0 21 0 0 1 Input FDMARO/Flag
Mux?
O 1 1 O 1 Input FDMARl/Flag
Mux/Flag Register!
12 000 11 |
1 0 1 0 1 Input Switch Status
1 1 0 0 1
u 1 1 1|0O 17 Input Character’
4 0 0 0 1 0 Output Memory
Address Zero!
0 0 1 1 0
O 1 0 1 0 |
0 21 1j 1 O Output FCD, PCD,
LCD!
11 0 04121 O Output Processor
| Status
1 0 1 1 0 Output Buffer
| | Length
11 010 0 Output Order Word!
1 1 1 1 0 |
Set } * —
(Write) < 0 0 O 12 1 Clear Coupler Ter-
| 0 0 1 1 1 minate Transfer
o 12 0 1 1. SE
0 1 1 1 1
1 0 0] 1 1] output Test!
1 0 1 1 1 Input Test!
1 1 0 1 1 Output Memory
Address
u 1 1 1} 1 1 Output Character?
‘Hardware maintenance feature
Figure 5-4. Communications Coupler-Processor Set/Sample Instruction Format
60472800 C | | | 5-3
15 12 11 10 9 8 7 6 5 4 3 2 1
0
| Not Used | A Register
Unit 0/1 Clear controller
selection! Clear interrupt
| | Enable interrupt on data
Motion controls —— | ‘ Enable interrupt on
end of operation
Enable interrupt on
alarm
Echo mode
ADT mode
"A manual switch on the controller card can override this function bit and
force Unit l to always be selected. Standard NPU systems always have this
Switch on. |
Figure 5-5. Cassette Tape Controller Control Functions Format
A Register Bits
10 9 8 7 Function
1 0 0 0 Search Tape Mark (Reverse)
1 0 0 1 Search Tape Mark (Forward)
1 0 1 O Write Tape Mark
1 0 1 1 Write One Record
1 1 0 0 Backspace One Record (or Tape Mark)
1 1 0 1 Rewind |
1 1 1 0 Erase
1 1 1 1 Read One Record
Figure 5-6. Cassette Tape Controller Motion Controls
5-4 | | 60472800 С
15 14 13121110 9 8 7 6 543 21 0
I TIT т | тт | т | | A Register
| ноу
Ls
Write Enabled
Data (Available/Request)
—End of Operation
— Alarm
—. Lost Data Overflow (during Read) /
— Protected Under flow (during Write)
—= CRC Error/Format Error
— End of Tape
— Beginning of Tape (Load Point)
— Tape Mark
— Side В
— (Unit)
— Data Available
— ADT Mode
Alarm condition |
Interrupt condition (if requested)
Figure 5-7. Cassette Tape Controller Status Response Format
MSB ' | | LSB
15 14 13 121110 9 8 7 6 5 4 3 2 1 O
| w=o Е = В 0
Q Register
MSB LSB
15 14 13 12 11 10 9 8 7
la Register
| Lees Controller
| Lo Interrupts
Interrupt on data
Interrupt on EOP
Interrupt on alarm
Not Used
| — ADT Mode
le Feed Request
Figure 5-8. Card Reader Controller Director Function Format
60472800 C
MSB LSB
15 11 10 7 6 5 2 l |
| W = 0 E 0 Not Used o 1 | Q Register
MSB LSB
15 1110 9 8 7 6 5 4 3 2 1 7
i T y y ’ 3 ' ' 1 |
| Not Used | | A Register
. 1 }
TT Ready
| Ls
Interrupt
Data
End of Operation
— Alarm
— Lost Data
Protected
| мос Used
— NOt ready
—e ADT Mode
Figure 5-9. Card Reader Controller Director Status 1 Format
. MSB | LSB
15 11 10
| Ом = 0 Е = В Q Register
MSB | LSB
A Register
| L Hopper Empty
| Loo Full
Fail to Feed
| » Not Used
Stacker Area Jam
Figure 5-10. Card Reader Controller Director Status 2 Format
5-6 e. 60472800 C
15 11 10 7 6 5 2 1 0
W=0 E = B 0 Q Register
MSB LSB
15 12 11 10 9 8 7 6 5 4 3 2 1 ©
60 1 2 3 4 5 6 7 8 9 |--— Сага Row
а 3 а в a A A a а _ В j A Register
A
Y Y
ZERO — DATA
Figure 5-11. Card Reader Controller Data Transfer Command Format
MSB | | Е LSB
15 11 10 7 6 5 2 1 0
Q Register
A Register
ser Test Mode
Figure 5-12. Peripheral Controller Self-Test Command Format
MSB LSB
15 11 10 7 6 5 | | 1 0 |
w = 0 Е = 4 0 Q Register
LSB
6 5 4 3 2 1 0
v I U 1 ' 1
A Register
Le Printer
Loss Interrupts
Interrupt on data
Interrupt on EOP
Interrupt on alarm
| Print
— ADT Mode
Figure 5-13. Line Printer Controller Director Function Format
60472800 C | 5-7
MSB
15 11 10 7
Q Register
LSB
9 8 7 6 5 4 3 2 1 7
v 1 Y т ¥ 3 y в 7 Ч
A Register
e 3 2 В 2 î `
| : Ready
TT Busy
Interrupt
Data
End of Operation (EOP)
— Alarm
— Error
— Protected
Load image
— ADT Mode
— Paper out
— Buffer overflow
Figure 5-14. Line Printer Controller Director Status Response Format
MSB
15 11 10 7 6
O Register
7 |
Character | A Register
Figure 5-15. Line Printer Controller Data Transfer Command Format
5-8 | В 60472800 С
HEXADECIMAL/DECIMAL CONVERSION A
TT НОО ОННОЕЕОООЧЕНООООЕОООООЕНООНОООНННННОНООННООООННСННННА ОНИ
TO CONVERT DECIMAL TO HEXADECIMAL
1. Find decimal number in body of table (Example: 157).
2. Scan horizontally to left to find first hexadecimal digit (e.g., 9
3. Scan vertically up (from 157 in table) to find second hexadecimal
digit (in this case, D).
4, Thus decimal number 157 = hexadecimal number 9D.
TO CONVERT HEXADECIMAL TO DECIMAL
1. To find first hexadecimal digit in left-hand column (Example: D).
2. Find second hexadecimal digit in top row (Example: 9).
3. Scan horizontally to right (from D) and scan vertically downward (from
9) to find point of intersection in body of table (in this case, 217)
4. Thus hexadecimal number D9 = decimal number 217.
TABLE A-1. HEXADECIMAL/DECIMAL CONVERSION
First В
Нех | Second Hexadecimal Digit
Digit Oo 1 2 3 4 5 6 7 8 9 A B C D E E
4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135 136 317 318 139 140 141 142 143
144 145 146 147 148 149 150 151 152 153 154 155 156 518 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215 216 218 219 220 221 222 223
224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
oO
o
jt
N
Ww
H Og OO AQ Y >» WO © N adds w N FF
60472800 C | | A-1
MNEMONICS LISTING
~ MNEMONIC AND DESCRIPTION
ALU
A/Q
BG
BP
CCITT
CIB
CLA
CLE
CLR
CLRF
CRC
CRCS
CRT
CTS
DMA
DSA
DSR
DTO
DTR
DTU
ECHO
EOB
EOF
EXGO
EXMC
EXSTOP
FCD
FCO
FCR
FES
FIFO
FNE
IAV
IDC
IEN
IER
I/F
ILE
INS
INT
INTU
Arithmetic and logical unit
Type of IDC interface (CDC)
Bit generator
Breakpoint
Consultive Committee, Interna-
tional Telephone & Telegraph
Circular input buffer
Communications line adapter
Communications line expansion
module
Clear |
Clear flags
Cyclic redundancy checksum
(created by cyclic encoder)
Cyclic redundancy checksum
(created by multiplex loop
interface adapter)
Cathode ray tube
Clear to send |
Direct memory access
Direct storage access
Data set ready
Data transfer overrun
Data terminal ready
Data transfer underrun
Echoplex mode
End of loop batch
End of line frame
External go |
External master clear
External stop
First character displacement
First character outbound
Function control register
Framing error status
First in, first out
Flag, null empty
Input available
Internal data channel
Input end |
Input error
Interface
Input loop error
Input select
Interrupt
Interrupt test
60472800 C
1/0
ION
ISON
ISR
IST
LCD
LED
LF
LFP
LIT
LOC
LRC
LSB
LSI
MA
MAC
MAE
MCA
MCL
MCR
MCT
MDS
MIR
MLIA
MML
Modem
MO5
MOS
MPE
MPP
MR
MSB
MSI
NCNA
NSYN
ODD
OER
OLE
OON
Input/output
Input section on
Input supervisor on
Input supervision report
Input strobe
End of loop batch flag
Last character displacement
Light-emitting diode
End of line frame flag
Last frame position
Loop input test
Location
Longitudinal redundancy
checksum
Least significant bit
Large-scale integration
Micromemory address
Memory address counter
Memory address error
Memory acknowledge
Master clear
Memory cycle request
Memory cycle timing
Memory data strobe
Microinstruction register
Multiplex loop interface
adapter
Micromemory lower
Micromemory upper
Modulator /Demodulator
Type of IDC interface (NCR)
Metal oxide semiconductor
Memory parity error
Microprogrammed processor
Master reset line
Most significant bit
Medium-scale integration
Memory write
Next character not available
‘New synchronization
Next word position
Output data demand
Output error
Output loop error
Originate mode
Output section on
Output select
Output strobe
Process additional data
Program controlled
Present character displacement
Parity error status
Protective ground
Parity inhibit
Program input/output
Page/micromemory address
Peripheral processing unit
Programmable read-only memory
Page storage
Parity set
Random access memory
Receive data
Receive data (modem)
Return address location
Ring indicator
Receive line signal detector
Read next instruction
Read-only memory
Restraint detector
Resynchronize
Return jump
Request to send
Read/write
SB
SCL
SCR
SCT
SD
SETF
SM
SMI
SO
SOD
SRLSD
SRTS
SSEE
SSI
SSTB
STERM
STJP
TB
TDATA
TMA
TTL
TTY
U/L
XT /MA
Stop bit
Serial computation logic
Serial block receive
Serial clock transmit
Send data
Set flags
Status mode
Status mode interrupt
Storage register outbound
Signal quality detector
Secondary receive line signal
detector
Secondary request to send
Test section and error number
Small-scale integration
Strobe line
Terminate
Stop jump
Terminal busy
Transmit data
Transmit memory address
Transistor/transistor logic
Teletypewriter
Upper/lower
Transform/memory address
60472800 C
> cuil mél
is
CUT ALONG UNE
mun
AA3419 REV. 4/79 PRINTED IN U.S.A.
Lo bl ia cabe ik mi
COMMENT SHEET
MANUAL TITLE: CDC Network Processor Unit 2551-1, 2551-2, 2551-3,
2551-4, 2552-2 Hardware Reference Manual
PUBLICATION NO.: 60472800 REVISION: D
NAME:
COMPANY:
STREET ADDRESS:
CITY: STATE: ZIP CODE:
This form is not intended to be used as an order blank. Control Data Corporation welcomes your evaluation of
this manual. Please indicate any errors, suggested additions or deletions, or general comments below (please
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