MCS-4 datasheet
 = 4-Bit Parallel € gy
Instructions
= Instruction Set ı Me
Conditional Branching, Jump lo
Subroutine and Indirect Fg
a Binary a and Decimal Arithmetic
Modes
= Addition of Tu 8. Digit Numbers
in 850 Microseconds
m 2- Phase [ Dynami e Operation -
The MCS-4 is a microprogrammable computer set designed for applications such as test
systems, peripherals, terminals, billing machines, measuring systems, numeric and process
control. The 4004 CPU, 4003 SR, and 4002 RAM are standard building blocks. The 4001
ROM contains the custom microprogram and is implemented using a metal mask accord-
ing to customer specifications.
MCS-4 systems interface easily with switches, keyboards, displays, teletypewriters,
printers, readers, A-D converters and other popular peripherals.
A system built with the MCS-4 micro computer set can have up to 4K x 8 bit ROM words,
1280 x 4 bit RAM characters and 128 1/0 lines without requiring any interface logic. By
adding a few simple gates the MCS-4 can have up to 48 RAM and ROM packages in any
combination, and 192 1/0 lines. The minimum system configuration consists of one CPU
and one 256 x 8 hit ROM.
The MCS-4 has a very powerful instruction set that allows both binary and decimal
arithmetic. It includes conditional branching, jump to subroutine, and provides for the
efficient use of ROM look-up tables by indirect fetching.
The Intel MCS-4 micro computer set (4001/2/3/4) is fabricated with Silicon Gate Tech-
nology. This low threshold technology allows the design and production of higher
performance MOS circuits and provides a higher functional density on a monolithic chip
than conventional MOS technologies.
~ Configu ration
ue RATE VE TE TE
Copyright Intel Corporation 1971. Contents may not be reproduced in whole or part without the written consent of Intel Corporation.
- ные DHIIN HSL
MICS:4 Description
256 x 8 BIT MASK PROGRAMMABLE
ROM AND 4 BIT 1/0 PORT
4001
«——o0 GND
RESET ©
— PIN CONFIGURATION
- on: > Hua) .
DATA oda Ш ES o
"0 0, []3 14] 1/0, Lines
The 4001 is a 2048-bit metal 13 De .
mask programmable ROM pro- | он ws ewe 14
viding custom microprogram- do. de " of
ming capability for the MCS-4 a ; Tu. sn
micro computer set. It is organ- ие в forest
ized as 256 x 8 bit words. |
Address and data are transferred in and out by time
multiplexing on 4 data bus lines. Timing is internally generated
using two clock signals, ¢,and ¢,, and a SYNC signal supplied
by the 4004. Addresses are received from the CPU on three
time periods following SYNC, and select 1 out of 256 words
and 1 out of 16 ROM's. For that purpose, each ROM is
identified as #0, 1, 2, through 15, by metal option. A
Command Line (CM) is also provided and its scope is to select
a ROM bank (group of 16 ROM's).
During the two time periods (M, 8%: M>) following the
addressing time, information is transferred from the ROM to
the data bus lines.
A second mode of operation of the ROM is as an Input/Output
control device. In that mode a ROM chip will route
information to and from data bus lines in and out of 41/0
external lines. Each chip has the capability to identify itself
for an 1/0 port operation, recognize an 1/0 port instruction
and decide whether it is an Input or an Output operation and
execute the instruction. An external signal (CL) will asyn-
chronously clear the output register during normal operation.
All internal flip flops (including the output register) will be re-
set when the RESET line goes low (negative voltage).
Each 1/0 pin can be uniquely chosen as either an input or
output port by metal option. Direct or inverted input or
output is optional. An on-chip resistor at the input pins,
connected to either Vp or Veg is also optional. (See ordering
information on page 12).
4002 320 BIT RAM AND 4 BIT OUTPUT PORT
©
—
O $,
ONE OF FOUR REGISTERS
IN THE RAM ARRAY
; REGISTER 0
4 | MEMORY CHARACTER 0
0 THROUGH 15
MAIN MEMORY CHARACTERS
Vpp o—— ; R/W
- i
® Y ! E
MEMORY CHARACTER 15 is
STATUS CHARACTER 0 =
| 2
(16) ' ©
O9 = STATUS CHARACTER 3 =
04 4BITS 5°
o e @ 5
° @
03 CM Po
RESET 2
The 4002 performs two func- [Pin ne pa
4 — PIN CONFIGURATION
tions. As a RAM it stores 320 . ; |
bits arranged in 4 registers of 0
twenty 4-bit characters each (16 10
main memory characters and 4 m
status characters). As a vehicle | Jo;
of communication with periph- | 2 vp —15%
eral devices, it is provided with | MO 6 1 Снт:
4 output lines and associated „осо С] won {HARES
control logic to perform output eg 8 9 [O neser
operations. Be
In the RAM mode, the operation is as follows: When the CPU
executes an SRC instruction (see Instruction Set on page 5) it
will send out the contents of the designated index register pair
during X, and X3 as an address to the RAM, and will activate
one CM-RAM line at X, for the previously (Note 1) selected
RAM bank (see Basic Instruction Cycle on page 5).
The data at X, and X 3 is interpreted as shown below:
(0 aBración 15)
. (0 cie 3) (0 through 3)
The status character locations (0 through 3) are selected by
the OPA portion of one of the 1/0 and RAM Instructions.
For chip selection, the 4002 is available in two metal options,
4002-1 and 4002-2. An external pin, Po (which may be hard
wired to either Vop or Vgg) is also available for chip selection.
The chip number is assigned as follows:
Chip # ul. _4002 Zo. ue
о | To à
>: | 1 0
3 1 1
Timing i is Tntermally presser: y using two clock signals, 6, and
¢, , and a sync signal provided by the 4004. Internal refresh
circuitry maintains data levels in the cells.
All communications with the system is through the data bus.
The 1/0 port permits data out from the system. When the
external RESET signal goes low, the memory and all static
flip-flops (including the output registers) will be cleared. To
fully clear the memory the RESET signal must be maintained
for at least 32 memory cycles (32 x 8 clock periods).
MICS-4 Description
10 BIT SERIAL-IN/PARALLEL-OUT,
SERIAL-OUT SHIFT REGISTER (SR)
Vpp GND
ñh A
a jo
© INARY GEN. - POWER
. 5 CLEAR ©
4003
~~ SERIAL
©
DATA IN O—
OUT
[|| 1 | 1 X | Lı
Ÿ
u ENABLE GATES |
FTTH
Qp О, Q, Оз Од ОБ 06 о, Qs Qg
Y | | Y
Y Y Y Y
©
The 4003 is a 10 bit static shift
register with serial-in, parallel-
out and serial-out data. Its func-
tion is to increase the number
of output lines to interface with
I/O devices such as keyboards,
displays, printers, teletypewrit-
ers, switches, readers, A-D con-
verters, etc.
me ENABLE INPUT
sentar our |
= — |
ag]
| PARALLEL |
7 Г OUTPUTS
Data is loaded serially and is available in parallel on 10 output
lines which are accessed through enable logic. When enabled
(E = low), the shift register contents is read out; when not
enabled (E = high), the parallel-out lines are at Ves. The serial-
out line is not affected by the enable logic.
Data is also available serially permitting an indefinite number
of similar devices to be cascaded together to provide shift
register length multiples of 10.
The data shifting is controlled by the CP signal. An internal
power-on-clear circuit will clear the shift register (Q; = Vss )
between the application of the supply voltage and the first
CP signal.
4002 320 BIT RAM AND 4 BIT OUTPUT PORT
NOTE 1: Bank switching is accomplished by the CPU after receiving
a "DCL" (designate command line) instruction. Prior to ex-
ecution of the DCL instruction the desired CM-RAM; code
has been stored in the accumulator (for example through an
НОМ instruction). During DCL the CM-RAM; code is trans-
ferred from the accumulator to the CM-RAM register. The
RAM bank is then selected starting with the next instruction.
4 BIT CENTRAL PROCESSOR UNIT
4004 (CPU) WITH 45 INSTRUCTIONS
CM-ROM CM-RAM, CM-RAM, CM-RAM, CM-RAM4 $ Фо
RN NA
CM LOGIC & BUFFERS * .. | — TIMING: SYNC
| I INDEX
|| rec. LL
16x 4
: RAM
Vpp O—=
GND o—»
®
|} INSTR. |]
DEC.
PROGRAM
ADDER ; 1656 STACK
AND à x 12
SHIFTER | RAM.
CONTROL —
CONTROL |
“INSTR,
RES.
OPR, OPA
>
TEST RESET
INCRE-
MENTER
o
N
=
©
A
Y
4
®
OJ §
D3 O" BUFFER
PIN CONFIGURATION
The 4004 is a central processor o Gi | E.
unit (CPU) designed to work | "A a EU
in conjunction with the other | A Г I um if
members of the MCS-4 (4001,
4002, 4003) for microprogram-
mable computer applications.
The CPU chip consists of a4 bit
adder, a 64 bit (16 x 4) index E “TT
register, a 48 bit (4 x 12) program counter Fand stack (nesting
up to three levels if possible), an address incrementer, an 8 bit
instruction register and decoder, and control logic. Information
flows between the 4004 and the other chips through a 4-line
data bus. One 4004 may be combined with up to 48 ROM
(4001) and RAM (4002) chips in any combination.
A typical machine cycle starts with the CPU sending a syn-
chronization signal (SYNC) to the ROM's and RAM's. Next,
12 bits of ROM address are sent to the data bus using three
clock cycles (@ .75 MHz). The address is then incremented by
one and stored in the program counter. The selected ROM
sends back 8 bits of instruction or data during the following 2
clock cycles. This information is stored in two registers: OPR
and OPA. The next three clock cycles are used to execute the
instruction. (See Basic Instruction Cycle on page 5.)
The ROM bank is controlled by a command ROM control
signal (CM-ROM) and up to four RAM banks are controlled
by four command RAM control signals (CM-RAMg , CM-
RAM, , CM-RAM, , CM-RAM3 ). Bank switching is accom-
plished by the execution of the DCL instruction (see Note 1
this page).
An input test signal (TEST) is used in conjunction with the
jump on condition (JCN) instruction. An external RESET
signal is used to clear all registers and flip-flops. To fully clear
all registers, the RESET signal must be applied for at least 8
memory cycles (8 x 8 clock periods). After RESET the program
will start from “0” step and CM-RAM(¿ will be selected.
CJ eMAAMa)
von 15V
| MEMORY
[_] CM-ROM {EH
OUTPUT
rest
Cr RESET
The instruction repertoire of the 4004 consists of:
(a) 16 machine instructions (5 of which are double length).
(b) 14 accumulator group instructions.
(с) 15 input/output & RAM instructions.
MICS-4 Operation
The detailed functional specifications describing the operation of the system, the instruction set, the activity of the CPU for each
instruction and some programming and hardware examples are published separately and are available upon request. Following is a
brief outline of the system operation.
The MCS-4 uses a 10.8 usec instruction cycle. The CPU (4004) generates a synchronizing signal (SYNC), indicating the start of an
instruction cycle, and sends it to the ROM's (4001) and RAM's (4002).
Basic instruction execution requires 8 or 16 cycles of a 750 KHz clock. In a typical sequence, the CPU sends 12 bits of address to
the ROM's in the first three cycles (A, A,, Aj). The selected ROM chip sends back 8 bits of instruction (OPR, OPA) to the CPU
in the next two cycles (M, , M, ). The instruction is then interpreted and executed in the final three cycles (X, , X5 , X-). (See
Figure 2.)
The CPU, RAM's and ROM's can be controlled by an external RESET line. While RESET is activated the contents of the registers
and flip-flops are cleared. After RESET, the CPU will start from address 0 and CM-RAM, is selected.
The MCS-4 can have up to 4K x 8 bit ROM words, 1280 x 4 bit RAM characters and 128 1/0 lines, without requiring any interface
logic. By adding a few simple gates, the MCS-4 can have up to 48 RAM and ROM packages in any combination and 192 1/0 lines.
The 4001, 4002, and 4004 are interconnected by a 4-line data bus (Dg, D1, D2, D3), used for all information flow between the
chips except for control signals sent by the CPU on 6 additional lines. The interconnection of the MCS-4 system is shown in
Figure 1. An expanded configuration is shown. The minimum system configuration consists of one CPU (4004) and one ROM
(4001). Figure 2 shows the activity on the data bus during each clock period, and how a basic instruction cycle is subdivided.
Each data bus output buffer has three possible states “1”, “0”, and floating. At a given time only one output buffer is allowed to
drive a data line, therefore, all the other buffers must be in a floating condition. However, more than one input buffer per data
line can receive data at the same time.
The MCS-4 has a very powerful Instruction Set that allows both binary and decimal arithmetic. It includes conditional branching,
jump to subroutine and provides for the efficient use of ROM look up tables by indirect fetching. Typically, two 8 digit numbers
can be added in 850 usec. The complete Instruction Set is shown on pages 5 and 6.
Figure 1. MCS-4 System Interconnection
mdcs-4 Operation
La Address Sent to ВОМ Егот СРу — — >
|< — ——
INSTRUCTION CYCLE
Instruction Sent to
CPU From ROM
—— >
l«————— Execution of Instruction — — >
Data is Operated on in the CPU, Or
]
La — 1.35 ив — >| Data or Address is Sent to/from the CPU
1
02
SYNC —
Memory X A
IFIOR The
The Selected 4001 Is Enabled The CPU The CPU
The CPU Is Enabled >< = Selected 4001
Device Is Enabled Or 4002 Are Is Enabled
Controlling Enabled, Other-
Data Bus wise The CPU
Output Is Enabled
y ; . . . . Data or Address
Data Lower 4-bit Middle 4-bit Higher 4-bit — -<—— Instruction to CPU ———| OPA Out to RAM's and Address to
Вы Address to Address to Address to PU ROM's If 101) RAM's If
ontents ROM's ROM's ROM's (Chip OPA to (2) SAC?)
Select Code) OPR to CPU and ROM's (Not Used) Or SRC
and RAM's Data to CPU
If 10M ТОВ’
IO instructions control the flow of information between accumulator in CPU, I/O lines in ROM's and RAM's and RAM storage. TOR stands for 10 Read. In this
case the CPU will receive data from RAM storage locations or I/O input lines of 4001's.
The SRC instruction designates the chip number and address for a following IO instruction,
Instruction Set
[Those instructions preceded by an asterisk (*) are 2 word instructions that occupy 2 successive locations in ROM
MACHINE INSTRUCTIONS
See Notes on Page 6.
Figure 2.
MCS-4 Basic Instruction Cycle
Te
Continued on page 6.
Instruction Set
INPUT/OUTPUT AND RAM INSTRUCTIONS
(The RAM's and ROM's operated on in the 1/0 and RAM instructions have been previously selected by the last SRC instruction executed.)
NOTES: (1 The condition code is assigned as follows:
C, =1 Invert jump condition Со = 1 Jump if accumulator is zero C4y=1 Jump if test signal is a O
O Not invert jump condition C,=1 Jump if carry/link isa 1
o
Il
(2)RRR is the address of 1 of 8 index register pairs in the CPU,
(3)RRRR is the address of 1 of 16 index registers in the CPU.
(4)Each RAM chip has 4 registers, each with twenty 4-bit characters subdivided into 16 main memory characters and 4 status characters.
Chip number, RAM register and main memory character are addressed by an SRC instruction. For the selected chip and register, however,
status character locations are selected by the instruction code (OPA).
Absolute Maximum Ratings*
Ambient Temperature Under Bias 0°C to +70°C *COMMENT
Storage Temperature —55°C to +150°C Stresses above those listed under “Absolute Maximum Ratings”
Input Voltages and Supply Voltage may cause permanent damage to the device. This is a stress rating
With Respect to V +0.5 to —20V only and functional operation of the device at these or any other
SS condition above those indicated in the operational sections of this
Power Dissipation 1.0 W specification is not implied.
D.C. and Operating Characteristic
TA= 0°C to +70°C; Vpp = —15V +5%, Ves = GND, tóPw = tóD1 = 400 nsec, ‘фр2 = 150 nsec, unless otherwise specified
Logic “0” is defined as the more positive voltage (ViH, Von}. Logic 1” is defined as the more negative voltage (М, Le Vor!
SUPPLY CURRENT
(1) Typical values are for Tp = 259C and Nominal Supply Voltages.
(2) If non-inverting input option 1$ used, V|| = —6.5 Volts maximum.
Typical D.C. Characteristics
--
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or
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=
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ES
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ass
Sw
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oc ñ
us
=
O
(a
+=
т
or
e
ok
O1
>=
ala
а = <
ui
DL
Eu
>>
O
[a
2
za dy
— — —
- (VW) 1N3HYHN9 A1ddNS HIMOd
AMBIENT TEMPERATURE (°C)
13
Lady В
(VW) INFHHNI A1ddNS 43IMOd
AMBIENT TEMPERATURE (°C)
POWER SUPPLY CURRENT
VS. TEMPERATURE
(4004)
6
2
<r
N N
vda] - (yw) iN3YHYHN9 AT1ddNs HIMOd
3
3
VS. TEMPERATURE
(4003)
POWER SUPPLY CURRENT
EQUAL - (yw) INIHHND A1ddNS HIMOJ
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
70)
> w
о
2 <<
w=
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o
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Org
5&2
ak
=>»
- O
O
E107 - (yw) INIHHND LNdLNO
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- ©
<.
SER
© = ©
cos
== =
он
нае
IES
a
=O
=
O
2107 - (yw) INIHHNI LNdLNO
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4001, 4002, 4004 A.C. Characteristics
y =0%C to +70% C; Vo, =-15V + 5%, Vez = GND
NOTES: (1)Data out, SYNC, CM-ROM, and CM-RAMi lines are clocked out with the trailing edge of the $) block.
(2)The CM-ROM and the selected CM-RAM,; lines are always activated during A3 time. They are also activated during Mo time if an 1/0 and
RAM instruction was fetched by the CPU, and during Xo time if an SRC instruction was fetched by the CPU.
(3) Pin Con 4001 is used to asynchronously clear the output flip-flops associated with the 1/0 lines.
4001, 4002, 4004 Timing Diagram
Outputs with loading conditions specified on A.C. Characteristics table.
a
O1
tr — =
t < toH >
@ —1V ve
DATA BUS LINES DATA IN DAT
>| | 1в
1 —«— —
@ —1V
4002 OUTPUT LINES, 4001 1/0 OUTPUT LINES EA
=> tos — —-— ‘OH
@ —1V
CM LINES
@ —5V CM OUT
ТЕ —>- - — - ‘в
ГС
VJ)
4001 1/0 INPUT LINES
@ —5V
4001 CLEAR LINE (Cp)
@ —5V
— > te -—
4001 1/0 OUTPUT LINES e—1v
Typical Load Characteristics
SET TIME VS. OUTPUT CAPACITANCE
(DATA LINES FOR 4001, 4002, 4004 SET TIME VS. OUTPUT CAPACITANCE
8: SYNC FOR 4004) (CM-ROM 4004)
700 700
9 600
500 >
$ +? 500
3 400 ë |
u 400 |
= 300 =
= -
5 200 5 200 |
100 200 }
0 0 100 | Lo
100 200 300 400 500 600 700 800 0 100 200 300 400 500 600
OUTPUT CAPACITANCE (pF)
OUTPUT CAPACITANCE (pF)
10
4003 A.C. Characteristics
T, = O%C to +70°C; Vy, = —15 + 5%, Vg = GND
NOTES: (1)twy can be any time greater than 6 Hsec.
(2) Data can occur prior to CP,
4003 Timing Diagram
-«t—— tW| — — >
@ —1V
CP @ —5V т < Чун >
{cp
EE ee Te TE
DATA IN @ —5V
— > ‘ра
@ —1V
DATA OUT F @ —5V
(Q;)
ENABLE e —5v
(E) | |
SERIAL OUT
—»{ 143 «—
Capacitance
f=1 MHz; VN = 0V; Ta= 25%C ; Unmeasured Pins Grounded.
NOTE: (1) Refers to all input pins except data bus 1/0 and ¢; and ¢,.
11
Packaging Information Ordering Information
(1) The 4004 (CPU) is available in ceramic only
and should be ordered as C4004.
(2) The 4001 (ROM), 4002 (RAM) and 4003
(SR) are presently available off the shelf in
plastic only. These devices can be ordered in
ceramic on special request. Standard devices
should be ordered as follows:
P4001 Plastic Package
P4002-1 (Metal Option #1)- Plastic Package
P4002-2 (Metal Option #2)- Plastic Package
P4003 Plastic Package
(3) Mask Programming of the 4001
The custom patterns, chip numbers and 1/0
options (including inverting and non-inverting
inputs or outputs and on-chip resistor con-
ke 100 +010 . uw su
mn
ee SU nected to either V,p or Ves) must be specified
; ; o on a truth table for each 4001 ordered. Blank
custom truth tables are available upon request
from Intel.
.060/.075 REF |
.060/.125 REF
ORIENT SALES OFFICE INTEL JAPAN EUROPEAN SALES OFFICE
Japan Tokyo 151 Parkside Flat Bldg. sue Bruxelles INTEL CORP.
~~ No.4-22, Sendagaya E 216 Avenue Louise
— Shibuya-Ku PP > >;*…— . 5 Bruxelles 1050, Belgium
03003440 020200200 Phone: 492003
— Telex: 26364 DA =
. (408) 246-7501
7144/1
INTEL CORP. 3065 Bowers Avenue, Santa Clara, California 95051
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