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MAX 10 External Memory Interface User
Guide
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TOC-2
Contents
MAX 10 External Memory Interface Overview.................................................. 1-1
MAX 10 External Memory Interface Architecture and Features.......................2-1
MAX 10 External Memory Interface Design Considerations............................ 3-1
DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices............................ 3-3
LPDDR2 Recommended Termination Schemes for MAX 10 Devices.................................... 3-6
Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation..... 3-6
Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2..........................3-8
MAX 10 External Memory Interface Implementation Guides.......................... 4-1
Altera Corporation
TOC-3
UniPHY IP Core References for MAX 10...........................................................5-1
Additional Information for MAX 10 External Memory Interface User Guide
......................................................................................................................... A-1
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MAX 10 External Memory Interface Overview
2014.12.15
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The MAX
®
10 devices are capable of interfacing with a broad range of external memory standards. With this capability, you can utilize MAX 10 devices in a wide range of applications such as image processing, storage, communications, and general embedded systems.
The external memory interface solution in MAX 10 devices consist of:
• The I/O elements that support external memory interfaces.
• The UniPHY IP core that allows you to configure the memory interfaces to support different external memory interface standards.
Note: Altera recommends that you construct all DDR2, DDR3, and LPDDR2 SDRAM external memory interfaces using the UniPHY IP core.
(1)
Related Information
•
MAX 10 External Memory Interface Architecture and Features
•
MAX 10 External Memory Interface Design Considerations
•
MAX 10 External Memory Interface Implementation Guides
on page 4-1
•
UniPHY IP Core References for MAX 10
•
Documentation: External Memory Interfaces
Provides more information about external memory system performance specification, board design guidelines, timing analysis, simulation, and debugging.
•
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
•
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
•
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
1
(1)
Licensing terms and costs for UniPHY IP core apply.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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MAX 10 External Memory Interface Support and Performance
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MAX 10 External Memory Interface Support and Performance
The MAX 10 devices contain circuitry that supports several memory external memory interface standards.
Table 1-1: Memory Standards Supported by MAX 10 Devices
External Memory Interface
Standard
DDR3
DDR3L
DDR2
LPDDR2 (2)
Voltage (V)
1.5
1.35
1.8
1.2
Max Frequency (MHz)
303
303
200
200 (3)
Related Information
•
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported external memory interfaces in Altera devices.
•
Contact Altera
•
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and informa‐ tion about the clock, address/command, data, data strobe, DM, and optional ECC signals.
•
MAX 10 Device Datasheet
(2)
(3)
MAX 10 devices support only single-die LPDDR2.
To achieve the specified performance, constrain the memory device I/O and core power supply variation to within ±3%. By default, the frequency is 167 MHz.
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MAX 10 External Memory Interface Overview
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MAX 10 External Memory Interface
Architecture and Features
2014.12.15
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The external memory interface architecture of MAX 10 devices is a combination of soft and hard IPs.
Figure 2-1: High Level Overview of MAX 10 External Memory Interface System
This figure shows a high level overview of the main building blocks of the external memory interface system in MAX 10 devices.
User
Design
Memory
Controller
Physical
Layer (PHY)
External
Memory SDRAM
2
• The full rate data capture and write registers use the DDIO registers inside the I/O elements.
• PHY logic is implemented as soft logic in the core fabric.
• The memory controller is the intermediary between the user logic and the rest of the external memory interface system. The Altera
®
memory controller IP is a soft memory controller that operates at half rate. You can also use your own soft memory controller or a soft memory controller IP from Altera's third-party partners.
• The physical layer (PHY) serves as the bridge between the memory controller and the external memory DRAM device.
Related Information
•
MAX 10 External Memory Interface Overview
on page 1-1
•
Documentation: External Memory Interfaces
Provides more information about external memory system performance specification, board design guidelines, timing analysis, simulation, and debugging.
•
Memories & Memory Controllers
Provides a list of memory controller IP solutions from Altera and partners.
MAX 10 I/O Banks for External Memory Interface
In MAX 10 devices, external memory interfaces are supported only on the I/O banks on the right side of the device. You must place all external memory I/O pins on the I/O banks on the right side of the device.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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MAX 10 DQ/DQS Groups
Figure 2-2: I/O Banks for External Memory Interfaces
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
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PLL 8 7 PLL
Only the top right PLL is usable for external memory interfaces
1A
1B
6
External memory interface support only available on
I/O banks on the right side of the device.
2
5
PLL 3 4
OCT
PLL
External memory interfaces support is available only for 10M16, 10M25, 10M40, and 10M50 devices.
MAX 10 DQ/DQS Groups
Different MAX 10 devices and packages support different numbers of DQ/DQS groups for external memory interfaces.
Table 2-1: Supported DQ/DQS Group Sizes in MAX 10 Devices and Packages
This table lists the number of DQ/DQS groups supported on different MAX 10 devices and packages. Only the
I/O banks on the right side of the devices support external memory interfaces.
Number of DQ Groups
Device Package
I/O Bank
(Right Side) x8
10M16
F256, U324, and
F484
B5
B6
1
1
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MAX 10 Memory Controller
Number of DQ Groups x8
2
2
1
1
2
2
1
2
2
1
1
1
2
1
1
1
2-3
10M25
10M40
10M50
Device
F256
F484
F256
F484
F672
F256
F484
F672
Package
I/O Bank
(Right Side)
B6
B5
B6
B5
B6
B6
B5
B6
B5
B5
B6
B5
B6
B5
B6
B5
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
MAX 10 Memory Controller
MAX 10 devices use the HPC II external memory controller.
Table 2-2: Features of the MAX 10 Memory Controller
Feature
Half-Rate Operation
Controller Latency
Description
The controller and user logic can run at half the memory clock rate.
The controller has a low best-case time between a read request or a write request on the local interface, and the memory command being sent to the AFI interface.
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MAX 10 Memory Controller
Feature
Data Reordering
Starvation Control
Priority Bypass
Standard Interface
Avalon-MM Data Slave Local
Interface
Bank Management
Streaming Reads and Writes
Bank Interleaving
Predictive Bank Management
Quasi-1T Address/Command
Half-Rate
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Description
The memory controller will reorder read and write requests as necessary to achieve the most efficient throughput of data.
The controller implements a starvation counter to limit the length of time that a command can go unserved. This counter ensures that lower-priority requests are not overlooked indefinitely due to data reordering. You can set a starvation limit, to ensure that a waiting command is served immediately, when the starvation counter reaches the specified limit.
The memory controller accepts user requests to bypass the priority established by data reordering. When the controller detects a highpriority request, it allows that request to bypass the current queue. The high-priority request is then processed immediate, reducing latency.
The memory controller uses Avalon-ST as its native interface, allowing the flexibility to extend to Avalon-MM, AXI, or a proprietary protocol with an adapter.
The controller supports the Altera Avalon memory-mapped protocol.
The memory controller will intelligently keep a page open based on incoming traffic, improving efficiency, especially for random traffic.
The memory controller has the ability to issue reads or writes continu‐ ously to sequential addresses each clock cycle, if the bank is open. This feature allows for the passage of large amounts of data, with high efficiency.
The memory controller has the ability to issue reads or writes continu‐ ously to random addresses. The bank addresses must be correctly cycled by user logic.
The memory controller has the ability to issue bank management commands early, so that the correct row is already open when a read or write request occurs. This feature allows for increased efficiency.
One controller clock cycle equals two memory clock cycles in a halfrate interface. To maximize command bandwidth, the memory controller provides the option to allow two memory commands on every controller clock cycle. The controller is constrained to issue a row command on the first clock phase and a column command on the second clock phase, or vice versa. Row commands include activate and precharge commands; column commands include read and write commands.
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Feature
Built-In Burst Adaptor
Self-Refresh Controls and User
Auto-Refresh Controls
Enable Auto Power-Down
MAX 10 External Memory Read Datapath
Description
The memory controller has the ability to accept bursts of arbitrary size on the local interface, and map these to efficient memory commands.
2-5
The memory controller has the ability to issue self-refresh commands and allow user auto-refresh through a sideband interface.
The memory controller has the ability to power-down if no commands are received.
MAX 10 External Memory Read Datapath
In MAX 10 devices, instead of using DQS strobes, the memory interface solution uses internal read capture clock to capture data directly in the double data rate I/O (DDIO) registers in the I/O elements.
• The PLL supplies memory clock to the DRAM device and generates read capture clock that is frequency-locked to the incoming data stream. The read capture clock and the incoming read data stream have an arbitrary phase relationship.
• For maximum timing margin, calibration sequence is used to position the read capture clock within the optimum sampling position in the read data eye.
• Data is captured directly in the DDIO registers implemented in the I/O periphery.
DDR Input Registers
The DDR input capture registers in MAX 10 devices are implemented in the I/O periphery.
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DDR Input Registers
Figure 2-3: External Memory Interface Read Datapath
FPGA Core
afi_rdata_en read_increment_vfifo
(from Sequencer) read_latency_counter
(from Sequencer) afi_rdata afi_rdata_valid
Latency Shifter
D
CLK latency_counter
Q
FIFO Shifter
D
INCR
CLK
Q
RDATA_LFIFO rdreq
Q wrreq
D
CLK
From Other DQ within DQS Group
Q
RDATA_FIFO
D
RD CLK WR CLK
Q
Q
Input HR Register
Input HR Register
D Q D
Q
Q D Q D
Q Q
PLL
GCLK AFI_CLK (HR)
PHYCLK MEM_CLK (FR)
PHYCLK DQ_WRITE_CLK (FR)
PHYCLK READ_CAPTURE_CLK0
TRACKING_CLK
FPGA Periphery
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dataout
DDIO_IN pad fr_clk hr_clk inclock
DQ clkin[0] clkin[1] clkin[2] clkin[3]
PHYCLK clkout[0] clkout[1] clkout[2] clkout[3]
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MAX 10 External Memory Write Datapath
Figure 2-4: External Memory Interface Read Datapath Timing
afi clock afi_rdata_en write_enable for LFIFO
(afi_rdata_valid) data transferred marked as valid soft
VFIFO pipe read_enable for LFIFO data transferred marked as valid afi_clk captured data
(after rdata _fifo) capture clock /2
HR register output
(clocked by div /2 clock)
2 nd
flopped data first ddio data captured on soft hard capture clock read mem _dq ddio output ba ba dc dcba dc fe a b c d e f g h ba dc fe hg dcba fe hg hgfe hg dcba hgfe dcba hgfe hgfe
2-7
In MAX 10 external memory interfaces, post-amble is not a concern because the read data strobe signal,
DQS, is not used during read operation.
MAX 10 External Memory Write Datapath
For all DDR applications supported by MAX 10 devices, the DQS strobe is sent to the external DRAM as center-aligned to the write DQ data.
The clock that clocks DDIO registers of the DQ output is phase-shifted –90º from the clock that drives the
DDIO registers of the DQS strobe. This create a DQS strobe that is center-aligned to the DQ data.
The external memory write datapath is not calibrated.
DDR Output Registers
A dedicated DDIO write block is implemented in the DDR output and output enable paths.
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DDR Output Registers
Figure 2-5: External Memory Interface Write Datapath
afi_wdata_valid
4
FPGA Core
Full Rate Cycle
Shifter for WL
Adjustment
D fr_cycle_shifter
Q
4
Multiplexer Generator datain muxsel fr_clk afi_wdata
4
D fr_cycle_shifter
Q
4 afi_dqs_burst
4
D fr_cycle_shifter
Q
4
Multiplexer Generator datain muxsel fr_clk
PLL
GCLK AFI_CLK (HR)
PHYCLK MEM_CLK (FR)
PHYCLK DQ_WRITE_CLK (FR)
PHYCLK READ_CAPTURE_CLK0
TRACKING_CLK
FPGA Periphery
Simple DDIO datain hr_clk fr_clk muxsel dataout
2
Transfer Register
D Q
2
Q
D Q
Q
Simple DDIO datain hr_clk fr_clk muxsel dataout
2
Transfer Register
D Q
2
Simple DDIO datain hr_clk fr_clk muxsel dataout
2
Q
Transfer Register
D Q
2 dqs/dqs#
2
Q
Transfer Register
D Q
2
DDIO OUT
D Q
D
Q
Q
Q
DDIO OUT
D Q
Q Q clkin[0]
PHYCLK clkout[0] clkin[1] clkin[2] clkin[3] clkout[1] clkout[2] clkout[3]
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DQ
DQS
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Figure 2-6: External Memory Interface Write Datapath Timing
MAX 10 Address/Command Path
soft afi clock
Write Data afi_wdata phy_ddio_dq
(after fr_cycle_shifter) mux select
WR DATA Hi
WR DATA Lo
afi_wdata_valid[0] afi_wdata_valid[1] phy_ddio_wrdata_en[0]
(after fr_cycle_shifter) phy_ddio_wrdata_en[1]
(after fr_cycle_shifter) afi_dqs_burst[0] afi_dqs_burst[1] phy_ddio_dqs_en[0]
(after fr_cycle_shifter) phy_ddio_dqs_en[1]
(after fr_cycle_shifter) mux select
Write Data Valid
DQS enable
DQS_OE
DQ_OE
hard mem clock
Transferred DQS_OE
Transferred DQ_OE adc clock
mem_dq mem_dqs mem_dqs_n
abcd cd xx
X
X efgh ghab d c b a xx ef h g f e
X
X d c b a h g f e
2-9
MAX 10 Address/Command Path
Altera's soft memory controller IP and PHY IP operate at half rate and issue address/command instructions at half-rate.
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MAX 10 PHY Clock (PHYCLK) Network
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• You must send the address/command instructions to the external DRAM center-aligned with respect to the external memory clock (CK/CK#).
• For LPDDR2 applications, the address/command path is double data rate (DDR). Dedicated DDIO output registers in the I/O periphery clocks out the address/command instructions to the external
DRAM.
• For DDR2/3 applications, the address/command path is single data rate (SDR). Instead of dedicated
DDIO output registers, simple output I/O registers in the I/O periphery clocks out the address/ command instructions to the external DRAM device.
MAX 10 PHY Clock (PHYCLK) Network
The PHYCLK network is a dedicated high-speed and low skew balanced clock tree that provides better clock skew for external memory interface applications.
In MAX 10 devices, only the top right PLL is routed to the PHYCLK tree. Therefore, the PHYCLK tree is available only for the I/O banks on the right side of the MAX 10 10M16, 10M25, 10M40, and 10M50 devices.
Figure 2-7: I/O Banks for External Memory Interfaces
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
PLL 8 7 PLL
Only the top right PLL is usable for external memory interfaces
1A
6
1B
External memory interface support only available on
I/O banks on the right side of the device.
2
5
PLL 3 4
OCT
PLL
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Phase Detector for VT Tracking
Phase Detector for VT Tracking
There may be variations in the read and write paths caused by voltage and temperature changes. The phase detector keeps track of the variation of the mimic clock to optimize the system timing.
Figure 2-8: VT Tracking System Overview
2-11
FPGA Core
CK/CK#
2
FPGA Periphery
I/O Register
DDIO
Out
CK/CK#
Sequencer
DRAM
RESET
ACK
PD_UP
PD_DOWN
Phase Detector
Phase alignment
MIMIC_CLK_P/N
Dynamic Phase
Shift Control
PLL
GCLK SYS_CLK (HR)
PHYCLK MEM_CLK (FR)
PHYCLK DQ_WRITE_CLK (FR)
PHYCLK READ_CAPTURE_CLK (FR)
TRACKING_CLK (FR)
In the MAX 10 external memory interface solution, the memory clocks are used to mimic the read and write paths. The memory clock pins loop back to the phase detector as a mimic clock. The phase detector provides any variation of the mimic clock to the sequencer. The sequencer adjusts the read capture clock to match the clock phase change.
On-Chip Termination
The MAX 10 devices support calibrated on-chip series termination (R
S
OCT) on the right side I/O banks.
• To use the calibrated OCT, use the
RUP
and
RDN
pins for each R
S
OCT control block.
• You can use each OCT calibration block to calibrate one type of termination with the same V
CCIO
.
You must set the
RUP
and
RDN
resistor values according to the R
S value is 34 Ω, then the set both
RUP
and
RDN
value to 34 Ω.
OCT value. For example, if the R
S
OCT
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Phase-Locked Loop
Related Information
MAX 10 On-Chip I/O Termination
Provides more information about OCT.
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Phase-Locked Loop
For the external memory interface, the PLL generates the memory system clock, write clock, capture clock, and the logic–core clock.
• The system clock clocks the DQS write strobe, and the address and command signals.
• The write clock that is shifted –90° from the system clock clocks out the DQ signals during memory writes.
You can use the PLL reconfiguration feature to calibrate the read–capture phase shift to balance the setup and hold margins. At startup, the sequencer calibrates the capture clock.
For external memory interfaces in MAX 10 devices, you must use the top right PLL (PLL 2).
Related Information
PLL Locations
Provides more information about PLL location and availability in different MAX 10 packages.
MAX 10 Low Power Feature
The MAX 10 low power feature is automatically activated when the self refresh or low power down modes are activated. The low power feature sends the afi_mem_clk_disable
signal to stop the clock used by the controller.
To conserve power, the MAX 10 UniPHY IP core performs the following functions:
• Tri-states the address and command signals except
CKE
and
RESET_N
signals
• Disables the input buffer of DDR input
Note: The MAX 10 low power feature is available from version 15.0 of the Quartus
15.0 or later.
®
II software. To enable this feature, regenerate your MAX 10 UniPHY IP core using the Quartus II software version
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MAX 10 External Memory Interface Design
Considerations
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There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
Related Information
•
MAX 10 External Memory Interface Overview
on page 1-1
•
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides pin planning guidelines for implementing external memory interfaces with Altera devices.
3
MAX 10 DDR2 and DDR3 Design Considerations
DDR2/DDR3 External Memory Interface Pins
In DDR2/DDR3 interfaces, the MAX 10 devices use data (DQ), data strobe (DQS), clock, address, and command pins to interface with external memory devices. The devices also use the data mask (DM) pins to enable data masking.
Related Information
DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
MAX 10 Data and Data Clock (Data Strobe) Pins
For the MAX 10 external memory interfaces, the DQ pins are the data pins for bidirectional read and write, and the DQS pins are the data strobe pins used only during write operations.
The MAX 10 devices support bidirectional data strobes. Connect the bidirectional DQ data signals to the same MAX 10 device DQ pins. The DQS pin is used only during write mode. In read mode, the MAX 10
PHY generates the read capture clock internally and ignores the DQS signal. However, you must still connect DQS signal to the MAX 10 DQS pin.
Related Information
Guidelines: Reading the MAX 10 Pin-Out Files
MAX 10 I/O Bank DQ/DQS Support for DDR2/DDR3
For DDR2/DDR3 SDRAM, I/O banks 5 and 6 in MAX 10 devices can support DQ and DQS signals with
DQ-bus widths of 8, 16 and 24 bits.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Data Mask Pins
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• For DDR2 and DDR3 SDRAM interfaces, the devices use ×8 mode DQS group regardless of the interface width.
• If you need to support wider interfaces, use multiple ×8 DQ groups.
• You can use any unused DQ pins as regular user I/O pins if they are not used as memory interface signals.
• The x24 interface is implemented through x16 + ECC.
Related Information
Provides the supported DQ/DQS groups for each device.
Data Mask Pins
In MAX 10 devices, the data mask (
DM
) pins are pre-assigned in the device pinouts. Although the Quartus
II Fitter treats the
DQ
and
DM
pins in a DQS group equally for placement purposes, the pre-assigned
DQ
and
DM
pins are the preferred pins.
Each group of
DQS
and
DQ
signals has one
DM
pin:
• You require data mask (
DM
) pins only while writing to the external memory devices.
• A low signal on the
DM
pin indicates that the write is valid.
• Driving the
DM
pin high causes the memory to mask the
DQ
signals.
• Similar to the DQ output signals, the DM signals are clocked by the –90º shifted clock.
DDR2/DDR3 Error Correction Coding Pins
Some DDR2 and DDR3 SDRAM devices support error correction coding (ECC). ECC is a method of detecting and automatically correcting errors in data transmission.
• In 24-bit DDR2 or DDR3 SDRAM, there are eight ECC data pins and 16 data pins.
• Connect the DDR2 and DDR3 SDRAM ECC pins to a separate DQS or DQ group in the MAX 10 device.
• The memory controller needs additional logic to encode and decode the ECC data.
Related Information
ALTECC (Error Correction Code: Encoder/Decoder) chapter, Integer Arithmetic Megafunctions User
Guide
Provides more information about ALTECC_ENCODER and ALTECC_DECODER IP cores that implement ECC functionality.
DDR2/DDR3 Address and Control/Command Pins
For DDR2/DDR3 interfaces, the address signals and the control or command signals are sent at a single data rate.
You can use any of the user I/O pins on all I/O banks of MAX 10 devices to generate the address and control or command signals to the external memory device.
Memory Clock Pins
At the external memory device, the memory clock signals (CK and CK#) are used to capture the address signals, and the control or command signals.
In MAX 10 devices, the double data rate I/O (DDIO) registers are used to generate the CK/CK# signals.
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DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
3-3
The memory clock pins are predefined and are listed in the device pinout files. Refer to the the relevant device pinout files to determine the locations of the memory clock pins.
Related Information
•
Pin Connection Guidelines Tables, Planning Pin and FPGA Resources chapter, External Memory
Interface Handbook
Provides more information about CK/CK# pins placement.
•
MAX 10 Device Pin-Out Files
DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
If you are creating interfaces with multiple DDR2 or DDR3 components where the address, command, and memory clock pins are connected to more than one load, follow these steps:
1. Simulate the system to get the new slew-rate for the DQ/DQS, DM, address and command, and clock signals.
2. Use the derated t
IS
and t
IH
specifications from the DDR2 or DDR3 datasheet based on the simulation results.
3. If timing deration causes your interface to fail timing requirements, consider duplication of these signals to lower their loading, and hence improve timing.
Note: Class I and Class II termination schemes in the following tables refer to drive strength and not physical termination.
Table 3-1: Termination Recommendations for MAX 10 DDR2 Component
Signal Type
DQ/DQS
DM
Address and command
Clock
SSTL 18 I/O
Standard
Class I 12 mA
Class I 12 mA
Class I with maximum drive strength
Class I 12 mA
FPGA–End Discrete
Termination
50 Ω parallel to V
TT discrete
—
Memory–End Termination 1 Memory I/O Standard
ODT75 (4) HALF
—
(5)
—
—
56 Ω parallel to V
TT
discrete
• x1 = 100 Ω differential
• x2 = 200 Ω differential.
(6)
(7)
—
—
(5)
(6)
(7)
(4)
ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
HALF is reduced drive strength.
x1 is a single-device load.
x2 is a two-device load.
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LPDDR2 Design Considerations
Table 3-2: Supported External Memory Interface Termination Scheme for DDR3 and DDR2
Memory Interface Standard
DDR3
DDR3L
DDR2
I/O Standard
SSTL-15
SSTL-135
SSTL-18
R
S
OCT
25, 50
34, 40
34, 40
25, 50
Related Information
Planning Pin and FPGA Resources
Provides more information about termination and signal duplication.
R
UP
, R
DN
(Ω)
25, 50
34, 40
34, 40
25, 50
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LPDDR2 Design Considerations
Note: MAX 10 devices support single-die LPDDR2 only.
LPDDR2 External Memory Interface Pins
In LPDDR2 interfaces, the MAX 10 devices use data (DQ), data strobe (DQS), clock, command, and address pins to interface with external memory devices. The devices also use the data mask (DM) pins to enable data masking.
MAX 10 Data and Data Clock (Data Strobe) Pins
For the MAX 10 external memory interfaces, the DQ pins are the data pins for bidirectional read and write, and the DQS pins are the data strobe pins used only during write operations.
The MAX 10 devices support bidirectional data strobes. Connect the bidirectional DQ data signals to the same MAX 10 device DQ pins. The DQS pin is used only during write mode. In read mode, the MAX 10
PHY generates the read capture clock internally and ignores the DQS signal. However, you must still connect DQS signal to the MAX 10 DQS pin.
Related Information
Guidelines: Reading the MAX 10 Pin-Out Files
MAX 10 I/O Bank DQ/DQS Support for LPDDR2
For LPDDR2 SDRAM, I/O banks 5 and 6 in MAX 10 devices can support DQ and DQS signals with DQbus widths of 8 and 16 bits.
• For LPDDR2 SDRAM interfaces, the devices use ×8 mode DQS group regardless of the interface width.
• If you need to support wider interfaces, use multiple ×8 DQ groups.
• You can use any unused DQ pins as regular user I/O pins if they are not used as memory interface signal.
Related Information
Provides the supported DQ/DQS groups for each device.
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Data Mask Pins
3-5
Data Mask Pins
In MAX 10 devices, the data mask (
DM
) pins are pre-assigned in the device pinouts. Although the Quartus
II Fitter treats the
DQ
and
DM
pins in a DQS group equally for placement purposes, the pre-assigned
DQ
and
DM
pins are the preferred pins.
Each group of
DQS
and
DQ
signals has one
DM
pin:
• You require data mask (
DM
) pins only while writing to the external memory devices.
• A low signal on the
DM
pin indicates that the write is valid.
• Driving the
DM
pin high causes the memory to mask the
DQ
signals.
• Similar to the DQ output signals, the DM signals are clocked by the –90º shifted clock.
LPDDR2 Address and Control/Command Pins
For LPDDR2 interfaces, the address signals and the control or command signals are sent at double data rate.
You can use any of the user I/O pins on all I/O banks of MAX 10 devices to generate the address and control or command signals to the external memory device.
Memory Clock Pins
At the external memory device, the memory clock signals (CK and CK#) are used to capture the address signals, and the control or command signals.
In MAX 10 devices, the double data rate I/O (DDIO) registers are used to generate the CK/CK# signals.
The memory clock pins are predefined and are listed in the device pinout files. Refer to the the relevant device pinout files to determine the locations of the memory clock pins.
Related Information
•
Pin Connection Guidelines Tables, Planning Pin and FPGA Resources chapter, External Memory
Interface Handbook
Provides more information about CK/CK# pins placement.
•
MAX 10 Device Pin-Out Files
LPPDDR2 Power Supply Variation Constraint
For an LPDDR2 interface that targets 200 MHz, constrain the memory device I/O and core power supply variation to within ±3%.
• Memory I/O power supply pin is
VDDQ
• Memory core power supply pin is
VDD
Related Information
MAX 10 Power Management User Guide
MAX 10 External Memory Interface Design Considerations
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LPDDR2 Recommended Termination Schemes for MAX 10 Devices
LPDDR2 Recommended Termination Schemes for MAX 10 Devices
Table 3-3: Supported External Memory Interface Termination Scheme for LPDDR2
Memory Interface
Standard
LPDDR2
I/O Standard
HSUL-12
R
S
OCT
34, 40, 48
R
UP
, R
DN
(Ω)
34, 40, 48
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Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface
I/O Limitation
While implementing certain external memory interface standards, the number of I/O pins available is limited.
• While implementing DDR2—for 25 percent of the remaining I/O pins available in I/O banks 5 and 6, you can assign them only as input pins.
• While implementing DDR3 or LPDDR2—the I/O pins listed in the following table are not available for use. Of the remaining I/O pins, you can assign only 75 percent of the available I/O pins in I/O banks 5 and 6 for normal I/O operation.
Table 3-4: Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in
Certain Device Packages—Preliminary
Device
10M16
F256
N16
P16
U324
R15
P15
R18
P18
E16
D16
Package
F484
U21
U22
M21
L22
F21
F20
E19
F18
F672
—
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Device
10M25
10M40
10M50
Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O
Limitation
Package
F256 U324 F484 F672
N16
P16
— U21
U22
M21
L22
F21
F20
E19
F18
F17
E17
—
N16
P16
— U21
U22
M21
L22
F21
F20
E19
F18
F17
E17
W23
W24
U25
U24
T24
R25
R24
P25
K23
K24
J23
H23
G23
F23
G21
G22
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Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
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Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and
LPDDR2
• For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
• To minimize unwanted inductance from the board via, Altera recommends that you keep the PCB via depth for V
CCIO
banks below 49.5 mil.
• For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Altera recommends that you use termination resistor value of 80 Ω to V
TT
.
• For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for
DDR3, or less than three inches for LPDDR2.
Related Information
•
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
•
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
•
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
•
MAX 10 FPGA Signal Integrity Design Guidelines
Provides design guidelines related to signal integrity for MAX 10 devices.
Guidelines: Reading the MAX 10 Pin-Out Files
For the maximum number of DQ pins and the exact number per group for a particular MAX 10 device, refer to the relevant device pin-out files.
In the pin-out files, the
DQS
and
DQSn
pins denote the differential data strobe/clock pin pairs. The
DQS
and
DQSn
pins are listed in the MAX 10 pin-out files as
DQSXR
and
DQSnXR
:
•
X
indicates the DQ/DQS grouping number.
•
R
indicates the location of the group which is always on the right side of the device.
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MAX 10 External Memory Interface
Implementation Guides
2014.12.15
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You can implement your external memory interface design in the Quartus II software. The software contains tools for you to create and compile you design, and configure your device.
In the Quartus II software, you can instantiate and configure the UniPHY IP core to suit your memory interface requirement.
Related Information
•
MAX 10 External Memory Interface Overview
on page 1-1
•
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
•
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
•
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
4
UniPHY IP Core
The UniPHY IP core allows you to control the soft IP of the MAX 10 external memory interface solution.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
4-2
IP Catalog and Parameter Editor
Figure 4-1: MAX 10 UniPHY IP Core Block Diagram
External Memory Interface IP
PLL
I/O Structure
Reference Clock
External
Memory
Device
DQ I/O
I/O Block
PHY
Calibration
Sequencer
Write Path
Read Path
Address/Command
Path
Memory
Controller
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IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.
Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Qsys system file (
.qsys
) or Quartus II IP file (
.qip
) representing the IP core in your project. You can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation.
• Click Search for Partner IP, to access partner IP information on the Altera website.
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Figure 4-2: Quartus II IP Catalog
Specifying IP Core Parameters and Options
4-3
Search for installed IP cores
Show IP only for target device
Double-click to customize, right-click for detailed information
Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating a System with Qsys in the Quartus II Handbook.
Related Information
Creating a System With Qsys, Volume 1: Design and Synthesis, Quartus II Handbook
Specifying IP Core Parameters and Options
You can quickly configure a custom IP variation in the parameter editor. Use the following steps to specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters
and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.
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Specifying IP Core Parameters and Options
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1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>
.qsys
. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.
• Optionally select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
• Specify parameters defining the IP core functionality, port configurations, and device-specific features.
• Specify options for processing the IP core files in other EDA tools.
4. Click Generate HDL, the Generation dialog box appears.
5. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
6. To generate a simulation testbench, click Generate > Generate Testbench System.
7. To generate an HDL instantiation template that you can copy and paste into your text editor, click
Generate > HDL Example.
8. Click Finish. The parameter editor adds the top-level
.qsys
file to the current project automatically. If you are prompted to manually add the
.qsys
file to the project, click Project > Add/Remove Files in
Project to add the file.
9. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
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Figure 4-3: IP Parameter Editor
Files Generated for Altera IP Cores (Legacy Parameter Editor)
4-5
View IP port and parameter details
Specify your IP variation name and target device
Apply preset parameters for specific applications
Files Generated for Altera IP Cores (Legacy Parameter Editor)
The Quartus II generates the following output for IP cores that use the legacy MegaWizard parameter editor.
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LPDDR2 External Memory Interface Implementation
Figure 4-4: IP Core Generated Files
<Project Directory>
<your_ip>.qip - Quartus II IP integration file
<your_ip>.v or .vhd - Top-level IP synthesis file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>.bsf - Block symbol schematic file
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist1
<your_ip>.vo or .vho - IP functional simulation model 2
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>.cmp - VHDL component declaration file
greybox_tmp
3
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
3. Ignore this directory
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LPDDR2 External Memory Interface Implementation
Figure 4-5: Top Level View of LPDDR2 Architecture in MAX 10 Devices
Core
Soft Memory
Controller
PLL clk[0] clk[1] clk[2] clk[3]
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
GCLK sys_clk phy_mem_clk dq_write_clk read_capture_clk dqs_tracking_clk
Periphery
Memory PHY
DQ x8 group
DQ x8 group
PHYCLK
Off FPGA
External Memory
Device
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Supported LPDDR2 Topology
4-7
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
Supported LPDDR2 Topology
For LPDDR2, the external memory interface IP for MAX 10 devices uses one capture clock and one tracking clock with one discrete device.
Figure 4-6: Supported Topology for LPDDR2 Memory Interfaces
This figure shows the supported LPDDR2 topology. Only one discrete LPDDR2 device is supported with a 16 bit maximum interface width. The memory interface IP in MAX 10 devices generates LPDDR2 IPs targeted for this configuration only.
FPGA
16
LPDDR2
CS
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DDR2 and DDR3 External Memory Interface Implementation
DDR2 and DDR3 External Memory Interface Implementation
Figure 4-7: Top Level View of DDR2, DDR3, or DDR3L Architecture in MAX 10 Devices
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Soft Memory
Controller
PLL clk[0] clk[1] clk[2] clk[3]
Core
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
DQ x8 group
(soft)
8 fr_resync_clk hr_resync_clk
GCLK sys_clk
Periphery
Memory PHY
DQ x8 group
DQ x8 group
DQ x8 group phy_mem_clk dq_write_clk read_capture_clk read_capture_ecc_clk
PHYCLK
Off FPGA
External Memory
Device
External Memory
Device
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
MAX 10 Supported DDR2 or DDR3 Topology
For DDR2 or DDR3/DDR3L, the external memory interface IP for MAX 10 devices uses two capture clocks with two discrete devices.
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MAX 10 Supported DDR2 or DDR3 Topology
Figure 4-8: Supported Topology for DDR2 or DDR3 Memory Interfaces
4-9
This figure shows the supported DDR2/DDR3 topology. One clock captures the lower 16 bit of data and the other clock captures the top 8 bit of data. The memory interface IP in MAX 10 devices generates
DDR2 or DDR3/DDR3L IPs targeted for this configuration only.
FPGA
16
DDR3
CS
8
DDR3
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UniPHY IP Core References for MAX 10
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For MAX 10 devices, there are three variations of the UniPHY IP core:
• DDR2 SDRAM Controller
• DDR3 SDRAM Controller
• LPDDR2 SDRAM Controller
Related Information
•
MAX 10 External Memory Interface Overview
on page 1-1
•
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
•
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
•
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
UniPHY Parameter Settings for MAX 10
You can set the parameter settings for the UniPHY IP core in the Quartus II software. There are six groups of options: PHY Settings, Memory Parameters, Memory Timing, Board Settings, Controller
Settings, and Diagnostics.
UniPHY Parameters—PHY Settings
There are three groups of options: General Settings, Clocks, and Advanced PHY Settings.
5
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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ISO
9001:2008
Registered
5-2
UniPHY Parameters—PHY Settings
Table 5-1: PHY Settings - General Settings
Parameter
Speed Grade
Generate PHY only
Description
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Specifies the speed grade of the targeted FPGA device that affects the generated timing constraints and timing reporting.
Note: For MAX 10 devices, DDR3 and LPDDR2 is supported only for speed grade –6, and DDR2 for speed grades –6 and –7.
Turn on this option to generate the UniPHY IP core without a memory controller.
If you turn on this option, the AFI interface is exported so that you can easily connect your own memory controller.
Table 5-2: PHY Settings - Clocks
Parameter
Memory clock frequency
Achieved memory clock frequency
PLL reference clock frequency
Rate on Avalon-MM interface
Achieved local clock frequency
Description
The frequency of the clock that drives the memory device. Use up to 4 decimal places of precision.
You can use the External Memory Spec Estimator to obtain the maximum supported frequency for your target memory configuration.
The actual frequency the PLL generates to drive the external memory interface (memory clock).
The frequency of the input clock that feeds the PLL. Use up to 4 decimal places of precision.
The width of data bus on the Avalon-MM interface.
The MAX 10 supports only Half rate, which results in a width of 4× the memory data width.
The actual frequency the PLL generates to drive the local interface for the memory controller (AFI clock).
Table 5-3: DDR3 SDRAM PHY Settings - Advanced PHY Settings
Parameter
Supply voltage
I/O standard
Description
The supply voltage and sub-family type of memory.
This option is available for DDR3 SDRAM only.
The I/O standard voltage.
Set the I/O standard according to your design’s memory standard.
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Parameter
Reconfigurable PLL location
UniPHY Parameters—Memory Parameters
Description
If you set the PLL used in the UniPHY IP core memory interface to be reconfigurable at run time, you must specify the location of the PLL.
This assignment generates a PLL that can only be placed in the given sides.
5-3
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported external memory interfaces in Altera devices.
UniPHY Parameters—Memory Parameters
There are three groups of options: Memory Parameters, Memory Topology, and Memory Initialization
Options.
Table 5-4: Memory Parameters
Use the Memory Parameters options group to apply the memory parameters from your memory manufacturer’s data sheet.
Parameter Description
Memory vendor
The vendor of the memory device. Select the memory vendor according to the memory vendor you use. For memory vendors that are not listed in the setting, select JEDEC with the nearest memory parameters and edit the parameter values according to the values of the memory vendor that you use. However, if you select a configuration from the list of memory presets, the default memory vendor for that preset setting is automatically selected.
Memory format
The format of the memory device.
This parameter is automatically set to Discrete Device.
Memory device speed grade
The maximum frequency at which the memory device can run.
Total interface width
The total number of DQ pins of the memory device. Limited to 8 to 24 bits.
DQ/DQS group size
The number of DQ bits per DQS group.
Number of DQS groups
The number of DQS groups is calculated automatically from the Total
interface width and the DQ/DQS group size parameters.
Number of chip selects
The number of chip-selects the IP core uses for the current device configuration.
Specify the total number of chip-selects according to the number of memory device.
This option is available for DDR2 and DDR3 SDRAM only.
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UniPHY Parameters—Memory Parameters
Parameter
Depth expansion
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Description
Specifies number of devices are expanded in depth. Only single chipselect is supported.
This option is available for LPDDR2 SDRAM only.
Number of clocks
The width of the clock bus on the memory interface.
Row address width
The width of the row address on the memory interface.
Column address width
The width of the column address on the memory interface.
Bank-address width
The width of the bank address bus on the memory interface.
Enable DM pins
Specifies whether the DM pins of the memory device are driven by the
FPGA. You can turn off this option to avoid overusing FPGA device pins when using x4 mode memory devices.
When you are using x4 mode memory devices, turn off this option for
DDR3 SDRAM.
You must turn on this option if you are using Avalon byte enable.
DQS# Enable
Turn on differential DQS signaling to improve signal integrity and system performance.
This option is available for DDR2 SDRAM only.
Table 5-5: Memory Parameters - Memory Topology (DDR3 SDRAM)
This options group is available for DDR3 SDRAM only.
Parameter
Fly-by topology
Description
Specifies whether the IP core uses fly-by topology in the layout of width-expanded discrete devices.
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UniPHY Parameters—Memory Parameters
Table 5-6: Memory Parameters - Memory Initialization Options (DDR3 SDRAM)
5-5
This table lists the memory initialization options for DDR3 SDRAM.
Parameter
Read burst type
Description
Specifies accesses within a given burst in sequential or interleaved order.
Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the
PHY Settings tab.
Mode Register 0
DLL precharge power down
Specifies whether the DLL in the memory device is off or on during precharge power-down.
Memory CAS latency setting
The number of clock cycles between the read command and the availability of the first bit of output data at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table.
Set this parameter according to the target memory speed grade and memory clock frequency.
Output drive strength setting
The output driver impedance setting at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Mode Register 1
Memory additive
CAS latency setting
The posted CAS additive latency of the memory device.
Enable this feature to improve command and bus efficiency, and increase system bandwidth. For more information about optimizing the memory controller, refer to related information.
ODT Rtt nominal value
The on-die termination resistance at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
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UniPHY Parameters—Memory Parameters
Mode Register 2
Parameter
Auto selfrefresh method
Selfrefresh temperature
Memory write
CAS latency setting
Dynamic ODT
(Rtt_WR) value
Description
Disable or enable auto selfrefresh.
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Specifies the selfrefresh temperature as Normal or
Extended.
The number of clock cycles from the releasing of the internal write to the latching of the first data in, at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table and set according to the target memory speed grade and memory clock frequency.
The mode of the dynamic ODT feature of the memory device. This is used for multi-rank configurations. For more guidelines about DDR2 and DDR3 SDRAM board layout, refer to the related information.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Table 5-7: Memory Parameters - Memory Initialization Options (DDR2 SDRAM)
This table lists the memory initialization options for DDR2 SDRAM.
Parameter
Burst length
Specifies the burst length.
Description
Read burst type
Specifies accesses within a given burst in sequential or interleaved order.
Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the
PHY Settings tab.
Mode Register 0
DLL precharge power down
Determines whether the DLL in the memory device is in slow exit mode or in fast exit mode during precharge power down. For more information, refer to memory vendor data sheet.
Memory CAS latency setting
Determines the number of clock cycles between the
READ command and the availability of the first bit of output data at the memory device. For more information, refer to memory vendor data sheet speed bin table.
Set this parameter according to the target memory speed grade and memory clock frequency.
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Mode Register 1
Mode Register 2
Parameter
Output drive strength setting
Memory additive
CAS latency setting
Memory on-die termination
(ODT) setting
SRT Enable
UniPHY Parameters—Memory Parameters
5-7
Description
Determines the output driver impedance setting at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Determines the posted CAS additive latency of the memory device.
Enable this feature to improve command and bus efficiency, and increase system bandwidth.
Determines the on-die termination resistance at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Determines the selfrefresh temperature (SRT). Select 1x
refresh rate for normal temperature (0-85C)or select 2x
refresh rate for high temperature (>85C).
Table 5-8: Memory Parameters - Memory Initialization Options (LPDDR2 SDRAM)
This table lists the memory initialization options for LPDDR2 SDRAM.
Parameter
Burst Length
Specifies the burst length.
Description
Read Burst Type
Mode Register 1
Specifies accesses within a given burst in sequential or interleaved order.
Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the
PHY Settings tab.
Mode Register 2 Memory CAS latency setting
Determines the number of clock cycles between the
READ command and the availability of the first bit of output data at the memory device.
Set this parameter according to the target memory interface frequency. Refer to memory data sheet and also target memory speed grade.
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UniPHY Parameters—Memory Timing
Mode Register 3
Parameter
Output drive strength settings
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Description
Determines the output driver impedance setting at the memory device.
To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.
Related Information
•
External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design
Flow
Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow.
•
External Memory Interface Handbook Volume 2: Design Guidelines
Provides more information about using Altera devices for external memory interfaces including memory selection, board design, implementing memory IP cores, timing, optimization, and debugging.
•
Functional Description—MAX 10 EMIF
Provides more information about implementing memory IP cores for MAX 10 devices.
UniPHY Parameters—Memory Timing
Use the Memory Timing options to apply the memory timings from your memory manufacturer’s data sheet.
Table 5-9: Memory Timing
For each parameter, refer to the memory vendor data sheet.
Parameter Applies To Description
tIS (base) tIH (base) tDS (base) tDH (base) tDQSQ tQHS
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2,
LPDDR2
Address and control setup to CK clock rise.
Address and control hold after CK clock rise.
Data setup to clock (DQS) rise.
Data hold after clock (DQS) rise.
DQS, DQS# to DQ skew, per access.
DQ output hold time from DQS, DQS#
(absolute time value).
tQH DDR3
DQ output hold time from DQS, DQS#
(percentage of tCK).
tDQSCK DDR2, DDR3,
LPDDR2
DQS output access time from CK/CK#.
Set According To
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
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Parameter
tDQSCK Delta
Short tDQSCK Delta
Medium tDQSCK Delta
Long tDQSS tDQSH tQSH tDSH tDSS tINIT tMRD tMRW tRAS tRCD tRP tREFI tREFIab tRFC
UniPHY Parameters—Memory Timing
5-9
Applies To
LPDDR2
Description
Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160 ns rolling window.
LPDDR2
Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 1.6 µs rolling window.
LPDDR2
Absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 32ms rolling window.
DDR2, DDR3,
LPDDR2
First latching edge of DQS to associated clock edge (percentage of tCK).
DDR2,
LPDDR2
DDR3
DQS Differential High Pulse Width
(percentage of tCK). Specifies the minimum high time of the DQS signal received by the memory.
DDR2, DDR3,
LPDDR2
DQS falling edge hold time from CK
(percentage of tCK).
DDR2, DDR3,
LPDDR2
DQS falling edge to CK setup time (percentage of tCK).
DDR2, DDR3,
LPDDR2
DDR2, DDR3
LPDDR2
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
Memory initialization time at power-up.
Load mode register command period.
Active to precharge time.
Active to read or write time.
DDR2, DDR3,
LPDDR2
Precharge command period.
DDR2, DDR3 Refresh command interval.
LPDDR2
Refresh command interval (all banks).
DDR2, DDR3 Auto-refresh command interval.
Set According To
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade
Memory speed grade and tempera‐ ture range
Memory speed grade
Memory device capacity
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tWR
UniPHY Parameters—Board Settings
Parameter
tRFCab tWTR tFAW tRRD tRTP
Applies To
LPDDR2
Description
Auto-refresh command interval (all banks).
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
Write recovery time.
Write to read period.
Calculate the value based on the memory clock frequency.
DDR2, DDR3,
LPDDR2
DDR2, DDR3,
LPDDR2
Four active window time.
RAS to RAS delay time.
Calculate the value based on the memory clock frequency.
DDR2, DDR3,
LPDDR2
Read to precharge time.
Calculate the value based on the memory clock frequency.
grade
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Set According To
Memory device capacity
Memory speed
Memory speed grade and memory clock frequency
Memory speed grade and page size
Memory speed grade, page size and memory clock frequency
Memory speed grade and memory clock frequency
UniPHY Parameters—Board Settings
There are three groups of options: Setup and Hold Derating, Channel Signal Integrity, and Board
Skews.
Table 5-10: Board Settings - Setup and Hold Derating
The slew rate of the output signals affects the setup and hold times of the memory device, and thus the write margin. You can specify the slew rate of the output signals to see their effect on the setup and hold times of both the address and command signals and the DQ signals, or alternatively, you may want to specify the setup and hold times directly. You should enter information derived during your PCB development process of prelayout (line) and postlayout (board) simulation.
Parameter Description
Derating method
Derating method. The default settings are based on Altera internal board simulation data. To obtain accurate timing analysis according to the condition of your board, Altera recommends that you perform board simulation and enter the slew rate in the Quartus II software to calculate the derated setup and hold time automatically or enter the derated setup and hold time directly.
CK/CK# slew rate (differential)
CK/CK# slew rate (differential).
Address/Command slew rate
Address and command slew rate.
DQS/DQS# slew rate (Differen‐ tial)
DQ slew rate
DQS and DQS# slew rate (differential).
DQ slew rate.
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tIS tIH tDS tDH
Parameter
UniPHY Parameters—Board Settings
Description
Address/command setup time to CK.
Address/command hold time from CK.
Data setup time to DQS.
Data hold time from DQS.
5-11
Table 5-11: Board Settings - Channel Signal Integrity
Channel signal integrity is a measure of the distortion of the eye due to intersymbol interference, crosstalk, or other effects. Typically, when going from a single-rank configuration to a multi-rank configuration there is an increase in the channel loss, because there are multiple stubs causing reflections. Although the Quartus II timing models include some channel uncertainty, you must perform your own channel signal integrity simulations and enter the additional channel uncertainty, relative to the reference eye, into the parameter editor.
Parameter Description
Derating method
Choose between default Altera settings (with specific Altera boards) or manually enter board simulation numbers obtained for your specific board.
Address and command eye reduction (setup)
The reduction in the eye diagram on the setup side (or left side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI. (For single rank designs, ISI can be zero; in multirank designs, ISI is necessary for accurate timing analysis.)
Address and command eye reduction (hold)
The reduction in the eye diagram on the hold side (or right side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI.
Write DQ eye reduction
Read DQ eye reduction
The total reduction in the eye diagram due to ISI on DQ signals compared to a case when there is no ISI. Altera assumes that the ISI reduces the eye width symmetrically on the left and right side of the eye.
Write Delta DQS arrival time
Read Delta DQS arrival time
The increase in variation on the range of arrival times of DQS compared to a case when there is no ISI. Altera assumes that the ISI causes DQS to further vary symmetrically to the left and to the right.
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UniPHY Parameters—Board Settings
Table 5-12: Board Settings - Board Skews
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PCB traces can have skews between them that can reduce timing margins. Furthermore, skews between different chip selects can further reduce the timing margin in multiple chip-select topologies. This section allows you to enter parameters to compensate for these variations.
Note: Altera recommends that you use the Board Skew Parameter Tool to help you calculate the board skews. For more information, refer to the related information section.
Description Parameter
Maximum CK delay to DIMM/device
The delay of the longest CK trace from the FPGA to the memory device is expressed by the following equation:
Maximum DQS delay to DIMM/ device
Where n is the number of memory clock and r is number rank of device.
The delay of the longest DQS trace from the FPGA to the memory device, whether on a DIMM or the same PCB as the FPGA is expressed by the following equation:
Where n is the number of DQS and r is number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank
DIMM, the maximum DQS delay is expressed by the following equation:
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Parameter
Minimum delay difference between
CK and DQS
UniPHY Parameters—Board Settings
5-13
Description
The minimum skew or smallest positive skew (or largest negative skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all
DIMMs/devices is expressed by the following equation:
Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementa‐ tion, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the minimum delay difference between CK and DQS is expressed by the following equation:
This parameter value affects the write leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to nonleveling configurations of any number of ranks with the requirement that DQS must have positive margins in Timequest Report DDR.
For multiple boards, the minimum skew between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:
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UniPHY Parameters—Board Settings
Parameter
Maximum delay difference between
CK and DQS
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Description
The maximum skew or smallest negative skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all
DIMMs/devices is expressed by the following equation:
Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementa‐ tion, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the maximum delay difference between CK and DQS is expressed by the following equation:
This value affects the write Leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to non-leveling configurations of any number of ranks with the requirement that DQS must have positive margins in Timequest Report DDR.
For multiple boards, the maximum skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:
Maximum skew within DQS group
The largest skew among DQ and DM signals in a DQS group. This value affects the read capture and write margins for DDR2 and DDR3 SDRAM interfaces in all configurations (single or multiple chip-select, DIMM or component).
For multiple boards, the largest skew between DQ and DM signals in a DQS group is expressed by the following equation:
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UniPHY Parameters—Board Settings
5-15
Parameter
Maximum skew between DQS groups
Description
The largest skew between DQS signals in different DQS groups. This value affects the resynchronization margin in memory interfaces without leveling such as DDR2
SDRAM and discrete-device DDR3 SDRAM in both single- or multiple chip-select configurations.
For multiple boards, the largest skew between DQS signals in different DQS groups is expressed by the following equation, if you want to use the same design for several different boards:
Average delay difference between
DQ and DQS
The average delay difference between each DQ signal and the DQS signal, calculated by averaging the longest and smallest DQ signal delay values minus the delay of DQS. The average delay difference between DQ and DQS is expressed by the following equation: where n is the number of DQS groups. For multi-rank or multiple CS configura‐ tion, the equation is:
Maximum skew within address and command bus
The largest skew between the address and command signals for a single board is expressed by the following equation:
For multiple boards, the largest skew between the address and command signals is expressed by the following equation, if you want to use the same design for several different boards:
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UniPHY Parameters—Controller Settings
Parameter
Average delay difference between address and command and CK
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Description
A value equal to the average of the longest and smallest address and command signal delay values, minus the delay of the CK signal. The value can be positive or negative. Positive values represent address and command signals that are longer than CK signals; negative values represent address and command signals that are shorter than CK signals. The average delay difference between address and command and CK is expressed by the following equation: where n is the number of memory clocks. For multi-rank or multiple CS configu‐ ration, the equation is:
The Quartus II software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins for DDR2 and
DDR3 SDRAM interfaces. You should derive this value through board simulation.
For multiple boards, the average delay difference between address and command and CK is expressed by the following equation, if you want to use the same design for several different boards:
Related Information
•
Analizing Timing of Memory IP chapter, External Memory Interface Handbook
Provides more information about derating method and measuring eye reduction.
•
Board Skew Parameter Tool
UniPHY Parameters—Controller Settings
There are four groups of options: Avalon Interface, Low Power Mode, Efficiency, and Configuration,
Status and Error Handling.
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Table 5-13: Controller Settings - Avalon Interface
UniPHY Parameters—Controller Settings
5-17
Parameter
Generate power-of-2 data bus widths for Qsys or SOPC Builder
Descriptions
Rounds down the Avalon-MM side data bus to the nearest power of 2.
You must enable this option for Qsys systems.
If this option is enabled, the Avalon data buses are truncated to 256 bits wide. One Avalon read-write transaction of 256 bit width maps to four memory beat transactions, each of 72 bits (8 MSB bits are zero, while
64 LSB bits carry useful content). The four memory beats may comprise an entire burst length-of-4 transaction, or part of a burstlength-of-8 transaction.
Generate SOPC Builder compatible resets
This option is not required when using the MegaWizard Plug-in
Manager or Qsys.
Maximum Avalon-MM burst length
Specifies the maximum burst length on the Avalon-MM bus. Affects the
AVL_SIZE_WIDTH
parameter.
Enable Avalon-MM byte-enable signal
When you turn on this option, the controller adds the byte enable signal (avl_be) for the Avalon-MM bus to control the data mask
(mem_dm) pins going to the memory interface. You must also turn on
Enable DM pins if you are turning on this option.
When you turn off this option, the byte enable signal (avl_be) is not enabled for the Avalon-MM bus, and by default all bytes are enabled.
However, if you turn on Enable DM pins with this option turned off, all write words are written.
Avalon interface address width
The address width on the Avalon-MM interface.
Avalon interface data width
The data width on the Avalon-MM interface.
Table 5-14: Controller Settings - Low Power Mode
Parameter
Enable Self-Refresh Controls
Enable Deep Power-Down
Controls
Enable Auto Power-Down
Description
Enables the self-refresh signals on the controller top-level design. These controls allow you to control when the memory is placed into selfrefresh mode.
Enables the Deep-Powerdown signals on the controller top level. These controls allow you to control when the memory is placed in Deep-
Powerdown mode.
This option is available only for LPDDR2 SDRAM.
Allows the controller to automatically place the memory into powerdown mode after a specified number of idle cycles. Specifies the number of idle cycles after which the controller powers down the memory in the auto-power down cycles parameter.
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UniPHY Parameters—Controller Settings
Parameter
Auto Power-Down Cycles
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Description
The number of idle controller clock cycles after which the controller automatically powers down the memory. The legal range is from 1 to
65,535 controller clock cycles.
Table 5-15: Controller Settings - Efficiency
Parameter
Enable User Auto-Refresh
Controls
Description
Enable Auto-Precharge Control Enables the autoprecharge control on the controller top level. Asserting the autoprecharge control signal while requesting a read or write burst allows you to specify whether the controller should close (autopre‐ charge) the currently open page at the end of the read or write burst.
Local-to-Memory Address
Mapping
Enables the user auto-refresh control signals on the controller top level.
These controller signals allow you to control when the controller issues memory autorefresh commands.
Allows you to control the mapping between the address bits on the
Avalon-MM interface and the chip, row, bank, and column bits on the memory:
• Chip-Row-Bank-Col—improves efficiency with sequential traffic.
• Chip-Bank-Row-Col—improves efficiency with random traffic.
• Row-Chip-Bank-Col—improves efficiency with multiple chip select and sequential traffic.
Command Queue Look-Ahead
Depth
Selects a look-ahead depth value to control how many read or writes requests the look-ahead bank management logic examines. Larger numbers are likely to increase the efficiency of the bank management, but at the cost of higher resource usage. Smaller values may be less efficient, but also use fewer resources. The valid range is from 1 to 16.
Enable Reordering
Allows the controller to perform command and data reordering that reduces bus turnaround time and row/bank switching time to improve controller efficiency.
Starvation limit for each command
Specifies the number of commands that can be served before a waiting command is served. The valid range is from 1 to 63.
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UniPHY Parameters—Diagnostics
Table 5-16: Controller Settings - Configuration, Status and Error Handling
5-19
Parameter
Enable Configuration and Status
Register Interface
Description
Enables run-time configuration and status interface for the memory controller. This option adds an additional Avalon-MM slave port to the memory controller top level, which you can use to change or read out the memory timing parameters, memory address sizes, mode register settings and controller status. If Error Detection and
Correction Logic is enabled, the same slave port also allows you to control and retrieve the status of this logic.
CSR port host interface
Specifies the type of connection to the CSR port. The port can be exported, internally connected to a JTAG Avalon Master, or both:
• Internal (JTAG)—connects the CSR port to a JTAG Avalon
Master.
• Avalon-MM Slave —exports the CSR port.
• Shared—exports and connects the CSR port to a JTAG Avalon
Master.
Enable Error Detection and
Correction Logic
Enables ECC for single-bit error correction and double-bit error detection. MAX 10 devices supports ECC only for 16 bits + 8 bits ECC memory configuration.
Enable Auto Error Correction
Allows the controller to perform auto correction when a single-bit error is detected by the ECC logic.
To turn this on, you must first turn on Enable Error Dectection and
Correction Logic.
UniPHY Parameters—Diagnostics
There is one option group supported for MAX 10 devices: Simulation Options.
Table 5-17: Diagnostics - Simulation Options
Parameter Description
Enable verbose memory model output Turn on this option to display more detailed information about each memory access during simulation.
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Memory Interface User Guide
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Document Revision History for MAX 10 External Memory Interface User
Guide
Date
May 2015
Version Changes
2015.05.04 • Updated the footnote in the topic about external memoy interface support and performance to specify that the default maximum frequency for LPDDR2 is 167 MHz.
• Removed the F672 package from the 10M25 device.
• Removed the note about contacting Altera for DDR3, DDR3L,
DDR2, and LPDDR2 external memory interface support. The
Quartus II software supports these external memory interfaces from version 15.0.
• Added a topic about the PHYCLK network.
• Moved information about recommended LPDDR2 termination scheme into a new topic under LPDDR2 design considerations section. The information was previously in the topic about recommended DDR2/DDR3 termination schemes.
• Updated the guidelines about board design requirement to improve clarity.
• Updated and added related information links to relevant informa‐ tion.
• Added a topic about the low power feature available from version
15.0 of the Quartus II software.
• Updated the topic about the phase detector to add a figure showing the VT tracking system overview.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Document Revision History for MAX 10 External Memory Interface User Guide
Date
December 2014
September 2014
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Version Changes
2014.12.15 • Changed Altera MAX 10 EMIF IP core to UniPHY IP core.
• Removed reference to DIMM in a footnote under the table that lists the termination recommendations for DDR2 component. The
UniPHY IP core for MAX 10 does not support DIMM.
• Added a list of the MAX 10 memory controller features.
• Added "Preliminary" tag to the table that lists the I/Os unavailable in certain MAX 10 packages while implementing DDR3 or
LPDDR2 external memory interfaces.
• Updated the board design requirement with additional guidelines.
• Added information for the MAX 10 external memory interface
UniPHY IP core. This addition includes the chapters about external memory interface implementation and IP core references.
• Edited texts and added related information links to improve clarity.
2014.09.22 Initial release.
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Table of contents
- 24 MAX 10 External Memory Interface Overview
- 24 MAX 10 External Memory Interface Support and Performance
- 25 MAX 10 External Memory Interface Architecture and Features
- 25 MAX 10 I/O Banks for External Memory Interface
- 25 MAX 10 DQ/DQS Groups
- 25 MAX 10 Memory Controller
- 25 MAX 10 External Memory Read Datapath
- 25 DDR Input Registers
- 25 MAX 10 External Memory Write Datapath
- 25 DDR Output Registers
- 25 MAX 10 Address/Command Path
- 25 MAX 10 PHY Clock (PHYCLK) Network
- 25 Phase Detector for VT Tracking
- 25 On-Chip Termination
- 25 Phase-Locked Loop
- 25 MAX 10 Low Power Feature
- 26 MAX 10 External Memory Interface Design Considerations
- 26 MAX 10 DDR2 and DDR3 Design Considerations
- 26 DDR2/DDR3 External Memory Interface Pins
- 26 DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
- 26 LPDDR2 Design Considerations
- 26 LPDDR2 External Memory Interface Pins
- 26 LPPDDR2 Power Supply Variation Constraint
- 26 LPDDR2 Recommended Termination Schemes for MAX 10 Devices
- 26 Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
- 26 Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR
- 26 Guidelines: Reading the MAX 10 Pin-Out Files
- 27 MAX 10 External Memory Interface Implementation Guides
- 27 UniPHY IP Core
- 27 IP Catalog and Parameter Editor
- 27 Specifying IP Core Parameters and Options
- 27 Files Generated for Altera IP Cores (Legacy Parameter Editor)
- 27 LPDDR2 External Memory Interface Implementation
- 27 Supported LPDDR2 Topology
- 27 DDR2 and DDR3 External Memory Interface Implementation
- 27 MAX 10 Supported DDR2 or DDR3 Topology
- 36 UniPHY IP Core References for MAX
- 36 UniPHY Parameter Settings for MAX
- 36 UniPHY Parameters—PHY Settings
- 36 UniPHY Parameters—Memory Parameters
- 36 UniPHY Parameters—Memory Timing
- 36 UniPHY Parameters—Board Settings
- 36 UniPHY Parameters—Controller Settings
- 36 UniPHY Parameters—Diagnostics