ISL91110IR

DATASHEET

High Efficiency Buck-Boost Regulator with 5.4A

Switches

ISL91110IR

The ISL91110IR is a high-current buck-boost switching regulator for systems using new battery chemistries. It uses Intersil’s proprietary buck-boost algorithm to maintain voltage regulation while providing excellent efficiency and very low output voltage ripple when the input voltage is close to the output voltage.

The ISL91110IR is capable of delivering at least 2A continuous output current (V

OUT

= 3.3V) over a battery voltage range of 2.5V to

4.35V. This maximizes the energy utilization of advanced single-cell

Li-ion battery chemistries that have significant capacity left at voltages below the system voltage. Its fully synchronous low

ON-resistance 4-switch architecture and a low quiescent current of only 35µA optimize efficiency under all load conditions.

The ISL91110IR supports standalone applications with a fixed 3.3V or 3.5V output voltage or adjustable output voltage with an external resistor divider. Output voltages as low as 1V or as high as 5.2V are supported.

The ISL91110IR requires only a single inductor and very few external components. Power supply solution size is minimized by its

2.5MHz switching frequency, allowing small size external components.

Features

• Accepts input voltages above or below regulated output voltage

• Automatic and seamless transitions between buck and boost modes

• Input voltage range: 1.8V to 5.5V

• Output current: up to 2A (PVIN = 3.4V, V

OUT

= 5V)

• Output current: up to 2A (PVIN = 2.5V, V

OUT

= 3.3V)

• Burst current: up to 3A (PVIN = 2.9V, V

OUT t = 4.6ms)

= 3.3V, t

ON

< 600µs,

• High efficiency: up to 95%

• 35µA quiescent current maximizes light load efficiency

• 2.5MHz switching frequency minimizes external component size

• Fully protected for short-circuit, over-temperature and undervoltage

• Small 4mmx4mm 20 Ld TQFN package

The ISL91110IR is available in a 4mmx4mm, 20 Ld TQFN package.

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

PART NUMBER ADJ or FIXED V

OUT

ISL91110IRNZ-T 3.3

ISL91110IRNZ-T7A 3.3

ISL91110IR2AZ-T 3.5

ISL91110IR2AZ-T7A 3.5

ISL91110IRAZ-T ADJ

ISL91110IRAZ-T7A ADJ

Applications

• Smartphones and tablet PCs

• Wireless communication devices

• Optical modules networking equipment

Related Literature

UG022 , “ISL91110IRx-EVZ Evaluation Boards User Guide”

V

IN

=

1.8V TO 5.5V

C

1

2x10µF

PVIN

ISL91110IRNZ

LX1

VIN

EN

LX2

VOUT

MODE

FB

L

1

1µH

V

OUT

= 3.3V

UP TO 3A

C

2

2x22µF

100

95

90

V

IN

= 4.2V

85

V

IN

= 3.6V

80

V

IN

= 3.3V

75

V

IN

= 3V

70

1 10 100

LOAD CURRENT (mA)

1000

FIGURE 2. EFFICIENCY: V

OUT

= 3.3V, T

A

= +25°C

April 17, 2015

FN8709.0

FIGURE 1. TYPICAL APPLICATION: V

OUT

= 3.3V

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

|

Copyright Intersil Americas LLC 2015. All Rights Reserved

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL91110IR

Block Diagram

4

LX1

5

LX2

1 2

6

7

PVIN

8

9

Q1

EN

11

VIN 10 VREF

EN

EN

Q2

VIN

MONITOR

THERMAL

SHUTDOWN

Q4

GATE

DRIVERS

AND

ANTI-SHOOT

THRU

Q3

+

CONTROL

VOUT

CLAMP

CURRENT

DETECT

EN

EN

OSC

+

COMP

-

ERROR

AMP

-

+

REF

VOLTAGE

PROG.

16 NC

ADJ

OUTPUT

FIXED

OUTPUT

15 FB

17

18

VOUT

19

20

3 PGND

13

14

SGND

12 MODE

FIGURE 3. BLOCK DIAGRAM

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Pin Configuration

LX2

1

LX2 2

PGND

3

LX1 4

LX1

5

ISL91110IR

(20 LD, 4X4 TQFN)

TOP VIEW

20 19 18 17 16

6 7

EPAD

8 9 10

15

FB

14 SGND

13

SGND

12 MODE

11

EN

ISL91110IR

Pin Descriptions

PIN #

6, 7, 8, 9,

PIN NAMES

PVIN

4, 5

3

1, 2

17, 18,

19, 20

12

10

11

13, 14

15

16

LX1

PGND

LX2

VOUT

MODE

VIN

EN

SGND

FB

NC

Epad

DESCRIPTION

Power input; Range: 1.8V to 5.5V. Connect

2x10μF capacitors to PGND.

Inductor connection, input side

Power ground for high switching current

Inductor connection, output side

Buck-boost regulator output; Connect

2x22μF capacitors to PGND for V

OUT and 3.5V applications, and 2x47µF

= 3.3V capacitors to PGND for V

OUT applications.

= 4.5V and 5V

Logic input, HIGH for auto PFM mode. LOW for forced PWM operation. Also, this pin can be used with an external clock sync input.

Range: 2.75MHz to 3.25MHz. Do not leave floating.

Supply input; Range: 1.8V to 5.5V.

Logic input, drive HIGH to enable device. Do not leave floating.

Analog ground pin

Voltage feedback pin, connect directly to the

VOUT pin for fixed output voltage versions.

No connect pin

Thermal pad, connect to PGND

Ordering Information

PART NUMBER

( Notes 1, 2, 3 )

ISL91110IRNZ-T

PART

MARKING

91110N

OUTPUT VOLTAGE

(V)

3.3

TEMP RANGE

(°C)

-40 to +85

PACKAGE

Tape and Reel

(RoHS Compliant)

20 Ld 4x4 TQFN

PKG.

DWG. #

L20.4X4C

ISL91110IRNZ-T7A

ISL91110IR2AZ-T

ISL91110IR2AZ-T7A

ISL91110IRAZ-T

91110N

911102

911102

91110A

3.3

3.5

3.5

ADJ

-40 to +85

-40 to +85

-40 to +85

-40 to +85

-40 to +85

20 Ld 4x4 TQFN

20 Ld 4x4 TQFN

20 Ld 4x4 TQFN

20 Ld 4x4 TQFN

20 Ld 4x4 TQFN

L20.4X4C

L20.4X4C

L20.4X4C

L20.4X4C

L20.4X4C

ISL91110IRAZ-T7A 91110A ADJ

ISL91110IRN-EVZ Evaluation Board for ISL91110IRNZ

ISL91110IR2A-EVZ

ISL91110IRA-EVZ

Evaluation Board for ISL91110IR2AZ

Evaluation Board for ISL91110IRAZ

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see product information page for ISL91110IR . For more information on MSL please see techbrief TB363 .

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ISL91110IR

Absolute Maximum Ratings

PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

FB (Adjustable Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V

FB (Fixed V

OUT

Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

SGND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

ESD Rating

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV

Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V

Charge Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV

Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Thermal Information

Thermal Resistance (Typical)

20 Ld 4x4 TQFN Package (

Notes 4 , 5

). . . .

JA

(°C/W)

JC

39

(°C/W)

4

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V

Max Load Current (V

Max Load Current (V

Max Load Current (V

IN

= 3.4V, V

IN

IN

= 2.9V, V

OUT

= 5V). . . . . . . . . . . . . . . . . . . . . . .2ADC

= 2.5V, V

OUT

OUT

= 3.3V) . . . . . . . . . . . . . . . . . . . . .2ADC

= 3.3V, t

ON

= 600µs, t = 4.6ms) . . . . . 3A

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

4.

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379

5. For

JC

, the “case temp” location is the center of the exposed metal pad on the package underside.

Analog Specifications

V

IN

= V

PVIN

= V

EN

= 3.6V, V

OUT

= 3.3V, L1 = 1µH, C1 = 2x10µF, C2 = 2x22µF, T

A

= +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V) unless specified otherwise.

TEST CONDITIONS

MIN

(

Note 6 )

TYP

(

Note 7 )

MAX

(

Note 6 )

UNITS SYMBOL

POWER SUPPLY

V

IN

V

UVLO

PARAMETER

Input Voltage Range

V

IN

Undervoltage Lockout Threshold

I

VIN

I

SD

V

V

IN

IN

Supply Current

Supply Current, Shutdown

OUTPUT VOLTAGE REGULATION

V

OUT

Output Voltage Range

Output Voltage Accuracy

V

FB

I

FB

V

OUT

/

V

IN

V

OUT

/

I

OUT

V

OUT

/

V

I

V

OUT

/

I

OUT

V

CLAMP

FB Pin Voltage Regulation

FB Pin Bias Current

Line Regulation, PWM Mode

Load Regulation, PWM Mode

Line Regulation, PFM Mode

Load Regulation, PFM Mode

Output Voltage Clamp

Output Voltage Clamp Hysteresis

DC/DC SWITCHING SPECIFICATIONS f

SW t

ONMIN

I

PFETLEAK

I

NFETLEAK

Oscillator Frequency

Minimum On Time

LX1 Pin Leakage Current

LX2 Pin Leakage Current

Rising

Falling

PFM mode, no external load on V

OUT

(

Note 8

)

EN = SGND, V

IN

= 3.6V

ISL91110IRAZ, I

OUT

= 100mA, V

IN

= 3.6V

V

IN

= 3.7V, V

OUT

= 3.3V, I

OUT

= 0mA, PWM mode

V

IN

= 3.7V, V

OUT

= 3.3V, I

OUT

= 1mA, PFM mode

For adjustable output version, V

IN

= 3.6V

For adjustable output version

I

OUT

5.5V

= 500mA, V

OUT

= 3.3V, V

IN

step from 2.3V to

V

IN

= 3.7V, V

OUT

= 3.3V, I

OUT

step from 0mA to

1000mA

I

OUT

5.5V

= 100mA, V

OUT

= 3.3V, V

IN

step from 2.3V to

V

IN

= 3.7V, V

OUT

= 3.3V, I

OUT

step from 0mA to

100mA

Rising

V

IN

= 3.6V

V

IN

= 3.6V

1.8

5.5

1.725

1.775

1.550

1.650

35

0.05

60

1.0

1.00

-2

-3

0.783

5.25

2.1

-1

-1

0.80

±5

±0.005

±12.5

±0.4

400

2.50

80

5.20

+2

+4

0.813

20

5.95

2.9

1

1

%

V

V

% nA mV/V

MHz ns

µA

µA

V

µA

V

V

µA mV/mA mV/V mV/mA

V mV

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ISL91110IR

Analog Specifications

V

IN

= V

PVIN

= V

EN

= 3.6V, V

OUT

= 3.3V, L1 = 1µH, C1 = 2x10µF, C2 = 2x22µF, T

A

= +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V) unless specified otherwise. (Continued)

SYMBOL PARAMETER

SOFT-START AND SOFT DISCHARGE t

SS

Soft-start Time

TEST CONDITIONS (

MIN

Note 6 ) (

TYP

Note 7 ) (

MAX

Note 6 ) UNITS

Time from when EN signal asserts to when output voltage ramp starts.

Time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in buck mode.

V

IN

= 4V, V

OUT

= 3.3V, I

O

= 200mA

Time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in boost mode.

V

IN

= 2V, V

OUT

= 3.3V, I

O

= 200mA

EN < V

IL

1

1

2 ms ms ms

R

DISCHG

V

OUT

POWER MOSFET

Soft-discharge ON-resistance

R

DSON_P

P-channel MOSFET ON-resistance

120 Ω

R

DSON_N

N-channel MOSFET ON-resistance

I

PK_LMT

P-channel MOSFET Peak Current Limit

PFM/PWM TRANSITION

Load Current Threshold, PFM to PWM

Load Current Threshold, PWM to PFM

Thermal Shutdown

Thermal Shutdown Hysteresis

V

V

V

V

V

V

IN

= 3.6V, I

IN

= 2.5V, I

IN

= 3.6V, I

IN

= 2.5V, I

IN

= 3.6V, V

IN

= 3.6V, V

O

= 200mA

O

= 200mA

O

= 200mA

O

= 200mA

OUT

= 3.3V

OUT

= 3.3V

4.9

47

62

40

55

5.4

200

75

155

30

5.9

mΩ mΩ mΩ mΩ

A mA mA

°C

°C

LOGIC INPUTS

I

LEAK

V

IH

Input Leakage

Input HIGH Voltage

V

IN

= 3.6V

V

IN

= 3.6V

1.4

0.05

1 µA

V

V

IL

Input LOW Voltage V

IN

= 3.6V

0.4

V

NOTES:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.

7. Typical values are for T

A

= +25°C and V

IN

= 3.6V.

8. Quiescent current measurements are taken when the output is not switching.

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Typical Performance Curves

Unless otherwise noted, operating conditions are: T

A

= +25°C, V

IN

= EN = 3.6V, L = 1µH,

C

1

= 2x10µF, C

2

= 2x22µF, V

OUT

= 3.3V, I

OUT

= 0A to 3A.

100

5.140

98

96

94

92

90

88

86

84

LOAD = 500mA

LOAD = 1000mA

LOAD = 100mA

82

80

2.5

3.0

3.5

V

IN

(V)

4.0

4.5

FIGURE 4. EFFICIENCY vs INPUT VOLTAGE (V

OUT

= 5V)

5.0

5.120

5.100

5.080

5.060

5.040

1

V

IN

= 3.6V

V

IN

= 3.3V

V

IN

= 3V

10 100

LOAD CURRENT (mA)

1000

FIGURE 5. OUTPUT VOLTAGE vs LOAD CURRENT (V

OUT

= 5V)

100

95

V

IN

= 3.6V

90

85

80

75

V

IN

= 3.3V

V

IN

= 4.2V

V

IN

= 3V

70

1 10 100

LOAD CURRENT (mA)

FIGURE 6. EFFICIENCY: V

OUT

= 5V, T

A

= +25°C

1000

3.340

3.320

3.300

3.280

3.260

V

IN

= 3.3V

V

IN

= 3.6V

V

IN

= 4.2V

V

IN

= 3V

3.240

1 10 100

LOAD CURRENT (mA)

1000

FIGURE 7. OUTPUT VOLTAGE vs LOAD CURRENT (V

OUT

= 3.3V)

100

98

96

94

92

90

88

86

84

82

LOAD = 500mA

LOAD = 1000mA

LOAD = 100mA

80

2.0

2.5

3.0

3.5

V

IN

(V)

4.0

4.5

FIGURE 8. EFFICIENCY vs INPUT VOLTAGE (V

OUT

= 3.3V)

5.0

130

120

110

100

90

80

70

60

50

40

30

1.5

V

OUT

= 5V

V

OUT

= 3.3V

2.5

3.5

V

IN

(V)

4.5

5.5

FIGURE 9. QUIESCENT CURRENT vs INPUT VOLTAGE (MODE = HIGH)

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Typical Performance Curves

Unless otherwise noted, operating conditions are: T

A

= +25°C, V

IN

= EN = 3.6V, L = 1µH,

C

1

= 2x10µF, C

2

= 2x22µF, V

OUT

= 3.3V, I

OUT

= 0A to 3A. (Continued)

LX1 (2V/DIV)

LX1 (2V/DIV)

LX2 (2V/DIV)

LX2 (2V/DIV)

V

OUT

(AC, 20mV/DIV)

I

L

(500mA/DIV)

400ns/DIV

FIGURE 10. STEADY STATE OPERATION IN PFM (V

IN

V

OUT

= 3.3V, NO LOAD)

= 4V,

V

OUT

(AC, 10mV/DIV)

I

L

(200mA/DIV)

400ns/DIV

FIGURE 11. STEADY STATE OPERATION IN PWM (V

IN

V

OUT

= 3.3V, NO LOAD)

= 4V,

EN (2V/DIV)

EN (2V/DIV)

V

OUT

(1V/DIV)

I

L

(500mA/DIV)

400µs/DIV

FIGURE 12. SOFT-START (V

IN

= 3.6V, V

OUT

= 3.3V, NO LOAD)

I

L

(1A/DIV)

LX1 (2V/DIV)

LX2 (2V/DIV)

V

OUT

(1V/DIV)

I

L

(500mA/DIV)

400µs/DIV

FIGURE 13. SOFT-START (V

IN

= 3.6V, V

OUT

= 3.3V, 1A RLOAD)

V

OUT

(AC, 200mV/DIV)

V

OUT

(AC, 50mV/DIV)

400ns/DIV

FIGURE 14. STEADY STATE OPERATION (V

2A LOAD)

IN

= 2.5V, V

OUT

= 3.3V,

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I

LOAD

(1A/DIV)

200µs/DIV

FIGURE 15. 0A TO 2A LOAD TRANSIENT (V

IN

= 3.6V, V

OUT

= 3.3V)

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ISL91110IR

Typical Performance Curves

Unless otherwise noted, operating conditions are: T

A

= +25°C, V

IN

= EN = 3.6V, L = 1µH,

C

1

= 2x10µF, C

2

= 2x22µF, V

OUT

= 3.3V, I

OUT

= 0A to 3A. (Continued)

V

OUT

(AC, 100mV/DIV)

V

OUT

(AC, 200mV/DIV)

I

LOAD

(500mA/DIV)

200µs/DIV

FIGURE 16. 0.5A TO 1.5A LOAD TRANSIENT (V

IN

= 3.6V, V

OUT

= 3.3V)

V

IN

(1V/DIV)

I

LOAD

(500mA/DIV)

100µs/DIV

FIGURE 17. 0A TO 1A LOAD TRANSIENT (V

IN

= 3.6V, V

OUT

= 3.3V)

V

OUT

(AC, 500mV/DIV)

V

OUT

(AC, 200mV/DIV)

20µs/DIV

FIGURE 18. 4V TO 3.2V LINE TRANSIENT (V

OUT

= 3.3V, LOAD = 1A)

I

LOAD

(1A/DIV)

200µs/DIV

FIGURE 19. 0.1A TO 2A LOAD TRANSIENT (V

IN

= 3.6V, V

OUT

= 5V)

V

OUT

(AC, 500mV/DIV)

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I

LOAD

(1A/DIV)

200µs/DIV

FIGURE 20. 0.5A TO 2A LOAD TRANSIENT (V

IN

= 3.6V, V

OUT

= 5V)

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ISL91110IR

Functional Description

Functional Overview

Refer to the “Block Diagram” on page 2 . The ISL91110IR

implements a complete buck boost switching regulator, with

PWM controller, internal switches, references, protection circuitry and control inputs.

The PWM controller automatically switches between buck and boost modes as necessary to maintain a steady output voltage with changing input voltages and dynamic external loads.

Internal Supply and References

Referring to the “Block Diagram” on page 2 , the ISL91110IR

provides four power input pins. The PVIN pin supplies input power to the DC/DC converter, while the VIN pin provides operating voltage source required for stable V

REF

generation. Separate ground pins (SGND and PGND) are provided to avoid problems caused by ground shift due to the high switching currents.

Enable Input

The device is enabled by asserting the EN pin HIGH. Driving EN

LOW invokes a power-down mode, where most internal device functions are disabled.

Soft Discharge

When the device is disabled by driving EN LOW, an internal resistor between VOUT and SGND is activated to slowly discharge the output capacitor. This internal resistor has a typical 120Ω resistance.

POR Sequence and Soft-start

Asserting the EN pin HIGH allows the device to power-up. A number of events occur during the start-up sequence. The internal voltage reference powers up and stabilizes. The device then starts to operate. There is a typical 1ms delay between assertion of the EN pin and the start of switching regulator soft-start ramp.

The soft-start feature minimizes output voltage overshoot and input in-rush currents. During soft-start, the reference voltage is ramped to provide a ramping V

OUT

voltage. While the output voltage is lower than approximately 20% of the target output voltage, switching frequency is reduced to a fraction of the normal switching frequency to aid in producing low duty cycles necessary to avoid input in-rush current spikes. Once the output voltage exceeds 20% of the target voltage, switching frequency is increased to its nominal value.

When the target output voltage is higher than the input voltage, there will be a transition from buck mode to boost mode during the soft-start sequence. At the time of this transition, the ramp rate of the reference voltage is decreased, such that the output voltage slew rate is decreased. This provides a slower output voltage slew rate.

The V

OUT

ramp time is not constant for all operating conditions.

Soft-start into boost mode will take longer than soft-start into buck mode. The total soft-start time into buck operating mode is typically 2ms, whereas the typical soft-start time into boost

PVIN

mode operating mode is typically 3ms. Increasing the load current will increase these typical soft-start times.

Short Circuit Protection

The ISL91110IR provides short-circuit protection by monitoring the feedback voltage. When feedback voltage is sensed to be lower than a certain threshold, the PWM oscillator frequency is reduced in order to protect the device from damage. The P-channel MOSFET peak current limit remains active during this state.

Thermal Shutdown

A built-in thermal protection feature protects the ISL91110IR, if the die temperature reaches +155°C (typical). At this die temperature, the regulator is completely shut down. The die temperature continues to be monitored in this thermal shutdown mode. When the die temperature falls to +125°C (typical), the device will resume normal operation. When exiting thermal shutdown, the

ISL91110IR will execute its soft-start sequence.

Buck-Boost Conversion Topology

The ISL91110IR operates in either buck or boost mode. When operating in conditions where PVIN is close to VOUT, ISL91110IR alternates between buck and boost mode as necessary to provide a regulated output voltage.

Figure 21

shows a simplified diagram of the internal switches and external inductor.

LX1

SWITCH A

SWITCH B

L

1

LX2

SWITCH D

SWITCH C

VOUT

FIGURE 21. BUCK BOOST TOPOLOGY

PWM Operation

In buck PWM mode, Switch D is continuously closed and

Switch C is continuously open. Switches A and B operate as a synchronous buck converter when in this mode.

In boost PWM mode, Switch A remains closed and Switch B remains open. Switches C and D operate as a synchronous boost converter when in this mode.

PFM Operation

During PFM operation in buck mode, Switch D is continuously closed and Switch C is continuously open. Switches A and B operate in discontinuous mode during PFM operation. During

PFM operation in boost mode, the ISL91110IR closes Switch A and Switch C to ramp up the current in the inductor. When the inductor current reaches a certain threshold, the device turns off

Switches A and C, then turns on Switches B and D. With Switches

B and D closed, output voltage increases as the inductor current ramps down.

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In most operating conditions, there will be multiple PFM pulses to charge up the output capacitor. These pulses continue until

V

OUT

has achieved the upper threshold of the PFM hysteretic controller. Switching then stops and remains stopped until V

OUT decays to the lower threshold of the hysteretic PFM controller.

Operation With V

IN

Close to V

OUT

When the output voltage is close to the input voltage, the

ISL91110IR will rapidly and smoothly switch from boost to buck mode as needed to maintain the regulated output voltage. This behavior provides excellent efficiency and very low output voltage ripple.

Output Voltage Programming

The ISL91110IR is available in fixed and adjustable output voltage versions. To use the fixed output version, the VOUT pin must be connected directly to FB.

In the adjustable output voltage version (ISL91110IRAZ), an external resistor divider is required to program the output voltage. The FB pin has very low input leakage current, so it is possible to use large value resistors (e.g., R

1

R

2

= 60.4kΩ for V the FB input.

OUT

= 187kΩ and

= 3.3V) in the resistor divider connected to

Applications Information

Component Selection

The fixed-output version of ISL91110IR requires only three external power components to implement the buck boost converter: an inductor, an input capacitor and an output capacitor.

The adjustable output version of ISL91110IR requires three additional components to program the output voltage, as shown

in Figure 22

. Two external resistors program the output voltage and a small capacitor is added to improve stability and response.

ISL91110IR

Output Voltage Programming, Adjustable

Version

When VREF is connected to SGND, setting and controlling the output voltage of the ISL91110IRAZ (adjustable output version) can be accomplished by selecting the external resistor values.

Equation 1 can be used to derive the R

1

and R

2

resistor values:

V

OUT

= 0.8V

1 +

R

1

R

2

(EQ. 1)

When designing a PCB, include a SGND guard band around the feedback resistor network to reduce noise and improve accuracy and stability. Resistors R

1 the FB pin.

and R

2

should be positioned close to

Feed-Forward Capacitor Selection

A small capacitor (C3 in

Figure 22

) in parallel with resistor R

1 required to provide the specified load and line regulation. The

is suggested value of this capacitor is 22pF for R

1

NPO type capacitor is recommended.

= 187kΩ. An

V

IN

=

1.8V TO 5.5V

ISL91110IRAZ

C

1

2x10µF

PVIN

LX1

VIN

EN

MODE

LX2

VOUT

FB

R

1

L

1

1µH

C

V

OUT

= 1V TO 5.2V

UP TO 3A

3

C

2

2x22µF

R

2

FIGURE 22. ADJUSTABLE OUTPUT APPLICATION

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ISL91110IR

MANUFACTURER

Coilcraft

Wurth Elektronik

MFR. PART NUMBER

XFL4020-102ME

7847730

TABLE 2. INDUCTOR VENDOR INFORMATION

DESCRIPTION DIMENSION (mm)

1µH, 20%, DCR = 10.8mΩ

typIsat = 5.4A (typ)

4x4x2.1

WEBSITE www.coilcraft.com

1µH, 20%, DCR = 14mΩ

typIsat = 5.72A (typ)

4x4.5x3.2

www.we-online.com

Inductor Selection

An inductor with high frequency core material (e.g., ferrite core) should be used to minimize core losses and provide good efficiency. The inductor must be able to handle the peak switching currents without saturating.

A 1µH inductor with ≥5.4A saturation current rating is recommended. Select an inductor with low DCR to provide good efficiency. In applications where radiated noise must be minimized, a toroidal or shielded inductor can be used.

PVIN and V

OUT

Capacitor Selection

The input and output capacitors should be ceramic X5R type with low ESL and ESR. The recommended input capacitor value is

2x10µF. The recommended input capacitor must meet the following requirements: Minimum type is X5R, minimum voltage rating is 16V and minimum case size is 0603. The recommended output capacitor value is 2x22µF for 3.3V and 3.5V V

OUT applications and 2x47µF for 4.5V and 5V V

OUT

applications. The recommended output capacitor must meet the following requirements: For 22µF, the minimum type is X5R, minimum voltage rating is 10V, and minimum case size is 0603. For 47µF, the minimum type is X5R, minimum voltage rating is 6.3V, and minimum case size is 0603.

TABLE 3. CAPACITOR VENDOR INFORMATION

MANUFACTURER SERIES WEBSITE

AVX

Murata

X5R

X5R www.avx.com

www.murata.com

Taiyo Yuden

TDK

X5R

X5R www.t-yuden.com

www.tdk.com

Recommended PCB Layout

Correct PCB layout is critical for proper operation of the

ISL91110IR. The following are some general guidelines for the recommended layout:

1. The input and output capacitors should be positioned as close to the IC as possible.

2. The ground connections of the input and output capacitors should be kept as short as possible. The objective is to minimize the current loop between the ground pads of the input and output capacitors and the PGND pins of the IC. Use vias, if required, to take advantage of a PCB ground layer underneath the regulator.

3. The analog ground pin (SGND) should be connected to a large/low-noise ground plane on the top or an intermediate layer on the PCB, away from the switching current path of

PGND. This ensures a low noise signal ground reference.

4. Minimize the trace lengths on the feedback loop to avoid switching noise pick-up. Vias should be avoided on the feedback loop to minimize the effect of board parasitic, particularly during load transients.

The LX1 and LX2 traces should be short and must be routed on the same layer as the IC.

FIGURE 23. RECOMMENDED LAYOUT

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ISL91110IR

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision.

DATE

April 17, 2015

REVISION

FN8709.0

Initial Release

CHANGE

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com

.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask .

Reliability reports are also available from our website at www.intersil.com/support

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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Package Outline Drawing

L20.4x4C

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 11/06

4.00

A

B

6

PIN 1

INDEX AREA

ISL91110IR

15

16

4X

2.0

16X

0.50

20

1

6

PIN #1 INDEX AREA

2 .70 ± 0 . 15

11

(4X) 0.15

TOP VIEW

10

20X 0.4 ± 0.10

5

6

4

0.10 M C A B

20X 0.25 +0.05 / -0.07

( 3. 8 TYP )

( 2. 70 )

0 . 90 ± 0 . 1

SEE DETAIL "X"

0.10

C

C

BASE PLANE

SEATING PLANE

0.08 C

( 20X 0 . 5 )

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

( 20X 0 . 25 )

( 20X 0 . 6)

C 0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

5

DETAIL "X"

NOTES:

1.

2.

3.

Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

4.

Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

5.

Tiebar shown (if present) is a non-functional feature.

6.

The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.

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