Schematic - Texas Instruments
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Major Component Product Pages
TI 66AK2L06 Product Page
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Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
TI ADC14X250 Product Page
A
TI LMK04828 Product Page
A
Table of Contents
Page Number
Page Name
Revision History
Page Description
Revision
Rev 1.0
B
11
k2l_soc_05.SchDoc
K2L Resets, Core PLL and SERDES PLL Inputs
13
k2l_soc_06_1.SchDoc
K2L Boot-Config, I2C, SPI, UART, Timer, and USIM
15
k2l_soc_08.SchDoc
K2L DFE JESD204B SYSREF, SYNCIN/OUT and DFE I/O
25
adc14x250_01.SchDoc
ADC power pins, power filtering and decoupling capacitors
26
adc14x250_02.SchDoc
ADC Input, JESD204B interface, SPI and discrete I/O control
30
lmk04828_01.SchDoc
LMK04828 power pins, power filtering and decoupling capacitors
31
lmk04828_02.SchDoc
Clock input, clock output, SPI and discrete I/O control
Notes
Initial revision release
B
C
C
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 1 of 35
File: CoverSheet_01.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
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TI66AK2L06 and ADC14X250 Example System Diagram
A
A
66AK2L06 SoC
SoC
Indicator LEDs
TM4C1231 H6PZ MCU
USB Connector
(System Terminal )
USB-to-UART
Bridge
UART System
Control
System
Indicator LEDs
GPIO
Resets/Pushbuttons
GPIO
DDR3A (72-bit)
DDR 3 SO-DIMM or
Discrete SDRAM
Array
EMIF16 (16-bit)
NAND Flash
SPI 0 (CS0)
NOR Flash
Reset/Boot/Config
Control
Reset/Boot Control
To ADC Clock Generation
JTAG Emulation
Header
GPIO[31:0]/BOOT/EMU
ADC14X250
Clock Solution
ADC14 X250
CLKIN +/-
VIN +/-
Balun
(If Required )
Filter
Input
Connector
JTAG
To DAC Clock Generation
From SYSREF Generator
SYSCLK
SYSREF+/-
DFE SYNCOUT
SYNCb +/-
JESD RX[0]
SO+/-
Clock Control
DDR3ACLK
CSISC 2_0_CLK
JESD RX[1]
MCU
Clock Solution
MCU Clocking
SGMIICLK
PCIECLK
VDD
MCU
Power Solution
System Power
Control
66 AK2L
Clock Solution
USBCLK
VA1.2
VDDA
VDDC
DFESYSREF
B
SPI
SPI 1 (CS0)
VA1.8
ADC14X250
VA3.0
Power Solution
BP2.5
B
SYSREF
Generation
To ADC SYSREF
Core DSP + ARM
AVS Supply
VCNTL
I2C 0
Digital SRAM
Supply
66 AK2L
Power Solution
Digital I/O
Supplies
1.8V
PLL/DLL Analog
Supplies
SERDES/USB
Analog Supplies
I2C0
I2C AccessoryIC
C
I2C1
C
I2C2
USB Connector
(Linux Terminal)
TI PoE Solution/
TI 1GigE PHY
Solution
USB-to-UART
Bridge
K2L Recommended
Ethernet Solution
UART0/SPI 2
CSIS2_2
SGMII[1:0]
MDIO
PCIe Card -Edge
Fingers /
PCIe Connector
CSIS2_3
PCIe[1:0]/SGMII[2:3]
USB3.0 Connector
USB 3.0 Super -Speed
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By: a0271760
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title: TI66AK2L06 and ADC14X250 Example System Diagram
Assembly Variant: 001
Sheet: 2 of 35
File: system_diagram.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
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TI66AK2L06 and ADC14X250 Example System Power Supply Diagram
A
A
TPS544B24 AVS Supply
PMBUS Control
66 AK2L06 SoC Power Nets
TPS73633DRB
Single -Channel LDO
TM4C1231 H6PZ MCU
Power Nets
3.3V, 400mA
Filter
VDD
Digital 3.3 V
VDDC
Digital 3.0 V
VDDA
Digital 3.3 V
TPS 65400
Quad-Channel
Buck Converter
66A2KL AVS Core
Supply
0.95V – 1.05V, 15A
Channel 4: 1.0V, 2A
K2L_CVDD 1V0
Channel 2: 1.8V, 4A
VSYS_DVDD 18
K2L_CVDD
CVDD
DSP /ARM
AVS Core (1.0-0.70 V)
VCNTL/I2C0
CVDD 1
AVS Control
DSP /ARM
Fixed Core (1.0V)
CDCM6208 v2
Power Nets
DVDD
DVDD 18
I/O Supply (1.8V)
Filter
Digital 1.8V
VDD _PRI _REF
VDD _SEC_REF
Primary Input 1.8V
Secondary Input1.8V
PMBUS Control
B
Channel 3: 0.85V, 2A
VSYS_DVDD 0V85
Filter
AVDDA 1
DDR3 A PLL Supply(1.8V)
Filter
VDD _VCO
VCO 1.8V
Filter
AVDDA 2
ARM PLL Supply(1.8V)
Filter
VDD _PLL1
PLL1 1.8V
Filter
AVDDA 3
Main PLL Supply(1.8V)
VDD _PLL2
PLL2 1.8V
Filter
AVDDA 4
PA PLL Supply (1.8V)
Filter
AVDDA 5
DFE PLL Supply(1.8V)
Filter
AVDDA 6
DDR3A DLL Supply(1.8V)
AVDDA 7
DDR3A DLL Supply(1.8V)
VDD _Y4
Outputs Y4 1.8V
AVDDA 8
DDR3A DLL Supply(1.8V)
VDD _Y5
Outputs Y5 1.8V
AVDDA 9
DDR3A DLL Supply(1.8V)
VDD _Y6
Outputs Y6 1.8V
AVDDA 10
DDR3A DLL Supply(1.8V)
VDD _Y7
Outputs Y7 1.8V
Filter
AVDDAHV
SERDES High Voltage (1.8V)
Filter
AVDDALV
SERDES Low Voltage (0.85 V)
Filter
VPTX
Filter
VDDUSB
Filter
VP
Filter
USB PHY
Transmit Supply (0.85 V)
USB Digital
I/O Supply (0.85 V)
USB PHY Low
Super -Speed Supply (0.85 V)
Filter
DVDD 33
Filter
VPH
Channel 1: 1.35/1.5V,
4A
Outputs Y0/Y 1 2 1.8V
VDD _Y2_Y3_1
Outputs Y2/Y3 1 1.8V
VDD _Y2_Y3_2
Outputs Y2/Y3 2 1.8V
VCC 1_VCO
USB Digital Supply(3.3V)
Filter
VCC 2_CG 1
USB PHY High
Super - Speed Supply (3.3V)
Filter
VCC 3_SYSREF
Filter
VCC 4_CG 2
Filter
VCC 6_PLL1
Filter
VCC 7_OSCOUT 1
Filter
VCC 8_OSCIN 1
TPS 65400
Quad-Channel
Buck Converter
C
Outputs Y0/Y1 1 1.8V
VDD _Y0_Y1_2
VCC 5_DIG
VSYS_DVDDR
DVDDR
DDR3 /DDR3 L I/O
Supply (1.35 /1.5V)
VDD
VREFSSTLA
VTT/VREF
Source-Sink
Regulator
TPS51200
PMBUS Control
B
LMK04828
Power Nets
VSYS_DVDD 3V3
Channel 1: 3.3V, 4A
VDD _Y0_Y1_1
SDRAM Core and
I/O Supply (1.35 V/1.5V)
DDR3 A I/O
Reference (DVDDR/2)
VREF
VTT
SDRAM I/O
Reference (VDD/2)
SDRAM
Termination (VDD/2)
ADC14 X250 Power Nets
Filter
VA1.8
Clock Group 1 3.3V
Clock Group 1 3.3V
SYSREF and SYNC 3.3V
Clock Group 2 3.3V
Digitial 3.3V
PLL1 3.3V
C
Oscillator Out 3.3V
Oscillator In 3.3V
Filter
VCC 9_CP 2
Filter
VCC 10_PLL2
PLL2 3.3V
Filter
VCC 11_CG 3
Clock Group 3 3.3V
Filter
VCC 12_CG 0
Clock Group 0 3.3V
Charge Pump 2 3.3V
Analog 1.8 V
Channel 3: 0.90V, 2A
VSYS_1V2
Filter
VA1.2
Analog 1.2 V
Channel 4: 1.9V, 2A
VSYS_3V0
Filter
VA3.0
Analog 3.0 V
Channel 2: Unused, 4A
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title: TI66AK2L06 and ADC14X250 Example System Power
Assembly Variant: 001
Sheet: 3 of 35
File: system_power_diagram.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
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TI66AK2L06 and ADC14X250 Example System Clocking Diagram
A
A
TM4C1231 H6PZ MCU
Reference Clocks
LMK04828 BISQ
I2C Control
RESET
16MHz XO
XOSC0
Primary Oscillator Input
SYNC /SYSREF_REQ
32.768KHz XO
XOSC1
Sleep Oscillator Input
Status_LD1
Status_LD2
19.2MHz TCXO
CLKin _0
ADC14 X250
Reference Clocks
CLKin _1
DCLKout_0
B
245.76 MHz
SDCLKout_1
DEVCLK
ADC Sampling Clock
/SERDES Clock
SYSREF
JESD 204 B SYSREF
B
JESD204 B SERDES TX : 4.9125 Gbps ,
DEVCLK = 245.76 MHz
66 AK2L06 SoC
Reference Clocks
DCLKout_4
122.88 MHz
SDCLKout_5
DCLKout_6
122.88 MHz
SYSCLK
DSP /ARM Main
PLL Reference Clock
DFESYSREF
JESD 204 B SYSREF
CSISC2_0_CLK
JESD 204 B PHY
Reference Clock
C
C
CDCM6208 v2
SPI Control
25MHz TCXO
OSCin
Y0
100 MHz
DDR 3ACLK
DDR3 Controller
PLL Reference Clock
Y1
156.25 MHz
SGMIICLK
SGMII SERDES Clock
Y2
100 MHz
PCIECLK
PCIe SERDES Clock
Y3
100 MHz
USBCLK
USB Clock
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title: TI66AK2L06 and ADC14X250 Example System Clocking
Assembly Variant: 001
Sheet: 4 of 35
File: system_clocking_diagram.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
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For schematic and layout recommendations
and requirements see the K2L product page
linked below.
5
6
VSYS_DVDD1V8
TI 66AK2L06 Product Page
PIR102
PIR202
K2L Reset and Core Configuration
PIR302
COR1
COR2
COR3
R1
R2
R3
A
PIR101
K2L BOOTMODE and RESET pins mastered
by Board Mangement Controller
(microcontroller) not shown here.
4
A
4.75k 4.75k 4.75k
PIR201
PIR301
K2L_RESETZ
K2L_RESETFULLZ
K2L_PORZ
K2L_LRESETZ
K2L_NMIZ
K2L_LRESETNMIENZ
COU1I
COU1J
U1I
NLK2L0RESETZ
K2L_RESETZ
NLK2L0RESETFULLZ
K2L_RESETFULLZ
NLK2L0PORZ
K2L_PORZ
AF3
PIU10AF3
NLK2L0LRESETZ
K2L_LRESETZ
NLK2L0NMIZ
K2L_NMIZ
NLK2L0LRESETNMIENZ
K2L_LRESETNMIENZ
AK3
PIU10AK3
AE2
PIU10AE2
G4
PIU10G4
AJ2
PIU10AJ2
AF2
PIU10AF2
RESETZ
RESETFULLZ
PORZ
AE4
RESETSTATZ PIU10AE4
AG3
BOOTCOMPLETE PIU10AG3
AH2
HOUT PIU10AH2
NLK2L0RESETSTATZ
K2L_RESETSTATZ
NLK2L0BOOTCOMPLETE
K2L_BOOTCOMPLETE
K2L_RESETSTATZ
K2L_BOOTCOMPLETE
LRESETZ
NMIZ
LRESETNMIENZ
PIR402
K2L RESETSTAT and BOOTCOMPLETE
monitored by System Controller
(microcontroller) not shown here.
PIR502
COR4
COR5
R4
R5
1.00k 1.00k
PIR401
PIR501
Resets and Core Config
NLK2L0CORESEL00BOOTMODE13
K2L_CORESEL0_BOOTMODE13
AE5
PIU10AE5
CORESEL0_BOOTMODE13
NLK2L0CORESEL10BOOTMODE14
K2L_CORESEL1_BOOTMODE14
AG6
PIU10AG6
CORESEL1_BOOTMODE14
NLK2L0CORESEL20BOOTMODE15
K2L_CORESEL2_BOOTMODE15
AH6
PIU10AH6
CORESEL2_BOOTMODE15
NLK2L0CORECLKSEL0
K2L_CORECLKSEL0
AE27
PIU10AE27
CORECLKSEL0
NLK2L0CORECLKSEL1
K2L_CORECLKSEL1
AF27
PIU10AF27
CORECLKSEL1
K2L_CORESEL0_BOOTMODE13
K2L_CORESEL1_BOOTMODE14
K2L_CORESEL2_BOOTMODE15
K2L_CORECLKSEL0
K2L_CORECLKSEL1
PIR602
PIR702
PIR802
COR6
COR7
COR8
R6
R7
R8
PIR601
1.00k 1.00k 1.00k
PIR701
PIR801
PIR902
PIR10 2
COR9
COR10
R9
R10
PIR901
1.00k 1.00k
PIR10 1
GND
TCI6630K2L
CORECLKSEL[1:0] = 0b00
Select SYSCLK as source for
K2L Main PLL
B
B
GND
GND
K2L Core Reference Clock Inputs
K2L PLLLOCK monitored by System
Controller (microcontroller) not shown
here.
U1J
Chip-Level PLL References Inputs
K2L SYSCLK sourced my LMK04828. When
utilizing LVDS outputs of LMK04828 only
AC-coupling is necessary.
NLK2L0SYSCLKP
K2L_SYSCLKP
K2L_SYSCLKP
K2L_SYSCLKN
NLK2L0SYSCLKN
K2L_SYSCLKN
COC267
NLK2L0SYSCLKP0CS
K2L_SYSCLKP_CS
C267
PIC26702 PIC267010.1µF
COC268
NLK2L0SYSCLKN0CS
C268
0.1µF
K2L_SYSCLKN_CS
PIC26802 PIC26801
AF29
PIU10AF29
AG29
PIU10AG29
K2L_ALTCORECLKP
K2L_ALTCORECLKN
DDR3 controller reference clock
solution not shown. Please see K2L
EVM schematics.
C
NLK2L0DDR3ACLKN
K2L_DDR3ACLKN
NLK2L0DDR3ACLKP
K2L_DDR3ACLKP
K2L_DDR3ACLKN
K2L_DDR3ACLKP
AG30
PIU10AG30
AH30
PIU10AH30
COC269
C269
0.1µF K2L_DDR3ACLKN
K2L_DDR3ACLKP
G30
PIC26902 PIC26901
COC270
C270
PIC27002 PIC270010.1µF
PIU10G30
F30
PIU10F30
SYSCLKP
SYSCLKN
ALTCORECLKP
ALTCORECLKN
AH29
PLLLOCK PIU10AH29
AF28
SYSCLKOUT PIU10AF28
AE29
RSV004 PIU10AE29
AE28
RSV005 PIU10AE28
NLK2L0PLLLOCK
K2L_PLLLOCK
NLK2L0SYSCLKOUT0RS
K2L_SYSCLKOUT_RS
COR11
R11
10.0
PIR1101
PIR1102
PIK2L0SYSCLKOUT01
COK2L0SYSCLKOUT
K2L_SYSCLKOUT
NLK2L0SYSCLKOUT
K2L_SYSCLKOUT
K2L_PLLLOCK
K2L_SYSCLKOUT_RS
PIR1202
COR12
R12
1.00k
PIR1201
DDR3ACLKN
DDR3ACLKP
C
GND
TCI6630K2L
VSYS_DVDD1V8
PIR1302
COR13
R13
Not utilizing ALTCORECLK.
Pull-up/down resistor necessary
to reserve off clock input.
PIR1301
PIR1402
1.00k
NLK2L0ALTCORECLKP
K2L_ALTCORECLKP
NLK2L0ALTCORECLKN
K2L_ALTCORECLKN
COR14
R14
1.00k
PIR1401
D
D
GND
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-14
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 11 of 35
File: k2l_soc_05.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
2
3
4
5
6
A
A
K2L Boot-Config, I2C, SPI, UART, Timer, and USIM
VSYS_DVDD1V8
PIR1502
PIR1602
COR15
COR16
R15
R16
4.75k 4.75k
PIR1501
TI K2L Demo 2 software
utilizes I2C_0 for
configuring/reading ADC
temperature sensor.
K2L_SCL1
K2L_SDA1
I2C0 utilized for Smart-Reflex
control of TPS544x24 CVDD
power supply. Solution not shown
here. Please see K2L EVM
schematics.
COU1N
U1N
UART0/SPI2
N2
PIU10N2
SCL0
M2
PIU10M2
SDA0
PIR1601
NLK2L0SCL1
K2L_SCL1
NLK2L0SDA1
K2L_SDA1
L3
PIU10L3
SCL1
M5
PIU10M5
SDA1
M3
PIU10M3
SCL2
M4
B
PIU10M4
TI K2L Demo 2 software
utilizes SPI_0 for
controlling ADC
K2L_SPI0CLK
K2L_SPI0SIMO
K2L_SPI0SOMI
K2L_SPI0SCS0
NLK2L0ADC0SPI0CLK
K2L_ADC_SPI0CLK
NLK2L0ADC0SPI0SIMO
K2L_ADC_SPI0SIMO
NLK2L0ADC0SPI0SOMI
K2L_ADC_SPI0SOMI
I2C0
COR17
R17
10.0
PIR1701
PIR1702
COR18
R18
10.0
PIR1801
PIR1802
NLK2L0ADC0SPI0CLK0RS
K2L_ADC_SPI0CLK_RS
NLK2L0ADC0SPI0SIMO0RS
K2L_ADC_SPI0SIMO_RS
NLK2L0ADC0SPI0SCS0
K2L_ADC_SPI0SCS0 COR19
R19
10.0 NLK2L0ADC0SPI0SCS00RS
K2L_ADC_SPI0SCS0_RS
PIR1901
PIR1902
L29
L27
SDA2
I2C1
I2C2
SPI0
K28
PIU10K28 SPI0SCS1
K30
PIU10K30
SPI0SCS2
K29
PIU10K29
SPI0SCS3
M29
PIU10M29 SPI0SCS4
M26
PIU10M26 SPI1CLK
N26
PIU10N26 SPI1SIMO
L26
PIU10L26
SPI1SOMI
B
TIMER0/Bootstrap
SPI0SIMO
N27
PIU10N27
SPI0SOMI
L30
PIU10L30
SPI0SCS0
K5
UART0RXD PIU10K5
K3
UART0TXD PIU10K3
K2
UART0RTS_SPI2SCS0 PIU10K2
L4
UART0CTS_SPI2CLK PIU10L4
UART1/SPI2
PIU10L29 SPI0CLK
PIU10L27
J5
UART1TXD PIU10J5
L5
UART1RXD PIU10L5
J4
UART1RTS_SPI2SIMO PIU10J4
K4
UART1CTS_SPI2SOMI PIU10K4
J2
TIMI0_AVSIFSEL0 PIU10J2
H3
TIMO0_CSISC20MUX PIU10H3
NLK2L0TIMI00AVSIFSEL0
K2L_TIMI0_AVSIFSEL0
NLK2L0TIMO00CSISC20MUX
K2L_TIMO0_CSISC20MUX
K2L_TIMI0
K2L_TIMO0
TIMER1/Bootstrap
J1
TIMI1_AVSIFSEL1 PIU10J1
J3
TIMO1_CSISC20CLKCTL PIU10J3
NLK2L0TIMI10AVSIFSEL1
K2L_TIMI1_AVSIFSEL1
NLK2L0TIMO10CSISC20CLKCTL
K2L_TIMO1_CSISC20CLKCTL
K2L_TIMI1
K2L_TIMO1
SPI1
M28
PIU10M28
SPI1SCS0
L28
M27
PIU10L28 SPI1SCS1
PIU10M27
SPI1SCS2
F3
PIU10F3
USIMCLK
C
F2
F1
PIU10F2 USIMIO
PIU10F1
USIMRST
C
USIM
TCI6630K2L
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 13 of 35
File: k2l_soc_06_1.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
2
For schematic and layout recommendations
and requirements see the K2L product page
linked below.
3
4
5
6
JESD204B SERDES shall be routed
according to routing rules specified in
the Keystone 2 SERDES User Guide
(SPRUH03)
DFE JESD204B SERDES
TI 66AK2L06 Product Page
Keystone2 SERDES User Guide (SPRUHO3)
A
A
COU1P
COU1S
U1P
CSISC2_0 - AIL/JESD
K2L_JESD_RXP0
K2L_JESD_RXN0
NLK2L0JESD0RXP0
K2L_JESD_RXP0
NLK2L0JESD0RXN0
K2L_JESD_RXN0
COC272
C272
0.1µF
PIC27202
NLK2L0JESD0RXP00CAP
K2L_JESD_RXP0_CAP
NLK2L0JESD0RXN00CAP
K2L_JESD_RXN0_CAP
PIC27201
PIC27302 PIC27301
COC273
C273
0.1µF
NLK2L0JESD0RXP10CAP
K2L_JESD_RXP1_CAP
NLK2L0JESD0RXN10CAP
K2L_JESD_RXN1_CAP
K2L_JESD_SERDES0_REFCLKP
K2L_JESD_SERDES0_REFCLKN
K2L JESD SERDES0/1 reference clock
sourced by LMK04828. When utilizing LVDS
outputs of LMK04828 no AC-coupling or
external bias or termination network is
necessary.
NLK2L0JESD0SERDES00REFCLKP
K2L_JESD_SERDES0_REFCLKP
NLK2L0JESD0SERDES00REFCLKN
K2L_JESD_SERDES0_REFCLKN
COJESDCLK0P
JESDCLK0P
COJESDCLK0N
JESDCLK0N
JESDTX[3:1] recievers are not
used in TI Demo 2. Unused K2L
SERDES RX shall be left as
no-connect pin.
AH18
SHARED_SERDES_0_TXP0 PIU10AH18
AH17
SHARED_SERDES_0_TXN0 PIU10AH17
NLK2L0JESD0TXP0
K2L_JESD_TXP0
NLK2L0JESD0TXN0
K2L_JESD_TXN0
AK19
PIU10AK19
SHARED_SERDES_0_RXP1
AG19
SHARED_SERDES_0_TXP1 PIU10AG19
AG18
SHARED_SERDES_0_TXN1 PIU10AG18
NLK2L0JESD0TXP1
K2L_JESD_TXP1
NLK2L0JESD0TXN1
K2L_JESD_TXN1
AK20
PIU10AK20
SHARED_SERDES_0_RXN1
AF17
PIU10AF17
SHARED_SERDES_0_REFCLKP
PIJESDCLK0P01
AF18
PIU10AF18
SHARED_SERDES_0_REFCLKN
PIJESDCLK0N01
JESDTX[3:0] transmiters are not
used in TI Demo 2. Unused K2L
SERDES TX shall be left as
no-connect pin.
AF20
PIU10AF20
RSV017
COR41
R41
NLK2L0SERDES00REF
K2L_SERDES0_REF
PIR4101
AJ18
SHARED_SERDES_0_RXP0
AJ19
PIU10AJ19
SHARED_SERDES_0_RXN0
PIU10AJ18
AE17
PIU10AE17
SHARED_SERDES_0_REFRES
PIR4102
3.0k
GND
CSISC2_1 - JESD
NLK2L0JESD0RXP20CAP
K2L_JESD_RXP2_CAP
NLK2L0JESD0RXN20CAP
K2L_JESD_RXN2_CAP
B
AH15
SHARED_SERDES_1_TXP0 PIU10AH15
AH14
SHARED_SERDES_1_TXN0 PIU10AH14
NLK2L0JESD0TXP2
K2L_JESD_TXP2
NLK2L0JESD0TXN2
K2L_JESD_TXN2
AK16
PIU10AK16
SHARED_SERDES_1_RXP1
AG16
SHARED_SERDES_1_TXP1 PIU10AG16
AG15
SHARED_SERDES_1_TXN1 PIU10AG15
NLK2L0JESD0TXP3
K2L_JESD_TXP3
NLK2L0JESD0TXN3
K2L_JESD_TXN3
AJ16
PIU10AJ16
SHARED_SERDES_1_RXN0
NLK2L0JESD0RXP30CAP
K2L_JESD_RXP3_CAP
NLK2L0JESD0RXN30CAP
K2L_JESD_RXN3_CAP
JESDTX[3:1] recievers are not
used in TI Demo 2. Unused K2L
SERDES RX shall be left as
no-connect pin.
AJ15
PIU10AJ15
SHARED_SERDES_1_RXP0
AK17
PIU10AK17 SHARED_SERDES_1_RXN1
NLK2L0JESD0SERDES10REFCLKP
K2L_JESD_SERDES1_REFCLKP
NLK2L0JESD0SERDES10REFCLKN
K2L_JESD_SERDES1_REFCLKN
B
AF14
PIU10AF14
SHARED_SERDES_1_REFCLKP
AF15
PIU10AF15
SHARED_SERDES_1_REFCLKN
AE15
PIU10AE15
RSV_018
NLK2L0SERDES10REF
K2L_SERDES1_REF
AE13
PIU10AE13
SHARED_SERDES_1_REFRES
TCI6630K2L
JESD204B SYSREF and SYNC shall be
utilized according to DFE User Guide
(SPRUHX8) and routed according to
Keystone 2 Hardware Design Guide
(SPRAVB0) DFE peripheral section.
DFE JESD204B SYSREF, SYNCIN/OUT and DFE I/O
Keystone2 Hardware Design Guide (SPRAVB0)
U1S
C
K2L SYSREF driven by
LMK04828
Digital Radio Front-End
COK2L0DFESYSREFP
K2L_DFESYSREFP
COK2L0DFESYSREFN
K2L_DFESYSREFN
K2L_DFESYSREFP
K2L_DFESYSREFN
COK2L0DFESYSREF0VSS
K2L_DFESYSREF_VSS
PIK2L0DFESYSREF0VSS01
Recommend including test
points near the DFESYSREF
pins.
PIK2L0DFESYSREFP01
PIK2L0DFESYSREFN01
NLK2L0DFESYSREFP
K2L_DFESYSREFP
NLK2L0DFESYSREFN
K2L_DFESYSREFN
AE30
AF30
DFESYSREFP
DFESYSREFN
AJ9
DFESYNCOUTP0 PIU10AJ9
AJ10
DFESYNCOUTN0 PIU10AJ10
NLK2L0DFESYNCOUT0P0
K2L_DFESYNCOUT_P0
NLK2L0DFESYNCOUT0N0
K2L_DFESYNCOUT_N0
AG12
DFESYNCINP0_RP1CLKP
DFESYNCINN0_RP1CLKN
AH11
DFESYNCOUTP1 PIU10AH11
AH12
DFESYNCOUTN1 PIU10AH12
NLK2L0DFESYNCOUT0P1
K2L_DFESYNCOUT_P1
NLK2L0DFESYNCOUT0N1
K2L_DFESYNCOUT_N1
PIU10AE30
PIU10AF30
NLDAC0DFESYNCINP0
DAC_DFESYNCINP0
NLDAC0DFESYNCINN0
DAC_DFESYNCINN0
PIU10AG12
AG13
PIU10AG13
NLK2L0DFESYNCIN0P1
K2L_DFESYNCIN_P1
NLK2L0DFESYNCIN0N1
K2L_DFESYNCIN_N1
PIU10AF10
NLK2L0DFEIO00
K2L_DFEIO0
K2L_DFEIO1
NLK2L0DFEIO01
PIU10AH5
AF10
AF11
PIU10AF11
C
K2L_DFESYNCOUT_P0
K2L_DFESYNCOUT_N0
K2L DFESYNCOUT0 drives
ADC SYNC input
DFESYNCINP1_RP1FBP
DFESYNCINN1_RP1FBN
NLK2L0DFEIO01700000
K2L_DFEIO[17..00]
AH5
DFEIO0
AJ5
DFEIO1
AG7
DFEIO2_GPIO48
AK5
PIU10AK5
DFEIO3_GPIO49
AH7
PIU10AH7 DFEIO4_GPIO50
AK6
PIU10AK6 DFEIO5_GPIO51
AJ7
PIU10AJ7 DFEIO6_GPIO52
AG8
PIU10AG8 DFEIO7_GPIO53
AK8
PIU10AK8 DFEIO8_GPIO54
AK7
PIU10AK7 DFEIO9_GPIO55
AG10
PIU10AG10
DFEIO10_GPIO56
AJ6
PIU10AJ6 DFEIO11_GPIO57
AK10
PIU10AK10 DFEIO12_GPIO58
AK9
PIU10AK9 DFEIO13_GPIO59
AF9
PIU10AF9 DFEIO14_GPIO60
AK11
PIU10AK11
DFEIO15_GPIO61
AG9
PIU10AG9 DFEIO16_GPIO62
AH9
PIU10AH9 DFEIO17_GPIO63
PIU10AJ5
NLK2L0DFEIO02
K2L_DFEIO2
NLK2L0DFEIO03
K2L_DFEIO3
NLK2L0DFEIO04
K2L_DFEIO4
NLK2L0DFEIO05
K2L_DFEIO5
NLK2L0DFEIO06
K2L_DFEIO6
NLK2L0DFEIO07
K2L_DFEIO7
K2L_DFEIO8
NLK2L0DFEIO08
NLK2L0DFEIO09
K2L_DFEIO9
NLK2L0DFEIO10
K2L_DFEIO10
NLK2L0DFEIO11
K2L_DFEIO11
NLK2L0DFEIO12
K2L_DFEIO12
K2L_DFEIO13
NLK2L0DFEIO13
NLK2L0DFEIO14
K2L_DFEIO14
NLK2L0DFEIO15
K2L_DFEIO15
NLK2L0DFEIO16
K2L_DFEIO16
NLK2L0DFEIO17
K2L_DFEIO17
D
PIU10AG7
D
TCI6630K2L
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 15 of 35
File: k2l_soc_08.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
2
3
4
5
6
For schematic and layout recommendations
and requirements see the ADC14X250 product
page linked below.
TI ADC14X250 Product Page
A
A
ADC Power Pins and Decoupling Capacitors
Decoupling caps shall be placed as close to ADC power pins as
possible. Utilize minimal via dog-bones (via-in pad ideally) to ensure
lowest possible mounting inductance.
VSYS_1V2
COL13
L13
PIL1301
PIC3COC350
5C350
01
PIC351µF
02
COU2A
U2A
B
NLVADC01V2A
VADC_1V2A
7
PIU207
17
PIU2017
28
PIU2028
NLVADC01V8A
VADC_1V8A
12
PIU2012
29
PIU2029
32
PIU2032
NLVADC02V50BYP
VADC_2V5_BYP
VA1.2
VA1.2
VA1.2
1.2V Analog
VA1.8
VA1.8
VA1.8
1.8V Analog
22
PIU2022
BP2.5
2.5V Bypass
31
AGND PIU2031
30
AGND PIU2030
27
AGND PIU2027
21
AGND PIU2021
18
AGND PIU2018
11
AGND PIU2011
8
AGND PIU208
5
AGND PIU205
2
AGND PIU202
1
PIU201
VA3.0
PIC101
PIC102
PIC201
PIC20
PIC301
PIC302
COC1COC2
COC3
C1
C2
C3
0.1µF
0.1µF
0.1µF
PIC401
PIC402
PIC501
PIC601
COC4
COC5
COC6 Each VA1.2 pin should include a 0.1uF and 0.01uF capacitor
C4
C5
C6
0.01µF
PIC502
PIC602
0.01µF
0.01µF
B
VSYS_1V8
COL1
L1
PIL101
PICCOC7
7C7
01
0
GND_PAD PIU200
VADC_1V8A
PIL102
120 ohm
PIC71µF
02
NLVADC03V0A
VADC_3V0A
VADC_1V2A
PIL1302
120 ohm
PIC801
PIC802
PIC901
PIC10 1
PIC1 01
COC8COC9
COC10
C8
C9
C10
0.1µF
0.1µF
0.1µF
PIC902
PIC10 2
PIC1 02
PIC1201
PIC1301
COC11
COC12
COC13 Each VA1.8 pin should include a 0.1uF and 0.01uF capacitor
C11
C12
C13
0.01µF
PIC1202
PIC1302
0.01µF
0.01µF
3.0V Analog
ADC14X250
VSYS_2V5
COL2
L2
The ADC14X250 thermal pad (Pin 0) provides thermal dissipation for
the ADC. Please ensure layout includes ground stitching vias to create
a good thermal coupling between the ADC GND pad and the PCB
GND layers
PIL201
PIC1COC14
4C14
01
VADC_2V5_BYP
PIL202
120 ohm
PIC141µF
02
PIC1501
PIC1502
PIC1601
COC15
C15
0.1µF
PIC1602
COC16
C16
Each BP2.5 pin should include a 0.1uF and 0.01uF capacitor
0.01µF
C
C
VSYS_3V0
COL3
L3
PIL301
PIC1COC17
7C17
01
PIC171µF
02
VADC_3V0A
PIL302
120 ohm
PIC1801
PIC1802
PIC1901
COC18
C18
0.1µF
PIC1902
COC19
C19
Each VA3.0 pin should include a 0.1uF and 0.01uF capacitor
0.01µF
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 25 of 11
File: adc14x250_01.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
2
3
4
5
6
For schematic and layout recommendations
and requirements see the ADC14X250 product
page linked below.
TI ADC14X250 Product Page
A
A
ADC Input, JESD204B Interface, SPI and Discrete I/O Control
AC-coupling capacitors and termination
resistors shall be placed as close as
possible to the input pads of the ADC.
Recommend including test-points for
single-ended and differential
measurements of the JESD ADC clock,
SYSREF and SYNCb inputs near the ADC
receivers.
CLKIN may require use of AC-coupling
capacitors unless clock driver meets input
common-mode requirements.
COADC0CLKIN0VSS
ADC_CLKIN_VSS
SYSREF requires exteranal 100-ohm
termination, but is compatible with
DC-coupled LVDS driver.
PIADC0CLKIN0VSS01
SYNCb intended to be DC coupled to
LVDS source driver. It includes on-die
100-ohm differential termination.
PIADC0SYNCb0VSS01
COADC0SYSREF0VSS
ADC_SYSREF_VSS
PIADC0SYSREF0VSS01
ADC_DEVCLK is a crtical clock net. Jitter
on this cock net will directly impact noise
floor of the ADC. ADC_DEVCLK should be
specially routed, and GND isolated in a
similar manner to the JESD SERDES
channels.
COADC0SYNCb0VSS
ADC_SYNCb_VSS
B
COU2B
U2B
ADC input signal signal conditioning
(bal-un, op-amps...etc) is not shown here.
The input circuit required is application
and system specific. Please see
ADC14X250 datasheet, application notes
and EVM design guide for specific
recommendations.
B
NLADC0VIN0P
ADC_VIN_P
NLADC0VIN0N
ADC_VIN_N
ADC_VIN_P
ADC_VIN_N
COADC0VCMO1
ADC_VCMO1
COADC0VCMO10VSS
ADC_VCMO1_VSS
3
VIN+
4
PIU204
VIN-
COC20
C20
0.1µF
9
PIC2002 PIC2001
CLKIN+ PIU209
COC21
C21
10
PIC2102 PIC21010.1µF
CLKIN- PIU2010
PIU203
PIADC0VCMO101
NLADC0VCMO PIU206
ADC_VCMO
6
VCM
ADC
Input
13 COC22
C22
PIC2202 PIC22010.1µF
SYSREF+ PIU2013
COC230.1µF
C23
14
PIC2302 PIC2301
SYSREF- PIU2014
PIADC0VCMO10VSS01
ADC common-mode input
voltage can be optionally
supplied from on-die regulator
or externally supplied VCM
pin.
JESD
PIADC0CLKIN001
PIADC0CLKIN001
COR20
R20 PIR2001
100
PIR2002
15
SYNCb+ PIU2015
16
SYNCb- PIU2016
SPI
PIADC0SYSREF001
PIADC0SYNCb001
PIADC0SYNCb001
NLADC0DEVCLKP
ADC_DEVCLKP
NLADC0DEVCLKN
ADC_DEVCLKN
COADC0SYSREF0
ADC_SYSREF+
ADC_SYSREF-
NLADC0SYSREFP
ADC_SYSREFP
NLADC0SYSREFN
ADC_SYSREFN
COADC0SYNCb0
ADC_SYNCb+
ADC_SYNCb-
NLK2L0DFESYNCOUT0P0
K2L_DFESYNCOUT_P0
NLK2L0DFESYNCOUT0N0
K2L_DFESYNCOUT_N0
NLK2L0JESD0RXP0
K2L_JESD_RXP0
NLK2L0JESD0RXN0
K2L_JESD_RXN0
19
SO+ PIU2019
20
SO- PIU2020
Implementation here simply
attaches probe point for
observation.
PIADC0SYSREF001
COADC0CLKIN0
ADC_CLKIN+
ADC_CLKIN-
24
SCLK PIU2024
23
CSB PIU2023
25
SDI PIU2025
K2L_SPI0SOMI_RS
26 NLK2L0SPI0SOMI0RS
SDO PIU2026
PIADC0SCLK01
PIADC0CSB01
COR83
R83
10.0
PIR8301
PIR8302
PIADC0SDI01
PIADC0SDO01
COADC0SCLK
ADC_SCLK
COADC0CSB
ADC_CSB
COADC0SDI
ADC_SDI
COADC0SDO
ADC_SDO
ADC_DEVCLKP
ADC_DEVCLKN
ADC DEVCLK driven by
LMK04828
ADC_SYSREFP
ADC_SYSREFN
ADC SYSREF driven by
LMK04828
K2L_DFESYNCOUT_P0
K2L_DFESYNCOUT_N0
ADC SYNCb driven by K2L
DFESYNCOUT0 LVDS driver
K2L_JESD_RXP0
K2L_JESD_RXN0
ADC JESD SERDES drives the K2L JESD0
SERDES RX pins
NLK2L0SPI0CLK
K2L_ADC_SPI0CLK
K2L_SPI0CLK
NLK2L0SPI0SCS0
K2L_ADC_SPI0SCS0
K2L_SPI0SCS0
NLK2L0SPI0SIMO
K2L_ADC_SPI0SIMO
K2L_SPI0SIMO
NLK2L0SPI0SOMI
K2L_ADC_SPI0SOMI
K2L_SPI0SOMI
ADC SPI port mastered by
K2L SPI_0
COADC0SPI0VSS
ADC_SPI_VSS
PIADC0SPI0VSS01
ADC14X250
C
C
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 26 of 35
File: adc14x250_02.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
2
3
4
5
6
LMK04828 Decoupling Capacitors
VSYS_DVDD3V3
LMK04828 decoupling shall be
placed as close to the IC package
as possible. See LMK04828
datasheet and EVM for example
decoupling layout.
A
PIC51201
PIC51202
PIC51301
PIC51401
PIC51501
PIC51601
PIC51701
PIC51801
A
COC512
COC513COC514
COC515
COC516COC517
COC518
C512
C513
C514
C515
C516
C517
C518
1µF
PIC51302
0.1µF
PIC51402
0.1µF
PIC51502
0.1µF
PIC51602
0.1µF
PIC51702
0.1µF
PIC51802
0.01µF
GND
VSYS_DVDD3V3
LMK_VCC1
VSYS_DVDD3V3
LMK_VCC2
COL20
L20
PIL2001
PIC51901
PIC51902
330 ohm
COC519
C519
0.1µF
GND
VSYS_DVDD3V3
B
PIL2101
PIC520 1
PIC520 2
COC520
C520
0.1µF
PIC52101
PIC52102
PIC52701
PIC52702
330 ohm
GND
GND
LMK_VCC5
VSYS_DVDD3V3
330 ohm
GND
VSYS_DVDD3V3
PIL2501
PIC52801
PIC52802
COC528
C528
0.1µF
PIC52901
PIC52902
330 ohm
GND
GND
LMK_VCC9
VSYS_DVDD3V3
PIC53502
COC535
C535
0.1µF
GND
COC522
C522
0.1µF
PIC52301
PIC52302
PIL2901
PIC53601
PIC53602
330 ohm
GND
GND
LMK_VCC6
VSYS_DVDD3V3
0.1µF
GND
PIC53702
COC537
C537
0.1µF
GND
LMK_VCC4
COL23
L23
PIL2301
PIC52401
PIC52402
COC524
C524
0.1µF
PIC52 01
PIC52 02
PIC530 1
PIC530 2
COC530
C530
0.1µF
PIC53101
PIC53102
330 ohm
GND
GND
LMK_VCC7
VSYS_DVDD3V3
330 ohm
GND
GND
LMK_VCC10
VSYS_DVDD3V3
PIC53801
PIC53802
LMK_VCC8
PIC53201
PIC53202
COC532
C532
0.1µF
PIC53 01
PIC53 02
GND
PIC53902
COC539
C539
0.1µF
GND
B
PIL2702
330 ohm
COC533
C533
0.1µF
GND
GND
LMK_VCC11
VSYS_DVDD3V3
PIC53401
PIC53402
COC534
C534
0.1µF
GND
LMK_VCC12
COL31
L31
PIL30 2
330 ohm
PIC53901
COC538
C538
0.1µF
COC526
C526
0.1µF
COL27
L27
PIL2701
COL30
L30
PIL3001
PIC52601
PIC52602
GND
PIL2602
COC531
C531
0.1µF
PIL2302
COC525
C525
0.1µF
COL26
L26
PIL2601
PIL2902
330 ohm
PIC53701
COC536
C536
VSYS_DVDD3V3
PIL2202
COC523
C523
0.1µF
COL29
L29
PIL2802
330 ohm
PIC53501
PIC52 01
PIC52 02
PIL2502
COC529
C529
0.1µF
COL28
L28
PIL2801
PIL2201
COL25
L25
PIL2402
COC527
C527
0.1µF
LMK_VCC3
COL22
L22
PIL2102
COC521
C521
0.1µF
COL24
L24
PIL2401
VSYS_DVDD3V3
COL21
L21
PIL2002
PIL3101
PIC540 1
PIC540 2
330 ohm
PIC5410
COC540
C540
0.1µF
GND
PIC54102
PIL3102
COC541
C541
0.1µF
GND
PIC54201
PIC5420
COC542
C542
0.1µF
GND
C
C
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-04-14
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 29 of 35
File: lmk04828_01.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
1
2
3
4
5
6
For schematic and layout recommendations
and requirements see the LMK04828 product
page linked below.
TI LMK04828 Product Page
A
LMK_VCC12
ADC_DEVCLKP
ADC_DEVCLKN
PIR14802
COR148
R148
2.32k
PIR14801
ADC_SYSREFP
LMK04828 SDCLKOUT0 used as
the SYSREF for the ADC
ADC_SYSREFN
LMK_RESET
LMK_SYNC
NLADC0SYSREFP
ADC_SYSREFP
PIU1103
NLADC0SYSREFN
ADC_SYSREFN
49 LMK-49
50 LMK-50
51 LMK-51
52 LMK-52
54 LMK-54
55 LMK-55
56 LMK-56
57 LMK-57
58 LMK-58
59 LMK-59
60 LMK-60
61 LMK-61
62 LMK-62
2
DCLKout0*
3
SDCLKout1
5
PIU1105
RESET
NLLMK0SYNC
LMK_SYNC
6
PIU1106
SYNC
PIC54701 PIC54702
PIR14701
LMK_VCC10
46
CPout2 PIU11046
NLLMK0CPOUT2
LMK_CPOUT2
45
Vcc9_CP2 PIU11045
LMK_VCC9
PIC54 01
53
64
NLLMK044
LMK-44
44
OSCin* PIU11044
PIC54 02
PIC54301
COC543
C543
COC544PIC54302 3900pF
C544
47pF
NLLMK043
43 LMK-43
OSCin PIU11043
42
Vcc8_OSCin PIU11042
NLLMK08
LMK-8
8
PIU1108 NC
41
OSCout*/CLKin2* PIU11041
NLLMK0LDOBYP2
LMK_LDOBYP2
COR147
R147
PIStatus102
PIR14702
270
47
PIU11047
NLLMK07
LMK-7
7
PIU1107
NC
LMK_VCC1
COC545
C545
0.1µF NLLMK0LDOBYP1
LMK_LDOBYP1
PIC54501 PIC54502
PILD101 PIStatus101
PIR14902
COR149
R149
619
LMK_VCC8
Please see LMK04828 datasheet, application notes and EVM design
guide for specific recommendations.
PIR14901
NLLMK041
LMK-41
B
10
39
Vcc7_OSCout PIU11039
19.2 MHz TCXO
LMK_VCC7
11
PIU11011
LDObyp1
38
CLKin0* PIU11038
NLLMK0CLKIN0N0CS
LMK_CLKIN0N_CS
COC5460.1µF
C546
PIC54601 PIC54602
12
PIU11012
LDObyp2
37
CLKin0 PIU11037
NLLMK0CLKIN0P0CS
LMK_CLKIN0P_CS
COC548
C548
0.1µF
PIC54801 PIC54802
13
PIU11013
SDCLKout3
14
Optional external charge-pump filter element. Shall be placed as close
as possible to LMK04828.
NLLMK040
40 LMK-40
OSCout/CLKin2 PIU11040
PIU11010 Vcc1_VCO
PIU11014
LMK04828 LD1 and LD2 monitored by
System Controller (microcontroller) not
shown here.
LMK_LD2
COStatus1
Status1
Green
COLD1
LD1
Vcc10_PLL2
NLLMK099
LMK-9
PIU1109 NC
COC547
C547 10µF
NLLMK0LD2
LMK_LD2
48
Status_LD2 PIU11048
4
PIU1104
SDCLKout1*
NLLMK0RESET
LMK_RESET
COU11
U11
LMK04828BISQ/NOPB
SDCLKout9
SDCLKout9*
DCLKout8
DCLKout8*
Vcc11_CG3
DCLKout10
DCLKout10*
SDCLKout11
SDCLKout11*
CLKin_SEL0
CLKin_SEL1
SDCLKout13
DCLKout12
DCLKout12*
65
PAD
PIU1102
PIR150 1
Vcc12_CG0
1
PIU1101
DCLKout0
NLADC0DEVCLKN
ADC_DEVCLKN
COR150
R150
1.3k
SDCLKout13*
NLADC0DEVCLKP
ADC_DEVCLKP
PIR150 2
B
PIU1065 PIU1 064 PIU1 063 PIU1 062 PIU1 061 PIU106 PIU1059 PIU1 058 PIU1 057 PIU1 056 PIU1 05 PIU1054 PIU1053 PIU1 052 PIU1 051 PIU1 05 PIU1 049
All unused pins shall be routed with
short stubs to aid in solderability and
mechanical robustness. Indicated by
the LMK-xx unused pin nets names.
LMK04828 DCLKOUT0 used as
the device clock for the ADC
63 LMK-63
NLMK063 NLMK062 NL MK061 NL MK06 NLMK059 NLMK058 NLMK057 NL MK056 NL MK05 NL MK054 NLMK052 NL MK051 NL MK05 NL MK049
LMK04828 RESET and SYNC
mastered by System Controller
(microcontroller) not shown here.
VSYS_DVDD3V3
A
LMK_VCC11
36
Vcc6_PLL1 PIU11036
NLLMK0CLKIN0P
LMK_CLKIN0P
COR151
R151
10.0
PIR15101
PIR15102
COU12
U12
NLLMK0CLKIN0P0RS
LMK_CLKIN0P_RS
3
PIU1203
OUT
VCC
Special care should be taken to GND isolate CLKIN0 signal.
LMK_VCC6
2
PIU1202
GND
NLLMK035
LMK-35
15
NLLMK034
34 LMK-34
CLKin1/Fin/FBCLKin PIU11034
16
33
Vcc5_DIG PIU11033
PIC54901
PIC54902
COC549
C549
1µF
LMK_VCC5
CPout1
Status_LD1
SDCLKout7*
SDCLKout7
DCLKout6*
DCLKout6
Vcc4_CG2
DCLKout4*
DCLKout4
SDCLKout5*
SDCLKout5
SDIO
SCK
CS*
Vcc2_CG1
PIU11016 DCLKout2*
Vcc3_SYSREF
PIU11015 DCLKout2
1
GND PIU1201
IT2100F
35
CLKin1*/Fin*/FBCLKin* PIU11035
SDCLKout3*
VSYS_DVDD1V8
4
PIU1204
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIU1 017 PIU1 018 PIU1 019 PIU1 02 PIU102 PIU102 PIU1 023 PIU1 024 PIU1 025 PIU1 026 PIU1027 PIU1028 PIU1 029 PIU1 03 PIU1 031 PIU1 032
NLLMK0CPOUT1
LMK_CPOUT1
LMK_VCC2
C
PIC5 10
LMK_SPI_CSB
LMK_SPI_CLK
LMK_SPI_DATA
NLLMK0SPI0CS
LMK_SPI_CS
NLLMK0SPI0CLK
LMK_SPI_CLK
NLLMK0SPI0DATA
COR152
LMK_SPI_DATA
R152
10.0
PIR15201
PIR15202
PILD201
NLLMK0SPI0DATA0RS
LMK_SPI_DATA_RS
COLD2
LD2
LMK04828 SPI port mastered by
System Controller (microcontroller)
not shown here.
LMK04828 DCLKOUT4 used as
the SYSCLK for the K2L
LMK04828 DCLKOUT6 used as
the JESD0 SERDES clock for the
K2L
K2L_DFESYSREFP
K2L_DFESYSREFN
K2L_SYSCLKP
K2L_SYSCLKN
K2L_JESD_SERDES0_REFCLKP
K2L_JESD_SERDES0_REFCLKN
PIC5 0 1
COC550
C550
COC551
C551
PIC5 0 2 3900pF
47pF
PIR15302
COR153
R153
619
C
Optional external charge-pump filter element. Shall be placed as close
as possible to LMK04828.
Please see LMK04828 datasheet, application notes and EVM design
guide for specific recommendations.
PIR15301
LMK_VCC4
LMK_VCC3
LMK04828 SDCLKOUT5 used as
the SYSREF for the K2L
PIC5 102
K2L_DFESYSREFP
NLK2L0DFESYSREFP
LMK_LD1
NLLMK0LD1
PIStaus201
NLK2L0DFESYSREFN
K2L_DFESYSREFN
NLK2L0SYSCLKP
K2L_SYSCLKP
NLK2L0SYSCLKN
K2L_SYSCLKN
PIStaus20
NLK2L0JESD0SERDES00REFCLKP
K2L_JESD_SERDES0_REFCLKP
NLK2L0JESD0SERDES00REFCLKN
K2L_JESD_SERDES0_REFCLKN
LMK_LD1
LMK04828 LD1 and LD2 monitored by
COStatus2System Controller (microcontroller) not
Status2
Green shown here.
PIR15402
R154
COR154
270
PIR15401
D
D
Orderable: ChangeMe!
TID #:
TIDEP0060
Number:
Rev: E1
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its Drawn By:
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. Engineer: a0271760
1
2
3
4
5
Designed for: Public Release
Mod. Date: 2015-12-15
Project Title: Optimized Radar System Design Using 66AK2L06 DSP+ARM® SoC and ADC14X250
Sheet Title:
Assembly Variant: 001
Sheet: 30 of 35
File: lmk04828_02.SchDoc
Size: B
http://www.ti.com
Contact: http://www.ti.com/support
© Texas Instruments 2015
6
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