DAC Limited | 711 Series | Datasheet | DAC Limited 711 Series Datasheet

IN
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VS1063a Datasheet
VS1063a DATASHEET
MP3/OGG/AAC/WMA/FLAC/
G.711/G.722 AUDIO CODEC CIRCUIT
Key Features
Description
VS1063a is an easy-to-use, versatile encoder,
decoder and codec for a multitude of audio
formats.
VS1063a contains a high-performance, proprietary low-power DSP core VS_DSP4 , ROM
memories, 16 KiB instruction RAM and upto
80 KiB data RAM for user applications running simultaneously with any built-in decoder,
serial control and input data interfaces, upto
12 general purpose I/O pins, a UART, as well
as a high-quality variable-sample-rate stereo
DAC and a stereo ADC, followed by an earphone amplifier and a common voltage buffer.
VS1063a can act both as an “MP3 decoder
IC” or “MP3 encoder IC” slave in a system
with a microcontroller, or as a stand-alone circuit that boots from external SPI memory.
PR
EL
IM
• Encoders:
MP3; Ogg Vorbis; PCM; IMA ADPCM;
G.711 (µ-law, A-law); G.722 ADPCM
• Decoders:
MP3 (MPEG 1 & 2 audio layer III (CBR
+VBR +ABR));
MP2 (layer II) (optional);
MPEG4 / 2 AAC-LC(+PNS),
HE-AAC v2 (Level 3) (SBR + PS);
Ogg Vorbis; FLAC;
WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps);
WAV (PCM, IMA ADPCM, G.711 µ-law/Alaw, G.722 ADPCM)
• Full Duplex Codecs:
PCM; G.711 (µ-law, A-law); G.722 ADPCM
• Streaming support
• Upto 96 KiB RAM for user code and data
• Unique ID for user code protection
• Quiet power-on and power-off
• I2S interface for external DAC
• Serial control and data interfaces
• Can be used either as a slave co-processor
or as a standalone processor
• UART for debugging purposes
• New functions may be added with software and upto 12 GPIO pins
Version: 0.42, 2011-11-24
Applications
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MP3-recording audio player
Streaming server and client
Wireless audio transfer
Standalone player and recorder
Internet phones
1
Additional Features
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EarSpeaker Spatial Processing
Bass & treble controls
Alternatively a 5-channel equalizer
AD Mixer allows monitoring A/D converter input while listening to stream
PCM Mixer allows inserting a sidestream
while listening to main stream
Adjustable Speed Shifter
Operates with a single 12. . . 13 MHz or
24. . . 26 MHz clock
Internal PLL clock multiplier
Low-power operation
High-quality on-chip stereo DAC with no
phase error between channels
Zero-cross detection for smooth volume
change
Stereo earphone driver capable of driving a 30 Ω load
Separate voltages for analog, digital, I/O
Lead-free RoHS-compliant package
Operating Modes
VS1063a operates in one of two host modes:
as a slave co-processor or as a standalone
processor.
When used as a slave co-processor VS1063a
can operate in three different operation modes:
decoder, encoder or codec mode. In decoder
mode VS1063a receives its input bitstream
through a serial input bus. The input stream
is decoded and passed through an 18-bit digital volume control to an oversampling sigmadelta DAC. Decoding is controlled via a serial
control bus. In addition to the basic decoding, it is possible to add application specific
features, like DSP effects, to the user RAM
memory, or even to load user applications.
In encoder mode VS1063a can reads audio
from its analog inputs, optionally compresses
the data, which can then be read by the host
processor. In codec mode VS1063a offers a
full-duplex audio interface.
When used as a standalone processor the
VS1063a can boot either from SPI EEPROM
or FLASH memory. Alternatively code and
data can be provided by a host controller.
IM
•
•
IN
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VS1063a Datasheet
Further Description
EL
VS1063a is a pin-compatible alternative for
VLSI Solution’s VS1053. It has all the functionality of VS1053 (except MP1 and MIDI
decoding) and many new features, particularly MP3 and Ogg Vorbis recording.
Also full-duplex codec functions for phone applications have been added to VS1063a.
PR
A factory-programmable unique chip ID provides a basis for digital rights management or
unit identification features.
Version: 0.42, 2011-11-24
User Code
Users can write their own user interface or
signal processing code for the VS1063a using VSIDE (VLSI Solution’s Integrated Development Environment).
As a default, there are 16 KiB of free code
RAM and about 4 KiB of free data RAM for
user plugin applications. Depending on the
application, the data RAM can be expanded
to the full 80 KiB that is available in VS1063a.
2
VS1063a Datasheet
IN
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CONTENTS
Contents
VS1063
1
Table of Contents
3
List of Figures
6
1 Disclaimer
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2 Licenses
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3 Definitions
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5 Packages and Pin Descriptions
5.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6 Connection Diagram, LQFP-48
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IM
4 Characteristics & Specifications
4.1 Absolute Maximum Ratings . . . . . . . . .
4.2 Recommended Operating Conditions . . . .
4.3 Analog Characteristics . . . . . . . . . . . .
4.4 Power Consumption . . . . . . . . . . . . .
4.5 Digital Characteristics . . . . . . . . . . . . .
4.6 Switching Characteristics - Boot Initialization
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8 Supported Audio Formats
8.1 Supported Audio Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PR
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7 SPI Buses
7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . .
7.2.1 VS10xx Native Modes (New Mode) . . . . . . . .
7.2.2 VS1001 Compatibility Mode (deprecated) . . . .
7.3 Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . .
7.4 Serial Protocol for Serial Data Interface (SDI) . . . . . . . .
7.4.1 General . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 SDI in VS10xx Native Modes (New Mode) . . . .
7.4.3 SDI in VS1001 Compatibility Mode (deprecated) .
7.4.4 Passive SDI Mode . . . . . . . . . . . . . . . . .
7.5 Serial Protocol for Serial Command Interface (SCI) . . . . .
7.5.1 General . . . . . . . . . . . . . . . . . . . . . . .
7.5.2 SCI Read . . . . . . . . . . . . . . . . . . . . . .
7.5.3 SCI Write . . . . . . . . . . . . . . . . . . . . . .
7.5.4 SCI Multiple Write . . . . . . . . . . . . . . . . . .
7.6 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . .
7.7 SPI Examples with SM_SDINEW and SM_SDISHARED set
7.7.1 Two SCI Writes . . . . . . . . . . . . . . . . . . .
7.7.2 Two SDI Bytes . . . . . . . . . . . . . . . . . . . .
7.7.3 SCI Operation in Middle of Two SDI Bytes . . . .
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Version: 0.42, 2011-11-24
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3
VS1063a Datasheet
IN
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8.1.1
8.1.2
8.1.3
8.1.4
8.2
CONTENTS
Supported MP3 (MPEG layer III) Decoder Formats . . . .
Supported MP2 (MPEG layer II) Decoder Formats . . . . .
Supported Ogg Vorbis Decoder Formats . . . . . . . . . .
Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3)
Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.5 Supported WMA Decoder Formats . . . . . . . . . . . . .
8.1.6 Supported FLAC Decoder Formats . . . . . . . . . . . . .
8.1.7 Supported RIFF WAV Decoder Formats . . . . . . . . . .
Supported Audio Encoding Formats . . . . . . . . . . . . . . . . . . .
8.2.1 Supported MP3 (MPEG layer III) Encoding Formats . . . .
8.2.2 Supported Ogg Vorbis Encoding Formats . . . . . . . . .
8.2.3 Supported RIFF WAV Encoding Formats . . . . . . . . . .
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10 Operation
10.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . .
10.2 Hardware Reset . . . . . . . . . . . . . . . . . . . .
10.3 Software Reset . . . . . . . . . . . . . . . . . . . .
10.4 Low Power Mode . . . . . . . . . . . . . . . . . . .
10.5 Play and Decode . . . . . . . . . . . . . . . . . . .
10.5.1 Playing a Whole File . . . . . . . . . . .
10.5.2 Cancelling Playback . . . . . . . . . . .
10.5.3 Fast Play . . . . . . . . . . . . . . . . . .
10.5.4 Fast Forward and Rewind without Audio
10.5.5 Maintaining Correct Decode Time . . . .
10.6 Feeding PCM Data . . . . . . . . . . . . . . . . . .
10.7 Audio Encoding . . . . . . . . . . . . . . . . . . . .
10.7.1 Encoding Control Registers . . . . . . .
10.7.2 The Encoding Procedure . . . . . . . . .
10.7.3 Reading Encoded Data Through SCI . .
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PR
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9 Functional Description
9.1 Main Features . . . . . . . . . . . . . . . . .
9.2 Decoder Data Flow of VS1063a . . . . . . .
9.3 Encoder Data Flow of VS1063a . . . . . . .
9.4 Codec Data Flow of VS1063a . . . . . . . .
9.5 EarSpeaker Spatial Processing . . . . . . .
9.6 Serial Data Interface (SDI) . . . . . . . . . .
9.7 Serial Control Interface (SCI) . . . . . . . .
9.8 SCI Registers . . . . . . . . . . . . . . . . .
9.8.1 SCI_MODE (RW) . . . . . . . . .
9.8.2 SCI_STATUS (RW) . . . . . . . .
9.8.3 SCI_BASS (RW) . . . . . . . . .
9.8.4 SCI_CLOCKF (RW) . . . . . . . .
9.8.5 SCI_DECODE_TIME (RW) . . .
9.8.6 SCI_AUDATA (RW) . . . . . . . .
9.8.7 SCI_WRAM (RW) . . . . . . . . .
9.8.8 SCI_WRAMADDR (W) . . . . . .
9.8.9 SCI_HDAT0 and SCI_HDAT1 (R)
9.8.10 SCI_AIADDR (RW) . . . . . . . .
9.8.11 SCI_VOL (RW) . . . . . . . . . .
9.8.12 SCI_AICTRL[x] (RW) . . . . . . .
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Decoder
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Version: 0.42, 2011-11-24
4
VS1063a Datasheet
IN
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CONTENTS
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11 VS1063a Version Changes
11.1 Firmware Changes Between VS1053b and VS1063a, 2011-04-13 . . . . . . . .
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12 Latest Document Version Changes
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13 Contact Information
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10.7.4 File Headers . . . . . . . . . . . . . .
10.7.5 Playing Encoded Data . . . . . . . .
10.7.6 Encoder Samplerate Considerations
10.7.7 Encode Monitoring Volume . . . . . .
10.7.8 Encoder-Specific Considerations . .
10.7.9 Encoder/Decoder Delays . . . . . . .
10.8 Codec Mode . . . . . . . . . . . . . . . . . . . .
10.9 SPI Boot . . . . . . . . . . . . . . . . . . . . . .
10.10 I2C Boot . . . . . . . . . . . . . . . . . . . . . .
10.11 Extra Parameters (Parametric Structure) . . . .
10.11.1 chipID, version, config1 . . . . . . . .
10.11.2 Player Configurations . . . . . . . . .
10.11.3 VU Meter . . . . . . . . . . . . . . . .
10.11.4 AD Mixer . . . . . . . . . . . . . . . .
10.11.5 PCM Mixer . . . . . . . . . . . . . . .
10.11.6 EQ5 5-band Equalizer . . . . . . . .
10.11.7 Speed Shifter . . . . . . . . . . . . .
10.11.8 EarSpeaker . . . . . . . . . . . . . .
10.11.9 Other Parameters . . . . . . . . . . .
10.12 SDI Tests . . . . . . . . . . . . . . . . . . . . .
10.12.1 Sine Test . . . . . . . . . . . . . . . .
10.12.2 Pin Test . . . . . . . . . . . . . . . .
10.12.3 SCI Test . . . . . . . . . . . . . . . .
10.12.4 Memory Test . . . . . . . . . . . . . .
10.12.5 New Sine and Sweep Tests . . . . .
Version: 0.42, 2011-11-24
5
List of Figures
Pin configuration, LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS1063a in LQFP-48 packaging . . . . . . . . . . . . . . . . . . . . . . . .
Typical connection diagram using LQFP-48 . . . . . . . . . . . . . . . . . .
BSYNC signal - one byte transfer . . . . . . . . . . . . . . . . . . . . . . . .
BSYNC signal - two byte transfer . . . . . . . . . . . . . . . . . . . . . . . .
SCI word read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI multiple word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two SCI operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two SDI bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two SDI bytes separated by an SCI operation . . . . . . . . . . . . . . . . .
Decoder data flow of VS1063a . . . . . . . . . . . . . . . . . . . . . . . . .
Encoder data flow of VS1063a . . . . . . . . . . . . . . . . . . . . . . . . .
Codec data flow of VS1063a . . . . . . . . . . . . . . . . . . . . . . . . . .
EarSpeaker externalized sound sources vs. normal inside-the-head sound
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12
12
15
20
20
21
22
22
23
24
24
25
34
35
36
37
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LIST OF FIGURES
IN
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VS1063a Datasheet
Version: 0.42, 2011-11-24
6
1
2
LICENSES
IN
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VS1063a Datasheet
Disclaimer
This is a preliminary datasheet. All properties and figures are subject to change.
This datasheet assumes that the VS1063a Patches package, available at
http://www.vlsi.fi/en/support/software/vs10xxplugins.html , has been loaded and activated.
Additional information is provided in two documents called VS1063a Hardware Guide, and
VS1063a Programmer’s Guide.
2
Licenses
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
IM
Supply of this product does not convey a license nor imply any right to distribute MPEG Layer-3
compliant content created with this product in revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet,
intranets and/or other networks), other content distribution systems (pay-audio of audio-ondemand applications and the like) or on physical media (compact discs, digital versatile discs,
semiconductior chips, hard drives, memory cards and the like). An independent license for
such use is required. For details, please visit http://mp3licensing.com.
Note: If you enable Layer II decoding, you are liable for any patent issues that may arise
from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III decoding does not cover
all patents pertaining to layer II.
EL
VS1063a contains WMA decoding technology from Microsoft.
This product is protected by certain intellectual property rights of Microsoft and cannot
be used or further distributed without a license from Microsoft.
VS1063a contains AAC decoding technology (ISO/IEC 13818-7 and ISO/IEC 14496-3) which
cannot be used without a proper license from Via Licensing Corporation or individual patent
holders.
PR
VS1063a contains spectral band replication (SBR) and parametric stereo (PS) technologies
developed by Coding Technologies. Both are currently part of the MPEG4 AAC licensing, see
http://www.vialicensing.com/licensing/aac-overview.aspx for more information.
To the best of VLSI Solution’s knowledge, if the end product does not play a specific format
that otherwise would require a customer license: MPEG 1.0/2.0 layer II, WMA, or AAC, the
respective license should not be required. Decoding of MPEG layer II is disabled by default,
and WMA and AAC formats can be excluded by using the parametric_x.config1 variable, or with
a microcontroller based on the contents of register SCI_HDAT1. Also PS and SBR decoding
can be separately disabled.
Version: 0.42, 2011-11-24
7
3
Definitions
3
DEFINITIONS
IN
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VS1063a Datasheet
ABR Average BitRate. Bitrate of stream may vary locally, but will stay close to a given number
when averaged over a longer time.
B Byte, 8 bits.
b Bit.
CBR Constant BitRate. Bitrate of stream will be the same for each compression block.
Ki “Kibi” = 210 = 1024 (IEC 60027-2).
Mi “Mebi” = 220 = 1048576 (IEC 60027-2).
VBR Variable BitRate. Bitrate will vary depending on the complexity of the source material.
VS_DSP VLSI Solution’s DSP core.
VSIDE VLSI Solution’s Integrated Development Environment.
PR
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W Word. In VS_DSP, instruction words are 32-bits and data words are 16-bits wide.
Version: 0.42, 2011-11-24
8
VS1063a Datasheet
4
4.1
Characteristics & Specifications
Absolute Maximum Ratings
Parameter
Analog Positive Supply
Digital Positive Supply
I/O Positive Supply
Current at Any Non-Power Pin1
Voltage at Any Digital Input
Operating Temperature
Storage Temperature
1
2
Symbol
AVDD
CVDD
IOVDD
Min
-0.3
-0.3
-0.3
-0.3
-30
-65
Higher current can cause latch-up.
Must not exceed 3.6 V
Max
3.6
1.85
3.6
±50
IOVDD+0.32
+85
+150
Symbol
AGND DGND
AVDD
AVDD
CVDD
IOVDD
XTALI
CLKI
EL
Parameter
Ambient Operating Temperature
Analog and Digital Ground 1
Positive Analog, REF=1.23V
Positive Analog, REF=1.65V 2
Positive Digital
I/O Voltage
Input Clock Frequency 3
Internal Clock Frequency
Internal Clock Multiplier 4
Master Clock Duty Cycle
1
Unit
V
V
V
mA
V
◦C
◦C
Recommended Operating Conditions
IM
4.2
CHARACTERISTICS & SPECIFICATIONS
IN
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4
Min
-30
2.5
3.3
1.7
1.8
12
12
1.0×
40
Typ
0.0
2.8
3.3
1.8
2.8
12.288
36.864
3.5×
50
Max
+85
3.6
3.6
1.85
3.6
13
61.5
5.0×
60
Unit
◦C
V
V
V
V
V
MHz
MHz
%
Must be connected together as close the device as possible for latch-up immunity.
Reference voltage can be internally selected between 1.23V and 1.65V, see section 9.8.2.
3 The maximum samplerate that can be played with correct speed is XTALI/256 (or XTALI/512
if SM_CLK_RANGE is set). Thus, XTALI must be at least 12.288 MHz (24.576 MHz) to be able
to play 48 kHz at correct speed.
4 Reset value is 1.0×. Recommended SC_MULT=3.5×, SC_ADD=1.0× (SCI_CLOCKF=0x8800).
Do not exceed maximum specification for CLKI.
PR
2
Version: 0.42, 2011-11-24
9
VS1063a Datasheet
4.3
Analog Characteristics
CHARACTERISTICS & SPECIFICATIONS
IN
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4
Unless otherwise noted: AVDD=3.3V, CVDD=1.8V, IOVDD=2.8V, REF=1.65V, TA=-30. . . +85◦ C,
XTALI=12. . . 13MHz, Internal Clock Multiplier 3.5×. DAC tested with 1307.894 Hz full-scale
output sinewave, measurement bandwidth 20. . . 20000 Hz, analog output load: LEFT to GBUF
30 Ω, RIGHT to GBUF 30 Ω. Microphone test amplitude 48 mVpp, fs =1 kHz. Line input test
amplitude 1.26 V, fs =1 kHz.
Symbol
2
Typ
18
0.07
0.02
IDR
SNR
100
94
80
53
-0.5
-0.1
1.64
AOLR
Max
16
1.851
0.5
0.1
2.06
5
302
100
MICG
MTHD
MSNR
LTHD
LSNR
60
85
26
48
0.03
70
45
2500
0.005
90
80
1403
0.07
28003
0.014
Unit
bits
%
%
dB
dB
dB
dB
dB
dB
Vpp
◦
Ω
pF
dB
mVpp AC
%
dB
kΩ
mVpp AC
%
dB
kΩ
3.0 volts can be achieved with +-to-+ wiring for mono difference sound.
AOLR may be much lower, but below Typical distortion performance may be compromised.
Above typical amplitude the Harmonic Distortion increases.
PR
3
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1
Min
THD
IM
Parameter
DAC Resolution
Total Harmonic Distortion
Third Harmonic Distortion
Dynamic Range (DAC unmuted, A-weighted)
S/N Ratio (full scale signal)
Interchannel Isolation (Cross Talk), 600Ω + GBUF
Interchannel Isolation (Cross Talk), 30Ω + GBUF
Interchannel Gain Mismatch
Frequency Response
Full Scale Output Voltage (Peak-to-peak)
Deviation from Linear Phase
Analog Output Load Resistance
Analog Output Load Capacitance
Microphone input amplifier gain
Microphone input amplitude
Microphone Total Harmonic Distortion
Microphone S/N Ratio
Microphone input impedances, per pin
Line input amplitude
Line input Total Harmonic Distortion
Line input S/N Ratio
Line input impedance
Version: 0.42, 2011-11-24
10
VS1063a Datasheet
4.4
Power Consumption
CHARACTERISTICS & SPECIFICATIONS
IN
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4
Tested with an Ogg Vorbis 128 kbps sample and generated sine. Output at full volume. Internal
clock multiplier 3.0×. TA=+25◦ C.
Parameter
Power Supply Consumption AVDD, Reset
Power Supply Consumption CVDD = 1.8V, Reset
Power Supply Consumption AVDD, sine test, 30 Ω + GBUF
Power Supply Consumption CVDD = 1.8V, sine test
Power Supply Consumption AVDD, no load
Power Supply Consumption AVDD, output load 30 Ω
Power Supply Consumption AVDD, 30 Ω + GBUF
Power Supply Consumption CVDD = 1.8V
4.5
Digital Characteristics
30
8
Min
0.7×IOVDD
0.7×CVDD
-0.2
0.7×IOVDD
IM
Parameter
High-Level Input Voltage (xRESET, XTALI, XTALO)
High-Level Input Voltage (other input pins)
Low-Level Input Voltage
Min
High-Level Output Voltage at XTALO = -0.1 mA
Low-Level Output Voltage at XTALO = 0.1 mA
1
2
EL
High-Level Output Voltage at IO = -1.0 mA
Low-Level Output Voltage at IO = 1.0 mA
Input Leakage Current
SPI Input Clock Frequency 2
Rise time of all output pins, load = 50 pF
Must not exceed 3.6V
Value for SCI reads. SCI and SDI writes allow
4.6
Max
5.0
20.0
60
15
Max
IOVDD+0.31
IOVDD+0.31
0.3×CVDD
0.3×IOVDD
0.7×IOVDD
-1.0
0.3×IOVDD
1.0
CLKI
7
50
Unit
µA
µA
mA
mA
mA
mA
mA
mA
Unit
V
V
V
V
V
V
V
µA
MHz
ns
CLKI
4 .
Switching Characteristics - Boot Initialization
PR
Parameter
XRESET active time
XRESET inactive to software ready
Power on reset, rise time to CVDD
1
Typ
0.6
12
36.9
10
5
11
11
11
Symbol
Min
2
22000
10
Max
500001
Unit
XTALI
XTALI
V/s
DREQ rises when initialization is complete. Do not send any data or commands before that.
Version: 0.42, 2011-11-24
11
VS1063a Datasheet
5
PACKAGES AND PIN DESCRIPTIONS
IN
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5
Packages and Pin Descriptions
5.1
Packages
LPQFP-48 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of
Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical
and electronic equipment.
5.1.1
LQFP-48
48
IM
1
Figure 1: Pin configuration, LQFP-48
PR
EL
LQFP-48 package dimensions are at http://www.vlsi.fi/ .
Figure 2: VS1063a in LQFP-48 packaging
Version: 0.42, 2011-11-24
12
VS1063a Datasheet
Pin
Type
AI
AI
DI
DGND
CPWR
IOPWR
CPWR
DO
DIO
DIO
DIO
DIO
Function
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DI
IOPWR
DO
DGND
AO
AI
IOPWR
DGND
DGND
DGND
DI
CPWR
DIO
DI
DO
DI
DI
DO3
CPWR
DI
DIO
Data chip select / byte sync
I/O power supply
For testing only (Clock VCO output)
Core & I/O ground
Crystal output
Crystal input
I/O power supply
Core & I/O ground
Core & I/O ground
Core & I/O ground
Chip select input (active low)
Core power supply
General purpose IO 5 / I2S_MCLK
UART receive, connect to IOVDD if not used
UART transmit
Clock for serial bus
Serial input
Serial output
Core power supply
Reserved for test, connect to IOVDD
Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down
resistor2
General purpose IO 1
I/O Ground
General purpose IO 4 / I2S_LROUT
Positive differential mic input, self-biasing / Line-in 1
Negative differential mic input, self-biasing
Active low asynchronous reset, schmitt-trigger input
Core & I/O ground
Core power supply
I/O power supply
Core power supply
Data request, input bus
General purpose IO 2 / serial input data bus clock
General purpose IO 3 / serial data input
General purpose IO 6 / I2S_SCLK
General purpose IO 7 / I2S_SDATA
EL
MICP / LINE1
MICN
XRESET
DGND0
CVDD0
IOVDD0
CVDD1
DREQ
GPIO2 / DCLK1
GPIO3 / SDATA1
GPIO6 / I2S_SCLK3
GPIO7
/
I2S_SDATA3
XDCS / BSYNC1
IOVDD1
VCO
DGND1
XTALO
XTALI
IOVDD2
DGND2
DGND3
DGND4
XCS
CVDD2
GPIO5 / I2S_MCLK3
RX
TX
SCLK
SI
SO
CVDD3
XTEST
GPIO0
LQFP
Pin
1
2
3
4
5
6
7
8
9
10
11
12
IM
Pad Name
PACKAGES AND PIN DESCRIPTIONS
IN
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5
/
34
35
36
DIO
DGND
DIO
37
38
39
40
41
42
APWR
APWR
AO
APWR
APWR
AO
43
44
45
46
47
48
APWR
AIO
APWR
AO
APWR
AI
PR
GPIO1
GND
GPIO4
I2S_LROUT3
AGND0
AVDD0
RIGHT
AGND1
AGND2
GBUF
AVDD1
RCAP
AVDD2
LEFT
AGND3
LINE2
Version: 0.42, 2011-11-24
Analog ground, low-noise reference
Analog power supply
Right channel output
Analog ground
Analog ground
Common buffer for headphones, do NOT connect to
ground!
Analog power supply
Filtering capacitance for reference
Analog power supply
Left channel output
Analog ground
Line-in 2 (right channel)
13
VS1063a Datasheet
1
PACKAGES AND PIN DESCRIPTIONS
IN
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5
First pin function is active in New Mode, latter in Compatibility Mode.
2
Unless pull-down resistor is used, SPI Boot, followed by I2C Boot, is tried. See Chapters 10.9,
SPI Boot, and 10.10, I2C Boot, for details.
3
If I2S_CF_ENA is ’0’ the pins are used for GPIO. See VS1063a Hardware Guide’s Chapter
I2S DAC Interface for details.
Pin types:
Type
DI
DO
DIO
DO3
Type
AO
AIO
APWR
DGND
CPWR
IOPWR
Description
Analog output
Analog input/output
Analog power supply pin
Core or I/O ground pin
Core power supply pin
I/O power supply pin
PR
EL
IM
AI
Description
Digital input, CMOS Input Pad
Digital output, CMOS Input Pad
Digital input/output
Digital output, CMOS Tri-stated Output
Pad
Analog input
Version: 0.42, 2011-11-24
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VS1063a Datasheet
Connection Diagram, LQFP-48
EL
IM
6
CONNECTION DIAGRAM, LQFP-48
IN
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6
PR
Figure 3: Typical connection diagram using LQFP-48
Figure 3 shows a typical connection diagram for VS1063.
Figure Note 1: Connect either Microphone In or Line In, but not both at the same time.
Note: This connection assumes SM_SDINEW is active (see Chapter 9.8.1). If also SM_SDISHARE
is used, xDCS should be tied high (see Chapter 7.2.1).
Version: 0.42, 2011-11-24
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VS1063a Datasheet
CONNECTION DIAGRAM, LQFP-48
IN
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6
The common buffer GBUF can be used for common voltage (1.23 V) for earphones. This will
eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins
from VS1063a may be connected directly to the earphone connector.
GBUF must NOT be connected to ground under any circumstances. If GBUF is not used,
LEFT and RIGHT must be provided with coupling capacitors. To keep GBUF stable, you should
always have the resistor and capacitor even when GBUF is not used.
Unused GPIO pins should have a pull-down resistor. Unused line and microphone inputs should
not be connected.
If UART is not used, RX should be connected to IOVDD and TX be unconnected.
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Do not connect any external load to XTALO.
Version: 0.42, 2011-11-24
16
7
SPI Buses
7.1
General
7
SPI BUSES
IN
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VS1063a Datasheet
The SPI Bus - that was originally used in some Motorola devices - has been used for both
VS1063a’s Serial Data Interface SDI (Chapters 7.4 and 9.6) and Serial Control Interface SCI
(Chapters 7.5 and 9.7).
7.2
SPI Bus Pin Descriptions
7.2.1
VS10xx Native Modes (New Mode)
These modes are active on VS1063a when SM_SDINEW is set to 1 (default at startup). DCLK
and SDATA are not used for data transfer and they can be used as general-purpose I/O pins
(GPIO2 and GPIO3). BSYNC function changes to data interface chip select (XDCS).
SCI Pin
XCS
SCK
SI
7.2.2
SO
EL
-
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM_SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
IM
SDI Pin
XDCS
VS1001 Compatibility Mode (deprecated)
PR
This mode is active when SM_SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC
are active.
Version: 0.42, 2011-11-24
17
SDI Pin
-
SCI Pin
XCS
BSYNC
DCLK
SCK
SDATA
-
SI
SO
7.3
7
SPI BUSES
IN
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VS1063a Datasheet
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state.
SDI data is synchronized with a rising edge of BSYNC.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
Data Request Pin DREQ
The DREQ pin/signal is used to signal if VS1063a’s 2048-byte FIFO is capable of receiving
data. If DREQ is high, VS1063a can take at least 32 bytes of SDI data or one SCI command.
DREQ is turned low when the stream buffer is too full and for the duration of a SCI command.
IM
Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a
time without checking the status of DREQ, making controlling VS1063a easier for low-speed
microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ
should only be used to decide whether to send more bytes. A transmission that has already
started doesn’t need to be aborted.
EL
Note: In VS1063a DREQ also goes down while an SCI operation is in progress.
PR
There are cases when you still want to send SCI commands when DREQ is low. Because
DREQ is shared between SDI and SCI, you can not determine if a SCI command has been
executed if SDI is not ready to receive. In this case you need a long enough delay after every
SCI command to make certain none of them is missed. The SCI Registers table in Chapter 9.8
gives the worst-case handling time for each SCI register write.
Version: 0.42, 2011-11-24
18
7.4
7.4.1
7
SPI BUSES
IN
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VS1063a Datasheet
Serial Protocol for Serial Data Interface (SDI)
General
The serial data interface operates in slave mode so DCLK signal must be generated by an
external circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 9.8).
VS1063a assumes its data input to be byte-sychronized. SDI bytes may be transmitted either
MSb or LSb first, depending of register SCI_MODE bit SM_SDIORD (Chapter 9.8.1).
The firmware is able to accept the maximum bitrate the SDI supports.
7.4.2
SDI in VS10xx Native Modes (New Mode)
IM
In VS10xx native modes (SM_NEWMODE is 1), byte synchronization is achieved by XDCS.
The state of XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization even if there may be glitches in the boards using VS1063a, it is
recommended to turn XDCS every now and then, for instance once after every disk data block,
just to make sure the host and VS1063a are in sync.
If SM_SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.
PR
EL
For new designs, using VS10xx native modes are recommended.
Version: 0.42, 2011-11-24
19
7.4.3
7
SPI BUSES
IN
AR
Y
VS1063a Datasheet
SDI in VS1001 Compatibility Mode (deprecated)
BSYNC
SDATA
D7
D6
D5
DCLK
D4
D3
D2
D1
D0
Figure 4: BSYNC signal - one byte transfer
When VS1063a is running in VS1001 compatibility mode, a BSYNC signal must be generated
to ensure correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or
falling, depending on selected polarity), during which the BSYNC is high, marks the first bit of
a byte (LSB, if LSB-first order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when
the last bit is received, the receiver stays active and next 8 bits are also received.
BSYNC
SDATA
D7
D6
D5
DCLK
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
7.4.4
IM
Figure 5: BSYNC signal - two byte transfer
Passive SDI Mode
PR
EL
If SM_NEWMODE is 0 and SM_SDISHARE is 1, the operation is otherwise like the VS1001
compatibility mode, but bits are only received while the BSYNC signal is ’1’. Rising edge of
BSYNC is still used for synchronization.
Version: 0.42, 2011-11-24
20
7.5
7.5.1
7
SPI BUSES
IN
AR
Y
VS1063a Datasheet
Serial Protocol for Serial Command Interface (SCI)
General
The serial bus protocol for the Serial Command Interface SCI (Chapter 9.7) consists of an
instruction byte, address byte and one 16-bit data word. Each read or write operation can read
or write a single register. Data bits are read at the rising edge, so the user should update data
at the falling edge. Bytes are always send MSb first. XCS should be low for the full duration of
the operation, but you can have pauses between bits if needed.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read
and write. See table below.
Instruction
Opcode
0b0000 0011
0b0000 0010
Name
READ
WRITE
Operation
Read data
Write data
7.5.2
SCI Read
XCS
0
1
2
3
4
0
0
0
0
0
SCK
IM
Note: VS1063a sets DREQ low after each SCI operation. The duration depends on the operation. It is not allowed to finish a new SCI/SDI operation before DREQ is high again.
5
6
7
8
9
10 11 12 13 14 15 16 17
0
1
1
0
0
0
3
SI
SO
0
0
0
0
0
0
1
0
don’t care
0
address
EL
instruction (read)
2
0
0
0
0
0
0
30 31
0
15 14
0
0
0
don’t care
data out
1
0
X
execution
DREQ
Figure 6: SCI word read
PR
VS1063a registers are read from using the following sequence, as shown in Figure 6. First,
XCS line is pulled low to select the device. Then the READ opcode (0x3) is transmitted via
the SI line followed by an 8-bit word address. After the address has been read in, any further
data on SI is ignored by the chip. The 16-bit data corresponding to the received address will be
shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
DREQ is driven low for a short while when in a read operation by the chip. This is a very short
time and doesn’t require special user attention.
Version: 0.42, 2011-11-24
21
VS1063a Datasheet
SCI Write
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
0
0
0
0
0
0
1
0
0
0
0
SCK
3
SI
instruction (write)
SO
0
0
0
0
0
0
2
1
0
0
0
0
30 31
15 14
0
1
0
X
0
data out
address
0
SPI BUSES
IN
AR
Y
7.5.3
7
0
0
0
0
0
0
0
0 X
0
execution
DREQ
Figure 7: SCI word write
VS1063a registers are written from using the following sequence, as shown in Figure 7. First,
XCS line is pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the
SI line followed by an 8-bit word address.
IM
After the word has been shifted in and the last clock has been sent, XCS should be pulled high
to end the WRITE sequence.
After the last bit has been sent, DREQ is driven low for the duration of the register update,
marked “execution” in the figure. The time varies depending on the register and its contents
(see table in Chapter 9.8 for details). If the maximum time is longer than what it takes from the
microcontroller to feed the next SCI command or SDI byte, status of DREQ must be checked
before finishing the next SCI/SDI operation.
XCS
SCI Multiple Write
EL
7.5.4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SI
0
0
0
0
0
0
1
0
0
0
0
SO
0
0
0
0
0
0
0
SCK
3
instruction (write)
0
0
0
1
0
15 14
1
0
0
0
0
0
0
32 33
0
15 14
m−2m−1
1
0
X
X
0
address
PR
0
2
29 30 31
data out 1
0
data out 2 d.out n
0
0
0
execution
0
0
0 X
execution
DREQ
Figure 8: SCI multiple word write
VS1063a allows for the user to send multiple words to the same SCI register, which allows fast
SCI uploads, shown in Figure 8. The main difference to a single write is that instead of bringing
Version: 0.42, 2011-11-24
22
VS1063a Datasheet
SPI BUSES
IN
AR
Y
7
XCS up after sending the last bit of a data word, the next data word is sent immediately. After
the last data word, XCS is driven high as with a single word write.
After the last bit of a word has been sent, DREQ is driven low for the duration of the register
update, marked “execution” in the figure. The time varies depending on the register and its
contents (see table in Chapter 9.8 for details). If the maximum time is longer than what it takes
from the microcontroller to feed the next SCI command or SDI byte, status of DREQ must be
checked before finishing the next SCI/SDI operation.
7.6
SPI Timing Diagram
tWL
tXCSS
XCS
tWH
tXCSH
tXCS
0
1
14
SCK
SI
tH
tSU
tZ
30
16
IM
SO
15
tV
31
tDIS
Figure 9: SPI timing diagram
The SPI timing diagram is presented in Figure 9.
Min
5
0
2
0
2
2
1
2 (+ 25 ns )
1
2
PR
EL
Symbol
tXCSS
tSU
tH
tZ
tWL
tWH
tV
tXCSH
tXCS
tDIS
1
Max
10
Unit
ns
ns
CLKI cycles
ns
CLKI cycles
CLKI cycles
CLKI cycles
CLKI cycles
CLKI cycles
ns
25 ns is when pin loaded with 100 pF capacitance. The time is shorter with lower capacitance.
Note: Although the timing is derived from the internal clock CLKI, the system always starts up in
1.0× mode, thus CLKI=XTALI. After you have configured a higher clock through SCI_CLOCKF
and waited for DREQ to rise, you can use a higher SPI speed as well.
Note: Because tWL + tWH + tH is 6×CLKI + 25 ns, the maximum speed for SCI reads is CLKI/7.
Version: 0.42, 2011-11-24
23
VS1063a Datasheet
7.7.1
SPI BUSES
IN
AR
Y
7.7
7
SPI Examples with SM_SDINEW and SM_SDISHARED set
Two SCI Writes
SCI Write 1
SCI Write 2
XCS
0
1
2
3
30
SCK
1
SI
0
0
0
32
31
0
X
0
33
0
61
62
63
2
1
0
X
0
DREQ up before finishing next SCI write
DREQ
Figure 10: Two SCI operations
7.7.2
Two SDI Bytes
IM
Figure 10 shows two consecutive SCI operations. Note that xCS must be raised to inactive
state between the writes. Also DREQ must be respected as shown in the figure.
SDI Byte 1
XCS
0
1
2
6
3
7
EL
SCK
SDI Byte 2
7
6
5
4
3
1
0
8
9
7
6
SI
5
13
14
15
2
1
0
X
DREQ
Figure 11: Two SDI bytes
PR
SDI data is synchronized with a raising edge of xCS as shown in Figure 11. However, every
byte doesn’t need separate synchronization.
Version: 0.42, 2011-11-24
24
VS1063a Datasheet
SPI BUSES
IN
AR
Y
7.7.3
7
SCI Operation in Middle of Two SDI Bytes
SDI Byte
XCS
0
7
1
8
SCK
7
6
5
1
9
39
0
0
SI
SDI Byte
SCI Operation
40
41
7
6
5
46
47
1
0
X
0
DREQ high before end of next transfer
DREQ
Figure 12: Two SDI bytes separated by an SCI operation
PR
EL
IM
Figure 12 shows how an SCI operation is embedded in between SDI operations. xCS edges
are used to synchronize both SDI and SCI. Remember to respect DREQ as shown in the figure.
Version: 0.42, 2011-11-24
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VS1063a Datasheet
8
Supported Audio Formats
8.1
Supported Audio Decoders
Mark
+
-
8.1.1
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
Conventions
Description
Format is supported
Format exists but is not supported
Format doesn’t exist
Supported MP3 (MPEG layer III) Decoder Formats
The VS1063 MP3 decoder is full-accuracy compliant.
MPEG 1.01 :
Samplerate / Hz
48000
44100
32000
32
+
+
+
40
+
+
+
8
+
+
+
16
+
+
+
8
+
+
+
16
+
+
+
48
+
+
+
56
+
+
+
64
+
+
+
Samplerate / Hz
24000
22050
16000
MPEG 2.51 :
12000
11025
8000
1
160
+
+
+
192
+
+
+
224
+
+
+
256
+
+
+
320
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56 64 80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56 64 80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
EL
Samplerate / Hz
Bitrate / kbit/s
96 112 128
+
+
+
+
+
+
+
+
+
IM
MPEG 2.01 :
80
+
+
+
Also all variable bitrate (VBR) formats are supported.
8.1.2
Supported MP2 (MPEG layer II) Decoder Formats
PR
Note: Layer II decoding must be specifically enabled from register SCI_MODE.
MPEG 1.0:
Samplerate / Hz
48000
44100
32000
32
+
+
+
48
+
+
+
Version: 0.42, 2011-11-24
56
+
+
+
64
+
+
+
80
+
+
+
96
+
+
+
Bitrate / kbit/s
112 128 160
+
+
+
+
+
+
+
+
+
192
+
+
+
224
+
+
+
256
+
+
+
320
+
+
+
384
+
+
+
26
VS1063a Datasheet
MPEG 2.0:
Samplerate / Hz
24000
22050
16000
8.1.3
8
+
+
+
16
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
48
+
+
+
Bitrate / kbit/s
56 64 80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
Supported Ogg Vorbis Decoder Formats
Parameter
Channels
Window size
Samplerate
Bitrate
Min
1
64
1
0
Max
2
4096
48000
500
Unit
samples
Hz
kbit/sec
Of the two Ogg Vorbis floors, only floor 1 is supported. No known encoders since early preliminary releases have ever used floor 0. All one- and two-channel Ogg Vorbis files should be
playable with this decoder.
Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Decoder Formats
IM
8.1.4
VS1063a decodes MPEG2-AAC-LC-2.0.0.0 and MPEG4-AAC-LC-2.0.0.0 streams, i.e. the low
complexity profile with maximum of two channels can be decoded. If a stream contains more
than one element and/or element type, you can select which one to decode from the 16 singlechannel, 16 channel-pair, and 16 low-frequency elements. The default is to select the first one
that appears in the stream.
EL
Dynamic range control (DRC) is supported and can be controlled by the user to limit or enhance
the dynamic range of the material that contains DRC information.
Both Sine window and Kaiser-Bessel-derived window are supported.
For MPEG4 pseudo-random noise substitution (PNS) is supported. Short frames (120 and 960
samples) are not fully supported.
PR
Spectral Band Replication (SBR) level 3, and Parametric Stereo (PS) level 3 are supported
(HE-AAC v2). Level 3 means that maximum of 2 channels, samplerates upto and including
48 kHz without and with SBR (with or without PS) are supported. Also, both mixing modes
(Ra and Rb ), IPD/OPD synthesis and 34 frequency bands resolution are implemented. The
downsampled synthesis mode (core coder samplerates > 24 kHz and <= 48 kHz with SBR) is
implemented.
SBR and PS decoding can also be disabled. Also different operating modes can be selected.
See config1 and sbrAndPsStatus in section 10.11 : "Extra parameters".
If enabled, the internal clock (CLKI) is automatically increased if AAC decoding needs a higher
Version: 0.42, 2011-11-24
27
VS1063a Datasheet
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
clock. PS and SBR operation is automatically switched off if the internal clock is too slow for
correct decoding. Generally HE-AAC v2 files need 4.5× clock to decode both SBR and PS
content. This is why 3.5× + 1.0× clock is the recommended default.
For AAC the streaming ADTS format is recommended. This format allows easy rewind and fast
forward because resynchronization is easily possible.
In addition to ADTS (.aac), MPEG2 ADIF (.aac) and MPEG4 AUDIO (.mp4 / .m4a) files are
played, but these formats are less suitable for rewind and fast forward operations. You can still
implement these features by using the jump points table, or using slightly less robust but much
easier automatic resync mechanism (see Section 10.5.4).
Because 3GPP (.3gp) and 3GPPv2 (.3g2) files are just MPEG4 files, those that contain only
HE-AAC or HE-AACv2 content are played.
Important Note: To be able to play the .3gp, .3g2, .mp4 and .m4a files, the mdat atom must
be the last atom in the MP4 file. Because VS1063a receives all data as a stream, all metadata
must be available before the music data is received. Several MP4 file formatters do not satisfy
this requirement and some kind of conversion is required. This is also why the streamable
ADTS format is recommended.
AAC12 :
Samplerate / Hz
1
Maximum Bitrate kbit/s - for 2 channels
132 144 192 264 288 384 529
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
576
+
EL
48000
44100
32000
24000
22050
16000
12000
11025
8000
≤96
+
+
+
+
+
+
+
+
+
IM
Programs exist that optimize the .mp4 and .m4a into so-called streamable format that has the
mdat atom last in the file, and thus suitable for web servers’ audio streaming. You can use this
kind of tool to process files for VS1063a too. For example mp4creator -optimize file.mp4.
64000 Hz, 88200 Hz, and 96000 Hz AAC files are played at the highest possible samplerate
(48000 Hz with 12.288 MHz XTALI).
2
PR
Also all variable bitrate (VBR) formats are supported. Note that the table gives the maximum
bitrate allowed for two channels for a specific samplerate as defined by the AAC specification.
The decoder does not actually have a fixed lower or upper limit.
Version: 0.42, 2011-11-24
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VS1063a Datasheet
8.1.5
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
Supported WMA Decoder Formats
Windows Media Audio codec versions 2, 7, 8, and 9 are supported. All WMA profiles (L1,
L2, and L3) are supported. Previously streams were separated into Classes 1, 2a, 2b, and
3. The decoder has passed Microsoft’s conformance testing program. Windows Media Audio
Professional and Windows Media Audio Voice are different codecs and are not supported.
WMA 4.0 / 4.1:
Samplerate
/ Hz
8000
11025
16000
22050
32000
44100
48000
5
+
6
+
8
+
+
10
+
+
12
+
16
+
+
+
WMA 7:
5
+
6
+
8
+
+
WMA 8:
WMA 9:
5
+
6
+
8
+
+
+
+
12
+
16
+
+
+
+
+
+
+
+
20
+
+
+
10
+
+
12
+
16
20
+
+
+
+
+
+
EL
Samplerate
/ Hz
8000
11025
16000
22050
32000
44100
48000
10
Bitrate / kbit/s
22 32 40
5
+
6
+
8
+
+
10
+
+
PR
Samplerate
/ Hz
8000
11025
16000
22050
32000
44100
48000
+
+
+
+
Bitrate / kbit/s
22 32 40
+
+
+
+
+
IM
Samplerate
/ Hz
8000
11025
16000
22050
32000
44100
48000
20
12
+
16
20
+
+
+
+
+
+
+
22
+
Bitrate / kbit/s
22 32 40
+
+
+
+
+
48
64
80
96
128 160 192
+
+
+
+
+
+
+
+
48
64
80
96
128 160 192
+
+
+
+
+
+
+
48
64
80
96
128 160 192
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Bitrate / kbit/s
32 40 48 64
80
96
128 160 192 256 320
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
In addition to these expected WMA decoding profiles, all other bitrate and samplerate combinations are supported, including variable bitrate WMA streams. Note that WMA does not
consume the bitstream as evenly as MP3, so you need a higher peak transfer capability for
clean playback at the same bitrate.
Version: 0.42, 2011-11-24
29
VS1063a Datasheet
8.1.6
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
Supported FLAC Decoder Formats
The FLAC decoder provides the highest quality by providing lossless audio decompression.
Upto 48 kHz and 24-bit FLAC files with upto two channels are supported.
Because of the high data rate, the requirements for data transfer are much higher than for lossy
codecs. Because of compression, audio buffer being shorter than the default FLAC block size,
and some design choices in the FLAC format itself, the peak data transfer rate must be even
higher than the sustained data rate required for uncompressed WAV files.
The FLAC decoder lowers the peak data transfer requirement a little by providing a larger
stream buffer (12 KiB).
8.1.7
Supported RIFF WAV Decoder Formats
The following RIFF WAV formats are supported, with 1 or 2 audio channels and any samplerate
upto XT ALI/256 (48 kHz with 12.288 MHz clock).
Comments
32, 24, 16 and 8 bits
IEEE floating point data
non-linear-quantized 8-bit samples (G.711 A-law)
non-linear-quantized 8-bit samples (G.711 µ-law)
4 bits per sample
For supported MP3 modes, see Chapter 8.1.1
two samples in 8 bits, same as 0x28f
two samples in 8 bits, same as 0x65
32, 24, 16 and 8 bits, default channel configuration supported
EL
IM
Name
PCM
IEEE_FLOAT
ALAW
MULAW
IMA_ADPCM
MPEGLAYER3
G722_ADPCM
ADPCM_G722
Extended PCM
PR
Format
0x01
0x03
0x06
0x07
0x11
0x55
0x65
0x28f
0xfffe
Version: 0.42, 2011-11-24
30
VS1063a Datasheet
8.2
8.2.1
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
Supported Audio Encoding Formats
Supported MP3 (MPEG layer III) Encoding Formats
VS1063a supports all MP3 samplerates and bitrates, in stereo and mono, both with constant
bit-rate (CBR) or variable bitrate (VBR). The following tables apply to both formats.
Symbol
++
+
x
v
<
-
Conventions
Description
Format is supported and recommended for this channel configuration and bitrate.
Format is supported.
Format is supported but use is strongly discouraged for quality reasons.
Format is supported but for best quality lower samplerate with same bitrate is recommended.
Format is supported but lower bitrate will give same quality.
Format exists but isn’t supported.
Format doesn’t exist.
MPEG 1.0 layer III (MP3 full-rates), stereo:
Samplerate / Hz
40
v
v
v
48
v
v
v
56
v
v
v
64
v
v
v
Bitrate / kbit/s, stereo
80 96 112 128
v
v
+
+
v
+
+
+
+
+
++ ++
IM
48000
44100
32000
32
v
v
v
160
++
+
+
192
++
+
+
224
++
+
+
256
++
+
+
320
++
+
<
96
++
+
+
+
+
+
112
+
+
+
+
+
+
128
+
+
+
+
+
<
144
+
<
<
<
<
<
160
<
<
<
<
<
<
160
++
+
+
192
++
+
+
224
++
+
<
256
++
+
<
320
<
<
<
96
+
+
<
<
<
<
112
+
+
<
<
<
<
128
<
<
<
<
<
<
144
<
<
<
<
<
<
160
<
<
<
<
<
<
MPEG 2.0 & 2.5 layer III (MP3 low rates), stereo:
Samplerate / Hz
16
v
v
v
v
v
++
24
v
v
v
v
v
++
32
v
v
v
+
+
++
40
v
v
+
++
+
+
Bitrate / kbit/s, stereo
48 56 64 80
v
v
+
++
v
+
+
+
+
+
++ +
++ ++ +
+
+
+
+
+
+
+
+
+
EL
24000
22050
16000
12000
11025
8000
8
x
x
x
v
v
++
MPEG 1.0 layer III (MP3 full-rates), mono:
Samplerate / Hz
48000
44100
32000
32
v
v
+
40
v
v
+
48
v
v
+
56
+
+
++
64
+
+
++
Bitrate / kbit/s, mono
80 96 112 128
++ ++ ++ ++
+
+
+
+
+
+
+
+
PR
MPEG 2.0 & 2.5 layer III (MP3 low rates), mono:
Samplerate / Hz
24000
22050
16000
12000
11025
8000
8
v
v
v
v
v
++
16
v
v
v
v
v
++
Version: 0.42, 2011-11-24
24
+
+
+
++
+
+
32
+
+
++
+
+
+
40
+
+
++
+
+
+
Bitrate / kbit/s, mono
48 56 64 80
++ +
+
+
+
+
+
+
+
+
+
+
+
+
+
<
+
+
+
<
+
<
<
<
31
VS1063a Datasheet
8.2.2
SUPPORTED AUDIO FORMATS
IN
AR
Y
8
Supported Ogg Vorbis Encoding Formats
The Ogg Vorbis Encoder supports encoding in mono and stereo, with any samplerate between
1 and 48000 Hz, and with different quality settings. Ogg Vorbis is always encoded using variable
bitrate (VBR).
Some example setting profiles are provided below. Note, however, that the encoder is not
limited to these configurations.
The “Voice” profiles are intended for speech applications.
Voice: 8000 Hz mono
Quality setting 0 1 2
3
4
5
6
7
8
Typical kbit/s
6 7 9 10 12 13 16 19 22
9
25
10
28
“Wideband Voice” is intended to be used when high speech quality is required.
Wideband Voice: 16000 Hz mono
Quality setting 0
1
2
3
4
5
6
7
8
9 10
Typical kbit/s
7 11 14 18 21 25 31 37 43 49 55
IM
“Wideband Stereo Voice” is intended to be used when high speech quality with directional
information is required.
Wideband Stereo Voice: 16000 Hz stereo
Quality setting
0
1
2
3
4
5
6
7
8
9
10
Typical kbit/s
10 18 26 34 42 50 65 81 96 112 127
When extremely high quality speech is required, use the “HiFi Voice” profiles.
HiFi Voice, 48000 Hz mono
Quality setting
0
1
2
3
4
5
6
7
8
9
10
Typical kbit/s
37 47 57 68 78 88 99 110 122 133 144
8.2.3
EL
The “Music” profiles are intended for HiFi music.
HiFi Voice, 48000 Hz stereo
Quality setting
0
1
2
3
4
5
6
Typical kbit/s
53 72 91 110 129 148 185
7
222
8
259
9
296
10
333
Supported RIFF WAV Encoding Formats
PR
The following RIFF WAV formats are supported in encoding and codec modes with one or two
channels and samplerates upto XT ALI/256 (48 kHz with 12.288 MHz clock).
Format
0x01
0x06
0x07
0x11
0x28f
Name
PCM
ALAW
MULAW
IMA_ADPCM
ADPCM_G722
Version: 0.42, 2011-11-24
Comments
16 and 8 bits linear PCM
A-law, non-linear-quantized 8-bit samples
µ-law, non-linear-quantized 8-bit samples
IMA ADPCM, 4 bits per sample, 505 samples per block
G722 subband ADPCM, two samples in 8 bits
32
VS1063a Datasheet
9
9.1
Functional Description
Main Features
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
VS1063a is based on a proprietary digital signal processor, VS_DSP. It contains all the code
and data memory needed for Ogg Vorbis, MP3, AAC, WMA, FLAC and WAV PCM + ADPCM
audio decoding together with serial interfaces, a multirate stereo audio DAC and analog output
amplifiers and filters.
Also MP3, OGG, PCM, ADPCM, µ-law, A-law and G.722 audio encoding is supported using a
microphone amplifier and/or line-level inputs and a stereo A/D converter.
For streaming applications there exists a codec mode that supports full-duplex operation using
PCM, ADPCM, µ-law, A-law or G.722 formats. The formats and samplerates don’t have to be
the same in both directions.
PR
EL
IM
A UART is provided for debugging purposes to connect with VLSI Solution’s Integrated Developments Environment VSIDE.
Version: 0.42, 2011-11-24
33
VS1063a Datasheet
9.2
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
Decoder Data Flow of VS1063a
SDI bus
Bitstream
Bitstream
FIFO
WAV, MP2/3,
OGG, WMA,
AAC, FLAC
EarSpeakerLevel!=0 &
SPEEDSHIFTER_ON=0
5−channel
equalizer
PCM audio
AIADDR=0
SB_AMPLITUDE=0
User
plugin
Bass
enhancer
SB_AMPLITUDE != 0
AIADDR != 0
MONO_OUTPUT=0
Mono
MONO_OUTPUT=1
PAUSE_ON
0
SPEEDSHIFTER_ON=0&
earSpeakerLevel=0
Treble
control
Speed
shifter
SPEEDSHIFTER_ON=1
ST_AMPLITUDE!=0
To DAC
DAC
SRC
SCI_VOL
PCMMIXER_ON=1&
ADMIXER_ON=0
PCMMISER_ON=0 & ADMIXER_ON=0
Sidestream
SDM
ADMIXER_ON=1
IM
ADC
EarSpeaker
ST_AMPLITUDE=0
Audio
FIFO
Pause
SCI bus
Mic/Line In
SB_AMPL=0 &
ST_AMPL=0 &
EQ5 Enable = 1
adMixerGain or
pcmMixerVol
Figure 13: Decoder data flow of VS1063a
Figure 13 presents the decoder dataflow of VS1063a.
EL
First, depending on the audio data, and provided encoding mode is not set (register SCI_MODE
but SM_ENCODE is 0), audio bitstream is received from the SDI bus and decoded.
After decoding, if SCI_AIADDR is non-zero, user plugin code is executed from the address
pointed to by that register. For more details, see VS1063a Programmer’s Guide.
Then data may be sent to the Bass Enhancer and Treble Control depending on the SCI_BASS
register. If SCI_BASS is 0, but EQ5 Enable bit in Extra Parameters register playMode is 1, the
the 5-channel equalizer is used.
PR
Next, if bit speedShifterEnable of Extra Parameters register playMode is 1, speed shifter is
called. Otherwise, and if EarSpeakerLevel is not 0, headphone processing is done.
At this stage, and if Extra Parameters register playMode bit monoOutputSelect is 1, audio is
converted to mono.
If Extra Parameters register playMode bit pause is 1, audio transmission is stopped.
Version: 0.42, 2011-11-24
34
VS1063a Datasheet
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
After that the data is fed to the Audio FIFO. The size of the audio FIFO is 2048 stereo (2×16-bit)
samples, or 8 KiB.
Now decoded and processed audio is sent to a samplerate converter, where volume control is
applied. After this step it is combined with an optional sidestream which may be either PCM
samples coming through the SCI bus or analog data from the line/mic input.
The samplerate converter upsamples all different samplerates to XTALI/2, or 128 times the
highest usable samplerate with 18-bit precision. Volume control is performed in the upsampled
domain. New volume settings are loaded only when the upsampled signal crosses the zero
point (or after a timeout). This zero-crossing detection almost completely removes all audible
noise that occurs when volume is suddenly changed.
The samplerate conversion to a common samplerate removes the need for complex PLL-based
clocking schemes and allows almost unlimited samplerate accuracy with one fixed input clock
frequency. With a 12.288 MHz clock, the DA converter operates at 128 × 48 kHz, i.e. 6.144
MHz, and creates a stereo in-phase analog signal. The oversampled output is low-pass filtered
by an on-chip analog filter. This signal is then forwarded to the earphone amplifier.
9.3
Encoder Data Flow of VS1063a
To DAC
Mic/Line In
ADC
IM
DAC
SRC
Resampler
SRC
Software
decimator
Audio in
FIFO
SCI_VOL
To UART
UartTxEna=1
MP3,OGG,
WAV
Encoder
Bitstream
out FIFO
To SCI
UartTxEna=0
EL
Figure 14: Encoder data flow of VS1063a
Figure 14 presents the encoder dataflow of VS1063a.
Depending on which samplerate the user has requested, data is read from the Analog-to-Digital
Converter with one of samplerates or 12, 24, or 48 kHz. A 10 Hz subsonic high-pass filter (not
shown in the figure) is applied to the signal.
Here audio is split into two: one path going to monitoring, the other path going to the encoder.
PR
Depending whether the signal needs to be resampled, it may be fed to the Resampler Sample
Rate Converter that is used for samplerate fine tuning, and/or to the Software decimator which
can decimate the signal by 2 or 3. (E.g. if chosen samplerate is 8 kHz, it will be digitized at
24 kHz, then downsampled by 3 with the Software decimator).
From the decimator stages, audio is fed to audio in FIFO, from which the encoder reads the
samples.
The bitstream generated by the encoder is fed to the Bitstream out FIFO. The data is then either
read through SCI by the user or output by the VS1063a to the UART.
Version: 0.42, 2011-11-24
35
VS1063a Datasheet
9.4
Codec Data Flow of VS1063a
SDI bus
Bitstream
FIFO
Bitstream
WAV
SB_AMPL=0 &
ST_AMPL=0 &
EQ5 Enable = 1
EarSpeakerLevel!=0 &
SPEEDSHIFTER_ON=0
5−channel
equalizer
PCM audio
AIADDR=0
SB_AMPLITUDE=0
User
plugin
Bass
enhancer
SB_AMPLITUDE != 0
AIADDR != 0
MONO_OUTPUT=0
Mono
Pause
MONO_OUTPUT=1
PAUSE_ON
AEC
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
EarSpeaker
ST_AMPLITUDE=0
SPEEDSHIFTER_ON=0&
earSpeakerLevel=0
Treble
control
Speed
shifter
ST_AMPLITUDE!=0
Audio
FIFO
SPEEDSHIFTER_ON=1
To DAC
DAC
SRC
SCI_VOL
To UART
Mic/Line In
ADC
IM
UartTxEna=1
Software
decimator
Audio in
FIFO
WAV
Encoder
Bitstream
out FIFO
To SCI
UartTxEna=0
Figure 15: Codec data flow of VS1063a
Figure 15 presents the codec dataflow of VS1063a.
EL
The decoder and encoder paths are almost similar as in the decoder and encoder data flow
Chapters 9.2 and 9.3, except that there is no decoder audio side path and the amount of
samplerates in the encoder is much more limited because the Resampler SRC is not used.
A new path is when Acoustic Echo Cancellation (AEC) is active. In this case there is a feedback
from the output path to the input path.
Note: Do not use Speed shifter in Codec mode, nor Pause mode.
PR
Note: Do not use EarSpeaker if AEC is active.
Note: If AEC is used, encoding and decoding samplerates must be the same. Otherwise they
may be different.
Version: 0.42, 2011-11-24
36
VS1063a Datasheet
9.5
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
EarSpeaker Spatial Processing
While listening to headphones the sound has a tendency to be localized inside the head. The
sound field becomes flat and lacking the sensation of dimensions. This is an unnatural, awkward and sometimes even disturbing situation. This phenomenon is often referred in literature
as ‘lateralization’, meaning ’in-the-head’ localization. Long-term listening to lateralized sound
may lead to listening fatigue.
All real-life sound sources are external, leaving traces to the acoustic wavefront that arrives to
the ear drums. From these traces, the auditory system of the brain is able to judge the distance
and angle of each sound source. In loudspeaker listening the sound is external and these
traces are available. In headphone listening these traces are missing or ambiguous.
PR
EL
IM
EarSpeaker processes sound to make listening via headphones more like listening to the same
music from real loudspeakers or live music. Once EarSpeaker processing is activated, the
instruments are moved from inside to the outside of the head, making it easier to separate
the different instruments (see Figure 16). The listening experience becomes more natural and
pleasant, and the stereo image is sharper as the instruments are widely on front of the listener
instead of being inside the head.
Figure 16: EarSpeaker externalized sound sources vs. normal inside-the-head sound
Note that EarSpeaker differs from any common spatial processing effects, such as echo, reverb,
or bass boost. EarSpeaker accurately simulates the human auditory model and real listening
environment acoustics. Thus is does not change the tonal character of the music by introducing
artificial effects.
Version: 0.42, 2011-11-24
37
VS1063a Datasheet
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
EarSpeaker processing can be adjusted using parametric_x.earSpeakerLevel. Different levels
simulate a little different type of acoustical situation, suiting different personal preferences and
types of recording.
• 0: Best option when listening through loudspeakers or if the audio to be played contains
binaural preprocessing.
• 12000: Suited for listening to normal musical scores with headphones, very subtle.
• 38000: Suited for listening to normal musical scores with headphones, moves sound
source further away than minimal.
• 50000: Suited for old or ’dry’ recordings, or if the audio to be played is artificial.
EarSpeaker requires approximately 11 MIPS at 48 kHz samplerate.
9.6
Serial Data Interface (SDI)
The serial data interface is meant for transferring compressed data for the different decoders of
VS1063a.
IM
If the input of the decoder is invalid or it is not received fast enough, analog outputs are automatically muted.
Also several different tests may be activated through SDI as described in Chapter 10.
9.7
Serial Control Interface (SCI)
EL
The serial control interface is compatible with the SPI bus specification. Data transfers are
always 16 bits. VS1063a is controlled by writing and reading the registers of the interface.
The main controls of the serial control interface are:
control of the operation mode, clock, and builtin effects
access to status information and header data
receiving encoded data in recording mode
uploading and controlling user programs
PR
•
•
•
•
Version: 0.42, 2011-11-24
38
VS1063a Datasheet
9.8
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
SCI Registers
VS1063a sets DREQ low when it detects an SCI operation (this delay is 16 to 40 CLKI cycles
depending on whether an interrupt service routine is active) and restores it when it has processed the operation. The duration depends on the operation. If DREQ is low when an SCI
operation is performed, it also stays low after SCI operation processing.
If DREQ is high before an SCI operation, do not start a new SCI/SDI operation before DREQ is
high again. If DREQ is low before a SCI operation because the SDI can not accept more data,
make certain there is enough time to complete the operation before sending another.
Typ.
rw
rw
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
Reset
0x40006
0x000C3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
IM
Reg
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
SCI registers, prefix SCI_
Write Time1 Name
Description
4
80 CLKI
MODE
Mode control
80 CLKI STATUS
Status of VS1063a
80 CLKI BASS
Built-in bass/treble control
1200 XTALI5 CLOCKF
Clock freq + multiplier
100 CLKI DECODE_TIME Decode time in seconds
450 CLKI2 AUDATA
Misc. audio data
100 CLKI WRAM
RAM write/read
100 CLKI WRAMADDR
Set address for RAM write/read
80 CLKI HDAT0
Stream header data 0
80 CLKI HDAT1
Stream header data 1
2
210 CLKI
AIADDR
Start address of application/plugin
80 CLKI VOL
Volume control
2
80 CLKI
AICTRL0
Application control register 0
80 CLKI2 AICTRL1
Application control register 1
2
80 CLKI
AICTRL2
Application control register 2
80 CLKI2 AICTRL3
Application control register 3
2
3
EL
This is the worst-case time that DREQ stays low after writing to this register. The user may
choose to skip the DREQ check for those register writes that take less than 100 clock cycles to
execute and use a fixed delay instead.
In addition, the cycles spent in the user application/plugin routine must be counted.
Firmware changes the value of this register immediately to 0x68 (analog enabled), and after
a short while to 0x60 (analog drivers enabled).
4
When mode register write specifies a software reset the worst-case time is 22000 XTALI
cycles.
5
PR
If the clock multiplier is changed, writing to SCI_CLOCKF register may force internal clock
to run at 1.0 × XTALI for a while. Thus it is not a good idea to send SCI or SDI bits while this
register update is in progress.
6
Firmware changes the value of this register immediately to 0x4800.
Reads from all SCI registers complete in under 100 CLKI cycles, except for SCI_AIADDR,
which may take 200 cycles. In addition the cycles spent in the user application/plugin routine
must be counted to the read time of SCI_AIADDR, SCI_AUDATA, and SCI_AICTRL0. . . 3.
Some bits in SCI_MODE and SCI_STATUS are hardware bits; other registers only control the
firmware. See VS1063 Hardware Guide for details.
Version: 0.42, 2011-11-24
39
VS1063a Datasheet
9.8.1
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
SCI_MODE (RW)
SCI_MODE is used to control the operation of VS1063a and defaults to 0x0800 (SM_SDINEW
set).
Note: “Mode” in the following table tells if that bit is a hardware (HW) or software (SW) control.
Name
SM_DIFF
Bit
0
Mode
SW
Function
Differential
1
SW
Allow MPEG layer II
SM_RESET
2
SW
Soft reset
SM_CANCEL
3
SW
Cancel decoding current file
4
SW
reserved
5
SW
Allow SDI tests
6
SW
reserved
7
SW
reserved
SM_TESTS
SM_DACT
8
SM_SDIORD
9
10
SM_SDINEW
11
SM_ENCODE
12
-
HW
DCLK active edge
HW
SDI bit order
HW
Share SPI chip select
HW
VS10xx native SPI modes
SW
Activate Encoding
EL
SM_SDISHARE
IM
SM_LAYER12
13
SW
-
SM_LINE1
14
HW
MIC / LINE1 selector
SM_CLK_RANGE
15
HW
Input clock range
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
normal in-phase audio
left channel inverted
no
yes
no reset
reset
no
yes
right
wrong
not allowed
allowed
right
wrong
right
wrong
rising
falling
MSb first
MSb last
no
yes
no
yes
no
yes
right
wrong
MICP
LINE1
12. . . 13 MHz
24. . . 26 MHz
PR
When SM_DIFF is set, the player inverts the left channel output. For a stereo input this creates
virtual surround, and for a mono input this creates a differential left/right signal.
SM_LAYER12 enables MPEG 1.0 and 2.0 layer II decoding in addition to layer III. If you enable
Layer II decoding, you are liable for any patent issues that may arise. Joint licensing of
MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II.
Software reset is initiated by setting SM_RESET to 1. This bit is cleared automatically.
If you want to stop decoding a in the middle, set SM_CANCEL, and continue sending data
Version: 0.42, 2011-11-24
40
VS1063a Datasheet
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
honouring DREQ. When SM_CANCEL is detected by a codec, it will stop decoding and return
to the main loop. The stream buffer content is discarded and the SM_CANCEL bit cleared.
SCI_HDAT1 will also be cleared. See Chapter 10.5.2 for details.
If SM_TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 10.12.
SM_DACT defines the active edge of data clock for SDI. When ’0’, data is read at the rising
edge, when ’1’, data is read at the falling edge.
When SM_SDIORD is clear, bytes on SDI are sent MSb first. By setting SM_SDIORD, the user
may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however,
still sent in the default order. This register bit has no effect on the SCI bus.
Setting SM_SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, if also SM_SDINEW is set.
Setting SM_SDINEW will activate VS10xx native serial modes as described in Chapters 7.2.1 and 7.4.2.
Note, that this bit is set as a default when VS1063a is started up.
IM
By activating SM_ENCODE and SM_RESET at the same time, the user will activate the encoding or codec mode (see Chapter 10.7 on page 55). However, note that if the recommended
VS1063a Patches package is used (http://www.vlsi.fi/en/support/software/vs10xxplugins.html),
then audio encoding is started as instructed in the manual of the package.
SM_LINE_IN is used to select the left-channel input for analog input. If ’0’, differential microphone input pins MICP and MICN are used; if ’1’, line-level MICP/LINEIN1 pin is used.
PR
EL
SM_CLK_RANGE activates a clock divider in the XTAL input. When SM_CLK_RANGE is set,
the clock is divided by 2 at the input. From the chip’s point of view e.g. 24 MHz becomes
12 MHz. SM_CLK_RANGE should be set as soon as possible after a chip reset.
Version: 0.42, 2011-11-24
41
VS1063a Datasheet
9.8.2
SCI_STATUS (RW)
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
SCI_STATUS contains information on the current status of VS1063a. It also controls some
low-level things that the user does not usually have to care about.
Note: “Mode” in the following table tells if that bit is a hardware (HW) or software (SW) control.
Name
SS_DO_NOT_JUMP
SS_SWING
SS_VCM_OVERLOAD
SS_VCM_DISABLE
SS_VER
SS_APDOWN2
SS_APDOWN1
SS_AD_CLOCK
SS_REFERENCE_SEL
Bits
15
14:12
11
10
9:8
7:4
3
2
1
0
Mode
SW
HW
HW
HW
SW
SW
HW
HW
HW
HW
Description
Header in decode, do not fast forward/rewind
Set swing to +0 dB, +0.5 dB, . . . , or +3.5 dB
GBUF overload indicator ’1’ = overload
GBUF overload detection ’1’ = disable
reserved
Version
Analog driver powerdown
Analog internal powerdown
AD clock select, ’0’ = 6 MHz, ’1’ = 3 MHz
Reference voltage selection, ’0’ = 1.23 V, ’1’ = 1.65 V
IM
SS_DO_NOT_JUMP is set when a WAV, Ogg Vorbis, WMA, MP4, or AAC-ADIF header is
being decoded and jumping to another location in the file is not allowed. If you use soft reset or
cancel, clear this bit yourself or it can be accidentally left set.
SS_SWING allows you to go above the 0 dB volume setting. Value 0 is normal mode, 1 gives
+0.5 dB, and 2 gives +1.0 dB. Settings from 3 to 7 cause the DAC modulator to be overdriven
and should not be used. You can use SS_SWING with I2S to control the amount of headroom.
EL
VS1063a contains GBUF protection circuit which disconnects the GBUF driver when too much
current is drawn, indicating a short-circuit to ground. SS_VCM_OVERLOAD is high while the
overload is detected. SS_VCM_DISABLE can be set to disable the protection feature.
SS_VER is 0 for VS1001, 1 for VS1011, 2 for VS1002, 3 for VS1003, 4 for VS1053 and VS8053,
5 for VS1033, 6 for VS1063, and 7 for VS1103.
SS_APDOWN2 controls analog driver powerdown. SS_APDOWN1 controls internal analog
powerdown. These bits are meant to be used by the system firmware only.
PR
If the user wants to powerdown VS1063a with a minimum power-off transient, set SCI_VOL to
0xffff, then wait for at least a few milliseconds before activating reset.
SS_AD_CLOCK can be set to divide the AD modulator frequency by 2 if XTALI is in the
24. . . 26 MHz range.
If AVDD is at least 3.3 V, SS_REFERENCE_SEL can be set to select 1.65 V reference voltage
to increase the analog output swing.
Version: 0.42, 2011-11-24
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VS1063a Datasheet
9.8.3
SCI_BASS (RW)
Name
ST_AMPLITUDE
ST_FREQLIMIT
SB_AMPLITUDE
SB_FREQLIMIT
Bits
15:12
11:8
7:4
3:0
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
Description
Treble Control in 1.5 dB steps (-8. . . 7, 0 = off)
Lower limit frequency in 1000 Hz steps (1. . . 15)
Bass Enhancement in 1 dB steps (0. . . 15, 0 = off)
Lower limit frequency in 10 Hz steps (2. . . 15)
The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the
most out of the users earphones without causing clipping.
VSBE is activated when SB_AMPLITUDE is non-zero. SB_AMPLITUDE should be set to the
user’s preferences, and SB_FREQLIMIT to roughly 1.5 times the lowest frequency the user’s
audio system can reproduce. For example setting SCI_BASS to 0x00f6 will have 15 dB enhancement below 60 Hz.
Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music
material, or when the playback volume is not set to maximum. It also does not create bass: the
source material must have some bass to begin with.
IM
Treble Control VSTC is activated when ST_AMPLITUDE is non-zero. For example setting
SCI_BASS to 0x7a00 will have 10.5 dB treble enhancement at and above 10 kHz.
Bass Enhancer uses about 2.1 MIPS and Treble Control 1.2 MIPS at 44100 Hz samplerate.
Both can be on simultaneously.
In VS1063a bass and treble initialization and volume change is delayed until the next batch of
samples are sent to the audio FIFO. Thus, unlike with earlier VS10XX chips, audio interrupts
can no longer be missed when SCI_BASS or SCI_VOL is written to.
PR
EL
When either the Bass Enhancer or Treble Control is active, the 5-band equalizer (Chapter 10.11.6)
is not run.
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VS1063a Datasheet
9.8.4
SCI_CLOCKF (RW)
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
The operation of SCI_CLOCKF has changed slightly in VS1063a compared to VS1003 and
VS1033. Multiplier 1.5× and addition 0.5× have been removed to allow higher clocks to be
configured.
Name
SC_MULT
SC_ADD
SC_FREQ
SCI_CLOCKF bits
Bits
Description
15:13 Clock multiplier
12:11 Allowed multiplier addition
10: 0 Clock frequency
SC_MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.
When the multiplier is changed by more than 0.5×, the chip runs at 1.0× clock for a few hundres
clock cycles. The values are as follows:
MASK
0x0000
0x2000
0x4000
0x6000
0x8000
0xa000
0xc000
0xe000
CLKI
XTALI
XTALI×2.0
XTALI×2.5
XTALI×3.0
XTALI×3.5
XTALI×4.0
XTALI×4.5
XTALI×5.0
IM
SC_MULT
0
1
2
3
4
5
6
7
SC_ADD tells how much the decoder firmware is allowed to add to the multiplier specified by
SC_MULT if more cycles are temporarily needed to decode a WMA or AAC stream. The values
are:
MASK
0x0000
0x0800
0x1000
0x1800
Multiplier addition
No modification is allowed
1.0×
1.5×
2.0×
EL
SC_ADD
0
1
2
3
SC_FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz.
XTALI is set in 4 kHz steps. The formula for calculating the correct value for this register is
XT ALI−8000000
(XTALI is in Hz).
4000
Note: The default value 0 is assumed to mean XTALI=12.288 MHz.
PR
Note: because maximum samplerate is
12.288 MHz.
XT ALI
256 ,
all samplerates are not available if XTALI <
Note: Automatic clock change can only happen when decoding WMA and AAC files. Automatic
clock change is done one 0.5× at a time. This does not cause a drop to 1.0× clock and you can
use the same SCI and SDI clock throughout the file.
Example: If SCI_CLOCKF is 0x8BE8, SC_MULT = 4, SC_ADD = 1 and SC_FREQ = 0x3E8 = 1000.
This means that XTALI = 1000 × 4000 + 8000000 = 12 MHz. The clock multiplier is set to
3.5×XTALI = 42 MHz, and the maximum allowed multiplier that the firmware may automatically
choose to use is (3.5 + 1.0)×XTALI = 54 MHz.
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9.8.5
SCI_DECODE_TIME (RW)
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
When decoding correct data, current decoded time is shown in this register in full seconds.
The user may change the value of this register. In that case the new value should be written
twice to make absolutely certain that the change is not overwritten by the firmware. A write to
SCI_DECODE_TIME also resets the bitRatePer100 calculation.
SCI_DECODE_TIME is reset at every hardware and software reset. It is no longer cleared
when decoding of a file ends to allow the decode time to proceed automatically with looped
files and with seamless playback of multiple files.
With fast playback (see the playSpeed extra parameter) the decode time also counts faster.
Some codecs (WMA and Ogg Vorbis) can also indicate the absolute play position, see the
positionMsec extra parameter in section 10.11.
9.8.6
SCI_AUDATA (RW)
When decoding correct data, the current samplerate and number of channels can be found
in bits 15:1 and 0 of SCI_AUDATA, respectively. Bits 15:1 contain the samplerate divided by
two, and bit 0 is 0 for mono data and 1 for stereo. Writing to SCI_AUDATA will change the
samplerate directly.
IM
Example: 44100 Hz stereo data reads as 0xAC45 (44101).
Example: 11025 Hz mono data reads as 0x2B10 (11024).
Example: Writing 0xAC80 sets samplerate to 44160 Hz, stereo mode does not change.
To reduce digital power consumption when idle, you can write a low samplerate to SCI_AUDATA.
9.8.7
SCI_WRAM (RW)
9.8.8
EL
SCI_WRAM is used to upload application programs and data to instruction and data RAMs. The
start address must be initialized by writing to SCI_WRAMADDR prior to the first write/read of
SCI_WRAM. One 16-bit data word can be transferred with one SCI_WRAM write/read. As the
instruction word is 32 bits long, two consecutive writes/reads are needed for each instruction
word. The byte order is big-endian (i.e. most significant words first). After each full-word
write/read, the internal pointer is autoincremented.
SCI_WRAMADDR (W)
PR
SCI_WRAMADDR is used to set the program address for following SCI_WRAM writes/reads.
Use an address offset from the following table to access X, Y, I or peripheral memory.
WRAMADDR
Dest. addr.
Bits/ Description
Start. . . End
Start. . . End
Word
0x0000. . . 0x3FFF
0x0000. . . 0x3FFF 16
X data RAM
0x4000. . . 0x7FFF
0x0000. . . 0x3FFF 16
Y data RAM
0x8000. . . 0x8FFF
0x0000. . . 0x0FFF 32
Instruction RAM
0xC000. . . 0xC0BF 0xC000. . . 0xC0BF 16
I/O
0xC0C0. . . 0xC0FF 0x1E00. . . 0x1E3F 16
parametric_x
0xE000. . . 0xFFFF 0xE000. . . 0xFFFF 16
Y data RAM
Note: Unless otherwise specified, only user areas in X, Y, and instruction memory should be accessed.
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VS1063a Datasheet
9.8.9
SCI_HDAT0 and SCI_HDAT1 (R)
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
For WAV files, SCI_HDAT1 contains 0x7665 (“ve”). SCI_HDAT0 contains the data rate measured in bytes per second for all supported RIFF WAVE formats. To get the bitrate of the file,
multiply the value by 8.
Note: if bitrate is over 524280 bit/s, SCI_HDAT1 value saturates to 65535.
For AAC ADTS streams, SCI_HDAT1 contains 0x4154 (“AT”). For AAC ADIF files, SCI_HDAT1
contains 0x4144 (“AD”). For AAC .mp4 / .m4a files, SCI_HDAT1 contains 0x4D34 (“M4”).
SCI_HDAT0 contains the average data rate in bytes per second. To get the bitrate of the file,
multiply the value by 8.
For WMA files, SCI_HDAT1 contains 0x574D (“WM”) and SCI_HDAT0 contains the data rate
measured in bytes per second. To get the bitrate of the file, multiply the value by 8.
For Ogg Vorbis files, SCI_HDAT1 contains 0x4F67 “Og”. SCI_HDAT0 contains the average
data rate in bytes per second. To get the bitrate of the file, multiply the value by 8.
PR
EL
IM
When FLAC format is detected, SCI_HDAT1 contains “fL” (0x664c). SCI_HDAT0 contains the
average data rate in byte quadruples per second. To get the bitrate of the file, multiply the value
by 32.
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VS1063a Datasheet
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
For MP3 files, SCI_HDAT1 is between 0xFFE0 and 0xFFFF. SCI_HDAT1 / 0 contain the following:
Function
syncword
ID
HDAT1[2:1]
layer
HDAT1[0]
protect bit
HDAT0[15:12]
HDAT0[11:10]
bitrate
samplerate
HDAT0[9]
pad bit
HDAT0[8]
HDAT0[7:6]
private bit
mode
HDAT0[5:4]
HDAT0[3]
HDAT0[2]
3
2
1
0
1
0
3
2
1
0
extension
copyright
original
emphasis
1
0
1
0
3
2
1
0
EL
HDAT0[1:0]
Value
2047
3
2
1
0
3
2
1
0
1
0
Explanation
stream valid
ISO 11172-3 MPG 1.0
ISO 13818-3 MPG 2.0 (1/2-rate)
MPG 2.5 (1/4-rate)
MPG 2.5 (1/4-rate)
I
II
III
reserved
No CRC
CRC protected
see bitrate table
reserved
32/16/ 8 kHz
48/24/12 kHz
44/22/11 kHz
additional slot
normal frame
not defined
mono
dual channel
joint stereo
stereo
see ISO 11172-3
copyrighted
free
original
copy
CCITT J.17
reserved
50/15 microsec
none
IM
Bit
HDAT1[15:5]
HDAT1[4:3]
When read, SCI_HDAT0 and SCI_HDAT1 contain header information that is extracted from
MP3 stream currently being decoded. After reset both registers are cleared, indicating no data
has been found yet.
PR
The “samplerate” field in SCI_HDAT0 is interpreted according to the following table:
“samplerate”
3
2
1
0
ID=3
32000
48000
44100
ID=2
16000
24000
22050
ID=0,1
8000
12000
11025
The “bitrate” field in HDAT0 is read according to the following table. Notice that for variable
bitrate stream the value changes constantly.
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VS1063a Datasheet
“bitrate”
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
Layer II
ID=3 ID=0,1,2
kbit/s
forbidden forbidden
384
160
320
144
256
128
224
112
192
96
160
80
128
64
112
56
96
48
80
40
64
32
56
24
48
16
32
8
-
Layer III
ID=3 ID=0,1,2
kbit/s
forbidden forbidden
320
160
256
144
224
128
192
112
160
96
128
80
112
64
96
56
80
48
64
40
56
32
48
24
40
16
32
8
-
IM
The average data rate in bytes per second can be read from memory, see the bitRatePer100
extra parameter. This variable contains the byte rate for all codecs. To get the bitrate of the file,
multiply the value by 100, and to get the kilobitrate, make a rounded divide by 10.
PR
EL
The bitrate calculation is not automatically reset between songs, but it can also be reset without
a software or hardware reset by writing to SCI_DECODE_TIME.
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VS1063a Datasheet
9.8.10
SCI_AIADDR (RW)
FUNCTIONAL DESCRIPTION
IN
AR
Y
9
SCI_AIADDR defines the start address of the application/plugin code that has been uploaded
earlier with SCI_WRAMADDR and SCI_WRAM registers. If no application code is used, this
register should not be written to, or it should be written zero.
Note: Reading SCI_AIADDR is not recommended.
For more details on how to write user applications and plugins, see VS1063 Programmer’s
Guide.
9.8.11
SCI_VOL (RW)
SCI_VOL is a volume control for the player hardware. The most significant byte of the volume
register controls the left channel volume, the low part controls the right channel volume. The
channel volume sets the attenuation from the maximum volume level in 0.5 dB steps. Thus,
maximum volume is 0x0000 and total silence is 0xFEFE.
IM
Setting SCI_VOL to 0xFFFF will activate analog powerdown mode.
Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (2.0/0.5)
= 4, 3.5/0.5 = 7 → SCI_VOL = 0x0407.
Example: SCI_VOL = 0x2424 → both left and right volumes are 0x24 * -0.5 = -18.0 dB
EL
In VS1063a bass and treble initialization and volume change is delayed until the next batch
of samples are sent to the audio FIFO. This delays the volume setting slightly. The hardware
volume control has zero-cross detection, which almost completely removes all audible noise
that occurs when volume is changed.
Note: After hardware reset the volume is set to full volume. Resetting the software does not
reset the volume setting.
SCI_AICTRL[x] (RW)
PR
9.8.12
SCI_AICTRL[x] registers ( x=[0. . . 3] ) can be used to access the user’s application/plugin program.
The SCI_AICTRL registers are also used as parameter registers when encoding audio. See
Chapter 10.7 for details.
For more details on how to write user applications, see VS1063 Programmer’s Guide.
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10
10.1
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Operation
Clocking
VS1063a operates on a single, nominally 12.288 MHz fundamental frequency master clock.
This clock can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface (pins XTALI and XTALO). This clock is used by the analog parts
and determines the highest available samplerate. With 12.288 MHz clock all samplerates upto
48000 Hz are available.
VS1063a can also use 24. . . 26 MHz clocks when bit SM_CLK_RANGE in the SCI_MODE register is set to 1. The system clock is then divided by 2 at the clock input and the IC gets a
12. . . 13 MHz input clock.
10.2
Hardware Reset
IM
When the XRESET signal is driven low, VS1063a is reset and all the control registers and
internal states are set to the initial values. XRESET-signal is asynchronous to any external
clock. The reset mode doubles as a full-powerdown mode, where both digital and analog parts
of VS1063a are in minimum power consumption stage, and where clocks are stopped. Also
XTALO is grounded.
When XRESET is asserted, all output pins go to their default states. All input pins will go to
high-impedance state (input state), except SO, which is still controlled by XCS.
EL
After a hardware reset (or at power-up) DREQ will stay down for around 22000 clock cycles,
which means an approximate 1.8 ms delay if VS1063a is run at 12.288 MHz. After this the
user should set such basic software registers as SCI_MODE, SCI_BASS, SCI_CLOCKF, and
SCI_VOL before starting decoding. See section 9.8 for details.
If the input clock is 24. . . 26 MHz, SM_CLK_RANGE should be set as soon as possible after a
chip reset without waiting for DREQ.
PR
Internal clock can be multiplied with a PLL. Supported multipliers through the SCI_CLOCKF
register are 1.0 × . . . 5.0× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If
typical values are wanted, the Internal Clock Multiplier needs to be set to 3.5× after reset. Wait
until DREQ rises, then write value 0x9800 to SCI_CLOCKF (register 3). See section 9.8.4 for
details.
Before VS1063a is used it is recommended to load and run the current VS1063a Patches
package. It is is available at http://www.vlsi.fi/en/support/software/vs10xxplugins.html .
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10.3
Software Reset
10
OPERATION
IN
AR
Y
VS1063a Datasheet
In some cases the decoder software has to be reset. This is done by activating bit SM_RESET
in register SCI_MODE (Chapter 9.8.1). Then wait for at least 2 µs, then look at DREQ. DREQ
will stay down for about 22000 clock cycles, which means an approximate 1.8 ms delay if
VS1063a is run at 12.288 MHz. When DREQ goes high, you may continue playback as usual.
As opposed to all earlier VS10XX chips, it is not recommended to do a software reset between
songs. This way the user may be sure that even files with low samplerates or bitrates are played
right to their end.
After each software reset it is recommended to load and run the current VS1063a Patches
package. It is available at http://www.vlsi.fi/en/support/software/vs10xxplugins.html .
10.4
Low Power Mode
IM
If you need to keep the system running while not decoding data, but need to lower the power
consumption, you can use the following tricks.
• Select the 1.0× clock by writing 0x0000 to SCI_CLOCKF. This disables the PLL and saves
some power.
• Write a low non-zero value, such as 0x0010 to SCI_AUDATA. This will reduce the samplerate and the number of audio interrupts required. Between audio interrupts the VSDSP
core will just wait for an interrupt, thus saving power.
EL
• Turn off all audio post-processing (tone controls, EarSpeaker and other post-processing
options).
• If possible for the application, write 0xffff to SCI_VOL to disable the analog drivers.
To return from low-power mode, revert register values in reverse order.
Note: The low power mode consumes significantly more electricity than hardware reset.
Play and Decode
PR
10.5
This is the normal operation mode of VS1063a. SDI data is decoded. Decoded samples are
converted to analog domain by the internal DAC. If no decodable data is found, SCI_HDAT0
and SCI_HDAT1 are set to 0.
When there is no input for decoding, VS1063a goes into idle mode (lower power consumption
than during decoding) and actively monitors the serial data input for valid data.
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10.5.1
Playing a Whole File
This is the default playback mode.
10
OPERATION
IN
AR
Y
VS1063a Datasheet
1. Send an audio file to VS1063a.
2. Read extra parameter value endFillByte (Chapter 10.11).
3. Send at least 2052 bytes of endFillByte[7:0]. For FLAC you should send 12288 endFillBytes when ending a file.
4. Set SCI_MODE bit SM_CANCEL.
5. Send at least 32 bytes of endFillByte[7:0].
6. Read SCI_MODE. If SM_CANCEL is still set, go to 5. If SM_CANCEL hasn’t cleared
after sending 2048 bytes, do a software reset (this should be extremely rare).
7. The song has now been successfully sent. HDAT0 and HDAT1 should now both contain
0 to indicate that no format is being decoded. Return to 1.
10.5.2
Cancelling Playback
IM
Cancelling playback of a song is a normal operation when the user wants to jump to another
song while doing playback.
10.5.3
EL
1. Send a portion of an audio file to VS1063a.
2. Set SCI_MODE bit SM_CANCEL.
3. Continue sending audio file, but check SM_CANCEL after every 32 bytes of data. If it
is still set, goto 3. If SM_CANCEL doesn’t clear after 2048 bytes or one second, do a
software reset (this should be extremely rare).
4. When SM_CANCEL has cleared, read extra parameter value endFillByte (Chapter 10.11).
5. Send 2052 bytes of endFillByte[7:0]. For FLAC you should send 12288 endFillBytes.
6. HDAT0 and HDAT1 should now both contain 0 to indicate that no format is being decoded.
You can now send the next audio file.
Fast Play
VS1063a allows fast audio playback. If your microcontroller can feed data fast enough to the
VS1063a, this is the preferred way to fast forward audio.
Start sending an audio file to VS1063a.
To set fast play, set extra parameter value playSpeed (Chapter 10.11).
Continue sending audio file.
To exit fast play mode, write 1 to playSpeed.
PR
1.
2.
3.
4.
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10
OPERATION
IN
AR
Y
VS1063a Datasheet
To estimate whether or not your microcontroller can feed enough data to VS1063a in fast play
mode, see contents of extra parameter value bitRatePer100 (Chapter 10.11). Note that bitRatePer100 contains the data speed of the file played back at nominal speed even when fast play is
active.
Note: Play speed is not reset when song is changed.
10.5.4
Fast Forward and Rewind without Audio
To do fast forward and rewind you need the capability to do random access to the audio file.
Unfortunately fast forward and rewind isn’t available at all times, like when file headers are
being read.
IM
1. Send a portion of an audio file to VS1063a.
2. When random access is required, read SCI_STATUS bit SS_DO_NOT_JUMP. If that bit
is set, random access cannot be performed, so go back to 1.
3. Read extra parameter value endFillByte (Chapter 10.11).
4. Send at least 2048 bytes of endFillByte[7:0].
5. Jump forwards or backwards in the file.
6. Continue sending the file.
Note: It is recommended that playback volume is decreased by e.g. 10 dB when fast forwarding/rewinding.
Note: Register DECODE_TIME does not take jumps into account.
Maintaining Correct Decode Time
EL
10.5.5
When fast forward and rewind operations are performed, there is no way to maintain correct
decode time for most files. However, WMA and Ogg Vorbis files offer exact time information in
the file. To use accurate time information whenever possible, use the following algorithm:
PR
1. Start sending an audio file to VS1063a.
2. Read extra parameter value pair positionMsec (Chapter 10.11).
3. If positionMsec is -1, show you estimation of decoding time using DECODE_TIME (and
your estimate of file position if you have performed fast forward / rewind operations).
4. If positionMsec is not -1, use this time to show the exact position in the file.
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10.6
Feeding PCM Data
10
OPERATION
IN
AR
Y
VS1063a Datasheet
VS1063a can be used as a PCM decoder by sending a WAV file header, followed by PCM
data. If the length sent in the WAV header is 0xFFFFFFFF, VS1063a will stay in PCM mode
indefinitely (or until SM_CANCEL has been set). 8-bit linear and 16-bit linear audio is supported
in mono or stereo. A WAV header looks like this:
File Offset
0
4
8
12
16
20
22
24
28
32
34
52
56
Field Name
ChunkID
ChunkSize
Format
SubChunk1ID
SubChunk1Size
AudioFormat
NumOfChannels
SampleRate
ByteRate
BlockAlign
BitsPerSample
SubChunk2ID
SubChunk2Size
Size
4
4
4
4
4
2
2
4
4
2
2
4
4
Bytes
"RIFF"
0xff 0xff 0xff 0xff
"WAVE"
"fmt "
0x10 0x0 0x0 0x0
0x1 0x0
C0 C1
S0 S1 S2 S3
R0 R1 R2 R3
A0 A1
B0 B1
"data"
0xff 0xff 0xff 0xff
Description
16
Linear PCM
1 for mono, 2 for stereo
0x1f40 for 8 kHz
0x3e80 for 8 kHz 16-bit mono
0x02 0x00 for mono, 0x04 0x00 for stereo 16-bit
0x10 0x00 for 16-bit data
Data size
•
•
•
•
•
IM
The rules to calculate the four variables are as follows:
S = samplerate in Hz, e.g. 44100 for 44.1 kHz.
For 8-bit data B = 8, and for 16-bit data B = 16.
For mono data C = 1, for stereo data C = 2.
A = C×B
8 .
R = S × A.
EL
Note: When playing back PCM, VS1063a ignores R and A. You may set them to anything if
you don’t intend the datastreams to be sent to any other devices.
PR
Example: A 44100 Hz 16-bit stereo PCM header would read as follows:
0000 52 49 46 46 ff ff ff ff 57 41 56 45 66 6d 74 20 |RIFF....WAVEfmt |
0010 10 00 00 00 01 00 02 00 44 ac 00 00 10 b1 02 00 |........D.......|
0020 04 00 10 00 64 61 74 61 ff ff ff ff
|....data....|
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10.7
Audio Encoding
10
OPERATION
IN
AR
Y
VS1063a Datasheet
This chapter explains how to use the encoding and codec modes of VS1063a.
VS1063 has a stereo ADC, thus also two-channel (separate AGC, if AGC enabled) and stereo
(common AGC, if AGC enabled) modes are available. Mono encoding can select either left or
right channel, or a mono down-mix of the left and right channels. The left channel is either MIC
or LINE1 depending on the SCI_MODE register, the right channel is LINE2.
Encoding Control Registers
Register
SCI_MODE
SCI_AICTRL0
SCI_AICTRL1
SCI_AICTRL2
SCI_AICTRL3
SCI_WRAMADDR
Bits
2, 12, 14
15:0
15:0
15:0
2:0
3
7:4
8:9
10
11
12
13
14
15
15. . . 0
Description
Start ENCODE mode, select MIC/LINE1
Samplerate 8000. . . 48000 Hz (read at encoding startup)
Encoding gain (1024 = 1×) or 0 for automatic gain control
Maximum autogain amplification (1024 = 1×, 65535 = 64×)
ADC mode 0. . . 4
Reserved, set to 0
Encoding format 0. . . 6
reserved, set to 0
No RIFF WAV header inserted (or expected in codec mode)
Pause enable
reserved, set to 0
UART TX enable
AEC enable
codec mode (both encode and decode)
Quality / bitrate selection for Ogg Vorbis and MP3
IM
10.7.1
EL
If you use the VS1063a Patches package, activate encoding mode by first setting the bit
SM_ENCODE in register SCI_MODE, then writing 0x50 to SCI_AIADDR. Otherwise, activate
encoding by setting bits SM_RESET and SM_ENCODE in SCI_MODE.
Line input 1 is used instead of differential mic input if SM_LINE1 is set. Before activating encoding, user must write the right values to SCI_AICTRL0, SCI_AICTRL3, and SCI_WRAMADDR.
These values are only read at encoding startup. SCI_AICTRL1 and SCI_AICTRL2 can be
altered anytime, but it is preferable to write good init values before activation.
PR
RL1
SCI_AICTRL1 controls linear encoding gain. The gain is AICT
, so 1024 is equal to digital
1024
gain 1.0, 2000 is 1.95, 512 is 0.5 and so on. If the user wants to use automatic gain control
(AGC), SCI_AICTRL1 should be set to 0. Typical speech applications usually are better off
using AGC, as this takes care of relatively uniform speech loudness in encodings.
SCI_AICTRL2 controls the maximum AGC gain. This can be used to limit the amplification of
noise when there is no signal. If SCI_AICTRL2 is zero, the maximum gain is initialized to 65535
(64×), i.e. whole range is used.
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OPERATION
IN
AR
Y
VS1063a Datasheet
SCI_WRAMADDR sets the quality / bit rate selection for Ogg Vorbis and MP3 encoding. For
WAV formats this setting is not used. Use value 0xe080 for constant bitrate of 128 kbps. Note
that WRAMADDR is read at encoder startup, so modifying it later does not change the settings.
Bits
Description
15:14 Bitrate mode, 0 = Quality Mode, 1 = VBR, 2 = ABR, 3 = CBR
13:12 Bitrate multiplier, 0 = 10, 1 = 100, 2 = 1000, 3 = 10000
11
Encoder-specific, Ogg Vorbis: 1=use parametric_x.i.encoding.serialNumber
10
Encoder-specific, Ogg Vorbis: 1=limited frame length
mp3: 1 = do not use bit-reservoir
9
Used internally, set to 0.
8:0
Bitrate base 0 to 511 (or quality 0 to 9 if Quality Mode selected).
The bitrate base and bitrate multipler define a target bitrate value. For example 2 in
multiplier and 128 in base means 128 kbit/s. The bitrate mode selects how the bitrate and
bitrate multiplier fields are interpreted. In variable bitrate (VBR) mode the bitrate and
bitrate multiplier fields sets a very relaxed average bitrate. Currently the average bitrate mode
(ABR) equals VBR mode in both encoders. In Quality Mode bitrate multiplier is ignored
and the bitrate base field value sets encoding quality from 0 to 9.
SCI_WRAMADDR bit 10 is encoder-specific. When set with the MP3 encoder, the bit reservoir
will not be used. When set with Ogg Vorbis encoder, the bit requests a smaller output delay.
IM
SCI_WRAMADDR bit 11 is encoder-specific. When set with Ogg Vorbis encoder, the stream
serial number is fetched from parametric_x.i.encoding.serialNumber.
SCI_AICTRL3 bits 0 to 2 select the ADC mode and implicitly the number of channels. 0 = joint
stereo (common AGC), 1 = dual channel (separate AGC), 2 = left channel, 3 = right channel,
4= mono downmix.
SCI_AICTRL3 bits 4 to 7 select the encoding format. 0 = IMA ADPCM, 1 = PCM , 2 = G.711
µ-law, 3 = G.711 A-law, 4 = G.722 ADPCM, 5 = Ogg Vorbis, 6 = MP3.
EL
If SCI_AICTRL3 bit 15 is set at startup, codec mode is initialized. If MP3 and Ogg Vorbis formats
are specified, the configuration bit is ignored and codec mode is not available. In codec mode
the encoded data is provided through HDAT0 and HDAT1, and data to be decoded is expected
through the serial data interface (SDI).
If SCI_AICTRL3 bit 13 is set at encode/codec startup, UART transmission of data is initialized
with parameters taken from parametric_x. If you want to use UART transmission, you must
first write the tx configuration values, then set the AICTRL3 UART TX enable bit, and only after
that start the encoding/codec mode using SCI_MODE register.
PR
UART is configured from parametric_x.i.encoding, that part of of the parametric structure is
no longer cleared at software reset.
txUartDiv = UART divider or 0 to use bytespeed
txUartByteSpeed = UART bytespeed
txPauseGpio = GPIO mask for transmit flow control
parametric_x.i.encoding.channelMax contains the maximum absolute value encountered in
the corresponding channel since the last clear of the variable. In mono modes only channelMax[0]
is updated.
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10.7.2
The Encoding Procedure
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The encoding procedure from start to finish goes as follows:
1. Pre-initialization; Setup system:
• Load the VS1063a Patches package, available at
http://www.vlsi.fi/en/support/software/vs10xxplugins.html . Note that the package is
required for conforming MP3 bitstreams: without it recording quality will be significantly lower and the bitstream may have errors.
2. Initialization; Set samplerate and parameters:
• SCI_AICTRL0 for samplerate (SCI_WRAMADDR for bitrate/quality setting)
• SCI_AICTRL1 for gain/AGC
• SCI_AICTRL2 for AGC max gain
• SCI_AICTRL3 for channel selection, encoding format and options
• If used, fill in UART configuration.
• If used, fill in Ogg Vorbis serial number.
• SCI_WRAMADDR to set bitrate/quality (mp3 and Ogg Vorbis only)
IM
• Activate encoding with one of the two ways:
– Recommended: If you use the VS1063a Patches package, start encoding as
follows: set bit SM_ENCODE in SCI_MODE, then write 0x50 to AIADDR.
– If you do not use the VS1063a Patches package, start encoding mode by setting
SM_ENCODE and SM_SOFTRESET in register SCI_MODE.
3. Recording:
EL
• Depending on whether you selected SCI or UART data transfers with bit 13 of
SCI_AICTRL3, read data through SCI_HDAT0/SCI_HDAT1 as described in Chapter 10.7.3, or through the UART.
4. Finalizing recording:
• When you want to finish encoding a file, set bit SM_CANCEL in SCI_MODE.
• After a while (typically less than 100 ms), SM_CANCEL will clear.
PR
• If using SCI for data transfers, read all remaining words using SCI_HDAT1/SCI_HDAT0.
Then read parametric_x.endFillByte. If the most significant bit (bit 15) is set to 1, then
the file is of an odd length and bits 7:0 contain the last byte that still should be written
to the output file. Now write 0 to endFillByte.
• When all samples have been transmitted, SM_ENCODE bit of SCI_MODE will be
cleared by VS1063a, and SCI_HDAT1 and SCI_HDAT0 are cleared.
5. Now you can give a software reset to enter player mode or start encoding again.
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Example of Encoding initialization including loading VS1063a Patches:
// First command line loads VS1063a Patches. The patch package can be
// loaded from http://www.vlsi.fi/en/support/software/vs10xxplugins.html
// This package is required for best MP3 quality and correct monitoring.
LoadUserCode(vs1063apatch);
WriteVS10xxRegister(SCI_AICTRL0, 48000U); // 48 kHz
WriteVS10xxRegister(SCI_AICTRL1, 1024U); // Manual gain at 1.0x
WriteVS10xxRegister(SCI_AICTRL3, 0x60);
// Stereo MP3
WriteVS10xxRegister(SCI_MODE, ReadVS10xxRegister(SCI_MODE) |
SM_ENCODE | SM_LINE1);
WriteVS10xxRegister(SCI_WRAMADDR, 0x50); // Activation
The previous code sets 48 kHz stereo MP3 recording with manual gain control set at 1×
(= 0 dB).
Example of initialization without loading VS1063a Patches:
IM
WriteVS10xxRegister(SCI_AICTRL0, 16000U); // 16 kHz
WriteVS10xxRegister(SCI_AICTRL1, 0);
// Manual gain 0 = AGC on
WriteVS10xxRegister(SCI_AICTRL2, 4096U); // AGC max gain 4.0x
WriteVS10xxRegister(SCI_AICTRL3, 2);
// Mono IMA ADPCM
WriteVS10xxRegister(SCI_MODE,
(ReadVS10xxRegister(SCI_MODE) | SM\_RESET | SM_ENCODE) &
~SM_LINE1); // Microphone input, activate
The previous code sets 16 kHz mono IMA ADPCM recording from the left channel using the
microphone amplifier, with automatic gain control and maximum amplification of 4× (= +12 dB).
10.7.3
Reading Encoded Data Through SCI
EL
After encoding mode has been activated, registers SCI_HDAT0 and SCI_HDAT1 have new
functions.
The encoding data buffer is 3712 16-bit words. The fill status of the buffer can be read from
SCI_HDAT1. If SCI_HDAT1 is greater than 0, you can read that many 16-bit words from
SCI_HDAT0. If the data is not read fast enough, the buffer overflows and returns to empty
state.
PR
The encoded data is read from SCI_HDAT0 and written into file as follows. The high 8 bits
of SCI_HDAT0 should be written as the first byte to a file, then the low 8 bits. Note that this
is contrary to the default operation of some 16-bit microcontrollers, and you may have to take
extra care to do this right.
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10.7.4
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File Headers
VS1063 automatically creates a suitable header for the selected encoding mode. If you have
selected MP3 or Ogg Vorbis, the headers will be in those formats, otherwise you get a RIFF
WAV header with the correct samplerate, number of channels, and other information. (If you
have set bit 10 of SCI_AICTRL3, the RIFF WAV header is not generated.) When you finish
encoding you have to fix the RIFF size and data size fields.
The following shows a header for a 8 kHz mono µ-law WAV file. Note that 2- and 4-byte values
are little-endian (least significant byte first).
00000000 52 49 46 46 ff ff ff ff 57 41 56 45 66 6d 74 20 |RIFFT ..WAVEfmt |
00000010 14 00 00 00 07 00 01 00 40 1f 00 00 40 1f 00 00 |........@...@...|
00000020 01 00 08 00 02 00 01 00 64 61 74 61 ff ff ff ff |........data, ..|
IM
EL
File Offset
0
4
8
12
16
20
22
24
28
32
34
36
38
40
44
48
VS1063a RIFF WAV Header
Field Name
Size Bytes
ChunkID
4 "RIFF"
ChunkSize
4 F0 F1 F2 F3
Format
4 "WAVE"
SubChunk1ID
4 "fmt "
SubChunk1Size
4 0x14 0x0 0x0 0x0
AudioFormat
2 0x07 0x0
NumOfChannels
2 0x01 0x00
SampleRate
4 0x40 0x1f 0x00 0x00
ByteRate
4 0x40 0x1f 0x00 0x00
BlockAlign
2 0x01 0x00
BitsPerSample
2 0x08 0x00
Extra size
2 0x02 0x00
Samples per block
2 0x01 0x00
SubChunk3ID
4 "data"
SubChunk3Size
4 D0 D1 D2 D3
Samples. . .
Description
RIFF ident
File size - 8
WAVE ident
fmt ident
20
Audio format
1 for mono, 2 for stereo
0x1f40 = 8000 Hz
Bytes per second
1 byte per block
8 bits / sample
2 extra bytes
1 sample per block
Data ident
Data size (File Size-48)
data
Because VS1063a cannot know in advance how long the recording will be, it will set both RIFF
ChunkSize and Data SubChunk3Size fields F and D to 0xFFFFFFFF. You have to fill in correct
values for F and D after finishing encoding.
PR
Below is an example of a valid header for a 44.1 kHz mono
1798772 (0x1B7274) bytes:
0000 52 49 46 46 6c 72 1b 00 57 41 56 45 66 6d 74 20
0010 14 00 00 00 01 00 01 00 80 bb 00 00 00 77 01 00
0020 02 00 10 00 02 00 01 00 64 61 74 61 44 72 1b 00
Version: 0.42, 2011-11-24
PCM file that has a final length of
|RIFFlr..WAVEfmt |
|.............w..|
|........dataDr..|
59
10.7.5
Playing Encoded Data
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VS1063a Datasheet
In order to play back your encoding, all you need to do is to provide the file through SDI as you
would with any audio file.
10.7.6
Encoder Samplerate Considerations
For encoder samplerates to work accurately, it is recommended to load and run the VS1063a
Patches package. It is is available at http://www.vlsi.fi/en/support/software/vs10xxplugins.html .
When the VS1063a Patches package, v1.2 or higher, is installed, then almost all recording samplerates for almost all encoders can be represented accurately. The only exception is Stereo
Ogg Vorbis recording at over 32 kHz, in which case recording speed may not be accurate.
Below is a encoding samplerate accuracy table for all standard MP3 samplerates, with nominal
crystal speed XTALI = 12.288 MHz.
10.7.7
IM
EL
Requested fs
48000 Hz
44100 Hz
44100 Hz
32000 Hz
24000 Hz
22050 Hz
16000 Hz
12000 Hz
11025 Hz
8000 Hz
Example encoder samplerates, XTALI = 12.288 MHz
Actual fs
Error Note
48000 Hz
0.00 %
44100 Hz
0.00 % All except Ogg Vorbis stereo.
44201 Hz +0.23 % Ogg Vorbis stereo; not recommended for streaming.
32000 Hz
0.00 %
24000 Hz
0.00 %
22050 Hz
0.00 %
16000 Hz
0.00 %
12000 Hz
0.00 %
11025 Hz
0.00 %
8000 Hz
0.00 %
Encode Monitoring Volume
PR
In VS1063a writing to the SCI_VOL register during encoding mode will update monitoring volume.
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Encoder-Specific Considerations
MP3 (format 5)
The MP3 encoder supports all bitrates and samplerates of the MP3 format, both in mono and
stereo. For details of supported and recommended modes, see Chapter 8.2.1. Notice particularly that only the MP3 official samplerates are supported (8000, 11025, 12000, 16000,
22050, 24000, 32000, 44100 and 48000 Hz). If you try to start MP3 encoding with any other
samplerate, the encoder will silently fail.
Quality mode, VBR, CBR are the main modes supported by the encoder. If ABR is selected,
VBR mode is used instead. When Quality mode is selected, 5 is designed to be "near PCM
quality" for the given samplerate.
The so-called MP3 bit reservoir offers a way to more efficiently encode MP3 files. To make
streaming more resilient to tranmission errors, encoder only makes bit reservoir references one
frame back.
Ogg Vorbis (format 6)
IM
For some streaming applications it may be beneficial to turn the bit reservoir off by setting bit
10 of register SCI_WRAMADDR before activating encoding. This will make frames more selfcontained. When using ABR/VBR/Quality encoding, turning bit reservoir off will increase the
bitrate approximately 4. . . 16 kbit/s. Turning bit reservoir off in CBR mode is strongly discouraged as it will have a huge impact in quality and coding efficiency.
EL
The Ogg Vorbis encoder supports a wide range of bitrates and all samplerates at 8. . . 48 kHz,
in mono and stereo. For some examples of supported modes, see Chapter 8.2.2.
Quality mode is the main mode supported by the encoder. If VBR is selected, the value is
internally converted to a quality value between 0. . . 9, and this value is used. If ABR or CBR
is selected, VBR mode is used instead. When Quality mode is selected, 5 is designed to be
"near PCM quality" for the given samplerate.
PR
When silence is detected, the bitstream width may be reduced by upto 90 %. Because the
encoder attempts to make Ogg frames as long as possible (upto 4 KiB), this means that in
such a case the frame delay may grow dramatically, which may cause problems for streaming
systems. To avoid this, the user may set register SCI_WRAMADDR bit 10 before activating
encoding. This will instruct the encoder to create a frame always after at least 1024 but not
more than 2048 samples have been generated in an Ogg frame.
As a default, the Ogg stream serial number is set to 0xfecaadab. If the user wants to set
a different serial number, he should, prior to activating encoding, write the requested serial
number to parametric_x.i.encoding.serialNumber (Chapter 10.11) and set bit 11 of register
SCI_WRAMADDR.
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10.7.9
Encoder/Decoder Delays
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This Chapter presents the absolute minimum estimated encoder/decoder total delays between
two VS1063a ICs. In addition to these numbers come all data transfer times from the transmitting to the receiving unit.
The following symbols are used:
- fs = samplerate
- dm = minimum encoder/decoder delay in milliseconds
Note! Delays have been calculated for standard MP3 samplerates. Other encoders can also
encode non-standard samplerates upto 48 kHz.
PCM/G.711/G.722 / ms
3
3
3
3
3
3
3
3
3
1
IMA / ms
14
15
19
25
26
35
46
49
66
MP3 / ms
36
40
54
48
52
72
96
105
144
IM
fs / Hz
48000
44100
32000
24000
22050
16000
12000
11025
8000
Ogg1 / ms
124
135
185
125
140
190
250
270
200
Numbers apply if “limited frame length” (bit 10 of register SCI_WRAMADDR) is set. If the bit
is not set, encoder/decoder delay can be upto several seconds. See Chapter 10.7.1, Encoding
Control Registers, for details on how to set the “limited frame length” bit.
Codec Mode
EL
10.8
In the codec mode the analog to digital and digital to analog paths are separate and you can
encode and decode at the same time.
However, there are some restrictions in codec mode. The samplerate should be a XTALI/256,
XTALI/512, XTALI/1024 or XTALI/1536 (with XTALI = 12.288 MHz, possible samplerates are
thus 48000, 24000, 12000 or 8000 Hz). Also, MP3 and Ogg Vorbis formats are not available.
PR
A RIFF WAV header is automatically generated in the encoded data, which is transferred
through SCI_HDAT1 and SCI_HDAT0 like in the normal encoding mode.
The data to be decoded is sent to SDI. The format, number of channels and samplerate are
determined from a RIFF WAV header. If you have set bit 10 of SCI_AICTRL3, the RIFF WAV
header is not expected and the format, number of channels and rate are set to the ones used
in encoding.
Note: the RIFF WAV parser used in the codec mode decoder is a simplified one.
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10.9
SPI Boot
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VS1063a Datasheet
If GPIO0 is set with a pull-up resistor to 1 at boot time, VS1063a tries to boot from external SPI
memory.
SPI boot redefines the following pins:
Normal Mode
GPIO0
GPIO1
DREQ
GPIO2
SPI Boot Mode
xCS
CLK
MOSI
MISO
The memory has to be an SPI Bus Serial EEPROM with 16-bit or 24-bit addresses. The serial
speed used by VS1063a is 245 kHz with the nominal 12.288 MHz clock. The first three bytes
in the memory have to be 0x50, 0x26, 0x48.
10.10
IM
The exact record format is explained in the VS1063a Programmer’s Guide.
I2C Boot
VS1063 also supports boot from I2C EEPROM. I2C boot is only tried if GPIO0 is pulled high,
but the required boot ident is not found from SPI EEPROM. When GPIO0 is low, boot is not
tried and normal decoding mode is entered.
EL
I2C boot redefines the following pins:
Normal Mode
GPIO0
GPIO4
GPIO6
SPI Boot Mode
high = enable SPI/I2C boot
SDA
SCL
Both SDA and SCL has to have an external pull-up.
PR
The memory has to be an I2C EEPROM with 8-bit or 16-bit address. The serial speed used by
VS1063a is <100 kHz with the nominal 12.288 MHz clock. The boot record format is the same
as for SPI boot.
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Extra Parameters (Parametric Structure)
The following parametric structure is in X memory at address 0x1e00 and can be used to set
extra parameters or get useful information. SCI_WRAMADDR addresses 0xc0c0 to 0xc0ff are
translated automatically to parametric structure addresses 0x1e00. . . 0x1e3f. Also, when an
address from 0xc0c0 to 0xc0ff is written, sdiFree and audioFill are updated.
PR
EL
IM
#define PARAMETRIC_VERSION 0x0004
struct parametric {
/* configs are not cleared between files */
u_int32 chipID;
/*0x1e00/01 Initialized at reset for your convenience*/
u_int16 version;
/*0x1e02 - structure version */
u_int16 config1;
/*0x1e03 wamf ---C ppss RRRR */
s_int16 playSpeed;
/*0x1e04 0,1 = normal speed, 2 = twice, etc. */
u_int16 bitRatePer100; /*0x1e05 average bitrate divided by 100 */
u_int16 endFillByte;
/*0x1e06 which byte value to send after file */
s_int32 rateTune;
/*0x1e07..8 samplerate tune in +-1ppm steps. V4*/
u_int16 playMode;
/*0x1e09 play and processing enables V4 */
s_int32 sampleCounter; /*0x1e0a..b sample counter. V4*/
u_int16 vuMeter;
/*0x1e0c VU meter result V4*/
u_int16 adMixerGain;
/*0x1e0d AD mixer attenuation in 3dB steps -3..-31*/
u_int16 adMixerConfig; /*0x1e0e AD mixer config, bits 5-4=rate, 7-6=mode */
u_int16 pcmMixerRate; /*0x1e0f PCM mixer samplerate (read when enabled)*/
u_int16 pcmMixerFree; /*0x1e10 PCM mixer FIFO free state */
u_int16 pcmMixerVol;
/*0x1e11 PCM mixer volume 0..191 (-0.5dB steps) */
u_int16 eq5Params[10]; /*0x1e12..0x1e1b 5-channel EQ parameters */
u_int16 eq5Updated;
/*0x1e1c write as non-zero to recalculate filters.*/
u_int16 speedShifter; /*0x1e1d Speed shifter speed 0x4000 == 1.0x V4 */
u_int16 earSpeakerLevel; /*0x1e1e EarSpeaker level, 0 = off. V4*/
u_int16 sdiFree;
/*0x1e1f SDI FIFO free in words. V4*/
u_int16 audioFill;
/*0x1e20 Audio buffer fill in stereo samples. V4*/
u_int16 reserved[4];
/*0x1e21..24 */
u_int32 latestSOF;
/*0x1e25/1e26 latest start of frame V4 */
u_int32 positionMsec; /*0x1e27-28 play position if known. V3*/
s_int16 resync;
/*0x1e29 > 0 for automatic m4a, ADIF, WMA resyncs*/
/* 42 words */
union {
/* 22 available -- these are not cleared at software reset! */
u_int16 generic[22]; /*1e2a*/
struct {
s_int16 txUartDiv;
/*1e2a direct set of UART divider*/
s_int16 txUartByteSpeed;
/*1e2b set UART byte speed (txUartDiv=0)*/
u_int16 txPauseGpio;
/*1e2c mask: a high level pauses tx*/
s_int16 aecAdaptMultiplier; /* 2 for default */
s_int16 reserved[14];
u_int16 channelMax[2]; /*1e3c,1e3d for record level monitoring*/
u_int32 serialNumber; /*1e3e,1e3f for Ogg Vorbis if enabled in WRAMADDR(11)*/
} encoding;
struct {
u_int32 curPacketSize;
u_int32 packetSize;
} wma; /* 4*/
struct {
u_int16 sceFoundMask; /*1e2a single-channel-el. found since last clr*/
u_int16 cpeFoundMask; /*1e2b channel-pair-el. found since last clr*/
u_int16 lfeFoundMask; /*1e2c low-frequency-el. found since last clr*/
u_int16 playSelect;
/*1e2d 0 = first any, initialized at aac init */
s_int16 dynCompress; /*1e2e -8192=1.0, initialized at aac init */
s_int16 dynBoost;
/*1e2f 8192=1.0, initialized at aac init */
/* playSelect: 0 = first sce or cpe or lfe
xxxx0001 first sce
xxxx0010 first cpe
xxxx0011 first lfe
eeee0101 sce eeee
eeee0110 cpe eeee
eeee0111 lfe eeee */
u_int16 sbrAndPsStatus; /*0x1e30 V3 gotSBR/upsampling/gotPS/PSactive*/
u_int16 sbrPsFlags;
/*0x1e31 V4*/
} aac; /* 3*/
struct {
s_int16 gain; /* 0x1e2a proposed gain offset, default = -12 */
} vorbis;
} i;
};
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10.11.1
chipID, version, config1
Parameter
chipID
version
config1
Address
0x1e00-01
0x1e02
0x1e03
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VS1063a Datasheet
Usage
Fuse-programmed unique ID (cosmetic copy of the fuses)
Structure version – 0x0004
Miscellaneous configuration
The fuse-programmed ID is read at startup and copied into the chipID field. If not available,
the value will be all zeros.
The version field can be used to determine the layout of the rest of the structure. The version
number is changed when the structure is changed. For VS1063a the structure version is 4.
config1 sets miscellanous settings. Bits 12 to 15 can be used by the user to easily disable
certain decoders. Disabling FLAC may be useful in standalone applications to increase the
data memory available for the application.
config1
IM
Usage
1 = Disable WMA decoding
1 = Disable AAC decoding
1 = Disable MP3 decoding
1 = Disable FLAC decoding
Reserved, set to 0
1 = Disable CRC checking for MP3
AAC PS configuration
AAC SBR configuration
not used in VS1063a
PR
EL
bits
15
14
13
12
11:9
8
7:6
5:4
3:0
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10.11.2
Player Configurations
Parameter
playSpeed
bitRatePer100
endFillByte
rateTune
playMode
sampleCounter
sdiFree
audioFill
latestSOF
positionMsec
resync
Address
0x1e04
0x1e05
0x1e06
0x1e07:1e08
0x1e09
0x1e0a:1e0b
0x1e1f
0x1e20
0x1e25:1e26
0x1e27:1e28
0x1e29
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Usage
0,1 = normal speed, 2 = double, 3 = three times etc.
average bitrate divided by 100
byte to send after file
samplerate finetune in +-1ppm steps
mono, pause, and extra audio processing selects
sample counter
SDI FIFO free space in words
Audio buffer fill in stereo samples
latest start of frame
File position in milliseconds, if available
Automatic resync selector
playSpeed makes it possible to fast forward songs. Decoding of the bitstream is performed,
but only each playSpeed frames are played. For example by writing 4 to playSpeed will play
the song four times as fast as normal, if you are able to feed the data with that speed. Write 0
or 1 to return to normal speed. SCI_DECODE_TIME will also count faster. All current codecs
support the playSpeed configuration.
IM
bitRatePer100 contains the average bitrate divided by 100. The value is updated once per
second and it can be used to calculate an estimate of the remaining playtime. This value is
also available in SCI_HDAT0 for all codecs except MP3, MP2, and MP1.
endFillByte indicates what byte value to send after file is sent before SM_CANCEL.
EL
rateTune finetunes the samplerate in 1 ppm steps. This is useful in streaming applications
where long-term buffer fullness is used to adjust the samplerate very accurately. Zero is normal
speed, positive values speed up, negative values slow down. To calculate rateTune for a speed,
use (x − 1.0) ∗ 1000000. For example 5.95% speedup (1.0595 − 1.0) ∗ 1000000 = 59500.
playMode provides mono and pause select bits. It also contains some extra processing block
enables. Setting the pause bit will immediately stop audio sample output. Samples already in
the audio buffer will be played, but stream buffer is not read until pause bit is cleared. The mono
select averages left and right channel so LEFT and RIGHT outputs will be the same. Other bits
are explained separately.
config1
Name
PLAYMODE_SPEEDSHIFTER_ON
PLAYMODE_EQ5_ON
PLAYMODE_PCMMIXER_ON
PLAYMODE_ADMIXER_ON
PLAYMODE_VUMETER_ON
PLAYMODE_PAUSE_ON
PLAYMODE_MONO_OUTPUT
PR
bits
6
5
4
3
2
1
0
Version: 0.42, 2011-11-24
Usage
Speedshifter enable
EQ5 enable
PCM Mixer enable
AD Mixer enable
VU Meter enable
Pause enable
Mono output select
66
10
OPERATION
IN
AR
Y
VS1063a Datasheet
sampleCounter advances for each played sample and is initialized by Ogg Vorbis decoding.
sdiFree and audioFill can be used to monitor and control the playback delay in special applications. sdiFree and audioFill are updated when WRAMADDR is written with values from
0xc0c0 to 0xc0ff. These translate to parametric stucture addresses 0x1e00. . . 0x1e3f automatically. So, write 0xc0df to WRAMADDR, and then read WRAM twice to get both sdiFree and
audioFill.
latestSOF returns the position of the current (AAC) or next (WMA) beginning of a frame. You
can use this information to implement glitch-free A-B loop or rewind.
positionMsec is a field that gives the current play position in a file in milliseconds, regardless
of rewind and fast forward operations. The value is only available in codecs that can determine
the play position from the stream itself. Currently WMA and Ogg Vorbis provide this information.
If the position is unknown, this field contains -1.
resync field is used to force a resynchronization to the stream for WMA and AAC (ADIF, .mp4
/ .m4a) instead of ending the decode at first error. This field can be used to implement almost
perfect fast forward and rewind for WMA and AAC (ADIF, .mp4 / .m4a). The user should set this
field before performing data seeks if they are not in packet or data block boundaries. The field
value tells how many tries are allowed before giving up. The value 32767 gives infinite tries.
IM
The resync field is set to 32767 after a reset to make resynchronization the default action, but
it can be cleared after reset to restore the old action. When resync is set, every file decode
should always end as described in Chapter 10.5.1.
When resync is required, WMA and AAC codecs now enter broadcast/stream mode where file
size information is ignored. Also, the file size and data size information of WAV files are ignored
when resync is non-zero. The user must use SM_CANCEL or software reset to end decoding.
EL
Note: WAV, WMA, ADIF, and .mp4 / .m4a files begin with a metadata or header section, which
must be fully processed before any fast forward or rewind operation. SS_DO_NOT_JUMP
(in SCI_STATUS) is clear when the header information has been processed and jumps are
allowed.
CFG1_NOWMA
(1<<15)
CFG1_NOAAC
(1<<14)
CFG1_NOMP3
(1<<13)
CFG1_NOFLAC
(1<<12)
CFG1_PSNORMAL
(0<<6)
CFG1_PSDOWNSAMPLED (1<<6)
CFG1_PSOFF
(3<<6)
CFG1_SBRNORMAL
(0<<4)
CFG1_SBRNOIMPLICIT (1<<4)
CFG1_SBRDOWNSAMPLED (2<<4)
CFG1_SBROFF
(3<<4)
CFG1_MP3_NOCRC
(1<<8)
CFG1_REVERB
(1<<0)
#define
#define
#define
#define
AAC_SBR_PRESENT 1
AAC_UPSAMPLE_ACTIVE 2
AAC_PS_PRESENT 4
AAC_PS_ACTIVE 8
PR
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
Version: 0.42, 2011-11-24
/* To allow more memory for the user */
/* PS in downsampled mode */
/* no PS */
/*
/*
/*
/*
/*
default! */
never upsample */
no SBR or PS */
turn off CRC checking*/
for MIDI (n/a VS1063) */
67
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Notice that reading two-word variables through the SCI_WRAMADDR and SCI_WRAM interface is only partly atomic. In VS1063 a write to SCI_WRAMADDR reads ahead two words that
it provides to SCI_WRAM, so the two halfs of a long variable are sampled together. But as the
write to the variable may not be protected from interrupts, the SCI interrupt may occur between
the update of the low and high parts of the variable.
It is quite improbable though. If you want to make certain the value is correct, read it twice and
compare the results.
10.11.3
VU Meter
Parameter
playMode
vuMeter
Address
0x1e09
0x1e0c
Usage
bit 2: VU meter enable
VU meter result (if VU meter enabled)
VU Meter takes the absolute maximum of the output samples and reports it in 3dB steps from
0 to 32, separately for left and right channel. Bits 15. . . 8 of parametric_x.vuMeter contain the
left channel result, bits 7. . . 0 contain the right channel result.
PR
EL
IM
VU Meter uses about 0.2MHz of processing power at 48 kHz samplerate.
Version: 0.42, 2011-11-24
68
10.11.4
AD Mixer
Parameter
playMode
adMixerGain
adMixerConfig
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
Address
0x1e09
0x1e0d
0x1e0e
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
bit 3: AD Mixer enable
AD mixer attenuation in 3dB steps -3. . . -31
AD mixer config
ADMIXER_RATEMASK
ADMIXER_RATE192
ADMIXER_RATE96
ADMIXER_RATE48
ADMIXER_RATE24
ADMIXER_MODEMASK
ADMIXER_MODESTEREO
ADMIXER_MODEMONO
ADMIXER_MODELEFT
ADMIXER_MODERIGHT
(3<<0)
(0<<0)
(1<<0)
(2<<0)
(3<<0)
(3<<2)
(0<<2)
(1<<2)
(2<<2)
(3<<2)
/*
/*
/*
/*
5MHz
*/
2.5MHz */
1.25MHz*/
0.6MHz */
AD Mixer allows to mix MIC or LINE inputs with any decoded audio format. Four modes are
provided: stereo, mono down-mix of left and right channels, left channel, right channel.
IM
The mix gain can be set in 3 dB steps using adMixerGain. The mixing samplerate can be
24 kHz, 48 kHz, 96 kHz, or 192 kHz. The higher the rate, the better the quality, but also the
more processing power is required.
In practise 48 kHz is good enough quality for all applications (takes 1.25 MHz), using 96 kHz
and 192 kHz are only recommended if you use I2S with those rates.
EL
The AD Mixer configuration adMixerConfig must be set before AD Mixer enable bit is set in
playMode. The gain control can be adjusted at any time.
PR
AD Mixer and PCM Mixer can not be on simultaneously. AD Mixer overrides PCM Mixer.
Version: 0.42, 2011-11-24
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10.11.5
PCM Mixer
Parameter
playMode
pcmMixerRate
pcmMixerFree
pcmMixerVol
Address
0x1e09
0x1e0f
0x1e10
0x1e11
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
bit 4: PCM Mixer enable
PCM mixer samplerate
PCM mixer FIFO free state
PCM mixer volume 0. . . 191 (-0.5 dB steps)
The PCM Mixer allows a mono 16-bit linear PCM stream be played back during any audio
format playback. Because the SDM audio side path does not have any interpolation, the PCM
audio is automatically upsampled to at least 22000 Hz to keep good audio quality.
The PCM samplerate is configured from pcmMixerRate, and it must be written before PCM
Mixer is enabled from the playMode variable. With the nominal 12.288 MHz clock the samplerates 8000 Hz, 12000 Hz, 16000 Hz, 24000 Hz, 32000 Hz, 48000 Hz are exact. You can use
other rates as well, but they are not exact (for example 11025 Hz, 22050 Hz and 44100 Hz play
0.23% too fast).
The PCM data is to be written to SCI_AICTRL0 register, and pcmMixerFree tells how much
space is in the PCM FIFO (you can send upto this many words). Note that SCI multiple write
can be used to write multiple words with minimal overhead.
IM
pcmMixerVol controls volume independently of the normal playback volume. Values from 0
to 182 control PCM volume in 0.5dB steps. Note: to prevent sigma-delta modulator overflow,
SCI_VOL should be at least 2dB (0x0404), and the sum of SCI_VOL and pcmMixerVol attenuations at least 6dB (12). If you have not set large enough attenuations, the PCM Mixer adjusts
the registers automatically to have at least these values. To have absolutely safe scaling, have
6dB (0x0c0c) or more in both SCI_VOL and pcmMixerVol.
EL
The processing power needed depends on the samplerate, e.g. 8 kHz = 4.0MHz, 16 kHz =
6.8MHz, 24 kHz = 4.9MHz, 32 kHz = 6.5MHz.
Processing will be automatically disabled after a 0.125-second timeout when samples are not
being written to SCI_AICTRL0. The processing is resumed when there are at least 128 samples
in the PCM FIFO (1/4 full).
AD Mixer and PCM Mixer can not be on simultaneously. AD Mixer overrides PCM Mixer.
PR
s_int16 samples[32];
s_int16 availSpace;
Mp3WriteReg(SCI_WRAMADDR, 0x1e10);
availSpace = Mp3ReadReg(SCI-WRAM);
if (availSpace >= 32) {
ReadSamples(samples, 32);
Mp3WriteRegMultiple(SCI_AICTRL0, samples, 32);
}
Version: 0.42, 2011-11-24
70
10.11.6
EQ5 5-band Equalizer
Parameter
playMode
eq5Params
eq5Update
Address
0x1e09
0x1e12/1b
0x1e1c
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
bit 5: EQ5 enable
Frequency/gain pairs
Indicator that settings have been changed
The 5-band equalizer takes its parameters from eq5Params array, which needs to be written
before the EQ5 is enabled from bit 5 of playMode. If the settings are changed while EQ5 is
active, new settings can be forced to be taken into use by writing a non-zero value to eq5Update.
Currently EQ5 and Bass/Treble control can not be active at the same time. Bass and treble
controls override EQ5.
High
0
32
150
32
1000
32
15000
32
15000
32
Usage
Not used
Bass level in dB
Bass/Mid-Bass cutoff in Hz
Mid-Bass level in dB
Mid-Bass/Mid cutoff in Hz
Mid level in dB
Mid/Mid-High cutoff in Hz
Mid-High level in dB
Mid-High/Treble cutoff in Hz
Treble level in dB
IM
eq5Params are as follows:
Parameter Address Low
eq5Dummy 0x1e12
0
eq5Level1
0x1e13
-32
eq5Freq1
0x1e14
20
eq5Level2
0x1e15
-32
eq5Freq2
0x1e16
50
eq5Level3
0x1e17
-32
eq5Freq3
0x1e18
1000
eq5Level4
0x1e19
-32
eq5Freq4
0x1e1a
2000
eq5Level5
0x1e1b
-32
EL
Freq values must be strictly ascending: e.g. eq5Freq2 must be higher than eq5Freq1, so e.g.
combination 80, 50 is not allowed.
PR
Example: Vector 0, 12, 70, 6, 300, -3, 3000, 2, 8000, 6 emphasizes bass and treble a lot.
Version: 0.42, 2011-11-24
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10.11.7
Speed Shifter
Parameter
playMode
speedShifter
Address
0x1e09
0x1e1d
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
bit 6: SpeedShifter enable
Speed shifter speed, 0x4000 = 1.0x
Speed shifter allows the playback tempo to be changed without changing the playback pitch.
ter
The playback tempo is speedShif
, i.e. 16384 is the normal speed. The minimum speed is
16384
0.68x (11141) and maximum speed 1.64x (26869).
If you want to change pitch without changing tempo, adjust the speed and compensate by also
adjusting the samplerate. For example two semitones is 2−2/12 = 0.8909, so set the speed
shifter to 2−2/12 ∗ 16384 = 14596 and set rateTune to (22/12 − 1) ∗ 1000000 = 122462.
Speed shifter and EarSpeaker can not be used at the same time. Speed shifter overrides
EarSpeaker.
EarSpeaker
Parameter
earSpeakerLevel
Address
0x1e1e
Usage
EarSpeaker level, 0 = off
IM
10.11.8
EarSpeaker processing can be adjusted using earSpeakerLevel. Different levels simulate a
little different type of acoustical situation, suiting different personal preferences and types of
recording.
EL
• 0: Best option when listening through loudspeakers or if the audio to be played contains
binaural preprocessing.
• 12000: Suited for listening to normal musical scores with headphones, very subtle.
• 38000: Suited for listening to normal musical scores with headphones, moves sound
source further away than minimal.
• 50000: Suited for old or ’dry’ recordings, or if the audio to be played is artificial.
PR
EarSpeaker takes approximately 11 MIPS at 48 kHz samplerate.
Speed shifter and EarSpeaker can not be used at the same time. Speed shifter overrides
EarSpeaker.
Version: 0.42, 2011-11-24
72
10.11.9
Other Parameters
WMA
Parameter
curPacketSize
packetSize
Address
0x1e2a/2b
0x1e2c/2d
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
The size of the packet being processed
The packet size in ASF header
The ASF header packet size is available in packetSize. With this information and a packet
start offset from latestSOF you can parse the packet headers and skip packets in ASF files.
WMA decoder can also increase the internal clock automatically when it detects that a file can
not be decoded correctly with the current clock. The maximum allowed clock is configured with
the SCI_CLOCKF register.
AAC
Usage
SBR and PS select
Single channel elements found
Channel pair elements found
Low frequency elements found
Play element selection
Compress coefficient for DRC, -8192=1.0
Boost coefficient for DRC, 8192=1.0
SBR and PS available flags
SBR and PS mode
IM
Address
0x1e03(7:4)
0x1e2a
0x1e2b
0x1e2c
0x1e2d
0x1e2e
0x1e2f
0x1e30
0x1e31
EL
Parameter
config1
sceFoundMask
cpeFoundMask
lfeFoundMask
playSelect
dynCompress
dynBoost
sbrAndPsStatus
sbrAndPsFlags
playSelect determines which element to decode if a stream has multiple elements. The value
is set to 0 each time AAC decoding starts, which causes the first element that appears in the
stream to be selected for decoding. Other values are: 0x01 - select first single channel element
(SCE), 0x02 - select first channel pair element (CPE), 0x03 - select first low frequency element
(LFE), S ∗ 16 + 5 - select SCE number S, P ∗ 16 + 6 - select CPE number P, L ∗ 16 + 7 select LFE number L. When automatic selection has been performed, playSelect reflects the
selected element.
PR
sceFoundMask, cpeFoundMask, and lfeFoundMask indicate which elements have been found in
an AAC stream since the variables have last been cleared. The values can be used to present
an element selection menu with only the available elements.
dynCompress and dynBoost change the behavior of the dynamic range control (DRC) that is
present in some AAC streams. These are also initialized when AAC decoding starts.
sbrAndPsStatus indicates spectral band replication (SBR) and parametric stereo (PS) status.
Version: 0.42, 2011-11-24
73
Bit
0
1
2
3
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
SBR present
upsampling active
PS present
PS active
Bits 7 to 4 in config1 can be used to control the SBR and PS decoding. Bits 5 and 4 select
SBR mode and bits 7 and 6 select PS mode. These configuration bits are useful if your AAC
license does not cover SBR and/or PS.
’10’
’11’
Usage
normal mode, upsample <24 kHz AAC files
do not automatically upsample <24 kHz AAC files, but
enable upsampling if SBR is encountered (default)
never upsample
disable SBR (also disables PS)
config1(7:6)
’00’
’01’
’10’
’11’
Usage
normal mode, process PS if it is available
process PS if it is available, but in downsampled mode
reserved
disable PS processing
IM
config1(5:4)
’00’
’01’
sbrAndPsFlags indicates the current spectral band replication (SBR) and parametric stereo
(PS) mode in the same format as the config1 SBR and PS bits.
EL
AAC decoder can also increase the internal clock automatically when it detects that a file can
not be decoded correctly with the current clock. The maximum allowed clock is configured with
the SCI_CLOCKF register.
PR
If even the highest allowed clock is too slow to decode an AAC file with SBR and PS components, the advanced decoding features are automatically dropped one by one until the file can
be played. First the parametric stereo processing is dropped (the playback becomes mono).
If that is not enough, the spectral band replication is turned into downsampled mode (reduced
bandwidth). As the last resort the spectral band replication is fully disabled. Dropped features
are restored at each song change.
Version: 0.42, 2011-11-24
74
Ogg Vorbis
Parameter
gain
Address
0x1e2a
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Usage
Preferred replay-gain offset
Ogg Vorbis decoding supports Replay Gain technology. The Replay Gain technology is used
to automatically give all songs a matching volume so that the user does not need to adjust
the volume setting between songs. If the Ogg Vorbis decoder finds a Replay Gain tag in the
song header, the tag is parsed and the decoded gain setting can be found from the gain
parameter. For a song without any Replay Gain tag, a default of -6 dB (gain value -12) is
used. For more details about Replay Gain, see http://en.wikipedia.org/wiki/Replay_Gain and
http://www.replaygain.org/.
The player software can use the gain value to adjust the volume level. Negative values mean
that the volume should be decreased, positive values mean that the volume should be increased.
Volume
0 (+0.0 dB)
3 (-1.5 dB)
0 (+0.0 dB)
1 (-0.5 dB)
4 (-2.0 dB)
SCI_VOL (Volume-Gain)
0x0b0b (-5.5 dB)
0x0e0e (-7.0 dB)
0x0000 (+0.0 dB)
0x0000 (+0.0 dB)
0x0202 (-1.0 dB)
PR
EL
Gain
-11 (-5.5 dB)
-11 (-5.5 dB)
+2 (+1.0 dB)
+2 (+1.0 dB)
+2 (+1.0 dB)
IM
For example gain = -11 means that volume should be decreased by 5.5 dB (−11/2 = −5.5),
and left and right attenuation should be increased by 11. When gain = 2 volume should be
increased by 1 dB (2/2 = 1.0), and left and right attenuation should be decreased by 2. Because
volume setting can not go above +0 dB, the value should be saturated.
Version: 0.42, 2011-11-24
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10.12
10
OPERATION
IN
AR
Y
VS1063a Datasheet
SDI Tests
There are several test modes in VS1063a, which allow the user to perform memory tests, SCI
bus tests, and several different sine wave tests.
All tests are started in a similar way: VS1063a is hardware reset, SM_TESTS is set, and then a
test command is sent to the SDI bus. Each test is started by sending a 4-byte special command
sequence, followed by 4 zeros. The sequences are described below.
10.12.1
Sine Test
Sine test is initialized with the 8-byte sequence 0x53 0xEF 0x6E n 0 0 0 0, where n defines the
sine test to use. n is defined as follows:
F s Idx
Fs
F s Idx
Fs
n bits
0
44100 Hz
4
24000 Hz
Name Bits Description
1
48000 Hz
5
16000 Hz
F s Idx
7:5 Samplerate index
2
32000 Hz
6
11025 Hz
S
4:0 Sine skip speed
3
22050 Hz
7
12000 Hz
S
128 .
IM
The frequency of the sine to be output can now be calculated from F = F s ×
Example: Sine test is activated with value 126, which is 0b01111110. Breaking n to its components, Fs Idx = 0b011 = 3 and thus Fs = 22050Hz. S = 0b11110 = 30, and thus the final sine
30
frequency F = 22050Hz × 128
≈ 5168Hz.
To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0.
10.12.2
EL
Note: Sine test signals go through the digital volume control, so it is possible to test channels
separately.
Pin Test
PR
Pin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant
for chip production testing only.
10.12.3
SCI Test
Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n is the
register number to test. The content of the given register is read and copied to SCI_HDAT0. If
the register to be tested is HDAT0, the result is copied to SCI_HDAT1.
Example: if n is 0, contents of SCI register 0 (SCI_MODE) is copied to SCI_HDAT0.
Version: 0.42, 2011-11-24
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10.12.4
Memory Test
10
OPERATION
IN
AR
Y
VS1063a Datasheet
Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After
this sequence, wait for 1100000 clock cycles. The result can be read from the SCI register
SCI_HDAT0, and ’one’ bits are interpreted as follows:
Bit(s)
15
14:10
9
8
7
6
5
4
3
2
1
0
Mask
0x8000
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
0x83ff
Meaning
Test finished
Unused
Mux test succeeded
Good MAC RAM
Good I RAM
Good Y RAM
Good X RAM
Good I ROM 1
Good I ROM 2
Good Y ROM
Good X ROM 1
Good X ROM 2
All ok
10.12.5
IM
Memory tests overwrite the current contents of the RAM memories.
New Sine and Sweep Tests
EL
A more frequency-accurate sine test can be started and controlled from SCI. SCI_AICTRL0 and
SCI_AICTRL1 set the sine frequencies for left and right channel, respectively. These registers,
volume (SCI_VOL), and samplerate (SCI_AUDATA) can be set before or during the test. Write
0x4020 to SCI_AIADDR to start the test.
SCI_AICTRLn can be calculated from the desired frequency and DAC samplerate by:
SCI_AICT RLn = Fsin × 65536/Fs
PR
The maximum value for SCI_AICTRLn is 0x8000U. For the best S/N ratio for the generated
sine, three LSb’s of the SCI_AICTRLn should be zero. The resulting frequencies Fsin can be
calculated from the DAC samplerate Fs and SCI_AICTRL0 / SCI_AICTRL1 using the following
equation.
Fsin = SCI_AICT RLn × F s /65536
Sine sweep test can be started by writing 0x4022 to SCI_AIADDR.
Both these tests use the normal audio path, thus also SCI_BASS, differential output mode, and
EarSpeaker settings have an effect.
Version: 0.42, 2011-11-24
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VS1063a Datasheet
11
VS1063A VERSION CHANGES
IN
AR
Y
11
VS1063a Version Changes
This chapter describes the lastest and most important changes done to VS1063a
11.1
Firmware Changes Between VS1053b and VS1063a, 2011-04-13
VS1063a is a pin-compatible firmware upgrade to the VS1053b.
Completely new or major changes:
• Added MP3, Ogg Vorbis, µ-law, A-law and G.722 encoding.
• Added codec mode.
• Removed MIDI and MPEG layer I (MP1) decoders.
• Layers II and III: new, more robust and accurate decoding. MP3 is now full accuracy
compliant. Use at least 2.5× clock to decode all MP3 bitrates and samplerates.
• CRC checking added for layer III files that contain CRC. CRC checking can be disabled.
IM
• Keeps track of the valid data in bit reservoir, which allows noiseless start of decoding in
the middle of an mp3 file.
• Samplerate finetuning in parametric_x.rateTune.
• Added hooks for detecting and decoding user audio formats.
• WRAMADDR 0xc0c0. . . 0xc0ff is mapped to parametric_x structure.
• Support reading u_int32’s (almost) atomically through WRAM.
• Reading of stream and audio buffer fill states possible.
• Proportional and fixed-width font in data ROM for standalone applications.
EL
• WAV decoding supports 24-bit and 32-bit and floating-point formats.
• RIFF-WAV header is generated automatically in WAV encoding (and codec) modes. The
user needs to fix the RIFF size and data size fields to make them valid WAV files.
• Sample-exact samplerate and volume change.
• Added mono mode and pause mode for player (parametric_x.playMode)
• Added FLAC decoding upto 2 channels.
• Added VU meter.
PR
• Added AD mixer.
• Added PCM mixer.
• Added Speed shifter.
• AAC, WMA, MP3 and FLAC decoding can be individually disabled using bits in parametric_x.config1.
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VS1063a Datasheet
Minor changes and bug fixes:
VS1063A VERSION CHANGES
IN
AR
Y
11
• IROM4 switched off and DO_NOT_JUMP cleared in software reset also.
• Handles SM_CANCEL also for mp3 (clears stream buffer).
• Fixed a problem when the first ’OggS’ in Ogg Vorbis file was spanning the end and beginning of stream buffer.
• AAC feature drop works in non-implicit upsample mode, and was also otherwise improved.
• Default AAC decoding mode is non-implicit upsample, i.e. upsample only when SBR/PS
is detected. This allows to save power with <24kHz files that do not have SBR.
• Ogg Vorbis sets rate only when it changes, allowing the user to override the rate.
• Output volume is now updated in encoding/codec modes.
• Bitrate calculation uses 32-bit second counter.
• Does not clear GPIO_DDR if SPI boot is not tried, so I2S will remain active if you need
to use a soft reset. If boot is tried (GPIO0 is high at startup) but failes, restores old
GPIO_DDR value.
• Subsonic filter always run for ADC inputs.
• EarSpeaker control is now in parametric_x and gives finer control.
• New adcMode 4 gives mono-downmix of left and right channels.
IM
• WMA fix: sflength must be non-zero.
• MP4 fix: first audio block does not need to start the beginning of the mdat atom.
• AAC fix: works now correctly even if PS header is not available at the first SBR block.
• AAC fix: PNS information was overwritten in transition frames.
• 1.65V reference voltage select (SCI_STATUS(0)) and 3 MHz ADC mode (SCI_STATUS(1))
now work.
PR
EL
• Extra parameter byteRate replaced with bitRatePer100. The new field works consistently
with all codecs.
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12
LATEST DOCUMENT VERSION CHANGES
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Latest Document Version Changes
This chapter describes the most important changes to this document.
Version 0.42, 2011-11-24
• Updated Chapter 10.7.6, Samplerate Considerations (page 60), to reflect enhancements
caused by the latest VS1063a Patches v1.2 package.
• Added text to Chapter 1, Disclaimer, to inform that this document is only valid when the
latest VS1063a Patches package has been loaded and activated.
Version 0.41, 2011-09-29
• New VS1063a Patches package is mentioned in Chapters 10.2, Hardware Reset, 10.3,
Software Reset, 10.7.2, Encoding Procedure, and 10.7.8, Encoder-Specific Considerations / MP3.
• Corrected Chapter 10.7.4, File Headers.
IM
• Added byte order information to Chapter 10.7.3, Reading Encoded Data Through SCI.
Version 0.40, 2011-09-02
• xRESET, XTALI and XTALO high-level are referenced from IOVDD in Chapter 4.5, Digital
Characteristics.
EL
• SCI_STATUS default values fixed.
• MP3 license text updated in Chapter 2.
• Added Chapter 10.7.9, Encoder/Decoder Delays.
• Added new Chapter 10.7.6 under Audio Encoding, Sample Rate Considerations.
• Added example samplerates to Chapter 10.8, Codec Mode.
• Other, minor corrections.
PR
Version 0.30, 2011-05-05
• Typo corrections, synced with VS1063a Hardware Guide.
Version 0.21, 2011-04-15
• Minor bug and typo corrections.
Version: 0.42, 2011-11-24
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Version 0.20, 2011-04-14
LATEST DOCUMENT VERSION CHANGES
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• First public release of the complete datasheet.
• Parts of datasheet split into VS1063a Hardware Guide and VS1063a Programmer’s Guide.
These guides will be published in May 2011.
Version 0.10, 2011-01-17
PR
EL
IM
• First two pages released on VLSI’s web pages.
Version: 0.42, 2011-11-24
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13
CONTACT INFORMATION
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Contact Information
VLSI Solution Oy
Entrance G, 2nd floor
Hermiankatu 8
FI-33720 Tampere
FINLAND
PR
EL
IM
Fax: +358-3-3140-8288
Phone: +358-3-3140-8200
Email: sales@vlsi.fi
URL: http://www.vlsi.fi/
Version: 0.42, 2011-11-24
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