SPRS864 - Texas Instruments
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)
1 AM5K2E0x Features and Description
1
1.1
Features
• ARM
®
Cortex
®
-A15 MPCore™ CorePac
– Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz
– 4MB L2 Cache Memory Shared by all Cortex-
A15 Processor Cores
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction and Data Caches per Core
– AMBA 4.0 AXI Coherency Extension (ACE)
Master Port, Connected to MSMC (Multicore
Shared Memory Controller) for Low Latency
Access to SRAM and DDR3
• Multicore Shared Memory Controller (MSMC)
– 2 MB SRAM Memory for ARM CorePac
– Memory Protection Unit for Both SRAM and
DDR3_EMIF
• Multicore Navigator
– 8k Multi-Purpose Hardware Queues with Queue
Manager
– One Packet-Based DMA Engine for Zero-
Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
• Transport Plane IPsec, GTP-U, SCTP,
PDCP
• L2 User Plane PDCP (RoHC, Air Ciphering)
• 1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
– Security Accelerator Engine Enables Support for
• IPSec, SRTP, 3GPP and WiMAX Air
Interface, and SSL/TLS Security
• ECB, CBC, CTR, F8, A5/3, CCM, GCM,
HMAC, CMAC, GMAC, AES, DES, 3DES,
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
Hash), MD5
• Up to 6.4 Gbps IPSec and 3 Gbps Air
Ciphering
– Ethernet Subsystem
• Eight SGMII Ports with Wire Rate Switching
• IEEE1588 v2 (with Annex D/E/F) Support
• 8 Gbps Total Ingress/Egress Ethernet BW from Core
• Audio/Video Bridging (802.1Qav/D6.0)
• QOS Capability
• DSCP Priority Mapping
• Peripherals
– Two PCIe Gen2 Controllers with Support for
• Two Lanes per Controller
• Supports Up to 5 GBaud
– One HyperLink
• Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
• Supports Up to 50 GBaud
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem
• Two SGMII/XFI Ports with Wire Rate
Switching and MACSEC Support
• IEEE1588 v2 (with Annex D/E/F) Support
– One 72-Bit DDR3/DDR3L Interface with Speeds
Up to 1600 MTPS in DDR3 Mode
– EMIF16 Interface
– Two USB 2.0/3.0 Controllers
– USIM Interface
– Two UART Interfaces
– Three I
2
C Interfaces
– 32 GPIO Pins
– Three SPI Interfaces
– One TSIP
• Support 1024 DS0s
• Support 2 Lanes at 32.768/16.3848.192
Mbps Per Lane
• System Resources
– Three On-Chip PLLs
– SmartReflex Automatic Voltage Scaling
– Semaphore Module
– Twelve 64-Bit Timers
– Five Enhanced Direct Memory Access (EDMA)
Modules
• Commercial Case Temperature:
– 0ºC to 85ºC
• Extended Case Temperature:
– -40ºC to 100ºC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
1.2
Applications
• Avionics and Defense
• Communications
• Industrial Automation
• Automation and Process Control
• Servers
• Enterprise Networking
• Cloud Infrastructure
1.3
KeyStone II Architecture
TI's KeyStone II Multicore Architecture provides a unified platform for integrating RISC processing cores along with both hardware/firmware based application-specific acceleration and high performance I/Os. The
KeyStone II Multicore Architecture is a proven device architecture to achieve the full performance entitlement through the following major components: TeraNet, Multicore Shared Memory Controller,
Multicore Navigator, and HyperLink.
TeraNet is a multipoint to multipoint non-blocking switch fabric. Its distributed arbiter provides multiple duplex communication channels in parallel between the master and slave ports without interference. The priority based arbitration mechanism ensures the delivery of the critical traffic delivery in the system.
The Multicore Shared Memory Controller (MSMC) is the center of the KeyStone II memory architecture. It provides multiple fast and high-bandwidth channels for processor cores to access DDR and minimizes the access latency by directly connecting to the DDR. The MSMC also provides the flexibility to expand processor cores with little impact at the device level. In addition, it provides multi-bank based fast on-chip
SRAM shared among processor cores and IOs. It also provides the I/O cache coherency for the device when the Cortex-A15 processor core is integrated.
The Multicore Navigator provides a packet-based IPC mechanism among processing cores and packet based peripherals. The hardware-managed queues supports multiple-in-multiple-out mode without using mutex. Coupled with the packet-based DMA, the Multicore Navigator provides a highly efficient and software-friendly tool to offload the processing core to achieve other critical tasks.
HyperLink provides a 50-GBaud chip-level interconnect that allows devices to work in tandem. Its low latency, low overhead and high throughput makes it an ideal interface for chip-to-chip interconnections.
There are two generations of KeyStone architecture. The AM5K2E0x device is based on KeyStone II, which integrates a Cortex-A15 processor CorePac.
1.4
Device Description
The AM5K2E0x is a high performance device based on TI's KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI's AM5K2E0x device enables a high performance, powerefficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.
TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared
Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3
(72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.
2
AM5K2E0x Features and Description
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The device enables developers to use a variety of development and debugging tools that include GNU
GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
1.5
Enhancements in KeyStone II
The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core cluster to enable Layer 2 (MAC/RLC) and higher layer processing. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC V2 architecture improvements. Multicore Navigator supports 2× the number of queues, descriptors and packet DMA, 4× the number of micro RISC engines and a significant increase in the number of push/pops per second, compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller and Asynchronous EMIF controller for NAND/NOR memory access. The 2-port Gigabit Ethernet switch in KeyStone I has been replaced with an 8-port
Gigabit Ethernet switch and a 10 GbE switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE1588 Annex D/E and
SyncE. The number of GPIOs and serial interface peripherals like I
2
C and SPI have been increased to enable more board level control functionality.
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
1.6
Functional Block Diagram
The figures below show the functional block diagrams of the AM5K2E0x devices.
AM5K2E04
Memory Subsystem
72-Bit
DDR3 EMIF
2MB
MSM
SRAM
MSMC
Debug & Trace
Boot ROM
Semaphore
Secure Mode
Power
Management
PLL
EDMA
3
´
5
´
HyperLink
32KB L1
P-Cache
32KB L1
D-Cache
32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
ARM
A15
4MB L2 Cache
ARM
A15
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
32KB L1
P-Cache
32KB L1
D-Cache
4 ARM Cores @ up to 1.4 GHz
TeraNet
3-Port
Ethernet
Switch www.ti.com
Multicore Navigator
Queue
Manager
Packet
DMA
Network Coprocessor
9-Port
Ethernet
Switch
Security
Accelerator
Packet
Accelerator
Figure 1-1. AM5K2E04 Functional Block Diagram
4
AM5K2E0x Features and Description
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AM5K2E02
Memory Subsystem
72-Bit
DDR3 EMIF
2MB
MSM
SRAM
MSMC
Debug & Trace
Boot ROM
Semaphore
Secure Mode
Power
Management
PLL
3
´
EDMA
5
´
HyperLink
4MB L2 Cache
ARM
A15
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
32KB L1
P-Cache
32KB L1
D-Cache
2 ARM Cores @ up to 1.4 GHz
TeraNet
Multicore Navigator
Queue
Manager
Packet
DMA
Network Coprocessor
9-Port
Ethernet
Switch
Security
Accelerator
Packet
Accelerator
Figure 1-2. AM5K2E02 Functional Block Diagram
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AM5K2E0x Features and Description
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Table of Contents
1 AM5K2E0x Features and Description
...............
1.1
Features
..............................................
1.2
Applications
...........................................
1.3
KeyStone II Architecture
..............................
1.4
Device Description
...................................
1.5
Enhancements in KeyStone II
........................
1.6
Functional Block Diagram
2 Revision History
............................
.........................................
3 Device Characteristics
..................................
3.1
ARM CorePac
........................................
3.2
Development Tools
..................................
3.3
Device Nomenclature
...............................
3.4
Related Documentation from Texas Instruments
...
3.5
Related Links
........................................
3.6
Community Resources
..............................
3.7
Trademarks
..........................................
3.8
Electrostatic Discharge Caution
.....................
3.9
Glossary
.............................................
4 ARM CorePac
4.1
Features
...........................................
.............................................
4.2
System Integration
..................................
4.3
ARM Cortex-A15 Processor
.........................
4.4
CFG Connection
....................................
4.5
Main TeraNet Connection
...........................
4.6
Clocking and Reset
.................................
5 Terminals
................................................
5.1
Package Terminals
..................................
5.2
Pin Map
.............................................
5.3
Terminal Functions
..................................
5.4
Pullup/Pulldown Resistors
..........................
6 Memory, Interrupts, and EDMA for AM5K2E0x
..
6.1
Memory Map SummaryAM5K2E0x
.................
6.2
Memory Protection Unit (MPU) for AM5K2E0x
.....
6.3
Interrupts for AM5K2E0x
............................
6.4
Enhanced Direct Memory Access (EDMA3)
Controller
...........................................
7 System Interconnect
.................................
7.1
Internal Buses and Switch Fabrics
................
7.2
Switch Fabric Connections Matrix - Data Space
..
7.3
Switch Fabric Connections Matrix - Configuration
Space
..............................................
7.4
Bus Priorities
.......................................
8 Device Boot and Configuration
....................
8.1
Device Boot
........................................
8.2
Device Configuration
...............................
9 Device Operating Conditions
.......................
9.1
Absolute Maximum Ratings
........................
9.2
Recommended Operating Conditions
.............
9.3
Electrical Characteristics
...........................
9.4
Power Supply to Peripheral I/O Mapping
..........
10 AM5K2E0x Peripheral Information and Electrical
Specifications
.........................................
10.1
Recommended Clock and Control Signal Transition
Behavior
............................................
10.2
Power Supplies
....................................
10.3
Power Sleep Controller (PSC)
.....................
10.4
Reset Controller
....................................
10.5
Core PLL (Main PLL), DDR3 PLL, NETCP PLL and the PLL Controllers
................................
10.6
DDR3 PLL
..........................................
10.7
NETCP PLL
........................................
10.8
DDR3 Memory Controller
..........................
10.9
I
2
C Peripheral
......................................
10.10
SPI Peripheral
....................................
10.11
HyperLink Peripheral
10.12
UART Peripheral
.............................
.................................
10.13
PCIe Peripheral
...................................
10.14
Packet Accelerator
10.15
Security Accelerator
...............................
..............................
10.16
Network Coprocessor Gigabit Ethernet (GbE)
Switch Subsystem
.................................
10.17
SGMII/XFI Management Data Input/Output
(MDIO)
.............................................
10.18
Ten-Gigabit Ethernet (10GbE) Switch
Subsystem
.........................................
10.19
Timers
.............................................
10.20
General-Purpose Input/Output (GPIO)
10.21
Semaphore2
...........
......................................
10.22
Universal Serial Bus 3.0 (USB 3.0)
...............
10.23
TSIP Peripheral
...................................
10.24
Universal Subscriber Identity Module (USIM)
....
10.25
EMIF16 Peripheral
................................
10.26
Emulation Features and Capability
...............
10.27
Debug Port (EMUx)
...............................
11 Mechanical Data
11.1
Thermal Data
......................................
......................................
11.2
Packaging Information
.............................
6
Table of Contents
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2014) to Revision D Page
• Added Top Navigation links to front page of the document
• Changed Product Status to Production Data
.....................................................................
.....................................................................................
• Changed Mission Critical Systems to Avionics and Defense in
..................................................
• Changed mission critical to avionics and defense in first paragraph of
......................................
• Changed Product Status to PD and changed footnote (3) in
.......................................................
• Changed second list item under Software Development Tools in
...........................................
• Added Related Links, Community Resources, Trademarks, Electrostatic Discharge Caution, and Glossary sections to
................................................................................................................
• Added
....................................................................................................................
• Changed DDR3A to DDR3 in
.........................................................................................
• Changed All instances of DDR3A to DDR3 in
......................................................................
• Changed Supply DDR3AREFSSTL to DDR3REFSSTL in
........................................................
• Changed the DVDD15 Volts and Supply Description in
...........................................................
• Changed Start Address for PCIe1SerDes Config to 00 0232 6000, End Address for USB 0 MMR CFG to 00
026F FFFF, and all instances of DDR3A to DDR3 in
• Changed CPT_DDR3A to CPT_DDR3 in
..............................................................
............................................................................
• Changed DDR3A to DDR3 in Event No. 388 Name and Description in
• Changed DDR3A to DDR3 in
.......................................
......................................................................................
• Changed DDR3A to DDR3 in
• Changed DDR3A to DDR3 in
........................................................................................
.......................................................................................
• Changed DDR3A to DDR3 in
.......................................................................................
• Added EMIF and NAND to Description in
..........................................................................
• Changed DDR3A to DDR3 in
....................................................................................
• Changed DDR3APLLCTL0 and DDR3APLLCTL1 to DDR3PLLCTL0 and DDR3PLLCTL1 in
............
• Changed AVSIFSEL Description value 11 to Reserved in
.....................................................
• Changed ARMENDIAN_CFG4_0 Default Value to 0x00023A00 in
...........................................
• Changed ARMENDIAN_CFG5_1 Default Value to 0x00000006 in
...........................................
• Changed DDR3AVREFSSTL to DDR3VREFSSTL and DDR3A to DDR3 in
................................
• Changed MIN, NOM, and MAX values for CVDD Initial and CVDD1; changed DVDD15 to DDR3 I/O voltage and added values; changed DDR3A to DDR3 and DDR3AVREFSSTL to DDR3VREFSSTL; changed DSP to SOC in footnote (4) in
........................................................................................................
• Changed DDR3A to DDR3 in
......................................................................................
• Changed DDR3A to DDR3 and changed DVDD15 to DDR3 memory I/O voltage and DDR3 (1.5/1.35 V) I/O
Buffer Type in
..........................................................................................................
• Changed DDR3A to DDR3 and added 1.35 V to Voltage for DVDD15 in
....................................
• Changed EMIF(DDR3A) to EMIF(DDR3) in
• Changed DDR3A EMIF to DDR3 EMIF in
......................................................................
........................................................................
• Changed DDR3A in
• Changed DDR3A in
.............................................................................................
................................................................................................
• Changed
..............................................................................................................
• Deleted second sentence from
..............................................................................
• Changed DDR3A to DDR3 in
.....................................................................................
• Changed Address Range 00 0231 0128 to Reserved in
......................................................
• Changed OUTPUT DIVIDE Field Description in
...............................................................
• Changed MAX value for tj(CORECLKN) and tj(CORECLKP) in
.............................................
• Changed
............................................................................................................
• Changed PAPLL Field Description in
............................................................................
• Changed MAX value for tc(NETCPCLKN) and tc(NETCPCLKP) in
.........................................
• Changed DDR3A Memory Controller to DDR3 Memory Controller in
......................................
• Changed MIN and MAX values for t c
(CEL) in
• Changed DDR3A to DDR3 in
..................................................................
.....................................................................................
Revision History
7
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3 Device Characteristics
provides an overview of the AM5K2E0x device. The table shows the significant features of the device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
Table 3-1. Characteristics of the AM5K2E0x Processor
ARM Cores
Peripherals
Accelerators
On-Chip L3 Memory
JTAG BSDL_ID
Frequency
Voltage
BGA Package
Process Technology
Product Status
(3)
HARDWARE FEATURES
ARM Cortex A15 Cores
ARM L1 instruction cache memory size (per core)
ARM L1 data cache memory size (per core)
ARM L2 unified cache memory size (shared by all cores)
DDR3 memory controller (72-bit bus width) [1.5 V/1.35V] (clock source =
DDRREFCLKN|P)
EDMA3 (64 independent channels) [CPU/3 clock rate]
Hyperlink
USB 3.0
USIM
I
2
C
SPI
(1)
PCIe (2 lanes per instance)
UART
10/100/1000/10000 Ethernet ports
10/100/1000 Ethernet ports
Management Data Input/Output (MDIO)
64-bit timers (configurable)
General-Purpose Input/Output port (GPIO)
TSIP
Packet Accelerator
Security Accelerator
(2)
Organization
JTAGID Register (address location: 0x02620018)
ARM-A15 Processor
Core (V)
I/O (V)
27 mm x 27 mm nm
Product Preview (PP), Advance Information (AI), or Production Data (PD)
AM5K2E02
2
32KB
32KB
4MB
1
AM5K2E04
4
2
1
3
5
1
0
8
2
8
3
Twelve 64-bit or Twenty four 32-bit
32
1
1
3
2
2
1
2MB MSM SRAM
256 KB L3 ROM
0x0B9A_602F
1.25 GHz
1.4 GHz
SmartReflex variable supply
1.35 V, 1.5 V, 1.8 V, and 3.3 V
1089-Pin Flip-Chip Plastic BGA
(ABD)
28 nm
PD
(1) The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details.
(2) The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
(3) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
8
Device Characteristics
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3.1
ARM CorePac
The ARM CorePac of the AM5K2E0x integrates a Cortex-A15 Cluster (4 Cortex-A15 processors) with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order, superscalar pipeline with integrated L1 caches. The implementation also supports advanced SIMDV2 (Neon technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE
(Large Physical Address Extension), and multiprocessing extensions. The quad core cluster includes a
4MB L2 cache and support for AMBA4 AXI and AXI Coherence Extension (ACE) protocols. For more information see the KeyStone II Architecture ARM CorePac User's Guide User Guide ( SPRUHJ4 ).
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3.2
Development Tools
3.2.1
Development Support
In case the customer would like to develop their own features and software on the AM5K2E0x device, TI offers an extensive line of development tools for the KeyStone II platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of KeyStone devices:
• Software Development Tools:
– Code Composer Studio Integrated Development Environment (IDE), including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
– Scalable, Real-Time foundation software, which provides the basic run-time target software needed to support any application
• Hardware Development Tools:
– Extended Development System (XDS™) Emulator (supports multiprocessor system debug) XDS™
– EVM (Evaluation Module)
3.3
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each family member has one of two prefixes: X or [blank]. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices/tools.
3.3.1
Device Development Evolutionary Flow
The device development evolutionary flow is as follows:
• X: Experimental device that is not necessarily representative of the final device's electrical specifications
• [Blank]: Fully qualified production device
Support tool development evolutionary flow:
• X: Development-support product that has not yet completed Texas Instruments internal qualification testing.
• [Blank]: Fully qualified development-support product
Experimental (X) and fully qualified [Blank] devices and development-support tools are shipped with the following disclaimer:
Developmental product is intended for internal evaluation purposes.
Fully qualified and production devices and development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that experimental devices (X) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ABD), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).
For device part numbers and further ordering information for AM5K2E0x in the ABD package type, see the
TI website www.ti.com
or contact your TI sales representative.
10
Device Characteristics
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3.3.2
Part Number Legend
The following figures provide a legend for reading the complete device name for a KeyStone II device.
( _ )
AM5 K2 E 02
( _ ) ( _ )
ABD
( _ ) ( _ )
PREFIX
X = Experimental device
Blank = Qualified device
DEVICE FAMILY
AM5 = ARM SoC
ARCHITECTURE
K2 = KeyStone II
PLATFORM
E
DEVICE NUMBER
02
SILICON REVISION
Blank = Initial 1.0 silicon
MAXIMUM DEVICE SPEED
25 = 1.25 GHz
4 = 1.4 GHz
TEMPERATURE RANGE
Blank = Commercial temperature range ( 0°C to +85°C)
A = Extended temperature range (-40°C to +100°C)
PACKAGE TYPE
ABD = 1089-pin plastic ball grid array, with Pb-free solder balls and die bumps
SECURITY
Blank = Security Accelerator disabled / General Purpose device
X = Security Accelerator enabled / General Purpose device
D = Security Accelerator enabled / High Security device with TI developmental keys
S = Security Accelerator enabled / High Security device with production keys
Figure 3-1. Device Nomenclature for AM5K2E02
( _ )
AM5 K2 E 04
( _ ) ( _ )
ABD
( _ ) ( _ )
PREFIX
X = Experimental device
Blank = Qualified device
DEVICE FAMILY
AM5 = ARM SoC
ARCHITECTURE
K2 = KeyStone II
PLATFORM
E
DEVICE NUMBER
04
SILICON REVISION
Blank = Initial 1.0 silicon
MAXIMUM DEVICE SPEED
25 = 1.25 GHz
4 = 1.4 GHz
TEMPERATURE RANGE
Blank = Commercial temperature range ( 0°C to +85°C)
A = Extended temperature range (-40°C to +100°C)
PACKAGE TYPE
ABD = 1089-pin plastic ball grid array, with Pb-free solder balls and die bumps
SECURITY
Blank = Security Accelerator disabled / General Purpose device
X = Security Accelerator enabled / General Purpose device
D = Security Accelerator enabled / High Security device with TI developmental keys
S = Security Accelerator enabled / High Security device with production keys
Figure 3-2. Device Nomenclature for AM5K2E04
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3.4
Related Documentation from Texas Instruments
These documents describe the AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC). Copies of these documents are available on the Internet at www.ti.com
.
KeyStone Architecture Timer 64P User's Guide
KeyStone II Architecture ARM Bootloader User's Guide
KeyStone II Architecture ARM CorePac User's Guide
KeyStone Architecture Chip Interrupt Controller (CIC) User's Guide
KeyStone I Architecture Debug and Trace User's Guide
DDR3 Design Requirements for KeyStone Devices application report
KeyStone Architecture DDR3 Memory Controller User's Guide
KeyStone Architecture External Memory Interface (EMIF16) User's Guide
Emulation and Trace Headers Technical Reference Manual
KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide
KeyStone Architecture General Purpose Input/Output (GPIO) User's Guide
Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide
KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User's Guide
KeyStone Architecture HyperLink User's Guide
Hardware Design Guide for KeyStone II Devices application report
KeyStone Architecture Inter-IC control Bus (I
2
C) User's Guide
KeyStone Architecture Memory Protection Unit (MPU) User's Guide
KeyStone Architecture Multicore Navigator User's Guide
KeyStone Architecture Multicore Shared Memory Controller (MSMC) User's Guide
KeyStone II Architecture Multicore Shared Memory Controller (MSMC) User's Guide
KeyStone II Architecture Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide
Optimizing Application Software on KeyStone Devices application report
KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide
KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User's Guide
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
KeyStone Architecture Power Sleep Controller (PSC) User's Guide
KeyStone II Architecture Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide
Security Addendum for KeyStone II Devices application report
(1)
KeyStone Architecture Semaphore2 Hardware Module User's Guide
KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide
KeyStone Architecture Serial Peripheral Interface (SPI) User's Guide
KeyStone Architecture Telecom Serial Interface Port (TSIP) User's Guide
KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User's Guide
KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide
KeyStone II Architecture IQN2 User's Guide
(1) Contact a TI sales office to obtain this document.
SPRUGV5
SPRUHJ3
SPRUHJ4
SPRUGW4
SPRUGZ2
SPRABI1
SPRUGV8
SPRUGZ3
SPRU655
SPRUGS5
SPRUGV1
SPRUGV9
SPRUHJ5
SPRUGW8
SPRABV0
SPRUGV3
SPRUGW5
SPRUGR9
SPRUGW7
SPRUHJ6
SPRUHZ0
SPRABG8
SPRUHZ2
SPRUGS6
SPRUGV2
SPRUGV4
SPRUHZ1
SPRABS4
SPRUGS3
SPRUHO3
SPRUGP2
SPRUGY4
SPRUGP1
SPRUHJ7
SPRUH06
12
Device Characteristics
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3.5
Related Links
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS
AM5K2E04
AM5K2E02
PRODUCT FOLDER
Click here
Click here
Table 3-2. Related Links
SAMPLE & BUY
Click here
Click here
TECHNICAL
DOCUMENTS
Click here
Click here
TOOLS &
SOFTWARE
Click here
Click here
SUPPORT &
COMMUNITY
Click here
Click here
3.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use .
TI E2E™ Online Community
TI's Engineer-to-Engineer (E2E) Community.
Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
3.7
Trademarks
Code Composer Studio, XDS, E2E are trademarks of Texas Instruments.
MPCore is a trademark of ARM Ltd or its subsidiaries.
ARM, Cortex are registered trademarks of ARM Ltd or its subsidiaries.
All other trademarks are the property of their respective owners.
3.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
3.9
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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4 ARM CorePac
The ARM CorePac is added in the AM5K2E0x to enable the ability for layer 2 and layer 3 processing onchip. Operations such as traffic control, local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor core.
The ARM CorePac of the AM5K2E0x integrates one or more Cortex-A15 processor clusters with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order superscalar execution engine with integrated L1 caches. The implementation also supports advanced SIMDv2 (NEON technology) and VFPv4 (vector floating point) architecture extensions, security, virtualization, LPAE (large physical address extension), and multiprocessing extensions. The ARM CorePac includes an L2 cache and support for AMBA4 AXI and AXI coherence extension (ACE) protocols. An interrupt controller is included in the ARM CorePac to handle host interrupt requests in the system.
The ARM CorePac has three functional clock domains, including a high-frequency clock domain used by the Cortex-A15. The high-frequency domain is isolated from the rest of the device by asynchronous bridges.
The following figures show the ARM CorePac.
480 SPI
Interrupts
TeraNet
(CFG)
AM5K2E04
KeyStone II ARM CorePac (Quad Core)
ARM
ARM INTC
Generic
Interrupt
Controller
400
IRQ,
FIQ,
VIRQ,
VFIQ
16
PPI
VBUSP2AXI
Bridge
Global
Time Base
Counter
64
Bits
ARM Cluster
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
STM
ATB
ARM
Trace
ATB
PTM (
´
4)
Debug
CTI/CTM
CTM
CTI (
´
4)
APB
APB MUX
APB
VBUSP
OCP
ATB
APB
ARM
VBUSP
Registers
VBUSP
AXI-VBUS
Master
256b
VBUSM
Endian
CFG
ARM
CorePac
Clock
Main PLL
ARM
A15 Core
Clock
ARM PLL
Boot Config
Figure 4-1. AM5K2E04 ARM CorePac Block Diagram
PSC
TeraNet
(DMA)
Debug
SubSystem
TeraNet
(CFG)
MSMC
DDR3
14
ARM CorePac
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480 SPI
Interrupts
TeraNet
(CFG)
AM5K2E02
KeyStone II ARM CorePac (Dual Core)
ARM
ARM INTC
Generic
Interrupt
Controller
400
IRQ,
FIQ,
VIRQ,
VFIQ
8
PPI
VBUSP2AXI
Bridge
ARM Cluster
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
STM
ATB
ARM
Trace
ATB
PTM (
´
4)
Debug
APB
APB MUX
APB
CTI/CTM
Global
Time Base
Counter
64
Bits
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
CTM
CTI (
´
4)
VBUSP
OCP
ATB
APB
ARM
VBUSP
Registers
VBUSP
AXI-VBUS
Master
256b
VBUSM
Endian
CFG
Boot Config
ARM
CorePac
Clock
Main PLL
ARM
A15 Core
Clock
Figure 4-2. AM5K2E02 ARM CorePac Block Diagram
PSC
TeraNet
(DMA)
Debug
SubSystem
TeraNet
(CFG)
MSMC
DDR3
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4.1
Features
The key features of the Quad Core ARM CorePac are as follows:
• One or more Cortex-A15 processors, each containing:
– Cortex-A15 processor revision R2P4.
– ARM architecture version 7 ISA.
– Multi-issue, out-of-order, superscalar pipeline.
– L1 and L2 instruction and data cache of 32KB, 2-way, 16 word line with 128-bit interface.
– Integrated L2 cache of 4MB, 16-way, 16-word line, 128-bit interface to L1 along with ECC/parity.
– Includes the NEON media coprocessor (NEON™), which implements the advanced SIMDv2 media processing architecture and the VFPv4 Vector Floating Point architecture.
– The external interface uses the AXI protocol configured to 128-bit data width.
– Includes the System Trace Macrocell (STM) support for non-invasive debugging.
– Implements the ARMv7 debug with watchpoint and breakpoint registers and 32-bit advanced peripheral bus (APB) slave interface to CoreSight™ debug systems.
• Interrupt controller
– Supports up to 480 interrupt requests
– An integrated Global Time Base Counter (clocked by the SYSCLK divided by 6)
• Emulation/debug
– Compatible with CoreSight™ architecture
4.2
System Integration
The ARM CorePac integrates the following group of submodules.
• Cortex-A15 Processors: Provides a high processing capability, including the NEON™ technology for mobile multimedia acceleration. The Cortex-A15 communicates with the rest of the ARM CorePac through an AXI bus with an AXI2VBUSM bridge and receives interrupts from the ARM CorePac interrupt controller (ARM INTC).
• Interrupt Controller: Handles interrupts from modules outside of the ARM CorePac (for details, see
).
• Clock Divider: Provides the required divided clocks to the internal modules of the ARM CorePac and has a clock input from the Main PLL.
• In-Circuit Emulator: Fully compatible with CoreSight™ architecture and enables debugging capabilities.
4.3
ARM Cortex-A15 Processor
4.3.1
Overview
The ARM Cortex-A15 processor incorporates the technologies available in the ARM7™ architecture.
These technologies include NEON™ for media and signal processing and Jazelle™ RCT for acceleration of real-time compilers, Thumb®-2 technology for code density, and the VFPv4 floating point architecture.
For details, see the ARM Cortex-A15 Processor Technical Reference Manual.
4.3.2
Features
shows the features supported by the Cortex-A15 processor core.
FEATURES
ARM version 7-A ISA
Table 4-1. Cortex-A15 Processor Core Supported Features
DESCRIPTION
Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and media extensions
Backward compatible with previous ARM ISA versions
16
ARM CorePac
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FEATURES
Cortex-A15 processor version
Integer core
NEON core
Architecture Extensions
L1 Lcache and Dcache
L2 cache
Cache Coherency
Table 4-1. Cortex-A15 Processor Core Supported Features (continued)
Branch target address cache
DESCRIPTION
R2P4
Main core for processing integer instructions
Gives greatly enhanced throughput for media workloads and VFP-Lite support
Security, virtualization and LPAE (40-bit physical address) extensions
32KB, 2-way, 16 word line, 128 bit interface
4096KB, 16-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported shared between cores
L2 valid bits cleared by software loop or by hardware
Support for coherent memory accesses between A15 cores and other non-core master peripherals
(Ex: EDMA) in the DDR3 and MSMC SRAM space.
Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return stack, and an indirect predictor
Mapping sizes are 4KB, 64KB, 1MB, and 16MB Enhanced memory management unit
Buses
Non-invasive Debug Support
Misc Debug Support
Voltage
Power
128b AXI4 internal bus from Cortex-A15 converted to a 256b VBUSM to interface (through the
MSMC) with MSMC SRAM, DDR EMIF, ROM, Interrupt controller and other system peripherals
Processor instruction trace using 4x Program Trace Macrocell (Coresight™ PTM), Data trace (print-f style debug) using System Trace Macrocell (Coresight™ STM) and Performance Monitoring Units
(PMU)
JTAG based debug and Cross triggering
SmartReflex voltage domain for automatic voltage scaling
Support for standby modes and separate core power domains for additional leakage power reduction
4.3.3
ARM Interrupt Controller
The ARM CorePac interrupt controller (AINTC) is responsible for prioritizing all service requests from the system peripherals and the secondary interrupt controller CIC2 and then generating either nIRQ or nFIQ to the Cortex-A15 processor. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. The AINTC interfaces to the Cortex-A15 processor via the AXI port through an
VBUS2AXI bridge and runs at half the processor speed. It has the capability to handle up to 480 requests, which can be steered/prioritized as A15 nFIQ or nIRQ interrupt requests.
The general features of the AINTC are:
• Up to 480 level sensitive shared peripheral interrupts (SPI) inputs
• Individual priority for each interrupt input
• Each interrupt can be steered to nFIQ or nIRQ
• Independent priority sorting for nFIQ and nIRQ
• Secure mask flag
On the chip level, there is a dedicated chip level interrupt controller to serve the ARM interrupt controller.
See
for more details.
The figures below show an overall view of the ARM CorePac Interrupt Controller.
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Peripherals
CIC2
CPU/6 Clock
GTB Counter Clock
Power On Reset
480 SPI
Interrupts
ARM INTC
Generic
Interrupt
Controller
400
Global
Time Base
Counter
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
8 PPIs
64 Bits
Cortex
A15
VBUSP Interface
VBUSP2AXI
Bridge
16 Software
Generated
Inputs
Figure 4-3. ARM Interrupt Controller for Two Cortex-A15 Processor Cores
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
Peripherals
CIC2
480 SPI
Interrupts
ARM INTC
Generic
Interrupt
Controller
400
16 PPIs
CPU/6 Clock
GTB Counter Clock
Power On Reset
Global
Time Base
Counter
64 Bits
Cortex
A15
VBUSP Interface
VBUSP2AXI
Bridge
16 Software
Generated
Inputs
Figure 4-4. ARM Interrupt Controller for Four Cortex-A15 Processor Cores
4.3.4
Endianess
The ARM CorePac can operate in either little endian or big endian mode. When the ARM CorePac is in little endian mode and the rest of the system is in big endian mode, the bridges in the ARM CorePac are responsible for performing the endian conversion.
4.4
CFG Connection
The ARM CorePac has two slave ports. The AM5K2E0x masters cannot access the ARM CorePac internal memory space.
1. Slave port 0 (TeraNet 3P_A) is a 32 bit wide port used for the ARM Trace module.
2. Slave port 1 (TeraNet 3P_B) is a 32 bit wide port used to access the rest of the system configuration.
4.5
Main TeraNet Connection
There is one master port coming out of the ARM CorePac. The master port is a 256 bit wide port for the transactions going to the MSMC and DDR_EMIF data spaces.
18
ARM CorePac
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4.6
Clocking and Reset
4.6.1
Clocking
The Cortex-A15 processor core clocks are sourced from the Controller. The Cortex-A15 processor core clock has a maximum frequency of 1.4 GHz. The ARM CorePac subsytem also uses the SYSCLK1 clock source from the main PLL which is locally divided (/1, /3 and /6) and provided to certain sub-modules inside the ARM CorePac. AINTC sub module runs at a frequency of SYSCLK1/6.
4.6.2
Reset
The ARM CorePac does not support local reset. It is reset whenever the device is under reset. In addition, the interrupt controller (AINTC) can only be reset during POR and RESETFULL. AINTC also resets whenever device is under reset.
For the complete programming model, refer to the KeyStone II Architecture ARM CorePac User's Guide
( SPRUHJ4 ).
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5 Terminals
5.1
Package Terminals
shows the ABD 1089-ball grid array package (bottom view).
32 30 28 26 24 22 20 18 16 14 12 10 8
33 31 29 27 25 23 21 19 17 15 13 11 9 7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AN
AM
Figure 5-1. ABD 1089-Pin BGA Package (Bottom View)
5.2
Pin Map
The following figures show the AM5K2E0x pin assignments in four panels (A, B, C, and D).
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A B
C
D
20
Terminals
Figure 5-2. Pin Map Panels (Bottom View)
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NOTE
XFI pins are associated with the 10-GbE feature and are supported only in the AM5K2E04 part.
AJ
AK
AL
AM
AN
AE
AF
AG
AH
AA
AB
AC
AD
U
V
W
Y
R
T
N
P
L
M
J
K
G
H
E
F
C
D
A
B
UART1RTS
UART0DTR
GPIO03
GPIO09
GPIO14
GPIO16
GPIO18
GPIO21
GPIO28
GPIO30
RSV029
RSV028
POR
TCK
TSIP0CLKB
TSIP0TR1
DVDD18
VSS
33
33
VSS
DVDD15
DDRDQS7P
DDRDQS7N
DDRD60
DDRD57
VCNTL1
USIMIO
USIMCLK
TIMI0
SPI2CLK
SPI1CLK
SPI1SCS3
SPI2SCS2
UART0CTS
UART1TXD
VSS
GPIO04
GPIO06
GPIO12
VSS
GPIO17
GPIO24
GPIO27
VSS
RESETFULL
TRST
TMS
SDA1
TSIP0FSB
TSIP0TX0
TSIP0TX1
DVDD18
32
32
DVDD15
DDRD63
DDRD61
DDRD62
DDRD59
DDRD58
VCNTL4
RSV000
RSV001
TIMI1
SPI0SCS3
SPI1SCS1
VSS
SPI1DOUT
UART0RTS
UART1CTS
DVDD18
GPIO07
GPIO08
GPIO15
DVDD18
GPIO19
GPIO23
GPIO29
DVDD18
BOOTCOMPLETE
TDI
SCL2
TSIP0FSA
TSIP0CLKA
VSS
TSIP0TR0
VSS
31
31
DDRDQM7
DDRD50
DVDD15
VSS
DDRDQM6
DDRD56
VSS
VCNTL2
VCNTL5
TIMO0
SPI0SCS0
SPI0DIN
DVDD18
SPI2SCS0
SPI2DOUT
UART0RXD
UART1RXD
VCL
UART0DSR
GPIO02
GPIO01
GPIO10
GPIO20
GPIO22
RESET
TDO
SDA2
RESETSTAT
VSS
SGMII0TXN1
SGMII0TXP0
SGMII0RXP1
SGMII0RXN0
29
29
DDRD48
DDRD52
VSS
DVDD15
DDRD51
DVDD15
VSS
VCNTL0
RSV014
USIMRST
SPI0SCS2
SPI0SCS1
SPI0DOUT
SPI1SCS0
SPI2SCS1
UART0TXD
VD
GPIO00
GPIO05
GPIO11
GPIO13
GPIO25
GPIO26
GPIO31
RSV030
HOUT
SCL0
SCL1
DVDD18
VSS
SGMII0TXN0
VSS
SGMII0RXP0
30
30
DDRDQS6P
DDRDQS6N
DDRD53
DDRD55
DDRD54
VSS
DVDD15
VCNTL3
RSV013
TIMO1
SPI2SCS3
SPI0CLK
SPI1SCS2
SPI2DIN
SPI1DIN
Figure 5-3. AM5K2Ex Left End Panel (A) — Bottom View
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
SDA0
VSS
RSV018
SGMII0TXP1
VSS
SGMII0RXN1
VSS
28
28
DDRD49
DDRD44
DDRD42
DDRD41
DDRD40
VSS
DVDD15
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
SGMII00REFRES
VSS
SGMII0TXN2
VSS
SGMII0RXP2
27
27
DDRDQS5P
DDRDQS5N
VSS
DVDD15
DDRD43
DVDD15
VSS
DVDD15
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
VSS
DVDD18
VSS
RSV019
SGMII0TXN3
SGMII0TXP2
SGMII0RXP3
SGMII0RXN2
26
26
DDRD45
DDRD46
DDRD47
DDRDQM5
DDRDQM4
VSS
DVDD15
VSS
CVDD
VSSTMON
CVDDTMON
VSS
CVDD
VSS
CVDD
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Terminals
21
AJ
AK
AL
AM
AN
AE
AF
AG
AH
AA
AB
AC
AD
W
Y
U
V
R
T
N
P
L
M
J
K
E
F
G
H
C
D
A
B
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
SGMII0CLKN
SGMII0TXP3
VSS
SGMII0RXN3
VSS
25
25
DDRD39
DDRD38
DVDD15
VSS
DDRD37
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
VDDALV
VSS
VDDALV
VSS
SGMII0CLKP
VSS
SGMII0TXN4
VSS
SGMII0RXP4
24
24
DDRDQS4P
DDRDQS4N
DDRD35
DDRD34
DDRD36
VSS
AVDDA10
VSS
VNWA2
VSS
CVDD1
VSS
CVDD1
VSS
CVDD
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
VSS
VNWA3
VSS
VDDALV
VSS
VDDAHV
VSS
SGMII0TXN5
SGMII0TXP4
SGMII0RXP5
SGMII0RXN4
23
23
DDRCB00
DDRD32
VSS
DVDD15
DDRD33
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDALV
VSS
SGMII01REFRES
SGMII0TXP5
VSS
SGMII0RXN5
VSS
22
22
DDRDQS8N
DDRDQS8P
DDRCB04
DDRCB01
DDRCB02
VSS
AVDDA9
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
VSS
VSS
SGMII0TXN6
VSS
SGMII0RXP6
21
21
DDRCB07
DDRCB05
DVDD15
VSS
DDRCB03
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
Figure 5-4. AM5K2Ex Left Center Panel (B) — Bottom View
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDALV
VSS
RSV016
SGMII0TXN7
SGMII0TXP6
SGMII0RXP7
SGMII0RXN6
20
20
DDRCB06
DDRDQM8
DDRCKE0
DDRRESET
RSV022
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
VSS
SGMII0TXP7
VSS
SGMII0RXN7
VSS
19
19
DDRCKE1
RSV021
VSS
DVDD15
DDRA15
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
www.ti.com
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDALV
VSS
PCIE0CLKN
VSS
PCIE0TXN0
VSS
PCIE0RXP0
18
18
DDRA08
DDRBA2
DDRA14
DDRA11
DDRA12
VSS
DDRRZQ2
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
22
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CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
PCIE0CLKP
PCIE0TXN1
PCIE0TXP0
PCIE0RXP1
PCIE0RXN0
17
17
DDRA06
DDRA09
DVDD15
VSS
DDRA07
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDALV
VSS
VSS
PCIE0TXP1
VSS
PCIE0RXN1
VSS
16
16
DDRCLKOUTP1
DDRA02
DDRA03
DDRA04
DDRA05
VSS
AVDDA8
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
PCIE1CLKN
VSS
PCIE1TXN0
VSS
PCIE1RXP0
15
15
DDRCLKOUTN1
DDRCLKOUTP0
DDRA01
DDRA00
DDRRZQ0
DDRVREFSSTL
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
VDDALV
VSS
RSV017
VSS
XFICLKN
VSS
XFITXN0
VSS
XFIRXP0
12
12
DDRCE0
DDRCAS
DDRCE1
DDRODT0
DDRA13
VSS
DDRRZQ1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
VDDUSB1
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
VSS
PCIE1TXP1
VSS
PCIE1RXN1
VSS
13
13
DDRA10
DDRRAS
DDRBA1
DDRBA0
DDRWE
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
VDDALV
VSS
PCIE0REFRES
VSS
PCIE1CLKP
PCIE1TXN1
PCIE1TXP0
PCIE1RXP1
PCIE1RXN0
14
14
RSV023
DDRCLKOUTN0
VSS
DVDD15
AVDDA7
VSS
DVDD15
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
Figure 5-5. AM5K2Ex Right Center Panel (C) — Bottom View
VDDUSB1
VSS
VDDUSB0
VSS
USB0DVDD33
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
VDDAHV
XFICLKP
XFITXN1
XFITXP0
XFIRXP1
XFIRXN0
11
11
DDRD26
DDRD25
DVDD15
VSS
DDRODT1
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
CVDD1
VSS
USB1DVDD33
VSS
VSS
VDDUSB0
VSS
USB0VPH
VSS
CVDD
VSS
CVDD
VSS
VDDALV
VSS
XFIREFRES0
VSS
PCIE1REFRES
XFITXP1
VSS
XFIRXN1
VSS
10
10
DDRDQS3P
DDRDQS3N
DDRD27
DDRD28
DDRD24
VSS
DVDD15
VSS
CVDDCMON
VSS
CVDD
VSS
CVDD
VSS
USB1VPH
9
DDRD31
DDRD29
VSS
DVDD15
DDRD30
DVDD15
VSS
DVDD15
VSSCMON
VPP0
VSS
VPP1
VSS
VNWA1
VSS
USB1VPTX
VSS
USB0VPTX
VSS
CVDD
VSS
CVDD
VSS
VNWA4
VSS
VDDALV
VSS
RSV020
VSS
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
HYPLNK0TXN0 AL
VSS
AM
HYPLNK0RXP0 AN
9
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VSS
USB0VP
VSS
RSV011
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
RSV015
VSS
HYPLNK0CLKN
HYPLNK0TXN1
HYPLNK0TXP0
HYPLNK0RXP1
HYPLNK0RXN0
8
8
DDRD22
DDRD23
DDRD21
DDRDQM2
DDRDQM3
VSS
AVDDA6
VSS
RSV010
RSV009
DVDD18
VSS
DVDD18
VSS
USB1VP
DVDD18
VSS
DVDD18
RSV012
DVDD18
VSS
DVDD18
VSS
AVDDA3
XFIMDIO
AVDDA1
VSS
XFIREFRES1
HYPLNK0CLKP
HYPLNK0TXP1
VSS
HYPLNK0RXN1
VSS
7
7
DDRDQS2N
DDRDQS2P
DVDD15
VSS
DDRD18
DVDD15
VSS
DVDD15
VSS
AVDDA2
VSS
DVDD18
VSS
DVDD18
VSS
EMIFWAIT0
EMIFA02
EMIFA03
USB1ID0
USB0RESREF
EMU01
HYPLNK0TXPMCLK
HYPLNK0TXFLCLK
EMU04
EMU03
XFIMDCLK
NETCPCLKSEL
MDCLK0
VSS
VSS
HYPLNK0TXN2
VSS
HYPLNK0RXP2
6
6
DDRD09
DDRD19
DDRD20
DDRD16
DDRD17
VSS
EMIFD09
EMIFD06
EMIFD05
EMIFD14
EMIFA23
EMIFA18
EMIFA05
EMIFA04
EMIFBE1
EMIFA13
EMIFA12
USB1RESREF
USB0VBUS
EMU17
EMU15
EMU06
EMU00
VSS
TSSYNCEVT
HYPLNK0TXPMDAT
RSV008
MDIO0
HYPLNK0REFRES
HYPLNK0TXN3
HYPLNK0TXP2
HYPLNK0RXP3
HYPLNK0RXN2
5
5
DDRD08
DDRD10
VSS
DVDD15
DDRD11
DVDD15
EMIFD00
EMIFD04
EMIFD15
EMIFD10
EMIFA17
EMIFA09
EMIFA08
EMIFA01
EMIFWE
USBCLKM
USBCLKP
USB1VBUS
USB0ID0
EMIFCE1
VSS
EMU08
EMU02
DVDD18
SYSCLKOUT
TSCOMPOUT
EMU11
HYPLNK0TXFLDAT
VSS
HYPLNK0TXP3
VSS
HYPLNK0RXN3
VSS
4
4
DDRDQS1P
DDRDQS1N
DDRD12
DDRD13
DDRD14
VSS
DDRCLKP
EMIFD13
EMIFD12
EMIFD02
EMIFA21
EMIFA10
EMIFA07
USB1DM
USB1DP
3
DDRDQM0
DDRD15
DVDD15
VSS
DDRDQM1
DDRD06
DDRCLKN
EMIFD11
VSS
EMIFD01
EMIFA14
EMIFA06
EMIFWAIT1
EMIFA00
EMIFA22
EMIFA15
VSS
USB0DP
USB0DM
EMIFRW
DVDD18
EMU14
EMU07
VSS
USB0TX0M
USB0TX0P
VSS
EMIFOE
EMIFBE0
EMU16
EMU13
EMU05
HYPLNK0RXFLDAT
EMU10
TSPUSHEVT0
EMU12
RSV002
RSV003
TSRXCLKOUT1P
EMU09 EMU18
HYPLNK0RXFLCLK TSRXCLKOUT0N
VSS
RSV006
TSREFCLKP
RSV007
VSS
NETCPCLKN
3
NETCPCLKP
VSS
2
2
DVDD15
DDRD07
DDRDQS0N
DDRD05
DDRD00
DDRD02
RSV004
EMIFD08
DVDD18
EMIFA19
EMIFA16
DVDD18
VSS
USB1TX0P
USB1TX0M
1
VSS
DVDD15
DDRDQS0P
DDRD01
DDRD03
DDRD04
RSV005
EMIFD07
EMIFD03
EMIFA20
EMIFA11
VSS
USB1RX0M
USB1RX0P
VSS
USB0RX0M
USB0RX0P
VSS
EMIFCE2
EMIFCE3
EMIFCE0
USB0DRVVBUS
USB1DRVVBUS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
HYPLNK0RXPMDAT AD
HYPLNK0RXPMCLK
AE
CORECLKP
AF
CORECLKN
AG
TSRXCLKOUT1N
AH
TSRXCLKOUT0P
AJ
TSREFCLKN
AK
TSPUSHEVT1
VSS
VSS
1
AL
AM
AN
Figure 5-6. AM5K2Ex Right End Panel (D) — Bottom View
24
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5.3
Terminal Functions
numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin descriptions. This table is arranged by function. The power terminal functions table
(
) lists the various power supply pins and ground pins and gives functional pin descriptions.
shows all pins arranged by signal name.
shows all pins arranged by ball number.
Some pins have additional functions beyond their primary functions. There are 21 pins that have a secondary function and 15 pins that have a tertiary function. Secondary functions are indicated with a superscript 2 (
2
) and tertiary functions are indicated with a superscript 3 (
3
).
For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see
.
Use the symbol definitions in
when reading
.
Table 5-1. I/O Functional Symbol Definitions
FUNCTIONAL
SYMBOL
IPD or IPU
A
GND
I
O
P
Z
DEFINITION
Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-k Ω resistor can be used to oppose the IPD/IPU.
Analog signal
Ground
Input terminal
Output terminal
Power supply voltage
Three-state terminal or high impedance
COLUMN
HEADING
IPD/IPU
Type
Type
Type
Type
Type
Type
SIGNAL NAME
BOOTMODE_RSVD
2
AVSIFSEL[0]
2
AVSIFSEL[1]
2
BOOTCOMPLETE
BOOTMODE00
2
BOOTMODE01
2
BOOTMODE02
2
BOOTMODE03
2
BOOTMODE04
2
BOOTMODE05
2
BOOTMODE06
2
BOOTMODE07
2
BOOTMODE08
2
BOOTMODE09
2
BOOTMODE10
2
BOOTMODE11
2
BOOTMODE12
2
BOOTMODE13
2
BOOTMODE14
2
BOOTMODE15
2
LENDIAN
2
Table 5-2. Terminal Functions — Signals and Control by Function
BALL NO.
TYPE IPD/IPU
Y31
K33
K32
AF31
AA29
Y29
V33
V32
W30
W32
V31
W31
W33
AB29
Y30
Y32
AA30
AA33
AB32
AB33
V30
I
I
I
I
I
I
OZ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Up
DESCRIPTION
Boot Configuration Pins
ARM Big Endian Configuration pin. Secondary function for GPIO15.
Default value (bootstrapped) for SR PINMUX Register (SR_PINCTL). Secondary function for TIMI0
Default value (bootstrapped) for SR PINMUX Register (SR_PINCTL). Secondary function for TIMI1
Boot progress indication output
User defined Boot Mode pin. Secondary function for GPIO01.
User defined Boot Mode pin. Secondary function for GPIO02.
User defined Boot Mode pin. Secondary function for GPIO03.
User defined Boot Mode pin. Secondary function for GPIO04.
User defined Boot Mode pin. Secondary function for GPIO05.
User defined Boot Mode pin. Secondary function for GPIO06.
User defined Boot Mode pin. Secondary function for GPIO07.
User defined Boot Mode pin. Secondary function for GPIO08.
User defined Boot Mode pin. Secondary function for GPIO09.
User defined Boot Mode pin. Secondary function for GPIO10.
User defined Boot Mode pin. Secondary function for GPIO11.
User defined Boot Mode pin. Secondary function for GPIO12.
User defined Boot Mode pin. Secondary function for GPIO13.
User defined Boot Mode pin. Secondary function for GPIO16.
User defined Boot Mode pin. Secondary function for GPIO17.
User defined Boot Mode pin. Secondary function for GPIO18.
Little Endian Configuration pin. Secondary function for GPIO00.
Terminals
25
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CORECLKN
CORECLKP
DDRCLKN
DDRCLKP
HOUT
HYPLNK0CLKN
HYPLNK0CLKP
NETCPCLKN
NETCPCLKP
NETCPCLKSEL
PCIE0CLKN
PCIE0CLKP
PCIE1CLKN
PCIE1CLKP
POR
RESETFULL
RESETSTAT
SIGNAL NAME
MAINPLLODSEL
2
RESET
SGMII0CLKN
SGMII0CLKP
SYSCLKOUT
TSREFCLKN
TSREFCLKP
TSRXCLKOUT0N
TSRXCLKOUT0P
TSRXCLKOUT1N
TSRXCLKOUT1P
USBCLKM
USBCLKP
XFICLKN
XFICLKP
AK2
AJ2
AJ1
AH1
AG2
T4
AE29
AJ25
AJ24
AE4
AK1
U4
AJ12
AJ11
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
BALL NO.
TYPE
Y33 I
IPD/IPU
Down
DESCRIPTION
Post divider select for main PLL.. Secondary function for GPIO14.
Clock / Reset
AJ8
AJ7
AN3
AM2
AG6
AJ18
AJ17
AG1
AF1
G3
G4
AF30
AJ15
AJ14
AH33
AF32
AH29
I
I
I
I
I
I
I
I
I
I
I
OZ
I
I
I
I
O
Up
Down
Up
Up
Up
System clock input to main PLL
DDR3 reference clock input to DDR PLL
Interrupt output pulse created by IPCGRH
HyperLink reference clock to drive HyperLink SerDes
NETCP sub-system reference clock
NETCP clock select to choose between core clock and NETCPCLK pins
PCIe Clock input to drive PCIe0 SerDes
PCIe Clock Input to drive PCIe1 SerDes
Power-on reset
Full reset
Reset Status Output. Drives low during Power-on Reset (No HHV override). Available after core and IOs are completely powered-up.
Warm reset of non-isolated portion of the device
I
O
O
I
O
O
I
I
I
I
I
I
I
OZ Down
SGMII reference clock to drive both SGMII0 SerDes SGMII reference clock to drive the SGMII
SerDes
System clock output to be used as a general purpose output clock for debug purposes
Clock from external OCXO/VCXO for SyncE
SERDES recovered clock output for SyncE
SERDES recovered clock output for SyncE
USB0_3.0 reference clock
XFI reference clock to drive the XFI SerDes
26
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SIGNAL NAME
DDRA11
DDRA12
DDRA13
DDRA14
DDRA15
DDRBA0
DDRBA1
DDRBA2
DDRCAS
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRA00
DDRA01
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDRA08
DDRA09
DDRA10
DDRCB04
DDRCB05
DDRCB06
DDRCB07
DDRCE0
DDRCE1
DDRCKE0
DDRCKE1
DDRCLKOUTN0
DDRCLKOUTP0
DDRCLKOUTN1
DDRCLKOUTP1
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
BALL NO.
TYPE IPD/IPU DESCRIPTION
DDR3
B18
B12
A23
D22
E22
E21
D18
E18
E12
C18
E19
D13
C13
D16
E16
A17
E17
A18
B17
A13
D15
C15
B16
C16
A19
B14
B15
A15
A16
C22
B21
A20
A21
A12
C12
C20
OZ
OZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
DDR3 EMIF address bus
DDR3 EMIF bank address
DDR3 EMIF column address strobe
DDR3 EMIF check bits
DDR3 EMIF chip enable0
DDR3 EMIF chip enable1
DDR3 EMIF clock enable0
DDR3 EMIF clock enable1
DDR3 EMIF Output Clocks to drive SDRAMs for Rank0
DDR3 EMIF Output Clocks to drive SDRAMs for Rank1
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DDRD39
DDRD40
DDRD41
DDRD42
DDRD43
DDRD44
DDRD45
DDRD46
DDRD47
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD12
DDRD13
DDRD14
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
SIGNAL NAME
DDRD00
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
DDRD06
DDRD07
DDRD08
DDRD09
DDRD10
DDRD11
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
IPD/IPU DESCRIPTION
A25
E28
D28
C28
E27
B28
A26
B26
C26
B23
E23
D24
C24
E24
E25
B25
B9
E9
A9
B11
A11
C10
D10
B6
C6
C8
A8
B8
E10
B3
D6
E6
E7
C4
D4
E4
A6
B5
E5
D2
F3
B2
A5
F2
E1
F1
BALL NO.
TYPE
E2 IOZ
D1 IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
DDR3 EMIF data bus
DDR3 EMIF data bus
DDR3 EMIF data bus
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DDRDQS7N
DDRDQS7P
DDRDQS8N
DDRDQS8P
DDRODT0
DDRODT1
DDRRAS
DDRRESET
DDRRZQ0
DDRRZQ1
DDRRZQ2
DDRWE
DDRDQS0N
DDRDQS0P
DDRDQS1N
DDRDQS1P
DDRDQS2N
DDRDQS2P
DDRDQS3N
DDRDQS3P
DDRDQS4N
DDRDQS4P
DDRDQS5N
DDRDQS5P
DDRDQS6N
DDRDQS6P
DDRD60
DDRD61
DDRD62
DDRD63
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
SIGNAL NAME
DDRD48
DDRD49
DDRD50
DDRD51
DDRD52
DDRD53
DDRD54
DDRD55
DDRD56
DDRD57
DDRD58
DDRD59
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
IPD/IPU DESCRIPTION
B13
D20
E15
G12
G18
E13
D33
C33
A22
B22
D12
E11
A10
B24
A24
B27
A27
B30
A30
C2
C1
B4
A4
A7
B7
B10
E8
E26
D26
E31
A31
B20
E33
C32
D32
B32
A3
E3
D8
C30
E30
D30
F31
F33
F32
E32
BALL NO.
TYPE
A29 IOZ
A28 IOZ
B31
E29
B29
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
A
A
OZ
OZ
A
OZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
DDR3 EMIF data bus
DDR3 EMIF Data Masks
DDR3 EMIF data strobe. Programmable pull-up/dn 350-650 ohm.
DDR3 EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3 EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3 EMIF row address strobe
DDR3 reset signal. IO will work in LVCMOS mode to comply with JEDEC standard.
PTV compensation reference resistor pin for DDR3
PTV compensation reference resistor pin for DDR3
PTV compensation reference resistor pin for DDR3
DDR3 EMIF write enable
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EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFBE0
EMIFBE1
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
EMIFOE
EMIFRW
EMIFWAIT0
EMIFWAIT1
EMIFWE
SIGNAL NAME
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
BALL NO.
TYPE IPD/IPU DESCRIPTION
EMIF
L4
R3
L6
M6
K2
K1
L3
T3
L2
L5
L1
U5
T5
P6
N6
M3
N4
N5
M5
M4
P3
P5
U6
V6
Y3
T6
N3
R5
AA2
R6
AA1
Y4
W1
Y1
Y2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
O
O
O
O
O
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Up
Up
Up
Up
Up
Up
Up
Up
Down
Down
Up
EMIF address
EMIF address
EMIF control signals
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EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
EMU19
3
EMU20
3
EMU21
3
EMU22
3
EMU23
3
EMU24
3
EMU25
3
EMU26
3
EMU27
3
EMU28
3
EMU29
3
EMU30
3
EMU31
3
EMU32
3
EMU00
EMU01
EMU02
EMU03
EMU04
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
SIGNAL NAME
EMIFD00
EMIFD01
EMIFD02
EMIFD03
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
AC29
AC33
AD29
AC31
AC32
AB30
AC30
AD3
AB5
AC3
AB4
AH3
AF3
AG4
AC5
AA6
AC4
AE6
AD6
AD2
AC2
AB3
AA5
AB2
Y5
AH2
AB32
AB33
AB31
AD32
AD33
AD31
AE33
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
DESCRIPTION
J4
H4
K6
J5
J6
H6
H1
H2
G6
K5
H3
K4
J1
H5
BALL NO.
TYPE
G5 IOZ
K3 IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Down
Down
Down
Down
Down
Down
Down
IPD/IPU
Down
Down
Down
Down
Down
Down
Down
Down
Down
EMIF data
EMU
Down
Down
Down
Down
Down
Down
Down
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Down
Down
Down
Down
Down
Down
Down
Emulation and trace port
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO17.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO18.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO19.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO20.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO21.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO22.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO23.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO24.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO25.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO26.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO27.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO28.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO29.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO30.
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GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
SIGNAL NAME
EMU33
3
HYPLNK0RXN0
HYPLNK0RXN1
HYPLNK0RXN2
HYPLNK0RXN3
HYPLNK0RXP0
HYPLNK0RXP1
HYPLNK0RXP2
HYPLNK0RXP3
HYPLNK0TXN0
HYPLNK0TXN1
HYPLNK0TXN2
HYPLNK0TXN3
HYPLNK0TXP0
HYPLNK0TXP1
HYPLNK0TXP2
HYPLNK0TXP3
AM8
AN6
AM5
AL9
AK8
AL6
AK5
AN8
AM7
AN5
AM4
AN9
AL8
AK7
AL5
AK4
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
BALL NO.
TYPE
AD30 IOZ
IPD/IPU
Down
DESCRIPTION
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO31.
General Purpose Input/Output (GPIO)
AB33
AB31
AC29
AC33
AD29
AC31
AC32
Y32
AA30
Y33
Y31
AA33
AB32
AB30
AC30
AD32
AD33
AD31
AE33
AD30
V30
AA29
Y29
V33
V32
W30
W32
V31
W31
W33
AB29
Y30
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Up
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
GPIOs
GPIOs
HyperLink
O
O
O
I
O
I
I
I
I
I
I
I
O
O
O
O
HyperLink receive data
HyperLink transmit data
32
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SCL0
SCL1
SCL2
SDA0
SDA1
SDA2
SIGNAL NAME
HYPLNK0RXFLCLK
HYPLNK0RXFLDAT
HYPLNK0RXPMCLK
HYPLNK0RXPMDAT
HYPLNK0TXFLCLK
HYPLNK0TXFLDAT
HYPLNK0TXPMCLK
HYPLNK0TXPMDAT
HYPLNK0REFRES
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
DESCRIPTION BALL NO.
TYPE
AJ3 O
AE3 O
AE1
AD1
AC6
I
I
I
AH4
AB6
AF5
AJ5
O
A
I
O
IPD/IPU
down down down down down down down down
HyperLink sideband signals
TCK
TDI
TDO
TMS
TRST
MDCLK0
MDIO0
XFIMDCLK
XFIMDIO
PCIE0REFRES
PCIE0RXN0
PCIE0RXP0
PCIE0RXN1
PCIE0RXP1
PCIE0TXN0
PCIE0TXP0
PCIE0TXN1
PCIE0TXP1
PCIE1REFRES
PCIE1RXN0
PCIE1RXP0
PCIE1RXN1
PCIE1RXP1
PCIE1TXN0
PCIE1TXP0
PCIE1TXN1
PCIE1TXP1
AG30
AH30
AH31
AG28
AJ32
AG29
AJ33
AG31
AF29
AH32
AG32
AH6
AH5
AF6
AE7
AL17
AK17
AK16
AJ10
AN14
AN15
AG14
AN17
AN18
AM16
AM17
AL18
AM13
AM14
AL15
AL14
AK14
AK13
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
I
I
A
O
O
O
I
O
I
I
I
A
O
O
I
I
O
O
O
IOZ
O
IOZ
I
I
I
I
OZ
Up
Up
Up
Up
Down
Down
Up
Down
Up
HyperLink SerDes reference resistor input (3 k Ω ±1%)
I
2
C
I
2
C0 clock
I
2
C1 clock
I
2
C2 clock
I
2
C0 data
I
2
C1 data
I
2
C2 data
JTAG
JTAG clock input
JTAG data input
JTAG data output
JTAG test mode input
JTAG reset
MDIO
MDIO0 Clock
MDIO0 Data
XFI MDIO Clock
XFI MDIO Data
PCIe
PCIexpress0 SerDes reference resistor input (3 k Ω ±1%)
PCIexpress0 lane 0 receive data
PCIexpress0 lane 1 receive data
PCIexpress0 lane 0 transmit data
PCIexpress0 lane 1 transmit data
PCIexpress1 SerDes reference resistor input (3 k Ω ±1%)
PCIexpress1lane 0 receive data
PCIexpress1lane 1 receive data
PCIexpress1 lane 0 transmit data
PCIexpress1 lane 1 transmit data
SGMII00REFRES
SGMII01REFRES
SGMII0RXN0
SGMII0RXP0
AJ27
AJ22
AN29
AN30 I
I
A
A
SGMII
SGMII0 SerDes reference resistor input (3 k Ω ±1%)
SGMII1 SerDes reference resistor input (3 k Ω ±1%)
Ethernet MAC SGMII0 port 0 receive data
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VCL
VCNTL0
VCNTL1
VCNTL2
VCNTL3
VCNTL4
VCNTL5
VD
SGMII0RXN7
SGMII0RXP7
SGMII0TXN0
SGMII0TXP0
SGMII0TXN1
SGMII0TXP1
SGMII0TXN2
SGMII0TXP2
SGMII0TXN3
SGMII0TXP3
SGMII0TXN4
SGMII0TXP4
SGMII0TXN5
SIGNAL NAME
SGMII0RXN1
SGMII0RXP1
SGMII0RXN2
SGMII0RXP2
SGMII0RXN3
SGMII0RXP3
SGMII0RXN4
SGMII0RXP4
SGMII0RXN5
SGMII0RXP5
SGMII0RXN6
SGMII0RXP6
SGMII0TXP5
SGMII0TXN6
SGMII0TXP6
SGMII0TXN7
SGMII0TXP7
SPI0CLK
SPI0DIN
SPI0DOUT
SPI0SCS0
SPI0SCS1
SPI0SCS2
SPI0SCS3
SPI1CLK
SPI1DIN
SPI1DOUT
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
IPD/IPU DESCRIPTION
AL26
AK26
AK25
AL24
AL23
AK23
AM19
AM20
AL30
AL29
AK29
AK28
AL27
AM26
AN23
AN24
AM22
AM23
AN20
AN21
BALL NO.
TYPE
AM28 I
AM29 I
AN26
AN27
AM25
I
I
I
I
I
I
I
I
I
I
AK22
AL21
AL20
AK20
AK19
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
Ethernet MAC SGMII0 port 1 receive data
Ethernet MAC SGMII0 port 2 receive data
Ethernet MAC SGMII0 port 3 receive data
Ethernet MAC SGMII1 port 4 receive data
Ethernet MAC SGMII1 port 5 receive data
Ethernet MAC SGMII1 port 6 receive data
Ethernet MAC SGMII1 port 7 receive data
Ethernet MAC SGMII0 port 0 transmit data
Ethernet MAC SGMII0 port 1 transmit data
Ethernet MAC SGMII0 port 2 transmit data
Ethernet MAC SGMII0 port 3 transmit data
Ethernet MAC SGMII1 port 4 transmit data
Ethernet MAC SGMII1 port 5 transmit data
Ethernet MAC SGMII1 port 6 transmit data
Ethernet MAC SGMII1 port 7 transmit data
SmartReflex
Voltage control I
2
C clock
V29
H29
G33
H31
H30
G32
J31
U30
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
IOZ
Voltage control outputs to variable core power supply
M30
M31
N29
L31
M29
L29
L32
M33
R30
P32
I
OZ
OZ
OZ
OZ
OZ
OZ
OZ
I
OZ
Down
Down
Down
Up
Up
Up
Up
Down
Down
Down
Voltage control I
2
C data
SPI0
SPI0 clock
SPI0 data in
SPI0 data out
SPI0 interface enable 0
SPI0 interface enable 1
SPI0 interface enable 2
SPI0 interface enable 3
SPI1
SPI1 clock
SPI1 data in
SPI1 data out
34
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SIGNAL NAME
SPI1SCS0
SPI1SCS1
SPI1SCS2
SPI1SCS3
SPI2CLK
SPI2DIN
SPI2DOUT
SPI2SCS0
SPI2SCS1
SPI2SCS2
SPI2SCS3
TSCOMPOUT
TSPUSHEVT0
TSPUSHEVT1
TSSYNCEVT
TIMI0
TIMO0
TIMI1
TIMO1
TSIP0CLKA
TSIP0CLKB
TSIP0FSA
TSIP0FSB
TSIP0TR0
TSIP0TR1
TSIP0TX0
TSIP0TX1
UART0CTS
UART0DSR
UART0DTR
UART0RTS
UART0RXD
UART0TXD
UART1CTS
UART1RTS
UART1RXD
UART1TXD
USB0DM
USB0DP
USB0DRVVBUS
USB0ID0
USB0RESREF
USB0RX0M
USB0RX0P
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
K33
K31
K32
K30
L33
P30
R31
P31
R29
P33
L30
BALL NO.
TYPE
P29 OZ
M32 OZ
N30
N33
OZ
OZ
AF4
AG3
AL1
AE5
AK31
AK33
AJ31
AK32
AM31
AL33
AL32
AM32
I
I
I
I
I
I
OZ
OZ
I
I
OZ
OZ
I
OZ
OZ
OZ
OZ
OZ
OZ
I
O
I
O
IPD/IPU
Up
Up
Up
Up
Down
Down
Down
Down
Down
Down
Down
Down
Up
Up
Up
Down
Down
Down
Up
Down
Down
Down
Down
Down
Down
Down
Down
DESCRIPTION
SPI1 interface enable 0
SPI1 interface enable 1
SPI1 interface enable 2
SPI1 interface enable 3
SPI2
SPI2 clock
SPI2 data in
SPI2 data out
SPI2 interface enable 0
SPI2 interface enable 1
SPI2 interface enable 2
SPI2 interface enable 3
Sync-Ethernet / IEEE1588
IEEE1588 compare output
PPS push event from GPS for IEEE1588
Push event from BCN for IEEE1588
IEEE1588 sync event output
Timer
Timer 0 input
Timer 0 output
Timer 1 input
Timer 1 output
TSIP
CLKA0 TSIP0 external clock A
CLKB0 TSIP0 external clock B
FSA0 TSIP0 frame sync A
FSB0 TSIP0 frame sync B
TR00 TR01 TSIP0 receive data
TX00 TX01 TSIP0 transmit data
T31
T33
U29
T32
W3
V3
AB1
W4
Y6
T1
U1
R33
W29
U33
R32
T29
T30
I
I
IOZ
A
A
IOZ
O
I
I
OZ
OZ
I
I
OZ
I
OZ
OZ
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
UART0
UART0 clear to send
UART0 data set ready
UART0 data terminal ready
UART0 request to send
UART0 serial data in
UART0 serial data out
UART1
UART1 clear to send
UART1 request to send
UART1 serial data in
UART1 serial data out
USB0 (USB_3.0)
USB0 D-
USB0 D+
USB0 DRVVBUS output
USB0 ID
Reference resistor connection for USB0 PHY (200 Ω +- 1% resistor to ground)
USB0_3.0 receive data
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SIGNAL NAME
USB0TX0M
USB0TX0P
USB0VBUS
USB1DM
USB1DP
USB1DRVVBUS
USB1ID0
USB1RESREF
USB1RX0M
USB1RX0P
USB1TX0M
USB1TX0P
USB1VBUS
USIMCLK
USIMIO
USIMRST
XFIRXN0
XFIRXP0
XFIRXN1
XFIRXP1
XFITXN0
XFITXP0
XFITXN1
XFITXP1
XFIREFRES0
XFIREFRES1
AN11
AN12
AM10
AM11
AL12
AL11
AK11
AK10
AG10
AH7
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
IPD/IPU DESCRIPTION BALL NO.
TYPE
U2 O
V2 O
W5 A
USB0_3.0 transmit data
N1
P1
R2
P2
V4
P4
R4
AC1
W6
V5
I
I
O
O
A
IOZ
A
A
IOZ
O Down
USB0 5-V analog input. Connect to VBUS pin on USB connector through protection switch
USB1 (USB_3.0)
USB1 D-
USB1 D+
USB1 DRVVBUS output
USB1 ID
Reference resistor connection for USB1 PHY (200 Ω +- 1% resistor to ground)
USB1_3.0 receive data
USB1_3.0 transmit data
J33
H33
K29
OZ
IOZ
OZ
Down
Up
Down
USB1 5-V analog input. Connect to VBUS pin on USB connector through protection switch
USIM
USIM clock
USIM data
USIM reset
XFI (AM5K2E04 only)
I
O
O
I
I
I
A
A
O
O
Ethernet MAC XFI port 0 receive data
Ethernet MAC XFI port 1 receive data
Ethernet MAC XFI port 0 transmit data
Ethernet MAC XFI port 1 transmit data
XFI port 0 SerDes reference resistor input (3 k Ω ±1%)
XFI port 1 SerDes reference resistor input (3 k Ω ±1%)
36
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SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
RSV011
RSV012
RSV013
RSV014
RSV015
RSV016
RSV017
RSV018
RSV019
RSV020
RSV021
RSV022
RSV023
RSV028
RSV029
RSV030
RSV000
RSV001
RSV002
RSV003
RSV004
RSV005
RSV006
RSV007
RSV008
RSV009
RSV010
SIGNAL NAME
AJ28
AJ26
AH9
B19
E20
A14
W8
W7
J30
J29
AG8
AJ20
AG12
AG33
AF33
AE30
H32
J32
AE2
AF2
G2
G1
AL3
AL2
AG5
K8
J8
I
I
I
A
A
A
OZ
OZ
A
A
A
A
A
A
A
A
O
O
O
O
OZ
A
A
OZ
OZ
O
O
Table 5-2. Terminal Functions — Signals and Control by Function (continued)
BALL NO.
TYPE IPD/IPU
Down
Down
Down
DESCRIPTION
Reserved
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Connect to GND
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
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SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
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SUPPLY
AVDDA1
AVDDA2
AVDDA3
AVDDA6
AVDDA7
AVDDA8
AVDDA9
AVDDA10
CVDD
CVDD1
CVDDCMON
CVDDTMON
DDR3VREFSSTL
DVDD15
DVDD18
USB0DVDD33
USB0VP
USB0VPH
USB0VPTX
USB1DVDD33
USB1VP
USB1VPH
USB1VPTX
VDDAHV
VDDALV
VDDUSB0
VDDUSB1
VNWA1
VNWA2
VNWA3
VNWA4
VPP0
VPP1
Table 5-3. Terminal Functions — Power and Ground
BALL NO.
AF7
K7
AD7
G8
E14
VOLTS
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
G16
G22
G24
J12, J14, J16, J18, J20, J22, J26, K11, K13, K15, K17, K19,
K21, K23, K25, L10, L12, L14, L16, L18, L20, L22, M15, M17,
M19, M21, M25, N10, N14, N16, N18, N20, N22, N26, P13,
P15, P17, P19, P21, P23, P25, R14, R16, R18, R20, R22, R24,
R26, T13, T15, T17, T19, T21, T23, T25, U12, U14, U16, U18,
U20, U22, U24, U26, V13, V15, V17, V19, V21, V23, V25, W12,
W14, W16, W18, W20, W22, W24, W26, Y9, Y15, Y17, Y19,
Y21, Y25, AA10, AA16, AA18, AA20, AA22, AA26, AB9, AB11,
AB13, AB15, AB17, AB19, AB21, AB25, AC10, AC12, AC14,
AC16, AC18, AC20, AC22, AC24, AC26, AD11, AD13, AD15,
AD17, AD19, AD21, AD25
AVS
L24, M11, M13, M23, N12, N24, Y13, Y23, AA12, AA14, AA24, 0.95 V
AB23
J10 AVS
L26
F15
A2, A32, B1, B33, C3, C7, C11, C17, C21, C25, C31, D5, D9,
D14, D19, D23, D27, D29, F5, F7, F9, F11, F13, F17, F19, F21,
F23, F25, F27, F29, G10, G14, G20, G26, G28, G30, H7, H9,
H11, H13, H15, H17, H19, H21, H23, H25, H27
J2, J28, K27, L8, L28, M2, M7, M27, N8, N28, N31, P7, P27,
R28, T7, T27, U28, U31, V7, V27, W28, Y7, Y27, AA3, AA8,
AA28, AA31, AB7, AB27, AC8, AC28, AD4, AD27, AE8, AE26,
AE28, AE31, AF27, AG26, AH27, AJ30, AM33, AN32
1.8 V
1.8 V
1.8 V
AVS
DVDD15/2
1.5 V/1.35 V
1.8 V
Y11
U8
3.3 V
0.85 V
DESCRIPTION
COREPLL supply
NETCPPLL supply
DDRPLL supply
DDRA DLL supply
DDRA DLL supply
DDRA DLL supply
DDRA DLL supply
DDRA DLL supply
Smart Reflex core supply voltage
Core supply voltage for memory array
CVDD Supply Monitor
CVDD Supply Monitor
DDR3 reference voltage
DDR IO supply
1.8-V IO supply
W10
V9
P11
R8
3.3 V
0.85 V
3.3 V
0.85 V
3.3 V
0.85 V
1.8 V
0.85 V
3.3-V USB0 high supply High-speed
0.85-V USB0 PHY analog and digital Super-speed supply
3.3-V USB0 high supply Super-speed
0.85-V USB0 PHY transmit supply
3.3-V USB1 high supply High-speed
0.85-V USB1 PHY analog and digital Super-speed supply
3.3-V USB1 high supply Super-speed
0.85-V USB1 PHY transmit supply
1.8-V high analog supply
SerDes low voltage
R10
T9
AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25
AE10, AE12, AE14, AE16, AE18, AE20, AE22, AE24, AF9,
AF11, AF13, AF15, AF17, AF19, AF21, AF23, AF25, AG16,
AG18, AG20, AG22, AG24
U10, V11
R12, T11
P9
J24
AD23
AD9
K9
M9
0.85 V
0.85 V
0.95 V
0.95 V
0.95 V
0.95 V
USB0 PHY analog and digital High-speed supply
USB1 PHY analog and digital High-speed supply
Fixed Nwell supply - connect to CVDD1
Fixed Nwell supply - connect to CVDD1
Fixed Nwell supply - connect to CVDD1
Fixed Nwell supply - connect to CVDD1
Leave unconnected
Leave unconnected
38
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SUPPLY
VSS
VSSCMON
VSSTMON
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 5-3. Terminal Functions — Power and Ground (continued)
BALL NO.
VOLTS
A1, A33, C5, C9, C14, C19, C23, C27, C29, D3, D7, D11, D17, GND
D21, D25, D31, F4, F6, F8, F10, F12, F14, F16, F18, F20, F22,
F24, F26, F28, F30, G7, G9, G11, G13, G15, G17, G19, G21,
G23, G25, G27, G29, G31, H8, H10, H12, H14, H16, H18, H20,
H22, H24, H26, H28, J3, J7, J11, J13, J15, J17, J19, J21, J23,
J25, J27, K10, K12, K14, K16, K18, K20, K22, K24, K28, L7,
L9, L11, L13, L15, L17, L19, L21, L23, L25, L27, M1, M8, M10,
M12, M14, M16, M18, M20, M22, M24, M26, M28, N2, N7, N9,
N11, N13, N15, N17, N19, N21, N23, N25, N27, N32, P8, , P10,
P12, P14, P16, P18, P20, P22, P24, P26, P28, R1, R7, R9,
R11, R13, R15, R17, R19, R21, R23, R25, R27, T2, T8, T10,
T12, T14, T16, T18, T20, T22, T24, T26, T28, U3, U7, U9, U11,
U13, U15, U17, U19, U21, U23, U25, U27, U32, V1, V8, V10,
V12, V14, V16, V18, V20, V22, V24, V26, V28, W2, W9, W11,
W13, W15, W17, W19, W21, W23, W25, W27, Y8, Y10, Y12,
Y14, Y16, Y18, Y20, Y22, Y24, Y26, Y28, AA4, AA7, AA9,
AA11, AA13, AA15, AA17, AA19, AA21, AA23, AA25, AA27,
AA32, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22,
AB24, AB26, AB28, AC7, AC9, AC11, AC13, AC15, AC17,
AC19, AC21, AC23, AC25, AC27, AD5, AD8, AD10, AD12,
AD14, AD16, AD18, AD20, AD22, AD24, AD26, AD28, AE9,
AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE25, AE27,
AE32, AF8, AF10, AF12, AF14, AF16, AF18, AF20, AF22,
AF24, AF26, AF28, AG7, AG9, AG11, AG13, AG15, AG17,
AG19, AG21, AG23, AG25, AG27, AH8, AH10, AH12, AH14,
AH16, AH18, AH20, AH22, AH24, AH26, AH28, AJ4, AJ6, AJ9,
AJ13, AJ16, AJ19, AJ21, AJ23, AJ29, AK3, AK6, AK9, AK12,
AK15, AK18, AK21, AK24, AK27, AK30, AL4, AL7, AL10, AL13,
AL16, AL19, AL22, AL25, AL28, AL31, AM1, AM3, AM6, AM9,
AM12, AM15, AM18, AM21, AM24, AM27, AM30, AN1, AN2,
AN4, AN7, AN10, AN13, AN16, AN19, AN22, AN25, AN28,
AN31, AN33
J9 GND
K26 GND
DESCRIPTION
Ground
GND Monitor
GND Monitor
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 5-4. Terminal Functions — By Signal Name www.ti.com
40
Terminals
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SIGNAL NAME
BOOTMODE_RSVD
2
AVDDA1
AVDDA2
AVDDA3
AVDDA6
AVDDA7
AVDDA8
AVDDA9
AVDDA10
AVSIFSEL[0]
2
AVSIFSEL[1]
2
BOOTCOMPLETE
BOOTMODE00
2
BOOTMODE01
2
BOOTMODE02
2
BOOTMODE03
2
BOOTMODE04
2
BOOTMODE05
2
BOOTMODE06
2
BOOTMODE07
2
BOOTMODE08
2
BOOTMODE09
2
BOOTMODE10
2
BOOTMODE11
2
BOOTMODE12
2
BOOTMODE13
2
BOOTMODE14
2
BOOTMODE15
2
CORECLKN
CORECLKP
CVDD
CVDD
CVDD
CVDD
CVDD1
CVDDCMON
CVDDTMON
DDRA00
DDRA01
K32
AF31
AA29
Y29
V33
BALL NUMBER
Y31
E14
G16
G22
G24
K33
AF7
K7
AD7
G8
W33
AB29
Y30
Y32
AA30
V32
W30
W32
V31
W31
DDRBA1
DDRBA2
DDRCAS
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRCB04
DDRCB05
DDRCB06
AA33
AB32
AB33
DDRCB07
DDRCE0
DDRCE1
J10
L26
D15
C15
AG1
AF1
DDRCKE0
DDRCKE1
J12, J14, J16, J18, J20, J22,
J26, K11, K13, K15, K17, K19,
K21, K23, K25, L10, L12, L14,
L16, L18, L20, L22, M15, M17,
M19, M21, M25, N10, N14, N16,
N18, N20, N22
N26, P13, P15, P17, P19, P21,
P23, P25, R14, R16, R18, R20,
R22, R24, R26, T13, T15, T17,
T19, T21, T23, T25, U12, U14,
U16, U18, U20, U22, U24, U26,
V13, V15
V17, V19, V21, V23, V25, W12,
W14, W16, W18, W20, W22,
W24, W26, Y9, Y15, Y17, Y19,
Y21, Y25, AA10, AA16, AA18,
AA20, AA22, AA26, AB9, AB11,
AB13, AB15
DDRCLKN
DDRCLKOUTN0
DDRCLKOUTN1
DDRCLKOUTP0
DDRCLKOUTP1
DDRCLKP
DDRD00
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
AB17, AB19, AB21, AB25, AC10, DDRD06
AC12, AC14, AC16, AC18,
AC20, AC22, AC24, AC26,
DDRD07
AD11, AD13, AD15, AD17,
DDRD08
AD19, AD21, AD25
DDRD09 L24, M11, M13, M23, N12, N24,
Y13, Y23, AA12, AA14, AA24,
AB23
DDRD10
DDRD11
DDRD12
DDRD13
DDRD14
SIGNAL NAME
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDRA08
DDRA09
DDRA10
DDRA11
DDRA12
DDRA13
DDRA14
DDRA15
DDRBA0
A6
B5
E5
C4
D4
E4
E22
E21
C22
B21
A20
C13
B18
B12
A23
D22
A21
A12
C12
F2
E1
F1
D2
F3
B2
A5
A16
G4
E2
D1
C20
A19
G3
B14
A15
B15
E18
E12
C18
E19
D13
BALL NUMBER
B16
E17
A18
B17
A13
D18
C16
D16
E16
A17
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD39
DDRD40
DDRD41
DDRD42
DDRD43
DDRD44
DDRD45
DDRD46
DDRD47
DDRD48
DDRD49
DDRD50
DDRD51
DDRD52
DDRD53
DDRD54
DDRD55
DDRD56
DDRD57
DDRD58
DDRD59
SIGNAL NAME
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD60
DDRD61
DDRD62
DDRD63
DDRDQM0
DDRDQM1
E33
C32
D32
B32
A3
E3
C24
E24
E25
B25
A25
E9
A9
B23
E23
D24
E28
D28
C28
C30
E30
D30
F31
A28
B31
E29
B29
F33
F32
E32
E27
B28
A26
B26
C26
A29
B11
A11
C10
D10
B9
BALL NUMBER
B3
C6
C8
A8
B8
E10
D6
E6
E7
B6
Terminals
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DDRDQS6P
DDRDQS7N
DDRDQS7P
DDRDQS8N
DDRDQS8P
DDRODT0
DDRODT1
DDRRAS
DDRRESET
DDRRZQ0
DDRRZQ1
DDRRZQ2
DDRVREFSSTL
DDRWE
DVDD15
SIGNAL NAME
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
DDRDQS0N
DDRDQS0P
DDRDQS1N
DDRDQS1P
DDRDQS2N
DDRDQS2P
DDRDQS3N
DDRDQS3P
DDRDQS4N
DDRDQS4P
DDRDQS5N
DDRDQS5P
DDRDQS6N
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
DVDD15
DVDD18
DVDD18
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
A24
B27
A27
B30
A4
A7
B7
B10
A10
D26
E31
A31
B20
C2
C1
B4
BALL NUMBER
D8
E8
E26
B24
A30
D33
C33
A22
B22
EMIFBE1
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
D12
E11
B13
D20
EMIFD00
EMIFD01
EMIFD02
E15
G12
G18
F15
E13
A2, A32, B1, B33, C3, C7, C11,
C17, C21, C25, C31, D5, D9,
D14, D19, D23, D27, D29, F5,
F7, F9, F11, F13, F17, F19, F21
F23, F25, F27, F29, G10, G14,
G20, G26, G28, G30, H7, H9,
H11, H13, H15, H17, H19, H21,
H23, H25, H27
J2, J28, K27, L8, L28, M2, M7,
M27, N8, N28, N31, P7, P27,
R28, T7, T27, U28, U31, V7,
V27, W28, Y7, Y27, AA3, AA8
P3
P5
U6
V6
P6
AA28, AA31, AB7, AB27, AC8,
AC28, AD4, AD27, AE8, AE26,
AE28, AE31, AF27, AG26, AH27,
AJ30, AM33, AN32
EMIFD03
EMIFD15
EMIFOE
EMIFRW
EMIFWAIT0
EMIFWAIT1
EMIFWE
EMU00
EMU01
EMU02
EMU03
EMU04
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
SIGNAL NAME
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFBE0
G5
K3
K4
J1
R5
AC5
AA6
AC4
AE6
AD6
J5
Y2
Y3
T6
N3
H2
G6
K5
H3
J4
H4
K6
H5
J6
H6
H1
R6
AA1
Y4
W1
Y1
L4
R3
L6
AA2
T3
L2
L5
M6
K2
N5
M5
M4
L1
U5
T5
L3
BALL NUMBER
N6
M3
N4
K1
AD33
AD31
AE33
AD30
AA33
AB32
AB33
AB31
AC29
AC33
Y30
Y32
AA30
Y33
Y31
V30
AA29
Y29
V33
V32
W30
W32
V31
W31
W33
AB29
AC31
AC32
AB30
AC30
AD32
AA5
AB2
Y5
AH2
AB32
BALL NUMBER
AD3
AB5
AC3
AB4
AH3
AF3
AG4
AD2
AC2
AB3
AB33
AB31
AC29
AC33
AD29
www.ti.com
EMU23
3
EMU24
3
EMU25
3
EMU26
3
EMU27
3
EMU28
3
EMU29
3
EMU30
3
EMU31
3
EMU32
3
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
EMU33
3
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
SIGNAL NAME
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
EMU19
3
EMU20
3
EMU21
3
EMU22
3
42
Terminals
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Y33
AH6
AH5
AN3
AM2
AG6
AJ18
AJ17
AG14
AN17
AM16
AN18
AL6
AK5
AL8
AK7
AL5
AK4
AB6
AF5
V30
AD1
AC6
AH4
AL9
AK8
AN9
AM8
AN6
AM5
AE1
AE3
AN8
AM7
AN5
AM4
AF30
AJ8
AJ7
AJ5
AJ3
BALL NUMBER
AD29
AC31
AC32
AB30
AC30
AD32
AD33
AD31
AE33
AD30
HYPLNK0RXP0
HYPLNK0RXP1
HYPLNK0RXP2
HYPLNK0RXP3
HYPLNK0RXPMCLK
HYPLNK0RXPMDAT
HYPLNK0TXFLCLK
HYPLNK0TXFLDAT
HYPLNK0TXN0
HYPLNK0TXN1
HYPLNK0TXN2
HYPLNK0TXN3
HYPLNK0TXP0
HYPLNK0TXP1
HYPLNK0TXP2
HYPLNK0TXP3
HYPLNK0TXPMCLK
HYPLNK0TXPMDAT
SIGNAL NAME
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
HOUT
HYPLNK0CLKN
HYPLNK0CLKP
HYPLNK0REFRES
HYPLNK0RXFLCLK
HYPLNK0RXFLDAT
HYPLNK0RXN0
HYPLNK0RXN1
HYPLNK0RXN2
HYPLNK0RXN3
LENDIAN
2
MAINPLLODSEL
2
MDCLK0
MDIO0
NETCPCLKN
NETCPCLKP
NETCPCLKSEL
PCIE0CLKN
PCIE0CLKP
PCIE0REFRES
PCIE0RXN0
PCIE0RXN1
PCIE0RXP0
AJ26
AH9
B19
E20
A14
AG33
AF33
AE30
AG30
AH30
AH31
AG28
J8
W8
W7
J30
J29
AG8
AJ20
AG12
AJ28
G1
AL3
AL2
AG5
K8
H32
J32
AE2
AF2
G2
AN15
AM14
AL15
AK14
AL14
AK13
AH33
AF32
AH29
AE29
BALL NUMBER
AM17
AL18
AK17
AL17
AK16
AJ15
AJ14
AJ10
AN14
AM13
RSV019
RSV020
RSV021
RSV022
RSV023
RSV028
RSV029
RSV030
SCL0
SCL1
SCL2
SDA0
RSV010
RSV011
RSV012
RSV013
RSV014
RSV015
RSV016
RSV017
RSV018
RSV000
RSV001
RSV002
RSV003
RSV004
RSV005
RSV006
RSV007
RSV008
RSV009
SIGNAL NAME
PCIE0RXP1
PCIE0TXN0
PCIE0TXN1
PCIE0TXP0
PCIE0TXP1
PCIE1CLKN
PCIE1CLKP
PCIE1REFRES
PCIE1RXN0
PCIE1RXN1
PCIE1RXP0
PCIE1RXP1
PCIE1TXN0
PCIE1TXN1
PCIE1TXP0
PCIE1TXP1
POR
RESETFULL
RESETSTAT
RESET
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
SPI0DIN
SPI0DOUT
SPI0SCS0
SPI0SCS1
SPI0SCS2
SPI0SCS3
SPI1CLK
SPI1DIN
SPI1DOUT
SPI1SCS0
SPI1SCS1
SPI1SCS2
SGMII0RXP6
SGMII0RXP7
SGMII0TXN0
SGMII0TXN1
SGMII0TXN2
SGMII0TXN3
SGMII0TXN4
SGMII0TXN5
SGMII0TXN6
SGMII0TXN7
SGMII0TXP0
SGMII0TXP1
SGMII0TXP2
SGMII0TXP3
SGMII0TXP4
SGMII0TXP5
SGMII0TXP6
SGMII0TXP7
SPI0CLK
SIGNAL NAME
SDA1
SDA2
SGMII00REFRES
SGMII01REFRES
SGMII0CLKN
SGMII0CLKP
SGMII0RXN0
SGMII0RXN1
SGMII0RXN2
SGMII0RXN3
SGMII0RXN4
SGMII0RXN5
SGMII0RXN6
SGMII0RXN7
SGMII0RXP0
SGMII0RXP1
SGMII0RXP2
SGMII0RXP3
SGMII0RXP4
SGMII0RXP5
M31
M33
R30
P32
P29
M32
N30
N29
L31
M29
L29
L32
AL29
AK28
AL26
AK25
AL23
AK22
AL20
AK19
M30
AK26
AL24
AK23
AL21
AK20
AN21
AM20
AL30
AK29
AL27
AN23
AM22
AN20
AM19
AN30
AM29
AN27
AM26
AN24
AM23
BALL NUMBER
AJ32
AG29
AJ27
AJ22
AJ25
AJ24
AN29
AM28
AN26
AM25
Terminals
43
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
SIGNAL NAME
SPI1SCS3
SPI2CLK
SPI2DIN
SPI2DOUT
SPI2SCS0
SPI2SCS1
SPI2SCS2
SPI2SCS3
SYSCLKOUT
TCK
TDI
TDO
TIMI0
TIMI1
TIMO0
TIMO1
TMS
TRST
TSCOMPOUT
TSIP0CLKA
TSIP0CLKB
TSIP0FSA
TSIP0FSB
TSIP0TR0
TSIP0TR1
TSIP0TX0
TSIP0TX1
TSPUSHEVT0
TSPUSHEVT1
TSREFCLKN
TSREFCLKP
TSRXCLKOUT0N
AK33
AJ31
AK32
AM31
AL33
AL32
AM32
AG3
AL1
AK1
AK2
AJ2
AG31
AF29
K33
K32
K31
K30
AH32
AG32
AF4
AK31
BALL NUMBER
N33
L33
P30
R31
P31
R29
P33
L30
AE4
AJ33
SIGNAL NAME
TSRXCLKOUT0P
TSRXCLKOUT1N
TSRXCLKOUT1P
TSSYNCEVT
UART0CTS
UART0DSR
UART0DTR
UART0RTS
UART0RXD
UART0TXD
UART1CTS
UART1RTS
UART1RXD
UART1TXD
USB0DM
USB0DP
USB0DRVVBUS
USB0DVDD33
USB0ID0
USB0RESREF
USB0RX0M
USB0RX0P
USB0TX0M
USB0TX0P
USB0VBUS
USB0VP
USB0VPH
USB0VPTX
USB1DM
USB1DP
USB1DRVVBUS
USB1DVDD33
USB1ID0
U8
W10
V9
P4
R4
T1
U1
U2
V2
W5
AC1
P11
W6
V3
AB1
Y11
W4
Y6
T31
T33
U29
T32
W3
BALL NUMBER
AJ1
AH1
AG2
AE5
R33
W29
U33
R32
T29
T30
USBCLKP
USIMCLK
USIMIO
USIMRST
VCL
VCNTL0
VCNTL1
VCNTL2
VCNTL3
VCNTL4
VCNTL5
VD
VDDAHV
SIGNAL NAME
USB1RESREF
USB1RX0M
USB1RX0P
USB1TX0M
USB1TX0P
USB1VBUS
USB1VP
USB1VPH
USB1VPTX
USBCLKM
VDDALV
VDDUSB0
VDDUSB1
VNWA1
VNWA2
www.ti.com
R2
P2
V4
R8
R10
T9
T4
BALL NUMBER
V5
N1
P1
H29
G33
H31
H30
G32
U4
J33
H33
K29
V29
J31
U30
AH11, AH13, AH15, AH17,
AH19, AH21, AH23, AH25
AE10, AE12, AE14, AE16, AE18,
AE20, AE22, AE24, AF9, AF11,
AF13, AF15, AF17, AF19, AF21,
AF23, AF25, AG16, AG18,
AG20, AG22, AG24
U10, V11
R12, T11
P9
J24
44
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SIGNAL NAME
VNWA3
VNWA4
VPP0
VPP1
VSS
VSS
VSS
VSS
VSS
BALL NUMBER
AD23
AD9
K9
M9
SIGNAL NAME
VSS
A1, A33, C5, C9, C14, C19, C23, VSS
C27, C29, D3, D7, D11, D17,
D21, D25, D31, F4, F6, F8, F10,
F12, F14, F16, F18, F20, F22,
F24, F26, F28, F30, G7, G9,
G11, G13, G15, G17
VSS G19, G21, G23, G25, G27, G29,
G31, H8, H10, H12, H14, H16,
H18, H20, H22, H24, H26, H28,
J3, J7, J11, J13, J15, J17, J19,
J21, J23, J25, J27, K10, K12,
K14, K16, K18
K20, K22, K24, K28, L7, L9, L11, VSS
L13, L15, L17, L19, L21, L23,
L25, L27, M1, M8, M10, M12,
M14, M16, M18, M20, M22, M24,
M26, M28, N2, N7, N9, N11,
N13, N15, N17
VSS N19, N21, N23, N25, N27, N32,
P8, P10, P12, P14, P16, P18,
P20, P22, P24, P26, P28, R1,
R7, R9, R11, R13, R15, R17,
R19, R21, R23, R25, R27, T2,
T8, T10, T12, T14
T16, T18, T20, T22, T24, T26,
T28, U3, U7, U9, U11, U13, U15,
U17, U19, U21, U23, U25, U27,
U32, V1, V8, V10, V12, V14,
V16, V18, V20, V22, V24, V26,
V28, W2, W9
VSS
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
BALL NUMBER
W11, W13, W15, W17, W19,
W21, W23, W25, W27, Y8, Y10,
Y12, Y14, Y16, Y18, Y20, Y22,
Y24, Y26, Y28, AA4, AA7, AA9,
AA11, AA13, AA15, AA17, AA19,
AA21, AA23
AA25, AA27, AA32, AB8, AB10,
AB12, AB14, AB16, AB18, AB20,
AB22, AB24, AB26, AB28, AC7,
AC9, AC11, AC13, AC15, AC17,
AC19, AC21, AC23, AC25
AC27, AD5, AD8, AD10, AD12,
AD14, AD16, AD18, AD20,
AD22, AD24, AD26, AD28, AE9,
AE11, AE13, AE15, AE17, AE19,
AE21, AE23, AE25, AE27, AE32
AF8, AF10, AF12, AF14, AF16,
AF18, AF20, AF22, AF24, AF26,
AF28, AG7, AG9, AG11, AG13,
AG15, AG17, AG19, AG21,
AG23, AG25, AG27, AH8, AH10
AH12, AH14, AH16, AH18,
AH20, AH22, AH24, AH26,
AH28, AJ4, AJ6, AJ9, AJ13,
AJ16, AJ19, AJ21, AJ23, AJ29,
AK3, AK6, AK9, AK12, AK15,
AK18, AK21, AK24
AK27, AK30, AL4, AL7, AL10,
AL13, AL16, AL19, AL22, AL25,
AL28, AL31, AM1, AM3, AM6,
AM9, AM12, AM15, AM18,
AM21, AM24, AM27, AM30, AN1,
AN2
SIGNAL NAME
VSS
VSSCMON
VSSTMON
XFICLKN
XFICLKP
XFIMDCLK
XFIMDIO
XFIREFRES0
XFIREFRES1
XFIRXN0
XFIRXN1
XFIRXP0
XFIRXP1
XFITXN0
XFITXN1
XFITXP0
XFITXP1
BALL NUMBER
AN4, AN7, AN10, AN13, AN16,
AN19, AN22, AN25, AN28,
AN31, AN33
AE7
AG10
AH7
AN11
AM10
AN12
AM11
AL12
J9
K26
AJ12
AJ11
AF6
AK11
AL11
AK10
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Terminals
45
B5
B6
B7
B8
B9
A33
B1
B2
B3
B4
A28
A29
A30
A31
A32
A23
A24
A25
A26
A27
B15
B16
B17
B18
B19
B10
B11
B12
B13
B14
A18
A19
A20
A21
A22
A13
A14
A15
A16
A17
A6
A7
A8
A9
A10
A11
A12
BALL NUMBER
A1
A2
A3
A4
A5
DDRCB00
DDRDQS4P
DDRD39
DDRD45
DDRDQS5P
DDRD49
DDRD48
DDRDQS6P
DDRDQM7
DVDD15
VSS
DVDD15
DDRD07
DDRD15
DDRDQS1N
DDRD10
DDRD19
DDRDQS2P
DDRD23
DDRD29
SIGNAL NAME
VSS
DVDD15
DDRDQM0
DDRDQS1P
DDRD08
DDRD09
DDRDQS2N
DDRD22
DDRD31
DDRDQS3P
DDRD26
DDRCE0
DDRA10
RSV023
DDRCLKOUTN1
DDRCLKOUTP1
DDRA06
DDRA08
DDRCKE1
DDRCB06
DDRCB07
DDRDQS8N
DDRDQS3N
DDRD25
DDRCAS
DDRRAS
DDRCLKOUTN0
DDRCLKOUTP0
DDRA02
DDRA09
DDRBA2
RSV021
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 5-5. Terminal Functions — By Ball Number
C24
C25
C26
C27
C28
C19
C20
C21
C22
C23
C14
C15
C16
C17
C18
C9
C10
C11
C12
C13
D1
D2
D3
D4
D5
C29
C30
C31
C32
C33
C4
C5
C6
C7
C8
B32
B33
C1
C2
C3
B25
B26
B27
B28
B29
B30
B31
BALL NUMBER
B20
B21
B22
B23
B24
VSS
DDRCKE0
DVDD15
DDRCB04
VSS
DDRD35
DVDD15
DDRD47
VSS
DDRD42
VSS
DDRD27
DVDD15
DDRCE1
DDRBA1
VSS
DDRA01
DDRA03
DVDD15
DDRA14
SIGNAL NAME
DDRDQM8
DDRCB05
DDRDQS8P
DDRD32
DDRDQS4N
DDRD38
DDRD46
DDRDQS5N
DDRD44
DDRD52
DDRDQS6N
DDRD50
DDRD63
DVDD15
DDRDQS0P
DDRDQS0N
DVDD15
DDRD12
VSS
DDRD20
DVDD15
DDRD21
VSS
DDRD53
DVDD15
DDRD61
DDRDQS7P
DDRD01
DDRD05
VSS
DDRD13
DVDD15
E10
E11
E12
E13
E14
E5
E6
E7
E8
E9
D33
E1
E2
E3
E4
D28
D29
D30
D31
D32
E20
E21
E22
E23
E24
E15
E16
E17
E18
E19
D23
D24
D25
D26
D27
D18
D19
D20
D21
D22
D11
D12
D13
D14
D15
D16
D17
BALL NUMBER
D6
D7
D8
D9
D10
DDRRZQ0
DDRA05
DDRA07
DDRA12
DDRA15
RSV022
DDRCB03
DDRCB02
DDRD33
DDRD36
DDRD11
DDRD17
DDRD18
DDRDQM3
DDRD30
DDRD24
DDRODT1
DDRA13
DDRWE
AVDDA7
DDRD41
DVDD15
DDRD55
VSS
DDRD62
DDRDQS7N
DDRD03
DDRD00
DDRDQM1
DDRD14
SIGNAL NAME
DDRD16
VSS
DDRDQM2
DVDD15
DDRD28
VSS
DDRODT0
DDRBA0
DVDD15
DDRA00
DDRA04
VSS
DDRA11
DVDD15
DDRRESET
VSS
DDRCB01
DVDD15
DDRD34
VSS
DDRDQM5
DVDD15
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46
Terminals
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F28
F29
F30
F31
F32
F23
F24
F25
F26
F27
F18
F19
F20
F21
F22
F13
F14
F15
F16
F17
G5
G6
G7
G8
G9
G10
F33
G1
G2
G3
G4
F8
F9
F10
F11
F12
F3
F4
F5
F6
F7
E31
E32
E33
F1
F2
BALL NUMBER
E25
E26
E27
E28
E29
E30
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
H14
H15
H16
H17
H18
H9
H10
H11
H12
H13
H4
H5
H6
H7
H8
G32
G33
H1
H2
H3
H24
H25
H26
H27
H28
H29
H19
H20
H21
H22
H23
G27
G28
G29
G30
G31
G22
G23
G24
G25
G26
G17
G18
G19
G20
G21
BALL NUMBER
G11
G12
G13
G14
G15
G16
Table 5-5. Terminal Functions — By Ball Number (continued)
DDRD57
RSV005
RSV004
DDRCLKN
DDRCLKP
EMIFD00
EMIFD09
VSS
AVDDA6
VSS
DVDD15
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DDRD56
DDRD58
DVDD15
VSS
DDRVREFSSTL
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DDRD06
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
SIGNAL NAME
DDRD37
DDRDQM4
DDRD43
DDRD40
DDRD51
DDRD54
DDRDQM6
DDRD59
DDRD60
DDRD04
DDRD02
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
VCNTL4
VCNTL1
EMIFD07
EMIFD08
EMIFD11
EMIFD13
EMIFD04
EMIFD06
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
VCNTL0
AVDDA9
VSS
AVDDA10
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
SIGNAL NAME
VSS
DDRRZQ1
VSS
DVDD15
VSS
AVDDA8
VSS
DDRRZQ2
VSS
DVDD15
VSS
J33
K1
K2
K3
K4
J28
J29
J30
J31
J32
J23
J24
J25
J26
J27
J18
J19
J20
J21
J22
K10
K11
K12
K13
K14
K15
K5
K6
K7
K8
K9
J13
J14
J15
J16
J17
J8
J9
J10
J11
J12
J3
J4
J5
J6
J7
BALL NUMBER
H30
H31
H32
H33
J1
J2
DVDD18
RSV014
RSV013
VCNTL5
RSV001
USIMCLK
EMIFA20
EMIFA19
EMIFD01
EMIFD02
CVDD
VSS
CVDD
VSS
CVDD
VSS
VNWA2
VSS
CVDD
VSS
EMIFD10
EMIFD14
AVDDA2
RSV009
VPP0
VSS
CVDD
VSS
CVDD
VSS
CVDD
SIGNAL NAME
VCNTL3
VCNTL2
RSV000
USIMIO
EMIFD03
DVDD18
VSS
EMIFD12
EMIFD15
EMIFD05
VSS
RSV010
VSSCMON
CVDDCMON
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
Terminals
47
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K27
K28
K29
K30
K31
K32
K32
K22
K23
K24
K25
K26
BALL NUMBER
K16
K17
K18
K19
K20
K21
K33
K33
L17
L18
L19
L20
L21
L12
L13
L14
L15
L16
L5
L6
L7
L8
L9
L10
L11
L1
L2
L3
L4
L27
L28
L29
L30
L31
L32
L22
L23
L24
L25
L26
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
CVDD
VSS
CVDD1
VSS
CVDDTMON
VSS
DVDD18
SPI0SCS2
SPI2SCS3
SPI0SCS0
SPI0SCS3
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
AVSIFSEL[0]
2
EMIFA11
EMIFA16
EMIFA14
EMIFA21
EMIFA17
EMIFA23
VSS
DVDD18
VSS
CVDD
VSS
SIGNAL NAME
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSSTMON
DVDD18
VSS
USIMRST
TIMO1
TIMO0
TIMI1
AVSIFSEL[1]
2
TIMI0
Table 5-5. Terminal Functions — By Ball Number (continued)
M11
M12
M13
M14
M15
M16
M17
M6
M7
M8
M9
M10
BALL NUMBER
L33
M1
M2
M3
M4
M5
CVDD1
VSS
CVDD1
VSS
CVDD
VSS
CVDD
SIGNAL NAME
SPI2CLK
VSS
DVDD18
EMIFA06
EMIFA10
EMIFA09
EMIFA18
DVDD18
VSS
VPP1
VSS
M18
M19
VSS
CVDD
N30
N31
N32
N33
P1
P2
P3
N25
N26
N27
N28
N29
BALL NUMBER
N19
N20
N21
N22
N23
N24
P4
P5
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
DVDD18
VSS
SPI0SCS1
SPI0CLK
SPI0DIN
SPI1SCS1
SPI1CLK
USB1RX0M
VSS
EMIFWAIT1
EMIFA07
EMIFA08
EMIFA05
VSS
DVDD18
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
N3
N4
N5
N6
N7
M31
M32
M33
N1
N2
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
N13
N14
N15
N16
N17
N18
N8
N9
N10
N11
N12
P22
P23
P24
P25
P26
P17
P18
P19
P20
P21
P10
P11
P12
P13
P14
P15
P16
P6
P7
P8
P9
R2
R3
R4
P32
P33
R1
P27
P28
P29
P30
P31
DVDD18
VSS
SPI1SCS0
SPI2DIN
SPI2SCS0
SPI1DOUT
SPI2SCS2
VSS
USB1TX0M
EMIFA22
USB1DP
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
EMIFA04
DVDD18
VSS
VNWA1
VSS
USB1DVDD33
VSS
CVDD
VSS
CVDD
VSS
SIGNAL NAME
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
DVDD18
SPI0DOUT
SPI1SCS2
DVDD18
VSS
SPI1SCS3
USB1RX0P
USB1TX0P
EMIFA00
USB1DM
EMIFA01
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R27
R28
R29
R30
R21
R22
R23
R24
R25
R26
R16
R17
R18
R19
R20
R11
R12
R13
R14
R15
BALL NUMBER
R5
R6
R7
R8
R9
R10
R31
R32
T18
T19
T20
T21
T22
T23
T13
T14
T15
T16
T17
T6
T7
T8
T9
T10
T11
T12
R33
T1
T2
T3
T4
T5
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
SPI2DOUT
UART0RTS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
UART0CTS
USB0RX0M
VSS
EMIFA15
USBCLKM
EMIFA13
EMIFWAIT0
DVDD18
VSS
USB1VPTX
VSS
VDDUSB1
VSS
Table 5-5. Terminal Functions — By Ball Number (continued)
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
SIGNAL NAME
EMIFWE
EMIFBE1
VSS
USB1VP
VSS
USB1VPH
VSS
VDDUSB1
VSS
CVDD
VSS
U7
U8
U9
U10
U11
U12
U2
U3
U4
U5
U6
T30
T31
T32
T33
U1
BALL NUMBER
T24
T25
T26
T27
T28
T29
USB0TX0M
VSS
USBCLKP
EMIFA12
EMIFA02
VSS
USB0VP
VSS
VDDUSB0
VSS
CVDD
SIGNAL NAME
VSS
CVDD
VSS
DVDD18
VSS
UART0RXD
UART0TXD
UART1CTS
UART1TXD
UART1RTS
USB0RX0P
V26
V27
V28
V29
V30
V30
V21
V22
V23
V24
V25
V16
V17
V18
V19
V20
BALL NUMBER
V10
V11
V12
V13
V14
V15
VSS
DVDD18
SPI2SCS1
SPI1DIN
U13
U14
U15
U16
U17
U18
V7
V8
V9
V4
V5
V6
U32
U33
V1
V2
V3
U25
U26
U27
U28
U29
U30
U31
U19
U20
U21
U22
U23
U24
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
UART1RXD
VD
DVDD18
VSS
UART0DTR
VSS
USB0TX0P
USB0DP
USB1VBUS
USB1RESREF
EMIFA03
DVDD18
VSS
USB0VPTX
V31
V31
V32
V32
V33
V33
W19
W20
W21
W22
W23
W24
W14
W15
W16
W17
W18
W7
W8
W9
W10
W11
W12
W13
W1
W2
W3
W4
W5
W6
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
VSS
VCL
GPIO00
SIGNAL NAME
VSS
VDDUSB0
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
LENDIAN
2
GPIO07
BOOTMODE06
2
GPIO04
BOOTMODE03
2
GPIO03
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
USB0VPH
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
BOOTMODE02
2
EMIFCE2
VSS
USB0DM
USB0ID0
USB0VBUS
USB1ID0
RSV012
RSV011
Terminals
49
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Y31
Y31
Y32
Y32
Y27
Y28
Y29
Y29
Y23
Y24
Y25
Y26
Y30
Y30
Y33
Y33
AA1
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y5
Y6
Y7
W33
W33
Y1
Y2
Y3
Y4
W31
W31
W32
W32
BALL NUMBER
W25
W26
W27
W28
W29
W30
W30
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
CVDD1
VSS
CVDD
VSS
DVDD18
VSS
GPIO02
BOOTMODE01
2
GPIO11
BOOTMODE10
2
GPIO15
BOOTMODE_RSVD
2
GPIO12
BOOTMODE11
2
GPIO14
MAINPLLODSEL
2
EMIFCE0
SIGNAL NAME
VSS
CVDD
VSS
DVDD18
UART0DSR
GPIO05
BOOTMODE04
2
GPIO08
BOOTMODE07
2
GPIO06
Table 5-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
AA2
AA3
AA4
AA5
AA6
AA7
AA8
SIGNAL NAME
EMIFBE0
DVDD18
VSS
EMU15
EMU01
VSS
DVDD18
BALL NUMBER
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AA9
AA10
AA11
AA12
VSS
CVDD
VSS
CVDD1
AB25
AB26
AB27
AB28
BOOTMODE05
2
GPIO09
BOOTMODE08
2
EMIFCE3
EMIFOE
AA13
AA14
AA15
AA16
VSS
CVDD1
VSS
CVDD
AB29
AB29
AB30
AB30
SIGNAL NAME
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
DVDD18
VSS
EMIFRW
EMIFCE1
EMU17
USB0RESREF
DVDD18
VSS
CVDD
VSS
USB0DVDD33
VSS
CVDD1
VSS
CVDD
VSS
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA29
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
AB31
AB31
AB32
AB32
AB32
AB33
AB33
AB33
AC1
AC2
AC3
AC4
AC5
AC6
GPIO10
BOOTMODE09
2
GPIO25
EMU27
3
GPIO19
EMU21
3
GPIO17
EMU19
3
BOOTMODE14
2
GPIO18
EMU20
3
BOOTMODE15
2
USB1DRVVBUS
EMU13
EMU07
EMU02
EMU00
HYPLNK0TXFLCLK
CVDD
VSS
CVDD
VSS
CVDD
VSS
AA30
AA30
AA31
AA32
AA33
AA33
AB5
AB6
AB7
AB8
AB1
AB2
AB3
AB4
AB9
AB10
CVDD1
VSS
CVDD
VSS
DVDD18
GPIO01
BOOTMODE00
2
GPIO13
BOOTMODE12
2
DVDD18
VSS
GPIO16
BOOTMODE13
2
USB0DRVVBUS
EMU16
EMU14
EMU08
EMU06
HYPLNK0TXPMCLK
DVDD18
VSS
CVDD
VSS
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
AB11
AB12
AB13
AB14
AB15
AB16
AB17
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
AC23
AC24
AC25
AC26
AC27
AC28
AC29
VSS
CVDD
VSS
CVDD
VSS
DVDD18
GPIO20
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AD31
AD31
AD32
AD32
AD33
AD33
AE1
AE2
AE3
AE4
AE5
AC32
AC32
AC33
AC33
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD29
AD30
AD30
BALL NUMBER
AC29
AC30
AC30
AC31
AC31
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
CVDD
VSS
VNWA3
VSS
CVDD
VSS
DVDD18
VSS
GPIO22
EMU24
3
GPIO31
Table 5-5. Terminal Functions — By Ball Number (continued)
SIGNAL NAME BALL NUMBER
AE6
SIGNAL NAME
EMU03
BALL NUMBER
AF24
EMU22
3
GPIO26
EMU28
3
GPIO23
AE7
AE8
AE9
AE10
XFIMDIO
DVDD18
VSS
VDDALV
AF25
AF26
AF27
AF28
EMU25
3
GPIO24
EMU26
3
GPIO21
VSS
VNWA4
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
EMU23
3
HYPLNK0RXPMDAT
EMU12
EMU05
DVDD18
VSS
EMU04
AVDDA3
AE11
AE12
AE13
AE14
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE33
AE22
AE23
AE24
AE25
AE26
AE15
AE16
AE17
AE18
AE19
AE20
AE21
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
DVDD18
VSS
DVDD18
RESET
RSV030
DVDD18
VSS
GPIO30
EMU32
3
CORECLKP
RSV003
EMU10
TSCOMPOUT
HYPLNK0TXPMDAT
XFIMDCLK
AVDDA1
VSS
VDDALV
VSS
AF29
AF30
AF31
AF32
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AF33
AG1
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AF11
AF12
VDDALV
VSS
AG30
AG31
EMU33
3
GPIO29
EMU31
3
GPIO27
AF13
AF14
AF15
AF16
VDDALV
VSS
VDDALV
VSS
AG32
AG33
AH1
AH2
EMU29
3
GPIO28
EMU30
3
HYPLNK0RXPMCLK
RSV002
HYPLNK0RXFLDAT
SYSCLKOUT
TSSYNCEVT
AF17
AF18
AF19
AF20
AF21
AF22
AF23
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
AH3
AH4
AH5
AH6
AH7
AH8
AH9
SIGNAL NAME
VSS
VDDALV
VSS
DVDD18
VSS
TDO
HOUT
BOOTCOMPLETE
RESETFULL
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
DVDD18
VSS
SDA0
SDA2
RSV029
CORECLKN
TSRXCLKOUT1P
TSPUSHEVT0
EMU11
RSV008
NETCPCLKSEL
VSS
RSV015
VSS
XFIREFRES0
VSS
RSV017
VSS
PCIE0REFRES
VSS
VDDALV
VSS
VDDALV
VSS
SCL0
TDI
TRST
RSV028
TSRXCLKOUT1N
EMU18
EMU09
HYPLNK0TXFLDAT
MDIO0
MDCLK0
XFIREFRES1
VSS
RSV020
Terminals
51
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AM5K2E04 AM5K2E02
AJ13
AJ14
AJ15
AJ16
AJ17
AJ8
AJ9
AJ10
AJ11
AJ12
AJ3
AJ4
AJ5
AJ6
AJ7
AH31
AH32
AH33
AJ1
AJ2
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ18
AJ19
AJ20
AJ21
AJ22
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
BALL NUMBER
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
AK32
AK33
AL1
AL2
AL3
AK27
AK28
AK29
AK30
AK31
AK22
AK23
AK24
AK25
AK26
AK17
AK18
AK19
AK20
AK21
AL9
AL10
AL11
AL12
AL13
AL14
AL4
AL5
AL6
AL7
AL8
AK12
AK13
AK14
AK15
AK16
AK7
AK8
AK9
AK10
AK11
AK2
AK3
AK4
AK5
AK6
BALL NUMBER
AJ29
AJ30
AJ31
AJ32
AJ33
AK1
Table 5-5. Terminal Functions — By Ball Number (continued)
SCL2
TMS
POR
TSRXCLKOUT0P
TSRXCLKOUT0N
HYPLNK0RXFLCLK
VSS
HYPLNK0REFRES
VSS
HYPLNK0CLKP
HYPLNK0CLKN
VSS
PCIE1REFRES
XFICLKP
XFICLKN
VSS
PCIE1CLKP
PCIE1CLKN
VSS
PCIE0CLKP
SIGNAL NAME
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
DVDD18
VSS
RESETSTAT
SCL1
PCIE0CLKN
VSS
RSV016
VSS
SGMII01REFRES
VSS
SGMII0CLKP
SGMII0CLKN
RSV019
SGMII00REFRES
RSV018
PCIE0TXN1
VSS
SGMII0TXP7
SGMII0TXN7
VSS
SGMII0TXP5
SGMII0TXN5
VSS
SGMII0TXP3
SGMII0TXN3
VSS
SGMII0TXP1
SGMII0TXN1
VSS
TSIP0CLKA
TSIP0FSB
TSIP0CLKB
TSPUSHEVT1
RSV007
RSV006
SIGNAL NAME
VSS
DVDD18
TSIP0FSA
SDA1
TCK
TSREFCLKN
TSREFCLKP
VSS
HYPLNK0TXP3
HYPLNK0TXN3
VSS
HYPLNK0TXP1
HYPLNK0TXN1
VSS
XFITXP1
XFITXN1
VSS
PCIE1TXP1
PCIE1TXN1
VSS
PCIE0TXP1
VSS
HYPLNK0TXP2
HYPLNK0TXN2
VSS
HYPLNK0TXP0
HYPLNK0TXN0
VSS
XFITXP0
XFITXN0
VSS
PCIE1TXP0
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AL31
AL32
AL33
AM1
AM2
AL26
AL27
AL28
AL29
AL30
AL21
AL22
AL23
AL24
AL25
BALL NUMBER
AL15
AL16
AL17
AL18
AL19
AL20
VSS
HYPLNK0RXN3
HYPLNK0RXP3
VSS
HYPLNK0RXN1
HYPLNK0RXP1
VSS
XFIRXN1
XFIRXP1
VSS
PCIE1RXN1
PCIE1RXP1
VSS
PCIE0RXN1
PCIE0RXP1
VSS
SGMII0RXN7
SGMII0RXP7
VSS
SGMII0RXN5
SIGNAL NAME
PCIE1TXN0
VSS
PCIE0TXP0
PCIE0TXN0
VSS
SGMII0TXP6
SGMII0TXN6
VSS
SGMII0TXP4
SGMII0TXN4
VSS
SGMII0TXP2
SGMII0TXN2
VSS
SGMII0TXP0
SGMII0TXN0
VSS
TSIP0TX0
TSIP0TR1
VSS
NETCPCLKP
SGMII0RXP5
VSS
SGMII0RXN3
SGMII0RXP3
VSS
SGMII0RXN1
SGMII0RXP1
VSS
TSIP0TR0
TSIP0TX1
DVDD18
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Terminals
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
BALL NUMBER
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Table 5-5. Terminal Functions — By Ball Number (continued)
SIGNAL NAME
VSS
VSS
NETCPCLKN
VSS
HYPLNK0RXN2
HYPLNK0RXP2
VSS
HYPLNK0RXN0
HYPLNK0RXP0
VSS
XFIRXN0
BALL NUMBER
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
SIGNAL NAME
XFIRXP0
VSS
PCIE1RXN0
PCIE1RXP0
VSS
PCIE0RXN0
PCIE0RXP0
VSS
SGMII0RXN6
SGMII0RXP6
VSS
AN29
AN30
AN31
AN32
AN33
BALL NUMBER
AN23
AN24
AN25
AN26
AN27
AN28
SIGNAL NAME
SGMII0RXN4
SGMII0RXP4
VSS
SGMII0RXN2
SGMII0RXP2
VSS
SGMII0RXN0
SGMII0RXP0
VSS
DVDD18
VSS
5.4
Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Device Configuration Pins: If the pin is both routed out and not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.
For the device configuration pins (listed in
Table 8-25 ), if they are both routed out and are not driven (in
Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented.
Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Be sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V
IL all inputs connected to the net. For a pullup resistor, this should be above the highest V
IH level of level of all inputs on the net. A reasonable choice would be to target the V the limiting device; which, by definition, have margin to the V
IL
OL or V
OH and V
IH levels for the logic family of levels.
• Select a pullup/pulldown resistor with the largest possible value that still ensures that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems:
• A 1-k Ω resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
Terminals
53
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• A 20-k Ω resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
For more detailed information on input current (I
I
), and the low-level/high-level input voltages (V
IL and V
IH for the AM5K2E0x device, see
. To determine which pins on the device include internal
) pullup/pulldown resistors, see
54
Terminals
Copyright © 2012–2015, Texas Instruments Incorporated
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SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
6 Memory, Interrupts, and EDMA for AM5K2E0x
6.1
Memory Map SummaryAM5K2E0x
The following table shows the memory map address ranges of the device.
00 01D2 0080
00 01D2 8000
00 01D2 8080
00 01D3 0000
00 01D3 0080
00 01D3 8000
00 01D3 8080
00 01D4 0000
00 01D4 0080
00 01D4 8000
00 01D4 8080
00 01D5 0000
00 01D5 0080
00 01D5 8000
00 01D5 8080
00 01D6 0000
00 01D6 0080
00 01D6 8000
00 01D6 8080
00 01D7 0000
00 01D7 0080
00 01D7 8000
00 01D7 8080
Physical 40-bit Address
Start
00 0000 0000
00 0004 0000
End
00 0003 FFFF
00 007F FFFF
00 0080 0000
00 0090 0000
00 00E0 0000
00 00E0 8000
00 00F0 0000
00 00F0 8000
00 0100 0000
00 008F FFFF
00 00DF FFFF
00 00E0 7FFF
00 00EF FFFF
00 00F0 7FFF
00 00FF FFFF
00 0100 FFFF
00 0101 0000
00 0110 0000
00 0101 0000
00 01C0 0000
00 01D0 0000
00 01D0 0080
00 01D0 8000
00 01D0 8080
00 01D1 0000
00 01D1 0080
00 01D1 8000
00 01D1 8080
00 01D2 0000
00 010F FFFF
00 0110 FFFF
00 01BF FFFF
00 01CF FFFF
00 01D0 007F
00 01D0 7FFF
00 01D0 807F
00 01D0 FFFF
00 01D1 007F
00 01D1 7FFF
00 01D1 807F
00 01D1 FFFF
00 01D2 007F
00 01D2 7FFF
00 01D2 807F
00 01D2 FFFF
00 01D3 007F
00 01D3 7FFF
00 01D3 807F
00 01D3 FFFF
00 01D4 007F
00 01D4 7FFF
00 01D4 807F
00 01D4 FFFF
00 01D5 007F
00 01D5 7FFF
00 01D5 807F
00 01D5 FFFF
00 01D6 007F
00 01D6 7FFF
00 01D6 807F
00 01D6 FFFF
00 01D7 007F
00 01D7 7FFF
00 01D7 807F
00 01D7 FFFF
Table 6-1. Device Memory Map Summary AM5K2E0x
Reserved
Tracer CFG7
Reserved
Tracer CFG8
Reserved
Tracer CFG9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer CFG0
Reserved
Tracer CFG1
Reserved
Tracer CFG2
Reserved
Tracer CFG3
Reserved
Tracer CFG4
Reserved
Tracer CFG5
Reserved
Tracer CFG6
ARM View
ARM ROM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM AXI2VBUSM registers
Reserved
ARM STM Stimulus Ports
Reserved
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
1M
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
Bytes
256K
8M-256K
1M
5M
32K
1M-32K
32K
1M-32K
64K
1M-64K
64K
11M-64K
Reserved
Tracer CFG7
Reserved
Tracer CFG8
Reserved
Tracer CFG9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer CFG0
Reserved
Tracer CFG1
Reserved
Tracer CFG2
Reserved
Tracer CFG3
Reserved
Tracer CFG4
Reserved
Tracer CFG5
Reserved
Tracer CFG6
SOC View
ARM ROM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for AM5K2E0x
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www.ti.com
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
00 01DE 0000
00 01DE 0080
00 01DE 0400
00 01DD 0480
00 01DE 0800
00 01DE 0880
00 01DE 8000
00 01DE 8080
00 01E0 0000
00 01E4 0000
00 01E8 0000
00 01E8 4000
00 01EC 0000
00 01F0 0000
00 01F8 0000
00 01F9 0000
00 01FA 0000
00 01FC 0000
00 01FE 0000
00 0200 0000
00 01DA 8080
00 01DB 0000
00 01DB 0080
00 01DB 8000
00 01DB 8080
00 01DC 0000
00 01DC 0080
00 01DC 8000
00 01DC 8080
00 01DD 0000
00 01DD 0080
00 01DD 8000
00 01DD 8080
Physical 40-bit Address
Start
00 01D8 0000
End
00 01D8 007F
00 01D8 0080
00 01D8 8000
00 01D8 8080
00 01D8 7FFF
00 01D8 807F
00 01D8 8FFF
00 01D9 0000
00 01D9 0080
00 01D9 8000
00 01D9 8080
00 01DA 0000
00 01DA 0080
00 01DA 8000
00 01D9 007F
00 01D9 7FFF
00 01D9 807F
00 01D9 FFFF
00 01DA 007F
00 01DA 7FFF
00 01DA 807F
00 01DA FFFF
00 01DB 007F
00 01DB 7FFF
00 01DB 807F
00 01DB 8FFF
00 01DC 007F
00 01DC 7FFF
00 01DC 807F
00 01DC FFFF
00 01DD 007F
00 01DD 7FFF
00 01DD 807F
00 01DD FFFF
00 01DE 007F
00 01DE 03FF
00 01DE 047F
00 01DD 07FF
00 01DE 087F
00 01DE 7FFF
00 01DE 807F
00 01DF FFFF
00 01E3 FFFF
00 01E7FFFF
00 01E8 3FFF
00 01EB FFFF
00 01EF FFFF
00 01F7 FFFF
00 01F8 FFFF
00 01F9 FFFF
00 01FB FFFF
00 01FD FFFF
00 01FF FFFF
00 020F FFFF
00 0210 0000
00 0211 0000
00 0212 0000
00 0214 0000
00 0216 0000
00 0210 FFFF
00 0211 FFFF
00 0213 FFFF
00 0215 FFFF
00 0217 FFFF
64K
64K
128K
128K
128K
1M
128
1K-128
128
1K-128
128
30K-128
128
64K-128
256K
256k
16K
240k
256K
512K
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
Bytes
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
32K-128
128
64K
64K
128K
128K
128K
ARM View
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer CFG20
Reserved
Reserved
Reserved
Tracer CFG22
Reserved
Reserved
Reserved
Tracer CFG24
Reserved
Tracer CFG25
Reserved
Tracer CFG26
Reserved
Tracer CFG27
Reserved
Tracer CFG28
Reserved
Tracer CFG29
Reserved
Tracer CFG30
Reserved
Tracer CFG31
Reserved
Reserved
TSIP_CFG
ARM CorePac_CFG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Network Coprocessor 0(Packet Accelerator,
1-gigabit Ethernet switch subsystem and
Security Accelerator)
Reserved
Reserved
Reserved
Reserved
Reserved
SOC View
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer CFG20
Reserved
Reserved
Reserved
Tracer CFG22
Reserved
Reserved
Reserved
Tracer CFG24
Reserved
Tracer CFG25
Reserved
Tracer CFG26
Reserved
Tracer CFG27
Reserved
Tracer CFG28
Reserved
Tracer CFG29
Reserved
Tracer CFG30
Reserved
Tracer CFG31
Reserved
Reserved
TSIP_CFG
ARM CorePac_CFG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Network Coprocessor 0(Packet Accelerator,
1-gigabit Ethernet switch subsystem and
Security Accelerator)
Reserved
Reserved
Reserved
Reserved
Reserved
56
Memory, Interrupts, and EDMA for AM5K2E0x
Copyright © 2012–2015, Texas Instruments Incorporated
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Product Folder Links:
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K
2K
2K
2K
10K
2K
14K
2K
14K
2K
14K
128
64K-128
128
1K
31K
1K
128
15K-128
256
16K-256
256
16K-256
256
12K-256
128
4K-128
7K
1K
7K
64K
1K
15K
1K
Bytes
32k
32k
64k
64K
00 021E 0000
00 021F 0000
00 021F 0800
00 021F 1000
00 021F 1800
00 021F 4000
00 021F 4800
00 021F 8000
00 021F 8800
00 021F C000
00 021F C800
00 0220 0000
00 0220 0080
00 0221 0000
00 0221 0080
00 0222 0000
00 0222 0080
00 0223 0000
00 0223 0080
00 0224 0000
00 0224 0080
00 0225 0000
00 0225 0080
00 0226 0000
00 0226 0080
00 0227 0000
00 021C 8000
00 021C 8400
00 021D 0000
00 021D 0400
00 021D 0100
00 021D 4000
00 021D 4100
00 021D 8000
00 021D 8100
00 021D C000
00 021D C100
00 021D F000
00 021D F080
Physical 40-bit Address
Start
00 0218 0000
End
00 0218 7FFF
00 0218 8000
00 0219 0000
00 021A 0000
00 0218 FFFF
00 0219 FFFF
00 021A FFFF
00 021B 0000
00 021C 0000
00 021C 0400
00 021C 4000
00 021C 4400
00 021C 6000
00 021C 6400
00 021B FFFF
00 021C 03FF
00 021C 3FFF
00 021C 43FF
00 021C 5FFF
00 021C 63FF
00 021C 7FFF
00 021C 83FF
00 021C FFFF
00 021D 03FF
00 021D 047F
00 021D 3FFF
00 021D 40FF
00 021D 7FFF
00 021D 80FF
00 021D BFFF
00 021D C0FF
00 021D EFFF
00 021D F07F
00 021D FFFF
00 021E FFFF
00 021F 07FF
00 021F 0FFF
00 021F 17FF
00 021F 3FFF
00 021F 47FF
00 021F 7FFF
00 021F 87FF
00 021F BFFF
00 021F C7FF
00 021F FFFF
00 0220 007F
00 0220 FFFF
00 0221 007F
00 0221 FFFF
00 0222 007F
00 0222 FFFF
00 0223 007F
00 0223 FFFF
00 0224 007F
00 0224 FFFF
00 0225 007F
00 0225 FFFF
00 0226 007F
00 0226 FFFF
00 0227 007F
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM View
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 15
Tracer CFG32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USIM configuration
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SOC View
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 15
Tracer CFG32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USIM configuration
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for AM5K2E0x
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www.ti.com
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
256
16K
256
16K
256
16K
256
16K
4K
64K-4K
1K
31K
8K
4K
4K
8K
1K
1K
62K
8K
4K
4K
8K
8K
16K
8K
128
64K-128
128
64K-128
128
128
128
128
128
64K
512
40K-512
8K
Bytes
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
00 0231 C000
00 0231 E000
00 0232 0000
00 0232 4000
00 0232 6000
00 0232 8000
00 0232 9000
00 0232 A000
00 0232 C000
00 0232 D000
00 0232 E000
00 0233 0000
00 0233 0400
00 0233 0400
00 0234 0000
00 0234 0100
00 0234 4000
00 0234 4100
00 0234 8000
00 0234 8100
00 0234 C000
00 0234 C100
00 0235 0000
00 0235 1000
00 0236 0000
00 0236 0400
00 022D 0000
00 022D 0080
00 022E 0000
00 022E 0080
00 022F 0000
00 022F 0080
00 022F 0100
00 022F 0180
00 022F 0200
00 0230 0000
00 0231 0000
00 0231 0200
00 0231 A000
Physical 40-bit Address
Start
00 0227 0080
End
00 0227 FFFF
00 0228 0000
00 0228 0080
00 0229 0000
00 0228 007F
00 0228 FFFF
00 0229 007F
00 0229 0080
00 022A 0000
00 022A 0080
00 022B 0000
00 022B 0080
00 022C 0000
00 022C 0080
00 0229 FFFF
00 022A 007F
00 022A FFFF
00 022B 007F
00 022B FFFF
00 022C 007F
00 022C FFFF
00 022D 007F
00 022D FFFF
00 022E 007F
00 022E FFFF
00 022F 007F
00 022F 00FF
00 022F 017F
00 022F 01FF
00 022F 027F
00 0230 FFFF
00 0231 01FF
00 0231 9FFF
00 0231 BFFF
00 0231 DFFF
00 0231 FFFF
00 0232 3FFF
00 0232 5FFF
00 0232 7FFF
00 0232 8FFF
00 0232 9FFF
00 0232 BFFF
00 0232 CFFF
00 0232 DFFF
00 0232 EFFF
00 0233 03FF
00 0233 07FF
00 0233 FFFF
00 0234 00FF
00 0234 3FFF
00 0234 40FF
00 0234 7FFF
00 0234 80FF
00 0234 BFFF
00 0234 C0FF
00 0234 FFFF
00 0235 0FFF
00 0235 FFFF
00 0236 03FF
00 0236 7FFF
ARM View
Reserved
Timer 8
Reserved
Timer 9
Reserved
Timer 10
Reserved
Timer 11
Reserved
Timer 12
Reserved
Timer 13
Reserved
Timer 14
Reserved
Timer 15
Timer 16
Timer 17
Timer 18
Timer 19
Reserved
PLL Controller
Reserved
HyperLink0 SerDes Config
Reserved
10GbE SerDes Config
PCIe0 SerDes Config
SGMII 1 SerDes Config
PCIe1SerDes Config
Reserved
DDRA PHY Config
SGMII 0 SerDes Config
Reserved
Reserved
Reserved
SmartReflex0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Power sleep controller (PSC)
Reserved
Memory protection unit (MPU) 0
Reserved
SOC View
Reserved
Timer 8
Reserved
Timer 9
Reserved
Timer 10
Reserved
Timer 11
Reserved
Timer 12
Reserved
Timer 13
Reserved
Timer 14
Reserved
Timer 15
Timer 16
Timer 17
Timer 18
Timer 19
Reserved
PLL Controller
Reserved
HyperLink0 SerDes Config
Reserved
10GbE SerDes Config
PCIe0 SerDes Config
SGMII 1 SerDes Config
PCIe1SerDes Config
Reserved
DDRA PHY Config
SGMII 0 SerDes Config
Reserved
Reserved
Reserved
SmartReflex0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Power sleep controller (PSC)
Reserved
Memory protection unit (MPU) 0
Reserved
58
Memory, Interrupts, and EDMA for AM5K2E0x
Copyright © 2012–2015, Texas Instruments Incorporated
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Product Folder Links:
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
62K
192K
128
32K-128
32K
64K
1K
64K-1K
128
16K
48K
16K
48K
512
1K-512
1K
48K
16K
48K
16K
48K
16K
48K
256K
16K
48K
16K
48K
16K
1K
1K
1K
1K
1K
1K
471K
1K
1K
1K
1K
31K
1K
1K
Bytes
1K
31K
1K
31K
1K-128
128
1K-128
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
00 0246 4000
00 0247 0000
00 0247 4000
00 0248 0000
00 0248 4000
00 0249 0000
00 0249 4000
00 024A 0000
00 024A 4000
00 024B 0000
00 024B 4000
00 024C 0000
00 024C 0200
00 024C 0400
00 024C 0800
00 024D 0000
00 0250 0000
00 0250 0080
00 0250 8000
00 0251 0000
00 0252 0000
00 0252 0400
00 0253 0000
00 0238 9000
00 0238 9400
00 0238 9800
00 0238 9C00
00 0238 A000
00 0238 A400
00 0238 A800
00 0240 0000
00 0244 0000
00 0244 4000
00 0245 0000
00 0245 4000
00 0246 0000
Physical 40-bit Address
Start
00 0236 8000
End
00 0236 83FF
00 0236 8400
00 0237 0000
00 0237 0400
00 0236 FFFF
00 0237 03FF
00 0237 7FFF
00 0237 8000
00 0237 8400
00 0238 0000
00 0238 8000
00 0238 8400
00 0238 8800
00 0238 8C00
00 0237 83FF
00 0237 FFFF
00 0238 03FF
00 0238 83FF
00 0238 87FF
00 0238 8BFF
00 0238 8FFF
00 0238 93FF
00 0238 97FF
00 0238 9BFF
00 0238 9FFF
00 0238 A3FF
00 0238 A7FF
00 023F FFFF
00 0243 FFFF
00 0244 3FFF
00 0244 FFFF
00 0245 3FFF
00 0245 FFFF
00 0246 3FFF
00 0246 FFFF
00 0247 3FFF
00 0247 FFFF
00 0248 3FFF
00 0248 FFFF
00 0249 3FFF
00 0249 FFFF
00 024A 3FFF
00 024A FFFF
00 024B 3FFF
00 024B FFFF
00 024C 01FF
00 024C 03FF
00 024C 07FF
00 024C FFFF
00 024F FFFF
00 0250 007F
00 0250 7FFF
00 0250 FFFF
00 0251 FFFF
00 0252 03FF
00 0252 FFFF
00 0253 007F
00 0253 0080
00 0253 0400
00 0253 0480
00 0253 03FF
00 0253 047F
00 0253 07FF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I
2
C0
Reserved
I
2
C1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM View
Memory protection unit (MPU) 1
Reserved
Memory protection unit (MPU) 2
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 5
Reserved
Memory protection unit (MPU) 7
Memory protection unit (MPU) 8
Memory protection unit (MPU) 9
Memory protection unit (MPU) 10
Memory protection unit (MPU) 11
Memory protection unit (MPU) 12
Memory protection unit (MPU) 13
Memory protection unit (MPU) 14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I
2
C0
Reserved
I
2
C1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SOC View
Memory protection unit (MPU) 1
Reserved
Memory protection unit (MPU) 2
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 5
Reserved
Memory protection unit (MPU) 7
Memory protection unit (MPU) 8
Memory protection unit (MPU) 9
Memory protection unit (MPU) 10
Memory protection unit (MPU) 11
Memory protection unit (MPU) 12
Memory protection unit (MPU) 13
Memory protection unit (MPU) 14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for AM5K2E0x
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Product Folder Links:
AM5K2E04 AM5K2E02
59
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
Bytes
128
31K
1K
31K
1K
1K
31K
1K
31K
1K
31K
1K
1K
31K
1K
31K
1K
31K
32K
64K
32K
32K
64K
32K
96K
60K
64K
2K
62K
192K
512K
32K
8K
8K-256
256
64K
16K
4K
1K-128
64
1K-64
64
60K-64
8K
8K
8K
8K
128K
128K
512K
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
Physical 40-bit Address
Start
00 0253 0800
End
00 0253 087F
00 0270 8000
00 0271 0000
00 0272 0000
00 0272 8000
00 0273 0000
00 0274 0000
00 0274 8000
00 0276 0000
00 0276 0400
00 0276 8000
00 0276 8400
00 0277 0000
00 0277 0400
00 0277 8000
00 0278 0400
00 0278 0000
00 0278 0400
00 0278 8000
00 0278 8400
00 0279 0000
00 0279 0400
00 0279 8000
00 0279 8400
00 027A 0000
00 0253 0880
00 0253 0C00
00 0253 0C40
00 0253 1000
00 0253 1040
00 0254 0000
00 0256 0080
00 0258 0000
00 0260 0000
00 0260 2000
00 0260 4000
00 0260 6000
00 0260 8000
00 0260 A000
00 0260 BF00
00 0260 C000
00 0261 C000
00 0262 0000
00 0262 1000
00 0263 0000
00 0264 0000
00 0264 0800
00 0265 0000
00 0268 0000
00 0270 0000
00 0270 FFFF
00 0271 FFFF
00 0272 7FFF
00 0272 FFFF
00 0273 FFFF
00 0274 7FFF
00 0275 FFFF
00 0276 03FF
00 0276 7FFF
00 0276 83FF
00 0276 FFFF
00 0277 03FF
00 0277 7FFF
00 0277 83FF
00 0277 FFFF
00 0278 03FF
00 0278 7FFF
00 0278 83FF
00 0278 FFFF
00 0279 03FF
00 0279 7FFF
00 0279 83FF
00 0279 FFFF
00 027A 03FF
00 0253 0BFF
00 0253 0C3F
00 0253 FFFF
00 0253 103F
00 0253 FFFF
00 0255 FFFF
00 0257 FFFF
00 025F FFFF
00 0260 1FFF
00 0260 3FFF
00 0260 5FFF
00 0260 7FFF
00 0260 9FFF
00 0260 BEFF
00 0260 BFFF
00 0261 BFFF
00 0261 FFFF
00 0262 0FFF
00 0262 FFFF
00 0263 FFFF
00 0264 07FF
00 0264 FFFF
00 0267 FFFF
00 026F FFFF
00 0270 7FFF
ARM View
I
2
C2
Reserved
UART0
Reserved
UART1
Reserved
Reserved
ARM CorePac INTC
Reserved
Secondary interrupt controller (CIC) 0
Reserved
Reserved
Reserved
Secondary interrupt controller (CIC) 2
Reserved
GPIO Config
Reserved
Reserved
BOOTCFG chip-level registers
Reserved
USB 0 PHY CFG
Semaphore Config
Reserved
Reserved
USB 0 MMR CFG
EDMA channel controller (TPCC) 0
EDMA channel controller (TPCC) 4
Reserved
EDMA channel controller (TPCC) 1
EDMA channel controller (TPCC) 3
Reserved
EDMA channel controller (TPCC) 2
Reserved
EDMA TPCC0 transfer controller (TPTC) 0
Reserved
EDMA TPCC0 transfer controller (TPTC) 1
Reserved
EDMA TPCC1 transfer controller (TPTC) 0
Reserved
EDMA TPCC1 transfer controller (TPTC) 1
Reserved
EDMA TPCC1 transfer controller (TPTC) 2
Reserved
EDMA TPCC1 transfer controller (TPTC) 3
Reserved
EDMA TPCC2 transfer controller (TPTC) 0
Reserved
EDMA TPCC2 transfer controller (TPTC) 1
Reserved
EDMA TPCC2 transfer controller (TPTC) 2
SOC View
I
2
C2
Reserved
UART0
Reserved
UART1
Reserved
Reserved
ARM CorePac INTC
Reserved
Secondary interrupt controller (CIC) 0
Reserved
Reserved
Reserved
Secondary interrupt controller (CIC) 2
Reserved
GPIO Config
Reserved
Reserved
BOOTCFG chip-level registers
Reserved
USB 0 PHY CFG
Semaphore Config
Reserved
Reserved
USB 0 MMR CFG
EDMA channel controller (TPCC) 0
EDMA channel controller (TPCC) 4
Reserved
EDMA channel controller (TPCC) 1
EDMA channel controller (TPCC) 3
Reserved
EDMA channel controller (TPCC) 2
Reserved
EDMA TPCC0 transfer controller (TPTC) 0
Reserved
EDMA TPCC0 transfer controller (TPTC) 1
Reserved
EDMA TPCC1 transfer controller (TPTC) 0
Reserved
EDMA TPCC1 transfer controller (TPTC) 1
Reserved
EDMA TPCC1 transfer controller (TPTC) 2
Reserved
EDMA TPCC1 transfer controller (TPTC) 3
Reserved
EDMA TPCC2 transfer controller (TPTC) 0
Reserved
EDMA TPCC2 transfer controller (TPTC) 1
Reserved
EDMA TPCC2 transfer controller (TPTC) 2
60
Memory, Interrupts, and EDMA for AM5K2E0x
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
AM5K2E04 AM5K2E02
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
00 027D 8000
00 027E 0000
00 027E 4000
00 027F 0000
00 027F 4000
00 0280 0000
00 0280 4000
00 0281 0000
00 0281 4000
00 0282 0000
00 0282 4000
00 0283 0000
00 0283 4000
00 0284 0000
00 0284 4000
00 0285 0000
00 0285 8000
00 0286 0000
00 0290 0000
00 0294 0000
00 02A0 0000
00 02B0 0000
00 02C0 0000
00 02C1 0000
00 02C2 0000
00 02C4 0000
00 02C6 0000
00 02C8 0000
00 02C9 0000
00 02CA 0000
00 02CC 0000
00 02CE 0000
00 02F0 0000
00 0300 0000
00 0310 0000
00 0800 0000
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
Physical 40-bit Address
Start
00 027A 0400
End
00 027A 7FFF
00 027A 8000
00 027A 8400
00 027B 0000
00 027A 83FF
00 027A FFFF
00 027B 03FF
00 027B 0400
00 027B 8000
00 027B 8400
00 027B 8800
00 027B 8C00
00 027C 0000
00 027C 0400
00 027D 0000
00 027D 4000
00 027B 7FFF
00 027B 83FF
00 027B 87FF
00 027B 8BFF
00 027B FFFF
00 027C 03FF
00 027C FFFF
00 027D 3FFF
00 027D 7FFF
00 027D FFFF
00 027E 3FFF
00 027E FFFF
00 027F 3FFF
00 027F FFFF
00 0280 3FFF
00 0280 FFFF
00 0281 3FFF
00 0281 FFFF
00 0282 3FFF
00 0282 FFFF
00 0283 3FFF
00 0283 FFFF
00 0284 3FFF
00 0284 FFFF
00 0285 7FFF
00 0285 FFFF
00 028F FFFF
00 0293 FFFF
00 029F FFFF
00 02AF FFFF
00 02BF FFFF
00 02C0 FFFF
00 02C1 FFFF
00 02C3 FFFF
00 02C5 FFFF
00 02C7 FFFF
00 02C8 FFFF
00 02C9 FFFF
00 02CB FFFF
00 02CD FFFF
00 02EF FFFF
00 02FF FFFF
00 030F FFFF
00 07FF FFFF
00 0801 FFFF
256K
768K
1M
1M
64K
64K
128K
16K
48K
16K
48K
32K
32K
640K
16K
48K
16K
48K
16K
48K
32K
16K
48K
16K
48K
128K
128K
64K
64K
128K
128K
15M-896K
1M
1M
79M
128K
31K
1K
1K
1K
29K
1K
63K
16K
16K
Bytes
31K
1K
31K
1K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM View
Reserved
EDMA TPCC2 transfer controller (TPTC) 3
Reserved
EDMA TPCC3 transfer controller (TPTC) 0
SOC View
Reserved
EDMA TPCC2 transfer controller (TPTC) 3
Reserved
EDMA TPCC3 transfer controller (TPTC) 0
Reserved
EDMA TPCC3 transfer controller (TPTC) 1
EDMA TPCC4 transfer controller (TPTC) 0
EEDMA TPCC4 transfer controller (TPTC) 1
Reserved
Reserved
Reserved
Reserved
EDMA TPCC3 transfer controller (TPTC) 1
EDMA TPCC4 transfer controller (TPTC) 0
EEDMA TPCC4 transfer controller (TPTC) 1
Reserved
Reserved
Reserved
TI embedded trace buffer (TETB) - CorePac0 TI embedded trace buffer (TETB) - CorePac0
TBR_ARM CorePac - Trace buffer - ARM
CorePac
Reserved
TBR_ARM CorePac - Trace buffer - ARM
CorePac
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TBR_SYS- Trace buffer - System
Reserved
Reserved
Reserved
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE Config
DBG Config
Reserved
Extended memory controller (XMC) configuration
TBR_SYS- Trace buffer - System
Reserved
Reserved
Reserved
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE Config
DBG Config
Reserved
Extended memory controller (XMC) configuration
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for AM5K2E0x
Submit Documentation Feedback
Product Folder Links:
AM5K2E04 AM5K2E02
61
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
Physical 40-bit Address
Start
00 0802 0000
End
00 0BBF FFFF
00 0BC0 0000 00 0BCF FFFF
00 13E0 8000
00 13F0 0000
00 13F0 8000
00 1480 0000
00 1490 0000
00 14E0 0000
00 14E0 8000
00 14F0 0000
00 14F0 8000
00 1580 0000
00 1590 0000
00 15E0 0000
00 15E0 8000
00 15F0 0000
00 15F0 8000
00 1680 0000
00 1690 0000
00 16E0 0000
00 16E0 8000
00 16F0 0000
00 16F0 8000
00 1780 0000
00 0BD0 0000
00 0C00 0000
00 0C20 0000
00 0C60 0000
00 1000 0000
00 1080 0000
00 1090 0000
00 10E0 0000
00 10E0 8000
00 10F0 0000
00 10F0 8000
00 1180 0000
00 1190 0000
00 11E0 0000
00 11E0 8000
00 11F0 0000
00 11F0 8000
00 1280 0000
00 1290 0000
00 12E0 0000
00 12E0 8000
00 12F0 0000
00 12F0 8000
00 1380 0000
00 1390 0000
00 13E0 0000
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
00 13EF FFFF
00 13F0 7FFF
00 147F FFFF
00 148F FFFF
00 14DF FFFF
00 14E0 7FFF
00 14EF FFFF
00 14F0 7FFF
00 157F FFFF
00 158F FFFF
00 15DF FFFF
00 15E0 7FFF
00 15EF FFFF
00 15F0 7FFF
00 167F FFFF
00 168F FFFF
00 16DF FFFF
00 16E0 7FFF
00 16EF FFFF
00 16F0 7FFF
00 177F FFFF
00 178F FFFF
00 0BFF FFFF
00 0C1F FFFF
00 0C5F FFFF
00 0FFF FFFF
00 107F FFFF
00 108F FFFF
00 10DF FFFF
00 10E0 7FFF
00 10EF FFFF
00 10F0 7FFF
00 117F FFFF
00 118F FFFF
00 11DF FFFF
00 11E0 7FFF
00 11EF FFFF
00 11F0 7FFF
00 127F FFFF
00 128F FFFF
00 12DF FFFF
00 12E0 7FFF
00 12EF FFFF
00 12F0 7FFF
00 137F FFFF
00 1388 FFFF
00 13DF FFFF
00 13E0 7FFF
Bytes
60M-128K
1M
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
1M-32K
32K
9M-32K
1M
5M
32K
3M
2M
4M
58M
8M
1M
5M
32K
1M-32K
32K
9M-32K
1M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM View
Reserved
Multicore shared memory controller (MSMC) config
Reserved
Multicore shared memory (MSM)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SOC View
Reserved
Multicore shared memory controller (MSMC) config
Reserved
Multicore shared memory (MSM)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
62
Memory, Interrupts, and EDMA for AM5K2E0x
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
AM5K2E04 AM5K2E02
www.ti.com
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
00 2100 0800
00 2100 0A00
00 2100 0B00
00 2101 0000
00 2101 0200
00 2101 0800
00 2101 0A00
00 2101 1000
00 2102 0000
00 2102 8000
00 2104 0000
00 2140 0000
00 2140 0100
00 2140 0400
00 2180 0000
00 2180 8000
00 21C0 0000
00 2200 0000
00 22A0 0000
00 22A1 0000
00 22B0 0000
00 22B1 0000
00 22C0 0000
00 22C1 0000
00 22D0 0000
00 22D1 0000
00 2079 0000
00 2080 0000
00 2090 0000
00 20A0 0000
00 20A4 0000
00 20A5 0000
00 20B0 0000
00 20B4 0000
00 20BF 0000
00 20C0 0000
00 2100 0000
00 2100 0400
00 2100 0600
Physical 40-bit Address
Start
00 1790 0000
End
00 17DF FFFF
00 17E0 0000
00 17E0 8000
00 17F0 0000
00 17E0 7FFF
00 17EF FFFF
00 17F0 7FFF
00 17F0 8000
00 2000 0000
00 2010 0000
00 2020 0000
00 2060 0000
00 2070 0000
00 2078 0000
00 1FFF FFFF
00 200F FFFF
00 201F FFFF
00 205F FFFF
00 206F FFFF
00 2077 FFFF
00 2078 FFFF
00 207F FFFF
00 208F FFFF
00 209F FFFF
00 20A3 FFFF
00 20A4 FFFF
00 20AF FFFF
00 20B3 FFFF
00 20BE FFFF
00 20BF 01FF
00 20FF FFFF
00 2100 03FF
00 2100 05FF
00 2100 07FF
00 2100 09FF
00 2100 0AFF
00 2100 FFFF
00 2101 01FF
00 2101 07FF
00 2101 09FF
00 2101 0FFF
00 2101 FFFF
00 2102 7FFF
00 2103 FFFF
00 217F FFFF
00 2140 00FF
00 2140 01FF
00 217F FFFF
00 2180 7FFF
00 21BF FFFF
00 21FF FFFF
00 229F FFFF
00 22A0 FFFF
00 22AF FFFF
00 22B0 FFFF
00 22BF FFFF
00 22C0 FFFF
00 22CF FFFF
00 22D0 FFFF
00 22DF FFFF
PCIe 0 config
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI2
EMIF Config
Reserved
DDR3 EMIF Config
Reserved
Reserved
Reserved
Reserved
PCIe 1 config
Reserved
Reserved
HyperLink0 config
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Boot ROM
Reserved
Reserved
Reserved
Reserved
SPI0
SPI1
ARM View
Reserved
Reserved
Reserved
Reserved
Reserved
System trace manager (STM) configuration
Reserved
Reserved
Reserved
Reserved
Reserved
32K
4M-32K
4M
10M
64K
1M-64K
64K
1M-64K
64K
1M-64K
64K
1M-64K
512
256
62K-768
512
2K-512
512
2K-512
60K
32K
96K
4M-256K
256
256
4M-512
704K
64K
4M
1K
512
512
448K
1M
1M
256K
64K
704K
256K
Bytes
5M
32K
1M-32K
32K
129M-32K
1M
1M
4M
1M
512K
64K
PCIe 0 config
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI2
EMIF Config
Reserved
DDR3 EMIF Config
Reserved
Reserved
Reserved
Reserved
PCIe 1 config
Reserved
Reserved
HyperLink0 config
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Boot ROM
Reserved
Reserved
Reserved
Reserved
SPI0
SPI1
SOC View
Reserved
Reserved
Reserved
Reserved
Reserved
System trace manager (STM) configuration
Reserved
Reserved
Reserved
Reserved
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for AM5K2E0x
Submit Documentation Feedback
Product Folder Links:
AM5K2E04 AM5K2E02
63
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
Table 6-1. Device Memory Map Summary AM5K2E0x (continued)
00 23C0 0000
00 2400 0000
00 2500 0000
00 2508 0000
00 2509 0000
00 2800 0000
00 3000 0000
00 3400 0000
00 3800 0000
00 3C00 0000
00 4000 0000
00 5000 0000
00 6000 0000
Physical 40-bit Address
Start
00 22E0 0000
End
00 22E0 FFFF
00 22E1 0000
00 22F0 0000
00 22F1 0000
00 22EF FFFF
00 22F0 FFFF
00 22FF FFFF
00 2300 0000
00 2301 0000
00 2310 0000
00 2311 0000
00 2320 0000
00 2325 0000
00 23A0 0000
00 2300 FFFF
00 230F FFFF
00 2310 FFFF
00 231F FFFF
00 2324 FFFF
00 239F FFFF
00 23BF FFFF
00 7000 0000
01 0000 0000
01 2100 0000
01 2100 0200
08 0000 0000
0A 0000 0000
00 23FF FFFF
00 24FF FFFF
00 2507 FFFF
00 2508 FFFF
00 27FF FFFF
00 2FFF FFFF
00 33FF FFFF
00 37FF FFFF
00 3BFF FFFF
00 3FFF FFFF
00 4FFF FFFF
00 5FFF FFFF
00 6FFF FFFF
00 FFFF FFFF
01 20FF FFFF
01 2100 01FF
07 FFFF FFFF
09 FFFF FFFF
FF FFFF FFFF
ARM View
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Navigator
Reserved
NETCP15 config
USB 1 MMR config
USB 1 PHY config
Reserved
Reserved
EMIF16 CE0
EMIF16 CE1
EMIF16 CE2
EMIF16 CE3
HyperLink0 data
PCIe 0 data
PCIe 1data
Reserved
Reserved
Reserved
Reserved
DDR3 data
Reserved
64M
64M
64M
256M
256M
256M
4M
16M
512K
64K
48M-576K
128M
64M
Bytes
64K
1M-64K
64K
1M-64K
64K
1M-64K
64K
1M-64K
384K
8M-384K
2M
2304M
528M
512
32G-512
8G
984G
SOC View
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Navigator
Reserved
NETCP15 config
USB 1 MMR config
USB 1 PHY config
Reserved
Reserved
EMIF16 CE0
EMIF16 CE1
EMIF16 CE2
EMIF16 CE3
HyperLink0 data
PCIe 0 data
PCIe 1data
Reserved
Reserved
DDR3 EMIF configuration
Reserved
DDR3 data
Reserved
6.2
Memory Protection Unit (MPU) for AM5K2E0x
64
CFG (configuration) space of all slave devices on the TeraNet is protected by the MPU. The AM5K2E0x contains sixteen MPUs of which thirteen MPUs are used:
• MPU0 is used to protect main CORE/3 CFG TeraNet_3P_B (SCR_3P (B)).
• MPU1/2/5 are used for QM_SS (one for VBUSM port and one each for the two configuration VBUSP port).
• MPU3/4/6 are not used.
• MPU7 is used for PCIe1.
• MPU8 is used for peripherals connected to TeraNet_6P_A (SCR_6P (A)).
• MPU9 is used for interrupt controllers connected to TeraNet_3P (SCR_3P).
• MPU10 is used for semaphore.
• MPU11 is used to protect TeraNet_6P_B (SCR_6P (B)) CPU/6 CFG TeraNet.
• MPU12/13/14 are used for SPI0/1/2.
• MPU15 is used for USB1.
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and details of generic MPU registers, see the KeyStone Architecture Memory Protection Unit
(MPU) User's Guide ( SPRUGW5 ).
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The following tables show the configuration of each MPU and the memory regions protected by each
MPU.
Table 6-2. MPU0-MPU5 Default Configuration
SETTING
Default permission
MPU0 MPU1
MAIN SCR_3P QM_SS DATA
(B) PORT
Assume allowed Assume allowed
16 16 Number of allowed IDs supported
Number of programmable 16 ranges supported
Compare width
16
1KB granularity 1KB granularity
MPU2
QM_SS CFG1
PORT
Assume allowed
16
16
1KB granularity
MPU3
Reserved
MPU4
Reserved
MPU5
QM_SS CFG2
PORT
Assume allowed
16
16
1KB granularity
SETTING
Default permission
Number of allowed IDs supported
Number of programmable ranges supported
Compare width
MPU6
Reserved
Table 6-3. MPU6-MPU11 Default Configuration
MPU7
PCIe1
Assume allowed
16
MPU8
EMIF16
Assume allowed
16
MPU9
CIC
Assume allowed
16
16
1KB granularity
8
1KB granularity
4
MPU10
SM
Assume allowed
16
2
MPU11
SCR_6P (B)
Assume allowed
16
16
1KB granularity 1KB granularity 1KB granularity
SETTING
Default permission
Number of allowed IDs supported
Number of programmable ranges supported
Compare width
Table 6-4. MPU12-MPU15 Default Configuration
MPU12
SPI0
Assume allowed
16
2
MPU13
SPI1
Assume allowed
16
2
MPU14
SPI2
Assume allowed
16
2
1KB granularity 1KB granularity 1KB granularity
MPU15
USB1
Assume allowed
16
8
1KB granularity
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
MPU6
MPU7
MPU8
MPU9
MPU10
MPU11
MPU12
MPU13
MPU14
Table 6-5. MPU Memory Regions
MEMORY PROTECTION
Main CFG SCR
QM_SS DATA PORT
QM_SS CFG1 PORT
Reserved
Reserved
QM_SS CFG2 PORT
Reserved
PCIe1
SPIROM/EMIF16
CIC/AINTC
Semaphore
SCR_6 and CPU/6 CFG SCR
SPI0
SPI1
SPI2
START ADDRESS
0x01D0_0000
0x23A0_0000
0x02A0_0000
N/A
N/A
0x02A0_4000
N/A
0x2101_0000
0x20B0_0000
0x0264_0000
0x0260_0000
0x0220_0000
0x2100_0400
0x2100_0400
0x2100_0800
END ADDRESS
0X01E7_FFFF
0x23BF_FFFF
0x02AF_FFFF
N/A
N/A
0x02BF_FFFF
N/A
0xFFFF_FFFF
0x3FFF_FFFF
0x0264_07FF
0x0260_9FFF
0x03FF_FFFF
0x2100_07FF
0x2100_07FF
0x2100_0AFF
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MPU15
Table 6-5. MPU Memory Regions (continued)
MEMORY PROTECTION
USB1
START ADDRESS
0x2400_0000
END ADDRESS
0x2508_FFFF
shows the unique Master ID assigned to each CorePac and peripherals on the device.
Table 6-6. Master ID Settings
Reserved
Reserved
Reserved
EDMA0_TC0 read
EDMA0_TC0 write
EDMA0_TC1 read
Hyperlink0
USB1
Reserved
PCIe0
EDMA0_TC1 write
EDMA1_TC0 read
EDMA1_TC0 write
EDMA1_TC1 read
EDMA1_TC1write
EDMA1_TC2 read
EDMA1_TC2 write
EDMA1_TC3 read
EDMA1_TC3 write
EDMA2_TC0 read
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AM5K2E0x
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM CorePac 0
ARM CorePac1
ARM CorePac 2
ARM CorePac 3
37
38
39
40
41
32
33
34
35
36
27
28
29
30
31
22
23
24
25
26
17
18
19
20
21
12
13
14
15
16
7
8
9
5
6
10
11
1
2
3
4
Master ID
0
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Table 6-6. Master ID Settings (continued)
EDMA3CC2
Reserved
Reserved
Reserved
Queue Manager
NETCP_GLOBAL1
Reserved
TSIP
Reserved
Reserved
Reserved
10GbE
Reserved
Reserved
Packet DMA MST1
Reserved
PCIe1
Reserved
Reserved
Reserved
Reserved
DBG_DAP
Reserved
NETCP_LOCAL
Reserved
Reserved
AM5K2E0x
EDMA2_TC0 write
EDMA2_TC1 read
EDMA2_TC1 write
EDMA2_TC2 read
EDMA2_TC2 write
EDMA2_TC3 read
EDMA2_TC3 write
EDMA3_TC0 read
EDMA3_TC0 write
EDMA3_TC1 read
Reserved
EDMA3_TC1 write
Reserved
USB0
Reserved
Reserved
Reserved
Reserved
Reserved
EDMA3CC0
EDMA3CC1
83
84-87
88-91
92-95
96-99
100-101
102
103
104
105
64
65
66
67
68-71
72-75
76-79
80
81
82
106
107
108-111
112-119
120-139
140
59
60
61
62
63
53
54-55
56
57
58
48
49
50
51
52
Master ID
42
43
44
45
46
47
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172
173
174
175
176
177
178
179
180-183
184-255
167
168
169
170
171
162
163
164
165
166
157
158
159
160
161
152
153
154
155
156
147
148
149
150
151
Master ID
141
142
143
144
145
146
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Table 6-6. Master ID Settings (continued)
AM5K2E0x
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPT_MSMC0
CPT_MSMC1
CPT_MSMC2
CPT_MSMC3
CPT_DDR3
CPT_SM
CPT_QM_CFG1
CPT_QM_M
CPT_CFG
Reserved
Reserved
Reserved
CPT_QM_CFG2
CPT_PCIe1
Reserved
Reserved
CPT_EDMA3CC0_4
CPT_EDMA3CC1_2_3
CPT_CIC
CPT_SPI_ROM_EMIP16
Reserved
EDMA4_TC0 read
EDMA4_TC0 write
EDMA4_TC1 read
EDMA4_TC1 write
EDMA4_CC_TR
CPT_MSMC7
CPT_MSMC6
CPT_MSMC5
CPT_MSMC4
CPT_NETCP_CFG_MST
Reserved
NETCP_GLOBAL0
Reserved
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shows the privilege ID of each mastering peripheral. The table also shows the privilege level
(supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs.
data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.
10
11
12
13
14
15
7
8
9
5
6
1
2
3
4
PRIVILEGE ID MASTER
0 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM CorePac
All packet DMA masters
(Both NetCP, Both
QM_CDMA) Both USB
QM_SECOND
PCIe0
DAP
PCIe1
Hyperlink
TSIP
Table 6-7. Privilege ID Settings
PRIVILEGE LEVEL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
User/Supervisor (S/W dependent)
User
User
User/Supervisor
User/Supervisor (Emulation S/W dependent)
User/Supervisor
User/Supervisor
User
Data
Data
Data
Data
Data
Data
ACCESS TYPE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Instruction/Data
Data
6.2.1
MPU Registers
This section includes the offsets for MPU registers and definitions for device-specific MPU registers. For
Number of Programmable Ranges supported (PROGx_MPSA, PROGxMPEA) refer to the following tables.
6.2.1.1
MPU Register Map
208h
210h
214h
218h
220h
224h
228h
18h
1Ch
20h
200h
204h
OFFSET
0h
4h
10h
14h
NAME
REVID
CONFIG
IRAWSTAT
IENSTAT
IENSET
IENCLR
EOI
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPAR
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPAR
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPAR
Table 6-8. MPU Registers
DESCRIPTION
Revision ID
Configuration
Interrupt raw status/set
Interrupt enable status/clear
Interrupt enable
Interrupt enable clear
End of interrupt
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
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2F0h
2F4h
2F8h
300h
304h
308h
2D4h
2Dh
2E0h
2E4h
2E8h
2A0h
2A4h
2A8h
2B0h
2B4h
2B8h
2C0h
2C4h
2C8h
2D0h
284h
288h
290h
294h
298h
268h
270h
274h
278h
280h
250h
254h
258h
260h
264h
OFFSET
230h
234h
238h
240h
244h
248h
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPAR
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPAR
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPAR
PROG13_MPSAR
PROG13_MPEAR
PROG13_MPPAR
PROG14_MPSAR
PROG14_MPEAR
PROG14_MPPAR
PROG15_MPSAR
PROG15_MPEAR
PROG15_MPPAR
FLTADDRR
FLTSTAT
FLTCLR
NAME
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPAR
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPAR
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPAR
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPAR
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPAR
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPAR
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPAR
Table 6-8. MPU Registers (continued)
DESCRIPTION
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Programmable range 13, start address
Programmable range 13, end address
Programmable range 13, memory page protection attributes
Programmable range 14, start address
Programmable range 14, end address
Programmable range 14, memory page protection attributes
Programmable range 15, start address
Programmable range 15, end address
Programmable range 15, memory page protection attributes
Fault address
Fault status
Fault clear
6.2.1.2
Device-Specific MPU Registers
6.2.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
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Table 6-9. Configuration Register Field Descriptions
Bits
31-24
Field
ADDR_WIDTH
Description
Address alignment for range checking
• 0 = 1KB alignment
• 6 = 64KB alignment
23-20 NUM_FIXED
19-16 NUM_PROG
15-12 NUM_AIDS
11-1 Reserved
0
Number of fixed address ranges
Number of programmable address ranges
Number of supported AIDs
Reserved. Always read as 0.
ASSUME_ALLOWED Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not.
• 0 = Assume disallowed
• 1 = Assume allowed
6.2.2
MPU Programmable Range Registers
6.2.2.1
Programmable Range n Start Address Register (PROGn_MPSAR)
The Programmable Address Start Register holds the start address for the range. This register is writeable by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register, then the register is also writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines the width of the address field in MPSAR and MPEAR.
Figure 6-1. Programmable Range n Start Address Register (PROGn_MPSAR)
10 9 31
START_ADDR
R/W
Legend: R = Read only; R/W = Read/Write
Reserved
R
0
Bit
31-10
9-0
Table 6-10. Programmable Range n Start Address Register Field Descriptions
Field
START_ADDR
Reserved
Description
Start address for range n
Reserved. Always read as 0.
Table 6-11. MPU0-MPU5 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
REGISTER
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
MPU0
0x01D0_0000
0x01F0_0000
0x02F0_0000
0x0200_0000
0x020C_0000
0x021C_0000
0x021D_0000
0x021F_0000
0x0234_0000
0x0254_0000
0x0258_0000
0x0000_0000
0x0290_0000
0x01E8_0000
MPU1
0x23A0_0000
0x23A0_2000
0x023A_6000
0x23A0_6800
0x23A0_7000
0x23A0_8000
MPU2
0x02A0_0000
0x02A0_2000
0x02A0_6000
0x02A0_6800
0x02A0_7000
0x02A0_8000
0x23A0_C000 0x02A0_C000
0x23A0_E000
0x23A0_F000
0x02A0_E000
0x02A0_F000
0x23A0_F800
0x23A1_0000
0x02A0_F800
0x02A1_0000
0x23A1_C000 0x02A2_0000
0x23A4_0000
0x23A8_0000
0x02A4_0000
0x02A8_0000
MPU3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU5
0x02A0_4000
0x02A0_5000
0x02A0_6400
0x02A0_7400
0x02A0_A000
0x02A0_D000
0x02A0_E000
0x02A0_F000
0x02A0_F800
0x02A1_2000
0x02A1_C000
0x02A2_8000
0x02A6_0000
0x02AA_0000
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Table 6-11. MPU0-MPU5 Programmable Range n Start Address Register (PROGn_MPSAR) Reset
Values (continued)
REGISTER
PROG14_MPSAR
PROG15_MPSAR
MPU0
0x01E8_0800
0x01E0_0000
MPU1
0x23B0_0000
0x23B8_0000
MPU2
0x02AC_0000
0x02AE_0000
MPU3
Reserved
Reserved
MPU4
Reserved
Reserved
MPU5
0x02B0_0000
0x02B8_0000
Table 6-12. MPU6-MPU11 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
REGISTER
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
PROG14_MPSAR
PROG15_MPSAR
MPU6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU7
0x2101_0000
0x0000_0000
0x0800_0000
0x1000_0000
0x1800_0000
0x2000_0000
0x2800_0000
0x3000_0000
0x3800_0000
0x4000_0000
0x4800_0000
0x5000_0000
0x5800_0000
0x6000_0000
0x6800_0000
0x7000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU8
0x3000_0000
0x3200_0000
0x3400_0000
0x3600_0000
0x3800_0000
0x3A00_0000
0x3C00_0000
0x2100_0800
MPU9
0x0260_0000
0x0260_4000
0x0260_8000
0x0256_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU10
0x0264_0000
0x0000_0000
N/A
MPU11
0x0220_0000
0x0231_0000
0x0231_A000
0x0233_0000
0x0235_0000
0x0263_0000
0x0244_0000
0x024C_0000
0x0250_0000
0x0253_0000
0x0253_0C00
0x0260_B000
0x0262_0000
0x0300_0000
0x021E_0000
0x0268_0000
Table 6-13. MPU12-MPU15 Programmable Range n Start Address Register (PROGn_MPSAR) Reset
Values
REGISTER
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
PROG14_MPSAR
PROG15_MPSAR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU12
0x2100_0400
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU13
0x2100_0400
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU14
0x2100_0800
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU15
0x2400_0000
0x2408_0000
0x2410_0000
0x2500_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
N/A
6.2.2.2
Programmable Range n - End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register then the register is also writeable only by a secure entity.
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The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field in MPSAR and MPEAR.
Figure 6-2. Programmable Range n End Address Register (PROGn_MPEAR)
10 9 31
END_ADDR
R/W
Legend: R = Read only; R/W = Read/Write
Reserved
R
0
Bit
31-10
9-0
Field
END_ADDR
Reserved
Table 6-14. Programmable Range n End Address Register Field Descriptions
Description
End address for range n
Reserved. Always read as 3FFh.
Table 6-15. MPU0-MPU5 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
REGISTER
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
MPU0
0x01DF_FFFF
0x01F7_FFFF
0x02FF_FFFF
0x020B_FFFF
0x020F_FFFF
0x021C_83FF
0x021D_C0FF
0x021F_C7FF
0x0234_C0FF
0x0255_FFFF
0x025F_FFFF
0x0000_0000
0x029F_FFFF
0x01E8_07FF
0x01E8_43FF
0x01E7_FFFF
MPU1
0x23A0_1FFF
0x23A0_5FFF
0x23A0_67FF
0x23A0_6FFF
0x23A0_7FFF
0x23A0_BFFF
0x23A0_DFFF
0x23A0_EFFF
0x23A0_F7FF
0x23A0_FFFF
0x23A1_BFFF
0x23A3_FFFF
0x23A7_FFFF
0x23AF_FFFF
0x23B7_FFFF
0x23BF_FFFF
MPU2
0x02A0_00FF
0x02A0_3FFF
0x02A0_63FF
0x02A0_6FFF
0x02A0_73FF
0x02A0_9FFF
0x02A0_CFFF
0x02A0_E7FF
0x02A0_F7FF
0x02A0_FFFF
0x02A1_1FFF
0x02A2_5FFF
0x02A5_FFFF
0x02A9_FFFF
0x02AD_FFFF
0x02AF_FFFF
MPU3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU5
0x02A0_4FFF
0x02A0_5FFF
0x02A0_67FF
0x02A0_7FFF
0x02A0_BFFF
0x02A0_DFFF
0x02A0_E7FF
0x02A0_F7FF
0x02A0_FFFF
0x02A1_7FFF
0x02A1_FFFF
0x02A3_FFFF
0x02A7_FFFF
0x02AB_FFFF
0x02B7_FFFF
0x02BF_FFFF
Table 6-16. MPU6-MPU11 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
REGISTER
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
MPU6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU7
0x2103_FFFF
0x07FF_FFFF
0x0FFF_FFFF
0x17FF_FFFF
0x1FFF_FFFF
0x27FF_FFFF
0x2FFF_FFFF
0x37FF_FFFF
0x3FFF_FFFF
0x47FF_FFFF
0x4FFF_FFFF
0x57FF_FFFF
0x5FFF_FFFF
N/A
N/A
N/A
N/A
MPU8
0x31FF_FFFF
0x33FF_FFFF
0x35FF_FFFF
0x37FF_FFFF
0x39FF_FFFF
0x3BFF_FFFF
0x3FFF_FFFF
0x2100_0AFF
N/A
MPU9 MPU10 MPU11
0x0260_1FFF 0x0264_07FF 0x022F_027F
0x0260_5FFF 0x0000_0000 0x0231_01FF
0x0260_9FFF N/A
0x0257_FFFF N/A
0x0232_FFFF
0x0233_07FF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0235_0FFF
0x0263_FFFF
0x024B_3FFF
0x024C_0BFF
0x0250_7FFF
0x0253_0BFF
0x0253_FFFF
0x0260_BFFF
0x0262_0FFF
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Table 6-16. MPU6-MPU11 Programmable Range n End Address Register (PROGn_MPEAR) Reset
Values (continued)
REGISTER
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
MPU6
Reserved
Reserved
Reserved
MPU7
0x67FF_FFFF
0x6FFF_FFFF
0x7FFF_FFFF
MPU8
N/A
N/A
N/A
MPU9
0x0000_0000
0x0000_0000
0x0000_0000
MPU10
N/A
N/A
N/A
MPU11
0x03FF_FFFF
0x021E_1FFF
0x026F_FFFF
Table 6-17. MPU12-MPU15 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
REGISTER
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU12
0x2100_07FF
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU13
0x2100_07FF
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU14
0x2100_0AFF
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU15
0x2407_FFFF
0x240F_FFFF
0x24FF_FFFF
0x2507_FFFF
0x2508FFFF
0x0000_0000
0x0000_0000
0x0000_0000
N/A
N/A
N/A
N/A
6.2.2.3
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
The programmable address memory protection page attribute register holds the permissions for the region. This register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also writeable only by a non-debug secure entity. The NS bit is writeable only by a non-debug secure entity. For debug accesses, the register is writeable only when NS = 1 or EMU = 1.
Figure 6-3. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
31
14 13
Reserved
R
12 11
26
10
25
AID15
R/W
9
AID4 AID3 AID2 AID1 AID0 AIDX
24
AID14
R/W
8
23
AID13
R/W
Reserved
22
AID12
R/W
7
NS
21
AID11
R/W
6
EMU
20
AID10
R/W
5
SR
19
AID9
R/W
4
SW
18
AID8
R/W
3
SX
17
AID7
R/W
2
UR
16
AID6
R/W
1
UW
15
AID5
R/W
0
UX
R/W R/W R/W R/W R/W
Legend: R = Read only; R/W = Read/Write
R/W R R/W R/W R/W R/W R/W R/W R/W R/W
Bits
31-26
25
24
Table 6-18. Programmable Range n Memory Protection Page Attribute Register Field Descriptions
Name
Reserved
AID15
AID14
Description
Reserved. Always read as 0.
Controls access from ID = 15
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 14
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
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8
7
Bits
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Table 6-18. Programmable Range n Memory Protection Page Attribute Register Field Descriptions
(continued)
Name
AID13
AID12
AID11
AID10
AID9
AID8
AID7
AID6
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Reserved
NS
Description
Controls access from ID = 13
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 12
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 11
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 10
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 9
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 8
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 7
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 6
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 5
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 4
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 3
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 2
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 1
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID = 0
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Controls access from ID > 15
• 0 = Access is not checked for permissions
• 1 = Access is checked for permissions
Reserved. Always reads as 0.
Non-secure access permission
• 0 = Only secure access allowed
• 1 = Non-secure access allowed
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Bits
6
5
4
3
2
1
0
Table 6-18. Programmable Range n Memory Protection Page Attribute Register Field Descriptions
(continued)
Name
EMU
SR
SW
SX
UR
UW
UX
Description
Emulation (debug) access permission. This bit is ignored if NS = 1
• 0 = Debug access not allowed
• 1 = Debug access allowed
Supervisor Read permission
• 0 = Access not allowed
• 1 = Access allowed
Supervisor Write permission
• 0 = Access not allowed
• 1 = Access allowed
Supervisor Execute permission
• 0 = Access not allowed
• 1 = Access allowed
User Read permission
• 0 = Access not allowed
• 1 = Access allowed
User Write permission
• 0 = Access not allowed
• 1 = Access allowed
User Execute permission
• 0 = Access not allowed
• 1 = Access allowed
Table 6-19. MPU0-MPU5 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values
REGISTER
PROG0_MPPAR
PROG1_MPPAR
PROG2_MPPAR
PROG3_MPPAR
PROG4_MPPAR
PROG5_MPPAR
PROG6_MPPAR
PROG7_MPPAR
PROG8_MPPAR
PROG9_MPPAR
PROG10_MPPAR
PROG11_MPPAR
PROG12_MPPAR
PROG13_MPPAR
PROG14_MPPAR
PROG15_MPPAR
MPU0
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
MPU1 MPU2
0x03FF_FCB6 0x03FF_FCB6
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCA4 0x03FF_FCA4
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCF4 0x03FF_FCF4
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCF4 0x03FF_FCF4
0x03FF_FCB4 0x03FF_FCB4
0x03FF_FCF4 0x03FF_FCF4
0x03FF_FCA4 0x03FF_FCA4
0x03FF_FCB6 0x03FF_FCB6
0x03FF_FCA4 0x03FF_FCB6
0x03FF_FCA4 0x03FF_FCB6
MPU3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU5
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCA4
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCF4
0x03FF_FCA4
0x03FF_FCB6
0x03FF_FCA4
0x03FF_FCA4
Table 6-20. MPU6-MPU11 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values
REGISTER
PROG0_MPPAR
PROG1_MPPAR
PROG2_MPPAR
MPU6
Reserved
Reserved
Reserved
MPU7 MPU8
0x03FF_FCB6 0x03FF_FCBF
0x03FF_FCBF 0x03FF_FCBF
0x03FF_FCBF 0x03FF_FCBF
MPU9 MPU10 MPU11
0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6
0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB0
0x03FF_FCB6 N/A 0x03FF_FCB6
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Table 6-20. MPU6-MPU11 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values (continued)
REGISTER
PROG3_MPPAR
PROG4_MPPAR
PROG5_MPPAR
PROG6_MPPAR
PROG7_MPPAR
PROG8_MPPAR
PROG9_MPPAR
PROG10_MPPAR
PROG11_MPPAR
PROG12_MPPAR
PROG13_MPPAR
PROG14_MPPAR
PROG15_MPPAR
MPU6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU7 MPU8
0x03FF_FCBF 0x03FF_FCBF
0x03FF_FCBF 0x03FF_FCBF
0x03FF_FCBF 0x03FF_FCBF
0x03FF_FCBF 0x03FF_FCBF
0x03FF_FCBF 0x03FF_FCB6
0x03FF_FCBF N/A
0x03FF_FCBF N/A
0x03FF_FCBF N/A
0x03FF_FCBF N/A
0x03FF_FCBF N/A
0x03FF_FCBF N/A
0x03FF_FCBF N/A
0x03FF_FCBF N/A
MPU9 MPU10
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
MPU11
0x03FF_FCB0
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
Table 6-21. MPU12-MPU15 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values
REGISTER
PROG0_MPPAR
PROG1_MPPAR
PROG2_MPPAR
PROG3_MPPAR
PROG4_MPPAR
PROG5_MPPAR
PROG6_MPPAR
PROG7_MPPAR
PROG8_MPPAR
PROG9_MPPAR
PROG10_MPPAR
PROG11_MPPAR
PROG12_MPPAR
PROG13_MPPAR
PROG14_MPPAR
PROG15_MPPAR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU12
0x03FF_FCB6
0x03FF_FCBF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU13
0x03FF_FCB6
0x03FF_FCBF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU14
0x03FF_FCB6
0x03FF_FCBF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MPU15
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
N/A
N/A
N/A
N/A
6.3
Interrupts for AM5K2E0x
This section discusses the interrupt sources, controller, and topology. Also provided are tables describing the interrupt events.
6.3.1
Interrupt Sources and Interrupt Controller
The ARM CorePac interrupts on the AM5K2E0x device are configured through the ARM CorePac Interrupt
Controller. It allows for up to 480 system events to be programmed to any of the ARM core’s IRQ/FIQ interrupts. In addition error-class events or infrequently used events are also routed through the system event router to offload the ARM CorePac interrupt controller. This is accomplished through the CorePac
Interrupt Controller block CIC2. Further, CIC2 provides 8 events each to EDMA3CC0, EDMA3CC1,
EDMA3C2, EDMA3CC3, EDMA3CC4, and Hyperlink.
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Modules such as CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI handshaking interface. The EOI value is 0 for CP_MPU, BOOT_CFG, and CP_Tracer.
shows the AM5K2E0x interrupt topology.
11
12
13
14
15
16
17
18
19
6
7
8
9
10
1
2
3
4
5
EVENT NO.
0
AM5K2E
479 Events CIC2
448 Primary Events
32 Secondary Events †
56 Primary Events
8 Secondary Events
56 Primary Events
8 Secondary Events †
ARM
INTC
HyperLink
EDMA3
CC0
56 Primary Events
8 Secondary Events †
56 Primary Events
8 Secondary Events †
56 Primary Events
8 Secondary Events †
EDMA3
CC1
EDMA3
CC2
EDMA3
CC3
56 Primary Events
8 Secondary Events †
EDMA3
CC4
† ARM shares two secondary events with every instance of EDMA.
Figure 6-4. Interrupt Topology
lists the ARM CorePac event inputs
Table 6-22. System Event Mapping — ARM CorePac Interrupts
EVENT NAME
RSTMUX_INT8
RSTMUX_INT9
RSTMUX_INT10
RSTMUX_INT11
IPC_GR8
IPC_GR9
IPC_GR10
IPC_GR11
SEM_INT8
SEM_INT9
SEM_INT10
SEM_INT11
SEM_ERR8
SEM_ERR9
SEM_ERR10
SEM_ERR11
MSMC_MPF_ERROR8
MSMC_MPF_ERROR9
MSMC_MPF_ERROR10
MSMC_MPF_ERROR11
DESCRIPTION
Boot config watchdog timer expiration (timer 16) event for ARM core 0
Boot config watchdog timer expiration (timer 17) event for ARM core 1
Boot config watchdog timer expiration (timer 18) event for ARM core 2
Boot config watchdog timer expiration (timer 19) event for ARM core 3
Boot config IPCG
Boot config IPCG
Boot config IPCG
Boot config IPCG
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Memory protection fault indicators for system master PrivID = 8
Memory protection fault indicators for system master PrivID = 9
Memory protection fault indicators for system master PrivID = 10
Memory protection fault indicators for system master PrivID = 11
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56
57
58
59
60
51
52
53
54
55
64
65
66
61
62
63
46
47
48
49
50
41
42
43
44
45
36
37
38
39
40
31
32
33
34
35
26
27
28
29
30
EVENT NO.
20
21
22
23
24
25
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NAME
ARM_NPMUIRQ0
ARM_NPMUIRQ1
ARM_NPMUIRQ2
ARM_NPMUIRQ3
ARM_NINTERRIRQ
ARM_NAXIERRIRQ
PCIE_0_INT0
PCIE_0_INT1
PCIE_0_INT2
PCIE_0_INT3
PCIE_0_INT4
PCIE_0_INT5
PCIE_0_INT6
PCIE_0_INT7
PCIE_0_INT8
PCIE_0_INT9
PCIE_0_INT10
PCIE_0_INT11
PCIE_0_INT12
PCIE_0_INT13
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
QMSS_QUE_PEND_528
QMSS_QUE_PEND_529
QMSS_QUE_PEND_530
QMSS_QUE_PEND_531
QMSS_QUE_PEND_532
QMSS_QUE_PEND_533
QMSS_QUE_PEND_534
QMSS_QUE_PEND_535
QMSS_QUE_PEND_536
QMSS_QUE_PEND_537
QMSS_QUE_PEND_538
QMSS_QUE_PEND_539
QMSS_QUE_PEND_540
QMSS_QUE_PEND_541
QMSS_QUE_PEND_542
QMSS_QUE_PEND_543
QMSS_QUE_PEND_544
QMSS_QUE_PEND_545
QMSS_QUE_PEND_546
DESCRIPTION
ARM performance monitoring unit interrupt request
ARM performance monitoring unit interrupt request
ARM performance monitoring unit interrupt request
ARM performance monitoring unit interrupt request
ARM internal memory ECC error interrupt request
ARM bus error interrupt request
PCIE0 legacy INTA interrupt
PCIE0 legacy INTB interrupt
PCIE0 legacy INTC interrupt
PCIE0 legacy INTD interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 error interrupt
PCIE0 power management interrupt
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Copyright © 2012–2015, Texas Instruments Incorporated
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103
104
105
106
107
98
99
100
101
102
108
109
110
111
112
113
93
94
95
96
97
88
89
90
91
92
83
84
85
86
87
78
79
80
81
82
73
74
75
76
77
EVENT NO.
67
68
69
70
71
72
80
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
TSIP_XMT_SFINT0
TSIP_EINT0
TSIP_RCV_FINT1
TSIP_XMT_FINT1
TSIP_RCV_SFINT1
TSIP_XMT_SFINT1
TSIP_EINT1
Reserved
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
TIMER_16_INTL
TIMER_16_INTH
EVENT NAME
QMSS_QUE_PEND_547
QMSS_QUE_PEND_548
QMSS_QUE_PEND_549
QMSS_QUE_PEND_550
QMSS_QUE_PEND_551
QMSS_QUE_PEND_552
QMSS_QUE_PEND_553
QMSS_QUE_PEND_554
QMSS_QUE_PEND_555
QMSS_QUE_PEND_556
QMSS_QUE_PEND_557
QMSS_QUE_PEND_558
QMSS_QUE_PEND_559
Reserved
Reserved
USIM_PONIRQ
USIM_RREQ
USIM_WREQ
TSIP_RCV_FINT0
TSIP_XMT_FINT0
TSIP_RCV_SFINT0
DESCRIPTION
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Reserved
Reserved
USIM interrupt
USIM read DMA event
USIM write DMA event
TSIP receive frame interrupt for channel 0
TSIP transmit frame interrupt for channel 0
TSIP receive super frame interrupt for channel 0
TSIP transmit super frame interrupt for channel 0
TSIP error interrupt for channel 0
TSIP receive frame interrupt for channel 1
TSIP transmit frame interrupt for channel 1
TSIP receive super frame interrupt for channel 1
TSIP transmit super frame interrupt for channel 1
TSIP error interrupt for channel 1
Reserved
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Memory, Interrupts, and EDMA for AM5K2E0x
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150
151
152
153
154
145
146
147
148
149
155
156
157
158
159
160
140
141
142
143
144
135
136
137
138
139
130
131
132
133
134
125
126
127
128
129
120
121
122
123
124
EVENT NO.
114
115
116
117
118
119
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
GPIO_INT15
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
USB_0_INT00
USB_0_INT01
USB_0_INT02
USB_0_INT03
USB_0_INT04
USB_0_INT05
USB_0_INT06
USB_0_INT07
USB_0_INT08
EVENT NAME
TIMER_17_INTL
TIMER_17_INTH
TIMER_18_INTL
TIMER_18_INTH
TIMER_19_INTL
TIMER_19_INTH
GPIO_INT0
GPIO_INT1
GPIO_INT2
GPIO_INT3
GPIO_INT4
GPIO_INT5
GPIO_INT6
GPIO_INT7
GPIO_INT8
GPIO_INT9
GPIO_INT10
GPIO_INT11
GPIO_INT12
GPIO_INT13
GPIO_INT14
DESCRIPTION
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
USB 0 event ring 0 interrupt
USB 0 event ring 1 interrupt
USB 0 event ring 2 interrupt
USB 0 event ring 3 interrupt
USB 0 event ring 4 interrupt
USB 0 event ring 5 interrupt
USB 0 event ring 6 interrupt
USB 0 event ring 7 interrupt
USB 0 event ring 8 interrupt
Copyright © 2012–2015, Texas Instruments Incorporated
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197
198
199
200
201
192
193
194
195
196
202
203
204
205
206
207
187
188
189
190
191
182
183
184
185
186
177
178
179
180
181
172
173
174
175
176
167
168
169
170
171
EVENT NO.
161
162
163
164
165
166
82
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NAME
USB_0_INT09
USB_0_INT10
USB_0_INT11
USB_0_INT12
USB_0_INT13
USB_0_INT14
USB_0_INT15
USB_0_OABSINT
USB_0_MISCINT
MSMC_DEDC_CERROR
MSMC_DEDC_NC_ERROR
DESCRIPTION
USB 0 event ring 9 interrupt
USB 0 event ring 10 interrupt
USB 0 event ring 11 interrupt
USB 0 event ring 12 interrupt
USB 0 event ring 13 interrupt
USB 0 event ring 14 interrupt
USB 0 event ring 15 interrupt
USB 0 OABS interrupt
USB0_misc_int
MSMC interrupt
MSMC interrupt
MSMC_DEDC_SCRUB_CERROR MSMC interrupt
MSMC_DEDC_SCRUB_NC_ERROR MSMC interrupt
Reserved Reserved
Reserved
QMSS1_ECC_INTR
Reserved
Navigator ECC error interrupt
QMSS_INTD_1_PKTDMA_0
QMSS_INTD_1_PKTDMA_1
QMSS_INTD_1_HIGH_0
QMSS_INTD_1_HIGH_1
QMSS_INTD_1_HIGH_2
Navigator interrupt for Packet DMA starvation
Navigator interrupt for Packet DMA starvation
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
QMSS_INTD_1_HIGH_3
QMSS_INTD_1_HIGH_4
QMSS_INTD_1_HIGH_5
QMSS_INTD_1_HIGH_6
QMSS_INTD_1_HIGH_7
QMSS_INTD_1_HIGH_8
QMSS_INTD_1_HIGH_9
QMSS_INTD_1_HIGH_10
QMSS_INTD_1_HIGH_11
QMSS_INTD_1_HIGH_12
QMSS_INTD_1_HIGH_13
QMSS_INTD_1_HIGH_14
QMSS_INTD_1_HIGH_15
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_17
QMSS_INTD_1_HIGH_18
QMSS_INTD_1_HIGH_19
QMSS_INTD_1_HIGH_20
QMSS_INTD_1_HIGH_21
QMSS_INTD_1_HIGH_22
QMSS_INTD_1_HIGH_23
QMSS_INTD_1_HIGH_24
QMSS_INTD_1_HIGH_25
QMSS_INTD_1_HIGH_26
QMSS_INTD_1_HIGH_27
QMSS_INTD_1_HIGH_28
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Memory, Interrupts, and EDMA for AM5K2E0x
Copyright © 2012–2015, Texas Instruments Incorporated
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244
245
246
247
248
239
240
241
242
243
249
250
251
252
253
254
234
235
236
237
238
229
230
231
232
233
224
225
226
227
228
219
220
221
222
223
214
215
216
217
218
EVENT NO.
208
209
210
211
212
213
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NAME
QMSS_INTD_1_HIGH_29
QMSS_INTD_1_HIGH_30
QMSS_INTD_1_HIGH_31
QMSS_INTD_1_LOW_0
QMSS_INTD_1_LOW_1
QMSS_INTD_1_LOW_2
QMSS_INTD_1_LOW_3
QMSS_INTD_1_LOW_4
QMSS_INTD_1_LOW_5
QMSS_INTD_1_LOW_6
QMSS_INTD_1_LOW_7
QMSS_INTD_1_LOW_8
QMSS_INTD_1_LOW_9
QMSS_INTD_1_LOW_10
QMSS_INTD_1_LOW_11
QMSS_INTD_1_LOW_12
QMSS_INTD_1_LOW_13
QMSS_INTD_1_LOW_14
QMSS_INTD_1_LOW_15
Reserved
Reserved
QMSS_INTD_2_HIGH_0
QMSS_INTD_2_HIGH_1
QMSS_INTD_2_HIGH_2
QMSS_INTD_2_HIGH_3
QMSS_INTD_2_HIGH_4
QMSS_INTD_2_HIGH_5
QMSS_INTD_2_HIGH_6
QMSS_INTD_2_HIGH_7
QMSS_INTD_2_HIGH_8
QMSS_INTD_2_HIGH_9
QMSS_INTD_2_HIGH_10
QMSS_INTD_2_HIGH_11
QMSS_INTD_2_HIGH_12
QMSS_INTD_2_HIGH_13
QMSS_INTD_2_HIGH_14
QMSS_INTD_2_HIGH_15
QMSS_INTD_2_HIGH_16
QMSS_INTD_2_HIGH_17
QMSS_INTD_2_HIGH_18
QMSS_INTD_2_HIGH_19
QMSS_INTD_2_HIGH_20
QMSS_INTD_2_HIGH_21
QMSS_INTD_2_HIGH_22
QMSS_INTD_2_HIGH_23
QMSS_INTD_2_HIGH_24
QMSS_INTD_2_HIGH_25
DESCRIPTION
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Reserved
Reserved
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Copyright © 2012–2015, Texas Instruments Incorporated
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291
292
293
294
295
286
287
288
289
290
296
297
298
299
300
301
281
282
283
284
285
276
277
278
279
280
271
272
273
274
275
266
267
268
269
270
261
262
263
264
265
EVENT NO.
255
256
257
258
259
260
84
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NAME
QMSS_INTD_2_HIGH_26
QMSS_INTD_2_HIGH_27
QMSS_INTD_2_HIGH_28
QMSS_INTD_2_HIGH_29
QMSS_INTD_2_HIGH_30
QMSS_INTD_2_HIGH_31
QMSS_INTD_2_LOW_0
QMSS_INTD_2_LOW_1
QMSS_INTD_2_LOW_2
QMSS_INTD_2_LOW_3
QMSS_INTD_2_LOW_4
QMSS_INTD_2_LOW_5
QMSS_INTD_2_LOW_6
QMSS_INTD_2_LOW_7
QMSS_INTD_2_LOW_8
QMSS_INTD_2_LOW_9
QMSS_INTD_2_LOW_10
QMSS_INTD_2_LOW_11
QMSS_INTD_2_LOW_12
QMSS_INTD_2_LOW_13
QMSS_INTD_2_LOW_14
QMSS_INTD_2_LOW_15
UART_0_UARTINT
UART_0_URXEVT
UART_0_UTXEVT
UART_1_UARTINT
UART_1_URXEVT
UART_1_UTXEVT
I2C_0_INT
I2C_0_REVT
I2C_0_XEVT
I2C_1_INT
I2C_1_REVT
I2C_1_XEVT
I2C_2_INT
I2C_2_REVT
I2C_2_XEVT
SPI_0_INT0
SPI_0_INT1
SPI_0_XEVT
SPI_0_REVT
SPI_1_INT0
SPI_1_INT1
SPI_1_XEVT
SPI_1_REVT
SPI_2_INT0
SPI_2_INT1
DESCRIPTION
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
UART0 interrupt
UART0 receive event
UART0 transmit event
UART1 interrupt
UART1 receive event
UART1 transmit event
I2C interrupt
I2C receive event
I2C transmit event
I2C interrupt
I2C receive event
I2C transmit event
I2C interrupt
I2C receive event
I2C transmit event
SPI interrupt
SPI interrupt
SPI DMA TX event
SPI DMA RX event
SPI interrupt
SPI interrupt
SPI DMA TX event
SPI DMA RX event
SPI interrupt
SPI interrupt
Memory, Interrupts, and EDMA for AM5K2E0x
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338
339
340
341
342
333
334
335
336
337
343
344
345
346
347
348
328
329
330
331
332
323
324
325
326
327
318
319
320
321
322
313
314
315
316
317
308
309
310
311
312
EVENT NO.
302
303
304
305
306
307
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EDMACC_1_GINT
EDMACC_1_TC_0_INT
EDMACC_1_TC_1_INT
EDMACC_1_TC_2_INT
EDMACC_1_TC_3_INT
EDMACC_1_TC_4_INT
EDMACC_1_TC_5_INT
EDMACC_1_TC_6_INT
EDMACC_1_TC_7_INT
EDMACC_2_GINT
EDMACC_2_TC_0_INT
EDMACC_2_TC_1_INT
EDMACC_2_TC_2_INT
EDMACC_2_TC_3_INT
EDMACC_2_TC_4_INT
EDMACC_2_TC_5_INT
EDMACC_2_TC_6_INT
EDMACC_2_TC_7_INT
EDMACC_3_GINT
EDMACC_3_TC_0_INT
EDMACC_3_TC_1_INT
EDMACC_3_TC_2_INT
EDMACC_3_TC_3_INT
EDMACC_3_TC_4_INT
EDMACC_3_TC_5_INT
EDMACC_3_TC_6_INT
EVENT NAME
SPI_2_XEVT
SPI_2_REVT
DBGTBR_DMAINT
DBGTBR_ACQCOMP
ARM_TBR_DMA
ARM_TBR_ACQ
NETCP_MDIO_LINK_INT0
NETCP_MDIO_LINK_INT1
NETCP_MDIO_USER_INT0
NETCP_MDIO_USER_INT1
NETCP_MISC_INT
Reserved
EDMACC_0_GINT
EDMACC_0_TC_0_INT
EDMACC_0_TC_1_INT
EDMACC_0_TC_2_INT
EDMACC_0_TC_3_INT
EDMACC_0_TC_4_INT
EDMACC_0_TC_5_INT
EDMACC_0_TC_6_INT
EDMACC_0_TC_7_INT
DESCRIPTION
SPI DMA TX event
SPI DMA RX event
Debug trace buffer (TBR) DMA event
Debug Trace buffer (TBR) acquisition has been completed
ARM Trace Buffer (TBR) DMA event
ARM Trace Buffer (TBR) Acquisition has been completed
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
EDMA3CC0 global completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC1 global completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC2 global completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC3 global completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for AM5K2E0x
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85
366
367
368
369
370
385
386
387
388
389
380
381
382
383
384
390
391
392
375
376
377
378
379
371
372
373
374
360
361
362
363
364
355
356
357
358
359
EVENT NO.
349
350
351
352
353
354
365
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
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Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NAME
EDMACC_3_TC_7_INT
EDMACC_4_GINT
EDMACC_4_TC_0_INT
EDMACC_4_TC_1_INT
EDMACC_4_TC_2_INT
EDMACC_4_TC_3_INT
EDMACC_4_TC_4_INT
EDMACC_4_TC_5_INT
EDMACC_4_TC_6_INT
EDMACC_4_TC_7_INT
SR_0_PO_VCON_SMPSERR_INT
SR_0_SMARTREFLEX_INTREQ0
SR_0_SMARTREFLEX_INTREQ1
SR_0_SMARTREFLEX_INTREQ2
SR_0_SMARTREFLEX_INTREQ3
SR_0_VPNOSMPSACK
SR_0_VPEQVALUE
SR_0_VPMAXVDD
SR_0_VPMINVDD
SR_0_VPINIDLE
SR_0_VPOPPCHANGEDONE
SR_0_VPSMPSACK
SR_0_SR_TEMPSENSOR
SR_0_SR_TIMERINT
PCIE_1_INT0
PCIE_1_INT1
PCIE_1_INT2
PCIE_1_INT3
PCIE_1_INT4
PCIE_1_INT5
PCIE_1_INT6
PCIE_1_INT7
PCIE_1_INT8
PCIE_1_INT9
PCIE_1_INT10
PCIE_1_INT11
PCIE_1_INT12
PCIE_1_INT13
HYPERLINK_0_INT
DDR3_ERR
ARM_NCTIIRQ0
ARM_NCTIIRQ1
ARM_NCTIIRQ2
ARM_NCTIIRQ3
DESCRIPTION
EDMA3CC3 individual completion interrupt
EDMA3CC4 global completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
SmartReflex SMPS error interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex VPVOLTUPDATE has been asserted, but SMPS has not been responded to in a defined time interval
SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
SmartReflex. The new voltage required is equal to or greater than MaxVdd
SmartReflex. The new voltage required is equal to or less than MinVdd
SmartReflex indicating that the FSM of voltage processor is in idle
SmartReflex indicating that the average frequency error is within the desired limit
SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
SmartReflex temperature threshold crossing interrupt
SmartReflex internal timer expiration interrupt
PCIE1 legacy INTA interrupt
PCIE1 legacy INTB interrupt
PCIE1 legacy INTC interrupt
PCIE1 legacy INTD interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 error interrupt
PCIE1 power management interrupt
HyperLink interrupt
DDR3 interrupt
ARM cross trigger (CTI) IRQ interrupt
ARM cross trigger (CTI) IRQ interrupt
ARM cross trigger (CTI) IRQ interrupt
ARM cross trigger (CTI) IRQ interrupt
86
Memory, Interrupts, and EDMA for AM5K2E0x
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429
430
431
432
433
424
425
426
427
428
434
435
436
437
438
439
419
420
421
422
423
414
415
416
417
418
409
410
411
412
413
404
405
406
407
408
399
400
401
402
403
EVENT NO.
393
394
395
396
397
398
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE_LINK_INT0
10GbE_USER_INT0
10GbE_LINK_INT1
10GbE_USER_INT1
10GbE_MISC_INT
10GbE_INT_PKTDMA_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USB_1_INT00
USB_1_INT01
USB_1_INT02
USB_1_INT03
USB_1_INT04
USB_1_INT05
USB_1_INT06
USB_1_INT07
USB_1_INT08
USB_1_INT09
USB_1_INT10
USB_1_INT11
USB_1_INT12
USB_1_INT13
USB_1_INT14
USB_1_INT15
USB_1_OABSINT
USB_1_MISCINT
NETCP_GLOBAL_STARVE
NETCP_LOCAL_STARVE
NETCP_PA_ECC_INT
NETCP_SA_ECC_INT
NETCP_SWITCH_ECC_INT
NETCP_SWITCH_STAT_INT0
NETCP_SWITCH_STAT_INT1
NETCP_SWITCH_STAT_INT2
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet Packet DMA starvation interrupt
USB 1 event ring 0 interrupt
USB 1 event ring 1 interrupt
USB 1 event ring 2 interrupt
USB 1 event ring 3 interrupt
USB 1 event ring 4 interrupt
USB 1 event ring 5 interrupt
USB 1 event ring 6 interrupt
USB 1 event ring 7 interrupt
USB 1 event ring 8 interrupt
USB 1 event ring 9 interrupt
USB 1 event ring 10 interrupt
USB 1 event ring 11 interrupt
USB 1 event ring 12 interrupt
USB 1 event ring 13 interrupt
USB 1 event ring 14 interrupt
USB 1 event ring 15 interrupt
USB 1 OABS interrupt
USB 1 miscellaneous interrupt
NETCP GLOBAL interrupt
NETCP LOCAL interrupt
NETCP PA ECC interrupt
NETCP SA ECC interrupt
NETCP SWITCH ECC interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
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471
472
473
474
475
476
477
478
479
466
467
468
469
470
461
462
463
464
465
456
457
458
459
460
451
452
453
454
455
446
447
448
449
450
EVENT NO.
440
441
442
443
444
445
lists the CIC2 event inputs.
Table 6-22. System Event Mapping — ARM CorePac Interrupts (continued)
CIC_2_OUT42
CIC_2_OUT43
CIC_2_OUT44
CIC_2_OUT45
CIC_2_OUT46
CIC_2_OUT47
CIC_2_OUT18
CIC_2_OUT19
CIC_2_OUT22
CIC_2_OUT23
CIC_2_OUT50
CIC_2_OUT51
CIC_2_OUT66
CIC_2_OUT67
CIC_2_OUT88
CIC_2_OUT89
CIC_2_OUT90
CIC_2_OUT91
CIC_2_OUT92
EVENT NAME
NETCP_SWITCH_STAT_INT3
NETCP_SWITCH_STAT_INT4
NETCP_SWITCH_STAT_INT5
NETCP_SWITCH_STAT_INT6
NETCP_SWITCH_STAT_INT7
NETCP_SWITCH_INT
NETCP_SWITCH_STAT_INT0
Reserved
CIC_2_OUT29
CIC_2_OUT30
CIC_2_OUT31
CIC_2_OUT32
CIC_2_OUT33
CIC_2_OUT34
CIC_2_OUT35
CIC_2_OUT36
CIC_2_OUT37
CIC_2_OUT38
CIC_2_OUT39
CIC_2_OUT40
CIC_2_OUT41
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
DESCRIPTION
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH interrupt
NETCP SWITCH STAT interrupt
Reserved
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
1
2
EVENT NO.
0
88
Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink)
EVENT NAME
GPIO_INT8
GPIO_INT9
GPIO_INT10
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NAME
GPIO_INT11
GPIO_INT12
GPIO_INT13
GPIO_INT14
GPIO_INT15
DBGTBR_DMAINT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DFT_PBIST_CPU_INT
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_17
QMSS_INTD_1_HIGH_18
QMSS_INTD_1_HIGH_19
QMSS_INTD_1_HIGH_20
QMSS_INTD_1_HIGH_21
QMSS_INTD_1_HIGH_22
QMSS_INTD_1_HIGH_23
QMSS_INTD_1_HIGH_24
QMSS_INTD_1_HIGH_25
QMSS_INTD_1_HIGH_26
QMSS_INTD_1_HIGH_27
QMSS_INTD_1_HIGH_28
QMSS_INTD_1_HIGH_29
QMSS_INTD_1_HIGH_30
QMSS_INTD_1_HIGH_31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRACER_DDR_INT
39
40
41
42
43
34
35
36
37
38
47
48
49
44
45
46
29
30
31
32
33
24
25
26
27
28
19
20
21
22
23
14
15
16
17
18
9
10
11
12
13
4
5
6
7
8
EVENT NO.
3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Debug trace buffer (TBR) DMA event
Reserved
Reserved
Reserved
Reserved
Reserved
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer sliding time window interrupt for MSMC-DDR3
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
86
87
88
89
90
81
82
83
84
85
94
95
96
91
92
93
76
77
78
79
80
71
72
73
74
75
66
67
68
69
70
61
62
63
64
65
56
57
58
59
60
EVENT NO.
50
51
52
53
54
55
EVENT NAME
TRACER_MSMC_0_INT
TRACER_MSMC_1_INT
TRACER_MSMC_2_INT
TRACER_MSMC_3_INT
TRACER_CFG_INT
TRACER_QMSS_QM_CFG1_INT
TRACER_QMSS_DMA_INT
TRACER_SEM_INT
Reserved
Reserved
Reserved
Reserved
BOOTCFG_INT
NETCP_0_PKTDMA_INT0
MPU_0_INT
MSMC_SCRUB_CERROR
MPU_1_INT
Reserved
MPU_2_INT
QMSS_INTD_1_PKTDMA_0
Reserved
QMSS_INTD_1_PKTDMA_1
MSMC_DEDC_CERROR
MSMC_DEDC_NC_ERROR
MSMC_SCRUB_NC_ERROR
Reserved
MSMC_MPF_ERROR0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MSMC_MPF_ERROR8
MSMC_MPF_ERROR9
MSMC_MPF_ERROR10
MSMC_MPF_ERROR11
MSMC_MPF_ERROR12
MSMC_MPF_ERROR13
MSMC_MPF_ERROR14
MSMC_MPF_ERROR15
Reserved
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
DESCRIPTION
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for TeraNet CFG
Tracer sliding time window interrupt for Navigator CFG1 slave port
Tracer sliding time window interrupt for Navigator VBUSM slave port
Tracer sliding time window interrupt for Semaphore interrupt
Reserved
Reserved
Reserved
Reserved
BOOTCFG error interrupt
Packet Accelerator0 Packet DMA starvation interrupt
MPU0 interrupt
MSMC error interrupt
MPU1 interrupt
Reserved
MPU2 interrupt
Navigator Packet DMA interrupt
Reserved
Navigator Packet DMA interrupt
MSMC error interrupt
MSMC error interrupt
MSMC error interrupt
Reserved
Memory protection fault indicators for system master PrivID = 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory protection fault indicators for system master PrivID = 8
Memory protection fault indicators for system master PrivID = 9
Memory protection fault indicators for system master PrivID = 10
Memory protection fault indicators for system master PrivID = 11
Memory protection fault indicators for system master PrivID = 12
Memory protection fault indicators for system master PrivID = 13
Memory protection fault indicators for system master PrivID = 14
Memory protection fault indicators for system master PrivID = 15
Reserved
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
90
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NAME
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AEMIF_EASYNCERR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
QMSS_INTD_1_HIGH_0
QMSS_INTD_1_HIGH_1
QMSS_INTD_1_HIGH_2
QMSS_INTD_1_HIGH_3
QMSS_INTD_1_HIGH_4
QMSS_INTD_1_HIGH_5
133
134
135
136
137
128
129
130
131
132
138
139
140
141
142
143
123
124
125
126
127
118
119
120
121
122
113
114
115
116
117
108
109
110
111
112
103
104
105
106
107
EVENT NO.
97
98
99
100
101
102
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Asynchronous EMIF16 error interrupt
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NAME
QMSS_INTD_1_HIGH_6
QMSS_INTD_1_HIGH_7
QMSS_INTD_1_HIGH_8
QMSS_INTD_1_HIGH_9
QMSS_INTD_1_HIGH_10
QMSS_INTD_1_HIGH_11
QMSS_INTD_1_HIGH_12
QMSS_INTD_1_HIGH_13
QMSS_INTD_1_HIGH_14
QMSS_INTD_1_HIGH_15
QMSS_INTD_2_HIGH_0
QMSS_INTD_2_HIGH_1
QMSS_INTD_2_HIGH_2
QMSS_INTD_2_HIGH_3
QMSS_INTD_2_HIGH_4
QMSS_INTD_2_HIGH_5
QMSS_INTD_2_HIGH_6
QMSS_INTD_2_HIGH_7
QMSS_INTD_2_HIGH_8
QMSS_INTD_2_HIGH_9
QMSS_INTD_2_HIGH_10
QMSS_INTD_2_HIGH_11
QMSS_INTD_2_HIGH_12
QMSS_INTD_2_HIGH_13
QMSS_INTD_2_HIGH_14
QMSS_INTD_2_HIGH_15
QMSS_INTD_2_HIGH_16
QMSS_INTD_2_HIGH_17
QMSS_INTD_2_HIGH_18
QMSS_INTD_2_HIGH_19
QMSS_INTD_2_HIGH_20
QMSS_INTD_2_HIGH_21
QMSS_INTD_2_HIGH_22
QMSS_INTD_2_HIGH_23
QMSS_INTD_2_HIGH_24
QMSS_INTD_2_HIGH_25
QMSS_INTD_2_HIGH_26
QMSS_INTD_2_HIGH_27
QMSS_INTD_2_HIGH_28
QMSS_INTD_2_HIGH_29
QMSS_INTD_2_HIGH_30
QMSS_INTD_2_HIGH_31
MPU_12_INT
MPU_13_INT
MPU_14_INT
MPU_15_INT
Reserved
180
181
182
183
184
175
176
177
178
179
185
186
187
188
189
190
170
171
172
173
174
165
166
167
168
169
160
161
162
163
164
155
156
157
158
159
150
151
152
153
154
EVENT NO.
144
145
146
147
148
149
DESCRIPTION
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
MPU12 addressing violation interrupt and protection violation interrupt
MPU13 addressing violation interrupt and protection violation interrupt
MPU14 addressing violation interrupt and protection violation interrupt
MPU15 addressing violation interrupt and protection violation interrupt
Reserved
92
Memory, Interrupts, and EDMA for AM5K2E0x
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219
220
221
222
223
214
215
216
217
218
209
210
211
212
213
202
203
204
205
206
207
208
229
230
231
232
233
234
235
236
237
224
225
226
227
228
Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
197
198
199
200
201
EVENT NO.
191
192
193
194
195
196
EVENT NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRACER_QMSS_QM_CFG2_INT
TRACER_EDMACC_0
TRACER_EDMACC_123_INT
TRACER_CIC_INT
Reserved
MPU_5_INT
Reserved
MPU_7_INT
MPU_8_INT
Reserved
Reserved
Reserved
DDR3_0_ERR
HYPERLINK_0_INT
EDMACC_0_ERRINT
EDMACC_0_MPINT
EDMACC_0_TC_0_ERRINT
EDMACC_0_TC_1_ERRINT
EDMACC_1_ERRINT
EDMACC_1_MPINT
EDMACC_1_TC_0_ERRINT
EDMACC_1_TC_1_ERRINT
EDMACC_1_TC_2_ERRINT
EDMACC_1_TC_3_ERRINT
EDMACC_2_ERRINT
EDMACC_2_MPINT
EDMACC_2_TC_0_ERRINT
EDMACC_2_TC_1_ERRINT
EDMACC_2_TC_2_ERRINT
EDMACC_2_TC_3_ERRINT
EDMACC_3_ERRINT
EDMACC_3_MPINT
EDMACC_3_TC_0_ERRINT
EDMACC_3_TC_1_ERRINT
EDMACC_4_ERRINT
EDMACC_4_MPINT
EDMACC_4_TC_0_ERRINT
EDMACC_4_TC_1_ERRINT
QMSS_QUE_PEND_652
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer sliding time window interrupt for Navigator CFG2 slave port
Tracer sliding time window interrupt foR EDMA3CC0
Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2, and
EDMA3CC3
Tracer sliding time window interrupt for interrupt controllers (CIC)
Reserved
MPU5 addressing violation interrupt and protection violation interrupt
Reserved
MPU7 addressing violation interrupt and protection violation interrupt
MPU8 addressing violation interrupt and protection violation interrupt
Reserved
Reserved
Reserved
DDR3 error interrupt
HyperLink interrupt
EDMA3CC0 error interrupt
EDMA3CC0 memory protection interrupt
EDMA3CC0 TPTC0 error interrupt
EDMA3CC0 TPTC1 error interrupt
EDMA3CC1 error interrupt
EDMA3CC1 memory protection interrupt
EDMA3CC1 TPTC0 error interrupt
EDMA3CC1 TPTC1 error interrupt
EDMA3CC1 TPTC2 error interrupt
EDMA3CC1 TPTC3 error interrupt
EDMA3CC2 error interrupt
EDMA3CC2 memory protection interrupt
EDMA3CC2 TPTC0 error interrupt
EDMA3CC2 TPTC1 error interrupt
EDMA3CC2 TPTC2 error interrupt
EDMA3CC2 TPTC3 error interrupt
EDMA3CC3 error interrupt
EDMA3CC3 memory protection interrupt
EDMA3CC3 TPTC0 error interrupt
EDMA3CC3 TPTC1 error interrupt
EDMA3CC4 error interrupt
EDMA3CC4 memory protection interrupt
EDMA3CC4 TPTC0 error interrupt
EDMA3CC4 TPTC1 error interrupt
Navigator transmit queue pending event for indicated queue
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NAME
QMSS_QUE_PEND_653
QMSS_QUE_PEND_654
QMSS_QUE_PEND_655
QMSS_QUE_PEND_656
QMSS_QUE_PEND_657
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
QMSS_QUE_PEND_666
QMSS_QUE_PEND_667
QMSS_QUE_PEND_668
QMSS_QUE_PEND_669
QMSS_QUE_PEND_670
QMSS_QUE_PEND_671
QMSS_QUE_PEND_672
QMSS_QUE_PEND_673
QMSS_QUE_PEND_674
QMSS_QUE_PEND_675
QMSS_QUE_PEND_676
QMSS_QUE_PEND_677
QMSS_QUE_PEND_678
QMSS_QUE_PEND_679
QMSS_QUE_PEND_680
QMSS_QUE_PEND_681
QMSS_QUE_PEND_682
QMSS_QUE_PEND_683
QMSS_QUE_PEND_684
QMSS_QUE_PEND_685
QMSS_QUE_PEND_686
QMSS_QUE_PEND_687
QMSS_QUE_PEND_688
QMSS_QUE_PEND_689
QMSS_QUE_PEND_690
QMSS_QUE_PEND_691
10GbE_LINK_INT0
10GbE_LINK_INT1
10GbE_USER_INT0
10GbE_USER_INT1
10GbE_MISC_INT
10GbE_INT_PKTDMA_0
Reserved
Reserved
274
275
276
277
278
269
270
271
272
273
279
280
281
282
283
284
264
265
266
267
268
259
260
261
262
263
254
255
256
257
258
249
250
251
252
253
244
245
246
247
248
EVENT NO.
238
239
240
241
242
243
DESCRIPTION
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet Packet DMA starvation interrupt
Reserved
Reserved
94
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SEM_INT8
SEM_INT9
SEM_INT10
SEM_INT11
SEM_INT12
Reserved
Reserved
Reserved
SEM_ERR8
SEM_ERR9
SEM_ERR10
SEM_ERR11
SEM_ERR12
QMSS1_ECC_INTR
QMSS_INTD_1_LOW_0
QMSS_INTD_1_LOW_1
QMSS_INTD_1_LOW_2
QMSS_INTD_1_LOW_3
QMSS_INTD_1_LOW_4
QMSS_INTD_1_LOW_5
QMSS_INTD_1_LOW_6
QMSS_INTD_1_LOW_7
QMSS_INTD_1_LOW_8
QMSS_INTD_1_LOW_9
QMSS_INTD_1_LOW_10
QMSS_INTD_1_LOW_11
QMSS_INTD_1_LOW_12
QMSS_INTD_1_LOW_13
QMSS_INTD_1_LOW_14
QMSS_INTD_1_LOW_15
QMSS_INTD_2_LOW_0
QMSS_INTD_2_LOW_1
QMSS_INTD_2_LOW_2
QMSS_INTD_2_LOW_3
QMSS_INTD_2_LOW_4
QMSS_INTD_2_LOW_5
QMSS_INTD_2_LOW_6
QMSS_INTD_2_LOW_7
QMSS_INTD_2_LOW_8
QMSS_INTD_2_LOW_9
QMSS_INTD_2_LOW_10
321
322
323
324
325
316
317
318
319
320
326
327
328
329
330
331
311
312
313
314
315
306
307
308
309
310
301
302
303
304
305
296
297
298
299
300
291
292
293
294
295
EVENT NO.
285
286
287
288
289
290
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Reserved
Reserved
Reserved
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Navigator ECC error interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NAME
QMSS_INTD_2_LOW_11
QMSS_INTD_2_LOW_12
QMSS_INTD_2_LOW_13
QMSS_INTD_2_LOW_14
QMSS_INTD_2_LOW_15
NETCP_MDIO_LINK_INT0
NETCP_MDIO_LINK_INT1
NETCP_MDIO_USER_INT0
NETCP_MDIO_USER_INT1
NETCP_MISC_INT
NETCP_GLOBAL_STARVE_INT
NETCP_LOCAL_STARVE_INT
NETCP_PA_ECC_INT
NETCP_SA_ECC_INT
NETCP_SWITCH_ECC_INT
NETCP_SWITCH_STAT_INT0
NETCP_SWITCH_STAT_INT1
NETCP_SWITCH_STAT_INT2
NETCP_SWITCH_STAT_INT3
NETCP_SWITCH_STAT_INT4
NETCP_SWITCH_STAT_INT5
NETCP_SWITCH_STAT_INT6
NETCP_SWITCH_STAT_INT7
NETCP_SWITCH_STAT_INT8
NETCP_SWITCH_INT
Reserved
Reserved
Reserved
Reserved
Reserved
PSC_ALLINT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU_9_INT
MPU_10_INT
MPU_11_INT
TRACER_MSMC_4_INT
TRACER_MSMC_5_INT
TRACER_MSMC_6_INT
TRACER_MSMC_7_INT
368
369
370
371
372
363
364
365
366
367
373
374
375
376
377
378
358
359
360
361
362
353
354
355
356
357
348
349
350
351
352
343
344
345
346
347
338
339
340
341
342
EVENT NO.
332
333
334
335
336
337
DESCRIPTION
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator interrupt
Packet Accelerator interrupt
Packet Accelerator interrupt
Packet Accelerator interrupt
NETCP SWITCH ECC interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
PSC interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU9 addressing violation interrupt and protection violation interrupt
MPU10 addressing violation interrupt and protection violation interrupt
MPU11 addressing violation interrupt and protection violation interrupt
Tracer sliding time window interrupt for MSMC SRAM bank 4
Tracer sliding time window interrupt for MSMC SRAM bank 4
Tracer sliding time window interrupt for MSMC SRAM bank 4
Tracer sliding time window interrupt for MSMC SRAM bank 4
96
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
USB_0_INT01
USB_0_INT02
USB_0_INT03
USB_0_INT04
USB_0_INT05
USB_0_INT06
USB_0_INT07
USB_0_INT08
USB_0_INT09
USB_0_INT10
USB_0_INT11
USB_0_INT12
USB_0_INT13
USB_0_INT14
USB_0_INT15
USB_0_MISCINT
USB_0_OABSINT
Reserved
USB_1_INT00
USB_1_INT01
USB_1_INT02
USB_1_INT03
USB_1_INT04
USB_1_INT05
USB_1_INT06
USB_1_INT07
EVENT NAME
TRACER_PCIE1_INT
Reserved
Reserved
Reserved
Reserved
TRACER_SPI_ROM_EMIF_INT
Reserved
TRACER_USB1_INT
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
USB_0_INT00
415
416
417
418
419
410
411
412
413
414
420
421
422
423
424
425
405
406
407
408
409
400
401
402
403
404
395
396
397
398
399
390
391
392
393
394
385
386
387
388
389
EVENT NO.
379
380
381
382
383
384
DESCRIPTION
Tracer sliding time window interrupt for PCIE1
Reserved
Reserved
Reserved
Reserved
Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
Reserved
Tracer sliding time window interrupt for USB1 CFG port tracer
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
USB 0 event ring 0 interrupt
USB 0 event ring 1 interrupt
USB 0 event ring 2 interrupt
USB 0 event ring 3 interrupt
USB 0 event ring 4 interrupt
USB 0 event ring 5 interrupt
USB 0 event ring 6 interrupt
USB 0 event ring 7 interrupt
USB 0 event ring 8 interrupt
USB 0 event ring 9 interrupt
USB 0 event ring 10 interrupt
USB 0 event ring 11 interrupt
USB 0 event ring 12 interrupt
USB 0 event ring 13 interrupt
USB 0 event ring 14 interrupt
USB 0 event ring 15 interrupt
USB 0 Miscellaneous interrupt
USB 0 OABS interrupt
Reserved
USB 1 event ring 0 interrupt
USB 1 event ring 1 interrupt
USB 1 event ring 2 interrupt
USB 1 event ring 3 interrupt
USB 1 event ring 4 interrupt
USB 1 event ring 5 interrupt
USB 1 event ring 6 interrupt
USB 1 event ring 7 interrupt
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
TIMER_18_INTL
TIMER_18_INTH
TIMER_19_INTL
TIMER_19_INTH
Reserved
RSTMUX_INT8
RSTMUX_INT9
RSTMUX_INT10
RSTMUX_INT11
GPIO_INT0
GPIO_INT1
GPIO_INT2
GPIO_INT3
GPIO_INT4
GPIO_INT5
GPIO_INT6
GPIO_INT7
Reserved
Reserved
EVENT NAME
USB_1_INT08
USB_1_INT09
USB_1_INT10
USB_1_INT11
USB_1_INT12
USB_1_INT13
USB_1_INT14
USB_1_INT15
USB_1_MISCINT
USB_1_OABSINT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TIMER_12_INTL
462
463
464
465
466
457
458
459
460
461
467
468
469
470
471
472
452
453
454
455
456
447
448
449
450
451
442
443
444
445
446
437
438
439
440
441
432
433
434
435
436
EVENT NO.
426
427
428
429
430
431
DESCRIPTION
USB 1 event ring 8 interrupt
USB 1 event ring 9 interrupt
USB 1 event ring 10 interrupt
USB 1 event ring 11 interrupt
USB 1 event ring 12 interrupt
USB 1 event ring 13 interrupt
USB 1 event ring 14 interrupt
USB 1 event ring 15 interrupt
USB 1 miscellaneous interrupt
USB 1 OABS interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Reserved
Boot config watchdog timer expiration event for ARM Core 0
Boot config watchdog timer expiration event for ARM Core 1
Boot config watchdog timer expiration event for ARM Core 2
Boot config watchdog timer expiration event for ARM Core 3
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Reserved
Reserved
98
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Table 6-23. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
473
474
475
476
477
478
EVENT NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6.3.2
CIC Registers
This section includes the CIC memory map information and registers.
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6.3.2.1
CIC2 Register Map
Table 6-24. CIC2 Registers
0x294
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8
0x22C
0x230
0x234
0x238
0x23C
0x280
0x284
0x288
0x28C
0x290
0x2BC
0x300
0x304
0x308
0x30C
0x310
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
ADDRESS
OFFSET
0x0
0x10
0x20
0x24
0x28
0x2C
0x34
0x38
0x200
100
REGISTER MNEMONIC
REVISION_REG
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
RAW_STATUS_REG5
RAW_STATUS_REG6
RAW_STATUS_REG7
RAW_STATUS_REG8
RAW_STATUS_REG9
RAW_STATUS_REG10
RAW_STATUS_REG11
RAW_STATUS_REG12
RAW_STATUS_REG13
RAW_STATUS_REG14
RAW_STATUS_REG15
ENA_STATUS_REG0
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENA_STATUS_REG5
ENA_STATUS_REG6
ENA_STATUS_REG7
ENA_STATUS_REG8
ENA_STATUS_REG9
ENA_STATUS_REG10
ENA_STATUS_REG11
ENA_STATUS_REG12
ENA_STATUS_REG13
ENA_STATUS_REG14
ENA_STATUS_REG15
ENABLE_REG0
ENABLE_REG1
ENABLE_REG2
ENABLE_REG3
ENABLE_REG4
REGISTER NAME
Revision Register
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Raw Status Register 5
Raw Status Register 6
Raw Status Register 7
Raw Status Register 8
Raw Status Register 9
Raw Status Register 10
Raw Status Register 11
Raw Status Register 12
Raw Status Register 13
Raw Status Register 14
Raw Status Register 15
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enabled Status Register 5
Enabled Status Register 6
Enabled Status Register 7
Enabled Status Register 8
Enabled Status Register 9
Enabled Status Register10
Enabled Status Register 11
Enabled Status Register 12
Enabled Status Register 13
Enabled Status Register 14
Enabled Status Register 15
Enable Register 0
Enable Register 1
Enable Register 2
Enable Register 3
Enable Register 4
Memory, Interrupts, and EDMA for AM5K2E0x
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Table 6-24. CIC2 Registers (continued)
REGISTER MNEMONIC
ENABLE_REG5
ENABLE_REG6
ENABLE_REG7
ENABLE_REG8
ENABLE_REG9
ENABLE_REG10
ENABLE_REG11
ENABLE_REG12
ENABLE_REG13
ENABLE_REG14
ENABLE_REG15
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
ENABLE_CLR_REG5
ENABLE_CLR_REG6
ENABLE_CLR_REG7
ENABLE_CLR_REG8
ENABLE_CLR_REG9
ENABLE_CLR_REG10
ENABLE_CLR_REG11
ENABLE_CLR_REG12
ENABLE_CLR_REG13
ENABLE_CLR_REG14
ENABLE_CLR_REG15
CH_MAP_REG0
CH_MAP_REG1
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
CH_MAP_REG5
CH_MAP_REG6
CH_MAP_REG7
CH_MAP_REG8
CH_MAP_REG9
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
CH_MAP_REG116
CH_MAP_REG117
CH_MAP_REG118
CH_MAP_REG119
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0x420
0x424
0x428
0x39C
0x3A0
0x3A4
0x3A8
0x3AC
0x3B0
0x3B4
0x3B8
0x38C
0x400
0x42C
0x430
0x434
0x438
0x43C
0x5C0
0x5C4
0x5C8
0x5CC
0x334
0x338
0x33C
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
ADDRESS
OFFSET
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
REGISTER NAME
Enable Register 5
Enable Register 6
Enable Register 7
Enable Register 8
Enable Register 9
Enable Register 10
Enable Register 11
Enable Register 12
Enable Register 13
Enable Register 14
Enable Register 15
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Enable Clear Register 5
Enable Clear Register 6
Enable Clear Register 7
Enable Clear Register 8
Enable Clear Register 9
Enable Clear Register 10
Enable Clear Register 11
Enable Clear Register 12
Enable Clear Register 13
Enable Clear Register 14
Enable Clear Register 15
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
Interrupt Channel Map Register for 20 to 20+3
Interrupt Channel Map Register for 24 to 24+3
Interrupt Channel Map Register for 28 to 28+3
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Interrupt Channel Map Register for 464 to 464+3
Interrupt Channel Map Register for 468 to 468+3
Interrupt Channel Map Register for 472 to 472+3
Interrupt Channel Map Register for 476 to 476+3
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Table 6-24. CIC2 Registers (continued)
102
CH_MAP_REG138
CH_MAP_REG139
CH_MAP_REG140
CH_MAP_REG141
CH_MAP_REG142
CH_MAP_REG143
CH_MAP_REG144
CH_MAP_REG145
CH_MAP_REG146
CH_MAP_REG147
CH_MAP_REG148
CH_MAP_REG149
CH_MAP_REG150
CH_MAP_REG151
CH_MAP_REG152
CH_MAP_REG153
CH_MAP_REG154
CH_MAP_REG155
CH_MAP_REG156
CH_MAP_REG157
REGISTER MNEMONIC
CH_MAP_REG120
CH_MAP_REG121
CH_MAP_REG122
CH_MAP_REG123
CH_MAP_REG124
CH_MAP_REG125
CH_MAP_REG126
CH_MAP_REG127
CH_MAP_REG128
CH_MAP_REG129
CH_MAP_REG130
CH_MAP_REG131
CH_MAP_REG132
CH_MAP_REG133
CH_MAP_REG134
CH_MAP_REG135
CH_MAP_REG136
CH_MAP_REG137
CH_MAP_REG158
CH_MAP_REG159
CH_MAP_REG160
CH_MAP_REG161
CH_MAP_REG162
CH_MAP_REG163
CH_MAP_REG164
CH_MAP_REG165
CH_MAP_REG166
0x640
0x644
0x648
0x64C
0x650
0x654
0x658
0x65C
0x660
0x664
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
0x638
0x63C
0x668
0x66C
0x670
0x674
0x678
0x67C
0x680
0x684
0x688
0x5F0
0x5F4
0x5F8
0x5FC
0x600
0x604
0x608
0x60C
0x610
0x614
ADDRESS
OFFSET
0x5D0
0x5D4
0x5D8
0x5DC
0x5E0
0x5E4
0x5E8
0x5EC
REGISTER NAME
Interrupt Channel Map Register for 480 to 480+3
Interrupt Channel Map Register for 484 to 484+3
Interrupt Channel Map Register for 488 to 488+3
Interrupt Channel Map Register for 482 to 492+3
Interrupt Channel Map Register for 496 to 496+3
Interrupt Channel Map Register for 500 to 500+3
Interrupt Channel Map Register for 504 to 504+3
Interrupt Channel Map Register for 508 to 508+3
Interrupt Channel Map Register for 512 to 512+3
Interrupt Channel Map Register for 516 to 516+3
Interrupt Channel Map Register for 520 to 520+3
Interrupt Channel Map Register for 524 to 524+3
Interrupt Channel Map Register for 528 to 528+3
Interrupt Channel Map Register for 532 to 532+3
Interrupt Channel Map Register for 536 to 536+3
Interrupt Channel Map Register for 540 to 540+3
Interrupt Channel Map Register for 544 to 544+3
Interrupt Channel Map Register for 548 to 548+3
Interrupt Channel Map Register for 552 to 552+3
Interrupt Channel Map Register for 556 to 556+3
Interrupt Channel Map Register for 560 to 560+3
Interrupt Channel Map Register for 564 to 564+3
Interrupt Channel Map Register for 568 to 568+3
Interrupt Channel Map Register for 572 to 572+3
Interrupt Channel Map Register for 576 to 576+3
Interrupt Channel Map Register for 580 to 580+3
Interrupt Channel Map Register for 584 to 584+3
Interrupt Channel Map Register for 588 to 588+3
Interrupt Channel Map Register for 592 to 592+3
Interrupt Channel Map Register for 596 to 596+3
Interrupt Channel Map Register for 600 to 600+3
Interrupt Channel Map Register for 604 to 604+3
Interrupt Channel Map Register for 608 to 608+3
Interrupt Channel Map Register for 612 to 612+3
Interrupt Channel Map Register for 616 to 616+3
Interrupt Channel Map Register for 620 to 620+3
Interrupt Channel Map Register for 624 to 624+3
Interrupt Channel Map Register for 628 to 628+3
Interrupt Channel Map Register for 632 to 632+3
Interrupt Channel Map Register for 636 to 636+3
Interrupt Channel Map Register for 640 to 640+3
Interrupt Channel Map Register for 644 to 644+3
Interrupt Channel Map Register for 648 to 648+3
Interrupt Channel Map Register for 652 to 652+3
Interrupt Channel Map Register for 656 to 656+3
Interrupt Channel Map Register for 660 to 660+3
Interrupt Channel Map Register for 664 to 664+3
Memory, Interrupts, and EDMA for AM5K2E0x
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0x85C
0x860
0x864
0x868
0x86C
0x1500
0x1504
0x1508
0x150C
0x834
0x838
0x83C
0x840
0x844
0x848
0x84C
0x850
0x854
0x858
0x80C
0x810
0x814
0x818
0x81C
0x820
0x824
0x828
0x82C
0x830
ADDRESS
OFFSET
0x68C
0x690
0x694
0x698
0x69C
0x800
0x804
0x808
REGISTER MNEMONIC
CH_MAP_REG167
CH_MAP_REG168
CH_MAP_REG169
CH_MAP_REG170
CH_MAP_REG171
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
HINT_MAP_REG13
HINT_MAP_REG14
HINT_MAP_REG15
HINT_MAP_REG16
HINT_MAP_REG17
HINT_MAP_REG18
HINT_MAP_REG19
HINT_MAP_REG20
HINT_MAP_REG21
HINT_MAP_REG22
HINT_MAP_REG23
HINT_MAP_REG24
HINT_MAP_REG25
HINT_MAP_REG26
HINT_MAP_REG27
ENABLE_HINT_REG0
ENABLE_HINT_REG1
ENABLE_HINT_REG2
ENABLE_HINT_REG3
Table 6-24. CIC2 Registers (continued)
REGISTER NAME
Interrupt Channel Map Register for 668 to 668+3
Interrupt Channel Map Register for 672 to 672+3
Interrupt Channel Map Register for 676 to 676+3
Interrupt Channel Map Register for 680 to 680+3
Interrupt Channel Map Register for 684 to 684+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Interrupt Map Register for 52 to 52+3
Host Interrupt Map Register for 56 to 56+3
Host Interrupt Map Register for 60 to 60+3
Host Interrupt Map Register for 63 to 63+3
Host Interrupt Map Register for 66 to 66+3
Host Interrupt Map Register for 68 to 68+3
Host Interrupt Map Register for 72 to 72+3
Host Interrupt Map Register for 76 to 76+3
Host Interrupt Map Register for 80 to 80+3
Host Interrupt Map Register for 84 to 84+3
Host Interrupt Map Register for 88 to 88+3
Host Interrupt Map Register for 92 to 92+3
Host Interrupt Map Register for 94 to 94+3
Host Interrupt Map Register for 96 to 96+3
Host Interrupt Map Register for 100 to 100+3
Host Int Enable Register 0
Host Int Enable Register 1
Host Int Enable Register 2
Host Int Enable Register 3
6.4
Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memorymapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device
ARM CorePac.
There are 5 EDMA channel controllers on the device:
• EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1
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• EDMA3CC1 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
• EDMA3CC2 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
• EDMA3CC3 has two transfer controllers: TPTC0 and TPTC1
• EDMA3CC4 has two transfer controllers: TPTC0 and TPTC1
In the context of this document, TPTCx is associated with EDMA3CCy, and is referred to as EDMA3CCy
TPTCx. Each of the transfer controllers has a direct connection to the switch fabric.
lists the peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR3 subsytems. The others are used for the remaining traffic.
Each EDMA3 channel controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
• Array (multiple bytes)
• Frame (multiple arrays)
• Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 512 PaRAM entries for all EDMA3CC
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 64 DMA channels for all EDMA3CC
– Manually triggered (CPU writes to channel controller register)
– External event triggered
– Chain triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA3CCx
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• Two transfer controllers and two event queues with programmable system-level priority for
EDMA3CC0, EDMA3CC3 and EDMA3CC4
• Four transfer controllers and four event queues with programmable system-level priority for each of
EDMA3CC1 and EDMA3CC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
6.4.1
EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode.
Constant addressing mode is applicable to a very limited set of use cases. For most applications increment mode can be used. For more information on these two addressing modes, see the KeyStone
Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide ( SPRUGS5 ).
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For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers and EDMA3 transfer controller (TPTC) control registers, see Section
. For memory offsets and other details on EDMA3CC and TPTC Control Register entries, see the KeyStone Architecture Enhanced
Direct Memory Access 3 (EDMA3) User's Guide ( SPRUGS5 ).
6.4.2
EDMA3 Channel Controller Configuration
shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 6-25. EDMA3 Channel Controller Configuration
DESCRIPTION
Number of DMA channels in channel controller
Number of QDMA channels
Number of interrupt channels
Number of PaRAM set entries
Number of event queues
Number of transfer controllers
Memory protection existence
Number of memory protection and shadow regions
512
2
2
Yes
8
EDMA3 CC0 EDMA3 CC1 EDMA3 CC2 EDMA3 CC3 EDMA3 CC4
64 64 64 64 64
8
64
8
64
8
64
8
64
8
64
512
4
4
Yes
8
512
4
4
Yes
8
512
2
2
Yes
8
512
2
2
Yes
8
6.4.3
EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data. The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of destination FIFO register sets for a transfer controller determines the maximum number of outstanding transfer requests.
All four parameters listed above are fixed by the design of the device.
shows the configuration of each of the EDMA3 transfer controllers present on the device.
Table 6-26. EDMA3 Transfer Controller Configuration
PARAMETER
FIFOSIZE
BUSWIDTH
EDMA3 CC0/CC4
TC0
1024 bytes
32 bytes
TC1
1024 bytes
32 bytes
TC0
1024 bytes
16 bytes
TC1
1024 bytes
16
EDMA3 CC1
bytes
TC2
1024 bytes
16 bytes
TC3
1024 bytes
16 bytes
TC0
1024 bytes
16 bytes
EDMA3 CC2
TC1
1024 bytes
16 bytes
TC2
1024 bytes
16 bytes
TC3
1024 bytes
16 bytes
EDMA3CC3
TC0
1024 bytes
16 bytes
TC1
1024 bytes
16 bytes
DSTREGDEPTH 4 4 4 4 4 4 4 4 4 4 4 4 entries entries entries entries entries entries entries entries entries entries entries entries
DBS 128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
64 bytes
64 bytes
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29
30
31
32
33
34
35
36
24
25
26
27
28
19
20
21
22
23
14
15
16
17
18
9
10
11
12
13
4
5
6
7
8
2
3
EVENT NO.
0
1
6.4.4
EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables list the source of the synchronization event associated with each of the EDMA3CC DMA channels. On the AM5K2E0x, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the KeyStone Architecture Enhanced Direct
Memory Access 3 (EDMA3) User's Guide ( SPRUGS5 ).
GPIO_INT11
GPIO_INT12
GPIO_INT13
GPIO_INT14
GPIO_INT15
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
TIMER_18_INTL
TIMER_18_INTH
TIMER_19_INTL
TIMER_19_INTH
GPIO_INT0
GPIO_INT1
GPIO_INT2
GPIO_INT3
GPIO_INT4
EVENT NAME
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
CIC_2_OUT66
CIC_2_OUT67
CIC_2_OUT68
CIC_2_OUT69
CIC_2_OUT70
CIC_2_OUT71
CIC_2_OUT72
CIC_2_OUT73
GPIO_INT8
GPIO_INT9
GPIO_INT10
Table 6-27. EDMA3CC0 Events for AM5K2E0x
DESCRIPTION
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
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53
54
55
56
57
48
49
50
51
52
61
62
63
58
59
60
43
44
45
46
47
EVENT NO.
37
38
39
40
41
42
Table 6-27. EDMA3CC0 Events for AM5K2E0x (continued)
EVENT NAME
GPIO_INT5
GPIO_INT6
GPIO_INT7
Reserved
Reserved
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
Reserved
SEM_INT8
SEM_INT9
SEM_INT10
SEM_INT11
SEM_INT12
DBGTBR_DMAINT
ARM_TBR_DMA
QMSS_QUE_PEND_560
QMSS_QUE_PEND_561
QMSS_QUE_PEND_562
QMSS_QUE_PEND_563
QMSS_QUE_PEND_564
QMSS_QUE_PEND_565
QMSS_QUE_PEND_566
QMSS_QUE_PEND_567
QMSS_QUE_PEND_568
QMSS_QUE_PEND_569
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
Reserved
Reserved
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Reserved
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
14
15
16
11
12
13
6
7
8
9
10
1
2
3
4
5
EVENT NO.
0
Table 6-28. EDMA3CC1 Events for AM5K2E0x
EVENT NAME
GPIO_INT28
GPIO_INT29
SPI_0_XEVT
SPI_0_REVT
SEM_INT8
SEM_INT9
GPIO_INT0
GPIO_INT1
GPIO_INT2
GPIO_INT3
QMSS_QUE_PEND_570
QMSS_QUE_PEND_571
QMSS_QUE_PEND_572
QMSS_QUE_PEND_573
Reserved
QMSS_QUE_PEND_574
QMSS_QUE_PEND_575
DESCRIPTION
GPIO interrupt
GPIO interrupt
SPI0 transmit event
SPI0 receive event
Semaphore interrupt
Semaphore interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Reserved
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
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53
54
55
56
57
48
49
50
51
52
61
62
63
58
59
60
43
44
45
46
47
38
39
40
41
42
33
34
35
36
37
28
29
30
31
32
23
24
25
26
27
EVENT NO.
17
18
19
20
21
22
Table 6-28. EDMA3CC1 Events for AM5K2E0x (continued)
EVENT NAME
QMSS_QUE_PEND_576
QMSS_QUE_PEND_577
QMSS_QUE_PEND_578
QMSS_QUE_PEND_579
QMSS_QUE_PEND_580
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
SEM_INT10
SEM_INT11
SEM_INT12
SR_0_SR_TEMPSENSOR
TSIP_RCV_FINT0
TSIP_XMT_FINT0
TSIP_RCV_SFINT0
TSIP_XMT_SFINT0
TSIP_RCV_FINT1
TSIP_XMT_FINT1
TSIP_RCV_SFINT1
TSIP_XMT_SFINT1
CIC_2_OUT8
GPIO_INT30
GPIO_INT31
I2C_0_REVT
I2C_0_XEVT
CIC_2_OUT13
CIC_2_OUT14
CIC_2_OUT15
CIC_2_OUT16
CIC_2_OUT17
CIC_2_OUT18
CIC_2_OUT19
Reserved
Reserved
DESCRIPTION
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
SmartReflex temperature threshold crossing interrupt
TSIP receive frame interrupt for Channel 0
TSIP transmit frame interrupt for Channel 0
TSIP receive super frame interrupt for Channel 0
TSIP transmit super frame interrupt for Channel 0
TSIP receive frame interrupt for Channel 1
TSIP transmit frame interrupt for Channel 1
TSIP receive super frame interrupt for Channel 1
TSIP transmit super frame interrupt for Channel 1
CIC2 Interrupt Controller output
GPIO interrupt
GPIO interrupt
I2C0 receive
I2C0 transmit
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
Reserved
Reserved
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37
38
39
40
41
32
33
34
35
36
42
43
44
45
46
27
28
29
30
31
22
23
24
25
26
17
18
19
20
21
12
13
14
15
16
7
8
9
5
6
10
11
1
2
3
4
EVENT NO.
0
Table 6-29. EDMA3CC2 Events for AM5K2E0x
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT0
GPIO_INT1
GPIO_INT2
GPIO_INT3
GPIO_INT4
GPIO_INT5
GPIO_INT6
GPIO_INT7
ARM_NCNTVIRQ3
ARM_NCNTVIRQ2
ARM_NCNTVIRQ1
ARM_NCNTVIRQ0
CIC_2_OUT48
Reserved
UART_0_URXEVT
UART_0_UTXEVT
CIC_2_OUT22
CIC_2_OUT23
CIC_2_OUT24
CIC_2_OUT25
CIC_2_OUT26
EVENT NAME
UART_1_URXEVT
UART_1_UTXEVT
SPI_1_XEVT
SPI_1_REVT
SPI_2_XEVT
SPI_2_REVT
DBGTBR_DMAINT
ARM_TBR_DMA
Reserved
Reserved
I2C_1_REVT
I2C_1_XEVT
I2C_2_REVT
I2C_2_XEVT
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
DESCRIPTION
UART1 receive event
UART1 transmit event
SPI1 receive event
SPI1 transmit event
SPI2 receive event
SPI2 transmit event
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
Reserved
Reserved
I2C1 receive
I2C1 transmit
I2C2 receive
I2C2 transmit
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
ARM virtual timer interrupt for core 3
ARM virtual timer interrupt for core 2
ARM virtual timer interrupt for core 1
ARM virtual timer interrupt for core 0
CIC2 Interrupt Controller output
Reserved
UART0 receive event
UART0 transmit event
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
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61
62
63
58
59
60
53
54
55
56
57
EVENT NO.
47
48
49
50
51
52
Table 6-29. EDMA3CC2 Events for AM5K2E0x (continued)
EVENT NAME
CIC_2_OUT27
CIC_2_OUT28
SPI_0_XEVT
SPI_0_REVT
Reserved
ARM_NCNTPNSIRQ3
ARM_NCNTPNSIRQ2
ARM_NCNTPNSIRQ1
ARM_NCNTPNSIRQ0
QMSS_QUE_PEND_581
QMSS_QUE_PEND_582
QMSS_QUE_PEND_583
QMSS_QUE_PEND_584
QMSS_QUE_PEND_585
QMSS_QUE_PEND_586
QMSS_QUE_PEND_587
QMSS_QUE_PEND_588
DESCRIPTION
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
SPI0 receive event
SPI0 transmit event
Reserved
ARM non secure timer interrupt for Core 3
ARM non secure timer interrupt for Core 2
ARM non secure timer interrupt for Core 1
ARM non secure timer interrupt for Core 0
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
16
17
18
19
20
11
12
13
14
15
24
25
26
21
22
23
6
7
8
9
10
1
2
3
4
5
EVENT NO.
0
EVENT NAME
Reserved
Reserved
SPI_2_XEVT
SPI_2_REVT
I2C_2_REVT
I2C_2_XEVT
UART_1_URXEVT
UART_1_UTXEVT
Reserved
Reserved
SPI_1_XEVT
SPI_1_REVT
I2C_0_REVT
I2C_0_XEVT
I2C_1_REVT
I2C_1_XEVT
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
ARM_TBR_DMA
DBGTBR_DMAINT
UART_0_URXEVT
UART_0_UTXEVT
GPIO_INT16
GPIO_INT17
GPIO_INT18
Table 6-30. EDMA3CC3 Events for AM5K2E0x
DESCRIPTION
Reserved
Reserved
SPI2 transmit event
SPI2 receive event
I2C2 receive
I2C2 transmit
UART1 receive event
UART1 transmit event
Reserved
Reserved
SPI1 transmit event
SPI1 receive event
I2C0 receive
I2C0 transmit
I2C1 receive
I2C1 transmit
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
UART0 receive event
UART0 transmit event
GPIO interrupt
GPIO interrupt
GPIO interrupt
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53
54
55
56
57
48
49
50
51
52
61
62
63
58
59
60
43
44
45
46
47
38
39
40
41
42
33
34
35
36
37
EVENT NO.
27
28
29
30
31
32
Table 6-30. EDMA3CC3 Events for AM5K2E0x (continued)
EVENT NAME
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
QMSS_QUE_PEND_589
QMSS_QUE_PEND_590
QMSS_QUE_PEND_591
QMSS_QUE_PEND_592
QMSS_QUE_PEND_593
QMSS_QUE_PEND_594
QMSS_QUE_PEND_595
QMSS_QUE_PEND_596
QMSS_QUE_PEND_597
QMSS_QUE_PEND_598
QMSS_QUE_PEND_599
QMSS_QUE_PEND_600
QMSS_QUE_PEND_601
QMSS_QUE_PEND_602
QMSS_QUE_PEND_603
QMSS_QUE_PEND_604
CIC_2_OUT57
CIC_2_OUT50
CIC_2_OUT51
CIC_2_OUT52
CIC_2_OUT53
CIC_2_OUT54
CIC_2_OUT55
CIC_2_OUT56
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
4
5
6
1
2
3
EVENT NO.
0
EVENT NAME
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
Table 6-31. EDMA3CC4 Events for AM5K2E0x
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
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43
44
45
46
47
38
39
40
41
42
51
52
53
48
49
50
33
34
35
36
37
28
29
30
31
32
23
24
25
26
27
18
19
20
21
22
13
14
15
16
17
EVENT NO.
7
8
9
10
11
12
Table 6-31. EDMA3CC4 Events for AM5K2E0x (continued)
EVENT NAME
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
Reserved
SEM_INT8
SEM_INT9
SEM_INT10
SEM_INT11
SEM_INT12
TIMER_12_INTL
TIMER_12_INTH
TIMER_8_INTL
TIMER_8_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
DBGTBR_DMAINT
ARM_TBR_DMA
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
QMSS_QUE_PEND_605
QMSS_QUE_PEND_606
QMSS_QUE_PEND_607
QMSS_QUE_PEND_608
QMSS_QUE_PEND_609
QMSS_QUE_PEND_610
QMSS_QUE_PEND_611
QMSS_QUE_PEND_612
ARM_NCNTVIRQ3
ARM_NCNTVIRQ2
ARM_NCNTVIRQ1
ARM_NCNTVIRQ0
ARM_NCNTPNSIRQ3
ARM_NCNTPNSIRQ2
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Reserved
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
ARM virtual timer interrupt for Core 3
ARM virtual timer interrupt for Core 2
ARM virtual timer interrupt for Core 1
ARM virtual timer interrupt for Core 0
ARM non secure timer interrupt for Core 3
ARM non secure timer interrupt for Core 2
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60
61
62
63
EVENT NO.
54
55
56
57
58
59
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 6-31. EDMA3CC4 Events for AM5K2E0x (continued)
EVENT NAME
ARM_NCNTPNSIRQ1
ARM_NCNTPNSIRQ0
CIC_2_OUT82
CIC_2_OUT83
CIC_2_OUT84
CIC_2_OUT85
CIC_2_OUT86
CIC_2_OUT87
CIC_2_OUT88
CIC_2_OUT89
DESCRIPTION
ARM non secure timer interrupt for Core 1
ARM non secure timer interrupt for Core 0
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
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7 System Interconnect
On the KeyStone II devices, the EDMA3 transfer controllers and the system peripherals are interconnected through the TeraNets, which are non-blocking switch fabrics enabling fast and contentionfree internal data movement. The TeraNets provide low-latency, concurrent data transfers between master peripherals and slave peripherals. The TeraNets also allow for seamless arbitration between the system masters when accessing system slaves.
The ARM CorePac is connected to the MSMC and the debug subsystem directly, and to other masters via the TeraNets. Through the MSMC, the ARM CorePacs can be interconnected to DDR3 and TeraNet 3_A, which allows the ARM CorePacs to access to the peripheral buses:
• TeraNet 3P_A for peripheral configuration
• TeraNet 6P_A for ARM Boot ROM
7.1
Internal Buses and Switch Fabrics
The the ARM CorePacs, the EDMA3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves.
• Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers.
• Slaves on the other hand rely on the masters to perform transfers to and from them.
Examples of masters include the EDMA3 traffic controllers and network coprocessor packet DMA.
Examples of slaves include the SPI, UART, and I
2
C.
The masters and slaves in the device communicate through the TeraNet (switch fabric). The device contains two types of switch fabric:
• Data TeraNet is a high-throughput interconnect mainly used to move data across the system
• Configuration TeraNet is mainly used to access peripheral registers
Some peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.
Note that the data TeraNet also connects to the configuration TeraNet.
7.2
Switch Fabric Connections Matrix - Data Space
The figures below show the connections between masters and slaves through various sections of the
TeraNet.
114
System Interconnect
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Bridge_1
Bridge_2
Bridge_3
From TeraNet_3_C
QM
Packet DMA
USB_0_MST
M
QM_2
Packet DMA
M
Debug_SS
TSIP
M
M
M
TNet_3_D
CPU/3
TNet_3_G
CPU/3
Bridge_11
Tracer_SPI_
ROM_EMIF16
TNet_6P_A
CPU/6
MPU_8
MPU_12
MPU_13
MPU_14
S
S
S
S
EMIF16
SPI_0
SPI_1
SPI_2
AM5K2E
S
Boot_ROM
ARM
To TeraNet_3_C
To TeraNet_3P_A
Bridge_5
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
Bridge_12
Bridge_13
Bridge_14
Figure 7-1. TeraNet 3_A-1
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NETCP_
Global_0
NETCP_
Global_1
EDMA
CC1
10GbE
TC_0
TC_1
TC_2
TC_3
EDMA
CC2
EDMA
CC3
TC_0
TC_1
TC_2
TC_3
TC_0
TC_1
M
M
M
M
M
M
M
M
M
M
M
M
M
PCIe_0
PCIe_1
M
M
TNet_3_L
CPU/3
Figure 7-2. TeraNet 3_A-2 www.ti.com
Tracer_QM_M
MPU_1
S
QM_SS
Tracer_SPI_
ROM_EMIF16
S
PCIe
AM5K2E
116
System Interconnect
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ARM CorePac
NETCP_LOCAL
HyperLink_0
USB_1
M
M
M
Bridge_5
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
From TeraNet_3_A
QM_Second
M
EDMA
CC0
EDMA
CC4
TC_0
TC_1
TC_0
TC_1
M
M
M
M
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
AM5K2E
MPU_15
S
USB_1 MMR CFG
S
USB_1 PHY CFG
S
NetCP
Tracer_NETCP_
USB_CFG
S
S
SES
SMS
M
S
MSMC
M
Tracer_
MSMC0-8
DDR3
BR_SES_0
BR_SES_1
BR_SES_2
BR_SMS_0
BR_SMS_1
BR_SMS_2
TNet_SES
CPU/1
TNet_SMS
CPU/1
TNet_msmc_sys
CPU/1
To TeraNet_3_A
To TeraNet_3P_A
CPU Port
Sys Port
TNet_3_U
CPU/3
MPU_7
Tracer_PCIe1
PCIe_1
To TeraNet_3_A
Bridge_1
Bridge_2
Bridge_3
Figure 7-3. TeraNet 3_C
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The following table lists the master and slave end-point connections.
Intersecting cells may contain one of the following:
• Y — There is a connection between this master and that slave.
• - — There is NO connection between this master and that slave.
• n — A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 7-1. AM5K2E04/02 Data Space Interconnect
Slaves
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
MASTERS
10GbE
CPT_CFG
CPT_DDR3
CPT_INTC
CPT_MSMC(0-7)
CPT_QM_CFG1
CPT_QM_CFG2
CPT_QM_M
CPT_SPI_ROM_EMIF16
CPT_TPCC(0_4)T
CPT_TPCC(1_2_3)T
DBG_DAP
TSIP_DMA
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
118
System Interconnect
11
11
11
11
11
11
11
11
11
11
11
11
-
-
11
11
11
11
-
2, 11
2, 11
3, 11
3, 11
-
-
-
Y
Y
AEMIF16
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
Y
-
-
-
Y
-
-
-
-
-
Y
-
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
-
-
-
-
Y
Y
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
11
-
Y
-
-
2, 11
-
3, 11
-
-
-
-
-
-
Y
Y
-
-
-
-
-
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
SES_2
-
-
-
-
-
-
-
-
-
-
Y
Y
-
SES_0
SES_0
SES_1
SES_1
-
SES_0
SES_0
SES_1
SES_1
SES_1
SES_1
SES_1
SES_1
-
SES_2
SES_2
SES_2
SES_2
SES_0
SES_0
SES_0
SES_0
MSMC_SMS
SMS_2
-
-
-
Y
Y
SMS_0
SMS_0
SMS_1
SMS_1
-
-
-
-
-
-
-
-
-
SMS_0
SMS_0
SMS_1
SMS_1
SMS_1
SMS_1
SMS_1
SMS_1
-
SMS_2
SMS_2
SMS_2
SMS_2
SMS_0
SMS_0
SMS_0
SMS_0
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
-
-
-
-
Y
Y
-
-
-
-
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
-
-
-
-
Y
Y
-
-
-
-
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
11
11
11
11
-
2, 11
2,11
3, 11
3, 11
-
-
-
-
-
Y
Y
-
-
-
-
-
-
11
11
11
11
11
11
11
11
11
11
11
11
-
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Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
-
Y
Y
-
-
-
-
-
Y
Y
-
-
-
-
-
QM
Y
-
-
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MASTERS
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0_Master
MSMC_SYS
NETCP
PCIE0
PCIE1
QM_Master1
QM_Master2
QM_SEC
USB0
USB1
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 7-1. AM5K2E04/02 Data Space Interconnect (continued)
Slaves
-
-
-
-
-
-
-
-
-
3, 11
-
1, 11
11
-
Y
-
-
Y
-
2, 11
-
11
11
-
-
-
-
-
AEMIF16
-
11
11
11
11
-
2, 11
2, 11
3, 11
3, 11
11
11
-
10
10
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
-
Y
-
Y
Y
-
-
Y
Y
Y
-
-
-
-
Y
Y
-
-
-
-
-
-
SES_1
SES_2
SES_2
SES_0
SES_1
SES_2
SES_0
SES_0
-
SES_1
SES_1
SES_1
SES_1
-
SES_1
SES_1
SES_1
SES_1
Y
-
Y
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
Y
MSMC_SMS
-
SMS_1
SMS_1
SMS_1
SMS_1
-
SMS_1
SMS_1
SMS_1
SMS_1
Y
-
SMS_1
SMS_2
SMS_2
SMS_0
SMS_1
SMS_2
SMS_0
SMS_0
-
11
11
-
-
-
-
-
2, 11
3, 11
3, 11
Y
11
-
11
11
11
11
-
2, 11
Y
Y
Y
Y
Y
-
Y
Y
Y
-
-
-
Y
Y
Y
QM
-
Y
Y
-
-
Y
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
Y
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7.3
Switch Fabric Connections Matrix - Configuration Space
The figures below show the connections between masters and slaves through various sections of the
TeraNet.
Bridge_12
Bridge_13
Bridge_14
From TeraNet_3_A
From TeraNet_3_C
AM5K2E
MPU_2
Tracer_QM_CFG1
MPU_6
Tracer_QM_CFG2
Tracer_SM
MPU_10
S
M
QM_SS_
CFG1
M
QM_SS_
CFG2
S
Semaphore
Tracer
_EDMA
CC0 & CC4
TNet_3P_M
CPU/3
S
S
S
S
CC0
CC4
Tracer
_EDMA
CC1 - CC3
TNet_3P_C
CPU/3
MPU_9
Tracer_INTC
TNet_3P_L
CPU/3
Tracer_CFG
MPU_0
S
S
S
S
S
S
CC1
CC2
CC3
S
S
ARM INTC
CP_INTC02
DBG_TBR_SYS
(Debug_SS)
TBR_SYS_
ARM_CorePac
To TeraNet_3P_B
To TeraNet_3P_Tracer
Figure 7-4. TeraNet 3P_A
120
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From TeraNet_3P_A
AM5K2E
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
TNet_3P_N
CPU/3
TNet_3P_D
CPU/3
S
CP_T0-T8
(MSMC)
S
S
S
NetCP
TSIP
S
10GbE CFG
AM5K2E04 Only
MPU_11
To TeraNet_6P_B
Figure 7-5. TeraNet 3P_B
Bridge 20
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System Interconnect
121
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Bridge 20
From TeraNet_3P_B
AM5K2E
Figure 7-6. TeraNet 6P_B www.ti.com
S
S
S
S
S
S
S
USIM
OTP
Debug SS
PLL_CTL
GPSC
BOOT_CFG
S
S
S
GPIO
S
USB PHY CFG 0-1
S
PCIe SerDes CFG 0-1
S
HyperLink SerDes
CFG 0-1
S
XGE SerDes CFG
AM5K2E04 Only
S
NetCP SerDes CFG
S
S
S
DDR3 PHY CFG
USB MMR CFG 0-1
SmartReflex
122
System Interconnect
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Tracer_MSMC_0
Tracer_MSMC_1
Tracer_MSMC_2
Tracer_MSMC_3
Tracer_MSMC_4
Tracer_MSMC_5
Tracer_MSMC_6
Tracer_MSMC_7
Tracer_MSMC_8
M
M
M
M
M
M
M
M
M
From TeraNet_3P_A
AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
AM5K2E
Tracer_SM
Tracer_CIC
Tracer_QM_CFG1
Tracer_QM_CFG2
Tracer_QM_M
M
M
M
M
M
Tracer_CFG
M
Tracer_EDMA3CC0_4
M
Tracer_EDMA3CC1_2_3
M
Tracer_SPI_
ROM_EMIF16
M
S
Debug_SS
STM
Figure 7-7. TeraNet 3P_Tracer
The following tables list the master and slave end point connections.
Intersecting cells may contain one of the following:
• Y — There is a connection between this master and that slave.
• - — There is NO connection between this master and that slave.
• n — A numeric value indicates that the path between this master and that slave goes through bridge n.
System Interconnect
123
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SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 7-2. Configuration Space Interconnect - Section 1
SLAVES www.ti.com
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0
MSMC_SYS
NETCP
MASTERS
DBG_DAP
TSIP_DMA
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
124
System Interconnect
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
Y
Y
-
-
-
-
-
-
12
12
-
-
-
-
12
12
-
12
12
-
12
12
-
-
-
-
13
13
-
-
-
-
-
-
-
12
Y
-
Y
Y
-
-
12
12
12
-
12
12
12
Y
-
-
-
13
13
-
-
-
12
12
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
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-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
-
-
-
-
-
-
12
Y
-
-
-
13
13
-
-
-
12
12
-
12
12
-
12
12
12
-
-
-
-
-
-
-
-
12
-
-
Y
Y
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 7-2. Configuration Space Interconnect - Section 1 (continued)
SLAVES
MASTERS
PCIE0
PCIE1
QM_Master1
QM_Master2
QM_SEC
USB0
USB1
-
-
12
12
-
-
-
-
-
12
12
12
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
Table 7-3. Configuration Space Interconnect - Section 2
SLAVES
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
-
-
12
12
-
-
-
MASTERS
DBG_DAP
TSIP_DMA
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Y -
12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 -
Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
13 13 13 13 13 13 13 13 13 13 -
13 13 13 13 13 13 13 13 13 13 -
14 14 14 14 14 14 14 14 14 14 -
14 14 14 14 14 14 14 14 14 14 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
System Interconnect
125
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SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 7-3. Configuration Space Interconnect - Section 2 (continued)
SLAVES www.ti.com
MASTERS
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
13 13 13 13 13 13 13 13 13 13 -
13 13 13 13 13 13 13 13 13 13 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
14 14 14 14 14 14 14 14 14 14 -
14 14 14 14 14 14 14 14 14 14 -
-
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
14 14 14 14 14 14 14 14 14 14 14 -
14 14 14 14 14 14 14 14 14 14 -
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
-
12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 -
HyperLink0_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
MSMC_SYS
NETCP
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
PCIE0
PCIE1
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
QM_Master1
QM_Master2
QM_SEC
USB0
USB1
12 12 12 12 12 -
12 12 12 12 12 -
12 -
12 -
12 -
Table 7-4. Configuration Space Interconnect - Section 3
SLAVES
MASTERS
DBG_DAP
TSIP_DMA
EDMA0_CC_TR
126
System Interconnect
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 7-4. Configuration Space Interconnect - Section 3 (continued)
SLAVES
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0_Master
MSMC_SYS
NETCP
PCIE0
PCIE1
QM_Master1
QM_Master2
QM_SEC
USB0
USB1
MASTERS
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
-
-
-
-
-
-
-
-
-
-
12 12 12
12 12 12
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12
-
-
-
12 12 12
-
12 12 12
12 12 12
-
-
-
-
12 12 12
12 12 12
-
-
-
-
-
-
-
-
-
-
-
-
-
13 13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13 13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14 14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14 14
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
12 12
-
-
-
-
-
Y
-
-
12 12
-
12 12
-
-
-
-
12 12
-
-
-
-
-
12 12
-
-
-
-
-
-
-
-
-
-
-
-
13
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
-
-
-
-
-
-
-
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12 12 12 12 12
12 12 12 12 12 12 12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12 12 12 12 12
-
-
-
12 12 12 12 12 12 12
-
12 12 12 12 12 12 12
12 12 12 12 12 12 12
-
-
-
-
12 12 12 12 12 12 12
12 12 12 12 12 12 12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
13 13 13 13 13 13 13 13 13 13
-
-
-
14 14 14 14 14 14 14 14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
12
12 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12
-
12
-
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12
Y
-
Y
-
Y
-
-
Y
-
-
Y
-
-
Y
-
-
Y
-
-
Y
-
-
Y
-
-
Y
-
-
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
-
-
-
System Interconnect
127
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www.ti.com
7.4
Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User-programmable priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means higher priority — PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. All the Packet
DMA-based peripherals also have internal registers to define the priority level of their initiated transactions.
The Packet DMA secondary port is one master port that does not have priority allocation register inside the Multicore Navigator. The priority level for transaction from this master port is described by the
QM_PRIORITY bit field in the CHIP_MISC_CTL0 register shown in and
For all other modules, see the respective User's Guides listed in
for programmable priority registers.
128
System Interconnect
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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
8 Device Boot and Configuration
START ADDRESS SIZE
0xc17_e000 0xc00
0xc18_6f80
0xc18_7000
0x80
0x5000
0xc18_c000
0xc18_d000
0xc18_e000
0xc18_f000
0xc19_0000
0xc19_7e80
0xc19_7f00
0x1000
0x1000
0x1000
0x1000
0x7e80
080
4
0xc1a_6e00
0xc1a_7000
0xc1a_a000
0xc1a_d000
0xc1a_d004
0xc1a_d008
0xc1a_d00c
0xc1a_e000
0xc1a_e400
0xc1a_e800
4
4
0x200
0x3000
0x3000
4
4
0x400
0x400
0x400
0xc1a_ec00
0xc1a_f000
0xc1a_f400
0xc1a_f800
0xc1a_fc00
0xc1b_0000
0xc1b_0180
0xc1b_0200
0xc1b_0300
0x400
0x400
0x400
0x400
0x400
0x180
0x80
0x100
0x100
8.1
Device Boot
8.1.1
Boot Sequence
The boot sequence is a process by which the internal memory is loaded with program and data sections.
The boot sequence is started automatically after each power-on reset or warm reset.
The
AM5K2E0x supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[15:0] device configuration inputs to determine the software configuration that must be completed. For more details on boot sequence see the KeyStone II Architecture
ARM Bootloader User's Guide ( SPRUHJ3 ).
For AM5K2E0x non-secure devices, there is only one type of booting: the ARM CorePac as the boot master.The ARM CorePac does not support no-boot mode. The ARM CorePac needs to read the bootmode register to determine how to proceed with the boot.
shows addresses reserved for boot by the ARM CorePac.
Table 8-1. ARM Boot RAM Memory Map
DESCRIPTION
Context RAM not Scrubbed on Secure boot
Global Level 0 Non-secure Translation table
Global Non-secure Page Table for memory Covering ROM
Core 0 Non-secure Level 1 Translation table
Core 1 Non-secure Level 1 Translation table
Core 2 Non-secure Level 1 Translation table
Core 3 Non-secure Level 1 Translation table
Packet Memory Buffer
PCIE Block
Host Data Address (boot magic address for secure boot through master peripherals)
DDR3 Configuration Structure
Boot Data
Supervisor Stack, Each Core Gets 0xc000 Bytes
ARM Boot Magic Address, Core 0
ARM Boot Magic Address, Core 1
ARM Boot Magic Address, Core 2
ARM Boot Magic Address, Core 3
Abort Stack, Core 0
Abort Stack, Core 1
Abort Stack, Core 2
Abort Stack, Core 3
Unknown Mode Stack, Core 0
Unknown mOde Stack, Core 1
Unknown Mode Stack, Core 2
Unknown Mode Stack, Core 3
Boot Version String, Core 0
Boot Status Stack, Core 0
Boot Stats, Core 0
Boot Log, Core 0
Device Boot and Configuration
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START ADDRESS SIZE
0xc1b_0400 0x100
0xc1b_0500
0xc1b_0600
0xc1b_1fe0
0xc1b_4000
0xc1b_4180
0x100
0x19e0
0x1010
0x180
0x80
0xc1b_4200
0xc1b_4300
0xc1b_4400
0xc1b_4500
0xc1b_4600
0x100
0x100
0x100
0x100
0x19e0
0xc1b_5fe0
0xc1b_6000
0xc1b_6180
0xc1b_6200
0xc1b_6300
0xc1b_6400
0xc1b_6500
0xc1b_6600
0xc1b_7fe0
0xc1b_8000
0x1010
0x180
0x80
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x180
0xc1b_8180
0xc1b_8200
0xc1b_8300
0xc1b_8400
0xc1b_8500
0xc1b_8600
0xc1b_9fe0
0xc1c_0000
0x80
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x4_0000
Table 8-1. ARM Boot RAM Memory Map (continued)
DESCRIPTION
Boot RAM Call Table, Core 0
Boot Parameter Tables, Core 0
Boot Data, Core 0
Boot Trace, Core 0
Boot Version String, Core 1
Boot Status Stack, Core 1
Boot Stats, Core 1
Boot Log, Core 1
Boot RAM Call Table, Core 1
Boot Parameter Tables, Core 1
Boot Data, Core 1
Boot Trace, Core 1
Boot Version String, Core 2
Boot Status Stack, Core 2
Boot Stats, Core 2
Boot Log, Core 2
Boot RAM Call Table, Core 2
Boot Parameter Tables, Core 2
Boot Data, Core 2
Boot Trace, Core 2
Boot Version String, Core 3
Boot Status Stack, Core 3
Boot Stats, Core 3
Boot Log, Core 3
Boot RAM Call Table, Core 3
Boot Parameter Tables, Core 3
Boot Data, Core 3
Boot Trace, Core 3
Secure MSMC
8.1.2
Boot Modes Supported
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:
• Public ROM Boot when the ARM CorePac Core0 is the boot master — In this boot mode, the ARM
CorePac performs the boot process. When the ARM CorePac Core0 finishes the boot process, it may send Cortex-A15 processor cores through IPC registers.
• Secure ROM Boot when the ARM CorePac0 is the boot master — The ARM CorePac Core0 are released from reset simultaneously and begin executing from secure ROM. The ARM CorePac Core0 initiates the boot process. For more information, refer to the Secure device Addendum.
The boot process performed by the ARM CorePac Core0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[15:0] value in the DEVSTAT register. The ARM CorePac Core0 read this value, and then execute the associated boot process in software. The figure below shows the bits associated with BOOTMODE[15:0] pins (DEVSTAT[16:1] register bits) when the ARM CorePac is the boot master. Note that
does not include bit 0 of the DEVSTAT contents. Bit 0 is used to select overall system endianess that is independent of the boot mode.
130
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The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error occurs.
The PLL settings are shown at the end of this section, and the PLL set-up details can be found in
NOTE
It is important to keep in mind that BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits of the DEVSTAT register.
Figure 8-1. DEVSTAT Boot Mode Pins ROM Mapping
16
X
SlaveAddr
NETC
P clk
X
Port
15
X
X
14
0
1
13
X
Port
12
PLLEN
Bus Addr
0
Width
Base Addr
Csel
Wait
1 First Block
Ref clk
Ref clk
X
Mode
Width
Clear
Ext Con
Bar Config
Data Rate
Port
11
DEVSTAT Boot Mode Pins ROM Mapping
10 9 8 7 6 5 4 3 2 1
X
SYS PLL
CONFIG
Min
0 0 0
0 0 0
Param ldx
Port
X Port
Param ldx
0 0 1
0 1 0
X
Port
Chip Sel 0 (ARM Boot
Master)
Lane Setup
X
X
SYS PLL
CONFIG
0
Min
0
1
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
Min 1 1 1
Mode
SLEEP
I
2
C SLAVE
I
2
C MASTER
SPI
EMIF
NAND
Ethernet
PCIe
HyperLink
UART
8.1.2.1
Boot Device Field
The Boot Device field DEVSTAT[16-14-4-3-2-1] defines the boot device that is chosen.
shows the supported boot modes.
Bit Field
16, 14, 4, 3, 2, Boot Device
1
Table 8-2. Boot Mode Pins: Boot Device Values
Description
Device boot mode - ARM is a boot master when BOOTMODE[8]=0
• Sleep = X0[Min]000b
• I
2
C Slave = [Slave Addr1]1[Min]000 b
• I
2
C Master = XX[Min]001b
• SPI = [Width][Csel0][Min]010b
• EMIF = 0X0011b
• NAND = 1X[Min]011b
• Ethernet (SGMII) = [Pa clk][Ref Clk0][Min]101b
• PCI = XBar Config2]0110b
• Hyperlink = [Port][Ref Clk0]1110b
• UART = XX[Min]111b
8.1.2.2
Device Configuration Field
The device configuration fields DEVSTAT[16:1] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode.
8.1.2.2.1 Sleep Boot Mode Configuration
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16
X
15
X
14
0
13
X
Figure 8-2. Sleep Boot Mode Configuration Fields Description
12
PLLEN
11
DEVSTAT Boot Mode Pins ROM Mapping
10 9 8 7 6 5
X
Boot
Master
Sys PLL Config
4
Min
3 2
000
1 0
Lendian
Table 8-3. Sleep Boot Configuration Field Descriptions
Bit Field
16-15 Reserved
4
Description
Reserved
14
13
12
11-9
8
Boot Devices Boot Device- used in conjunction with Boot Devices [Used in conjunction with bits 3-1]
• 0 = Sleep (default)
• Others = Other boot modes
Reserved
PLLEN
Reserved
Boot Master
Enable the System PLL
• 0 = PLL disabled (default)
• 1 = PLL enabled
Reserved
This pin must be pulled down to GND
7-5 SYS PLL
Setting
Min
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
shows settings for various input clock frequencies.
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
3-1
0
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices Boot Devices[3:1] used in conjunction with Boot Device [14]
• 000 = Sleep
• Others = Other boot modes
Lendian Endianess (device)
• 0 = Big endian
• 1 = Little endian
8.1.2.2.2 I
2
C Boot Device Configuration
8.1.2.2.2.1 I
2
C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
16 15
Slave Addr
14
1
13
Port
12
Figure 8-3. I
2
C Passive Mode Device Configuration Fields
11
DEVSTAT Boot Mode Pins ROM Mapping
10 9 8 7 6 5
X
Boot
Master
Sys PLL Config
4
Min
3 2
000
1 0
Lendian
Bit Field
16-15 Slave Addr
Table 8-4. I
2
C Passive Mode Device Configuration Field Descriptions
Description
I
2
C Slave boot bus address
• 0 = I
2
C slave boot bus address is 0x00
• 1 = I
2
C slave boot bus address is 0x10 (default)
• 2 = I
2
C slave boot bus address is 0x20
• 3 = I
2
C slave boot bus address is 0x30
132
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8.1.2.2.2.2 I
2
C Master Mode
In master mode, the I
2
C device configuration uses ten bits of device configuration instead of seven as used in other boot modes. In this mode, the device makes the initial read of the I
2
C EEPROM while the
PLL is in bypass mode. The initial read contains the desired clock multiplier, which must be set up prior to any subsequent reads.
16 15
Reserved
14 13 12
Bus Addr
Figure 8-4. I
2
C Master Mode Device Configuration Fields
11
DEVSTAT Boot Mode Pins ROM Mapping
10
Param ldx/Offset
9 8
Boot Master
7
Reserved
6 5
Port
4
Min
3 2 1
001
0
Lendian
Bit Field
16-14 Reserved
13-12 Bus Addr
11-9 Param Idx
8
7
Table 8-4. I
2
C Passive Mode Device Configuration Field Descriptions (continued)
Bit Field Description
14
13-12
Boot Devices Boot Device[14] used in conjunction with Boot Devices [Use din conjunction with bits 3-1]
• 0 = Other boot modes
• 1= I
2
C Slave boot mode
Port I
2
C port number
• 0 = I
2
C0
• 1 = I
2
C1
• 2 = I
2
C2
• 3 = Reserved
11-9 Reserved
8 Boot Master
7-5
4
SYS PLL
Setting
Min
Reserved
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
shows settings for various input clock frequencies.
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
3-1
0
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices Boot Devices[3:1] used in conjunction with Boot Device [14]
• 000 = I
2
C Slave
• Others = Other boot modes
Lendian Endianess
• 0 = Big endian
• 1 = Little endian
Boot Master
Reserved
Table 8-5. I
2
C Master Mode Device Configuration Field Descriptions
Description
Reserved
I
2
C bus address slave device
• 0 = I
2
C slave boot bus address is 0x50 (default)
• 1 = I
2
C slave boot bus address is 0x51
• 2 = I
2
C slave boot bus address is 0x52
• 3 = I
2
C slave boot bus address is 0x53
Parameter Table Index
• 0-7 = This value specifies the parameter table index (default = 0)
This pin must be pulled down to GND
Reserved
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Bit
6-5
4
3-1
0
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Field
Port
Min
Table 8-5. I
2
C Master Mode Device Configuration Field Descriptions (continued)
Description
I
2
C port number
• 0 = I
2
C0 (default)
• 1 = I
2
C1
• 2 = I
2
C2
• 3 = Reserved
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices Boot Devices[3:1]
• 001 = I
2
C Master
• Others = Other boot modes
Lendian Endianess
• 0 = Big endian
• 1 = Little endian
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8.1.2.2.3 SPI Boot Device Configuration
Bit Field
16-15 Width
14-13 Csel
12-11 Mode
10-9
8
7-5
4
3-1
0
16
Width
15
Port
Boot Master
Param Idx
Min
14
Csel
13
Boot Devices
Lendian
12
Mode
11
Figure 8-5. SPI Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
10 9 8
Port Boot Master
7 6 5
Param Ind
4
Min
3 2 1
010
0
Lendian
Table 8-6. SPI Device Configuration Field Descriptions
Description
SPI address width configuration
• 0 = 16-bit address values are used
• 1 = 24-bit address values are used (default)
The chip select field value 0-3 (default = 0)
Clk Polarity/ Phase
• 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
• 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK.
• 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge (default).
• 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK.
Specify SPI port
• 0 = SPI0 used (default)
• 1 = SPI1 used
• 2 = SPI2 used
• 3 = Reserved
This pin must be pulled down to GND
Parameter Table Index
• 0-7 = This value specifies the parameter table index (default = 0)
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1]
• 010 = SPI boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
8.1.2.2.4 EMIF Boot Device Configuration
16
0
15 14
Base Addr
13
Wait
Figure 8-6. EMIF Boot Device Configuration Fields
12
Width
DEVSTAT Boot Mode Pins ROM Mapping
11 10 9 8
X Chip Sel Boot Master
7 6 5 4 3 2 1
Sys PLL Cfg 0 011
0
Lendian
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Bit
16
Field
Boot Devices
15-14 Base Addr
13
12
11
10-9
8
7-5
4-1
0
Wait
Width
Reserved
Chip Sel
Boot Master
SYS PLL Setting
Boot Devices
Lendian
Table 8-7. EMIF Boot Device Configuration Field Descriptions
Description
Boot Devices[16] used conjunction with Boot Devices[4] and Boot Devices [Used in conjunction with bits
3-1]
• 0 = EMIF boot mode
• 1 = Other boot modes
Base address (0-3) used to calculate the branch address. Branch address is the chip select plus
Base Address *16MB
Extended Wait
• 0 = Extended Wait disabled
• 1 = Extended Wait enabled
EMIF Width
• 0 = 8-bit EMIF Width
• 1 = 16-bit EMIF Width
Reserved
Chip Sel that specifies the chip select region, EMIF16 CS2-EMIF16 CS5.
• 00 = EMIF16 CS2(EMIFCE0)
• 01 = EMIF16 CS3 (EMIFCE1)
• 10 = EMIF16 CS4 (EMIFCE2)
• 11 = EMIF16 CS5 (EMIFCE3)
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
shows settings for various input clock frequencies.
Boot Devices[4] used conjunction with Boot Devices[16]
• 0011 = EMIF boot mode
• 1XXX = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
8.1.2.2.5 NAND Boot Device Configuration
16
1
Bit
16
11-9
8
15 14
First Block
13 12
Clear
Field
Boot Devices
15-13 First Block
12 Clear
Chip Sel
Boot Master
11
X
Figure 8-7. NAND Boot Device Configuration Fields
10
DEVSTAT Boot Mode Pins ROM Mapping
9
Chip Sel
8
Boot Master
7 6
Sys PLL Cfg
5 4
Min
3 2 1
011
0
Lendian
Table 8-8. NAND Boot Device Configuration Field Descriptions
Description
Boot Devices[16] used conjunction with Boot Devices [3-1]
• 0 = Other boot modes
• 1 = NAND boot mode
First Block. This value is used to calculate the first block read. The first block read is the first block value
*16.
ClearNAND
• 0 = Device is not a ClearNAND (default)
• 1 = Device is a ClearNAND
Chip Sel that specifies the chip select region, EMIF16 CS2-EMIF16 CS5.
• 00 = EMIF16 CS2(EMIFCE0)
• 01 = EMIF16 CS3 (EMIFCE1)
• 10 = EMIF16 CS4 (EMIFCE2)
• 11 = EMIF16 CS5 (EMIFCE3)
This pin must be pulled down to GND
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Bit
7-5
4
3-1
0
Field
SYS PLL Setting
Min
Lendian
Table 8-8. NAND Boot Device Configuration Field Descriptions (continued)
Boot Devices
Description
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
shows settings for various input clock frequencies.
Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only
BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that would normally be set by the other BOOTMODE pins when Min is 0.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
Boot Devices
• 011 = NAND boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
8.1.2.3
Ethernet (SGMII) Boot Device Configuration
16
NETCP clk
15 14
Ref Clock
13
Figure 8-8. Ethernet (SGMII) Boot Device Configuration Fields
12
Ext Con
11
DEVSTAT Boot Mode Pins ROM Mapping
10 9 8 7
X
Lane
Setup
Boot Master
6 5
Sys PLL Cfg
4
Min
3 2 1
101
0
Lendian
Bit
16
8
7-5
Field
NETCP clk
15-14 Ref Clock
13-12 Ext Con
11-9 Lane Setup
Boot Master
SYS PLL Setting
Table 8-9. Ethernet (SGMII) Boot Device Configuration Field Descriptions
Description
NETCP clock reference
• 0 = NETCP clocked at the same reference as the core reference
• 1 = NETCP clocked at the same reference as the SerDes reference (default)
Reference clock frequency
• 0 = 125MHz
• 1 = 156.25MHz (default)
• 2 = Reserved
• 3 = Reserved
External connection mode
• 0 = MAC to MAC connection, master with auto negotiation
• 1 = MAC to MAC connection, slave with auto negotiation (default)
• 2 = MAC to MAC, forced link, maximum speed
• 3 = MAC to fiber connection
Lane Setup.
• 0 = All SGMII ports enabled (default)
• 1 = Only SGMII port 0 enabled
• 2 = SGMII port 0 and 1 enabled
• 3 = SGMII port 0, 1 and 2 enabled
• 4-5 = Reserved
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz.
shows settings for various input clock frequencies. (default = 4)
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Bit
4
3-1
0
Table 8-9. Ethernet (SGMII) Boot Device Configuration Field Descriptions (continued)
Field
Min
Description
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
Boot Devices
Lendian
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices
• 101 = Ethernet boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
8.1.2.3.1 PCIe Boot Device Configuration
Bit
16
16
Ref clk
15 14 13
Bar Config
12
Figure 8-9. PCIe Boot Device Configuration Fields
11
Port
DEVSTAT Boot Mode Pins ROM Mapping
10
X
9 8
Boot Master
7 6
Sys PLL Cfg
5 4 3 2 1
0110
Field
Ref clk
15-12 Bar Config
Table 8-10. PCIe Boot Device Configuration Field Descriptions
Description
PCIe Reference clock frequency
• 0 = 100MHz
• 1 = Reserved
PCIe BAR registers configuration
This value can range from 0 to 0xf. See
.
PCIe Port number (0-1) 11
10-9
8
7-5
Port
Reserved
Boot Master
SYS PLL Setting
4-1
0
Boot Devices
Lendian
0
Lendian
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits.This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz.
shows settings for various input clock frequencies.
Boot Devices[4:1]
• 0110 = PCIe boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
138
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Table 8-11. BAR Config / PCIe Window Sizes
BAR0 BAR1
PCIe MMRs 32
16
16
32
16
16
32
32
64
4
4
4
32
16
32
32
32
64
128
128
128
32-BIT ADDRESS TRANSLATION
BAR2
32
BAR3
32
BAR4
32
16
32
32
32
64
64
32
64
64
64
64
128
128
128
256
64
64
64
64
128
256
128
256
256
64-BIT ADDRESS
TRANSLATION
BAR2/3 BAR4/5
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
BAR CFG
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
BAR5
Clone of
BAR4
256
512
1024
2048
256
512
1024
2048
8.1.2.3.2 HyperLink Boot Device Configuration
16
X
15 14
RefClk
13 12
Data Rate
Figure 8-10. HyperLink Boot Device Configuration Fields
11
DEVSTAT Boot Mode Pins ROM Mapping
X
10 9 8
Boot Master
7 6
Sys PLL Cfg
5 4 3 2 1
1110
Table 8-12. HyperLink Boot Device Configuration Field Descriptions
Description Bit
16
Field
Reserve
15-14 Ref Clocks
13-12 Data Rate
HyperLink reference clock configuration
• 0 = 125 MHz
• 1 = 156.25 MHz
• 2-3 = Reserved
HyperLink data rate configuration
• 0 = 1.25 GBs
• 1 = 3.125 GBs
• 2 = 6.25 GBs
• 3 = 12.5GBs
11-9 Reserved
8 Boot Master
7-5 SYS PLL
Setting
4-1 Boot Devices
0 Lendian
0
Lendian
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz.
shows settings for various input clock frequencies.
Boot Devices[4:1]
• 1110 = HyperLink boot mode
• Others = Other boot modes
Endianess
• 0 = Big endian
• 1 = Little endian
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8.1.2.3.3 UART Boot Device Configuration
16
X
15
X
14
X
13
X
12
Port
Figure 8-11. UART Boot Mode Configuration Field Description
11
X
DEVSTAT Boot Mode Pins ROM Mapping
10
X
9
X
8
Boot Master
7 6
Sys PLL Config
5 4
Min
3 2 1
111
0
Lendian
Table 8-13. UART Boot Configuration Field Descriptions
Bit
12
Field
16-13 Reserved
Port
11-9 Reserved
8 Boot Master
7-5
4
3-1
0
SYS PLL
Setting
Min
Description
Not Used
UART Port number
• 0 = UART0
• 1 = UART1
Not Used
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
shows settings for various input clock frequencies. (default = 4)
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices Boot Devices[3:1]
• 111 = UART boot mode
• Others = Other boot modes
Lendian Endianess
• 0 = Big endian
• 1 = Little endian
8.1.2.4
Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the most common format the RBL employs to determine the boot flow. These boot parameter tables have certain parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The common entries in the boot parameter table are shown in
.
4
6
8
10
12
14
16
18
20
BYTE OFFSET NAME
0 Length
2 Checksum
Boot Mode
Port Num
SW PLL, MSW
SW PLL, LSW
Reserved
Reserved
System Freq
Core Freq
Boot Master
Table 8-14. Boot Parameter Table Common Parameters
DESCRIPTION
The length of the table, including the length field, in bytes.
The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum verification of the table by the boot ROM.
Internal values used by RBL for different boot modes.
Identifies the device port number to boot from, if applicable
PLL configuration, MSW
PLL configuration, LSW
Reserved
Reserved
The Frequency of the system clock in MHz
The frequency of the core clock in MHz
Set to FALSE if ARM is the master core.
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8.1.2.4.1 EMIF16 Boot Parameter Table
BYTE OFFSET NAME
22 Options
24
26
28
30
32
34
36
38
Type
Branch Address MSW
Branch Address LSW
Chip Select
Memory Width
Wait Enable
Async Config MSW
Async Config LSW
Table 8-15. EMIF16 Boot Parameter Table
DESCRIPTION
Async Config Parameters are used.
• 0 = Value in the async config paramters are not used to program async config registers.
• 1 = Value in the async config paramters are used to program async config registers.
Set to 0 for EMIF16 (NOR) boot
Most significant bit for Branch address (depends on chip select)
Least significant bit for Branch address (depends on chip select)
Chip Select for the NOR flash
Memory width of the EMIF16 bus (16 bits)
Extended wait mode enabled
• 0 = Wait enable is disabled
• 1 = Wait enable is enabled
Async Config Register MSW
Async Config Register LSW
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
NO
YES
YES
YES
YES
YES
NO
NO
8.1.2.4.2 Ethernet Boot Parameter Table
24
26
28
30
32
BYTE
OFFSET
22
34
NAME
Options
MAC High
MAC Med
MAC Low
Multi MAC High
Multi MAC Med
Multi MAC Low
Table 8-16. Ethernet Boot Parameter Table
DESCRIPTION
Bits 02 - 00 Interface
• 000 - 100 = Reserved
• 101 = SGMII
• 110 = Reserved
• 111 = Reserved
Bits 03 HD
• 0 = Half Duplex
• 1 = Full Duplex
Bit 4 Skip TX
• 0 = Send Ethernet Ready Frame every 3 seconds
• 1 = Don't send Ethernet Ready Frame
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
Bits 06 - 05 Initialize Config
• 00 = Switch, SerDes, SGMII and NETCP are configured
• 01 = Initialization is not done for the peripherals that are already enabled and running.
• 10 = Reserved
• 11 = None of the Ethernet system is configured.
Bits 15 - 07 Reserved
The 16 MSBs of the MAC address to receive during boot
The 16 middle bits of the MAC address to receive during boot
NO
NO
The 16 LSBs of the MAC address to receive during boot NO
The 16 MSBs of the multi-cast MAC address to receive during boot NO
The 16 middle bits of the multi-cast MAC address to receive during NO boot
The 16 LSBs of the multi-cast MAC address to receive during boot NO
Device Boot and Configuration
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52
66
68
70
72
54
56
58
60
62
64
38
40
42
44
46
48
50
BYTE
OFFSET
36
NAME
Source Port
Dest Port
Device ID 12
Device ID 34
Dest MAC High
Dest MAC Med
Dest MAC Low
Lane Enable
SGMII Config
SGMII Control
SGMII Adv Ability
SGMII TX Cfg High
SGMII TX Cfg Low
SGMII RX Cfg High
SGMII RX Cfg Low
SGMII Aux Cfg High
SGMII Aux Cfg Low
PKT PLL Cfg MSW
PKT PLL CFG LSW
Table 8-16. Ethernet Boot Parameter Table (continued)
DESCRIPTION
The destination port to accept boot packets on.
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
The source UDP port to accept boot packets from. A value of 0 will NO accept packets from any UDP port
NO
NO The first two bytes of the device ID. This is typically a string value, and is sent in the Ethernet ready frame
The 2nd two bytes of the device ID.
NO
The 16 MSBs of the MAC destination address used for the Ethernet NO ready frame. Default is broadcast.
The 16 middle bits of the MAC destination address NO
NO The 16 LSBs of the MAC destination address
One bit per lane.
• 0 - Lane disabled
• 1 - Lane enabled
Bits 0-3 are the config index, bit 4 set if direct config used, bit 5 set if NO no configuration done
The SGMII control register value NO
The SGMII ADV Ability register value
The 16 MSBs of the SGMII Tx config register
NO
NO
The 16 LSBs of the SGMII Tx config register
The 16 MSBs of the SGMII Rx config register
The 16 LSBs of the SGMII Rx config register
NO
NO
NO
The 16 MSBs of the SGMII Aux config register
The 16 LSBs of the SGMII Aux config register
The packet subsystem PLL configuration, MSW
The packet subsystem PLL configuration, LSW
NO
NO
NO
NO
8.1.2.4.3 PCIe Boot Parameter Table
Table 8-17. PCIe Boot Parameter Table
BYTE
OFFSET
22
NAME
Options
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
24
26
Address Width
Link Rate
DESCRIPTION
Bits 00 Mode
• 0 = Host Mode (Direct boot mode)
• 1 = Boot Table Boot Mode
Bits 01 Configuration of PCIe
• 0 = PCIe is configured by RBL
• 1 = PCIe is not configured by RBL
Bit 03-02 Reserved
Bits 04 Multiplier
• 0 = SERDES PLL configuration is done based on SERDES register values
• 1 = SERDES PLL configuration based on the reference clock values
Bits 05-15 Reserved
PCI address width, can be 32 or 64
SerDes frequency, in Mbps. Can be 2500 or 5000
YES with in conjunction with BAR sizes
NO
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46
48
50
52
54
56
58
36
38
40
42
30
32
34
BYTE
OFFSET
28
Table 8-17. PCIe Boot Parameter Table (continued)
NAME
Reference clock
Window 1 Size
Window 2 Size
Window 3 Size
Window 4 Size
Vendor ID
Device ID
Class code Rev ID
MSW
DESCRIPTION
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
Reference clock frequency, in units of 10 kHz. Value values are 10000 NO
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz) and 31250 (312.5 MHz). A value of 0 means that value is already in the SerDes cfg parameters and will not be computed by the boot
ROM.
Window 1size.
YES
Window 2 size.
Window 3 size. Valid only if address width is 32.
Window 4 Size. Valid only if the address width is 32.
Vendor ID
Device ID
Class code revision ID MSW
Class code Rev ID
LSW
SerDes cfg msw
SerDes cfg lsw
Class code revision ID LSW
PCIe SerDes config word, MSW
PCIe SerDes config word, LSW
SerDes lane 0 cfg msw SerDes lane config word, msw lane 0
SerDes lane 0 cfg lsw SerDes lane config word, lsw, lane 0
SerDes lane 1 cfg msw SerDes lane config word, msw, lane 1
SerDes lane 1 cfg lsw SerDes lane config word, lsw, lane 1
Timeout period (Secs) The timeout period. Values 0 disables the time out
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
8.1.2.4.4 I
2
C Boot Parameter Table
OFFSET
22
24
26
28
30
34
36
38
40
FIELD
Option
Boot Dev Addr
Boot Dev Addr Ext
Broadcast Addr
Local Address
Bus Frequency
Next Dev Addr
Next Dev Addr Ext
Address Delay
Table 8-18. I
2
C Boot Parameter Table
VALUE
Bits 02 - 00 Mode
• 000 = Boot Parameter Table Mode
• 001 = Boot Table Mode
• 010 = Boot Config Mode
• 011 = Load GP header format data
• 100 = Slave Receive Boot Config
Bits 15 - 03= Reserved
The I
2
C device address to boot from
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
Extended boot device address
I
2
C address used to send data in the I
2
C master broadcast mode.
The I
2
C address of this device
The desired I
2
C data rate (kHz)
The next device address to boot (Used only if boot config option is selected)
YES
YES
NO
NO
NO
NO
The extended next device address to boot (Used only NO if boot config option is selected)
The number of CPU cycles to delay between writing the address to an I
2
C EEPROM and reading data.
NO
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22
24
26
28
30
32
34
14
16
18
20
42
44
46
36
38
40
40
42
44
34
36
38
24
26
28
30
32
8.1.2.4.5 SPI Boot Parameter Table
BYTE
OFFSET
22
Table 8-19. SPI Boot Parameter Table
NAME
Options
Address Width
NPin
Chipsel
Mode
C2Delay
Bus Freq, 100kHz
Read Addr MSW
Read Addr LSW
DESCRIPTION
Bits 01 & 00 Modes
• 00 = Load a boot parameter table from the SPI (Default mode)
• 01 = Load boot records from the SPI (boot tables)
• 10 = Load boot config records from the SPI (boot config tables)
• 11 = Load GP header blob
Bits 15- 02= Reserved
The number of bytes in the SPI device address. Can be 16 or 24 bit
The operational mode, 4 or 5 pin
The chip select used (valid in 4 pin mode only). Can be 0-3.
Standard SPI mode (0-3)
Setup time between chip assert and transaction
The SPI bus frequency in kHz.
The first address to read from, LSW
Next Chip Select Next Chip Select to be used (Used only in boot Config mode)
Next Read Addr MSW The Next read address (used in boot config mode only)
Next Read Addr LSW The Next read address (used in boot config mode only)
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
YES
YES
YES
YES
NO
NO
The first address to read from, MSW (valid for 24 bit address width only) YES
YES
NO
NO
NO
8.1.2.4.6 HyperLink Boot Parameter Table
Table 8-20. HyperLink Boot Parameter Table
BYTE
OFFSET
12
NAME
Options
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
NO
Number of Lanes
SerDes cfg msw
SerDes cfg lsw
SerDes CFG RX lane 0 cfg msw
SerDes CFG RXlane 0 cfg lsw
SerDes CFG TX lane 0 cfg msw
SerDes CFG TXlane 0 cfg lsw
SerDes CFG RX lane 1 cfg msw
SerDes CFG RXlane 1 cfg lsw
SerDes CFG TX lane 1 cfg msw
SerDes CFG TXlane 1 cfg lsw
SerDes CFG RX lane 2 cfg msw
SerDes CFG RXlane 2 cfg lsw
SerDes CFG TX lane 2 cfg msw
SerDes CFG TXlane 2 cfg lsw
SerDes CFG RX lane 3 cfg msw
SerDes CFG RXlane 3 cfg lsw
DESCRIPTION
Bits 00 Reserved
Bits 01 Configuration of Hyperlink
• 0 = HyperLink is configured by RBL
• 1 = HyperLink is not configured by RBL
Bits 15-02 = Reserved
Number of Lanes to be configured
PCIe SerDes config word, MSW
PCIe SerDes config word, LSW
SerDes RX lane config word, msw lane 0
SerDes RX lane config word, lsw, lane 0
SerDes TX lane config word, msw lane 0
SerDes TX lane config word, lsw, lane 0
SerDes RX lane config word, msw lane 1
SerDes RX lane config word, lsw, lane 1
SerDes TX lane config word, msw lane 1
SerDes TX lane config word, lsw, lane 1
SerDes RX lane config word, msw lane 2
SerDes RX lane config word, lsw, lane 2
SerDes TX lane config word, msw lane 2
SerDes TX lane config word, lsw, lane 2
SerDes RX lane config word, msw lane 3
SerDes RX lane config word, lsw, lane 3
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
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Table 8-20. HyperLink Boot Parameter Table (continued)
BYTE
OFFSET
48
50
NAME
SerDes CFG TX lane 3 cfg msw
SerDes CFG TXlane 3 cfg lsw
DESCRIPTION
SerDes TX lane config word, msw lane 3
SerDes TX lane config word, lsw, lane 3
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
NO
NO
34
36
38
28
30
32
8.1.2.4.7 UART Boot Parameter Table
BYTE
OFFSET
22
24
26
40
42
44
46
48
Table 8-21. UART Boot Parameter Table
NAME
Reserved
DESCRIPTION
None
Data Format
Protocol
Bits 00 Data Format
• 0 = Data Format is BLOB
• 1 = Data Format is Boot Table
Bits 15 - 01 Reserved
Bits 00 Protocol
• 0 = Xmodem Protocol
• 1 = Reserved
Bits 15 - 01 Reserved
Initial NACK Count Number of NACK pings to be sent before giving up
Max Err Count
NACK Timeout
Character Timeout nDatabits
Maximum number of consecutive receive errors acceptable.
Time (msecs) waiting for NACK/ACK.
Time Period between characters
Number of bits supported for data. Only 8 bits is supported.
NO
Parity nStopBitsx2
Bits 01 - 00 Parity
• 00 = No Parity
• 01 = Odd parity
• 10 = Even Parity
Bits 15 - 02 Reserved
NO
Number of stop bits times two. Valid values are 2 (stop bits = 1), 3 (Stop NO
Bits = 1.5), 4 (Stop Bits = 2)
Over sample factor The over sample factor. Only 13 and 16 are valid.
Flow Control Bits 00 Flow Control
• 0 = No Flow Control
• 1 = RTS_CTS flow control
Bits 15 - 01 Reserved
NO
NO
Data Rate MSW
Data Rate LSW
Baud Rate, MSW
Baud Rate, LSW
NO
NO
NO
NO
NO
NO
NO
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
NA
NO
8.1.2.4.8 NAND Boot Parameter Table
Table 8-22. NAND Boot Parameter Table
BYTE OFFSET
22
NAME
Options
DESCRIPTION
Bits 00 Geometry
• 0 = Geometry is taken from this table
• 1 = Geometry is queried from NAND device.
Bits 01 Clear NAND
• 0 = NAND Device is a non clear NAND and requires ECC
• 1 = NAND is a clear NAND and doesn.t need
ECC.
Bits 15 - 02 Reserved
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CONFIGURED THROUGH
BOOT CONFIGURATION PINS
NO
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Table 8-22. NAND Boot Parameter Table (continued)
36
38
40
30
32
34
BYTE OFFSET NAME
24 numColumnAddrBytes
26
28 numRowAddrBytes
DESCRIPTION
Number of bytes used to specify column address
Number of bytes used to specify row address.
numofDataBytesperPage_msw Number of data bytes in each page, MSW numofDataBytesperPage_lsw numPagesperBlock busWidth
Number of data bytes in each page, LSW
Number of Pages per Block
EMIF bus width. Only 8 or 16 bits is supported.
numSpareBytesperPage csel
First Block
Number of spare bytes allocated per page.
Chip Select number (valid chip selects are 2-5)
First block for RBL to try to read.
CONFIGURED THROUGH
BOOT CONFIGURATION PINS
NO
NO
NO
NO
NO
NO
NO
YES
YES
8.1.2.4.9 DDR3 Configuration Table
The RBL also provides an option to configure the DDR table before loading the image into the external memory. More information on how to configure the DDR3, refer to the Bootloader User Guide. The configuration table for DDR3 is shown in
Table 8-23. DDR3 Boot Parameter Table
BYTE
OFFSET
0
NAME
configselect msw
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
4
8
76
80
84
88
92
96
100
56
60
64
68
72
28
32
36
40
44
48
52
12
16
20
24 configselect slsw configselect lsw pllprediv pllMult pllPostDiv sdRamConfig sdRamConfig2 sdRamRefreshctl sdRamTiming1 sdRamTiming2 sdRamTiming3
IpDfrNvmTiming powerMngCtl iODFTTestLogic performcountCfg performCountMstRegSel readIdleCtl sysVbusmIntEnSet sdRamOutImpdedCalcfg tempAlertCfg ddrPhyCtl1 ddrPhyCtl2 proClassSvceMap mstId2ClsSvce1Map mstId2ClsSvce2Map
DESCRIPTION
Selecting the configuration register below that to be set. Each filed below is represented by one bit each.
Selecting the configuration register below that to be set. Each filed below is represented by one bit each.
Selecting the configuration register below that to be set. Each filed below is represented by one bit each.
PLL pre divider value (Should be the exact value not value -1)
PLL Multiplier value (Should be the exact value not value -1)
PLL post divider value (Should be the exact value not value -1)
SDRAM config register
SDRAM Config register
SDRAM Refresh Control Register
SDRAM Timing 1 Register
SDRAM Timing 2 Register
SDRAM Timing 3 Register
LP DDR2 NVM Timing Register
Power management Control Register
IODFT Test Logic Global Control Register
Performance Counter Config Register
Performance Counter Master Region Select Register
Read IDLE counter Register
System Interrupt Enable Set Register
SDRAM Output Impedence Calibration Config Register
Temperature Alert Configuration Register
DDR PHY Control Register 1
DDR PHY Control Register 1
Priority to Class of Service mapping Register
Master ID to Class of Service Mapping 1 Register
Master ID to Class of Service Mapping 2Register
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
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Table 8-23. DDR3 Boot Parameter Table (continued)
BYTE
OFFSET
104
108
112
116
120 - 376
NAME
eccCtl eccRange1 eccRange2 rdWrtExcThresh
Chip Config
DESCRIPTION
ECC Control Register
ECC Address Range1 Register
ECC Address Range2 Register
Read Write Execution Threshold Register
Chip Specific PHY configuration
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
NO
NO
NO
NO
NO
8.1.2.5
Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for:
• Any level of customization to current boot methods
• Definition of a completely customized boot
8.1.3
SoC Security
The TI SoC contains security architecture that allows the ARM CorePac to perform secure accesses within the device. For more information, contact a TI sales office for additional information available with the purchase of a secure device.
8.1.4
System PLL Settings
The PLL default settings are determined by the BOOTMODE[7:5] bits.
shows the settings for various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
NOTE
Other frequencies are supported, but require a boot in a pre-configured mode.
The configuration for the NETCP PLL is also shown. The NETCP PLL is configured with these values only if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the SGMII
SerDes clock). See
for details on configuring Ethernet boot mode. The output from the NETCP
PLL goes through an on-chip divider to reduce the frequency before reaching the NETCP. The NETCP
PLL generates 1050 MHz, and after the chip divider (/3), applies 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. DDR3 PLL and NETCP PLL are controlled by chip level MMRs. For details on how to set up the PLL see
operation of the PLL controller module, see the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide ( SPRUGV2 ).
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Table 8-24. System PLL Configuration
BOOTMODE
[7:5]
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
INPUT
CLOCK
FREQ
(MHz)
50.00
66.67
80.00
100.00
156.25
250.00
312.50
122.88
800 MHz DEVICE
4
7
0
0
3
0
0
PLLD PLLM SoC ƒ
0 31 800
23
19
800.04
800
15
40
31
40
12
800
800.78
800
800.78
798.72
1000 MHz DEVICE
0
4
3
0
4
0
0
PLLD PLLM SoC ƒ
0 39 1000
29
24
1000.05
1000
19
63
7
31
64
1000
1000
1000
1000
999.989
1200 MHz DEVICE
4
2
0
0
2
0
0
PLLD PLLM SoC ƒ
0 47 1200
35
29
1200.06
1200
23
45
47
22
19
1200
1197.92
1200
1197.92
1228.80
1400 MHz DEVICE
4
0
0
0
0
0
0
PLLD PLLM SoC ƒ
0 55 1400
41
34
1400.1
1400
27
17
55
8
22
1400
1406.3
1400
1406.3
1413.1
(1) The NETCP PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
(2) ƒ represents frequency in MHz.
NETCP = 350 MHz
(1)
PLLD PLLM SoC ƒ
(2)
0 41 1050
1
3
0
24
4
24
11
62
104
20
335
41
167
204
1050.053
1050
1050
1050
1050
1050
1049.6
8.2
Device Configuration
Certain device configurations like boot mode and endianess are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used.
8.2.1
Device Configuration at Device Reset
The logic level present on each device configuration pin is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the SoC.
describes the device configuration pins.
NOTE
If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see
.
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Table 8-25. Device Configuration Pins
CONFIGURATION PIN
LENDIAN
(1) (2)
PIN NO.
V30
IPD/IPU
IPU
(1)
DESCRIPTION
Device endian mode (LENDIAN)
• 0 = Device operates in big endian mode
• 1 = Device operates in little endian mode
Method of boot
• See
for more details.
BOOTMODE[15:0]
(1) (2)
AB33, AB32, AA33, IPD
AA30, Y32, Y30,
AB29, W33, W31,
V31, W32, W30,
V32, V33, Y29,
AA29
K32, K33 IPD AVSIFSEL[1:0]
(1) (2)
MAINPLLODSEL
(1) (2)
BOOTMODE_RSVD
(1)
Y33
Y31
IPD
IPD
AVS interface selection
• 00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
• 01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
• 10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
• 11 = I
2
C
Main PLL Output divider select
• 0 = Main PLL output divider needs to be set to 2 by BOOTROM
• 1 = Reserved
Boot Mode Reserved. Secondary function for GPIO15. Pulldown resistor required on pin.
(1) Internal 100μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU.
For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see
.
(2) These signal names are the secondary functions of these pins.
8.2.2
Peripheral Selection After Device Reset
Several of the peripherals on the AM5K2E0x are controlled by the Power Sleep Controller (PSC). By default, the PCIe and HyperLink are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code automatically enables the module.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide ( SPRUGV4 ).
8.2.3
Device State Control Registers
The AM5K2E0x device has a set of registers that are used to control the status of its peripherals. These registers are shown in
.
Table 8-26. Device State Control Registers
ADDRESS
START
0x02620000
0x02620008
0x02620018
0x0262001C
0x02620020
0x02620024
0x02620038
0x0262003C
0x02620040
ADDRESS
END
0x02620007
0x02620017
0x0262001B
0x0262001F
0x02620023
0x02620037
0x0262003B
0x0262003F
0x02620043
20B
4B
4B
4B
SIZE ACRONYM
8B Reserved
16B
4B
4B
4B
Reserved
JTAGID
Reserved
DEVSTAT
Reserved
KICK0
KICK1
Reserved
DESCRIPTION
See
See
See
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Table 8-26. Device State Control Registers (continued)
0x0262014C
0x02620150
0x02620154
0x02620158
0x0262015C
0x02620160
0x02620164
0x02620168
0x0262016C
0x02620180
0x02620184
0x02620190
0x02620194
0x02620198
0x0262019C
0x026201A0
0x026201A4
0x026201A8
0x026201AC
0x026201B0
ADDRESS
START
0x02620044
0x02620048
0x0262004C
0x02620050
0x02620054
0x02620058
0x0262005C
0x02620060
0x026200E0
0x02620110
0x02620118
0x02620130
0x02620134
0x02620138
0x0262013C
0x02620140
0x02620144
0x02620148
0x026201B4
0x026201B8
0x026201BC
0x026201C0
0x026201C4
0x026201C8
0x026201CC
0x026201D0
0x02620200
150
Device Boot and Configuration
0x0262014F
0x02620153
0x02620157
0x0262015B
0x0262015F
0x02620160
0x02620167
0x0262016B
0x0262017F
0x02620183
0x0262018F
0x02620193
0x02620197
0x0262019B
0x0262019F
0x026201A3
0x026201A7
0x026201AB
0x026201AF
0x026201B3
ADDRESS
END
0x02620047
0x0262004B
0x0262004F
0x02620053
0x02620057
0x0262005B
0x0262005F
0x026200DF
0x0262010F
0x02620117
0x0262012F
0x02620133
0x02620137
0x0262013B
0x0262013F
0x02620143
0x02620147
0x0262014B
0x026201B7
0x026201BB
0x026201BF
0x026201C3
0x026201C7
0x026201CB
0x026201CF
0x026201FF
0x02620203
4B
4B
4B
4B
4B
12B
4B
4B
4B
4B
4B
4B
4B
20B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
48B
4B
4B
4B
4B
4B
4B
48B
8B
24B
4B
4B
SIZE ACRONYM
4B Reserved
4B
4B
Reserved
Reserved
4B
4B
4B
Reserved
Reserved
Reserved
4B Reserved
128B Reserved
Reserved
MACID
Reserved
Reserved
RESET_STAT_CLR
Reserved
BOOTCOMPLETE
Reserved
RESET_STAT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DEVCFG
PWRSTATECTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SmartReflex Class0
DESCRIPTION
See
See
See
See
See
See
See
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0x02620268
0x0262026C
0x02620270
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202A4
0x026202A8
0x026202AC
0x026202B0
0x026202BC
0x026202C0
0x02620300
0x02620304
ADDRESS
START
0x02620204
0x02620208
0x0262020C
0x02620210
0x02620214
0x02620218
0x0262021C
0x02620220
0x02620240
0x02620244
0x02620248
0x0262024C
0x02620250
0x02620254
0x02620258
0x0262025C
0x02620260
0x02620264
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SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
Table 8-26. Device State Control Registers (continued)
4B
12B
4B
64B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
12B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
32B
SIZE ACRONYM
4B Reserved
4B
4B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCGR8
IPCGR9
IPCGR10
IPCGR11
Reserved
IPCGRH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCAR8
IPCAR9
IPCAR10
IPCAR11
Reserved
IPCARH
Reserved
TINPSEL
TOUTPSEL
0x0262026B
0x0262026F
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202A3
0x026202A7
0x026202AB
0x026202AF
0x026202BB
0x026202BF
0x026202FF
0x02620303
0x02620307
ADDRESS
END
0x02620207
0x0262020B
0x0262020F
0x02620213
0x02620217
0x0262021B
0x0262021F
0x0262023F
0x02620243
0x02620247
0x0262024B
0x0262024F
0x02620253
0x02620257
0x0262025B
0x0262025F
0x02620263
0x02620267
DESCRIPTION
See
See
See
See
See
See
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151
0x02620364
0x02620368
0x0262036C
0x02620370
0x02620374
0x02620378
0x0262039C
0x02620400
0x02620404
0x02620408
0x0262040C
0x02620600
0x02620700
0x02620704
0x02620710
0x02620714
0x02620718
0x0262071C
0x02620720
0x02620730
ADDRESS
START
0x02620308
0x0262030C
0x02620310
0x02620314
0x02620318
0x0262031C
0x02620320
0x02620324
0x02620328
0x0262032C
0x02620330
0x02620334
0x02620338
0x02620350
0x02620354
0x02620358
0x0262035C
0x02620360
0x02620734
0x02620738
0x02620750
0x02620800
0x02620C7C
0x02620C80
0x02620C98
0x02620C9C
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4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
SIZE ACRONYM
4B Reserved
4B
4B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RSTMUX8
RSTMUX9
RSTMUX10
RSTMUX11
Reserved
CorePLLCTL0
CorePLLCTL1
PASSPLLCTL0
PASSPLLCTL1
DDR3PLLCTL0
4B
4B
4B
4B
4B
DDR3PLLCTL1
Reserved
Reserved
Reserved
Reserved
132B Reserved
4B
4B
Reserved
ARMENDIAN_CFG0_0
4B
4B
ARMENDIAN_CFG0_1
ARMENDIAN_CFG0_2
4B
4B
4B
16B
4B
62B Reserved
256B Reserved
4B CHIP_MISC_CTL0
12B
4B
Reserved
SYSENDSTAT
Reserved
Reserved
Reserved
Reserved
SYNECLK_PINCTL
4B Reserved
24B USB_PHY_CTL
176B Reserved
1148B Reserved
4B CHIP_MISC_CTL1
24B Reserved
4B DEVSPEED
868B Reserved
0x02620367
0x0262036B
0x0262036F
0x02620373
0x02620377
0x0262039B
0x0262039F
0x02620403
0x02620407
0x0262040B
0x026205FF
0x026206FF
0x02620703
0x0262070F
0x02620713
0x02620717
0x0262071B
0x0262071F
0x0262072F
0x02620733
ADDRESS
END
0x0262030B
0x0262030F
0x02620313
0x02620317
0x0262031B
0x0262031F
0x02620323
0x02620327
0x0262032B
0x0262032F
0x02620333
0x02620337
0x0262034F
0x02620353
0x02620357
0x0262035B
0x0262035F
0x02620363
0x02620737
0x0262074F
0x026207FF
0x02620C7B
0x02620C7F
0x02620C97
0x02620C9B
0x02620FFF
Table 8-26. Device State Control Registers (continued)
DESCRIPTION
See
See
See
See
See
See
See
See
See
See
See
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8.2.3.1
Device Status (DEVSTAT) Register
The Device Status Register depicts device configuration selected upon a power-on reset by the POR or
RESETFULL pin. Once set, these bits remain set until a power-on reset. The Device Status Register is shown in the figure below.
31
Reserved
R-0
22
Figure 8-12. Device Status Register
21 20
Reserved
R/W-00
19
MAINPLLODSEL
R/W-x
18 17
AVSIFSEL
R/W-xx
16 1
BOOTMODE
R/W-x xxxx xxxx xxxx xxx
0
LENDIAN
R-x
(1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) x indicates the bootstrap value latched via the external pin
Table 8-27. Device Status Register Field Descriptions
Bit Field
31-22 Reserved
21-20 Reserved
19 MAINPLLODSEL
Reserved
Main PLL Output divider select
• 0 = Main PLL output divider needs to be set to 2 by BOOTROM
• 1 = Reserved
18-17 AVSIFSEL
Description
Reserved
16-1 BOOTMODE
AVS interface selection
• 00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
• 01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
• 10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
• 11 = Reserved
Determines the bootmode configured for the device. For more information on bootmode, see
.
0 LENDIAN
See the KeyStone II Architecture ARM Bootloader User's Guide ( SPRUHJ3 ).
Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or little endian mode (default).
• 0 = System is operating in big endian mode
• 1 = System is operating in little endian mode (default)
8.2.3.2
Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in
and described in
Figure 8-13. Device Configuration Register (DEVCFG)
31 5
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
4
PCIE1SSMODE
3
R/W-00
2
PCIE0SSMODE
1
R/W-00
0
SYSCLKOUTEN
R/W-1
Table 8-28. Device Configuration Register Field Descriptions
Bit Field Description
31-5 Reserved
4-3 PCIE1SSMODE
Reserved. Read only, writes have no effect.
Device Type Input of PCIe1SS
• 00 = Endpoint
• 01 = Legacy Endpoint
• 10 = Rootcomplex
• 11 = Reserved
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Bit
2-1
0
Table 8-28. Device Configuration Register Field Descriptions (continued)
Field Description
PCIE0SSMODE Device Type Input of PCIe0SS
• 00 = Endpoint
• 01 = Legacy Endpoint
• 10 = Rootcomplex
• 11 = Reserved
SYSCLKOUTEN SYSCLKOUT enable
• 0 = No clock output
• 1 = Clock output enabled (default)
8.2.3.3
JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x02620018. The JTAG ID Register is shown below.
Figure 8-14. JTAG ID (JTAGID) Register
12 31 28 27
VARIANT
R-xxxx
PART NUMBER
R-1011 1001 1010 0110
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
11
MANUFACTURER
R-0000 0010 111
1 0
LSB
R-1
Table 8-29. JTAG ID Register Field Descriptions
Bit Field
31-28 VARIANT
Value
xxxx
Description
Variant value
27-12 PART NUMBER 1011 1001 1010 0110 Part Number for boundary scan
11-1 MANUFACTURER 0000 0010 111 Manufacturer
0 LSB 1 This bit is read as a 1
NOTE
The value of the VARIANT and PART NUMBER fields depends on the silicon revision being used. See the Silicon Errata for details.
8.2.3.4
Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent spurious writes from changing any of the
Bootcfg MMR (memory mapped registers) values. When the kicker is locked (which it is initially after power on reset), none of the Bootcfg MMRs are writable (they are only readable). This mechanism requires an MMR write to each of the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is unlocked. See
for the address location. Once released, all the Bootcfg
MMRs having write permissions are writable (the read only MMRs are still read only). The KICK0 data is
0x83e70b13. The KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs locks the kicker mechanism and blocks writes to Bootcfg MMRs. To ensure protection to all Bootcfg
MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.
8.2.3.5
Reset Status (RESET_STAT) Register
The Reset Status Register (RESET_STAT) captures the status of global device reset (GR). Software can use this information to take different device initialization steps. The GR bit is written as 1 only when a global reset is asserted.
The Reset Status Register is shown in the figure and table below.
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Figure 8-15. Reset Status Register (RESET_STAT)
31
GR
30
R-1
Legend: R = Read only; -n = value after reset
Reserved
R- 0
Bit
31 GR
Field
30-0 Reserved
Table 8-30. Reset Status Register Field Descriptions
Description
Global reset status
• 0 = Device has not received a global reset.
• 1 = Device received a global reset.
Reserved.
0
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8.2.3.6
Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear Register is shown in the figure and table below.
Figure 8-16. Reset Status Clear Register (RESET_STAT_CLR)
31
GR
30
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Reserved
R- 0
1 0
Bit
31
Field
GR
30-0 Reserved
Table 8-31. Reset Status Clear Register Field Descriptions
Description
Global reset clear bit
• 0 = Writing a 0 has no effect.
• 1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved.
8.2.3.7
Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status to indicate the completion of the
ROM booting process. The Boot Complete register is shown in the figure and table below.
Figure 8-17. Boot Complete Register (BOOTCOMPLETE)
6 5 31 12
Reserved
11
BC11
10
BC10
9
BC9
8
BC8
R-0 RW-0 RW-0 RW-0 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
7 4
Reserved
3
R-0
2 1 0
Table 8-32. Boot Complete Register Field Descriptions
Description Bit Field
31-12 Reserved
11 BC11
10
9
8
7-0
BC10
BC9
BC8
ARM CorePac 3 boot status (AM5K2E04 only)
• 0 = ARM CorePac 3 boot NOT complete
• 1 = ARM CorePac 3 boot complete
ARM CorePac 2 boot status (AM5K2E04 only)
• 0 = ARM CorePac 2 boot NOT complete
• 1 = ARM CorePac 2 boot complete
ARM CorePac 1 boot status (AM5K2Ex)
• 0 = ARM CorePac 1 boot NOT complete
• 1 = ARM CorePac 1 boot complete
ARM CorePac 0 boot status
• 0 = ARM CorePac 0 boot NOT complete
• 1 = ARM CorePac 0 boot complete
Reserved
The BCx bit indicates the boot complete status of the corresponding ARM CorePac. All BCx bits are sticky bits — that is, they can be set only once by the software after device reset and they will be cleared to 0 on all device resets (warm reset and power-on reset).
Boot ROM code is implemented such that each ARM CorePac sets its corresponding BCx bit immediately before branching to the predefined location in memory.
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8.2.3.8
Power State Control (PWRSTATECTL) Register
The Power State Control Register (PWRSTATECTL) is controlled by the software to indicate the powersaving mode. Under ROM code, the CorePac reads this register to differentiate between the various power saving modes. This register is cleared only by POR and is not changed by any other device reset.
See the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ) for more information. The PWRSTATECTL register is shown in
and described in
Figure 8-18. Power State Control Register (PWRSTATECTL)
3 31
Hibernation Recovery Branch Address
RW-0000 0000 0000 0000 0
Legend: R = Read Only, RW = Read/Write; -n = value after reset
2
Hibernation Mode
RW-0
1
Hibernation
RW-0
0
Standby
RW-0
Bit Field
31-3 Hibernation
Recovery Branch
Address
2 Hibernation Mode
Table 8-33. Power State Control Register Field Descriptions
Description
Used to provide a start address for execution out of the hibernation modes.
1
0
Hibernation
Standby
Indicates whether the device is in hibernation mode 1 or mode 2.
• 0 = Hibernation mode 1
• 1 = Hibernation mode 2
Indicates whether the device is in hibernation mode or not.
• 0 = Not in hibernation mode
• 1 = Hibernation mode
Indicates whether the device is in standby mode or not.
• 0 = Not in standby mode
• 1 = standby mode
8.2.3.9
IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts.
The AM5K2E device has four IPCGRx registers (IPCGR8-IPCGR11) and the 66AK2E02 has two IPCGRx registers (IPCGR8 and IPCGR9). These registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the IPCGRx register generates an interrupt pulse to the ARM CorePac.
These registers also provide a Source ID facility identifying up to 28 different sources of interrupts.
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. There can be numerous sources for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation Register is shown in
and described in
.
Figure 8-19. IPC Generation Registers (IPCGRx)
31
SRCS27 - SRCS0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4 3 1
Reserved
R-000
0
IPCG
RW-0
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Bit Field
31-4 SRCSx
3-1
0
Bit Field
31-4 SRCCx
3-0
Reserved
IPCG
Reserved
Table 8-34. IPC Generation Registers Field Descriptions
Description
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an inter-ARM interrupt.
8.2.3.10 IPC Acknowledgment (IPCARx) Registers
The IPCARx registers facilitate inter-CorePac interrupt acknowledgment.
The AM5K2E04 device has four IPCARx registers and the AM5K02 has two IPCARx registers. These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to
BOOTCFG module space can write to these registers. The IPC Acknowledgment Register is shown in the following figure and table.
Figure 8-20. IPC Acknowledgment Registers (IPCARx)
4 31
SRCC27 - SRCC0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
3
Reserved
R-0000
0
Table 8-35. IPC Acknowledgment Registers Field Descriptions
Description
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Clears both SRCCx and the corresponding SRCSx
Reserved
8.2.3.11 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6) followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight
SYSCLK1/6 cycle window — the pulse blocking window. To generate back-to-back pulses, the back-toback writes to the IPCGRH register must be written after the eight SYSCLK1/6 cycle pulse-blocking window has elapsed. The IPC Generation Host Register is shown in
and described in
158
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Figure 8-21. IPC Generation Registers (IPCGRH)
31
SRCS27 - SRCS0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4
Bit Field
31-4 SRCSx
3-1
0
Reserved
IPCG
Table 8-36. IPC Generation Registers Field Descriptions
Description
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
3 1
Reserved
R-000
0
IPCG
RW +0
8.2.3.12 IPC Acknowledgment Host (IPCARH) Register
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the same as for other IPCAR registers. The IPC Acknowledgment Host Register is shown in
and described in
Figure 8-22. Acknowledgment Register (IPCARH)
31
SRCC27 - SRCC0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
4 3
Reserved
R-0000
0
Bit Field
31-4 SRCCx
3-0 Reserved
Table 8-37. IPC Acknowledgment Register Field Descriptions
Description
Reads the return current value of the internal register bit.
Writes:
• 0 = No effect
• 1 = Clears both SRCCx and the corresponding SRCSx
Reserved
8.2.3.13 Timer Input Selection Register (TINPSEL)
The Timer Input Selection Register selects timer inputs and is shown in
and described in
.
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Figure 8-23. Timer Input Selection Register (TINPSEL)
31
TINPHSEL15
RW-0
23
TINPHSEL11
RW-0
30
TINPLSEL15
RW-0
22
TINPLSEL11
RW-0
29
TINPHSEL14
RW-0
21
TINPHSEL10
RW-0
28
TINPLSEL14
RW-0
20
TINPLSEL10
RW-0
15
Reserved
R-0
LEGEND: R = Read only; RW = Read/Write; -n = value after reset
27
TINPHSEL13
RW-0
19
TINPHSEL9
RW-0
26
TINPLSEL13
RW-0
18
TINPLSEL9
RW-0
25
TINPHSEL12
RW-0
17
TINPHSEL8
RW-0
Table 8-38. Timer Input Selection Field Description
Bit Field Description
31 TINPHSEL15 Input select for TIMER15 high.
• 0 = TIMI0
• 1 = TIMI1
30 TINPLSEL15 Input select for TIMER15 low.
• 0 = TIMI0
• 1 = TIMI1
29 TINPHSEL14 Input select for TIMER14 high.
• 0 = TIMI0
• 1 = TIMI1
28 TINPLSE14 Input select for TIMER14 low.
• 0 = TIMI0
• 1 = TIMI1
27 TINPHSEL13 Input select for TIMER13 high.
• 0 = TIMI0
• 1 = TIMI1
26 TINPLSEL13 Input select for TIMER13 low.
• 0 = TIMI0
• 1 = TIMI1
25 TINPHSEL12 Input select for TIMER12 high.
• 0 = TIMI0
• 1 = TIMI1
24 TINPLSEL12 Input select for TIMER12low.
• 0 = TIMI0
• 1 = TIMI1
23 TINPHSEL11 Input select for TIMER11 high.
• 0 = TIMI0
• 1 = TIMI1
22 TINPLSEL11 Input select for TIMER11 low.
• 0 = TIMI0
• 1 = TIMI1
21 TINPHSEL10 Input select for TIMER10 high.
• 0 = TIMI0
• 1 = TIMI1
20 TINPLSEL10 Input select for TIMER10 low.
• 0 = TIMI0
• 1 = TIMI1
24
TINPLSEL12
RW-0
16
TINPLSEL8
RW-0
0
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Table 8-38. Timer Input Selection Field Description (continued)
Bit Field Description
19 TINPHSEL9 Input select for TIMER9 high.
• 0 = TIMI0
• 1 = TIMI1
18 TINPLSEL9 Input select for TIMER9 low.
• 0 = TIMI0
• 1 = TIMI1
17 TINPHSEL8 Input select for TIMER8 high.
• 0 = TIMI0
• 1 = TIMI1
16 TINPLSEL8 Input select for TIMER8 low.
• 0 = TIMI0
• 1 = TIMI1
15-0 Reserved
8.2.3.14 Timer Output Selection Register (TOUTPSEL)
The control register TOUTSEL handles the timer output selection and is shown in
and described in
Figure 8-24. Timer Output Selection Register (TOUTPSEL)
5 4 31
Reserved
R-0000000000000000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
10 9
TOUTPSEL1
RW-00001
TOUTPSEL0
RW-00000
0
Bit Field
31-10 Reserved
9-5 TOUTPSEL1
Table 8-39. Timer Output Selection Field Description
Description
Reserved
Output select for TIMO1
• 00000: Reserved
• 00001: Reserved
• 00010: Reserved
• 00011: Reserved
• 00100: Reserved
• 00101: Reserved
• 00110: Reserved
• 00111: Reserved
• 01000: Reserved
• 01001: Reserved
• 01010: Reserved
• 01011: Reserved
• 01100: Reserved
• 01101: Reserved
• 01110: Reserved
• 01111: Reserved
• 10000: TOUTL8
• 10001: TOUTH8
• 10010: TOUTL9
• 10011: TOUTH9
• 10100: TOUTL10
• 10101: TOUTH10
• 10110: TOUTL11
• 10111: TOUTH11
• 11000: TOUTL12
• 11001: TOUTH12
• 11010: TOUTL13
• 11011: TOUTH13
• 11100: TOUTL14
• 11101: TOUTH14
• 11110: TOUTL15
• 11111: TOUTH15
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Bit
4-0
Field
TOUTPSEL0
Table 8-39. Timer Output Selection Field Description (continued)
Description
Output select for TIMO0
• 00000: Reserved
• 00001: Reserved
• 00010: Reserved
• 00011: Reserved
• 00100: Reserved
• 00101: Reserved
• 00110: Reserved
• 00111: Reserved
• 01000: Reserved
• 01001: Reserved
• 01010: Reserved
• 01011: Reserved
• 01100: Reserved
• 01101: Reserved
• 01110: Reserved
• 01111: Reserved
• 10000: TOUTL8
• 10001: TOUTH8
• 10010: TOUTL9
• 10011: TOUTH9
• 10100: TOUTL10
• 10101: TOUTH10
• 10110: TOUTL11
• 10111: TOUTH11
• 11000: TOUTL12
• 11001: TOUTH12
• 11010: TOUTL13
• 11011: TOUTH13
• 11100: TOUTL14
• 11101: TOUTH14
• 11110: TOUTL15
• 11111: TOUTH15
8.2.3.15 Reset Mux (RSTMUXx) Register
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX8-RSTMUX11 for the ARM CorePac (AM5K2E04) or RSTMUX8_RSTMUX9 for the ARM CorePac (AM5K2E02) on the device. These registers are located in Bootcfg memory space. The Reset Mux Register is shown in
and
below.
Figure 8-25. Reset Mux Register
31
Reserved
10
R-0000 0000 0000 0000 0000 00
9
EVTSTATCLR
RC-0
8
Reserved
R-0
7
DELAY
RW-100
5 4
EVTSTAT
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
3
OMODE
RW-000
1 0
LOCK
RW-0
8
7-5
4
Reserved
DELAY
EVTSTAT
Table 8-40. Reset Mux Register 8..11(RSTMUX8-RSTMUX11) Field Descriptions
Bit Field
31-10 Reserved
9 EVTSTATCLR
Description
Reserved
Clear event status
• 0 = Writing 0 has no effect
• 1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
Delay cycles between interrupt and device reset
• 000b = 256 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
• 001b = 512 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
• 010b = 1024 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
• 011b = 2048 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
• 100b = 4096 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b (default)
• 101b = 8192 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
• 110b = 16384 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
• 111b = 32768 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
Event status
• 0 = No event received (Default)
• 1 = WD timer event received by Reset Mux block
162
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Bit
3-1
0
Table 8-40. Reset Mux Register 8..11(RSTMUX8-RSTMUX11) Field Descriptions (continued)
Field
OMODE
LOCK
Description
Timer event operation mode
• 000b = WD timer event input to the Reset Mux block does not cause any output event (default)
• 001b = Reserved
• 010b = Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic generates reset to PLL Controller.
• 011b = WD Timer Event input to the Reset Mux block causes Local Reset output event of the RSTMUX logic to generate reset to PLL Controller.
• 100b = WD Timer Event input to the Reset Mux block causes an interrupt to be sent to the GIC.
• 101b = WD timer event input to the Reset Mux block causes device reset to AM5K2E0x. Note that for
Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to generate reset to PLL Controller.
• 110b = Reserved
• 111b = Reserved
Lock register fields
• 0 = Register fields are not locked (default)
• 1 = Register fields are locked until the next timer reset
8.2.3.16 Device Speed (DEVSPEED) Register
The Device Speed Register shows the device speed grade and is shown below.
Figure 8-26. Device Speed Register (DEVSPEED)
16 15 12 31 28 27
Reserved
Legend: R = Read only; -n = value after reset
DEVSPEED
R-n
Reserved
11
Table 8-41. Device Speed Register Field Descriptions
Bit Field
31-28 Reserved
Description
Reserved. Read only
27-16 DEVSPEED Indicates the speed of the device (read only)
• 0b0000 0000 0000 = 800 MHz
• 0b0000 0000 0001 = 1000 MHz
• 0b0000 0000 001x = 1200 MHz
• 0b0000 0000 01xx = 1350 MHz
• 0b0000 0000 1xxx = 1400 MHz
• 0b0000 0001 xxxx = 1500 MHz
• 0b0000 001x xxxx = 1400 MHz
• 0b0000 01xx xxxx = 1350.8 MHz
• 0b0000 1xxx xxxx = 1200 MHz
• 0b0001 xxxx xxxx= 1000 MHz
• 0b001x xxxx xxxx = 800 MHz
15-12 Reserved Reserved. Read only
ARMSPEED
R-n
0
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Table 8-41. Device Speed Register Field Descriptions (continued)
Bit Field Description
11-0 ARMSPEED Indicates the speed of the ARM (read only)
• 0b0000 0000 0000 = 800 MHz
• 0b0000 0000 0001 = 1000 MHz
• 0b0000 0000 001x = 1200 MHz
• 0b0000 0000 01xx = 1350 MHz
• 0b0000 0000 1xxx = 1400 MHz
• 0b0000 0001 xxxx = 1500 MHz
• 0b0000 001x xxxx = 1400 MHz
• 0b0000 01xx xxxx = 1350.8 MHz
• 0b0000 1xxx xxxx = 1200 MHz
• 0b0001 xxxx xxxx= 1000 MHz
• 0b001x xxxx xxxx = 800 MHz
8.2.3.17 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
The registers defined in ARM Configuration Register 0 (ARMENDIAN_CFGr_0) and ARM Configuration
Register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral
MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is shown.)
Figure 8-27. ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
8 7 31
BASEADDR
RW
Legend: RW = Read/Write; R = Read only
Reserved
R-0000 0000
0
Bit Field
31-8 BASEADDR
7-0 Reserved
Table 8-42. ARM Endian Configuration Register 0
Default Values
ARM ENDIAN CONFIGURATION REGISTER 0
ARMENDIAN_CFG0_0
ARMENDIAN_CFG1_0
ARMENDIAN_CFG2_0
ARMENDIAN_CFG3_0
ARMENDIAN_CFG4_0
ARMENDIAN_CFG5_0
ARMENDIAN_CFG6_0
ARMENDIAN_CFG7_0
DEFAULT
VALUES
0x0001C000
0x00020000
0x000BC000
0x00210000
0x00023A00
0x00240000
0x01000000
0xFFFFFF00
Table 8-43. ARM Endian Configuration Register 0 Field Descriptions
Description
24-bit Base Address of Configuration Region R
This base address defines the start of a contiguous block of Memory Mapped Register space for which a word swap is done by the ARM CorePac bridge.
Reserved
164
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8.2.3.18 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
Figure 8-28. ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
4 3 31
Reserved
R-0000 0000 0000 0000 0000 0000 0000
Legend: RW = Read/Write; R = Read only
SIZE
RW
0
Bit Field
31-4 Reserved
3-0 SIZE
Table 8-44. ARM Endian Configuration Register 1
Default Values
ARM ENDIAN CONFIGURATION REGISTER 1
ARMENDIAN_CFG0_1
ARMENDIAN_CFG1_1
ARMENDIAN_CFG2_1
ARMENDIAN_CFG3_1
ARMENDIAN_CFG4_1
ARMENDIAN_CFG5_1
ARMENDIAN_CFG6_1
ARMENDIAN_CFG7_1
DEFAULT
VALUES
0x00000006
0x00000009
0x00000004
0x00000008
0x00000005
0x00000006
0x00000000
0x00000000
Table 8-45. ARM Endian Configuration Register 1 Field Descriptions
Description
Reserved
4-bit encoded size of Configuration Region R
The value in the SIZE field defines the size of the contiguous block of Memory Mapped Register space for which a word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR).
• 0000 : 64KB
• 0001 : 128KB
• 0010 : 256KB
• 0011 : 512KB
• 0100 : 1MB
• 0101 : 2MB
• 0110 : 4MB
• 0111 : 8MB
• 1000 : 16MB
• 1001 : 32MB
• 1010 : 64MB
• 1011 : 128MB
• Others : Reserved
8.2.3.19 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
The registers defined in ARM Configuration Register 2 (ARMENDIAN_CFGr_2) enable the word swapping of a region.
31
Figure 8-29. ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
1
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
0
DIS
RW-0
Legend: RW = Read/Write
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Bit Field
31-1 Reserved
0 DIS
Table 8-46. ARM Endian Configuration Register 2
Default Values
ARM ENDIAN CONFIGURATION REGISTER 2
ARMENDIAN_CFG0_2
ARMENDIAN_CFG1_2
ARMENDIAN_CFG2_2
ARMENDIAN_CFG3_2
ARMENDIAN_CFG4_2
ARMENDIAN_CFG5_2
ARMENDIAN_CFG6_2
ARMENDIAN_CFG7_2
DEFAULT
VALUES
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
Table 8-47. ARM Endian Configuration Register 2 Field Descriptions
Description
Reserved
Disabling the word swap of a region
• 0 : Enable word swap for region
• 1 : Disable word swap for region
8.2.3.20 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
Figure 8-30. Chip Miscellaneous Control Register (CHIP_MISC_CTL0)
31
Reserved
R-0
17 13
Reserved
RW -0
Legend: R = Read only; W = Write only; -n = value after reset
19
12
MSMC_BLOCK_PARITY_RST
RW-0
USB_PME_EN
RW-0
11 3
Reserved
RW-0
18
2
QM_PRIORITY
RW-0
0
Table 8-48. Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions
Bit
31-19
18
Field
Reserved
USB_PME_EN
Description
Reserved.
Enables wakeup event generation from USB
• 0 = Disable PME event generation
• 1 = Enable PME event generation
17-13 Reserved
12 MSMC_BLOCK_PARITY_RST Controls MSMC parity RAM reset. When set to ‘1’ means the MSMC parity RAM will not be reset.
11-3 Reserved
2-0 QM_PRIORITY
Reserved
Control the priority level for the transactions from QM Master port, which access the external linking RAM.
8.2.3.21 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
Figure 8-31. Chip Miscellaneous Control Register (CHIP_MISC_CTL1)
13 31
Reserved
R- 0000 0000 00000000
15
Legend: R = Read only; RW = Read/Write; -n = value after reset
14
IO_TRACE_SEL
RW-0
Reserved
RW-0
0
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Table 8-49. Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions
Bit Field
31-15 Reserved
14 IO_TRACE_SEL
Description
Reserved.
This bit controls the pin muxing of GPIO[31:17] and EMU[33:19] pin
• 0 = GPIO[31:17] is selected
• 1 = EMU[33:19] pins is selected
13-0 Reserved
8.2.3.22 System Endian Status Register (SYSENDSTAT)
This register provides a way for reading the system endianness in an endian-neutral way. A zero value indicates big endian and a non-zero value indicates little endian. The SYSENDSTAT register captures the
LENDIAN bootmode pin and is used by the BOOTROM to guide the bootflow. The value is latched on the rising edge of POR or RESETFULL .
Figure 8-32. System Endian Status Register
31
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
1 0
SYSENDSTAT
R-0
Bit Field
31-1 Reserved
0 SYSENDSTAT
Table 8-50. System Endian Status Register Descriptions
Description
Reserved
Reflects the same value as the LENDIAN bit in the DEVSTAT register.
• 0 - SoC is in Big Endian
• 1 - SoC is in Little Endian
8.2.3.23 SYNECLK_PINCTL Register
This register controls the routing of recovered clock signals from any Ethernet port (SGMII/XFI of the multiport switches) to the clock output TSRXCLKOUT0/TSRXCLKOUT1.
31
Reserved
R-0000 0000 0000 0000 0000 0000 0
Legend: RW = Read/Write; - n = value after reset
Figure 8-33. SYNECLK_PINCTL Register
7 6
TSRXCLKOUT1SEL
4
RW-0
3
Reserved
2
TSRXCLKOUT0SEL
0
RW-0
Table 8-51. SYNECLK_PINCTL Register Descriptions
Bit Field Description
31-7 Reserved
6-4 TSRXCLKOUT1SEL •
Reserved
000 - SGMII Lane 0 rxbclk
• 001 - SGMII Lane 1 rxbclk
• 010 - SGMII Lane 2 rxbclk
• 011 - SGMII Lane 3 rxbclk
• 100 - XFI Lane 0 rxbclk
• 101 - XFI Lane 1 rxbclk
• 110 - XFI Lane 2 rxbclk
• 111 - XFI Lane 3 rxbclk
3 Reserved Reserved
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Bit
2-0
Table 8-51. SYNECLK_PINCTL Register Descriptions (continued)
Field Description
TSRXCLKOUT0SEL •
000 - SGMII Lane 0 rxbclk
• 001 - SGMII Lane 1 rxbclk
• 010 - SGMII Lane 2 rxbclk
• 011 - SGMII Lane 3 rxbclk
• 100 - XFI Lane 0 rxbclk
• 101 - XFI Lane 1 rxbclk
• 110 - XFI Lane 2 rxbclk
• 111 - XFI Lane 3 rxbclk
8.2.3.24 USB PHY Control (USB_PHY_CTLx) Registers
The following registers control the USB PHY.
Figure 8-34. USB_PHY_CTL0 Register
31
10
PHY_RTUNE_REQ
9
Reserved
Reserved
8
R-0
7 6
12 11
PHY_RTUNE_ACK
R-0
5
PHY_TC_VATESTENB PHY_TC_TEST_POWERDOWN PHY_TC_TEST_POWERDOWN
_SSP _HSP
R/W-00 R/W-0 R/W-0 R/W-0
4
PHY_TC_LOOPBACKENB
R-0
3
Reserved
2
UTMI_VBAUSVLDEXT
R/W-0 R-0
Legend: R = Read only; W = Write only; -n = value after reset
R/W-0
1
UTMI_TXBITSTUFFENH
R/W-0
0
UTMI_TXBITSTUFFEN
R/W-0
Table 8-52. USB_PHY_CTL0 Register Field Descriptions
Bit
10
9
8-7
6
5
Field
31-12 Reserved
11 PHY_RTUNE_ACK
Description
Reserved
The PHY uses an external resistor to calibrate the termination impedances of the PHY's highspeed inputs and outputs.
The resistor is shared between the USB2.0 high-speed outputs and the Super-speed I/O. Each time the PHY is taken out of a reset, a termination calibration is performed. For SS link, the calibration can also be requested externally by asserting the PHY_RTUNE_REQ. When the calibration is complete, the PHY_RTUNE_ACK transitions low.
PHY_RTUNE_REQ
Reserved
PHY_TC_VATESTENB
A resistor calibration on the SS link cannot be performed while the link is operational
See PHY_RTUNE_ACK.
Reserved
Analog Test Pin Select.
Enables analog test voltages to be placed on the ID pin.
• 11 = Invalid setting.
• 10 = Invalid setting.
• 01 = Analog test voltages can be viewed or applied on ID.
• 00 = Analog test voltages cannot be viewed or applied on ID.
PHY_TC_TEST_POWERDOWN SS Function Circuits Power-Down Control.
_SSP
Powers down all SS function circuitry in the PHY for IDDQ testing.
PHY_TC_TEST_POWERDOWN HS Function Circuits Power-Down Control
_HSP
Powers down all HS function circuitry in the PHY for IDDQ testing.
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3
2
Bit
4
1
0
Table 8-52. USB_PHY_CTL0 Register Field Descriptions (continued)
Field
PHY_TC_LOOPBACKENB
Description
Loop-back Test Enable
Places the USB3.0 PHY in HS Loop-back mode, which concurrently enables the HS receive and transmit logic.
• 1 = During HS data transmission, the HS receive logic is enabled.
• 0 = During HS data transmission, the HS receive logic is disabled.
Reserved
UTMI_VBAUSVLDEXT
• Reserved
External VBUS Valid Indicator
UTMI_TXBITSTUFFENH
UTMI_TXBITSTUFFEN
Function: Valid in Device mode and only when the VBUSVLDEXTSEL signal is set to 1'b1.
VBUSVLDEXT indicates whether the VBUS signal on the USB cable is valid. In addition,
VBUSVLDEXT enables the pull-up resistor on the D+ line.
• 1 = VBUS signal is valid, and the pull-up resistor on D+ is enabled.
• 0 = VBUS signal is not valid, and the pull-up resistor on D+ is disabled.
High-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAINH[7:0] when OPMODE[1:0]=11b.
• 1 = Bit stuffing is enabled.
• 0 = Bit stuffing is disabled.
Low-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAIN[7:0] when OPMODE[1:0]=11b.
• 1 = Bit stuffing is enabled.
• 0 = Bit stuffing is disabled.
Figure 8-35. USB_PHY_CTL1 Register
31
4
PIPE_TX2RX_LOOPBK
R/W-0
Reserved
R-0
3 2
PIPE_EXT_PCLK_REQ PIPE_ALT_CLK_SEL
R/W-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
R/W-0
6
1
PIPE_ALT_CLK_REQ
R-0
5
PIPE_REF_CLKREQ_N
R-0
0
PIPE_ALT_CLK_EN
R/W-0
Bit
31-6
5
4
3
2
Field
Reserved
PIPE_REF_CLKREQ_N
PIPE_TX2RX_LOOPBK
Table 8-53. USB_PHY_CTL1 Register Field Descriptions
Description
Reserved
Reference Clock Removal Acknowledge.
When the pipeP_power-down control into the PHY turns off the MPLL in the P3 state,
PIPE_REF_CLKREQ_N is asserted after the PLL is stable and the reference clock can be removed.
Loop-back.
PIPE_EXT_PCLK_REQ
PIPE_ALT_CLK_SEL
When this signal is asserted, data from the transmit predriver is looped back to the receiver slicers. LOS is bypassed and based on the tx_en input so that rx_los=!tx_data_en.
External PIPE Clock Enable Request.
When asserted, this signal enables the pipeP_pclk output regardless of power state (along with the associated increase in power consumption).
Alternate Clock Source Select.
Selects the alternate clock sources instead of the internal MPLL outputs for the PCS clocks.
• 1 = Uses alternate clocks.
• 0 = Users internal MPLL clocks.
Change only during a reset.
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Bit
1
0
Table 8-53. USB_PHY_CTL1 Register Field Descriptions (continued)
Field
PIPE_ALT_CLK_REQ
PIPE_ALT_CLK_EN
Description
Alternate Clock Source Request.
Indicates that the alternate clocks are needed by the slave PCS (that is, to boot the master
MPLL). Connect to the alt_clk_en on the master.
Alternate Clock Enable.
Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary, powers up the MPLL).
Figure 8-36. USB_PHY_CTL2 Register
31
20
13
Reserved
R-0
PHY_PC_TXRESTUNE
R/W-01
PHY_PC_TXFSLSTUNE
30
10
29
19
9
PHY_PC_LOS_BIAS
R/W-101
18
PHY_PC_
TXPREEMPPULSETUNE
R/W-0
PHY_PC_SQRXTUNE
27
7
26
PHY_PC_TXVREFTUNE
R/W-1000
17
23 22
16
PHY_PC_TXPREEMPAMPTUNE
4
R/W-00
6
PHY_PC_OTGTUNE
3
Reserved
PHY_PC_TXRISETUNE
15
2
R/W-01
PHY_PC_
TXHSXVTUNE
R/W-11
PHY_PC_
COMPDISTUNE
21
14
0
R/W-0011 R/W-011
Legend: R = Read only; R/W = Read/Write, -n = value after reset
R/W-100 R-0 R/W-100
Bit Field
31-30 Reserved
29-27 PHY_PC_LOS_BIAS
26-23 PHY_PC_TXVREFTUNE
22-21 PHY_PC_TXRISETUNE
Table 8-54. USB_PHY_CTL2 Register Field Descriptions
Description
Reserved
Loss-of-Signal Detector Threshold Level Control.
Sets the LOS detection threshold level.
• +1 = results in a +15 mVp incremental change in the LOS threshold.
• -1 = results in a -15 mVp incremental change in the LOS threshold.
Note: the 000b setting is reserved and must not be used.
HS DC Voltage Level Adjustment.
Adjusts the high-speed DC level voltage.
• +1 = results in a +1.25% incremental change in high-speed DC voltage level.
• -1 = results in a -1.25% incremental change in high-speed DC voltage level.
HS Transmitter Rise/Fall TIme Adjustment.
20-19 PHY_PC_TXRESTUNE
18 PHY_PC_
TXPREEMPPULSETUNE
Adjusts the rise/fall times of the high-speed waveform.
• +1 = results in a -4% incremental change in the HS rise/fall time.
• -1 = results in a +4% incremental change in the HS rise/fall time.
USB Source Impedance Adjustment.
Some applications require additional devices to be added on the USB, such as a series switch, which can add significant series resistance. This bus adjusts the driver source impedance to compensate for added series resistance on the USB.
HS Transmitter Pre-Emphasis Duration Control.
Controls the duration for which the HS pre-emphasis current is sourced onto DP or DM. It is defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and is defined as 1x pre-emphasis duration.
This signal valid only if either txpreempamptune[1] or txpreempamptune[0] is set to 1.
• 1 = 1x, short pre-emphasis current duration.
• 0 = 2x, long pre-emphasis current duration.
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Table 8-54. USB_PHY_CTL2 Register Field Descriptions (continued)
Bit Field Description
17-16 PHY_PC_TXPREEMPAMPTUNE HS Transmitter Pre-Emphasis Current Control.
Controls the amount of current sourced to DP and DM after a J-to-K or K-to-J transition.
15-14 PHY_PC_TXHSXVTUNE
13-10 PHY_PC_TXFSLSTUNE
9-7
6-4
3
2-0
PHY_PC_SQRXTUNE
PHY_PC_OTGTUNE
Reserved
PHY_PC_COMPDISTUNE
The HS Transmitter pre-emphasis current is defined in terms of unit amounts. One unit amount is approximately 600 µ;A and is defined as 1x pre-emphasis current.
• 11 = 3x pre-emphasis current.
• 10 = 2x pre-emphasis current.
• 01 = 1x pre-emphasis current.
• 00 = HS Transmitter pre-emphasis is disabled.
Transmitter High-Speed Crossover Adjustment.
Adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode.
• 11 = Default setting.
• 10 = +15 mV
• 01 = -15 mV
• 00 = Reserved
FS/LS Source Impedance Adjustment.
Adjusts the low- and full-speed single-ended source impedance while driving high.
This parameter control is encoded in thermometer code.
• +1 = results in a -2.5% incremental change in threshold voltage level.
• -1 = results in a +2.5% incremental change in threshold voltage level.
Any non-thermometer code setting (that is 1001) is not supported and reserved.
Squelch Threshold Adjustment.
Adjusts the voltage level for the threshold used to detect valid high-speed data.
• +1 = results in a -5% incremental change in threshold voltage level.
• -1 = results in a +5% incremental change in threshold voltage level.
VBUS Valid Threshold Adjustment.
Adjusts the voltage level for the VBUS valid threshold.
• +1 = results in a +1.5% incremental change in threshold voltage level.
• -1 = results in a -1.5% incremental change in threshold voltage level.
Reserved
Disconnect Threshold Adjustment.
Adjusts the voltage level for the threshold used to detect a disconnect event at the host.
• +1 = results in a +1.5% incremental change in the threshold voltage level.
• -1 = results in a -1.5% incremental change in the threshold voltage level.
Figure 8-37. USB_PHY_CTL3 Register
31 30
22 17
PHY_PC_PCS_TX_DEEMPH_6DB
Reserved
R-0
16 11
Reserved
R/W-100000 R-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
10 5
PHY_PC_PCS_TX_DEEMPH_3P5DB
R/W-010101
29
PHY_PC_PCS_TX_SWING_FULL
23
R/W-1111000
4
PHY_PC_LOS_LEVEL
R/W-01001
0
Table 8-55. USB_PHY_CTL3 Register Field Descriptions
Bit Field
31-30 Reserved
29-23 PHY_PC_PCS_TX_SWING_
FULL
Description
Reserved
Tx Amplitude (Full Swing Mode).
Sets the launch amplitude of the transmitter. It can be used to tune Rx eye for compliance.
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Table 8-55. USB_PHY_CTL3 Register Field Descriptions (continued)
Bit Field Description
22-17 PHY_PC_PCS_TX_DEEMPH_ Tx De-Emphasis at 6 dB.
6DB
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch amplitude.
16-11 Reserved
10-5 PHY_PC_PCS_TX_DEEMPH_
3P5DB
Reserved
Tx De-Emphasis at 3.5 dB.
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3 specification). Can be used for Rx eye compliance.
4-0 PHY_PC_LOS_LEVEL Loss-of-Signal Detector Sensitivity Level Control.
Sets the LOS detection threshold level. This signal must be set to 0x9.
Figure 8-38. USB_PHY_CTL4 Register
27
31
PHY_SSC_EN
R/W-1
PHY_FSEL
R/W-100111
16
R/W-0
22
PHY_OTG_VBUSVLDEXTSEL
30
PHY_REF_USE_PAD
21
R/W-0
PHY_RETENABLEN
R/W-1 R/W-10
29
PHY_REF_SSP_EN
20
R/W-0
19
PHY_REFCLKSEL
18
PHY_MPLL_REFSSC_CLK_EN
PHY_COMMONONN
R/W-0
28
R/W-0
17
Reserved
15
PHY_OTG_
OTGDISABLE
R/W-1
14 12 11 7
PHY_PC_TX_VBOOST PHY_PC_LANE0_TX_TERM_
_LVL OFFSET
R/W-100 R/W-00000
Legend: R = Read only; R/W = Read/Write, -n = value after reset
R-0
6 0
Reserved
R-0
Table 8-56. USB_PHY_CTL4 Register Field Descriptions
Bit
31
30
Field
PHY_SSC_EN
PHY_REF_USE_PAD
Description
Spread Spectrum Enable.
Enables spread spectrum clock production (0.5% down-spread at ~31.5 KHz) in the USB3.0
PHY. If the reference clock already has spread spectrum applied, ssc_en must be de-asserted.
Select Reference Clock Connected to ref_pad_clk_{p,m}.
When asserted, selects the external ref_pad_clk_{p,m} inputs as the reference clock source.
When de-asserted, ref_alt_clk_{p,m} are selected for an on-chip reference clock source.
Reference Clock Enables for SS function.
29 PHY_REF_SSP_EN
28
27-22
Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de asserted until the reference clock is running at the appropriate frequency, at which point ref_ssp_en can be asserted. For lower power states, ref_ssp_en can also be de asserted.
PHY_MPLL_REFSSC_CLK_EN Double-Word Clock Enable.
PHY_FSEL
Enables/disables the mpll_refssc_clk signal. To prevent clock glitch, it must be changed when the PHY is inactive.
Frequency Selection.
21 PHY_RETENABLEN
Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals will determine the clock frequency used for
SS and HS operations and if a shared or separate reference clock will be used.
Lowered Digital Supply Indicator.
Indicates that the vp digital power supply has been lowered in Suspend mode. This signal must be de-asserted before the digital power supply is lowered.
• 1 = Normal operating mode.
• 0 = The analog blocks are powered down.
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Table 8-56. USB_PHY_CTL4 Register Field Descriptions (continued)
Bit
20-19
18
17
16
Field
PHY_REFCLKSEL
Description
Reference Clock Select for PLL Block.
Selects reference clock source for the HS PLL block.
• 11 = HS PLL uses EXTREFCLK as reference.
• 10 = HS PLL uses either ref_pad_clk_{p,m} or ref_alt_clk_{p,m} as reference.
• x0 = Reserved.
Common Block Power-Down Control.
PHY_COMMONONN
Controls the power-down signals in the HS Bias and PLL blocks when the USB3.0 PHY is in
Suspend or Sleep mode.
• 1 = In Suspend or Sleep mode, the HS Bias and PLL blocks are powered down.
• 0 = In Suspend or Sleep mode, the HS Bias and PLL blocks remain powered and continue to draw current.
Reserved Reserved
PHY_OTG_VBUSVLDEXTSEL External VBUS Valid Select.
15
14-12
PHY_OTG_OTGDISABLE
PHY_PC_TX_VBOOST_LVL
Selects the VBUSVLDEXT input or the internal Session Valid comparator to indicate when the
VBUS signal on the USB cable is valid.
• 1 = VBUSVLDEXT input is used.
• 0 = Internal Session Valid comparator is used.
OTG Block Disable.
Powers down the OTG block, which disables the VBUS Valid and Session End comparators.
The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP in Device mode) is always on irrespective of the state of otgdisable. If the application does not use the OTG function, setting this signal to high to save power.
• 1 = OTG block is powered down.
• 0 = OTG block is powered up.
Tx Voltage Boost Level.
11-7
6-0
PHY_PC_LANE0_TX_TERM_
OFFSET
Reserved
Sets the boosted transmit launch amplitude (mV ppd
).
The default setting is intended to set the launch amplitude to approximately 1,008mV ppd
.
• +1 = results in a +156 mV ppd change in the Tx launch amplitude.
• -1 = results in a -156 mV ppd change in the Tx launch amplitude.
Transmitter Termination Offset.
Enables adjusting the transmitter termination value from the default value of 60 Ω.
Reserved
Figure 8-39. USB_PHY_CTL5 Register
19 31
12
Reserved
R-0
PHY_SSC_REF_CLK_SEL
R/W-000000000
21
4
20
PHY_REF_CLKDIV2
R/W-0
3
Reserved
R-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
PHY_MPLL_MULTIPLIER[6:0]
R/W +0011001
2
PHY_SSC_RANGE
R/W-000
13
0
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Bit Field
31-21 Reserved
20 PHY_REF_CLKDIV2
12-4
3
2-0
PHY_SSC_REF_CLK_SEL
Reserved
PHY_SSC_RANGE
Table 8-57. USB_PHY_CTL5 Register Field Descriptions
19-13 PHY_MPLL_MULTIPLIER[6:0]
Description
Reserved
Input Reference Clock Divider Control.
If the input reference clock frequency is greater than 100 MHz, this signal must be asserted.
The reference clock frequency is then divided by 2 to keep it in the range required by the
MPLL.
When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference clock frequency divided by 4.
MPLL Frequency Multiplier Control.
Multiplies the reference clock to a frequency suitable for intended operating speed.
Spread Spectrum Reference Clock Shifting.
Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient.
• . ssc_ref_clk_sel[8:6] = modulous - 1
• . ssc_ref_clk_sel[5:0] = 2's complement push amount.
Reserved
Spread Spectrum Clock Range.
Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator.
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9 Device Operating Conditions
9.1
Absolute Maximum Ratings
(1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
Supply voltage range
(2)
:
CVDD
CVDD1
DVDD15
DVDD18
DDR3VREFSSTL
VDDAHV
VDDALV
USB0DVDD33, USB0DVDD33
VDDUSB0, VDDUSB1
USB0VP, USB1VP
USB0VPH, USB1VPH
USB0VPTX, USB1VPTX
AVDDA1, AVDDA2, AVDDA3
AVDDA6, AVDDA7
-0.3 V to 1.3 V
-0.3 V to 1.3 V
-0.3 V to 1.98 V
-0.3 V to 2.45 V
0.49 × DVDD15 to 0.51 × DVDD15
-0.3 V to 1.98 V
-0.3 V to 0.935 V
-0.3V to 3.63 V
-0.3V to 0.935 V
-0.3V to 0.935 V
-0.3V to 3.63 V
-0.3V to 0.935 V
-0.3 V to 1.98 V
-0.3 V to 1.98 V
Input voltage (V
I
) range
(3)
:
AVDDA8, AVDDA9, AVDDA10
VSS Ground
LVCMOS (1.8 V)
DDR3
I
2
C
LVDS
LJCB
SerDes
LVCMOS (1.8 V)
0 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.98 V
-0.3 V to 2.45 V
-0.3 V to DVDD18+0.3 V
Output voltage (V
O
) range
Operating case temperature range, T
ESD stress voltage, V
ESD
(3)
(4)
:
C
:
DDR3
I
2
C
SerDes
Commercial
Extended
HBM (human body model)
(5)
CDM (charged device model)
(6)
-0.3 V to 1.3 V
-0.3 V to VDDAHV1+0.3 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.98 V
-0.3 V to 2.45 V
-0.3 V to VDDAHV+0.3 V
0°C to 85°C
-40°C to 100°C
±1000 V
±250 V
Overshoot/undershoot
(7)
LVCMOS (1.8 V)
DDR3
I
2
C
20% overshoot/undershoot for 20% of signal duty cycle
Storage temperature range, T stg
: -65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to V
SS
.
(3) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
(4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(5) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
(6) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
(7) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be V
SS
- 0.20 × DVDD18
Device Operating Conditions
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9.2
Recommended Operating Conditions
(1) (2)
CVDD SR core supply
Initial
(3)
1250MHz and
1400MHz Device
MIN
1.0
SRVnom*0.95
(4)
NOM
1.05
SRVnom
MAX
1.10
SRVnom*1.05
UNIT
V
V
CVDD1
DVDD18
DVDD15
Core supply
1.8-V supply I/O voltage
DDR3 I/O voltage
DDR3VREFSSTL DDR3 reference voltage
VDDAHV
VDDALH
AVDDx
(5)
SerDes regulator supply
SerDes termination supply
PLL analog, DDR DLL supply
USB0VP, USB1VP 0.85-V USB PHY supply
3.3-V USB USB0VPH,
USB1VPH
USB0VPTX,
USB1VPTX
VDDUSB0,
VDDUSB1
USBPHY Transmit supply
USB PHY supply
USB0DVDD33,
USB1DVDD33
V
SS
USB 3.3-V high supply
Ground
DDR3
DDR3L @ 1.5 V
DDR3L @ 1.35 V
0.95
1.71
1.425
1.425
1.283
0.49 × DVDD15
1.71
0.807
1.71
0.807
3.135
0.807
0.807
3.135
1.0
1.8
1.5
1.5
1.35
0.5 × DVDD15
1.8
0.85
1.8
0.85
3.3
0.85
0.85
3.3
1.05
1.89
1.575
1.575
1.45
0.51 × DVDD15
1.89
0.892
1.89
0.892
3.465
0.892
0.892
3.465
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
(6)
V
IL
(6)
T
C
High-level input voltage
Low-level input voltage
Operating case temperature
LVCMOS (1.8 V)
I
2
C
DDR3 EMIF
LVCMOS (1.8 V)
DDR3 EMIF
I
2
C
Commercial
Extended
0
0.65 × DVDD18
0.7 × DVDD18
VREFSSTL + 0.1
-0.3
0
-40
0 0
0.35 × DVDD18
VREFSSTL - 0.1
0.3 × DVDD18
85
100
(1) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI
Electrical Specification, IEEE 802.3ae-2002.
(2) All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
(3) Users are required to program their board CVDD supply initial value to 1.0 V on the device. The initial CVDD voltage at power-on will be
1.0V nominal and it must transition to VID set value, immediately after being presented on the VCNTL pins. This is required to maintain full power functionality and reliability targets guaranteed by TI.
(4) SRVnom refers to the unique SmartReflex core supply voltage that has a potential range of 0.8 V and 1.1 V which preset from the factory for each individual device. Your device may never be programmed to operate at the upper range but has been designed accordingly should it be determined to be acceptable or necessary. Power supplies intended to support the variable SRV function shall be capable of providing a 0.8V-1.1V dynamic range using a 4- or 6-bit binary input value which as provided by the SOC SmartReflex output.
(5) Where x=1,2,3,4... to indicate all supplies of the same kind.
(6) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
V
V
V
V
V
V
V
°C
°C
176
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9.3
Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
V
OH
(2)
V
OL
(2)
PARAMETER
High-level output voltage
Low-level output voltage
LVCMOS (1.8 V)
DDR3
I
2
C
(3)
LVCMOS (1.8 V)
DDR3
TEST
CONDITIONS
(1)
I
O
= I
OH
I
O
= I
OL
MIN
DVDD18 - 0.45
DVDD15 - 0.4
TYP
(3)
I
I
(4)
Input current [DC]
I
2
C
LVCMOS (1.8 V)
I
2
C
I
O
= 3 mA, pulled up to 1.8 V
No IPD/IPU
Internal pullup
Internal pulldown
0.1 × DVDD18 V < V
I
< 0.9 × DVDD18 V
-10
50
-170
-10
100
-100
I
I
OH
OL
I
OZ
(6)
High-level output current
[DC]
LVCMOS (1.8 V)
DDR3
I
2
C
(5)
LVCMOS (1.8 V)
Low-level output current [DC] DDR3
I
2
C
LVCMOS (1.8 V)
Off-state output current [DC] DDR3
I
2
C
-10
-10
-10
(5)
MAX UNIT
0.45
0.4
0.4
10
170
-50
10
-6
-8
V
V
µA
µA mA
3
10
10
10
6
8 mA
µA
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
(3) I
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
2
C uses open collector IOs and does not have a V
OH
Minimum.
(4) I
I applies to input-only pins and bidirectional pins. For input-only pins, I
I indicates the input leakage current. For bidirectional pins, I
I
(5) I includes input leakage current and off-state (Hi-Z) output leakage current.
2
C uses open collector IOs and does not have a I
OH
Maximum.
(6) I
OZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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9.4
Power Supply to Peripheral I/O Mapping
Table 9-1. Power Supply to Peripheral I/O Mapping
(1) (2)
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
CVDD
VDDALV
VDDAHV
DVDD15
DVDD18
POWER SUPPLY
Supply core AVS voltage
SerDes IO voltage
DDR3 memory I/O voltage
1.8-V supply I/O voltage
I/O BUFFER TYPE
LJCB
SerDes/CML
SerDes/CML
ASSOCIATED PERIPHERAL
CORECLK(P|N) PLL input buffer
DDR3CLK(P|N) PLL input buffer
NETCPCLK(P|N) PLL input buffer
USBCLK(P|M) PLL input buffer
SGMII0CLK(P|N) PLL input buffer
SERDES low voltage
PCIECLK(P|N) SerDes Clock Reference
HYPCLK(P|N) SerDes Clock Reference
XFICLK(P|N) SerDes Clock Reference
(3)
DDR3 (1.5/1.35 V) All DDR3 memory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All TIMER peripheral I/O buffer
LVCMOS (1.8 V)
All SPI peripheral I/O buffer
All TSIP peripheral I/O buffer
All RESETs, control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All Hyperlink sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
Open-drain (1.8 V) All I
2
C peripheral I/O buffer
LVDS TSREFCLK SerDes Clock Reference
(1) Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers.
(2) Please see the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ) for more information about individual peripheral I/O.
(3) 10 GbE supported in AM5K2E04 only.
178
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10 AM5K2E0x Peripheral Information and Electrical Specifications
This chapter covers the various peripherals on the AM5K2E0x device. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.
10.1 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V
IH manner.
and V
IL
(or between V
IL and V
IH
) in a monotonic
10.2 Power Supplies
The following sections describe the proper power-supply sequencing and timing needed to properly power on the AM5K2E0x. The various power supply rails and their primary functions are listed in
NAME
AVDDAx
DVDD15
DVDD18
USB0DVDD33, USB1DVDD33
VDDAHV
VDDALV
VDDUSB0, VDDUSB1
USB0VP, USB0VPTX, USB0VP,
USB0VPTX
VSS
Table 10-1. Power Supply Rails on the AM5K2E0x
PRIMARY FUNCTION
Core PLL, DDR3 DLL supply voltage
DDR3 I/O power supply voltage
1.8-V I/O power supply voltage
USB 3.3-V IO supply
SerDes I/O power supply voltage
SerDes analog power supply voltage
USB LV PHY power supply voltage
Filtered 0.85-V supply voltage
VOLTAGE
1.8 V
1.5/1.35 V
1.8 V
3.3 V
1.8 V
0.85 V
0.85 V
0.85 V
NOTES
Core PLL, DDR3 DLL supply
DDR3 I/O power supply
1.8-V I/O power supply
USB high voltage supply
SerDes I/O power supply
SerDes analog supply
USB LV PHY supply
Filtered 0.85-V USB supply
Ground GND Ground
10.2.1 Power-Up Sequencing
This section defines the requirements for a power-up sequencing from a power-on reset condition. There are two acceptable power sequences for the device.
The first sequence stipulates the core voltages starting before the IO voltages as shown below.
1. CVDD
2. CVDD1, VDDAHV, AVDDAx, DVDD18
3. DVDD15
4. VDDALV, VDDUSBx, USBxVP, USBxVPTX
5. USBxDVDD33
The second sequence provides compatibility with other TI processors with the IO voltage starting before
the core voltages as shown below.
1. VDDAHV, AVDDAx, DVDD18
2. CVDD
3. CVDD1
4. DVDD15
5. VDDALV, VDDUSBx, USBxVP, USBxVPTX
6. USBxDVDD33
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The clock input buffers for CORECLK, DDRCLK, NETCPCLK, and SGMIICLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDD is present.
If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled to ground through a 1-k Ω resistor. The P leg should be tied to CVDD to ensure it will not have any voltage present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before
DVDD18 or DVDD15 are valid could cause damage to the device.
The device initialization is divided into two phases. The first phase consists of the time period from the activation of the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence.
POR must be held low for the entire power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of
RESETFULL triggers the end of the initialization phase, but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock that is used by the CorePacs. See
for more details.
10.2.1.1 Core-Before-IO Power Sequencing
The details of the Core-before-IO power sequencing are defined in
shows power sequencing and reset control of the AM5K2E0x. POR may be removed after the power has been stable for the required 100 µsec. RESETFULL must be held low for a period (see item 9 in
rising edge of POR, but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed.
NOTE
TI recommends a maximum of 80 ms between one power rail being valid and the next power rail in the sequence starting to ramp.
ITEM
1
2a
Table 10-2. Core-Before-IO Power Sequencing
SYSTEM STATE
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR) is put into the reset state.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• CVDD1 (core constant) ramps at the same time or within 80 ms of CVDD. Although ramping CVDD1 simultaneously with
CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• The timing for CVDD1 is based on CVDD valid. CVDD1 and DVDD18/ADDAVH/AVDDAx may be enabled at the same time but do not need to ramp simultaneously. CVDD1 may be valid before or after DVDD18/ADDAVH/AVDDAx are valid, as long as the timing above is met.
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2c
2d
3
3a
4
5
6
7
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8
9
ITEM
2b
10
11
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Table 10-2. Core-Before-IO Power Sequencing (continued)
SYSTEM STATE
• VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD. DVDD18 must be enabled within 80 ms of CVDD valid and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100
ms from the time when CVDD is valid to the time when DVDD18 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD valid. DVDD18/ADDAVH/AVDDAx and CVDD1 may be enabled at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after
CVDD1 is valid, as long as the timing above is met.
• Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 7.
• DVDD15 can ramp up within 80ms of when DVDD18 is valid.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high.
• VDDALV, VDDUSBx, USBxVP and USBxVPTX ramp up within 80ms of when DVDD15 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• USBxDVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSBx, USBxVP and USBxVPTX are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• POR must continue to remain low for at least 100
μs after all power rails have stabilized.
End power stabilization phase
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33
nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire
16 μs.
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
• The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin.
• Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be
10000 to 50000 clock cycles.
End device initialization phase
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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Power Stabilization Phase Device Initialization Phase
POR
8
RESETFULL
Configuration
Inputs
10 11
RESET
1
1
CVDD
2a
CVDD1
2
VDDAHV
AVDDAx
DVDD18
2b
3
DVDD15
4
VDDALV
USBxVP
USBxVPTX
5 USBxDVDD33
3
4
5
3a
2d
6
7
SYSCLK1
2c
DDRCLKOUT
9
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RESETSTAT
Figure 10-1. Core-Before-IO Power Sequencing
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10.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in
and defined in
.
NOTE
TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.
3a
3b
4
2
2a
3
5
6
7
8
ITEM
1
9
10
11
12
Table 10-3. IO-Before-Core Power Sequencing
SYSTEM STATE
Begin Power Stabilization Phase
• VDDAHV, AVDDAx and DVDD18 ramp up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR ) is put into the reset state.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• CVDD (core AVS) ramps within 80 ms from the time ADDAHV, AVDDAx and DVDD18 are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• RESET may be driven high any time after DVDD18 is at a valid level. must be high before POR is driven high.
• CVDD1 (core constant) ramp at the same time or within 80 ms following CVDD. Although ramping CVDD1 simultaneously with CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state.
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 8.
• DVDD15 can ramp up within 80 ms of when CVDD1 is valid.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• VDDALV, VDDUSBx, USBxVP and USBxVPTX should ramp up within 80 ms of when DVDD15 is valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• USBxDVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSBx, USBxVP and USBxVPTX are valid.
• Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
• POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33
nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire
16 μs.
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be
10000 to 50000 clock cycles.
End device initialization phase
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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Power Stabilization Phase Device Initialization Phase
POR
RESETFULL
Configuration
Inputs
1
2
RESET
VDDAHV
AVDDAx
DVDD18
1
2
CVDD
3
3
CVDD1
4
DVDD15
5
VDDALV
USBxVP
USBxVPTX
6 USBxDVDD33
SYSCLK1
3a
2a
4
6
5
3b
7
8
DDRCLKOUT
9
11 12
10
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RESETSTAT
Figure 10-2. IO-Before-Core Power Sequencing
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10.2.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time may affect the long-term reliability of the part (due to an elevated voltage condition that can stress the part). The device should not be held in a reset for times exceeding one hour at a time and no more than 5% of the total lifetime for which the device is powered-up. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the device to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.
10.2.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the clocks is contingent on the state of the boot configuration pins.
describes the clock sequencing and the conditions that affect clock operation. Note that all clock drivers should be in a highimpedance state until CVDD is at a valid level and that all clock inputs be either active or in a static state with one leg pulled to ground and the other connected to CVDD.
Table 10-4. Clock Sequencing
CLOCK
DDRCLK
CORECLK
NETCPCLK
PCIECLK
HYPLNK0CLK
CONDITION
None
None
NETCPCLKSEL = 0
NETCPCLKSEL = 1
SEQUENCING
Must be present 16 µsec before POR transitions high.
CORECLK is used to clock the core PLL. It must be present 16 µsec before POR transitions high.
NETCPCLK is not used and should be tied to a static state.
NETCPCLK is used as a source for the NETCP PLL. It must be present before the NETCP
PLL is removed from reset and programmed.
PCIECLK must be present 16 µsec before POR transitions high.
PCIE will be used as a boot device.
PCIE will be used after boot.
PCIE will not be used.
PCIECLK is used as a source to the PCIE SerDes PLL. It must be present before the PCIe is removed from reset and programmed.
PCIECLK is not used and should be tied to a static state.
HyperLink will be used as HYPLNK0CLK must be present 16 µsec before POR transitions high.
a boot device.
HyperLink will be used after boot.
HyperLink will not be used.
HYPLNK0CLK is used as a source to the HyperLink SerDes PLL. It must be present before the HyperLink is removed from reset and programmed.
HYPLNK0CLK is not used and should be tied to a static state.
10.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent an excessive amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails.
Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can affect long term reliability.
10.2.3 Power Supply Decoupling and Bulk Capacitor
To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of power supply decoupling and bulk capacitors see the Hardware Design Guide for KeyStone II
Devices application report ( SPRABV0 ).
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10.2.4 SmartReflex
Increasing the device complexity increases its power consumption. With higher clock rates and increased performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in any powered circuit, independent of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, which is the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.
Texas Instruments SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the
AM5K2E0x device is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each AM5K2E0x device.
To help maximize performance and minimize power consumption of the device, SmartReflex is required to be implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins
(depending on power supply device being used), which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Consumption Summary for KeyStone
TCI66x Devices application report ( SPRABL4 ) and the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ).
Table 10-5. SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
(see
2
3
NO.
1
4
PARAMETER
td(VCNTL[4:2]-VCNTL[5]) Delay time - VCNTL[4:2] valid after VCNTL[5] low toh(VCNTL[5]-VCNTL[4:2]) Output hold time - VCNTL[4:2] valid after VCNTL[5] td(VCNTL[4:2]-VCNTL[5]) Delay time - VCNTL[4:2] valid after VCNTL[5] high toh(VCNTL[5]-VCNTL[2:0) Output hold time - VCNTL[4:2] valid after VCNTL[5] high
MIN MAX UNIT
300.00
0.07
172020C
(1) ns ms
0.07
300.00
172020C ns ms
(1) C = 1/SYSCLK1 frequency, in ms (see
4
VCNTL[5]
VCNTL[4:2]
1 3
LSB VID[2:0] MSB VID[5:3]
2
Figure 10-3. SmartReflex 4-Pin 6-Bit VID Interface Timing
10.2.5 Monitor Points
Two pairs of monitor points for the CVDD voltage level are provided. Both CVDDCMON and CVDDTMON are connected directly to the CVDD supply plane on the die itself. VSSCMON and VSSTMON are connected to the ground plane on the die. These pairs provide the best measurement points for the voltage at the silicon. They also provide the best point to connect the remote sense lines for the CVDD power supply. The use of a power supply with a differential remote sense input is highly desirable. The positive remote sense line should be connected to CVDDCMON and the negative remote sense line should be connected to VSSCMON. CVDDTMON and VSSTMON can be used as an alternative but always use either the CMON pair or the TMON pair. If the power supply remote sense is not differential
CVDDCMON or CVDDTMON can be connected to the sense line.
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10.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) includes a Global Power Sleep Controller (GPSC) and a number of
Local Power Sleep Controllers (LPSC) that control overall device power by turning off unused power domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several important power and clock operations.
For information on the Power Sleep Controller, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide ( SPRUGV4 ).
10.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various power domains.
The following table shows the AM5K2E0x power domains.
15
16
17
18
19
10
11
12
13
14
5
6
7
8
9
3
4
1
2
28
29
30
25
26
27
20
21
22
23
24
DOMAI
N
0
BLOCK(S)
Most peripheral logic (BOOTCFG,
EMIF16, I
2
C, INTC, GPIO, USB)
Per-core TETB and system TETB
Network Coprocessor
PCIe0
Reserved
HyperLink
SmartReflex
MSMC RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EMIF(DDR3)
Reserved
PCIe1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE
ARM Smart Reflex
Table 10-6. AM66K2Ex Power Domains
NOTE
Cannot be disabled
RAMs can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Cannot be disabled
MSMC RAM can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
POWER CONNECTION
Always on
Software control
Software control
Software control
Software control
Always on
Software control
Software control
Software control
Software control
Software control
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DOMAI
N
31
BLOCK(S)
ARM CorePac
Table 10-6. AM66K2Ex Power Domains (continued)
NOTE
Logic can be powered down
POWER CONNECTION
Software control
25
26
27
28
29
20
21
22
23
24
30
31
32
33
34
15
16
17
18
19
10
11
12
13
14
5
6
7
3
4
8
9
1
2
LPSC NUMBER
0
10.3.2 Clock Domains
Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls the clock gating logic for each module.
shows the AM5K2E0x clock domains.
Table 10-7. Clock Domains
Reserved
Reserved
PCIe_1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MODULE(S) NOTES
Shared LPSC for all peripherals other than those listed in this table Always on
USB_1
USB_0
EMIF16 and SPI
TSIP
Software control
Software control
Software control
Software control Debug subsystem and tracers
Reserved
Packet Accelerator
Always on
Software control
Ethernet SGMIIs
Security Accelerator
PCIe_0
Reserved
HyperLink
SmartReflex
MSMC RAM
Software control
Software control
Software control
Software control
Always on
Software control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DDR3 EMIF
Reserved
Software control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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41
42
43
44
45
LPSC NUMBER
35
36
37
38
39
40
46
47
48
49
50
51
52
No LPSC
Table 10-7. Clock Domains (continued)
MODULE(S)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE
ARM Smart Reflex
ARM CorePac
Bootcfg, PSC, and PLL Controller
NOTES
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Software control
Software control
Software control
These modules do not use LPSC
10.3.3 PSC Register Memory Map
shows the PSC Register memory map.
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
OFFSET
0x000
REGISTER
PID
0x004 - 0x010 Reserved
0x014 VCNTLID
0x018 - 0x11C Reserved
0x120 PTCMD
0x124 Reserved
0x128 PTSTAT
0x12C - 0x1FC Reserved
0x200
0x204
PDSTAT0
PDSTAT1
PDSTAT2
PDSTAT3
PDSTAT4
PDSTAT5
PDSTAT6
PDSTAT7
PDSTAT8
PDSTAT9
PDSTAT10
PDSTAT11
PDSTAT12
PDSTAT13
Table 10-8. PSC Register Memory Map
DESCRIPTION
Peripheral Identification Register
Reserved
Voltage Control Identification Register
Reserved
Power Domain Transition Command Register
Reserved
Power Domain Transition Status Register
Reserved
Power Domain Status Register 0
Power Domain Status Register 1
Power Domain Status Register 2
Power Domain Status Register 3
Power Domain Status Register 4
Power Domain Status Register 5
Power Domain Status Register 6
Power Domain Status Register 7
Power Domain Status Register 8
Power Domain Status Register 9
Power Domain Status Register 10
Power Domain Status Register 11
Power Domain Status Register 12
Power Domain Status Register 13
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0x330
0x334
0x338
0x33C
0x340
0x344
0x348
0x34C
0x350
0x354
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x358
0x35c
0x360
0x364
0x368
0x36C
OFFSET
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
REGISTER
PDSTAT14
PDSTAT15
PDSTAT16
PDSTAT17
PDSTAT18
PDSTAT19
PDSTAT20
PDSTAT21
PDSTAT22
PDSTAT23
PDSTAT24
0x264
0x268
0x26C
0x270
0x274
PDSTAT25
PDSTAT26
PDSTAT27
PDSTAT28
PDSTAT29
0x278 PDSTAT30
0x27C PDSTAT31
0x27C - 0x2FC Reserved
0x300
0x304
PDCTL0
PDCTL1
PDCTL12
PDCTL13
PDCTL14
PDCTL15
PDCTL16
PDCTL17
PDCTL18
PDCTL19
PDCTL20
PDCTL21
PDCTL2
PDCTL3
PDCTL4
PDCTL5
PDCTL6
PDCTL7
PDCTL8
PDCTL9
PDCTL10
PDCTL11
PDCTL22
PDCTL23
PDCTL24
PDCTL25
PDCTL26
PDCTL27
Table 10-8. PSC Register Memory Map (continued)
DESCRIPTION
Power Domain Status Register 14
Power Domain Status Register 15
Power Domain Status Register 16
Power Domain Status Register 17
Power Domain Status Register 18
Power Domain Status Register 19
Power Domain Status Register 20
Power Domain Status Register 21
Power Domain Status Register 22
Power Domain Status Register 23
Power Domain Status Register 24
Power Domain Status Register 25
Power Domain Status Register 26
Power Domain Status Register 27
Power Domain Status Register 28
Power Domain Status Register 29
Power Domain Status Register 30
Power Domain Status Register 31
Reserved
Power Domain Control Register 0
Power Domain Control Register 1
Power Domain Control Register 2
Power Domain Control Register 3
Power Domain Control Register 4
Power Domain Control Register 5
Power Domain Control Register 6
Power Domain Control Register 7
Power Domain Control Register 8
Power Domain Control Register 9
Power Domain Control Register 10
Power Domain Control Register 11
Power Domain Control Register 12
Power Domain Control Register 13
Power Domain Control Register 14
Power Domain Control Register 15
Power Domain Control Register 16
Power Domain Control Register 17
Power Domain Control Register 18
Power Domain Control Register 19
Power Domain Control Register 20
Power Domain Control Register 21
Power Domain Control Register 22
Power Domain Control Register 23
Power Domain Control Register 24
Power Domain Control Register 25
Power Domain Control Register 26
Power Domain Control Register 27
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0x868
0x86C
0x870
0x874
0x878
0x87C
0x880
0x884
0x888
0x88C
0x840
0x844
0x848
0x84C
0x850
0x854
0x858
0x85C
0x860
0x864
0x890
0x894
0x898
0x89C
0x8A0
0x8A4
0x818
0x81C
0x820
0x824
0x828
0x82C
0x830
0x834
0x838
0x83C
OFFSET
0x370
0x374
0x378
0x37C
REGISTER
PDCTL28
PDCTL29
PDCTL30
PDCTL31
0x380 - 0x7FC Reserved
0x800 MDSTAT0
0x804
0x808
0x80C
0x810
0x814
MDSTAT1
MDSTAT2
MDSTAT3
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
MDSTAT8
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
MDSTAT13
MDSTAT14
MDSTAT15
MDSTAT16
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
MDSTAT23
MDSTAT24
MDSTAT25
MDSTAT26
MDSTAT27
MDSTAT28
MDSTAT29
MDSTAT30
MDSTAT31
MDSTAT32
MDSTAT33
MDSTAT34
MDSTAT35
MDSTAT36
MDSTAT37
MDSTAT38
MDSTAT39
MDSTAT40
MDSTAT41
Table 10-8. PSC Register Memory Map (continued)
DESCRIPTION
Power Domain Control Register 28
Power Domain Control Register 29
Power Domain Control Register 30
Power Domain Control Register 31
Reserved
Module Status Register 0 (never gated)
Module Status Register 1
Module Status Register 2
Module Status Register 3
Module Status Register 4
Module Status Register 5
Module Status Register 6
Module Status Register 7
Module Status Register 8
Module Status Register 9
Module Status Register 10
Module Status Register 11
Module Status Register 12
Module Status Register 13
Module Status Register 14
Module Status Register 15
Module Status Register 16
Module Status Register 17
Module Status Register 18
Module Status Register 19
Module Status Register 20
Module Status Register 21
Module Status Register 22
Module Status Register 23
Module Status Register 24
Module Status Register 25
Module Status Register 26
Module Status Register 27
Module Status Register 28
Module Status Register 29
Module Status Register 30
Module Status Register31
Module Status Register 32
Module Status Register 33
Module Status Register 34
Module Status Register 35
Module Status Register 36
Module Status Register 37
Module Status Register 38
Module Status Register 39
Module Status Register 40
Module Status Register 41
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0xA4C
0xA50
0xA54
0xA58
0xA5C
0xA60
0xA64
0xA68
0xA6C
0xA70
0xA24
0xA28
0xA2C
0xA30
0xA34
0xA38
0xA3C
0xA40
0xA44
0xA48
0xA74
0xA78
0xA7C
0xA80
0xA84
0xA88
OFFSET
0x8A8
0x8AC
0x8B0
0x8B4
0x8B8
0x8BC
0x8C0
0x8C4
0x8C8
0x8CC
0x8D0
0x8D4 - 0x9FC Reserved
0xA00
0xA04
MDCTL0
MDCTL1
0xA08
0xA0C
MDCTL2
MDCTL3
0xA10
0xA14
0xA18
0xA1C
0xA20
MDCTL4
MDCTL5
MDCTL6
MDCTL7
MDCTL8
REGISTER
MDSTAT42
MDSTAT43
MDSTAT44
MDSTAT45
MDSTAT46
MDSTAT47
MDSTAT48
MDSTAT49
MDSTAT50
MDSTAT51
MDSTAT52
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
MDCTL9
MDCTL10
MDCTL11
MDCTL12
MDCTL13
MDCTL14
MDCTL15
MDCTL16
MDCTL17
MDCTL18
MDCTL29
MDCTL30
MDCTL31
MDCTL32
MDCTL33
MDCTL34
Table 10-8. PSC Register Memory Map (continued)
DESCRIPTION
Module Status Register 42
Module Status Register 43
Module Status Register 44
Module Status Register 45
Module Status Register 46
Module Status Register 47
Module Status Register 48
Module Status Register 49
Module Status Register 50
Module Status Register 51
Module Status Register 52
Reserved
Module Control Register 0 (never gated)
Module Control Register 1
Module Control Register 2
Module Control Register 3
Module Control Register 4
Module Control Register 5
Module Control Register 6
Module Control Register 7
Module Control Register 8
Module Control Register 9
Module Control Register 10
Module Control Register 11
Module Control Register 12
Module Control Register 13
Module Control Register 14
Module Control Register 15
Module Control Register 16
Module Control Register 17
Module Control Register 18
Module Control Register 19
Module Control Register 20
Module Control Register 21
Module Control Register 22
Module Control Register 23
Module Control Register 24
Module Control Register 25
Module Control Register 26
Module Control Register 27
Module Control Register 28
Module Control Register 29
Module Control Register 30
Module Control Register31
Module Control Register 32
Module Control Register 33
Module Control Register 34
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OFFSET
0xA8C
0xA90
0xA94
0xA98
0xA9C
0xAA0
0xAA4
0xAA8
0xAAC
0xAB0
0xAB4
REGISTER
MDCTL35
MDCTL36
MDCTL37
MDCTL38
MDCTL39
MDCTL40
MDCTL41
MDCTL42
MDCTL43
MDCTL44
MDCTL45
0xAB8
0xABC
0xAC0
0xAC4
0xAC8
MDCTL46
MDCTL47
MDCTL48
MDCTL49
MDCTL50
0xACC MDCTL51
0xAD0 MDCTL52
0xAD4 - 0xFFC Reserved
Table 10-8. PSC Register Memory Map (continued)
DESCRIPTION
Module Control Register 35
Module Control Register 36
Module Control Register 37
Module Control Register 38
Module Control Register 39
Module Control Register 40
Module Control Register 41
Module Control Register 42
Module Control Register 43
Module Control Register 44
Module Control Register 45
Module Control Register 46
Module Control Register 47
Module Control Register 48
Module Control Register 49
Module Control Register 50
Module Control Register 51
Module Control Register 52
Reserved
10.4 Reset Controller
The reset controller detects the different type of resets supported on the AM5K2E0x device and manages the distribution of those resets throughout the device. The device has the following types of resets:
• Power-on reset
• Hard reset
• Soft reset
• Local reset
explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more information on the effects of each reset on the PLL controllers and their clocks, see
.
TYPE
Power-on reset
INITIATOR
POR pin
RESETFULL pin
Hard reset
RESET pin
PLLCTL Register
(RSCTRL)
(1)
Watchdog timers
Emulation
Table 10-9. Reset Types
EFFECT(S)
Resets the entire chip including the test and emulation logic. The device configuration pins are latched only during power-on reset.
Hard reset resets everything except for test, emulation logic, and reset isolation modules.
This reset is different from power-on reset in that the PLL Controller assumes power and clocks are stable when a hard reset is asserted. The device configurations pins are not relatched.
Emulation-initiated reset is always a hard reset.
By default, these initiators are configured as hard reset, but can be configured (except emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the
DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in selfrefresh mode.
(1) All masters in the device have access to the PLL Control Registers.
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TYPE
Soft reset
Local reset
INITIATOR
RESET pin
PLLCTL Register
(RSCTRL)
Watchdog timers
LRESET pin
Watchdog timer timeout
LPSC MMRs
Table 10-9. Reset Types (continued)
EFFECT(S)
Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and
DDR3 EMIF MMRs contents are retained.
By default, these initiators are configured as hard reset, but can be configured as soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained during a soft reset if the SDRAM is placed in self-refresh mode.
Resets the C66x CorePac, without disturbing clock alignment or memory contents. The device configuration pins are not relatched.
10.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following:
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device, including the reset-isolated logic, when the device is already powered up. For this reason, the
RESETFULL pin, unlike POR, should be driven by the on-board host control other than the power good circuitry. For power-on reset, the Core PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR and
RESETFULL pins asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and remain in their reset state until otherwise configured by their respective peripheral. All peripherals that are power-managed are disabled after a power-on reset and must be enabled through the Device State Control Registers (for more details, see
).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in reset.
3. POR and RESETFULL must be held active until all supplies on the board are stable, and then for at least an additional period of time (as specified in
) for the chip-level PLLs to lock.
4. The POR pin can now be de-asserted.
5. After the appropriate delay, the RESETFULL pin can now be de-asserted. Reset-sampled pin values are latched at this point. Then, all chip-level PLLs are taken out of reset, locking sequences begin, and all power-on device initialization processes begin.
6. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, the DDR3 PLL has completed its locking sequences and are supplying a valid clock. The system clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide-by settings.
7. The device is now out of reset and code execution begins as dictated by the selected boot mode.
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NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The
RESET pin should not be tied to the POR pin.
10.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and resetisolated modules. POR should also remain de-asserted during this time.
Hard reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
• Emulation
By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft resets.
The following sequence must be followed during a hard reset:
1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time, the
RESET signal propagates to all modules (except those specifically mentioned above). To prevent offchip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
NOTE
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied to the POR pin.
10.4.3 Soft Reset
A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3 EMIF MMRs, PCIe MMRs sticky bits, and external memory content are retained. POR should also remain de-asserted during this time.
Soft reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers are not reset. If the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset, the DDR3 SDRAM memory content is retained.
During a soft reset, the following occurs:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates through the system. Internal system clocks are not affected. PLLs remain locked.
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2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the
PLL Controller pauses system clocks for approximately 8 cycles. At this point:
– The peripherals remain in the state they were in before the soft reset.
– The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT
Register.
– The DDR3 MMRs and PCIe MMRs retain their previous values. Only the DDR3 memory controller and PCIe state machines are reset by the soft reset.
– The PLL Controller remains in the mode it was in prior to the soft reset.
– System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration pins are not latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used to select the boot mode.
10.4.4 Local Reset
The local reset can be used to reset a particular C66x CorePac without resetting any other device components.
Local reset is initiated by the following:
• LRESET pin
• Watchdog timer should cause one of the below and RSTCFG registers in the PLL Controller. (See
and
– Local reset
– NMI
– NMI followed by a time delay and then a local reset for the C66x CorePac selected
– Hard reset by requesting reset via the PLL Controller
• LPSC MMRs (memory-mapped registers)
For more details see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
( SPRUGV2 ).
10.4.5 ARM CorePac Reset
The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such as the Cortex-A15 processor, memory subsystem, debug logic, etc. The ARM CorePac incorporates the
PSC to generate resets for its internal modules. Details of reset generation and distribution inside the
ARM CorePac can be found in the KeyStone II Architecture ARM CorePac User's Guide ( SPRUHJ4 ).
10.4.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLL Controller processes only the highest priority reset request. The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/soft reset
10.4.7 Reset Controller Register
The reset controller registers are part of the PLL Controller MMRs. All AM5K2E0x device-specific MMRs are covered in
. For more details on these registers and how to program them, see the
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide ( SPRUGV2 ).
10.4.8 Reset Electrical Data/Timing
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Table 10-10. Reset Timing Requirements
(1)
(see
and
NO.
1
2 tw(RESETFULL) tw(RESET)
RESETFULL Pin Reset
Pulse width - pulse width RESETFULL low
Soft/Hard-Reset
Pulse width - pulse width RESET low
(1) C = 1/SYSCLK1 clock frequency in ns
Table 10-11. Reset Switching Characteristics
(1)
(see
and
NO.
PARAMETER
RESETFULL Pin Reset
Delay time - RESETSTAT high after RESETFULL high 3 td(RESETFULLH-
RESETSTATH)
4 td(RESETH-RESETSTATH)
(1) C = 1/SYSCLK1 clock frequency in ns
Soft/Hard Reset
Delay time - RESETSTAT high after RESET high
MIN
500C
500C
MIN
MAX UNIT
ns ns
MAX UNIT
50000C ns
50000C ns
POR
1
RESETFULL
RESET
RESETSTAT
3
Figure 10-4. RESETFULL Reset Timing
POR
RESETFULL
2
RESET
4
RESETSTAT
Figure 10-5. Soft/Hard Reset Timing
Table 10-12. Boot Configuration Timing Requirements
(1)
(see
NO.
1
2 tsu(GPIOn-RESETFULL) Setup time - GPIO valid before RESETFULL asserted th(RESETFULL-GPIOn) Hold time - GPIO valid after RESETFULL asserted
(1) C = 1/SYSCLK1 clock frequency in ns.
MIN
12C
12C
MAX UNIT
ns ns
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POR
1
RESETFULL
GPIO[15:0]
2
Figure 10-6. Boot Configuration Timing
10.5 Core PLL (Main PLL), DDR3 PLL, NETCP PLL and the PLL Controllers
This section provides a description of the Core PLL, DDR3 PLL, NETCP PLL, and the PLL Controller. For details on the operation of the PLL Controller module, see the KeyStone Architecture Phase Locked Loop
(PLL) Controller User's Guide ( SPRUGV2 ).
The Core PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios, alignment, and gating for the system clocks to the device. By default, the device powers up with the Core
PLL bypassed.
shows a block diagram of the Core PLL and the PLL Controller.
The DDR3 PLL and NETCP PLL are used to provide dedicated clock to the DDR3 and NETCP respectively. These chip level PLLs support a wide range of multiplier and divider values, which can be programmed through the chip level registers located in the Device Control Register block. The Boot ROM will program the multiplier values for Core PLL and NETCP PLL based on boot mode. (See
for more details.)
The DDR3 PLL is used to supply clocks to DDR3 EMIF logic. This PLL can also be used without programming the PLL Controller. Instead, they can be controlled using the chip-level registers
(DDR3PLLCTL0, DDR3PLLCTL1) located in the Device Control Register block. To write to these registers, software must go through an unlocking sequence using the KICK0/KICK1 registers.
The multiplier values for all chip-level PLLs can be reprogrammed later based on the input parameter table. This feature provides flexibility in that these PLLs may be able to reuse other clock sources instead of having its own clock source.
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CORECLK(P|N)
PLLD
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PLLM
VCO
CLKOD
PLL
0
1
BYPASS
PLLOUT
PLLDIV1
PLL Controller
/1
/1
PLLDIV2
/x
PLLDIV3
/x
PLLDIV4
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
To Peripherals,
HyperLink, etc.
To Switch Fabric,
Accelerators,
SmartReflex, etc.
Figure 10-7. Core PLL and PLL Controller
Note that the Core PLL Controller registers can be accessed by any master in the device. The PLLM[5:0] bits of the multiplier are controlled by the PLLM Register inside the PLL Controller and the PLLM[12:6] bits are controlled by the chip-level COREPLLCTL0 Register. The output divide and bypass logic of the PLL are controlled by fields in the SECCTL Register in the PLL Controller. Only PLLDIV3, and PLLDIV4 are programmable on the device. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's
Guide ( SPRUGV2 ) for more details on how to program the PLL controller.
The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the Core PLL Controller. The Core PLL Controller also controls reset propagation through the chip, clock alignment, and test points. The Core PLL Controller monitors the PLL status and provides an output signal indicating when the PLL is locked.
Core PLL power is supplied externally via the Core PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ) for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).
The minimum CORECLK rise and fall times should also be observed. For the input clock timing requirements, see
It should be assumed that any registers not included in these sections are not supported by the device.
Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.
The PLL Controller module as described in the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide ( SPRUGV2 ) includes a superset of features, some of which are not supported on the device. The following sections describe the registers that are supported.
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10.5.1 Core PLL Controller Device-Specific Information
10.5.1.1 Internal Clocks and Maximum Operating Frequencies
The Core PLL, used to drive the SoC, the switch fabric, and a majority of the peripheral clocks (all but the
ARM CorePacs, DDR3, and the NETCP modules) requires a PLL Controller to manage the various clock divisions, gating, and synchronization. PLLM[5:0] input of the Core PLL is controlled by the PLL controller
PLLM register.
The Core PLL Controller has four SYSCLK outputs that are listed below along with the clock descriptions.
Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.
• SYSCLK1: Using local dividers, SYSCLK1 is used to derive clocks required for the majority of peripherals that do not need reset isolation.
The system peripherals and modules driven by SYSCLK1 are as follows; however, not all peripherals are supported in every part. See the Features chapter for the complete list of peripherals supported in your part.
EMIF16, USB 3.0, XFI, HyperLink, PCIe, SGMII, GPIO, Timer64, I
2
C, SPI, TSIP, TeraNet, UART,
ROM, CIC, Security Manager, BootCFG, PSC, Queue Manager, Semaphore, MPUs, EDMA, MSMC,
DDR3, EMIF.
• SYSCLK2:Full-rate, reset-isolated clock used to generate various other clocks required by peripherals that need reset isolation: e.g., SmartReflex.
• SYSCLK3: The default rate for this clock is 1/3. This clock is programmable from /1 to /32, where this clock does not violate the maximum of 350 MHz. SYSCLK3 can be turned off by software.
• SYSCLK4: 1/z-rate clock for the system trace module only. The default rate for this clock is 1/5. This clock is configurable: the maximum configurable clock is 210 MHz and the minimum configuration clock is 32 MHz. SYSCLK4 can be turned off by software.
Only SYSCLK3 and SYSCLK4 are programmable.
10.5.1.2 Local Clock Dividers
The clock signals from the Core PLL Controller are routed to various modules and peripherals on the device. Some modules and peripherals have one or more internal clock dividers. Other modules and peripherals have no internal clock dividers, but are grouped together and receive clock signals from a shared local clock divider. Internal and shared local clock dividers have fixed division ratios. See table
.
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Table 10-13. Core PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers
CLOCK
SYSCLK1
MODULE
INTERNAL CLOCK
DIVIDER(S)
SYSCLK1 Internal Clock Dividers
/1, /3, /3, /6, /6 ARM CorePac
Chip Interrupt Controllers (CICx)
DDR3 Memory Controller A (also receives clocks from the
DDR3_PLL)
EMIF16
HyperLink
MultiCore Shared Memory Controller (MSMC)
/6
/2
/6
/2, /3, /6
/1
/2, /3, /4, /6 PCI express (PCIe)
ROM
Serial Gigabit Media Independent Interface (SGMII)
/6
/2, /3, /6, /8
Universal Asynchronous Receiver/Transmitter (UART)
Universal Serial Bus 3.0 (USB 3.0)
Power/Sleep Controller (PSC)
EDMA
/6
/3, /6
SYSCLK1 Shared Local Clock Dividers
--
SYSCLK1 Memory Protection Units (MPUx)
Semaphore
TeraNet (SYSCLK1/3 domain)
Boot Config
General-Purpose Input/Output (GPIO)
I
2
C
SYSCLK1
Security Manager
Telecom Serial Interface Port (TSIP)
Serial Peripheral Interconnect (SPI)
TeraNet (CPU /6 domain)
Timers
--
--
SHARED LOCAL CLOCK
DIVIDER
--
--
--
--
--
--
--
--
--
--
--
/12, /24
/3
/6
10.5.1.3 Module Clock Input
lists various clock domains in the device and their distribution in each peripheral. The table also shows the distributed clock division in modules and their mapping with source clocks of the device
PLLs.
10.5.1.4 Core PLL Controller Operating Modes
The Core PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the BYPASS bit of the PLL Secondary Control Register (SECCTL).
• In bypass mode, PLL input is fed directly out as SYSCLK1.
• In PLL mode, SYSCLK1 is generated from the PLL output using the values set in the PLLM and PLLD fields in the COREPLLCTL0 Register.
External hosts must avoid access attempts to the SoC while the frequency of its internal clocks is changing. User software must implement a mechanism that causes the SoC to notify the host when the
PLL configuration has completed.
10.5.1.5 Core PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device power-up. The device should not be taken out of reset until this stabilization time has elapsed.
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The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
Core PLL reset time value, see
.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the PLL
Controller can be switched to PLL mode. The Core PLL lock time is given in
.
Table 10-14. Core PLL Stabilization, Lock, and Reset Times
PARAMETER
PLL stabilization time
PLL lock time
PLL reset time
(1) C = SYSCLK1(N|P) cycle time in ns.
MIN
100
1000
TYP MAX UNIT
µs
2000 × C
(1) ns
10.5.2 PLL Controller Memory Map
The memory map of the Core PLL Controller is shown in
Table 10-15 . AM5K2Exx-specific Core PLL
Controller Register definitions can be found in the sections following
. For other registers in the table, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide ( SPRUGV2 ).
It is recommended to use read-modify-write sequence to make any changes to the valid bits in the Core
PLL Controller registers.
Note that only registers documented here are accessible on the AM5K2Exx. Other addresses in the Core
PLL Controller memory map including the Reserved registers must not be modified. Furthermore, only the bits within the registers described here are supported.
Table 10-15. PLL Controller Registers (Including Reset Controller)
HEX ADDRESS RANGE
00 0231 0000 - 00 0231 00E3 -
ACRONYM
00 0231 00E4
00 0231 00E8
00 0231 00EC
RSTYPE
RSTCTRL
RSTCFG
00 0231 00F0
00 0231 00F0 - 00 0231 00FF -
RSISO
00 0231 0100
00 0231 0104
00 0231 0108
00 0231 010C
00 0231 0110
-
-
PLLCTL
SECCTL
PLLM
00 0231 0114
00 0231 0118
00 0231 011C
00 0231 0120
00 0231 0124
-
PLLDIV1
PLLDIV2
-
PLLDIV3
00 0231 0128 -
00 0231 012C - 00 0231 0134 -
00 0231 0138 PLLCMD
00 0231 013C
00 0231 0140
PLLSTAT
ALNCTL
00 0231 0144
00 0231 0148
00 0231 014C
DCHANGE
CKEN
CKSTAT
REGISTER NAME
Reserved
Reset Type Status Register (Reset Core PLL Controller)
Software Reset Control Register (Reset Core PLL Controller)
Reset Configuration Register (Reset Core PLL Controller)
Reset Isolation Register (Reset Core PLL Controller)
Reserved
PLL Control Register
Reserved
PLL Secondary Control Register
Reserved
PLL Multiplier Control Register
Reserved
PLL Controller Divider 1Register
PLL Controller Divider 2 Register
PLL Controller Divider 3Register
Reserved
Reserved
Reserved
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
Reserved
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Table 10-15. PLL Controller Registers (Including Reset Controller) (continued)
HEX ADDRESS RANGE
00 0231 0150
ACRONYM
SYSTAT
00 0231 0154 - 00 0231 015C -
00 0231 0160
00 0231 0164
PLLDIV4
PLLDIV5
00 0231 0168
00 0231 016C
PLLDIV6
PLLDIV7
00 0231 0170 PLLDIV8
00 0231 0174 - 00 0231 0193 PLLDIV9 - PLLDIV16
00 0231 0194 - 00 0231 01FF -
REGISTER NAME
SYSCLK Status Register
Reserved
PLL Controller Divider 4Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10.5.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Core PLL and is shown in
and described in
.
Figure 10-8. PLL Secondary Control Register (SECCTL)
22 19 31
Reserved
R-0000 0000
24 23
BYPASS
RW-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
OUTPUT DIVIDE
RW-0001
18 0
Reserved
RW-001 0000 0000 0000 0000
Table 10-16. PLL Secondary Control Register Field Descriptions
Bit Field
31-24 Reserved
Description
Reserved
23 BYPASS Core PLL bypass enable
• 0 - Core PLL bypass disabled
• 1 - Core PLL bypass enabled
22-19 OUTPUT DIVIDE Output divider ratio bits
• 0h - ÷1. Divide frequency by 1
• 1h - ÷2. Divide frequency by 2
• 2h - invalid entry
• 3h - ÷4. Divide frequency by 4
• 4h - invalid entry
• 5h - ÷6. Divide frequency by 6
• 6h - invalid entry
• 7h - ÷8. Divide frequency by 8
• 8h - invalid entry
• 9h - ÷10. Divide frequency by 10
• Ah - invalid entry
• Bh - ÷12. Divide frequency by 12
• Ch - invalid entry
• Dh - ÷14. Divide frequency by 14
• Eh - invalid entry
• Fh - ÷16. Divide frequency by 16
18-0 Reserved Reserved
10.5.2.2 PLL Controller Divider Register (PLLDIV3, and PLLDIV4)
The PLL Controller Divider Registers (PLLDIV3 and PLLDIV4) are shown in
and described in
mentioned in the footnote of
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Figure 10-9. PLL Controller Divider Register (PLLDIVn)
8 7 31
Reserved
R-0
16
Dn
15
(1)
EN
R/W-1
14
Legend: R/W = Read/Write; R = Read only; -n = value after reset
(1) D3EN for PLLDIV3; D4EN for PLLDIV4
(2) n=02h for PLLDIV3; n=03h for PLLDIV4
Reserved
R-0
Bit Field
31-16 Reserved
15 DnEN
14-8
7-0
Reserved
RATIO
RATIO
R/W-n
(2)
Table 10-17. PLL Controller Divider Register Field Descriptions
Description
Reserved
Divider Dn enable bit (See footnote of
)
• 0 = Divider n is disabled
• 1 = No clock output. Divider n is enabled.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits (See footnote of
• 0h = ÷1. Divide frequency by 1
• 1h = ÷2. Divide frequency by 2
• 2h = ÷3. Divide frequency by 3
• 3h = ÷4. Divide frequency by 4
• 4h - 4Fh = ÷5 to ÷80. Divide frequency range: divide frequency by 5 to divide frequency by 80.
0
10.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller Clock Align Control Register (ALNCTL) is shown in
and described in
.
Figure 10-10. PLL Controller Clock Align Control Register (ALNCTL)
31
Reserved
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
5 4 3
ALN4 ALN3
R/W-1 R/W-1
2
Reserved
R-0
0
Bit
31-5
2-0
4
3
Field
Reserved
ALN4
ALN3
Table 10-18. PLL Controller Clock Align Control Register Field Descriptions
Description
Reserved. This location is always read as 0. A value written to this field has no effect.
SYSCLKn alignment. Do not change the default values of these fields.
• 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
• 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
10.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLL CTL flags the change in the
DCHANGE Status Register. During the GO operation, the PLL controller changes only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also needs to be aligned to other clocks. The PLLDIV Divider Ratio Change Status Register is shown in
and described in
.
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Bit
31-5
2-0
4
3
Figure 10-11. PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
Reserved
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
5 4 3
SYS4 SYS3
R/W-1 R/W-1
2
Reserved
R-0
Field
Reserved
Table 10-19. PLLDIV Divider Ratio Change Status Register Field Descriptions
Description
Reserved. This bit location is always read as 0. A value written to this field has no effect.
SYS4
SYS3
Identifies when the SYSCLKn divide ratio has been modified.
• 0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
• 1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
0
10.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[4:1]. SYSTAT is shown in
and described in
.
Figure 10-12. SYSCLK Status Register (SYSTAT)
4 31
Reserved
R-n
Legend: R/W = Read/Write; R = Read only; -n = value after reset
3 2 1 0
SYS4ON SYS3ON SYS2ON SYS1ON
R-1 R-1 R-1 R-1
Table 10-20. SYSCLK Status Register Field Descriptions
Bit
31-4
3-0
Field Description
Reserved Reserved. This location is always read as 0. A value written to this field has no effect.
SYS[N
(1)
]ON SYSCLK[N] on status
• 0 = SYSCLK[N] is gated
• 1 = SYSCLK[N] is on
(1) Where N = 1, 2, 3, or 4
10.5.2.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status
Register is shown in
and described in
Figure 10-13. Reset Type Status Register (RSTYPE)
11 8 31 29
Reserved
28
EMU-RST
27 12
Reserved
R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
WDRST[N]
R-0
7 3
Reserved
R-0
2
PLLCTRLRST
R-0
1
RESET
R-0
0
POR
R-0
Bit Field
31-29 Reserved
28 EMU-RST
Table 10-21. Reset Type Status Register Field Descriptions
Description
Reserved. Always reads as 0. Writes have no effect.
Reset initiated by emulation
• 0 = Not the last reset to occur
• 1 = The last reset to occur
Reserved. Always reads as 0. Writes have no effect.
27-12 Reserved
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Bit
11
10
9
8
7-3
2
1
0
Field
WDRST3
WDRST2
WDRST1
WDRST0
Reserved
PLLCTLRST
RESET
POR
Table 10-21. Reset Type Status Register Field Descriptions (continued)
Description
Reset initiated by Watchdog Timer[N]
• 0 = Not the last reset to occur
• 1 = The last reset to occur
Reserved. Always reads as 0. Writes have no effect.
Reset initiated by PLLCTL
• 0 = Not the last reset to occur
• 1 = The last reset to occur
RESET reset
• 0 = RESET was not the last reset to occur
• 1 = RESET was the last reset to occur
Power-on reset
• 0 = Power-on reset was not the last reset to occur
• 1 = Power-on reset was the last reset to occur
10.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value is 0x5A69. A valid key will be stored as 0x000C. Any other key value is invalid. When the
RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key.
The Software Reset Control Register (RSTCTRL) is shown in
and described in
.
Figure 10-14. Reset Control Register (RSTCTRL)
17 15 31
Reserved
R-0x0000
Legend: R = Read only; -n = value after reset;
(1) Writes are conditional based on valid key.
16
SWRST
R/W-0x
(1)
KEY
R/W-0x0003
0
Bit Field
31-17 Reserved
16 SWRST
15-0 KEY
Table 10-22. Reset Control Register Field Descriptions
Description
Reserved
Software reset
• 0 = Reset
• 1 = Not reset
Key used to enable writes to RSTCTRL and RSTCFG.
10.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset (a hard reset or a soft reset) initiated by RESET, the watchdog timer, and the Core PLL Controller’s RSTCTRL Register. By default, these resets are hard resets. The Reset Configuration Register (RSTCFG) is shown in
and described in
Figure 10-15. Reset Configuration Register (RSTCFG)
31
Reserved
R-0x000000
14 13
PLLCTLRSTTYPE
R/W-0
(2)
Legend: R = Read only; R/W = Read/Write; -n = value after reset
(1) Where N = 1, 2, 3,....N (Not all these outputs may be used on a specific device.)
(2) Writes are conditional based on valid key. For details, see
12
RESETTYPE
R/W-0
(2)
206
11 4
Reserved
R-0x0
3
WDTYPE[N
(1)
]
R/W-0x00
(2)
0
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Table 10-23. Reset Configuration Register Field Descriptions
Bit
3
2
1
0
Field Description
31-14 Reserved
13 PLLCTLRSTTYPE
Reserved
PLL controller initiates a software-driven reset of type:
• 0 = Hard reset (default)
• 1 = Soft reset
12 RESETTYPE
11-4 Reserved
RESET initiates a reset of type:
• 0 = Hard reset (default)
• 1 = Soft reset
Reserved
WDTYPE3
WDTYPE2
WDTYPE1
WDTYPE0
Watchdog timer [N] initiates a reset of type:
• 0 = Hard reset (default)
• 1 = Soft reset
10.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non-power-on reset. Setting any of these bits effectively blocks reset to all Core PLL Control Registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the module-specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to resetisolate a particular module. For more information on the MDCTLx Register, see the KeyStone Architecture
Power Sleep Controller (PSC) User's Guide ( SPRUGV4 ). The Reset Isolation Register (RSISO) is shown in
and described in
.
Figure 10-16. Reset Isolation Register (RSISO)
9 7 31
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
8
SRISO
R/W-0
Reserved
R-0
0
Bit Field
31-9 Reserved
8 SRISO
7-0 Reserved
Table 10-24. Reset Isolation Register Field Descriptions
Description
Reserved.
Isolate SmartReflex control
• 0 = Not reset isolated
• 1 = Reset isolated
Reserved
10.5.3 Core PLL Control Registers
The Core PLL uses two chip-level registers (COREPLLCTL0 and COREPLLCTL1) along with the Core
PLL Controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.
For valid configurable values of the COREPLLCTL registers, see
for the address location of the KICK registers and their locking and unlocking sequences.
See
and
for COREPLLCTL0 details and
and
for
COREPLLCTL1 details.
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Figure 10-17. Core PLL Control Register 0 (COREPLLCTL0)
19 18 12 31 24 23
BWADJ[7:0]
RW,+0000 0101
Reserved
RW - 0000 0
Legend: RW = Read/Write; -n = value after reset
PLLM[12:6]
RW,+0000000
11
Reserved
6
RW, +000000
5 0
PLLD
RW,+000000
Bit Field
31-24 BWADJ[7:0]
23-19 Reserved
18-12 PLLM[12:6]
11-6 Reserved
5-0 PLLD
Table 10-25. Core PLL Control Register 0 (COREPLLCTL0) Field Descriptions
Description
BWADJ[11:8] and BWADJ[7:0] are located in COREPLLCTL0 and COREPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Reserved
7 bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor minus 1.
The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the
PLLM[12:6] bits are controlled by the above chip-level register. COREPLLCTL0 register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the KeyStone Architecture Phase Locked
Loop (PLL) Controller User's Guide ( SPRUGV2 ) for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Core PLL is also controlled by the SECCTL register in the PLL
Controller. See the
Reserved
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
Figure 10-18. Core PLL Control Register 1 (COREPLLCTL1)
7 31
Reserved
RW - 0000000000000000000000000
Legend: RW = Read/Write; -n = value after reset
6
ENSAT
RW-0
5 4
Reserved
R-00
3
BWADJ[11:8]
RW- 0000
0
Bit Field
31-7 Reserved
6 ENSAT
5-4
3-0
Reserved
BWADJ[11:8]
Table 10-26. Core PLL Control Register 1 (COREPLLCTL1) Field Descriptions
Description
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in COREPLLCTL0 and COREPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
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10.5.4 Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Electrical
Data/Timing
Table 10-27. Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Timing
Requirements
(1)
3
2
1
1
2
3
4
(see
through
NO.
4
5
5
3
4
2
2
1
1
3
2
3
4
1
1
3
2
4
5
5 tc(CORECLKN) tc(CORECLKP) tw(CORECLKN) tw(CORECLKN) tw(CORECLKP) tw(CORECLKP) tr(CORECLK_200 mV) tf(CORECLK_200 mV) tj(CORECLKN) tj(CORECLKP) tc(SGMII0CLKN) tc(SGMII0CLKP) tw(SGMII0CLKN) tw(SGMII0CLKN) tw(SGMII0CLKP) tw(SGMII0CLKP) tr(SGMII0CLK_200mV) tf(SGMII0CLK_200mV) tj(SGMII0CLKN) tj(SGMII0CLKP)
CORECLK[P:N]
Cycle time CORECLKN cycle time
Cycle time CORECLKP cycle time
Pulse width CORECLKN high
Pulse width CORECLKN low
Pulse width CORECLKP high
Pulse width CORECLKP low
Pulse width SGMII0CLKN low
Pulse width SGMII0CLKP high
Pulse width SGMII0CLKP low
Transition time SGMII0CLK differential rise time (200 mV)
Transition time SGMII0CLK differential fall time (200 mV)
Jitter, RMS SGMII0CLKN
3.2
3.2
0.45*tc
0.45*tc
0.45*tc
0.45*tc
25
25
0.55*tc
0.55*tc
0.55*tc
0.55*tc
Transition time CORECLK differential rise time (200 mV)
Transition time CORECLK differential fall time (200 mV)
Jitter, peak_to_peak _ periodic
CORECLKN
Jitter, peak_to_peak _ periodic
CORECLKP
50
50
350
350
0.02*tc(CORECLKN)
0.02*tc(CORECLKP)
SGMII0CLK[P:N]
Cycle time SGMII0CLKN cycle time
Cycle time SGMII0CLKP cycle time
Pulse width SGMII0CLKN high
3.2 or 6.4 or 8
3.2 or 6.4 or 8
0.45*tc(SGMII0CLKN) 0.55*tc(SGMII0CLKN)
0.45*tc(SGMII0CLKN)
0.45*tc(SGMII0CLKP)
0.45*tc(SGMII0CLKP)
50
50
0.55*tc(SGMII0CLKN)
0.55*tc(SGMII0CLKP)
0.55*tc(SGMII0CLKP)
350
350
4
Jitter, RMS SGMII0CLKP
MIN MAX UNIT
4 ps ps ps ps ps ps ps,
RMS ps,
RMS ns ns ns ns ns ns ns ns ns ns ns ns
4
5
5 tc(XFICLKN) tc(XFICLKP) tw(XFICLKN) tw(XFICLKN) tw(XFICLKP) tw(XFICLKP) tr(XFICLK_200mV) tf(XFICLK_200mV) tj(XFICLKN) tj(XFICLKP)
XFICLK[P:N]
Cycle time XFICLKN cycle time
Cycle time XFICLKP cycle time
Pulse width XFICLKN high
Pulse width XFICLKN low
Pulse width XFICLKP high
Pulse width XFICLKP low
Transition time XFICLK differential rise time (200 mV)
Transition time XFICLK differential fall time (200 mV)
Jitter, RMS XFICLKN
Jitter, RMS XFICLKP
3.2 or 6.4
3.2 or 6.4
0.45*tc(XFICLKN)
0.45*tc(XFICLKN)
0.45*tc(XFICLKP)
0.45*tc(XFICLKP)
50
50
0.55*tc(XFICLKN)
0.55*tc(XFICLKN)
0.55*tc(XFICLKP)
0.55*tc(XFICLKP)
350
350
4
4 ps ps ps,
RMS ps,
RMS ns ns ns ns ns ns
HYPLNK0CLK[P:N]
(1) See the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ) for detailed recommendations.
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1
1
3
2
3
4
1
1
3
2
3
2
2
1
1
3
4
Table 10-27. Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Timing
(continued)
(see
through
1
3
NO.
1
2
2
3
4
4
5 tc(HYPLNK0CLKN) tc(HYPLNK0CLKP) tw(HYPLNK0CLKN) tw(HYPLNK0CLKN) tw(HYPLNK0CLKP) tw(HYPLNK0CLKP) tr(HYPLNK0CLK) tf(HYPLNK0CLK) tj(HYPLNK0CLKN)
Cycle time HYPLNK0CLKN cycle time
Cycle time HYPLNK0CLKP cycle time
Pulse width HYPLNK0CLKN high
Pulse width HYPLNK0CLKN low
Pulse width HYPLNK0CLKP high
Pulse width HYPLNK0CLKP low
Rise time HYPLNK0CLK differential rise time (10% to 90%)
Fall time HYPLNK0CLK differential fall time (10% to 90%)
Jitter, RMS HYPLNK0CLKN
MIN
3.2 or 6.4
MAX UNIT
ns
3.2 or 6.4
0.45*tc(HYPLNK0CLKN) 0.55*tc(HYPLNK0CLKN) ns ns
0.45*tc(HYPLNK0CLKN) 0.55*tc(HYPLNK0CLKN)
0.45*tc(HYPLNK0CLKP) 0.55*tc(HYPLNK0CLKP)
0.45*tc(HYPLNK0CLKP) 0.55*tc(HYPLNK0CLKP) ns ns ns
0.2*tc(HYPLNK0CLKP)
0.2*tc(HYPLNK0CLKP)
4 ps ps
5 tj(HYPLNK0CLKP) Jitter, RMS HYPLNK0CLKP
4 ps,
RMS ps,
RMS
4
5
5 tc(PCIECLKN) tc(PCIECLKP) tw(PCIECLKN) tw(PCIECLKN) tw(PCIECLKP) tw(PCIECLKP) tr(PCIECLK) tf(PCIECLK) tj(PCIECLKN) tj(PCIECLKP)
PCIECLK[P:N]
Cycle time PCIECLKN cycle time
Cycle time PCIECLKP cycle time
Pulse width PCIECLKN high
Pulse width PCIECLKN low
Pulse width PCIECLKP high
Pulse width PCIECLKP low
Rise time PCIECLK differential rise time (10% to 90%)
Fall time PCIECLK differential fall time
(10% to 90%)
Jitter, RMS PCIECLKN
Jitter, RMS PCIECLKP
10
10
0.45*tc(PCIECLKN)
0.45*tc(PCIECLKN)
0.45*tc(PCIECLKP)
0.45*tc(PCIECLKP)
10
10
0.55*tc(PCIECLKN)
0.55*tc(PCIECLKN)
0.55*tc(PCIECLKP)
0.55*tc(PCIECLKP)
0.2*tc(PCIECLKP)
0.2*tc(PCIECLKP)
4
4 ps ps ps,
RMS ps,
RMS ns ns ns ns ns ns
4
5
5 tc(USBCLKN) tc(USBCLKP) tw(USBCLKN) tw(USBCLKN) tw(USBCLKP) tw(USBCLKP) tr(USBCLK) tf(USBCLK) tj(USBCLKN) tj(USBCLKP)
USBCLK[P:M]
Cycle time USBCLKM cycle time
Cycle time USBCLKP cycle time
Pulse width USBCLKM high
Pulse width USBCLKM low
Pulse width USBCLKP high
Pulse width USBCLKP low
Rise time USBCLK differential rise time
(10% to 90%)
Fall time USBCLK differential fall time
(10% to 90%)
Jitter, RMS USBCLKM
Jitter, RMS USBCLKP
10
10
0.45*tc(USBCLKN)
0.45*tc(USBCLKN)
0.45*tc(USBCLKP)
0.45*tc(USBCLKP)
50
50
10
10
0.55*tc(USBCLKN)
0.55*tc(USBCLKN)
0.55*tc(USBCLKP)
0.55*tc(USBCLKP)
350
350
4
4 ns ns ns ns ns ns ps ps ps,
RMS ps,
RMS tc(TSREFCLKN) tc(TSREFCLKP) tw(TSREFCLKN)
TSREFCLK[P:N]
(2)
Cycle time TSREFCLKN cycle time
Cycle time TSREFCLKP cycle time
Pulse width TSREFCLKN high
3.25
3.25
0.45*tc(TSREFCLKN)
32.55
32.55
0.55*tc(TSREFCLKN) ns ns ns
(2) TSREFCLK clock input is LVDS compliant.
210
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5
Table 10-27. Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Timing
(continued)
(see
through
2
3
NO.
2
4
4
5 tw(TSREFCLKN) tw(TSREFCLKP) tw(TSREFCLKP) tr(TSREFCLK_200mV) tf(TSREFCLK_200mV) tj(TSREFCLKN)
Pulse width TSREFCLKN low
Pulse width TSREFCLKP high
Pulse width TSREFCLKP low
Transition time TSREFCLK differential rise time (200 mV)
Transition time TSREFCLK differential fall time (200 mV)
Jitter, RMS TSREFCLKN tj(TSREFCLKP) Jitter, RMS TSREFCLKP
MIN
0.45*tc(TSREFCLKN)
0.45*tc(TSREFCLKP)
0.45*tc(TSREFCLKP)
50
50
MAX UNIT
0.55*tc(TSREFCLKN) ns
0.55*tc(TSREFCLKP)
0.55*tc(TSREFCLKP) ns ns
350
350
5.8
5.8
ps ps ps,
RMS ps,
RMS
1
2 3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
Figure 10-19. Clock Input Timing
5 peak-to-peak Differential Input
Voltage (250 mV to 2 V)
0 200 mV Transition Voltage Range for the 200-mV Transition Voltage Range
Figure 10-20. CORECLK, SGMII0CLK and USBCLK Clock Transition Time
peak-to-peak
Differential
Input Voltage
(400 mV to 1100 mV)
0
10% to 90% of peak-to-peak
Voltage
Max T = 0.2
× T from
10% to 90% of the peak-to-peak
Differential Voltage
Max T = 0.2
× T from
90% to 10% of the peak-to-peak
Differential Voltage
Figure 10-21. HYPLNK0CLK, XFICLK, and PCIECLK Rise and Fall Times
10.6 DDR3 PLL
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The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, DDR3 PLL is programmed to a valid frequency during the boot configuration process before being enabled and used.
DDR3 PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ) for detailed recommendations.
PLLM
DDR3 PLL
DDRCLK(N|P)
PLLD
VCO
0
PLLOUT
CLKOD
1
BYPASS
Figure 10-22. DDR3 PLL Block Diagram
´
2
DDR3
PHY
DDR3CLKOUT
10.6.1 DDR3 PLL Control Registers
The DDR3 PLL, which is used to drive the DDR3 PHY for the EMIF, does not use a PLL controller. DDR3
PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configurable values, see
for the address location of the registers and locking and unlocking sequences for accessing the registers. These registers are reset on
POR only.
Figure 10-23. DDR3 PLL Control Register 0 (DDR3PLLCTL0)
18 31
BWADJ[7:0]
RW,+0000 1001
24 23
BYPASS
RW,+0
Legend: RW = Read/Write; -n = value after reset
22
CLKOD
19
RW,+0001
PLLM
RW,+0000000010011
6 5 0
PLLD
RW,+000000
Bit Field
31-24 BWADJ[7:0]
23 BYPASS
22-19 CLKOD
18-6 PLLM
5-0 PLLD
Table 10-28. DDR3 PLL Control Register 0 Field Descriptions
Description
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1
A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply factor minus 1
A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide value minus 1
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Figure 10-24. DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31 15
Reserved
RW - 00000000000000000
Legend: RW = Read/Write; -n = value after reset
14
PLLRST
RW-0
13 7
Reserved
RW-0000000
6
ENSAT
RW-0
5 4
Reserved
R-00
3
BWADJ[11:8]
RW- 0000
0
Bit Field
31-15 Reserved
14 PLLRST
13-7 Reserved
6 ENSAT
5-4
3-0
Reserved
BWADJ[11:8]
Table 10-29. DDR3 PLL Control Register 1 Field Descriptions
Description
Reserved
PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in the DDR3PLLCTL0 and the DDR3PLLCTL1 registers.
BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
10.6.2 DDR3 PLL Device-Specific Information
As shown in
, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory controller. During power-on resets, the internal clocks of the DDR3 PLL are affected as described in Section
. The DDR3 PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
10.6.3 DDR3 PLL Input Clock Electrical Data/Timing
applies to DDR3 memory interface.
Table 10-30. DDR3 PLL DDRCLK(N|P) Timing Requirements
(see
and
No.
4
5
5
3
4
2
2
1
1
3 tc(DDRCLKN) tc(DDRCLKP) tw(DDRCLKN) tw(DDRCLKN) tw(DDRCLKP) tw(DDRCLKP) tr(DDRCLK_200 mV) tf(DDRCLK_200 mV) tj(DDRCLKN) tj(DDRCLKP)
DDRCLK[P:N]
Cycle time _ DDRCLKN cycle time
Cycle time _ DDRCLKP cycle time
Pulse width _ DDRCLKN high
Pulse width _ DDRCLKN low
Pulse width _ DDRCLKP high
Pulse width _ DDRCLKP low
Transition time _ DDRCLK differential rise time (200 mV)
Transition time _ DDRCLK differential fall time (200 mV)
Jitter, peak_to_peak _ periodic DDRCLKN
Jitter, peak_to_peak _ periodic DDRCLKP
Min Max Unit
3.2
25
3.2
25
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN)
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN)
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP)
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP)
50
50
350
350
0.02*tc(DDRCLKN)
0.02*tc(DDRCLKP) ps ps ps ps ns ns ns ns ns ns
1
2 3
DDRCLKN
DDRCLKP
4
5
Figure 10-25. DDR3 PLL DDRCLK Timing
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10.7 NETCP PLL
The NETCP PLL generates interface clocks for the Network Coprocessor. Using the NETCPCLKSEL pin the user can select the input source of the NETCP PLL as either the output of the Core PLL mux or the
NETCPCLK clock reference source. When coming out of power-on reset, NETCP PLL comes out in a bypass mode and needs to be programmed to a valid frequency before being enabled and used.
NETCP PLL power is supplied via the NETCP PLL power-supply pin (AVDDA3). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices application report ( SPRABV0 ) for detailed recommendations.
CORECLK(P|N)
NETCPCLK(P|N)
0
1
PLLD
PLLM
VCO
NETCP PLL
CLKOD
0
1
BYPASS
NETCP
Clock Source
MUX
SYSCLK0
0
/3
1
NETCP
Sub-system
NETCPCLKSEL
NETCPPLLCTL1.PAPLL
(bit13)
Figure 10-26. NETCP PLL Block Diagram
10.7.1 NETCP PLL Local Clock Dividers
The clock signal from the NETCP PLL Controller is routed to the Network Coprocessor. The NETCP module has two internal dividers with fixed division ratios. See table
10.7.2 NETCP PLL Control Registers
The NETCP PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. NETCP
PLL can be controlled using the NETCPPLLCTL0 and NETCPPLLCTL1 registers located in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configuration values, see
for the address location of the registers and locking and unlocking sequences for accessing these registers. These registers are reset on
POR only.
Figure 10-27. NETCP PLL Control Register 0 (NETCPPLLCTL0)
18 31
BWADJ[7:0]
RW,+0000 1001
24 23
BYPASS
RW,+0
Legend: RW = Read/Write; -n = value after reset
22
CLKOD
19
RW,+0001
PLLM
RW,+0000000010011
6 5 0
PLLD
RW,+000000
Bit Field
31-24 BWADJ[7:0]
23 BYPASS
22-19 CLKOD
Table 10-31. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0)
Description
BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1
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Bit Field
18-6 PLLM
5-0
Table 10-31. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0) (continued)
PLLD
Description
A 13-bit field that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor minus 1.
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
Figure 10-28. NETCP PLL Control Register 1 (NETCPPLLCTL1)
31
Reserved
15
RW - 00000000000000000
14
PLLRST
RW-0
Legend: RW = Read/Write; -n = value after reset
13
PAPLL
RW-0
12 7
Reserved
RW-000000
6
ENSAT
RW-0
5 4
Reserved
R-00
3
BWADJ[11:8]
RW-0000
0
Bit Field
31-15 Reserved
14 PLLRST
13 PAPLL
12-7 Reserved
6 ENSAT
5-4
3-0
Reserved
BWADJ[11:8]
Table 10-32. NETCP PLL Control Register 1 Field Descriptions (NETCPPLLCTL1)
Description
Reserved
PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
NETCP Clock Source MUX Control
• 0 = SYSCLK0
• 1 = NETCP PLL
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
10.7.3 NETCP PLL Device-Specific Information
As shown in
, the output of NETCP PLL (PLLOUT) is divided by 3 and directly fed to the
Network Coprocessor. During power-on resets, the internal clocks of the NETCP PLL are affected as described in
. The NETCP PLL is unlocked only during the power-up sequence and is locked
by the time the RESETSTAT pin goes high. It does not lose lock during any other resets.
10.7.4 NETCP PLL Input Clock Electrical Data/Timing
1
1
3
2
2
3
4
4
5
5 tc(NETCPCLKN) tc(NETCPCLKP) tw(NETCPCLKN) tw(NETCPCLKN) tw(NETCPCLKP) tw(NETCPCLKP) tr(NETCPCLK_250mV) tf(NETCPCLK_250mV) tj(NETCPCLKN) tj(NETCPCLKP)
Table 10-33. NETCP PLL Timing Requirements
(see
and
NO.
NETCPCLK[P:N]
Cycle time _ NETCPCLKN cycle time
Cycle time _ NETCPCLKP cycle time
Pulse width _ NETCPCLKN high
Pulse width _ NETCPCLKN low
Pulse width _ NETCPCLKP high
Pulse width _ NETCPCLKP low
Transition time _ NETCPCLK differential rise time
(250 mV)
Transition time _ NETCPCLK differential fall time
(250 mV)
Jitter, peak_to_peak _ periodic NETCPCLKN
Jitter, peak_to_peak _ periodic NETCPCLKP
MIN
3.2
3.2
0.45*tc(NETCPCLKN)
0.45*tc(NETCPCLKN)
0.45*tc(NETCPCLKP)
0.45*tc(NETCPCLKP)
50
50
MAX UNIT
25
25
0.55*tc(NETCPCLKN)
0.55*tc(NETCPCLKN)
0.55*tc(NETCPCLKP)
0.55*tc(NETCPCLKP)
350
350 ps
100 ps, pk-pk
100 ps, pk-pk ns ns ns ns ns ns ps
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1
2 3
NETCPCLKN
NETCPCLKP
4
Figure 10-29. NETCP PLL Timing
5
10.8 DDR3 Memory Controller
The 72-bit DDR3 Memory Controller bus of the AM5K2E0x is used to interface to JEDEC standardcompliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and does not share the bus with any other type of peripheral.
10.8.1 DDR3 Memory Controller Device-Specific Information
216
The AM5K2E0x includes one 64-bit wide, 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.
Due to the complicated nature of the interface, a limited number of topologies are supported to provide a
16-bit, 32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR JEDEC Specification JESD79-3C.
Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank topologies to be supported by the interface:
• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
• 36-bit:Five 8-bit SDRAMs (including 4 bits of ECC)
• 64-bit:Four 16-bit SDRAMs
• 64-bit:Eight 8-bit SDRAMs
• 32-bit:Two 16-bit SDRAMs
• 32-bit: Four 8-bit SDRAMs
• 16-bit:One 16-bit SDRAM
• 16-bit:Two 8-bit SDRAMs
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as I
2
C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes before signaling to master B that the message is ready, when master B attempts to read the software message, the master B read may bypass the master A write. Thus, master B may read stale data and receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering in the software.
If master A does not wait for an indication that a write is complete, it must perform the following workaround:
1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
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3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.
10.8.2 DDR3 Slew Rate Control
The DDR3 slew rate is controlled by use of the PHY registers. See theKeyStone Architecture DDR3
Memory Controller User's Guide
SPRUGV8 for details.
10.8.3 DDR3 Memory Controller Electrical Data/Timing
The DDR3 Design Requirements for KeyStone Devices application report SPRABI1 specifies a complete
DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the DDR3 JEDEC Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met. Therefore, no electrical data/timing information is supplied here for this interface.
NOTE
TI supports only designs that follow the board design guidelines outlined in the application report.
10.9 I
2
C Peripheral
The Inter-Integrated Circuit (I
2
C) module provides an interface between SoC and other devices compliant with Philips Semiconductors (now NXP Semiconductors) Inter-Integrated Circuit bus specification version
2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the device through the I
2
C module.
10.9.1 I
2
C Device-Specific Information
The device includes multiple I
2
C peripheral modules.
NOTE
When using the I
2
C module, ensure there are external pullup resistors on the SDA and SCL pins.
The I
2
C modules on the AM5K2E0x may be used by the SoC to control local peripheral ICs (DACs, ADCs, etc.), communicate with other controllers in a system, or to implement a user interface.
The I
2
C port supports:
• Compatibility with Philips I
2
C specification revision 2.1 (January 2000)
• Fast mode up to 400 kbps (no fail-safe I/O buffers)
• Noise filter to remove noise of 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
shows a block diagram of the I
2
C module.
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SCL
Noise
Filter
SDA
Noise
Filter
Clock
Prescale
Bit Clock
Generator
Transmit
Transmit
Shift
Transmit
Buffer
Receive
Receive
Buffer
Receive
Shift
Peripheral Clock
(CPU/6)
Control
Own
Address
Slave
Address
Mode
Data
Count
Extended
Mode
Interrupt/DMA
Interrupt
Mask/Status
Interrupt
Status
Interrupt
Vector
Shading denotes control/status registers.
Figure 10-30. I
2
C Module Block Diagram
10.9.2 I
2
C Peripheral Register Description
HEX ADDRESS OFFSETS ACRONYM
0x0000 ICOAR
0x0004
0x0008
ICIMR
ICSTR
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
0x0028
0x002C
0x0030
0x0034
0x0038
ICIVR
ICEMDR
ICPSC
ICPID1
ICPID2
Table 10-34. I
2
C Registers
REGISTER NAME
I
2
C Own Address Register
I
2
C Interrupt Mask/status Register
I
2
C Interrupt Status Register
I
2
C Clock Low-time Divider Register
I
2
C Clock High-time Divider Register
I
2
C Data Count Register
I
2
C Data Receive Register
I
2
C Slave Address Register
I
2
C Data Transmit Register
I
2
C Mode Register
I
2
C Interrupt Vector Register
I
2
C Extended Mode Register
I
2
C Prescaler Register
I
2
C Peripheral Identification Register 1 [value: 0x0000 0105]
I
2
C Peripheral Identification Register 2 [value: 0x0000 0005]
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HEX ADDRESS OFFSETS ACRONYM
0x003C -0x007F -
Table 10-34. I
2
C Registers (continued)
REGISTER NAME
Reserved
10.9.3 I
2
C Electrical Data/Timing
10.9.3.1 Inter-Integrated Circuits (I
2
C) Timing
Table 10-35. I
2
C Timing Requirements
(1)
(see
)
NO.
1
2
3 t t t c(SCL) su(SCLH-SDAL) h(SDAL-SCLL)
Cycle time, SCL
Setup time, SCL high before SDA low (for a repeated START condition)
Hold time, SCL low after SDA low (for a START and a repeated START condition)
STANDARD MODE
MIN
10
4.7
4
MAX
FAST MODE
MIN
2.5
0.6
0.6
MAX UNIT
µs
µs
µs
4
5
6
7 t w(SCLL) t w(SCLH) t su(SDAV-SCLH) t h(SCLL-SDAV)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (for I
2
C bus devices)
4.7
0
4
250
(3)
3.45
1.3
0.6
100
(2)
0
(3)
0.9
(4)
µs
µs ns
µs
8 t w(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
µs
9
10
11
12
13 t t t r(SDA) r(SCL) f(SDA) t f(SCL) t su(SCLH-SDAH)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Setup time, SCL high before SDA high (for STOP condition) 4
1000 20 + 0.1C
b
(5)
1000 20 + 0.1C
b
(5)
300 20 + 0.1C
b
(5)
300 20 + 0.1C
b
(5)
0.6
300
300
300
300 ns ns ns ns
µs
14 t w(SP)
C b
(5)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line 400
0 50
400 ns pF
(1) The I
2
C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r
(according to the Standard-mode I
2 max + t
C-Bus Specification) before the SCL line is released.
su(SDA-SCLH)
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin undefined region of the falling edge of SCL.
= 1000 + 250 = 1250 ns of the SCL signal) to bridge the
(4) The maximum t h(SDA-SCLL)
(5) C b has to be met only if the device does not stretch the low period [t w(SCLL)
] of the SCL signal.
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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11
9
SDA
8
4
10
5
6
14
13
SCL
1
7
12
2
3
3
Stop Start Repeated
Start
Figure 10-31. I
2
C Receive Timings
Stop
Table 10-36. I
2
C Switching Characteristics
(1)
(see
)
NO.
16
17
18 t t t c(SCL) su(SCLH-SDAL) h(SDAL-SCLL)
PARAMETER
Cycle time, SCL
Setup time, SCL high to SDA low (for a repeated START condition)
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
STANDARD
MODE
MIN
10
4.7
4
MAX
FAST MODE
MIN
2.5
0.6
0.6
19
20
21
22
23 t t t t w(SCLL) t w(SCLH) d(SDAV-SDLH) v(SDLL-SDAV) w(SDAH)
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (for I
2
C bus devices)
Pulse duration, SDA high between STOP and START conditions
4.7
4
250
0
4.7
1.3
0.6
100
0
1.3
24
25
26
27
28 t r(SDA) t r(SCL) t f(SDA) t f(SCL) t d(SCLH-SDAH)
C p
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I
2
C pin
4
1000 20 + 0.1C
b
(1)
1000 20 + 0.1C
b
(1)
300 20 + 0.1C
b
(1)
300 20 + 0.1C
b
(1)
10
(1) C b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
0.6
MAX UNIT
0.9
300
300
300
300
10
µs
µs
µs
µs
µs ns
µs
µs ns ns ns ns
µs pF
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26
24
SDA
23
19
25
20
21
28
SCL
16
22
27
17
18
18
Stop Start Repeated
Start
Figure 10-32. I
2
C Transmit Timings
Stop
10.10 SPI Peripheral
The Serial Peripheral Interconnect (SPI) module provides an interface between the SoC and other SPIcompliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot.
The SPI module on AM5K2E0x is supported only in master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander.
10.10.1 SPI Electrical Data/Timing
Table 10-37. SPI Timing Requirements
7
7
8
7
7
8
8
8
(see
)
NO.
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0 tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0 th(SPC-SPIDIN) Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
Table 10-38. SPI Switching Characteristics
3
4
1
2
(see
and
NO.
4
4
PARAMETER MIN
tc(SPC) tw(SPCH) tw(SPCL)
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
Cycle time, SPICLK, all master modes
Pulse width high, SPICLK, all master modes
Pulse width low, SPICLK, all master modes td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK. Polarity = 0, Phase = 0.
3*P2
(1)
0.5*(3*P2) - 1
0.5*(3*P2) - 1 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK. Polarity = 0, Phase = 1.
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK Polarity = 1, Phase = 0
MIN MAX UNIT
2
2
5
2
2
5
5
5
MAX UNIT
ns ns ns ns ns ns ns ns
5
5 ns ns
5 ns ns ns ns
(1) P2=1/(SYSCLK1/6)
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Table 10-38. SPI Switching Characteristics (continued)
(see
and
NO.
4
5
5
5
5
6
6
6
6
19
19
19
19
20
20
20
20
PARAMETER
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK Polarity = 1, Phase = 1 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK. Polarity = 0 Phase = 0 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 0 Phase = 1 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 1 Phase = 0 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 1 Phase = 1 toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 0 Phase = 0 toh(SPC-
SPIDOUT) toh(SPC-
SPIDOUT) toh(SPC-
SPIDOUT) td(SCS-SPC)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 0 Phase = 1
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 1 Phase = 0
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 1 Phase = 1
0.5*tc - 2
0.5*tc - 2
0.5*tc - 2
0.5*tc - 2
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
Delay from SPISCSx\ active to first SPICLK. Polarity = 0
Phase = 0
2*P2 - 5 td(SCS-SPC)
0.5*tc + (2*P2) - 5
2
2*P2 + 5
0.5*tc + (2*P2) + 5 td(SCS-SPC) td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0
Phase = 1
Delay from SPISCSx\ active to first SPICLK. Polarity = 1
Phase = 0
Delay from SPISCSx\ active to first SPICLK. Polarity = 1
Phase = 1
2*P2 - 5
0.5*tc + (2*P2) - 5
2*P2 + 5
0.5*tc + (2*P2) + 5 td(SPC-SCS) td(SPC-SCS) td(SPC-SCS) td(SPC-SCS) tw(SCSH)
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 0 Phase = 0
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 0 Phase = 1
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 1 Phase = 0
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 1 Phase = 1
Minimum inactive time on SPISCSx\ pin between two transfers when SPISCSx\ is not held using the CSHOLD feature.
MIN
1*P2 - 5
0.5*tc + (1*P2) - 5
1*P2 - 5
0.5*tc + (1*P2) - 5
2*P2 - 5
MAX UNIT
5
2
2
2
1*P2 + 5
0.5*tc + (1*P2) + 5
1*P2 + 5
0.5*tc + (1*P2) + 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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SPICLK
SPIDOUT
SPIDIN
2
1
3
4
MO(0)
7
MI(0)
8
5
MO(1)
MI(1)
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MASTER MODE
POLARITY = 0 PHASE = 0
6
MO(n−1)
MI(n−1)
MO(n)
MI(n)
SPICLK
SPIDOUT
SPIDIN
SPICLK
SPIDOUT
SPIDIN
MASTER MODE
POLARITY = 0 PHASE = 1
4
MO(0)
7
MI(0)
8
5
MO(1)
6
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
4
MO(0)
7
MI(0)
8
5
MO(1)
MI(1)
MASTER MODE
POLARITY = 1 PHASE = 0
6
MO(n−1)
MI(n−1)
MO(n)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPICLK
SPIDOUT
4
MO(0)
7
MI(0)
8
5
MO(1)
6
MO(n−1) MO(n)
SPIDIN
MI(1) MI(n−1) MI(n)
Figure 10-33. SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
MASTER MODE 4 PIN WITH CHIP SELECT
19 20
SPICLK
SPIDOUT
SPIDIN
SPISCSx
MO(0)
MI(0)
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
Figure 10-34. SPI Additional Timings for 4-Pin Master Mode with Chip Select Option
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10.11 HyperLink Peripheral
The AM5K2E0x includes HyperLink for companion device interfaces. This is a four-lane SerDes interface designed to operate at up to 10 Gbps per lane from pin-to-pin. The interface is used to connect with external accelerators that are manufactured using TI libraries. The HyperLink lines must be connected with DC coupling.
The interface includes the serial station management interfaces used to send power management and flow messages between devices. Each HyperLink interface consists of four LVCMOS inputs and four
LVCMOS outputs configured as two 2-wire input buses and two 2-wire output buses. Each 2-wire bus includes a data signal and a clock signal.
Table 10-39. HyperLink Peripheral Timing Requirements
3
6
1
2
1
2
3
6
(see
,
and
)
NO.
tc(HYPTXFLCLK) tw(HYPTXFLCLKH) tw(HYPTXFLCLKL)
FL Interface
Clock period - HYPTXFLCLK (C1)
High pulse width - HYPTXFLCLK
Low pulse width - HYPTXFLCLK
7
6 tsu(HYPTXFLDAT-HYPTXFLCLKH) th(HYPTXFLCLKH-HYPTXFLDAT) tsu(HYPTXFLDAT-HYPTXFLCLKL)
Setup time - HYPTXFLDAT valid before HYPTXFLCLK high
Hold time - HYPTXFLDAT valid after HYPTXFLCLK high
Setup time - HYPTXFLDAT valid before HYPTXFLCLK low
7 th(HYPTXFLCLKL-HYPTXFLDAT)
7
6
7 tc(HYPRXPMCLK) tw(HYPRXPMCLK) tw(HYPRXPMCLK) tsu(HYPRXPMDAT-
HYPRXPMCLKH) th(HYPRXPMCLKH-HYPRXPMDAT) tsu(HYPRXPMDAT-
HYPRXPMCLKL) th(HYPRXPMCLKL-HYPRXPMDAT)
Hold time - HYPTXFLDAT valid after HYPTXFLCLK low
PM Interface
Clock period - HYPRXPMCLK (C3)
High pulse width - HYPRXPMCLK
Low pulse width - HYPRXPMCLK
Setup time - HYPRXPMDAT valid before
HYPRXPMCLK high
Hold time - HYPRXPMDAT valid after HYPRXPMCLK high
Setup time - HYPRXPMDAT valid before
HYPRXPMCLK low
Hold time - HYPRXPMDAT valid after HYPRXPMCLK low
MIN
5.75
0.4*C1
0.4*C1
1
1
1
1
5.75
0.4*C3
0.4*C3
1
1
1
1
MAX
0.6*C1
0.6*C1
0.6*C3
0.6*C3
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 10-40. HyperLink Peripheral Switching Characteristics
3
4
1
2
3
4
1
2
(see
,
and
)
NO.
5
4
5 tc(HYPRXFLCLK) tw(HYPRXFLCLKH) tw(HYPRXFLCLKL) tosu(HYPRXFLDAT-
HYPRXFLCLKH) toh(HYPRXFLCLKH-HYPRXFLDAT)
PARAMETER
FL Interface
Clock period - HYPRXFLCLK (C2)
High pulse width - HYPRXFLCLK
Low pulse width - HYPRXFLCLK
Setup time - HYPRXFLDAT valid before HYPRXFLCLK high
Hold time - HYPRXFLDAT valid after HYPRXFLCLK high tosu(HYPRXFLDAT-
HYPRXFLCLKL)
Setup time - HYPRXFLDAT valid before HYPRXFLCLK low toh(HYPRXFLCLKL-HYPRXFLDAT) Hold time - HYPRXFLDAT valid after HYPRXFLCLK low
PM Interface
tc(HYPTXPMCLK) tw(HYPTXPMCLK) tw(HYPTXPMCLK) tosu(HYPTXPMDAT-
HYPTXPMCLKH)
Clock period - HYPTXPMCLK (C4)
High pulse width - HYPTXPMCLK
Low pulse width - HYPTXPMCLK
Setup time - HYPTXPMDAT valid before HYPTXPMCLK high
MIN
6.4
0.4*C2
0.4*C2
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
6.4
0.4*C4
0.4*C4
0.25*C2-0.4
224
MAX
0.6*C2
0.6*C2
0.6*C4
0.6*C4
UNIT
ns ns ns ns
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Table 10-40. HyperLink Peripheral Switching Characteristics (continued)
(see
,
and
)
NO.
5
4
5 toh(HYPTXPMCLKH-
HYPTXPMDAT) tosu(HYPTXPMDAT-
HYPTXPMCLKL) toh(HYPTXPMCLKL-HYPTXPMDAT)
PARAMETER
Hold time - HYPTXPMDAT valid after HYPTXPMCLK high
Setup time - HYPTXPMDAT valid before HYPTXPMCLK low
Hold time - HYPTXPMDAT valid after HYPTXPMCLK low
MIN
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
MAX UNIT
ns ns ns
1
2 3
Figure 10-35. HyperLink Station Management Clock Timing
4 5 4 5
HYPTX<xx>CLK
HYPTX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 10-36. HyperLink Station Management Transmit Timing
6
7 6 7
HYPRX<xx>CLK
HYPRX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 10-37. HyperLink Station Management Receive Timing
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10.12 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the device and a UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550 asynchronous communications element which, in turn, is a functional upgrade of the
TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the
UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the SoC of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to
16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the SoC to be sent to the peripheral device. The SoC can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on
UART, see the KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User's Guide
( SPRUGP1 ).
Table 10-41. UART Timing Requirements
(see
and
NO.
5
6
6
6
4
5
8 tw(RXSTART) tw(RXH) tw(RXL) tw(RXSTOP1) tw(RXSTOP15) tw(RXSTOP2) td(CTSL-TX)
Receive Timing
Pulse width, receive start bit
Pulse width, receive data/parity bit high
Pulse width, receive data/parity bit low
Pulse width, receive stop bit 1
Pulse width, receive stop bit 1.5
Pulse width, receive stop bit 2
Autoflow Timing Requirements
Delay time, CTS asserted to START bit transmit
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
MIN
0.96U
(1)
0.96U
0.96U
0.96U
0.96U
0.96U
P
(2)
MAX UNIT
1.05U
1.05U
1.05U
1.05U
1.05U
1.05U
5P ns ns ns ns ns ns ns
RXD
Stop/Idle
4
Start Bit 0
5
Bit 1 Bit N-1 Bit N
5
Parity
6
Stop Idle Start
Figure 10-38. UART Receive Timing Waveform
8
TXD Bit N-1 Bit N Stop Start Bit 0
CTS
Figure 10-39. UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
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Table 10-42. UART Switching Characteristics
(see
and
NO.
2
3
1
2
3
3
7 tw(TXSTART) tw(TXH) tw(TXL) tw(TXSTOP1) tw(TXSTOP15) tw(TXSTOP2) td(RX-RTSH)
PARAMETER
Transmit Timing
Pulse width, transmit start bit
Pulse width, transmit data/parity bit high
Pulse width, transmit data/parity bit low
Pulse width, transmit stop bit 1
Pulse width, transmit stop bit 1.5
Pulse width, transmit stop bit 2
Autoflow Timing Requirements
Delay time, STOP bit received to RTS deasserted
MIN
P
(2)
MAX UNIT
U
(1)
- 2
U - 2
U - 2
U - 2
U + 2
U + 2
U + 2
U + 2
1.5 * (U - 2) 1.5 * ('U + 2)
2 * (U - 2) 2 * ('U + 2)
5P ns ns ns ns ns ns ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
TXD Stop/Idle
1
Start Bit 0
2
Bit 1 Bit N-1 Bit N
2
Parity
3
Stop Idle Start
Figure 10-40. UART Transmit Timing Waveform
RXD Bit N-1 Bit N
7
Stop Start
CTS
Figure 10-41. UART RTS (Request-to-Send Output) – Autoflow Timing Waveform
10.13 PCIe Peripheral
The two-lane PCI express (PCIe) module on AM5K2E0x provides an interface between the device and other PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed data transfer at rates up to 5.0 Gbps per lane on the serial links. For more information, see the KeyStone
Architecture Peripheral Component Interconnect Express (PCIe) User's Guide ( SPRUGS6 ).
10.14 Packet Accelerator
The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for
Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as UDP ports. It maintains 8k multiple-in, multiple-out hardware queues and also provides checksum capability as well as some QoS capabilities. The PA enables a single IP address to be used for a multicore device and can process up to 1.5 Mpps. The Packet Accelerator is coupled with the Network
Coprocessor. For more information, see the KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E
and K2L Devices User's Guide ( SPRUHZ2 ).
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10.15 Security Accelerator
The Security Accelerator (SA) provides wire-speed processing on 1 Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air interface security protocols. It functions on the packet level with the packet and the associated security context being one of the above three types. The Security Accelerator is coupled with the Network Coprocessor, and receives the packet descriptor containing the security context in the buffer descriptor and the data to be encrypted/decrypted in the linked buffer descriptor. For more information, see the KeyStone II Architecture Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide
( SPRUHZ1 ).
10.16 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
The gigabit Ethernet (GbE) switch subsystem provides an efficient interface between the device and the networked community.
The Ethernet Media Access Controller (EMAC) supports 10Base-T
(10 Mbits/second), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with the Network Coprocessor. For more information, see the Gigabit Ethernet
(GbE) Switch Subsystem (1 GB) User's Guide ( SPRUGV9 ).
An address range is assigned to the AM5K2E0x. Each individual device has a 48-bit MAC address and consumes only one unique MAC address out of the range. There are two registers to hold these values,
MACID1[31:0] (32 bits) and MACID2[15:0] (16 bits) . The bits of these registers are defined as follows:
Figure 10-42. MACID1 Register (MMR Address 0x02620110)
31
MACID
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
0
Bit
31-0
Field
MAC ID
Table 10-43. MACID1 Register Field Descriptions
Description
MAC ID. Lower 32 bits.
Figure 10-43. MACID2 Register (MMR Address 0x02620114)
18 31 24
CRC
R+,cccc cccc
LEGEND: R = Read only; -x = value is indeterminate
23
Reserved
R,+rr rrrr
17
FLOW
R,+z
16
BCAST
R,+y
15 0
MACID
R,+xxxx xxxx xxxx xxxx
Bit Field
31-24 Reserved
23-18 Reserved
17 FLOW
16
15-0
BCAST
MAC ID
Table 10-44. MACID2 Register Field Descriptions
Description
Variable
000000
MAC Flow Control
• 0 = Off
• 1 = On
Default m/b-cast reception
• 0 = Broadcast
• 1 = Disabled
MAC ID. Upper 16 bits.
228
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There is a central processor time synchronization (CPTS) submodule in the Ethernet switch module that can be used for time synchronization. Programming this register selects the clock source for the
CPTS_RCLK. See the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide ( SPRUGV9 ) for the register address and other details about the time synchronization submodule.
The register
CPTS_RFTCLK_SEL for reference clock selection of the time synchronization submodule is shown in
.
CPTS also allows 8 HW signal inputs for timestamping. Two of these signals are connected to
TSPUSHEVT0 and TSPUSHEVT1. The other 6 are connected to internal SyncE and timer signals. See
for interconnectivity. Regarding the SyncE signal, see
for more details on how to control this input. Furthermore, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's
Guide ( SPRUGV9 ) for details on how to enable HW timestamping on CPTS.
Table 10-45. CPTS Hardware Push Events
6
7
8
2
3
4
5
EVENT NUMBER
1
CONNECTION
syncE
XGE sync
Tspushevt1
Tspushevt0
Timi1
Timi0
Reserved
Reserved
Figure 10-44. RFTCLK Select Register (CPTS_RFTCLK_SEL)
4 3 31
Reserved
R - 0
Legend: R = Read only; -x, value is indeterminate
CPTS_RFTCLK_SEL
RW - 0
0
Bit
31-4
3-0
Table 10-46. RFTCLK Select Register Field Descriptions
Field
Reserved
Description
Reserved. Read as 0.
CPTS_RFTCLK_SE Reference clock select. This signal is used to control an external multiplexer that selects one of 8 clocks for
L time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the TS_CTL register.
• 0000 = SYSCLK2
• 0001 = SYSCLK3
• 0010 = TIMI0
• 0011 = TIMI1
• 0100 = TSIPCLKA
• 1000 = TSREFCLK
• 1100 = TSIPCLKB
• Others = Reserved
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10.17 SGMII/XFI Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the gigabit
Ethernet (GbE) and 10-gigabit Ethernet (10GbE) switch subsystems for correct operation. The module allows almost transparent operation of the MDIO interface, with very little attention from the SoC. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide ( SPRUGV9 ) and the
KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide ( SPRUHJ5 ).
Table 10-47. MDIO Timing Requirements
(see
)
4
5
2
3
NO.
1 tc(MDCLK) tw(MDCLKH)
Cycle time, MDCLK
Pulse duration, MDCLK high tw(MDCLKL) Pulse duration, MDCLK low tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high th(MDCLKH-MDIO) tt(MDCLK)
Hold time, MDIO data input valid after MDCLK high
Transition time, MDCLK
MIN
400
180
180
10
10
MAX
5
UNIT
ns ns ns ns ns ns
1
MDCLK
2 3
4 5
MDIO
(Input)
Figure 10-45. MDIO Input Timing
Table 10-48. MDIO Switching Characteristics
(see
)
7
8
NO.
6
PARAMETER
td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO data output valid th(MDCLKH-MDIO) Hold time, MDIO data output valid after MDCLK high td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO Hi-Z
1
MDCLK
7
6 8
7
MDIO
(Ouput)
Figure 10-46. MDIO Output Timing
MIN
10
10
10
MAX
300
300
UNIT
ns ns ns
230
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10.18 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
The 3-port Ten Gigabit Ethernet Switch Subsystem (different from the Network Coprocessor integrated switch) includes a standalone EMAC switch subsystem and a 2-lane SerDes macro. The 2-lane macro enables only 2 external ports. It does not include any packet acceleration or security acceleration engine.
10.18.1 10GbE Supported Features
The key features of the 10GbE module are listed below:
• 10 Gbps EMAC switch subsystem
– MDIO: Media-dependent input/output module
– SGMII Interface for 10/100/1000 and 10GBASE-KR for 10G
– Ethernet switch with wire-rate switching (only two external ports are supported by the SerDes)
– CPTS module that supports time-stamping for IEEE1588v2 with support for eight hardware push events and generation of compare output pulses
– Supports XFI electrical interface
• CPDMA
The CPDMA component provides CPPI 4.2 compatible functionality, and provides a 128-bit wide data path to the TeraNet, enabling:
• Support for 8 transmit channel and 16 receive channels
• Support for reset isolation option
For more information, see the KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide
( SPRUHJ5 ).
10.19 Timers
The timers can be used to time events, count events, generate pulses, interrupt the ARM CorePac and send synchronization events to the EDMA3 channel controller.
10.19.1 Timers Device-Specific Information
The AM5K2E0x device has up to twenty 64-bit timers in total, but only 12 timers are used in AM5K2E04 and 10 timers are used in AM5K2E02, of which Timer16 and Timer17 (AM5K2E02) and Timer16 through
Timer19 (AM5K2E04) are dedicated to each of the Cortex-A15 processor cores as a watchdog timer and can also be used as general-purpose timers. The Timer8 through Timer15 can be configured as generalpurpose timers only, with each timer programmed as a 64-bit timer or as two separate 32-bit timers.
When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses
(rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable period. When operating in 32-bit mode, the timer is split into two independent 32bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins,
TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again.
If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming the Reset Type Status Register (RSTYPE) (see
reset initiated can set by programming the Reset Configuration Register (RSTCFG) (see
). For more information, see the KeyStone Architecture Timer 64P User's Guide
SPRUGV5 .
10.19.2 Timers Electrical Timing
The tables and figures below describe the timing requirements and switching characteristics of the timers.
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Table 10-49. Timer Input Timing Requirements
(1)
(see
)
NO.
1
2 t w(TINPH) t w(TINPL)
Pulse duration, high
Pulse duration, low
(1) C = 1/SYSCLK1 clock frequency in ns
Table 10-50. Timer Output Switching Characteristics
(1)
(see
)
NO.
3
4 t w(TOUTH) t w(TOUTL)
Pulse duration, high
Pulse duration, low
(1) C = 1/SYSCLK1 clock frequency in ns.
PARAMETER
1 2
TIMIx
3 4
TIMOx
MIN
12C
12C
MIN
12C - 3
12C - 3
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MAX UNIT
ns ns
MAX UNIT
ns ns
Figure 10-47. Timer Timing
10.20 General-Purpose Input/Output (GPIO)
10.20.1 GPIO Device-Specific Information
The GPIO peripheral pins are used for general purpose input/output for the device. These pins are also used to configure the device at boot time.
For more detailed information on device/peripheral configuration and the AM5K2E0x device pin muxing, see
These GPIO pins can also be used to generate individual core interrupts (no support of bank interrupt) and EDMA events.
10.20.2 GPIO Peripheral Register Description
Hex Address Offsets
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x008C
Acronym
-
BINTEN
DIR
OUT_DATA
SET_DATA
CLR_DATA
IN_DATA
SET_RIS_TRIG
CLR_RIS_TRIG
SET_FAL_TRIG
-
CLR_FAL_TRIG
Table 10-51. GPIO Registers
Register Name
GPIO interrupt per bank enable register
Reserved
GPIO Direction Register
GPIO Output Data Register
GPIO Set Data Register
GPIO Clear Data Register
GPIO Input Data Register
GPIO Set Rising Edge Interrupt Register
GPIO Clear Rising Edge Interrupt Register
GPIO Set Falling Edge Interrupt Register
GPIO Clear Falling Edge Interrupt Register
Reserved
232
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Hex Address Offsets
0x0090 - 0x03FF -
Acronym
Table 10-51. GPIO Registers (continued)
Register Name
Reserved
10.20.3 GPIO Electrical Data/Timing
Table 10-52. GPIO Input Timing Requirements
(1)
(see
)
NO.
1
2 t w(GPOH) t w(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
(1) C = 1/SYSCLK1 clock frequency in ns
MIN
12C
12C
Table 10-53. GPIO Output Switching Characteristics
(1)
(see
)
NO.
PARAMETER
3
4 t w(GPOH) t w(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
(1) C = 1/SYSCLK1 clock frequency in ns
MIN
36C - 8
36C - 8
1 2
GPIx
3 4
GPOx
MAX UNIT
ns ns
MAX UNIT
ns ns
Figure 10-48. GPIO Timing
10.21 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the
SoC. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modifywrite sequence is not broken. The Semaphore module has unique interrupts to each of the CorePacs to identify when that CorePac has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports three masters and contains 64 semaphores that can be shared within the system.
There are two methods of accessing a semaphore resource:
• Direct Access: A CorePac directly accesses a semaphore resource. If free, the semaphore is granted.
If not free, the semaphore is not granted.
• Indirect Access: A CorePac indirectly accesses a semaphore resource by writing to it. Once the resource is free, an interrupt notifies the CorePac that the resource is available.
10.22 Universal Serial Bus 3.0 (USB 3.0)
The device includes a USB 3.0 controller providing the following capabilities:
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• Support of USB 3.0 peripheral (or device) mode at the following speeds:
– Super Speed (SS) (5 Gbps)
– High Speed (HS) (480 Mbps)
– Full Speed (FS) (12 Mbps)
• Support of USB 3.0 host mode at the following speeds:
– Super Speed (SS) (5 Gbps)
– High Speed (HS) (480 Mbps)
– Full Speed (FS) (12 Mbps)
– Low Speed (LS) (1.5 Mbps)
• Integrated DMA controller with extensible Host Controller Interface (xHCI) support
• Support for 14 transmit and 14 receive endpoints plus control EP0
For more information, see the KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide
( SPRUHJ7 ).
10.23 TSIP Peripheral
The Telecom Serial Interface Port (TSIP) module provides a glueless interface to common telecom serial data streams. For more information, see the KeyStone Architecture Telecom Serial Interface Port (TSIP)
User Guide ( SPRUGY4 ).
10.23.1 TSIP Electrical Data/Timing
Table 10-54. Timing Requirements for TSIP 2x Mode
(1)
(see
)
8
9
10
5
6
7
3
4
NO.
1
2 t c
(CLK) t w
(CLKL) t w
(CLKH) t t
(CLK) t su
(FS-CLK) t h
(CLK-FS) t su
(TR-CLK) t h
(CLK-TR) t d
(CLKL-TX) t dis
(CLKH-TXZ)
Cycle time, CLK rising edge to next CLK rising edge
Pulse duration, CLK low
Pulse duration, CLK high
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
Disable time, CLK low to TX Hi-Z
MIN
61
(2)
0.4×t c
(CLK)
0.4×t c
(CLK)
5
1
2
5
5
5
MAX
2
12
10
(1) Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 1b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.
ns ns ns ns ns ns
UNIT
ns ns ns ns
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1 2 3
CLKA/B
5
6
FSA/B
TR[n]
ts127-3 ts127-2 ts127-1
8
7
ts127-0
9
ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0
TX[n]
ts127-3 ts127-2 ts127-1 ts127-0 ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0
A.
Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1 and a XMTDATD=1
Figure 10-49. TSIP 2x Timing Diagram
(A)
Table 10-55. Timing Requirements for TSIP 1x Mode
(1)
(see
)
18
19
20
15
16
17
NO.
11
12
13
14 t c
(CLK) t w
(CLKL) t w
(CLKH) t t
(CLK) t su
(FS-CLK) t h
(CLK-FS) t su
(TR-CLK) t h
(CLK-TR) t d
(CLKL-TX) t dis
(CLKH-TXZ)
Cycle time, CLK rising edge to next CLK rising edge
Pulse duration, CLK low
Pulse duration, CLK high
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
Disable time, CLK low to TX Hi-Z
MIN
122.1
(2)
0.4×t c
(CLK)
0.4×t c
(CLK)
5
1
2
5
5
5
MAX
2
12
10
(1) Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.
ns ns ns ns ns ns
UNIT
ns ns ns ns
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11 12 13
CLKA/B
16
15
FSA/B
TR[n]
ts127-3 ts127-2 ts127-1 ts127-0
17
18
ts000-7
19
ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0
TX[n]
ts127-3 ts127-2 ts127-1 ts127-0 ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0
A.
Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.
Figure 10-50. TSIP 1x Timing Diagram
(A)
10.24 Universal Subscriber Identity Module (USIM)
The AM5K2E0x is equipped with a Universal Subscriber Identity Module (USIM) for user authentication.
The USIM is compatible with ISO, ETSI/GSM, and 3GPP standards.
The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details.
10.25 EMIF16 Peripheral
The EMIF16 module provides an interface between the device and external memories such as NAND and
NOR flash. For more information, see the KeyStone Architecture External Memory Interface (EMIF16)
User's Guide ( SPRUGZ3 ).
10.25.1 EMIF16 Electrical Data/Timing
Table 10-56. EMIF16 Asynchronous Memory Timing Requirements
(1)
(see
through
NO.
2
28
14
3
3
4
5
4
5
6 t w
(WAIT) t d
(WAIT-WEH) t d
(WAIT-OEH) t
C
(CEL) t
C
(CEL) t osu
(CEL-OEL) t oh
(OEH-CEH) t osu
(CEL-OEL) t oh
(OEH-CEH) t osu
(BAV-OEL)
General Timing
Pulse duration, WAIT assertion and deassertion minimum time
Setup time, WAIT asserted before WE high
Setup time, WAIT asserted before OE high
Read Timing
EMIF read cycle time when ew = 0, meaning not in extended wait mode
EMIF read cycle time when ew =1, meaning extended wait mode enabled
Output setup time from CE low to OE low. SS = 0, not in select strobe mode
Output hold time from OE high to CE high. SS = 0, not in select strobe mode
Output setup time from CE low to OE low in select strobe mode, SS =
1
Output hold time from OE high to CE high in select strobe mode, SS =
1
Output setup time from BA valid to OE low
MIN
2E
4E + 3
4E + 3
(RS+RST+RH+3) (RS+RST+RH+3)
*E-3 *E+3
(RS+RST+RH+3) (RS+RST+RH+3)
*E-3 *E+3
(RS+1) * E - 3
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E - 3
(RS+1) * E - 3
MAX
(RS+1) * E + 3
(RH+1) * E + 3
(RS+1) * E + 3
(RH+1) * E + 3
(RS+1) * E + 3
UNIT
ns ns ns ns ns ns ns ns ns ns
(1) E = 1/(SYSCLK1/6)
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Table 10-56. EMIF16 Asynchronous Memory Timing Requirements
(continued)
24
26
27
25
22
23
24
18
19
20
21
(see
through
9
10
10
11
NO.
7
8
12
13
15
15
16
17
16
17 t oh
(OEH-BAIV) t osu
(AV-OEL) t oh
(OEH-AIV) t w
(OEL) t w
(OEL) t d
(WAITH-OEH) t su
(D-OEH) t h
(OEH-D) t c
(CEL) t c
(CEL) t osu
CEL-WEL) t oh
(WEH-CEH) t osu
CEL-WEL) t oh
(WEH-CEH) t osu
(RNW-WEL) t oh
(WEH-RNW) t osu
(BAV-WEL) t oh
(WEH-BAIV) t osu
(AV-WEL) t oh
(WEH-AIV) t w
(WEL) t w
(WEL) t osu
(DV-WEL) t oh
(WEH-DIV) t d
(WAITH-WEH)
Output hold time from OE high to BA invalid
Output setup time from A valid to OE low
Output hold time from OE high to A invalid
OE active time low, when ew = 0. Extended wait mode is disabled.
OE active time low, when ew = 1. Extended wait mode is enabled.
Delay time from WAIT deasserted to OE# high
Input setup time from D valid to OE high
Input hold time from OE high to D invalid
Write Timing
EMIF write cycle time when ew = 0, meaning not in extended wait mode
EMIF write cycle time when ew =1., meaning extended wait mode is enabled
Output setup time from CE low to WE low. SS = 0, not in select strobe mode
Output hold time from WE high to CE high. SS = 0, not in select strobe mode
Output setup time from CE low to WE low in select strobe mode, SS =
1
Output hold time from WE high to CE high in select strobe mode, SS =
1
Output setup time from RNW valid to WE low
Output hold time from WE high to RNW invalid
Output setup time from BA valid to WE low
Output hold time from WE high to BA invalid
Output setup time from A valid to WE low
Output hold time from WE high to A invalid
WE active time low, when ew = 0. Extended wait mode is disabled.
WE active time low, when ew = 1. Extended wait mode is enabled.
Output setup time from D valid to WE low
Output hold time from WE high to D invalid
Delay time from WAIT deasserted to WE# high
MIN
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E - 3 (RH+1) * E + 3
(RST+1) * E - 3 (RST+1) * E + 3
(RST+1) * E - 3 (RST+1) * E + 3
4E + 3
3
0.5
MAX
(RH+1) * E + 3
(RS+1) * E + 3
(WS+WST+WH+ (WS+WST+WH+
3)*E-3 3)*E+3
(WS+WST+WH+ (WS+WST+WH+
3)*E-3 3)*E+3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WST+1) * E - 3
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
4E + 3
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3
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EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
4
6
8
5
7
9
10
EM_OE
12
13
EM_D[15:0]
EM_WE
Figure 10-51. EMIF16 Asynchronous Memory Read Timing Diagram
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15
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
EM_WE
16
18
20
22
26
24
17
19
21
23
27
EM_D[15:0]
EM_OE
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_OE
Figure 10-52. EMIF16 Asynchronous Memory Write Timing Diagram
Setup Strobe Extended Due to EM_WAIT Strobe Hold
EM_WAIT
2
Asserted
14
2
Deasserted
11
Figure 10-53. EMIF16 EM_WAIT Read Timing Diagram
Setup Strobe Extended Due to EM_WAIT Strobe Hold
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
EM_WAIT
2
Asserted
28
2
Deasserted
25
Figure 10-54. EMIF16 EM_WAIT Write Timing Diagram
10.26 Emulation Features and Capability
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The debug capabilities of KeyStone II devices include the Debug subsystem module (DEBUGSS). The
DEBUGSS module contains the ICEPick module which handles the external JTAG Test Access Port
(TAP) and multiple secondary TAPs for the various processing cores of the device. It also provides Debug
Access Port (DAP) for system wide memory access from debugger, Cross triggering, System trace,
Peripheral suspend generation, Debug port (EMUx) pin management etc. The DEBUGSS module works in conjunction with the debug capability integrated in the processing cores to provide a comprehensive hardware platform for a rich debug and development experience.
10.26.1 Chip Level Features
• Support for 1149.1(JTAG and Boundary scan) and 1149.6 (Boundary scan extensions).
• Trace sources to DEBUG SubSystem System Trace Module (DEBUGSS STM)
– Provides a way for hardware instrumentation and software messaging to supplement the processor core trace mechanisms.
– Hardware instrumentation support of CPTracers to support logging of bus transactions for critical endpoints
– Software messaging/instrumentation support for SoC and QMSS PDSP cores through DEBUGSS
STM.
• Trace Sinks
– Support for trace export (from all processor cores and DEBUGSS STM) through emulation pins.
Concurrent trace of ARM and STM traces via EMU pins is possible.
– Support for 32KB DEBUGSS TBR (Trace Buffer and Router) to hold system trace. The data can be drained using EDMA to on-chip or DDR memory buffers. These intermediate buffers can subsequently be drained through the device high speed interfaces. The DEBUGSS TBR is dedicated to the DEBUGSS STM module. The trace draining interface used in KeyStone II for
DEBUGSS and ARMSS are based on the new CT-TBR.
• Cross triggering: Provides a way to propagate debug (trigger) events from one processor/subsystem/module to another
– Cross triggering between multiple devices via EMU0/EMU1 pins
– Cross triggering between multiple processing cores within the device like ARM Cores and nonprocessor entities like ARM STM (input only), CPTracers, CT-TBRs and DEBUGSS STM (input only)
• Synchronized starting and stopping of processing cores
– Global start of all ARM cores
– Global stopping of all ARM cores
• Emulation mode aware peripherals (suspend features and debug access features)
• Support system memory access via the DAP port (natively support 32-bit address, and it can support
36-bit address through configuration of MPAX inside MSMC). Debug access to any invalid memory location (reserved/clock-gated/power-down) does not cause system hang.
• Scan access to secondary TAPs of DEBUGSS is disabled in Secure devices by default. Security override sequence is supported (requires software override sequence) to enable debug in secure devices. In addition, Debug features of the ARM cores are blockable through the ARM debug authentication interface in secure devices.
• Support WIR (wait-in-reset) debug boot mode for Non-secure devices.
• Debug functionality survives all pin resets except power-on resets (POR/RESETFULL) and test reset
(TRST).
• PDSP Debug features like access/control through DAP, Halt mode debug and software instrumentation.
10.26.1.1 ARM Subsystem Features
• Support for invasive debug like halt mode debugging (breakpoint, watchpoints) and monitor mode debugging
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• Support for non-invasive debugging (program trace, performance monitoring)
• Support for A15 Performance Monitoring Unit (cycle counters)
• Support for per core CoreSight™ Program Trace Module (CS-PTM) with timing
• Support for an integrated CoreSight System Trace Module (CS-STM) for hardware event and software instrumentation
• A shared timestamp counter for all ARM cores and STM is integrated in ARMSS for trace data correlation
• Support for a 16KB Trace Buffer and Router (TBR) to hold PTM/STM trace. The trace data is copied by EDMA to external memory for draining by device high speed serial interfaces.
• Support for simultaneous draining of trace stream through EMUn pins and TBR (to achieve higher aggregate trace throughput)
• Support for debug authentication interface to disable debug accesses in secure devices
• Support for cross triggering between MPU cores, CS-STM and CT-TBR
• Support for debug through warm reset
10.26.2 ICEPick Module
The debugger is connected to the device through its external JTAG interface. The first level of debug interface seen by the debugger is connected to the ICEPick module embedded in the DEBUGSS. ICEPick is the chip-level TAP, responsible for providing access to the IEEE 1149.1 and IEEE1149.6 boundary scan capabilities of the device.
ICEPick manages the TAPs as well as the power/reset/clock controls for the logic associated with the
TAPs as well as the logic associated with the APB ports.
ICEPick provides the following debug capabilities:
• Debug connect logic for enabling or disabling most ICEPick instructions
• Dynamic TAP insertion
– Serially linking up to 32 TAP controllers
– Individually selecting one or more of the TAPS for scan without disrupting the instruction register
(IR) state of other TAPs
• Power, reset and clock management
– Provides the power and clock status of the domain to the debugger
– Provides debugger control of the power domain of a processor.
• Force the domain power and clocks on
• Prohibit the domain from being clock-gated or powered down
– Applies system reset
– Provides wait-in-reset (WIR) boot mode
– Provides global and local WIR release
– Provides global and local reset block
The ICEPick module implements a connect register, which must be configured with a predefined key to enable the full set of JTAG instructions. Once the debug connect key has been properly programmed,
ICEPick signals and subsystems emulation logic should be turned on.
10.26.2.1 ICEPick Dynamic Tap Insertion
To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP router to program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively choose which subsystem TAPs are accessible through the device-level debug interface. Each secondary
TAP can be dynamically included in or excluded from the scan path. From external JTAG interface point of view, secondary TAPS that are not selected appear not to exist.
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The CoreSight components are interfaced with ICEPick through the CS_DAP module. The CS_DAP is attached to the ICEPick secondary TAP and translates JTAG transactions into APBv3 transactions.
shows the ICEPick secondary taps in the system. For more details on the test related P1500
TAPs, see the DFTSS specification.
3
4
5
6
1
2
7
8
9..13
14
TAP # TYPE NAME
0 n/a n/a
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG Reserved
CS CS_DAP (APB-AP)
NA
4
CS_DAP (AHB-AP)
Table 10-57. ICEPick Debug Secondary TAPs
ACCESS IN
IR SCAN SECURE
LENGTH DEVICE
n/a No
No
No
DESCRIPTION
Reserved (This is an internal TAP and not exposed at the DEBUGSS boundary)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Spare ports for future expansion
ARM A15 Cores (This is an internal TAP and not exposed at the
DEBUGSS boundary)
PDSP Cores (This is an internal TAP and not exposed at the
DEBUGSS boundary)
For more information on ICEPick, see the KeyStone II Architecture Debug and Trace User’s Guide
( SPRUHM4 ).
10.27 Debug Port (EMUx)
The device also supports 34 emulation pins — EMU[33:0], which includes 19 dedicated EMU pins and 15 pins multiplexed with GPIO. These pins are shared by SoC STM trace, cross triggering, and debug boot modes as shown in
. The 34-pin dedicated emulation interface is also defined in the following table.
NOTE
Note that if EMU[1:0] signals are shared for cross-triggering purposes in the board level, they
SHOULD NOT be used for trace purposes.
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10.27.1 Concurrent Use of Debug Port
The following combinations are possible concurrently:
• Trigger 0/1
• Trigger 0/1 and STM Trace (up to 4 data pins)
• Trigger 0/1 and STM Trace (up to 4 data pins)
• Trigger 0/1 and STM Trace (1-4 data pins) and ARM Trace (27-24 data pins)
• STM Trace (1-4 data pins) and ARM Trace (29-26 data pins)
• Trigger 0/1 and ARM Trace (up to 29 data pins)
• ARM Trace (up to 32 data pins)
10.27.2 Master ID for HW and SW Messages
describes the master ID for the various hardware and software masters of the STM.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 10-58. MSTID Mapping for Hardware Instrumentation (CPTRACERS)
CPTRACER NAME
CPT_MSMCx_MST, where x =
0..3
CPT_MSMC4_MST
CPT_MSMCx_MST, where x =
5..7
CPT_DDR3_MST
CPT_L2_x_MST, where x = 0..7
CPT_TPCC0_4_MST
CPT_TPCC1_2_3_MST
CPT_INTC_MST
CPT_SM_MST
CPT_QM_CFG1_MST
CPT_QM_CFG2_MST
CPT_QM_M_MST
CPT_SPI_ROM_EMIF16_MST
CPT_CFG_MST
CLOCK
MSTID [7:0] DOMAIN
0x94-0x97 SYSCLK1/1
0xB1 SYSCLK1/1
0xAE - 0xB0 SYSCLK1/1
0x98 SYSCLK1/1
0x8C - 0x93 SYSCLK1/3
0xA4
0xA5
SYSCLK1/3
SYSCLK1/3
0xA6
0x99
0x9A
0xA0
0x9B
0xA7
0x9C
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SID[4:0]
0x0..3
0x4
0x5..7
DESCRIPTION
MSMC SRAM Bank 0 to MSMC SRAM Bank 3 monitors
MSMC SRAM Bank 4
MSMC SRAM Bank 5to MSMC SRAM Bank 7 monitors
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x8 MSMC DDR3 port monitor
0x9..0x10
Reserved
0x11
0x12
EDMA 0 and EDMA 4 CFG port monitor
EDMA 1, EDMA2 and EDMA3 CFG port monitor
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTC port monitor (for INTC 0/1/2 and GIC400)
Semaphore CFG port monitors
QMSS CFG1 port monitor
QMSS CFG2 port monitor
QM_M CFG/DMA port monitor
SPI ROM EMIF16 CFG port monitor
SCR_3P_B and SCR_6P_B CFG peripheral port monitors
Reserved
Reserved
Reserved
Reserved
Reserved
DDR 3B port monitor (on SCR 3C)
CORE NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x3
0x4
0x5
0x6
MSTID [7:0]
0x0
0x1
0x2
Table 10-59. MSTID Mapping for Software Messages
DESCRIPTION
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CORE NAME
Reserved
A15 Core0
A15 Core1
A15 Core2
A15 Core3
QMSS PDSPs
TSIP
Table 10-59. MSTID Mapping for Software Messages (continued)
MSTID [7:0]
0x7
0x8
0x9
0xA
0xB
0x46
0x80
DESCRIPTION
ARM Master IDs
ARM Master ID (AM5K2E04 only)
ARM Master ID(AM5K2E04 only)
ARM Master ID(AM5K2E04 only)
All QMSS PDSPs share the same master ID. Differentiating between the 8 PDSPs is done through the channel number used
TSIP Master ID
10.27.3 SoC Cross-Triggering Connection
The cross-trigger lines are shared by all the subsystems implementing cross-triggering. An MPU subsystem trigger event can therefore be propagated to any application subsystem or system trace component. The remote subsystem or system trace component can be programmed to be sensitive to the global SOC trigger lines to either:
• Generate a processor debug request
• Generate an interrupt request
• Start/Stop processor trace
• Start/Stop CBA transaction tracing through CPTracers
• Start external logic analyzer trace
• Stop external logic analyzer trace
NAME
Device-to-device trigger via EMU0/1 pins
MIPI-STM
CT-TBR
CS-TPIU
CP_Tracers
ARM
Table 10-60. Cross-Triggering Connection
SOURCE
TRIGGERS
SINK
TRIGGERS
Inside DEBUGSS
YES
NO
YES
NO
YES
YES
YES
YES
Outside DEBUGSS
YES
YES
YES
YES
COMMENTS
This is fixed (not affected by configuration)
Trigger input only for MIPI-STM in DebugSS
DEBUGSS CT-TBR
DEBUGSS CS-TPIU
ARM Cores, ARM CS-STM and ARM CT-
TBR
The following table describes the crosstrigger connection between various cross trigger sources and TI
XTRIG module.
Table 10-61. TI XTRIG Assignment
NAME
CPTracer 0..31 (The CPTracer number refers to the SID[4:0] as shown in
ASSIGNED XTRIG CHANNEL NUMBER
XTRIG 8 .. 39
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10.27.4 Peripherals-Related Debug Requirement
lists all the peripherals on this device, and the status of whether or not it supports emulation suspend or emulation request events.
The DEBUGSS supports upto 32 debug suspend sources (processor cores) and 64 debug suspend sinks
(peripherals). The assignment of processor cores is shown in and the assignment of peripherals is shown in
possible to select an individual core to be routed to the peripheral (For example: used in tightly coupled peripherals like timers), a logical AND of all cores (Global peripherals) or a logical OR of all cores by programming the DEBUGSS.DRM module.
The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral function is required or if the peripheral suspend should occur only after a particular completion point is reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the emulation suspend functionality.
PERIPHERAL
I
2
C_X, where X = 0/1/2
SPI_X, where X = 0/1/2
UART_X, where X = 0/1
USIM
STOP-
MODE
EDMA_x, where
X=0/1/2/3/4
QM_SS
N
CP_Tracers_X, where X =
0..32
MPU_X, where X = 0..11
CP_INTC
BOOT_CFG
SEC_MGR
PSC
PLL
TIMERx, x=0, 1..7, 8..19
Semaphore
GPIO
Y (CPDMA only)
N
N
N
N
N
N
N
Y
N
N
DDR3
MSMC
EMIF16
Hyperlink
PCIeSS 0..1
Reserved
NetCP (ethernet switch)
Y
N
Y
Y
N
N
N
N
N
Y
Table 10-62. Peripherals Emulation Support
EMULATION SUSPEND SUPPORT
REAL-TIME
MODE FREE BIT
Infrastructure Peripherals
N N
STOP BIT
N
EMULATION
REQUEST
SUPPORT
(cemudbg/emudbg)
Y
Y (CPDMA only)
N
Y
Y (CPDMA only)
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N N
Memory Controller Peripherals
N
N
N
Serial Interfaces
N Y
N
N
N
N
N
N
N
Y
Y
High Speed Serial Interfaces
N N
N N
Y
Y (CPDMA only)
N
Y
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
Y
Y
N
Y
Y
Y
N
Y
Y
Y
Y
N
Y
Y
Y
Y
N
N
N
Y
N
N
DEBUG
PERIPHERAL
ASSIGNMENT
NA
20
NA
NA
NA
NA
NA
NA
NA
0, 1..7, 8..19
NA
NA
NA
NA
NA
21/22/23
NA
24/25
28
26
27
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Table 10-62. Peripherals Emulation Support (continued)
EMULATION SUSPEND SUPPORT
PERIPHERAL
10GbE (ethernet switch)
(1)
USBSS
STOP-
MODE
Y
N
(1) 10 GbE supported by AM5K2E04 only.
REAL-TIME
MODE
N
N
FREE BIT
Y
N
STOP BIT
Y
N
EMULATION
REQUEST
SUPPORT
(cemudbg/emudbg)
N
N
DEBUG
PERIPHERAL
ASSIGNMENT
29
NA
Based on the above table the number of suspend interfaces in Keystone II devices is listed below.
Table 10-63. EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS)
INTERFACES
EMUSUSP Interfaces
EMUSUSP Realtime Interfaces
NUM_SUSPEND_PERIPHERALS
54
15
summarizes the DEBUG core assignment. Emulation suspend output of all the cores are synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.
Core #
8..11
12..29
30
31
Table 10-64. EMUSUSP Core Summary(for EMUSUSP handshake to DEBUGSS)
Assignment
ARM CorePac0-3
Reserved
Logical OR of Core #0..11
Logical AND of Core #0..11
10.27.5 Advanced Event Triggering (AET)
The device supports advanced event triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities:
• Hardware program breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.
• Data watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.
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For more information on the AET, see the following documents:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
( SPRA753 )
•
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report ( SPRA387 )
10.27.6 Trace
The device supports trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for trace advanced emulation, see the Emulation and
Trace Headers Technical Reference Manual ( SPRU655 ).
10.27.6.1 Trace Electrical Data/Timing
Table 10-65. Trace Switching Characteristics
2
2
3
(see
)
NO.
1
1
PARAMETER
t t w
(DPnH) w
(DPnL)
Pulse duration, DPn/EMUn high t w
(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
Pulse duration, DPn/EMUn low t w
(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh t sko
(DPn) Output skew time, time delay difference between DPn/EMUn pins configured as trace t skp
(DPn) Pulse skew, magnitude of difference between high-to-low (tphl) and low-tohigh (tplh) propagation delays.
t sldp_o
(DPn) Output slew rate DPn/EMUn
MIN
2.4
1.5
2.4
1.5
-1
3.3
MAX UNIT
ns ns ns ns
1 ns
600 ps
V/ns
Buffer
Inputs
Buffers DP[n] /
EMU[n] Pins
B
A
C
B
C
A
T
PLH
1
3
T
PLH
2
Figure 10-55. Trace Timing
10.27.7 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous test reset (TRST) and only the five baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SGMII) support the
AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
Specification (EAI/JESD8-5).
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10.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the AM5K2E0x device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device’s internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high, but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert
TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.
10.27.7.2 JTAG Electrical Data/Timing
Table 10-66. JTAG Test Port Timing Requirements
(see
)
NO.
4
4
3
3
1 t c(TCK)
1a tw(TCKH)
1b tw(TCKL)
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc) tsu(TDI-TCK) Input setup time, TDI valid to TCK high tsu(TMS-TCK) Input setup time, TMS valid to TCK high th(TCK-TDI) th(TCK-TMS)
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
Table 10-67. JTAG Test Port Switching Characteristics
(see
)
NO.
2 t d(TCKL-TDOV)
PARAMETER
Delay time, TCK low to TDO valid
MIN
23
9.2
9.2
2
2
10
10
MIN
MAX UNIT
ns ns ns ns ns ns ns
MAX UNIT
8.24
ns
1
1a 1b
TCK
2
TDO
4
3
TDI / TMS
Figure 10-56. JTAG Test-Port Timing
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11 Mechanical Data
11.1 Thermal Data
shows the thermal resistance characteristics for the PBGA - ABD 1089-pin mechanical package.
Table 11-1. Thermal Resistance Characteristics (PBGA Package) ABD
NO.
1 R
θ
JC
2 R θ
JB
Junction-to-case
Junction-to-board
°C/W
0.34
3.14
11.2 Packaging Information
The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document.
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PACKAGE OPTION ADDENDUM
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18-Feb-2016
PACKAGING INFORMATION
Orderable Device
AM5K2E02ABD25
AM5K2E02ABD4
AM5K2E02ABDA25
AM5K2E02ABDA4
AM5K2E02XABD25
Status
(1)
ACTIVE
ACTIVE
Package Type Package
Drawing
Pins Package
Qty
FCBGA
FCBGA
ABD
ABD
1089
1089
40
40
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
ABD 1089
ABD 1089
ABD 1089
40
40
40
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
Lead/Ball Finish
(6)
Call TI
SNAGCU
Call TI
SNAGCU
Call TI
MSL Peak Temp
(3)
Level-4-245C-72HR
Op Temp (°C)
0 to 85
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Call TI
0 to 85
-40 to 100
-40 to 100
0 to 85
Device Marking
(4/5)
AM5K2E02ABD
@2012 TI
AM5K2E02ABD
@2012 TI
1.4GHZ
AM5K2E02ABD
A1.25GHZ
AM5K2E02ABD
@2012 TI
A1.4GHZ
AM5K2E02XABD
AM5K2E04XABD25 ACTIVE FCBGA ABD 1089 40 Green (RoHS
& no Sb/Br)
Call TI Level-4-245C-72HR 0 to 85 AM5K2E04XABD
@2012 TI
AM5K2E04XABD4
AM5K2E04XABDA25
ACTIVE
ACTIVE
FCBGA
FCBGA
ABD 1089
ABD 1089
40
40
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SNAGCU
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
0 to 85
-40 to 100
AM5K2E04XABD
@2012 TI
1.4GHZ
AM5K2E04XABD
A1.25GHZ
AM5K2E04XABDA4 ACTIVE FCBGA ABD 1089 40 Green (RoHS
& no Sb/Br)
Call TI Level-4-245C-72HR -40 to 100 AM5K2E04XABD
@2012 TI
A1.4GHZ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2016
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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