Data Isolation for Loop-Powered Applications

Data Isolation for Loop-Powered Applications

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Data Isolation for Loop-Powered Applications

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Design Resources

TIDA-00245

MSP430FR5969

Design Folder

Product Folder

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Design Features

• Isolated Single-Wire Bidirectional Data

Transmission

• Bit Rates up to 1Mbps

• Low-Power Data Transmission

• System Shutdown Current 4μA at 3 V

• Integrated 64KB FRAM with 8MBps In-System

Writes

Featured Applications

• Factory Automation and Process Control

• Sensors and Field Transmitters

• Building Automation

• Field Actuators

• 4- to 20-mA Loop Process Control

• Sensor Management

• Data Logging

TX/

RX

MSP430FR5969

VCC VCC

TX/

RX

MSP430FR5969

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information.

All trademarks are the property of their respective owners.

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1

Introduction

1 Introduction

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Because ground potential differences higher than 100 V are common in industrial environments, some sensors (like thermocouple sensors) and signal conditioning circuitry must be galvanically isolated from ground. In isolated sensor transmitters, both the power supply and the data transmission have to be isolated. The data transmission can be either unidirectional or bidirectional. An isolated thermocouple sensor is shown in

Figure 1

. This design focuses on only the bidirectional communication between two microcontrollers (MSP430FR5969) across the isolation. For an isolated ultra-low power (ULP) design for

4- to 20-mA loop-powered transmitters, please see TIDA-00167 .

A bidirectional communication is needed in systems in which not only the isolated sensor side sends the data, but also the host provides, for example, configuration data to the isolated sensor side. The challenge of such a solution is first of all the limited size within sensor transmitters (industry standard) and, in case of a loop-powered system, the overall current consumption.

A single-wire interface is crucial to insure space and power consumption constrains. In the real application, one MCU (placed on the isolated side) takes care of the signal conditioning (linearization, calibration, data acquisition routine) while the second MCU (on the non-isolated side) takes care for the communication (in case of HART or more complex communications than just 4 to 20 mA) but as well of sending different configurations to the sensor side.

To show case the functionality, the hardware of the TIDA-00245 includes BoosterPack™ connectors on both sides of the isolation. BoosterPack plug-in modules allow the user to extend the functionality of the hardware and add features like wireless connectivity, capacitive touch, temperature sensing, displays, and much more. The design files include design considerations, block diagrams, schematics, bill of materials

(BOM), layer plots, Altium files, Gerber files, and MSP430 firmware.

TC Filters

LDO

4.5 V

3.3 V

MCU

Half Bridge LDO

4.7 V

LDO

3.3 V

MCU

DAC

Loop:

10

±

33 V

Isothermal block

CJ RTD

PT100

ADC

TIDA-00245

Figure 1. Isolated Thermocouple Sensor

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2 Key System Specifications

The key design requirements and features are as follows:

Table 1. Key System Specifications

PARAMETER

V

CC

T

A f

SYSTEM

Data rate

Supply voltage range

SPECIFICATION

Operating free-air temperature

Processor frequency (maximum MCLK frequency)

Active current for complete system

Both CPUs active at 8 MHz and bidirectional communication with 1 Mbaud at 3 V

Both CPUs active at 8 MHz and bidirectional communication with 1 Mbaud at 2.2 V

Both CPUs active at 8 MHz and unidirectional communication with 1 Mbaud at 3 V

Both CPUs active at 8 MHz and unidirectional communication with 1 Mbaud at 2.2 V

Standby current System standby and receive ready at 3 V

System standby and receive ready at 2.2 V

Shutdown current System shutdown current at 3 V

System shutdown current at 2.2 V

FRAM write speed

MIN

1.8

–40

Key System Specifications

TYP

1826

1772

2157

2090

44

33

4

3.4

8

MAX

3.6

85

16

1

µA

µA

µA

µA

µA

µA

µA

MBps

UNIT

V

°C

MHz

Mbps

µA

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3

System Description

3 System Description

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3.1

Transformer Coupled Interface

The TIDA-00245 uses galvanic isolation, which has an inherent life span advantage over an optocoupler isolator. Industrial devices are typically pressed into service for much longer periods of time than consumer electronics. Therefore, maintenance of effective isolation over a period of over 15 years is important. In systems requiring galvanic isolation between the transmitter and the receiver, the commonly used coupling element is a pulse transformer.

For the data transmission, the eUSCI_A (Enhanced Universal Serial Communication Interface) module and the Comparator_E (COMP_E) module of the MSP430FR5969 are used. The eUSCI_A module is configured for asynchronous UART mode. In asynchronous UART mode, the eUSCI_A module connect the MSP430FR5969 to an external system through two external pins, UCAxRXD and UCAxTXD. In UART mode, the eUSCI_A transmits and receives characters at a bit rate asynchronous to another device.

Timing for each character is based on the selected baud rate of the eUSCI_A module. The transmit and receive functions use the same baud-rate frequency. Alternatively, the automatic baud rate detection feature of the eUSCI_A module can be used. For automatic baud rate detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field.

The transformer passes only the AC components of the eUSCI_A square waveform resulting in an impulse train across the secondary winding. The COMP_E of the MSP430 then converts the impulse train into a square waveform. This square waveform is identical to the TX square waveform of the eUSCI_A module from the primary side and is fed into the UCAxRXD pin of the eUSCI_A module on the secondary side.

Because the transformer is a symmetrical device (particularly one with a 1:1 winding ratio), it is simple to reverse the data flow through it and have bidirectional communication. In general, the transformers developed for T1/E1 telecom applications are well suited as the interface element in an galvanically isolated industrial transmitter. A number of suggested off the shelf transformers are listed in

Table 2

.

MANUFACTURER

Wurth Elektronik

Wurth Elektronik

Coilcraft

Table 2. Transformers

P/N

750315105

750315155

S5394–CLB

MIN INDUCTANCE (µH)

400

400

400

ISOLATION

1500-V AC

1500-V AC

1500-V AC

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System Description

3.2

MSP430 ULP FRAM Platform

The MSP430 ULP ferroelectric RAM (FRAM) platform is used in the TIDA-00245 reference design. The

MSP430 combines uniquely embedded FRAM and a holistic ULP system architecture, allowing innovators to increase performance at lowered energy budgets. FRAM is much faster to write to than flash and has near infinite endurance, which means that in a remote sensor, data could be written more often for improved data accuracy, or it could collect data for longer. Due to the lack of a charge pump, FRAM enables lower average and peak power during writes. Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read current is included in the active mode current consumption numbers already.

The bitwise programmable memory can be used at the programmer’s convenience for data or program storage. It also does not require things like pre-erasure of segments before a write. Security is another area where FRAM can offer advantages. It is inherently more secure due to its makeup and de-layering is not effective. FRAM is also resistant to alpha radiation and SER effects. There are two main differences between FRAM and SRAM:

• FRAM is nonvolatile; that is, it retains contents on loss of power.

• The embedded FRAM on MSP430 devices can be accessed (read or write) at a maximum speed of 8

MHz.

In comparison to MSP430 flash, FRAM:

• Is very easy to use

• Requires no setup or preparation such as unlocking of control registers

• Is not segmented and each bit is individually erasable, writable, and addressable

• Does not require an erase before a write

• Allows low-power write accesses (does not require a charge pump)

• Can be written to across the full voltage range (1.8 to 3.6 V)

• Can be written to at speeds close to 8MBps (maximum flash write speed including the erase time is approximately 14 kBps)

• Writing to FRAM does not require additional power when compared to reading from FRAM. The FRAM read current is included in the active mode current consumption numbers already.

Table 3

summarizes the FRAM advantage versus other memory technologies.

SPECIFICATION

Write speed per word

Erase time

Bit-wise programmable

Write endurance

Nonvolatile

Internal write voltage

Table 3. FRAM Advantages

FRAM

125 ns

No pre-erase required

Yes

10

15 write per erase cycle

Yes

1.5 V

SRAM

< 125 ns

No pre-erase required

Yes

N/A

No

1.5 V

FLASH

85 µs

23 ms for 512 bytes

No

10

5 write per erase cycle

Yes

12 to 14 V (charge pump required)

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Block Diagram

4 Block Diagram

TX/RX

COUT

/C1

C2

TX

RX

eUSCI_A

+

±

VCC/2

MSP430FR5969

MUX

COUT

www.ti.com

RX/TX

C1

/COUT

C2

TX

RX

eUSCI_A

Vref0/

Vref1

+

±

MSP430FR5969

MUX

COUT

Figure 2. TIDA-00245 Block Diagram

4.1

Highlighted Products

For the low-power isolated bidirectional data transmission, the COMP_E module and the eUSCI module of the MSP430FR5969 have been used in this design. For more details regarding the functionality of these modules, please see MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family

User's Guide

[2] .

4.1.1

MSP430FR5969

The MSP430 ULP FRAM platform combines uniquely embedded FRAM and a holistic ULP system architecture, allowing innovators to increase performance at lowered energy budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash at much lower power.

Features:

• Embedded microcontroller

– 16-bit RISC architecture up to 16-MHz clock

– Wide supply voltage range (1.8 to 3.6 V; minimum supply voltage is restricted by SVS levels.)

• Optimized ULP modes

– Active mode: Approximately 100 μA/MHz

– Standby (LPM3 with VLO): 0.4

μA (typical)

– Real-time clock (LPM3.5): 0.25

μA (typical; RTC is clocked by a 3.7-pF crystal.)

– Shutdown (LPM4.5): 0.02

μA (typical)

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Block Diagram

• ULP FRAM

– Up to 64KB of nonvolatile memory

– ULP writes

– Fast write at 125 ns per word (64KB in 4 ms)

– Unified memory = Program + Data + Storage in one single space

– 10

15 write cycle endurance

– Radiation resistant and nonmagnetic

• Intelligent digital peripherals

– 32-bit hardware multiplier (MPY)

– Three-channel internal DMA

– RTC with calendar and alarm functions

– Five 16-bit timers with up to seven capture/compare registers each

– 16-Bit cyclic redundancy checker (CRC)

• High-performance analog

– 16-channel analog comparator

– 12-bit analog-to-digital converter (ADC) with internal reference and sample-and-hold and up to 16 external input channels

• Multifunction I/O ports

– All pins support capacitive touch capability with no need for external components

– Accessible bit-, byte-, and word-wise (in pairs)

– Edge-selectable wake from LPM on all ports

– Programmable pullup and pulldown on all ports

• Code security and encryption

– 128-bit or 256-bit AES security encryption and decryption coprocessor

– Random number seed for random number generation algorithms

• Enhanced serial communication

– eUSCI_A0 and eUSCI_A1 support

• UART with automatic baud-rate detection

• IrDA encode and decode

• SPI at rates up to 10 Mbps

– eUSCI_B0 supports

• I2C with multiple slave addressing

• SPI at rates up to 8Mbps

– Hardware UART and I

2

C bootstrap loader (BSL)

• Flexible clock system

– Fixed-frequency DCO with 10 selectable factory-trimmed frequencies

– Low-power low-frequency internal clock source (VLO)

– 32-kHz crystals (LFXT)

– High-frequency crystals (HFXT)

• Development tools and software

– Free professional development environments with EnergyTrace++™ technology development kit

(MSP-TS430RGZ48C)

For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and

MSP430FR69xx Family User's Guide

[2]

.

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Block Diagram

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P1.x, P2.x

2x8

P3.x, P4.x

2 x 8

PJ.x

1 x 8

LFXIN,

HFXIN

LFXOUT,

HFXOUT

DMA

Controller

3 Channel

CPUXV2 incl. 16

Registers

MCLK

Clock

System

Bus

Control

Logic

MAB

MAB

MDB

MDB

MPU

IP Encap

FRAM

64KB

48KB

32KB

RAM

2KB

1KB

MDB

MAB

ACLK

SMCLK

Comp_E

(up to 16 inputs)

ADC12_B

(up to 16 standard inputs, up to 8 differential inputs)

Power

Mgmt

LDO

SVS

Brownout

CRC16

REF_A

Voltage

Reference

Capacitive Touch IO 0/1

I/O Ports

P1, P2

2x8 I/Os

PA

1x16 I/Os

I/O Ports

P3 , P 4

2x8 I/Os

PB

1x16 I/Os

MPY32

AES256

Security

En cryption,

Decryption

(128, 256)

Watchdog

TA2

TA3

Timer_A

2 CC

Registers

(int. only)

I/O Port

PJ

1x8 I/Os

EEM

(S: 3 + 1)

EnergyTrace++

JTAG

Interface

Spy-Bi-Wire

TB0 TA0 TA1

Timer_B

7 CC

Registers

(int, ext)

Timer_A

3 CC

Registers

(int, ext)

Timer_A

3 CC

Registers

(int, ext) eUSCI_A0 eUSCI_A1

(UART,

IrDA,

SPI) eUSCI_B0

(I2C,

SPI)

LPM3.5 Domain

Figure 3. MSP430FR5969 Block Diagram

The MSP430 ULP FRAM portfolio consists of a diverse set of devices featuring FRAM, the ULP 16-bit

MSP430 CPU, and intelligent peripherals targeted for various applications. The COMP_E and the eUSCI_A modules are used in this application.

The COMP_E module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.

Features of COMP_E include:

• Inverting and non-inverting terminal input multiplexer

• Software-selectable RC filter for the comparator output

• Output provided to Timer_A capture input

• Software control of the port input buffer

• Interrupt capability

• Selectable reference voltage generator and voltage hysteresis generator

• Reference voltage input from shared reference

• ULP comparator mode

• Interrupt driven measurement system for low-power operation support

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Block Diagram

The enhanced universal serial communication interface A (eUSCI_A) supports multiple serial communication modes with one hardware module. In this design the UART mode is used. UART mode features include:

• 7-bit or 8-bit data with odd, even, or non-parity

• Independent transmit and receive shift registers

• Separate transmit and receive buffer registers

• LSB-first or MSB-first data transmit and receive

• Built-in idle-line and address-bit communication protocols for multiprocessor systems

• Receiver start-edge detection for auto wake up from LPMx modes (wake up from LPMx.5 is not supported)

• Programmable baud rate with modulation for fractional baud-rate support

• Status flags for error detection and suppression

• Status flags for address detection

• Independent interrupt capability for receive, transmit, start bit received, and transmit complete

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System Design Theory

5 System Design Theory

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5.1

Design Challenges

This design provides a method for transmitting digital data bidirectional over an isolation boundary from one MCU to another MCU using a single isolation component, a pulse transformer. The use of the transformers to cross the isolation boundary is typical in industrial applications due to their robustness, low-power consumption, and low cost. The challenge of such a solution is first of all the limited size within sensor transmitters (industry standard) and in case of a loop-powered system the overall current consumption.

5.2

Isolated Data Transmission

For the MCUs, the MSP430FR5969 has been chosen because of its ULP system architecture, integrated comparator, and integrated UART module, which is used for the isolated data transmission. The UART square waveform for the data transmission is generated with the eUSCI_A module. The transmitter’s DC component is blocked by a capacitor and the transformer passes only the AC components of the UART square waveform resulting in an impulse train across the secondary winding. The square waveform needs then to be recovered from the impulse train on the secondary winding. For restoring the signal, the internal

COMP_E of the MSP430FR5969 is used. The COMP_E has a feature to generate a hysteresis for the output signal, which is used to restore the square waveform from the impulse train. The port pin of the

MSP430 connected to the transmission circuit is P1.1. This pin is multiplexed with several functions like comparator output COUT and comparator input C1. When the MSP430 is configured as the transceiver, this pin is configured as COUT, and when the MSP430 is configured as the receiver this pin is configured as C1. Because the transformer is a symmetrical device (particularly one with 1:1 winding ratio) and the circuit is symmetrical as well, it is simple to reverse the data flow through it. The block diagram for the isolated data transmission can be seen in

Figure 2 .

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System Design Theory

5.2.1

Receiving Data

If the MSP430 is in receiving mode, the P1.1 pin connected to the transmission circuit is configured as comparator input C1. The comparator output COUT is mapped to a different pin P3.5, which is externally connected to the UART RX pin (see

Figure 4

).

TX

RX

C2

R2

R7

R8

R4

C1

/COUT

RX

eUSCI_A

Vref0/

Vref1

+

±

MSP430FR5969

MUX

COUT

Figure 4. Receiving Block Diagram

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System Design Theory

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The internal comparator of the MSP430 has two different reference voltages: Vref0 and Vref1. Vref1 is used while the output signal COUT of the comparator is 1, and Vref0 is used while COUT is 0. This allows the generation of a hysteresis without using external components. If the magnitude of the positive impulse exceeds the threshold Vref0 of the comparator, COUT goes high. This new COUT state will persist until an opposite polarity impulse appears across the secondary winding and exceeds the threshold Vref1 of the comparator. COUT will go low and this state will again persist until another positive pulse will occur. If no data is transmitted and no pulses occur, the voltage on the comparator input will be V

CC

/2. As Vref0 is above V

CC

/2 and Vref1 is below V

CC

/2 the comparator output COUT will keep its state until a pulse in the opposite direction occurs.

Figure 5

shows the output signal of the comparator depending on the pulses on the comparator input C1. The output signal of the comparator COUT on the receiver side looks again like the TX signal on the transmitter side. This COUT signal is then feed into the eUSCI_A module RX pin and the eUSCI_A module is used to decode the UART protocol.

Figure 5. Comparator Input and Output Signal

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System Design Theory

5.2.2

Transmitting Data

In this circuit, the default V

CC level on the connected MCU pin is V

CC

/2 when no data is transmitted. This is necessary to have the negative pulses not be going below 0 V as the I/O pins of the MSP430 do not accept negative voltage. But when voltage levels around V

CC

/2 are applied to digital CMOS gates, parasitic current can flow from V

CC to GND inside the pin. This parasitic current occurs if the input voltage is near the transition level of the gate. As the TX pin of the eUSCI module is a digital CMOS gate, it should not be directly connected to the transmission circuitry as parasitic current would flow from V

CC to

GND inside the pin. But on the P1.1/COUT/C1 pin, the port pin buffer can be disabled and this eliminates the parasitic current flow. Therefore, P1.1/COUT/C1 pin is connected to the transmission circuit. For transmitting, P1.1 is configured as comparator output COUT and the TX signal of the eUSCI_A module is connected to the comparator input pin C2 (see

Figure 6 ).The inverting input of the comparator is

connected to V

CC

/2 as a reference and the comparator output signal COUT then follows directly the TX signal on pin C2. To transmit data, the eUSCI_A module is used in UART mode. The transmitter’s DC component is blocked by a capacitor and only the AC components of the TX square waveform are passed to the secondary winding of the transformer.

RX

TX

COUT

/C1

C2

TX

eUSCI_A

+

±

VCC/2

MSP430FR5969

MUX

Figure 6. Transmitting Block Diagram

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System Design Theory

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When the MSP430FR5969 on one side of the isolation is configured for RX and the other MSP430FR5969 on the other side is configured for TX, data transmission in one direction can be done continuously without any delay (see

Figure 7 ). The turquoise signal is the transmitted data and the green signal is the received

signal on the other side of the isolation.

Figure 7. Transmitting Data

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System Design Theory

5.2.3

Bidirectional Data Communication

Because the used transformer is a symmetrical device (1:1 winding ratio) and the circuit is symmetrical as well, data transmission can be done in both directions. The only thing that needs to be considered is to change the configuration of the MSP430FR5969 pins from transmitting to receiving and vice versa. When changing from transmitting to receiving the capacitor C1 or respectively C2 has to be first discharged and the voltage needs to settle at V

CC

/2 for receiving. This takes less than 10 μs and then the transmission can start again in the other direction (see

Figure 8

). If the CPU is running with 8 MHz this equates to about 80

CPU cycles. So this time should not be a problem as after receiving the last byte it usually takes much more CPU cycles until the received byte has been processed and a new transmission gets started. This idle time needs only be adhered to when changing the communication direction. See the delay in

Figure 8 .

The blue signal is restored from the turquoise signal on one side of the isolation and the purple signal is restored from the green signal on the other side of the isolation. The turquoise and the green signals are the signals on the pins C1/COUT. The blue and the purple signals are the signals on the eUSCI_A RX input.

Figure 8. Bidirectional Data Communication

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System Design Theory

5.2.4

Automated Baud-Rate Detection and Break/Synch Sequence Feature

Automatic baud-rate (ABR) detection feature of the eUSCI module allows matching of baud rates between the different isolations sides. For ABR detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field. A break is detected when 11 or more continuous zeros (spaces) are received. If the length of the break exceeds 21 bit times, the break timeout error flag UCBTOE is set.

The synch field follows the break as shown in

Figure 9

.

Break Delimiter Synch www.ti.com

Figure 9. ABR Detection — Break/Synch Sequence

The synch field consists of the data 055h inside a byte field (see

Figure 10

). The synchronization is based on the time measurement between the first falling edge and the last falling edge of the pattern. The result of the measurement is transferred into the baud-rate control registers.

Synch

8 Bit Times

Start

Bit

0 1 2 3 4 5 6 7

Stop

Bit

Figure 10. ABR Detection — Synch Field

The break field can be used to detect the beginning of a new frame. The UCDORM bit is used to control data reception in this mode. When UCDORM is set, all characters are received but not transferred into the eUSCI receive buffer UCA0RXBUF, and interrupts are not generated. When UCDORM is set, in UART mode with ABR detection, only the combination of a break and synch field sets the UCRXIFG. When a break/synch field is detected, the character following the break/synch field is transferred into UCA0RXBUF and the UCRXIFG interrupt flag is set. When a break/synch field is received, user software must reset

UCDORM to continue receiving data. If UCDORM remains set, only the character after the next reception of a break/synch field is received. This feature can make the communication really robust in noisy environments. In addition the MSP430FR5969 includes a hardware CRC module (CRC16). The CRC16 produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

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System Design Theory

Figure 11

shows a scope screenshot of the communication using the ABR Detection and Break/Synch

Sequence feature followed by one data byte.

Figure 11. ABR Detection — Break/Synch Sequence Plus One Data Byte

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Getting Started: Hardware

6 Getting Started: Hardware

6.1

Board Description

Figure 12

shows the different sections of the TIDA-00245 design.

www.ti.com

Isolation barrier

Primary board side

Boosterpack

Connectors

JTAG connector

J16

MSP430FR5969

J4

J15

Transformer

Secondary board side

J1

MSP430FR5969

J23

JTAG connector

Boosterpack

Connectors

J22

J11 J18

Figure 12. TIDA-00245 Board Description

6.2

Hardware Setup

Jumper J11 and jumper J18 can be used for external power supply. The current consumption can be measured for the primary side on jumper J16 and for the secondary side on jumper J23.

6.2.1

Power During Debugging

If an external power supply is used during debug, make sure pin 2 and pin 3 are connected on jumper J16 and respectively on jumper J22. If there is no external power connected and power from the MSP-FET

Debugger Interface should be used, make sure pin 1 and pin 2 are connected on jumper J16 and respectively on jumper J22.

6.2.2

Isolation

Jumper J4 and jumper J1 can be used to disconnect the two MSP430FR5969 from the isolation circuitry and the transformer on the board. Instead the jumpers can be used to connect different isolation circuits and transformers.

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7 Getting Started: Firmware

To download the software files for this reference design, please see the link at http://www.ti.com/tool/TIDA-00245 .

Getting Started: Firmware

7.1

Software Setup

1. Install Code Composer Studio™ (CCS) before connecting MSP-FET to PC. During CCS installation,

USB drivers are installed automatically. Make sure to use the latest CCS version, otherwise the USB drivers might not be able to recognize the MSP-FET.

2. Connect the MSP-FET to a USB port on the PC with the provided USB cable.

3. The following procedure applies to operation under Windows®:

(a) After connecting to the PC, the MSP-FET should be recognized automatically, as the USB device driver has been already installed together with the IDE.

(b) If the driver has not been installed yet, the Found New Hardware wizard starts. Follow the instructions and point the wizard to the driver files.

(c) The default location for CCS is c:\ti\ccsv6\ccs_base\emulation\drivers\msp430\USB_CDC.

4. After connecting to a PC, the MSP-FET performs a self-test. If the self-test passes successfully, the green LED stays on.

5. If an external power supply is used during debug, make sure pin 2 and pin 3 are connected on jumper

J16 and respectively on jumper J22. If there is no external power connected and power from the MSP-

FET Debugger Interface should be used, make sure pin 1 and pin 2 are connected on jumper J16 and respectively on jumper J22.

6. Connect the MSP-FET with the 14-conductor cable to one of the JTAG connectors of the TIDA-00245 board.

7. Import the CCS project (TIDA-00245) into CCS and download the firmware to the MSP430FR5969 on the TIDA-00245 board.

8. Connect the MSP-FET with the 14-conductor cable to the other JTAG connector of the TIDA-00245 board.

9. Download the firmware to the other MSP430FR5969 on the TIDA-00245 board.

7.2

Software Function Documentation

The file swif.c contains the functions for the data transmission.

void initCompE(void)

This function is called to configure the COMP_E

void config_USCIA0_UART(uint16_t div)

This function is called to configure the eUSCIA0 module in UART mode.

void sendByte(uint8_t x)

This function is called to send the break/synch field plus one byte. The parameter x is the byte to send.

The MSP430 stays in TX mode.

void sendByte_RX(uint8_t x)

This function is called to send the break/synch field plus one byte. After transmission is completed the

MSP430 is configured for receive again. The parameter x is the byte to send.

void prepareTX(void)

This function is called to prepare the MSP430 for TX mode.

void prepareRX(void)

This function is called to prepare the MSP430 for RX mode.

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19

Getting Started: Firmware

www.ti.com

7.3

Demo Software: Bidirectional Communication

The software files can be downloaded at http://www.ti.com/tool/TIDA-00245 . The CCS project TIDA-

00245_bidirectional is an example project for bidirectional communication.

Transmission is started on one side with the buttons S1 or S4. The value for the first transmitted byte is

0x00. When the byte has been received on the other side of the isolation, it is echoed back. The value is then incremented by one and sent again. If the value of the echoed back byte is not the same as the transmitted byte the red LED goes on. After transmitting 1 kB, the green LED toggles. The transmission can be stopped with button S1 or S4. The LEDs can be disabled with the buttons S2 and S3 or S5 and S6 for current measurement purposes.

7.4

Demo Software: Unidirectional Communication

The software files can be downloaded at http://www.ti.com/tool/TIDA-00245 . The CCS project TIDA-

00245_unidirectional is an example project for unidirectional communication.

Transmission is started on one side with button S1 or S4. The value for the first transmitted byte is 0x00.

The value is then incremented by one and sent again. The receiver checks the received byte and increments the counter. If the value of the received byte is not equal to the counter the red LED goes on.

After transmitting 1 kB, the green LED toggles. The transmission can be stopped with button S1 or S4.

The LEDs can be disabled with the buttons S2 and S3 or S5 and S6 for current measurement purposes.

20

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8 Test Results

Test Results

The current can be measured on jumper J16 and on the other side of the isolation on jumper J23.

Table 4

shows the results for the shutdown and the standby current of the complete system.

Table 4. Shutdown and Standby Current

PARAMETER SPECIFICATION

Standby current

Shutdown current

System standby and receive ready at 3 V

System standby and receive ready at 2.2 V

System shutdown current at 3 V

System shutdown current at 2.2 V

TRANSMITTER

22

16.5

2

1.7

RECEIVER

22

16.5

2

1.7

COMPLETE

SYSTEM

44

33

4

3.4

UNIT

µA

µA

µA

µA

Figure 13

shows the typical dynamic current consumption of the complete system in unidirectional mode.

Both MSP430FR5969s are active and the CPU is running with 8 MHz. The communication is continuously running in one direction.

2200

2.2 V

3 V

2150

2100

2050

2000

1950

1900

1850

0 100 200 300 400 500 600

Data Rate (Kbps)

700 800 900 1000

D001

Figure 13. Total Supply Current in Unidirectional Mode

Figure 14

shows the typical dynamic current consumption of the complete system in bidirectional mode.

Both MSP430FR5969s are active and the CPU is running with 8 MHz. The communication is continuously running in both directions. One byte is sent and than echoed back from the other side of the isolation.

1850

2.2 V

3 V

1800

1750

1700

1650

1600

1550

0 100 200 300 400 500 600

Data Rate (Kbps)

700 800 900 1000

D002

Figure 14. Total Supply Current in Bidirectional Mode

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21

Design Files

9 Design Files

9.1

Schematics

To download the most recent schematics, see the design files at TIDA-00245 .

D1

Super Red

D2

Green

D3

Yellow

C7

10pF

C8

10pF

1

1

S2

1

S1

S3

2

2

2

GND_iso

R9

R10

R11

470

470

470

Y1

MS3V-T1R 32.768KHZ +/-20PPM 12.5PF

32.768kHz

P1.0_iso

ISO_RX/TX_iso

ISO_TX_iso

P1.3_iso

P1.4_SPI_CS_iso

P1.5_SPI_CS_iso

P1.6_UCB0SIMO_iso

P1.7_UCB0SOMI_iso

ISO_TX_iso

ISO_RX_iso

P2.2_UCB0CLK_iso

P2.3_iso

P2.4_iso

P2.5_UCA1TXD_iso

P2.6_UCA1RXD_iso

P2.7_iso

P3.0_iso

P3.1_A13_iso

P3.2_A14_iso

P3.3_A15_iso

P3.4_iso

ISO_RX_iso

P3.6_iso

P3.7_iso

P4.0_A8_iso

P4.1_A9_iso

TDO_iso

TDI_iso

TMS_iso

TCK_iso

12

13

14

15

45

46

42

43

16

17

18

19

33

34

35

8

4

7

27

5

6

28

29

30

24

25

26

39

40

20

21

38

10

11

31

3

9

1

2

32

U1

P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-

P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

P1.2/TA1.1/TA0CLK/COUT/A2/C2

P1.3/TA1.2/UCB0STE/A3/C3

P1.4/TB0.1/UCA0STE/A4/C4

P1.5/TB0.2/UCA0CLK/A5/C5

P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0

P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0

P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK

P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0

P2.2/TB0.2/UCB0CLK

P2.3/TA0.0/UCA1STE/A6/C10

P2.4/TA1.0/UCA1CLK/A7/C11

P2.5/TB0.0/UCA1TXD/UCA1SIMO

P2.6/TB0.1/UCA1RXD/UCA1SOMI

P2.7

P3.0/A12/C12

P3.1/A13/C13

P3.2/A14/C14

P3.3/A15/C15

P3.4/TB0.3/SMCLK

P3.5/TB0.4/COUT

P3.6/TB0.5

P3.7/TB0.6

P4.0/A8

P4.1/A9

P4.2/A10

P4.3/A11

P4.4/TB0.5

P4.5

P4.6

P4.7

PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6

PJ.1/TDI/TCLK/MCLK/SRSCG0/C7

PJ.2/TMS/ACLK/SROSCOFF/C8

PJ.3/TCK/SRCPUOFF/C9

PJ.4/LFXIN

PJ.5/LFXOUT

PJ.6/HFXIN

PJ.7/HFXOUT

MSP430FR5969IRGZ

GND_iso GND_iso

AVCC

DVCC

48

37

TEST/SBWTCK

22

RST/NMI/SBWTDIO

23

DVSS

AVSS

AVSS

AVSS

PAD

36

47

44

41

49

GND_iso

VCC_iso

C3

10µF

C4

0.1µF

TEST_iso

RST_iso

GND_iso

C5

10µF

C6

0.1µF

VCC_iso

P3.2_A14_iso

P2.6_UCA1RXD_iso

P2.5_UCA1TXD_iso

P2.3_iso

P3.1_A13_iso

P2.2_UCB0CLK_iso

P2.4_iso

P3.6_iso

P3.7_iso

11

13

15

17

19

5

7

9

1

3

J13

12

14

16

18

20

2

4

6

8

10

SSW-110-23-F-D

+5V_LP_iso

P3.3_A15_iso

P4.0_A8_iso

P4.1_A9_iso

GND_iso

P1.0_iso

P3.4_iso

11

13

15

17

19

5

7

9

1

3

J14

12

14

16

18

20

2

4

6

8

10

SSW-110-23-F-D

P1.3_iso

P3.0_iso

RST_iso

P1.6_UCB0SIMO_iso

P1.7_UCB0SOMI_iso

P1.5_SPI_CS_iso

P1.4_SPI_CS_iso

P2.7_iso

GND_iso

RST_iso

VCC_iso

47k

R12

47k

C9

2200pF

GND_iso

Figure 15. TIDA-00245 Schematic Page 1

TDO_iso

TDI_iso

TMS_iso

TCK_iso

GND_iso

SH-J15

J15

9

11

13

5

7

1

3

J9

6

8

2

4

10

12

14

VCC_TOOL_iso

VCC_TARGET_iso

TEST_iso

P2.5_UCA1TXD_iso

P2.6_UCA1RXD_iso

SBH11-PBPC-D07-RA-BK www.ti.com

SH-J16

J16

61300211121

VCC_iso

1

2

3

J11

TSW-103-08-G-S-RA

GND_iso

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D4

Super Red

D5

Green

D6

Yellow

GND GND

1

1

S5

1

S6

S4

2

2

2

GND

R13

R14

R15

470

470

470

C14

10pF

C15

10pF

Y2

MS3V-T1R 32.768KHZ +/-20PPM 12.5PF

32.768kHz

TDO

TDI

TMS

TCK

P1.0

ISO_RX/TX

ISO_TX

P1.3

P1.4_SPI_CS

P1.5_SPI_CS

P1.6_UCB0SIMO

P1.7_UCB0SOMI

ISO_TX

ISO_RX

P2.2_UCB0CLK

P2.3

P2.4

P2.5_UCA1TXD

P2.6_UCA1RXD

P2.7

P3.0

P3.1_A13

P3.2_A14

P3.3_A15

P3.4

ISO_RX

P3.6

P3.7

P4.0_A8

P4.1_A9

VCC

45

46

42

43

12

13

14

15

16

17

18

19

33

34

35

8

27

28

29

30

6

7

4

5

24

25

26

39

40

20

21

38

3

9

10

1

2

11

31

32

U2

P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-

P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

P1.2/TA1.1/TA0CLK/COUT/A2/C2

P1.3/TA1.2/UCB0STE/A3/C3

P1.4/TB0.1/UCA0STE/A4/C4

P1.5/TB0.2/UCA0CLK/A5/C5

P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0

P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0

P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK

P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0

P2.2/TB0.2/UCB0CLK

P2.3/TA0.0/UCA1STE/A6/C10

P2.4/TA1.0/UCA1CLK/A7/C11

P2.5/TB0.0/UCA1TXD/UCA1SIMO

P2.6/TB0.1/UCA1RXD/UCA1SOMI

P2.7

P3.0/A12/C12

P3.1/A13/C13

P3.2/A14/C14

P3.3/A15/C15

P3.4/TB0.3/SMCLK

P3.5/TB0.4/COUT

P3.6/TB0.5

P3.7/TB0.6

P4.0/A8

P4.1/A9

P4.2/A10

P4.3/A11

P4.4/TB0.5

P4.5

P4.6

P4.7

PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6

PJ.1/TDI/TCLK/MCLK/SRSCG0/C7

PJ.2/TMS/ACLK/SROSCOFF/C8

PJ.3/TCK/SRCPUOFF/C9

PJ.4/LFXIN

PJ.5/LFXOUT

PJ.6/HFXIN

PJ.7/HFXOUT

MSP430FR5969IRGZ

AVCC

DVCC

37

TEST/SBWTCK

22

RST/NMI/SBWTDIO

23

DVSS

AVSS

AVSS

AVSS

PAD

48

36

47

44

41

49

GND

C10

10µF

RST

C11

0.1µF

TEST

GND

C12

10µF

C13

0.1µF

VCC

P3.2_A14

P2.6_UCA1RXD

P2.5_UCA1TXD

P2.3

P3.1_A13

P2.2_UCB0CLK

P2.4

P3.6

P3.7

11

13

5

7

9

1

3

15

17

19

J20

12

14

16

18

20

2

4

6

8

10

SSW-110-23-F-D

P3.3_A15

P4.0_A8

P4.1_A9

+5V_LP

GND

Design Files

P1.0

P3.4

11

13

5

7

9

1

3

15

17

19

J21

12

14

16

18

20

2

4

6

8

10

SSW-110-23-F-D

P1.3

P3.0

RST

P1.6_UCB0SIMO

P1.7_UCB0SOMI

P1.5_SPI_CS

P1.4_SPI_CS

P2.7

GND

VCC

47k

R16

47k

RST

Figure 16. TIDA-00245 Schematic Page 2

GND

C16

2200pF

TDO

TDI

TMS

TCK

GND

SH-22

J22

SH-J23

J23

VCC

7

9

11

13

1

3

5

J10

2

4

6

8

10

12

14

VCC_TOOL

VCC_TARGET

TEST

P2.5_UCA1TXD

P2.6_UCA1RXD

SBH11-PBPC-D07-RA-BK

61300211121

GND

1

2

3

J18

TSW-103-08-G-S-RA

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Design Files

SH-J1

J1

ISO_RX/TX

61300211121

R3

1.0k

VCC

J7

1

61300111121

R1

1.0M

C1

220pF

R5

1.0M

J2

61300111121

R6

1.50k

GND

1

T1

6

2 4

3

750315155

J3

61300111121

R7

1.50k

J8

VCC_iso

1

61300111121

R2

1.0M

C2

R4

1.0k

220pF

R8

1.0M

J5

61300111121

GND GND_iso J6

61300111121

Figure 17. TIDA-00245 Schematic Page 3

GND_iso www.ti.com

SH-J4

J4

61300211121

ISO_RX/TX_iso

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9.2

Bill of Materials

To download the most recent bill of materials (BOM), see the design files at TIDA-00245 .

Design Files

Table 5. BOM

ITEM #

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

J8

DESIGNATOR

!PCB1

C1, C2

C3, C5, C10, C12

C4, C6, C11, C13

C7, C8, C14, C15

C9, C16

D1, D4

D2, D5

D3, D6

H1, H2, H3, H4

H5, H6, H7, H8

J1, J4, J16, J23

J2, J3, J5, J6, J7,

J9, J10

J11, J18

J13, J14, J20,

J21

J15, J22

R1, R2, R5, R8

R3, R4

R6, R7

QTY

1

2

4

4

4

2

2

2

2

4

4

4

6

2

2

4

2

4

2

2

VALUE

220pF

10uF

0.1uF

10pF

2200pF

Super

Red

Green

Yellow

1.0Meg

1.0k

1.50k

PARTNUMBER MANUFACTURER DESCRIPTION

PACKAGE

REFERENCE

TIDA-00245

C1608C0G1H221J

GRM21BR70J106KE7

6L

GRM155R71A104KA0

1D

GRM1555C1H100JA01

D

GRM155R70J222KA01

D

Any

TDK

MuRata

MuRata

MuRata

MuRata

Printed Circuit

Board

CAP, CERM, 220 pF, 50 V, +/- 5%,

C0G/NP0, 0603

CAP, CERM, 10

µF, 6.3 V, +/-

10%, X7R, 0805

CAP, CERM, 0.1

µF, 10 V, +/-

10%, X7R, 0402

CAP, CERM, 10 pF, 50 V, +/- 5%,

C0G/NP0, 0402

CAP, CERM,

2200 pF, 6.3 V,

+/- 10%, X7R,

0402

LED, Super Red,

SMD

0603

0805

0402

0402

0402

150060SS75000

150060VS75000

Wurth Elektronik eiSos

Wurth Elektronik eiSos

Wurth Elektronik eiSos

LED, Green, SMD

LED_0603

LED_0603

150060YS75000

NY PMS 440 0025 PH

1902C

61300311121

B&F Fastener Supply

Keystone

Wurth Elektronik eiSos

LED, Yellow,

SMD

Machine Screw,

Round, #4-40 x

1/4, Nylon, Philips panhead

Standoff, Hex,

0.5"L #4-40 Nylon

Header, 2.54 mm,

3x1, Gold, TH

LED_0603

Screw

Standoff

61300211121

61300111121

Wurth Elektronik eiSos

Wurth Elektronik eiSos

Header, 2.54 mm,

2x1, Gold, TH

Header, 2.54 mm,

1x1, Gold, TH

Header

SBH11-PBPC-D07-RASullins Connector (Shrouded), 2.54

BK Solutions mm, 7x2, Gold,

R/A, TH

Header,

2.54mm, 2x1,

TH

Header, 2.54

mm, 1x1, TH

Header

(Shrouded),

2.54 mm, 7x2,

R/A, TH

TSW-103-08-G-S-RA

SSW-110-23-F-D

Samtec

Samtec

Header, 100mil,

3x1, Gold, R/A,

TH

Connector,

Receptacle,

100mil, 10x2,

Gold plated, TH

3x1 R/A

Header

10x2

Receptacle

Header,

2.54mm, 3x1,

TH

CRCW06031M00JNEA

CRCW06031K00JNEA

CRCW06031K50FKEA

Vishay-Dale

Vishay-Dale

Vishay-Dale

RES, 1.0 M, 5%,

0.1 W, 0603

RES, 1.0 k, 5%,

0.1 W, 0603

RES, 1.50 k, 1%,

0.1 W, 0603

0603

0603

0603

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Copyright © 2015, Texas Instruments Incorporated

Design Files

www.ti.com

ITEM # DESIGNATOR QTY VALUE

21

22

23

24

25

26

27

28

R9, R10, R11,

R13, R14, R15

R12, R16

S1, S2, S3, S4,

S5, S6

SH-22, SH-J1,

SH-J4, SH-J15,

SH-J16, SH-J23

T1

U1, U2

Y1, Y2

FID1, FID2, FID3

6

2

6

6

1

2

2

0

470

47k

1x2

400 uH

Table 5. BOM (continued)

PARTNUMBER

CRCW0402470RJNED

CRCW040247K0JNED

434121025816

969102-0000-DA

750315155

MSP430FR5969IRGZ

MS3V-T1R 32.768KHZ

+/-20PPM 12.5PF

N/A

MANUFACTURER DESCRIPTION

PACKAGE

REFERENCE

Vishay-Dale

Vishay-Dale

RES, 470, 5%,

0.063 W, 0402

RES, 47 k, 5%,

0.063 W, 0402

Wurth Elektronik eiSos

3M

Switch, Tactile,

SPST, 12 V, SMD

Shunt, 100mil,

Gold plated,

Black

Transformer, 400 uH, SMT

Wurth Elektronik eiSos

Mixed Signal

Texas Instruments Microcontroller,

RGZ0048B

Micro Crystal AG

Crystal,

32.768kHz,

12.5pF, SMD

N/A

Fiducial mark.

There is nothing to buy or mount.

0402

0402

SMD, 6x3.9mm

Shunt

SMD, Body

8.26x6.6mm

RGZ0048B

1.4x1.4x5.0mm

SMD

N/A

26

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Design Files

9.3

PCB Layout Recommendations

The TIDA-00245 board has the form factor of a LaunchPad™. A LaunchPad is an easy-to-use development tool intended for beginners and experienced users alike for creating microcontroller-based applications. For the LaunchPad, there are BoosterPack plug-in boards available to expand the

LaunchPad's functionality. BoosterPack plug-in modules ( www.ti.com/boosterpack ) allow the user to add features like wireless connectivity, capacitive touch, temperature sensing, displays, and much more.

To create a BoosterPack for specific needs, use the resources at http://www.ti.com/ww/en/launchpad/byob.html

to create your BoosterPack design files, get support from the community, and take an idea from concept to PCB to product in a few easy steps.

9.3.1

Layout Prints

To download the most recent layer plots, see the design files at TIDA-00245 .

Figure 18. Top Overlay Figure 19. Top Solder Mask

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Design Files

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Figure 20. Top Layer Figure 21. MidLayer1

Figure 22. MidLayer2 Figure 23. Bottom Layer

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Figure 24. Bottom Solder Mask Figure 25. Bottom Overlay

Design Files

Figure 26. Drill Drawing Figure 27. Board Dimensions

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Design Files

9.4

Altium Project

To download the most recent Altium project files, see the design files at TIDA-00245 .

www.ti.com

Figure 28. Multilayer Composite Print

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9.5

Gerber Files

To download the most recent Gerber files, see the design files at TIDA-00245 .

Design Files

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Figure 29. Fabrication Drawing

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Design Files

9.6

Assembly Drawings

To download the most recent assembly drawings, see the design files at TIDA-00245 .

www.ti.com

Figure 30. Top Assembly Drawing Figure 31. Bottom Assembly Drawing

9.7

Software Files

To download the most recent software files, see the design files at TIDA-00245 .

10 References

1. Texas Instruments, MSP430FR59xx Mixed-Signal Microcontrollers ( SLAS704 )

2. Texas Instruments, MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family

User's Guide ( SLAU367 )

3. Texas Instruments, Maximizing Write Speed on the MSP430™ FRAM ( SLAA498 )

4. Texas Instruments, MSP430 FRAM Technology – How To and Best Practices ( SLAA628 )

11 About the Author

THOMAS SCHNEIDER is a systems applications engineer at Texas Instruments where he is responsible

for developing reference design solutions for the industrial segment. Thomas brings to this role his wide experience in TI microcontrollers, especially MSP430. Thomas earned his Dipl.-Ing. (Univ.) degree in electrical engineering from the Technical University Munich (TUM) in Munich, Germany.

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