Freescale Semiconductor MPC7447AEC Rev. 5, 01/2006 Technical Data MPC7447A RISC Microprocessor Hardware Specifications This document is primarily concerned with the PowerPC™ MPC7447A; however, unless otherwise noted, all information here also applies to the MPC7447. The MPC7447A is an implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the MPC7447A. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family Reference Manual. To locate any published updates for this document, refer to the Freescale website located at http://www.freescale.com. 1 Overview The MPC7447A is the fifth implementation of the fourth-generation (G4) microprocessors from Freescale. The MPC7447A implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7447A consists of a processor core and a 512-Kbyte L2. Figure 1 shows a block diagram of the MPC7447A. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. © Freescale Semiconductor, Inc., 2006. All rights reserved. Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Comparison with the MPC7447, MPC7445, and MPC7441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. Electrical and Thermal Characteristics . . . . . . . . . . . . 9 6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. System Design Information . . . . . . . . . . . . . . . . . . . 34 10. Document Revision History . . . . . . . . . . . . . . . . . . . 52 11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 52 2 Vector Integer Unit 2 L1 Service Queues Vector Integer Unit 1 +++ x÷ 32-Bit Integer Integer Integer Unit 122 Unit Unit (3) Integer Unit 2 32-Bit Reservation Reservation Reservation Station Station Station L2 Store Queue (L2SQ) Snoop Push/ Interventions L1 Castouts (4) Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status 32-Bit 16 Rename Buffers GPR File Vector Touch Queue FPR Issue (2-Entry/1-Issue) 512-Kbyte Unified L2 Cache Controller 128-Bit Dispatch Unit Instruction Queue (12-Word) Notes: The Castout Queue and Push Queue share resources such that they have a combined total of 6 entries. The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push. Cacheable Store Miss (1) 128-Bit Vector FPU L2 Prefetch (3) Instruction Fetch (2) L1 Load Miss (5) L1 Load Queue (LLQ) L1 Store Queue (LSQ) Memory Subsystem Vector Permute Unit 16 Rename Buffers VR File Reservation Stations (2) LR BHT (2048-Entry) VR Issue (4-Entry/2-Issue) CTR BTIC (128-Entry) Fetcher GPR Issue (6-Entry/3-Issue) Instruction Unit Branch Processing Unit Reservation Reservation Reservation Reservation Station Station Station Station Completes up to three instructions per clock Completion Unit 96-Bit (3 Instructions) Completion Queue (16-Entry) • Time Base Counter/Decrementer • Clock Multiplier • JTAG/COP Interface • Thermal/Power Management • Performance Monitor • Dynamic Frequency Switching (DFS) • Temperature Diode Additional Features 128-Entry ITLB Completed Stores L1 Push Finished Stores FPR File Tags 64-Bit FPSCR + x÷ FloatingPoint Unit Reservation Stations (2) 36-Bit Address Bus 64-Bit Data Bus Bus Accumulator Bus Store Queue Castout Queue (5) / Push Queue (6)1 System Bus Interface 64-Bit 32-Kbyte I Cache 32-Kbyte D Cache Tags 128-Bit (4 Instructions) 16 Rename Buffers PA Load Queue (11) Load Miss L1 Castout + (EA Calculation) Vector Touch Engine Load/Store Unit Reservation Stations (2-Entry) EA 128-Entry DTLB DBAT Array SRs (Original) Data MMU IBAT Array SRs (Shadow) Instruction MMU Overview Figure 1. MPC7447A Block Diagram MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor Features NOTE The MPC7447A is a footprint-compatible, drop-in replacement in an MPC7447 application if the core power supply is 1.3 V. 2 Features This section summarizes features of the MPC7447A implementation of the PowerPC architecture. Major features of the MPC7447A are as follows: • High-performance, superscalar microprocessor — Up to four instructions can be fetched from the instruction cache at a time. — Up to 12 instructions can be in the instruction queue (IQ). — Up to 16 instructions can be at some stage of execution simultaneously. — Single-cycle execution for most instructions — One instruction per clock cycle throughput for most instructions — Seven-stage pipeline control • Eleven independent execution units and three register files — Branch processing unit (BPU) features static and dynamic branch prediction – 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. – 2048-entry branch history table (BHT) with 2 bits per entry for four levels of prediction—not taken, strongly not taken, taken, and strongly taken – Up to three outstanding speculative branches – Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. – Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions — Four integer units (IUs) that share 32 GPRs for integer operands – Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. – IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. — Five-stage FPU and a 32-entry FPR file – Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Hardware support for denormalized numbers – Thirty-two 64-bit FPRs for single- or double-precision operands MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 3 Features • • • • — Four vector units and 32-entry vector register file (VRs) – Vector permute unit (VPU) – Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add instructions (for example, vaddsbs, vaddshs, and vaddsws). – Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm). – Vector floating-point unit (VFPU) — Three-stage load/store unit (LSU) – Supports integer, floating-point, and vector instruction load/store traffic – Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations – 3-cycle GPR and AltiVec load latency (byte, half word, word, vector) with 1-cycle throughput – 4-cycle FPR load latency (single, double) with 1-cycle throughput – No additional delay for misaligned access within double-word boundary – Dedicated adder calculates effective addresses (EAs) – Supports store gathering – Performs alignment, normalization, and precision conversion for floating-point data – Executes cache control and TLB instructions – Performs alignment, zero padding, and sign extension for integer data – Supports hits under misses (multiple outstanding misses) – Supports both big- and little-endian modes, including misaligned little-endian accesses Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: — Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2. — A maximum of three instructions can be dispatched to the issue queues per clock cycle. — Space must be available in the CQ for an instruction to dispatch. (This includes instructions that are assigned a space in the CQ but not in an issue queue.) Rename buffers — 16 GPR rename buffers — 16 FPR rename buffers — 16 VR rename buffers Dispatch unit — Decode/dispatch stage fully decodes each instruction Completion unit — The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 4 Freescale Semiconductor Features • • • — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch — Retires as many as three instructions per clock cycle Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set-associative instruction and data caches — Pseudo least-recently-used (PLRU) replacement algorithm — 32-byte (eight-word) L1 cache block — Physically indexed/physical tags — Cache write-back or write-through operation programmable on a per-page or per-block basis — Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle — Caches can be disabled in software. — Caches can be locked in software. — MESI data cache coherency maintained in hardware — Separate copy of data cache tags for efficient snooping — Parity support on cache and tags — No snooping of instruction cache except for icbi instruction — Data cache supports AltiVec LRU and transient instructions — Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding. Level 2 (L2) cache interface — On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache — Fully pipelined to provide 32 bytes per clock cycle to the L1 caches — A total 9-cycle load latency for an L1 data cache miss that hits in L2 — Cache write-back or write-through operation programmable on a per-page or per-block basis — 64-byte, two-sectored line size — Parity support on cache Separate memory management units (MMUs) for instructions and data — 52-bit virtual address, 32- or 36-bit physical address — Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBATs (eight each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs) – Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 5 Features • • • • • • – TLBs are hardware- or software-reloadable (that is, a page table search is performed in hardware or by system software on a TLB miss). Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits. — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs. — The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache. — As many as eight outstanding out-of-order cache misses are allowed between the L1 data cache and the L2 bus. — As many as 16 out-of-order transactions can be present on the MPX bus. — Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). — Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache — Separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the L1 data cache and L2 cache Multiprocessing support features include the following: — Hardware-enforced, MESI cache coherency protocols for data cache — Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations Power and thermal management — A new dynamic frequency switching (DFS) feature allows processor core frequency to be halved through software to reduce power consumption. — The following three power-saving modes are available to the system: – Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol. – Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. – Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed upon exiting the deep sleep state. — Instruction cache throttling provides control of instruction fetching to limit device temperature. — A new temperature diode can determine the temperature of the microprocessor. — Support for core voltage derating to further reduce power consumption Performance monitor can be used to help debug system designs and improve software efficiency. In-system testability and debugging features through JTAG boundary-scan capability Testability — LSSD scan design MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 6 Freescale Semiconductor Comparison with the MPC7447, MPC7445, and MPC7441 • 3 — IEEE 1149.1 JTAG interface — Array built-in self test (ABIST)—factory test only Reliability and serviceability — Parity checking on system bus — Parity checking on the L1 and L2 caches Comparison with the MPC7447, MPC7445, and MPC7441 Table 1 compares the key features of the MPC7447A with the key features of the earlier MPC7447, MPC7445, and MPC7441. All are based on the MPC7450 RISC microprocessor and are very similar architecturally. The MPC7447A is identical to the MPC7447 but includes the DFS and temperature diode features. Table 1. Microarchitecture Comparison Microarchitectural Specs MPC7447A MPC7447 MPC7445 MPC7441 Basic Pipeline Functions Logic inversions per cycle 18 Pipeline stages up to execute 5 Total pipeline stages (minimum) 7 Pipeline maximum instruction throughput 3 + branch Pipeline Resources Instruction buffer size 12 Completion buffer size 16 Renames (integer, float, vector) 16, 16, 16 Maximum Execution Throughput SFX 3 Vector 2 (any 2 of 4 units) Scalar floating-point 1 Out-of-Order Window Size in Execution Queues SFX integer units 1 entry × 3 queues Vector units In order, 4 queues Scalar floating-point unit In order Branch Processing Resources Prediction structures BTIC size, associativity BTIC, BHT, link stack 128-entry, 4-way MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 7 Comparison with the MPC7447, MPC7445, and MPC7441 Table 1. Microarchitecture Comparison (continued) Microarchitectural Specs MPC7447A MPC7447 BHT size MPC7445 MPC7441 2K-entry Link stack depth 8 Unresolved branches supported 3 Branch taken penalty (BTIC hit) 1 Minimum misprediction penalty 6 Execution Unit Timings (Latency-Throughput) Aligned load (integer, float, vector) 3-1, 4-1, 3-1 Misaligned load (integer, float, vector) 4-2, 5-2, 4-2 L1 miss, L2 hit latency 9 data/13 instruction SFX (aDd Sub, Shift, Rot, Cmp, logicals) 1-1 Integer multiply (32 × 8, 32 × 16, 32 × 32) 3-1, 3-1, 4-2 Scalar float 5-1 VSFX (vector simple) 1-1 VCFX (vector complex) 4-1 VFPU (vector float) 4-1 VPER (vector permute) 2-1 MMUs TLBs (instruction and data) 128-entry, 2-way Tablewalk mechanism Hardware + software Instruction BATs/data BATs 8/8 8/8 8/8 4/4 L1 I Cache/D Cache Features Size 32K/32K Associativity 8-way Locking granularity Way Parity on Instruction cache Word Parity on data cache Byte Number of data cache misses (load/store) 5/1 Data stream touch engines 4 streams On-Chip Cache Features Cache level Size/associativity Access width L2 512-Kbyte/8-way 256-Kbyte/8-way 256 bits MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 8 Freescale Semiconductor General Parameters Table 1. Microarchitecture Comparison (continued) Microarchitectural Specs MPC7447A MPC7447 Number of 32-byte sectors/line MPC7445 MPC7441 2 Parity Byte Thermal Control 4 Dynamic frequency switching (DFS) Yes No No No Thermal diode Yes No No No General Parameters The following list is a summary of the general parameters of the MPC7447A: Technology Die size Transistor count Logic design Packages Core power supply I/O power supply 5 0.13-μm CMOS, nine-layer metal 8.51 mm × 9.86 mm 48.6 million Fully-static Surface mount 360 ceramic ball grid array (HCTE) Surface mount RoHS-compliant 360 ceramic ball grid array (HCTE) Surface mount 360 ceramic land grid array (HCTE) 1.3 V ± 50 mV DC (nominal), or 1.2 V ± 50 mV DC (derated) 1.8 V ± 5% DC, or 2.5 V ± 5% DC Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7447A. 5.1 DC Electrical Characteristics The tables in this section describe the MPC7447A DC electrical characteristics. Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings1 Characteristic Symbol Maximum Value Core supply voltage VDD –0.3 to 1.60 V 2 PLL supply voltage AVDD –0.3 to 1.60 V 2 BVSEL = 0 OVDD –0.3 to 1.95 V 3, 4 BVSEL = HRESET or OVDD OVDD –0.3 to 2.7 V 3, 5 Processor bus Vin –0.3 to OVDD + 0.3 V 6, 7 JTAG signals Vin –0.3 to OVDD + 0.3 V — Processor bus supply voltage Input voltage Unit Notes MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 9 Electrical and Thermal Characteristics Table 2. Absolute Maximum Ratings1 (continued) Characteristic Symbol Maximum Value Tstg –55 to 150 Storage temperature range Unit Notes °C — Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VDD/AVDD must not exceed OVDD by more than 1.0 V during normal operation; this limit may be exceeded for a maximum of 20 ms during the power-on reset and power-down sequences. 3. Caution: OVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be exceeded for a maximum of 20 ms during the power-on reset and power-down sequences. 4. BVSEL must be set to 0, such that the bus is in 1.8-V mode. 5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode. 6. Caution: Vin must not exceed OVDD by more than 0.3 V at any time including during power-on reset. 7. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. Figure 2 shows the undershoot and overshoot voltage on the MPC7447A. OVDD + 20% OV DD + 5% OVDD VIH VIL GND GND – 0.3 V GND – 0.7 V Not to Exceed 10% of tSYSCLK Figure 2. Overshoot/Undershoot Voltage The MPC7447A provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7447A core voltage must always be provided at the nominal voltage (see Table 4) or at the supported derated voltage (see Section 5.3, “Voltage and Frequency Derating”). The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD power pins. Table 3 provides the input threshold voltage settings. Because these settings may change in future products, it is recommended that BVSEL be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 10 Freescale Semiconductor Electrical and Thermal Characteristics Table 3. Input Threshold Voltage Settings BVSEL Signal Processor Bus Input Threshold is Relative to: Notes 0 1.8 V 1, 2 ¬HRESET Not available 1 HRESET 2.5 V 1 1 2.5 V 1 Notes: 1. Caution: The input threshold selection must agree with the OV DD voltages supplied. See notes in Table 2. 2. If used, pull-down resistors should be less than 250 Ω. Table 4 provides the recommended operating conditions for the MPC7447A. NOTE Table 4 describes the nominal operating conditions of the device. For information regarding the operation of the device at supported derated core voltage conditions, see Section 5.3, “Voltage and Frequency Derating.” Table 4. Recommended Operating Conditions1 Recommended Value Characteristic Symbol Minimum Unit Notes Maximum Core supply voltage VDD 1.3 V ± 50 mV V 3 PLL supply voltage AVDD 1.3 V ± 50 mV V 2, 3 BVSEL = 0 OV DD 1.8 V ± 5% V BVSEL = HRESET or OVDD OV DD 2.5 V ± 5% Processor bus supply voltage Input voltage Processor bus Vin GND OV DD JTAG signals Vin GND OV DD Tj 0 105 Die-junction temperature V °C Notes: 1. These are the recommended and tested operating conditions. In addition, these devices also support voltage derating; see Section 5.3, “Voltage and Frequency Derating.” Proper device operation outside of these conditions and those specified in Section 5.3 is not guaranteed. 2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. 3. VDD and AVDD may be reduced in order to reduce power consumption if further maximum core frequency constraints are observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information. Table 5 provides the package thermal characteristics for the MPC7447A. Table 5. Package Thermal Characteristics1 Characteristic Symbol Value Unit Notes Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board RθJA 26 °C/W 2, 3 Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board RθJMA 19 °C/W 2, 4 Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board RθJMA 20 °C/W 2, 4 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 11 Electrical and Thermal Characteristics Table 5. Package Thermal Characteristics1 (continued) Characteristic Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board Symbol Value Unit Notes RθJMA 16 °C/W 2, 4 Junction-to-board thermal resistance RθJB 10 °C/W 5 Junction-to-case thermal resistance RθJC < 0.1 °C/W 6 Notes: 1. Refer to Section 9.8, “Thermal Management Information,” for details about thermal management. 2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 4. Per JEDEC JESD51-6 with the board horizontal. 5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 6. This is the thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W. Table 6 provides the DC electrical characteristics for the MPC7447A. Table 6. DC Electrical Specifications At recommended operating conditions. See Table 4. Nominal Bus Voltage 1 Symbol Min Max Unit Notes Input high voltage (all inputs) 1.8 VIH OVDD × 0.65 OVDD + 0.3 V 2 1.7 OVDD + 0.3 Input low voltage (all inputs) 1.8 –0.3 OVDD × 0.35 V 2, 6 –0.3 0.7 µA 2, 3 µA 2, 3, 4 Characteristic 2.5 VIL 2.5 Input leakage current, Vin = OV DD Vin = GND — High-impedance (off-state) leakage current, Vin = OV DD Vin = GND — Output high voltage @ IOH = –5 mA 1.8 Iin — 30 – 30 ITSI 30 – 30 VOH 2.5 Output low voltage @ IOL = 5 mA — 1.8 2.5 VOL OVDD – 0.45 — 1.8 — — 0.45 — 0.6 V V MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 12 Freescale Semiconductor Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) At recommended operating conditions. See Table 4. Nominal Bus Voltage 1 Characteristic Capacitance, Vin = 0 V, f = 1 MHz Symbol Min Max Unit Notes Cin — 8.0 pF 5 All other inputs Notes: 1. Nominal voltages; see Table 4 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD 3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals 4. The leakage is measured for nominal OVDD and V DD, or both OVDD and VDD must vary in the same direction (for example, both OV DD and VDD vary by either +5% or –5%). 5. Capacitance is periodically sampled rather than 100% tested. 6. Excludes signals with internal pullups: BVSEL, LSSD_MODE, TDI, TMS, and TRST. Table 7 provides the power consumption for the MPC7447A. For information regarding power consumption when dynamic frequency switching is enabled, see Section 9.8.5, “Dynamic Frequency Switching (DFS).” NOTE The power consumption information in this table applies when the device is operated at the nominal core voltage indicated in Table 4. For power consumption at derated core voltage conditions, see Section 5.3, “Voltage and Frequency Derating.” Table 7. Power Consumption for MPC7447A Processor (CPU) Frequency 1000 1267 1333 5 Unit Notes 1420 MHz Full-Power Mode Typical 16.0 18.3 18.0 21.0 W 1, 2 Maximum 23.0 26.0 25.0 30.0 W 1, 3 3.3 4.1 W 1, 2 3.3 4.1 W 1, 2 Nap Mode Typical 4.1 4.1 Sleep Mode Typical 4.1 4.1 Deep Sleep Mode (PLL Disabled) MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 13 Electrical and Thermal Characteristics Table 7. Power Consumption for MPC7447A (continued) Processor (CPU) Frequency Typical 1000 1267 1333 5 1420 MHz 4.1 4.0 3.2 4.0 Unit Notes W 1, 2 Notes: 1. These values specify the power consumption for the core power supply (VDD) at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include I/O supply power (OVDD) or PLL supply power (AVDD). OVDD power is system dependent but is typically < 5% of VDD power. Worst case power consumption for AVDD < 3 mW. 2. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. 3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a result, power consumption for this mode is not tested. 5. Power consumption for these devices is artificially constrained during screening to assure lower power consumption than other speed grades. 5.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC7447A. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Section 5.2.1, “Clock AC Specifications,” and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals, and can be dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum processor core frequency; see Section 11, “Ordering Information,” for information on ordering parts. DFS is described in Section 9.8.5, “Dynamic Frequency Switching (DFS).” 5.2.1 Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 3 and represents the tested operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8, is considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK frequency for any application of the MPC7447A will be a function of the AC timings of the MPC7447A, the AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the value given in Table 8. NOTE The core frequency information in this table applies when operating the device at the nominal core voltage indicated in Table 4. For core frequency specifications at derated core voltage conditions, see Section 5.3, “Voltage and Frequency Derating.” MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 14 Freescale Semiconductor Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications At recommended operating conditions. See Table 4. Maximum Processor Core Frequency Characteristic Symbol 1000 MHz 1267 MHz 1333 MHz 1420 MHz Unit Notes Min Max Min Max Min Max Min Max 1000 600 1267 600 1333 600 1420 Processor core frequency fcore 600 VCO frequency fVCO 1200 2000 1200 2533 1200 2667 1200 2840 MHz 1, 8, 9 MHz 1, 9 SYSCLK frequency fSYSCLK 33 167 33 167 33 167 33 167 SYSCLK cycle time tSYSCLK 6.0 30 6.0 30 6.0 30 6.0 30 ns 2 SYSCLK rise and fall time tKR, tKF — 1.0 — 1.0 — 1.0 — 1.0 ns 3 SYSCLK duty cycle measured at OVDD/2 tKHKL/ tSYSCLK 40 60 40 60 40 60 40 60 % 4 SYSCLK cycle-to-cycle jitter — 150 — 150 — 150 — 150 ps 5, 6 Internal PLL relock time — 100 — 100 — 100 — 100 μs 7 MHz 1, 2, 8 Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 9.1.1, “PLL Configuration,” for valid PLL_CFG[0:4] settings. 2. Assumes a lightly-loaded, single-processor system. 3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V. 4. Timing is guaranteed by design and characterization. 5. Guaranteed by design. 6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB. 7. Relock timing is guaranteed by design and characterization. PLL relock time is the maximum amount of time required for PLL lock after a stable V DD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence. 8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting processor frequency is greater than or equal to the minimum core frequency. 9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at the nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be reduced. See Section 5.3, “Voltage and Frequency Derating,” for more information. Figure 3 provides the SYSCLK input timing diagram. SYSCLK VM VM tKHKL VM CVIH CVIL tKR tKF tSYSCLK VM = Midpoint Voltage (OV DD/2) Figure 3. SYSCLK Input Timing Diagram MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 15 Electrical and Thermal Characteristics 5.2.2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC7447A as defined in Figure 4 and Figure 5. Table 9. Processor Bus AC Timing Specifications1 At recommended operating conditions. See Table 4. Parameter Input setup times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] BMODE[0:1], BVSEL Input hold times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] BMODE[0:1], BVSEL Output valid times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT TS ARTRY, SHD[0:1] Symbol 2 All Speed Grades Unit Notes Min Max tAVKH tDVKH tIVKH 1.8 1.8 1.8 — — — — — — tMVKH 1.8 — 8 tAXKH tDXKH tIXKH 0 0 0 — — — — — — — tMXKH 0 — 8 tKHAV tKHDV tKHOV — — — 2.0 2.0 2.0 tKHTSV tKHARV — — 2.0 2.0 ns ns ns ns Output hold times: A[0:35], AP[0:4] D[0:63], DP[0:7] AACK, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], WT TS ARTRY, SHD[0:1] tKHAX tKHDX tKHOX 0.5 0.5 0.5 — — — tKHTSX tKHARX 0.5 0.5 — — SYSCLK to output enable tKHOE 0.5 — ns 5 SYSCLK to output high impedance (all except TS, ARTRY, SHD0, SHD1) tKHOZ — 3.5 ns 5 SYSCLK to TS high impedance after precharge tKHTSPZ — 1 tSYSCLK 3, 4, 5 Maximum delay to ARTRY/SHD0/SHD1 precharge tKHARP — 1 tSYSCLK 3, 5, 6, 7 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 16 Freescale Semiconductor Electrical and Thermal Characteristics Table 9. Processor Bus AC Timing Specifications1 (continued) At recommended operating conditions. See Table 4. All Speed Grades Symbol 2 Parameter SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge Unit tKHARPZ Min Max — 2 Notes tSYSCLK 3, 5, 6, 7 Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and precharged high before returning to high impedance, as shown in Figure 6. The nominal precharge width for TS is 0.5 × tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design. 5. Guaranteed by design and not tested. 6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high impedance for 1 clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design. 7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations). 8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing. Figure 4 provides the AC test load for the MPC7447A. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 4. AC Test Load MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 17 Electrical and Thermal Characteristics Figure 5 provides the mode select input timing diagram for the MPC7447A. The mode select inputs are sampled twice, once before and once after HRESET negation. VM VM SYSCLK HRESET Mode Signals 2nd Sample 1st Sample VM = Midpoint Voltage (OV DD/2) Figure 5. Mode Input Sample Timing Diagram Figure 6 provides the input/output timing diagram for the MPC7447A. SYSCLK VM VM VM tAVKH tIVKH tMVKH tAXKH tIXKH tMXKH All Inputs All Outputs (Except TS, ARTRY, SHD0, SHD1) tKHAV tKHAX tKHDV tKHDX tKHOV tKHOX tKHOE tKHOZ All Outputs (Except TS, ARTRY, SHD0, SHD1) tKHTSPZ tKHTSV tKHTSX tKHTSV TS tKHARPZ tKHARV ARTRY, SHD0, SHD1 tKHARP tKHARX VM = Midpoint Voltage (OV DD/2) Figure 6. Input/Output Timing Diagram MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 18 Freescale Semiconductor Electrical and Thermal Characteristics 5.2.3 IEEE 1149.1 AC Timing Specifications Table 10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 16 through Figure 19. Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1 At recommended operating conditions. See Table 4. Parameter Symbol Min Max Unit TCK frequency of operation fTCLK 0 33.3 MHz TCK cycle time tTCLK 30 — ns TCK clock pulse width measured at 1.4 V tJHJL 15 — ns tJR and tJF — 2 ns TRST assert time tTRST 25 — ns 2 Input setup times: Boundary-scan data TMS, TDI ns 3 tDVJH tIVJH 4 0 — — Input hold times: Boundary-scan data TMS, TDI ns 3 tDXJH tIXJH 20 25 — — Valid times: Boundary-scan data TDO ns 4 tJLDV tJLOV 4 4 20 25 Output hold times: Boundary-scan data TDO ns 4 tJLDX tJLOX 30 30 — — TCK to output high impedance: Boundary-scan data TDO ns 4, 5 tJLDZ tJLOZ 3 3 19 9 TCK rise and fall times Notes Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 7). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. TRST is an asynchronous level sensitive signal. The time is for test purposes only. 3. Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization. Figure 7 provides the AC test load for TDO and the boundary-scan outputs of the MPC7447A. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 7. Alternate AC Test Load for the JTAG Interface MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 19 Electrical and Thermal Characteristics Figure 8 provides the JTAG clock input timing diagram. TCLK VM VM VM tJHJL tJR tJF tTCLK VM = Midpoint Voltage (OVDD/2) Figure 8. JTAG Clock Input Timing Diagram Figure 9 provides the TRST timing diagram. VM VM TRST tTRST VM = Midpoint Voltage (OVDD/2) Figure 9. TRST Timing Diagram Figure 10 provides the boundary-scan timing diagram. TCK VM VM tDVJH Boundary Data Inputs tDXJH Input Data Valid tJLDV tJLDX Boundary Data Outputs Output Data Valid tJLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OV DD/2) Figure 10. Boundary-Scan Timing Diagram MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 20 Freescale Semiconductor Electrical and Thermal Characteristics Figure 11 provides the test access port timing diagram. TCK VM VM tIVJH tIXJH Input Data Valid TDI, TMS tJLOV tJLOX Output Data Valid TDO tJLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 11. Test Access Port Timing Diagram 5.3 Voltage and Frequency Derating To reduce the power consumption of the device, these devices support voltage and frequency derating whereby the core voltage (VDD) may be reduced if the reduced maximum processor core frequency requirements are observed. The supported derated core voltage, resulting maximum processor core frequency (fcore), and power consumption are provided in Table 11. Only those parameters in Table 11 are affected; all other parameter specifications are unaffected. Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating Maximum Rated Core Frequency (Device Marking) Supported Derated Core Voltage (VDD) Maximum Derated Core Frequency (fcore) 1000 1.20 V ±50mV Full-Power Mode Power Consumption Maximum Typical 867 MHz 15.5 W 10.5 W 1267 1065 MHz 18.2 W 12.3 W 1333 1167 MHz 18.1 W 12.3 W 1420 1267 MHz 21.0 W 14.2 W MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 21 Pin Assignments 6 Pin Assignments Figure 12 (in Part A) shows the pinout of the MPC7447A, 360 high coefficient of thermal expansion ceramic ball grid array (HCTE) package as viewed from the top surface. Part B shows the side profile of the HCTE package to indicate the direction of the top surface view. Part A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J K L M N P R T U V W Not to Scale Part B Substrate Assembly Encapsulant View Die Figure 12. Pinout of the MPC7447A, 360 HCTE Package as Viewed from the Top Surface MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 22 Freescale Semiconductor Pinout Listings 7 Pinout Listings Table 12 provides the pinout listing for the MPC7447A, 360 HCTE package. The pinouts of the MPC7447A and MPC7447 are pin compatible, but there have been some changes. An MPC7447A may be populated on a board designed for a MPC7447 provided all pins defined as ‘no connect’ for the MPC7447 are unterminated as required by the MPC7457 RISC Microprocessor Hardware Specifications. The MPC7447A uses pins previously marked ‘no connect’ for the temperature diode pins and for additional power and ground connections. Because these ‘no connect’ pins in the MPC7447 360 pin package are not driven in functional mode, an MPC7447 can be populated in an MPC7447A board. See Section 9.4, “Connection Recommendations,” for additional information. NOTE Caution must be exercised when performing boundary scan test operations on a board designed for an MPC7447A but populated with an MPC7447. This is because in the MPC7447 it is possible to drive the latches associated with the former ‘no connect’ pins in the MPC7447, potentially causing contention on those pins. To prevent this, ensure that these pins are not connected on the board or, if they are connected, ensure that the states of internal MPC7447 latches do not cause these pins to be driven during board testing. NOTE This pinout is not compatible with the MPC750, MPC7400, or MPC7410 360 BGA and LGA package. Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package Pin Number Active I/O I/F Select1 Notes A[0:35] E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4, V1, J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1, B12, C4, G10, B11 High I/O BVSEL 2 AACK R1 Low Input BVSEL AP[0:4] C1, E3, H6, F5, G7 High I/O BVSEL 2 ARTRY N2 Low I/O BVSEL 3 AVDD A8 — Input N/A BG M1 Low Input BVSEL BMODE0 G9 Low Input BVSEL 4 BMODE1 F8 Low Input BVSEL 5 BR D2 Low Output BVSEL BVSEL B7 High Input BVSEL CI J1 Low Output BVSEL CKSTP_IN A3 Low Input BVSEL CKSTP_OUT B1 Low Output BVSEL Signal Name 1, 6 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 23 Pinout Listings Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued) Signal Name Pin Number Active I/O I/F Select1 Notes CLK_OUT H2 High Output BVSEL D[0:63] R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14, W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9, P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17, R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17, W3, V17, U4, U8, U7, R7, P6, R8, W8, T8 High I/O BVSEL DBG M2 Low Input BVSEL DP[0:7] T3, W4, T4, W9, M6, V3, N8, W6 High I/O BVSEL DRDY R3 Low Output BVSEL 7 DTI[0:3] G1, K1, P1, N1 High Input BVSEL 8 EXT_QUAL A11 High Input BVSEL 9 GBL E2 Low I/O BVSEL GND B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10, J12, K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13, N7, P3, P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11, V15 — — N/A GND A17, A19, B13, B16, B18, E12, E19, F13, F16, F18, G19, H18, J14, L14, M15, M17, M19, N14, N16, P15, P19 — — N/A 15 GND_SENSE G12, N13 — — N/A 19 HIT B2 Low Output BVSEL 7 HRESET D8 Low Input BVSEL INT D4 Low Input BVSEL L1_TSTCLK G8 High Input BVSEL 9 L2_TSTCLK B3 High Input BVSEL 10 NC (no connect) A6, A14, A15, B14, B15, C14, C15, C16, C17, C18, C19, D14, D15, D16, D17, D18, D19, E14, E15, F14, F15, G14, G15, H15, H16, J15, J16, J17, J18, J19, K15, K16, K17, K18, K19, L15, L16, L17, L18, L19 — — — 11 LSSD_MODE E8 Low Input BVSEL 6, 12 MCP C9 Low Input BVSEL OVDD B4, C2, C12, D5, F2, H3, J5, K2, L5, M3, N6, P2, P8, P11, R4, R13, R16, T6, T9, U2, U12, U16, V4, V7, V10, V14 — — N/A OVDD_SENSE E18, G18 — — N/A PLL_CFG[0:4] B8, C8, C7, D7, A7 High Input BVSEL PMON_IN D9 Low Input BVSEL PMON_OUT A9 Low Output BVSEL 16 13 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 24 Freescale Semiconductor Pinout Listings Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued) Signal Name Pin Number Active I/O I/F Select1 Notes QACK G5 Low Input BVSEL QREQ P4 Low Output BVSEL SHD[0:1] E4, H5 Low I/O BVSEL SMI F9 Low Input BVSEL SRESET A2 Low Input BVSEL SYSCLK A10 — Input BVSEL TA K6 Low Input BVSEL TBEN E1 High Input BVSEL TBST F11 Low Output BVSEL TCK C6 High Input BVSEL TDI B9 High Input BVSEL TDO A4 High Output BVSEL TEA L1 Low Input BVSEL TEMP_ANODE N18 17 TEMP_CATHODE N19 17 TEST[0:3] A12, B6, B10, E10 — Input BVSEL 12 TEST D10 — Input BVSEL 9 TMS F1 High Input BVSEL 6 TRST A5 Low Input BVSEL 6, 14 TS L4 Low I/O BVSEL 3 TSIZ[0:2] G6, F7, E7 High Output BVSEL TT[0:4] E5, E6, F6, E9, C5 High I/O BVSEL WT D3 Low Output BVSEL VDD H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13, M8, M10, M12 — — N/A VDD A13, A16, A18, B17, B19, C13, E13, E16, F12, F17, F19, G11, G16, H14, H17, H19, M14, M16, M18, N15, N17, P16, P18 — — N/A 3 6 15 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 25 Pinout Listings Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued) Signal Name VDD_SENSE Pin Number G13, N12 Active I/O I/F Select1 Notes — — N/A 18 Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals; VDD supplies power to the processor core and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V), or to HRESET or OVDD (selects 2.5 V); see Table 3. If used, the pull-down resistor should be less than 250 Ω. Because these settings may change in future products, it is recommended BVSEL be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. For actual recommended value of Vin or supply voltages see Table 4. 2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OVDD. 3. These pins require weak pull-up resistors (for example, 4.7 KΩ ) to maintain the control signals in the negated state after they have been actively negated and released by the MPC7447A and other bus masters. 4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going high. 5. This signal must be negated during reset, by pull-up resistor to OV DD or negation by ¬HRESET (inverse of HRESET), to ensure proper operation. 6. Internal pull up on die. 7. Ignored in 60x bus mode. 8. These signals must be pulled down to GND if unused, or if the MPC7447A is in 60x bus mode. 9. These input signals are for factory use only and must be pulled down to GND for normal machine operation. 10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance. 11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes. 12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation. 13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software. 14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation. 15.These pins were NCs on the MPC7447, MPC7445, and MPC7441. They may be left unconnected for backward compatibility with these devices, but it is recommended they be connected in new designs to facilitate future products. See Section 9.4, “Connection Recommendations,” for more information. 16.These pins were OVDD pins on the MPC7447, MPC7445, and MPC7441. These pins are internally connected to OVDD and are intended to allow an external device to detect the I/O voltage level present inside the device package. If unused, they must be connected directly to OVDD or left unconnected. 17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature of the processor. These pins may be left unterminated if unused. 18.These pins are internally connected to V DD and are intended to allow an external device to detect the processor core voltage level present inside the device package. If unused, they must be connected directly to VDD or left unconnected. 19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 26 Freescale Semiconductor Package Description 8 Package Description The following sections provide the package parameters and mechanical dimensions for the HCTE package. 8.1 Package Parameters for the MPC7447A, 360 HCTE BGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (HCTE). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 25 × 25 mm 360 (19 × 19 ball array – 1) 1.27 mm (50 mil) 2.72 mm 3.24 mm 0.89 mm (35 mil) Coefficient of thermal expansion 12.3 ppm/°C MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 27 Package Description 8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA Figure 13 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360 HCTE BGA package. 2X 0.2 D Capacitor Region B D1 D3 A1 CORNER D2 A 1 0.15 A NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters. 3. Top side A1 corner index is a metalized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array. E3 E4 E Millimeters E2 E1 2X 0.2 D4 C 1 2 3 4 5 6 7 8 9 10 111213141516 171819 W V U T R P N M L K J H G F E D C B A e 360X b 0.3 A B C 0.15 A A3 A2 A1 A 0.35 A Dim Min Max A 2.72 3.24 A1 0.80 1.00 A2 1.10 1.30 A3 — 0.6 b 0.82 0.93 D 25.00 BSC D1 — 11.3 D2 8.0 — D3 — 6.5 D4 9.76 9.96 e 1.27 BSC E 25.00 BSC E1 — 11.3 E2 8.0 — E3 — 6.5 E4 8.41 8.61 Figure 13. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A, 360 HCTE BGA Package MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 28 Freescale Semiconductor Package Description 8.3 Package Parameters for the MPC7447A, 360 HCTE LGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 high coefficient of thermal expansion ceramic land grid array (HCTE). Package outline Interconnects Pitch Minimum module height Maximum module height Coefficient of thermal expansion 25 × 25 mm 360 (19 × 19 ball array – 1) 1.27 mm (50 mil) 1.92 mm 2.20 mm 12.3 ppm/°C MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 29 Package Description 8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA Figure 14 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360 HCTE LGA package. 2X 0.2 D Capacitor Region B D1 D3 A1 CORNER D2 A 1 0.15 A NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters. 3. Top side A1 corner index is a metalized feature with various shapes. Bottom side A1 corner is designated with a pad missing from the array. E3 E4 E Millimeters E2 E1 2X 0.2 D4 C 1 2 3 4 5 6 7 8 9 10 111213141516 171819 W V U T R P N M L K J H G F E D C B A e 360X b 0.3 A B C A2 A1 A 0.35 A Dim Min Max A 1.92 2.20 A1 1.10 1.30 A2 — 0.6 b 0.82 0.93 D 25.00 BSC D1 — 11.3 D2 8.0 — D3 — 6.5 D4 9.76 9.96 e 1.27 BSC E 25.00 BSC E1 — 11.3 E2 8.0 — E3 — 6.5 E4 8.41 8.61 0.15 A Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A, 360 HCTE LGA Package MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 30 Freescale Semiconductor Package Description 8.5 Package Parameters for the MPC7447A, 360 HCTE RoHS-Compliant BGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 lead-free high coefficient of thermal expansion ceramic ball grid array (HCTE). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter Coefficient of thermal expansion 25 × 25 mm 360 (19 × 19 ball array – 1) 1.27 mm (50 mil) 2.32 mm 2.80 mm 0.75 mm (30 mil) 12.3 ppm/°C MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 31 Package Description 8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE RoHS-Compliant BGA Figure 15 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447A, 360 HCTE BGA package. 2X 0.2 D Capacitor Region B D1 D3 A1 CORNER D2 A 1 0.15 A E3 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters. 3. Top side A1 corner index is a metalized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array. 4. Dimension A1 represents the collapsed sphere diameter. E4 E Millimeters E2 E1 2X Dim Min Max A 2.32 2.80 0.40 0.60 A2 1.10 1.30 A3 — 0.6 b 0.60 0.90 A1 0.2 D4 C 1 2 3 4 5 6 7 8 9 10 111213141516 171819 W V U T R P N M L K J H G F E D C B A e 360X b 0.3 A B C 0.15 A A3 A2 A1 A 0.35 A 4 D 25.00 BSC D1 — 11.3 D2 8.0 — D3 — 6.5 D4 9.76 9.96 e 1.27 BSC E 25.00 BSC E1 — 11.3 E2 8.0 — E3 — 6.5 E4 8.41 8.61 Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A, 360 HCTE RoHS-Compliant BGA Package MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 32 Freescale Semiconductor Package Description 8.7 Substrate Capacitors for the MPC7447A, 360 HCTE Figure 16 shows the connectivity of the substrate capacitor pads for the MPC7447A, 360 HCTE. All capacitors are 100 nF. Pad Number Capacitor A1 CORNER C1-1 C2-1 C3-1 C4-1 C5-1 C6-1 1 C8-2 C18-2 C17-2 C16-2 C15-2 C14-2 C13-2 C18-1 C17-1 C16-1 C15-1 C14-1 C13-1 C7-1 C6-2 C8-1 C5-2 C12-1 C11-1 C10-1 C9-1 C4-2 C7-2 C2-2 C3-2 C12-2 C11-2 C10-2 C9-2 C19-2 C20-2 C21-2 C22-2 C23-2 C24-2 C19-1 C20-1 C21-1 C22-1 C23-1 C24-1 C1-2 –1 –2 C1 GND VDD C2 GND VDD C3 GND OV DD C4 GND VDD C5 GND VDD C6 GND VDD C7 GND VDD C8 GND VDD C9 GND VDD C10 GND VDD C11 GND VDD C12 GND VDD C13 GND VDD C14 GND VDD C15 GND VDD C16 GND OV DD C17 GND VDD C18 GND OV DD C19 GND OV DD C20 GND VDD C21 GND OV DD C22 GND VDD C23 GND OV DD C24 GND VDD Figure 16. Substrate Bypass Capacitors for the MPC7447A, 360 HCTE MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 33 System Design Information 9 System Design Information This section provides system and thermal design recommendations for successful application of the MPC7447A. 9.1 9.1.1 Clocks PLL Configuration The MPC7447A PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the MPC7447A is shown in Table 13 for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1400 MHz column in Table 8. When enabled, dynamic frequency switching (DFS) also affects the core frequency by halving the bus-to-core multiplier; see Section 9.8.5, “Dynamic Frequency Switching (DFS),” for more information. Note that when DFS is enabled the resulting core frequency must meet the minimum core frequency requirements described in Table 8. Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_ CFG[0:4] Bus (SYSCLK) Frequency Bus-toCore Multiplier Core-toVCO Multiplier 01000 2x 1 2x 10000 3x 1 2x 10100 4x 1 2x 10110 5x 2x 665 (1333) 835 (1670) 10010 5.5x 2x 732 (1466) 919 (1837) 11010 6x 2x 600 (1200) 798 (1600) 1002 (2004) 01010 6.5x 2x 650 (1300) 865 (1730) 1086 (2171) 00100 7x 2x 700 (1400) 931 (1862) 1169 (2338) 00010 7.5x 2x 623 (1245) 750 (1500) 998 (2000) 1253 (2505) 11000 8x 2x 664 (1328) 800 (1600) 1064 (2128) 1336 (2672) 33 MHz 50 MHz 67 MHz 75 MHz 83 MHz 100 MHz 133 MHz 167 MHz 668 (1333) 600 (1200) MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 34 Freescale Semiconductor System Design Information Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued) Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_ CFG[0:4] Bus-toCore Multiplier Core-toVCO Multiplier 01100 8.5x 2x 01111 9x 2x 01110 9.5x 10101 Bus (SYSCLK) Frequency 33 MHz 50 MHz 67 MHz 75 MHz 83 MHz 100 MHz 133 MHz 167 MHz 638 (1276) 706 (1412) 850 (1700) 1131 (2261) 1420 (2833) 603 (1200) 675 (1350) 747 (1494) 900 (1800) 1197 (2394) 2x 637 (1266) 713 (1524) 789 (1578) 950 (1900) 1264 (2528) 10x 2x 670 (1333) 750 (1500) 830 (1660) 1000 (2000) 1330 (2667) 10001 10.5x 2x 704 (1400) 788 (1876) 872 (1744) 1050 (2100) 1397 (2793) 10011 11x 2x 737 (1466) 825 (1650) 913 (1826) 1100 (2200) 00000 11.5x 2x 771 (532) 863 (1726) 955 (1910) 1150 (2300) 10111 12x 2x 600 (1200) 804 (1600) 900 (1800) 996 (1992) 1200 (2400) 11111 12.5x 2x 625 (1200) 838 (1666) 938 (1876) 1038 (2076) 1250 (2500) 01011 13x 2x 650 (1300) 871 (1730) 975 (1950) 1079 (2158) 1300 (2600) 11100 13.5x 2x 675 (1350) 905 (1800) 1013 (2026) 1121 (2242) 1350 (2700) 11001 14x 2x 700 (1400) 938 (1866) 1050 (2100) 1162 (2324) 1400 (2800) 00011 15x 2x 750 (1500) 1005 (2000) 1125 (2250) 1245 (2490) 11011 16x 2x 800 (1600) 1072 (2132) 1200 (2400) 1328 (2656) 00001 17x 2x 850 (1900) 1139 (2264) 1275 (2550) 1411 (2822) 00101 18x 2x 900 (1800) 1206 (2400) 1350 (2700) 00111 20x 2x 660 (1334) 1000 (2000) 1340 (2664) 01001 21x 2x 693 (1400) 1050 (2100) 1407 (2797) MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 35 System Design Information Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued) Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_ CFG[0:4] Bus-toCore Multiplier Core-toVCO Multiplier 01101 24x 11101 28x Bus (SYSCLK) Frequency 33 MHz 50 MHz 2x 792 (1600) 1200 (2400) 2x 924 (1866) 1400 (2800) 00110 PLL bypass 11110 PLL off 67 MHz 75 MHz 83 MHz 100 MHz 133 MHz 167 MHz PLL off, SYSCLK clocks core circuitry directly PLL off, no core clocking occurs Notes: 1. Ratios below 5:1 require an AACK delay See MPC7450 RISC Microprocessor Family Reference Manual, Section 9.3.3, “MPX Bus Address Tenure Termination.” 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies that are not useful, not supported, or not tested for by the MPC7455; see Section 5.2.1, “Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL-off mode, no clocking occurs inside the MPC7447A regardless of the SYSCLK input. 9.1.2 System Bus Clock (SYSCLK) and Spread Spectrum Sources Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8 considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the MPC7457 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns, and the MPC7457 is compatible with spread spectrum sources if the recommendations listed in Table 14 are observed. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 36 Freescale Semiconductor System Design Information Table 14. Spread Specturm Clock Source Recommendations At recommended operating conditions. See Table 4. Parameter Min Max Unit Notes Frequency modulation — 50 kHz 1 Frequency spread — 1.0 % 1, 2 Notes: 1. Guaranteed by design. 2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the minimum and maximum specifications given in Table 8. It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core or bus frequency should avoid violating the stated limits by using down-spreading only. 9.2 PLL Power Supply Filtering The AVDD power signal is provided on the MPC7447A to provide power to the clock generation PLL. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 17 using surface-mount capacitors with minimum effective series inductance (ESL) is recommended. The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 HCTE footprint. 10 Ω VDD AVDD 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 17. PLL Power Supply Filter Circuit 9.3 Decoupling Recommendations Due to the MPC7447A dynamic power management feature, large address and data buses, and high operating frequencies, the MPC7447A can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC7447A system, and the MPC7447A itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer use sufficient decoupling capacitors, typically one capacitor for every 1–2 VDD pins, and a similar or lesser number for the OVDD pins, placed as close as possible to the power pins of the MPC7447A. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 37 System Design Information These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors should be used to minimize lead inductance. Orientations where connections are made along the length of the part, such as 0204, are preferable but not mandatory. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are: 100–330 µF (AVX TPS tantalum or Sanyo OSCON). 9.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unless otherwise noted, unused active-low inputs should be tied to OVDD, and unused active-high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, and GND pins in the MPC7447A. For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a system originally designed for one of these devices to the MPC7447A, the new power and ground signals (formerly NC, see Table 12) may be left unconnected. There is no performance degradation associated with leaving these pins unconnected. However, future devices may require these additional power and ground signals to be connected to achieve maximum performance, and it is recommended that new designs include the additional connections to facilitate future upgrades. See also Section 7, “Pinout Listings,” for additional information. 9.5 Output Buffer DC Impedance The MPC7447A processor bus drivers are characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. The value of each resistor is varied until the pad voltage is OVDD/2. Figure 18 shows the driver impedance measurement. The output impedance is the average of two components—the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 38 Freescale Semiconductor System Design Information OVDD RN SW2 Data Pad SW1 RP OGND Figure 18. Driver Impedance Measurement Table 15 summarizes the signal impedance results. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Table 15. Impedance Characteristics VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C Impedance Z0 9.6 Processor Bus Unit Typical 33–42 Ω Maximum 31–51 Ω Pull-Up/Pull-Down Resistor Requirements The MPC7447A requires high-resistive (weak: 4.7 KΩ) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC7447A or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1. Some pins designated as being factory test pins must be pulled up to OVDD or down to GND to ensure proper device operation. The pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (weak or stronger: 4.7 KΩ–1 KΩ) to prevent erroneous assertions of this signal. In addition, the MPC7447A has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 KΩ–1 KΩ) if it is used by the system. This pin is CKSTP_OUT. If pull-down resistors are used to configure BVSEL, the resistors should be less than 250 Ω (see Table 12). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down resistors (1 KΩ or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 39 System Design Information During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7447A must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC7447A or by other receivers in the system. These signals can be pulled up through weak (10-KΩ) pull-up resistors by the system, address bus driven mode enabled (see the MPC7450 RISC Microprocessor Family Users’ Manual for more information on this mode), or they may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw. Preliminary studies have shown the additional power draw by the MPC7447A input receivers to be negligible and, in any event, none of these measures are necessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL. If address or data parity is not used by the system, and respective parity checking is disabled through HID1, the input receivers for those pins are disabled and do not require pull-up resistors, and may be left unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused and must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking is enabled (HID1[EBA] = 1) and extended addressing is not used, AP must be pulled up to OVDD through a weak pull-up resistor. If the MPC7447A is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down resistors. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods. The data bus signals are: D[0:63] and DP[0:7]. 9.7 JTAG Configuration Signals Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 19 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. Although Freescale recommends that the COP header be designed into the system as shown in Figure 19, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 40 Freescale Semiconductor System Design Information The COP header shown in Figure 19 adds many benefits—breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 19; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 19 is common to all known emulators. The QACK signal shown in Figure 19 is usually connected to the PCI bridge chip in a system and is an input to the MPC7447A informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7447A must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged through logic so that it also can be driven by the PCI bridge. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 41 System Design Information From Target Board Sources (if any) SRESET SRESET HRESET HRESET 6 QACK 13 11 HRESET 10 KΩ SRESET 10 KΩ OVDD OVDD 10 KΩ OVDD 10 KΩ OVDD 0Ω5 1 2 3 4 5 6 7 8 9 10 11 12 6 5 10 KΩ OVDD OVDD CHKSTP_OUT CHKSTP_OUT Key 14 2 10 KΩ OVDD OVDD CHKSTP_IN COP Header COP Connector Physical Pin Out 2 KΩ 10 KΩ KEY 16 VDD_SENSE 1 15 13 No Pin 15 TRST 6 TRST 4 CHKSTP_IN 8 TMS 9 1 3 TMS TDO TDO TDI TDI TCK 7 2 10 12 16 TCK QACK QACK NC NC 2 KΩ 3 OV DD 10 KΩ 10 KΩ 4 OV DD Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7447A. Connect pin 5 of the COP header to OV DD with a 10-KΩ pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. 3. Component not populated. Populate only if debug tool does not drive QACK. 4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK. 5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to TRST of the part through a 0-Ω isolation resistor. 6. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above. Figure 19. JTAG Interface Connection MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 42 Freescale Semiconductor System Design Information 9.8 Thermal Management Information This section provides thermal management information for the high coefficient of thermal expansion (HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The MPC7447A implements several features designed to assist with thermal management, including DFS and the temperature diode. DFS reduces the power consumption of the device by reducing the core frequency; see Section 220.127.116.11, “Power Consumption with DFS Enabled,” for specific information regarding power reduction and DFS. The temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see Section 9.8.4, “Temperature Diode,” for more information. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (see Figure 20 and Figure 21); however, due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. In any implementation of a heat sink solution, the force on the die should not exceed ten pounds. Heat Sink HCTE BGA Package Heat Sink Clip Thermal Interface Material Printed-Circuit Board Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options NOTE A clip on heat sink is not recommended for LGA because there may not be adequate clearance between the device and the circuit board. A through-hole solution is recommended, as shown in Figure 21 below. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 43 System Design Information Heat Sink HCTE LGA Package Heat Sink Clip Thermal Interface Material Printed-Circuit Board Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the MPC7447A. There are several commercially-available heat sinks for the MPC7447A provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com 603-224-9988 Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com 408-567-8082 Calgreg Thermal Solutions 60 Alhambra Road Warwick, RI 02886 Internet: www.calgregthermalsolutions.com 401-732-8100 International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com 818-842-7277 Tyco Electronics Chip Coolers™ P.O. Box 3608 Harrisburg, PA 17105-3608 Internet: www.chipcoolers.com 717-564-0100 Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-635-2800 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 44 Freescale Semiconductor System Design Information 9.8.1 Internal Package Conduction Resistance For the exposed-die packaging technology described in Table 5, the intrinsic conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) • The die junction-to-board thermal resistance Figure 22 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Internal Resistance Printed-Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance.) Figure 22. C4 Package with Heat Sink Mounted to a Printed-Circuit Board Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected for a first-order analysis. Thus the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. 9.8.2 Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 23 shows the thermal performance of three thin-sheet thermal interface materials (silicone, graphite/oil, fluoroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 20). Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the MPC7447A. Of course, MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 45 System Design Information the selection of any thermal interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on. Silicone Sheet (0.006 in.) Bare Joint Fluoroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 23. Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration requirements. There are several commercially available thermal interfaces and adhesive materials provided by the following vendors: The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 800-347-4572 Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com 781-935-4850 Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com 800-248-2481 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 46 Freescale Semiconductor System Design Information Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com 888-642-7674 Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 888-246-9050 The following section provides a heat sink selection example using one of the commercially available heat sinks. 9.8.3 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ti + Tr + (RθJC + Rθint + Rθsa) × Pd where: Tj is the die-junction temperature Ti is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet RθJC is the junction-to-case thermal resistance Rθint is the adhesive or interface material thermal resistance Rθsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ti) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of the thermal interface material (Rθint) is typically about 1.5°C/W. For example, assuming a Ti of 30°C, a Tr of 5°C, an HCTE package RθJC = 0.1, and a typical power consumption (Pd) of 18.7 W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + Rθsa) × 18.7 W For this example, a Rθsavalue of 2.1°C/W or less is required to maintain the die junction temperature below the maximum value of Table 4. Though the die-junction-to-ambient and the heat-sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature—airflow, board population (local MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 47 System Design Information heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on. Due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. For system thermal modeling, the MPC7447A thermal model is shown in Figure 24. Four volumes represent this device. Two of the volumes, solder ball-air and substrate, are modeled using the package outline size of the package. The other two, die and bump-underfill, have the same size as the die. The silicon die should be modeled 8.5 × 9.9 × 0.7 mm3 with the heat source applied as a uniform source at the bottom of the volume. The bump and underfill layer is modeled as 8.5 × 9.9 × 0.07 mm3 (or as a collapsed volume) with orthotropic material properties: 0.6 W/(m • K) in the xy-plane and 1.9 W/(m • K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm3, and has 8.1 W/(m • K) isotropic conductivity in the xy-plane and 4 W/(m • K) in the direction of the z-axis. The solder ball and air layer are modeled with the same horizontal dimensions as the substrate and are 0.6 mm thick. They can also be modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m • K) in the xy-plane direction and 3.8 W/(m • K) in the direction of the z-axis. Conductivity Value Unit Die 3 Bump and Underfill (8.5 × 9.9 × 0.07 mm ) Bump and Underfill z kx 0.6 ky 0.6 kz 1.9 W/(m • K) Substrate Solder and Air Side View of Model (Not to Scale) 3 Substrate (25 × 25 × 1.2 mm ) kx 8.1 ky 8.1 kz 4.0 x Substrate Solder Ball and Air (25 × 25 × 0.6 mm3) kx 0.034 ky 0.034 kz 3.8 Die y Top View of Model (Not to Scale) Figure 24. Recommended Thermal Model of MPC7447A MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 48 Freescale Semiconductor System Design Information 9.8.4 Temperature Diode The MPC7447A has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. For proper operation, the monitoring device used should auto-calibrate the device by canceling out the VBE variation of each MPC7447A’s internal diode. The following are the specifications of the MPC7447A on-board temperature diode: 0.40 V <Vf <0.90 V Operating range 2–300 μA Diode leakage < 10 nA @ 125 C Ideality factor (n) over 5–150 μA @ 60 C: 1.0275 ± 0.9 % Ideality factor is defined as the deviation from the ideal diode equation: qVf ___ Ifw = Is e nKT – 1 Where: Ifw = Forward current Is = Saturation current V d = Voltage at diode BM: this does not show up in any equations. V f = Voltage forward biased q = Charge of electron (1.6 x 10 -19 C) n = Ideality factor (normally 1.0) K = Boltzman’s constant (1.38 x 10-23 Joules/K) T = Temperature (Kelvins) Another useful equation is : KT IH VH – VL = n__ ln __ q IL Where: V H = Diode voltage while IH is flowing V L = Diode voltage while IL is flowing IH = Larger diode bias current IL = Smaller diode bias current MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 49 System Design Information The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following: VH – VL = 1.986 × 10-4 × nT Solving for T, the equation becomes: nT = 9.8.5 VH – VL __________ 1.986 × 10-4 Dynamic Frequency Switching (DFS) The new DFS feature in the MPC7447A adds the ability to divide the processor-to-system bus ratio by two during normal functional operation by setting the HID1[DFS2] bit. The frequency change occurs in 1 clock cycle, and no idle waiting period is required to switch between modes. Additional information regarding DFS can be found in the MPC7450 RISC Microprocessor Family Reference Manual. 18.104.22.168 Power Consumption with DFS Enabled Power consumption with DFS enabled can be approximated using the following formula: fDFS PDFS = ___ (P – PDS) + PDS f Where: PDFS = Power consumption with DFS enabled fDFS = Core frequency with DFS enabled f = Core frequency prior to enabling DFS P = Power consumption prior to enabling DFS (see Table 7) PDS = Deep sleep mode power consumption (see Table 7) The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed. 22.214.171.124 Bus-to-Core Multiplier Constraints with DFS DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:4] during hard reset. Specifically, because the MPC7447A does not support quarter clock ratios or the 1x multiplier, the DFS feature is limited to integer PLL multipliers of 4x and higher. The complete listing is shown in Table 16. Table 16. Valid Divide Ratio Configurations Bus-to-Core Multiplier Configured by PLL_CFG[0:4] (see Table 13) Bus-to-Core Multiplier with HID1[DFS1] = 1 (÷2) 2x N/A 3x N/A MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 50 Freescale Semiconductor System Design Information Table 16. Valid Divide Ratio Configurations (continued) 126.96.36.199 Bus-to-Core Multiplier Configured by PLL_CFG[0:4] (see Table 13) Bus-to-Core Multiplier with HID1[DFS1] = 1 (÷2) 4x 2x 5x 2.5x 5.5x N/A 6x 3x 6.5x N/A 7x 3.5x 7.5x N/A 8x 4x 8.5x N/A 9x 4.5x 9.5x N/A 10x 5x 10.5x N/A 11x 5.5x 11.5x N/A 12x 6x 12.5x N/A 13x 6.5x 13.5x N/A 14x 7x 15x 7.5x 16x 8x 17x 8.5x 18x 9x 20x 10x 21x 10.5x 24x 12x 28x 14x Minimum Core Frequency Requirements with DFS In many systems, enabling DFS can result in very low processor core frequencies. However, care must be taken to ensure that the resulting processor core frequency is within the limits specified in Table 8. Proper operation of the device is not guaranteed at core frequencies below the specified minimum fcore. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 51 Document Revision History 10 Document Revision History Table 17 provides a revision history for this hardware specification. Table 17. Document Revision History Revision Number Date Substantive Changes 5 01/30/2005 Corrected RoHS BGA sphere diameter dimensions 4 09/23/2005 Added RoHS BGA case outlines and part numbers. Removed note references for CI and WT in Table 12 3 08/23/2005 Added “Section 9.1.2, “System Bus Clock (SYSCLK) and Spread Spectrum Sources” Section 9.8, “Thermal Management Information”: Added vendor to list Section 9.8.3, “Heat Sink Selection Example”: Correct silicon die and underfil/bump model dimensions 2 02/16/2005 Changed die size Table 8: Modified jitter specifications to conform to JEDEC standards, changed jitter specification to cycle-to-cycle jitter (instead of long- and short-term jitter); changed jitter bandwidth recommendations. Added information for LGA package. 1 — Added tKHTSV, tKHARV, tKHTSX, and tKHARX to Table 9; these were previously grouped with tKHOV and tKHOX. NOTE: Documentation change only; the values for the output valid and output hold AC timing specifications remain unchanged for TS, ARTRY, and SHD[0:1]. Added derating section with table; added 1000 MHz speed bin 0.1 — Retitled Table 19 to include document order information for MC7447AnnnnNx series hardware specification addendum. 0 — Initial revision. 11 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact a local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier that may specify special application conditions. Each part number also contains a revision level code that refers to the die mask revision number. Section 11.2, “Part Numbers Not Fully Addressed by This Document,” lists the part numbers that do not fully conform to the specifications of this document. These special part numbers require an additional document called a hardware specification addendum. MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 52 Freescale Semiconductor Ordering Information 11.1 Part Numbers Fully Addressed by This Document Table 18 provides the Freescale part numbering nomenclature for the MPC7447A. Table 18. Part Numbering Nomenclature MC 7447A xx nnnn L x Product Code Part Identifier Package Processor Frequency Application Modifier Revision Level MC 7447A 11.2 HX = HCTE BGA VS = RoHS LGA VU = RoHS BGA 1000 1267 1333 1420 L: 1.3 V ± 50 mV 0 to 105°C B: 1.1:PVR = 8003 0101 Part Numbers Not Fully Addressed by This Document Parts with application modifiers or revision levels not fully addressed in this specification document are described in separate hardware specification addenda which supplement and supersede this document. As such parts are released, these specifications will be listed in this section. Table 19. Part Numbers Addressed by MC7447Axxnnnn Nx Series Hardware Specification Addendum (Document Order No. MPC7447AECS01AD) MC 7447A xx nnnn N x Product Code Part Identifier Package Processor Frequency Application Modifier Revision Level MC 7447A HX = HCTE BGA VS = RoHS LGA VU = RoHS BGA 600 733 867 1000 1167 N: 1.1 V ± 50 mV 0 to 105°C B:1.1: PVR = 8003 0101 MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 53 Ordering Information Table 20. Part Numbers Addressed by MC7447ATxxnnnn N x Series Hardware Specification Addendum (Document Order No. MPC7447AECS02AD) MC 7447A T xx nnnn N x Product Code Part Identifier Specification Modifier Package Processor Frequency Application Modifier Revision Level MC 7447A T = Extended Temperature Device 11.3 HX = HCTE BGA 867 1000 1167 N: 1.1 V ± 50 mV –40 to 105°C B:1.1: PVR = 8003 0101 Part Marking Parts are marked as the example shown in Figure 25. MC7447A xxnnnnLx AWLYYWW MMMMMM YWWLAZ 7447A BGA / LGA Notes: AWLYYWW is the test code. MMMMMM is the M00 (mask) number. YWWLAZ is the assembly traceability code. Figure 25. Part Marking for BGA and LGA Device MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 54 Freescale Semiconductor Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 55 How to Reach Us: Home Page: www.freescale.com email: email@example.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 firstname.lastname@example.org Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. 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