AN-746: SDI II VCXO
AN-746: SDI II VCXO Reference Design for Arria 10
Devices
2015.08.31
AN-746
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The Serial Digital Interface II (SDI II) VCXO reference design demonstrates the transmission and
receiption of video data using the Altera® SDI II MegaCore® function and the Arria 10 GX FPGA
Development Kit. This reference design uses two instances of the triple-rate SDI II MegaCore function,
which supports the SD-SDI, HD-SDI, and 3G-SDI standards. This application note describes the design
components and requirements. It also includes the instructions on setting up and testing the reference
design.
Block Diagram
The reference design provides a general platform that enables you to control, test, and monitor different
speeds of the SDI II operations. The following figure shows a high-level block diagram of the reference
design. This reference design consists of two channels: channel 0—SDI II IP in duplex mode and channel
1—SDI II IP configured as a transmitter. In Arria 10 devices, the transceiver is no longer part of the SDI II
IP and the TX PLL is separated from the transceiver PHY.
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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Block Diagram
Figure 1: Block Diagram
Arria 10 GX Device
RX Transceiver
PHY Reset
Controller
Channel 0
Triple-rate SDI II IP
Loopback
FIFO Buffer
VCXO
(148.5/148.35 MHz
clock source)
Phase Frequency
Detector (PFD)
Oscillator
(100 MHz)
CDR
Arria 10
Transceiver
Native PHY
Transmitter
Receiver
RX Transceiver
Reconfiguration
Management
TX
PLL
To SDI Receiver
SDI Serial Data
From SDI
Transmitter
TX Transceiver
PHY Reset
Controller
To Reconfiguration Clock
Channel 1
Triple-rate SDI II IP
Pattern
Generator
TX
PLL
Oscillator
(270 MHz)
Legend
Altera Corporation
Arria 10
Transceiver
Native PHY
Transmitter
Clock Input 148.5/148.35 MHz
Clock Input 100 MHz
Clock Input 270 MHz
To SDI Receiver
TX Transceiver
PHY Reset
Controller
Control/Status
Video Data
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Design Components
3
Design Components
The following table describes each component in the reference design.
Table 1: Design Components
Name
Triple-rate SDI II IP
Description
The Altera SDI II MegaCore function.
• Channel 0—the instance of the SDI II IP in this channel is
configured to support full-duplex operations and the triple-rate
video standards, SD-SDI, HD-SDI, and 3G-SDI.
The SDI II receiver, TX fPLL, and TX transceiver reset controller
use the 148.5Mhz/148.35Mhz external clock source from the VCXO
(si516) block on the development board. The RX data is looped
back to the transmitter through a FIFO buffer. The interface is
configured to operate at 270Mbps, 1.485/1.4835Gbps, or 2.97/
2.967Gbps.
• Channel 1—the instance of the SDI II IP is configured as a
transmitter that supports the triple-rate video standards, SD-SDI,
HD-SDI, and 3G-SDI. This instance acts as a video source, and
transmits video stream at 270Mbps (SD), 1.485/1.4835Gbps (HD),
or 2.97/2.967Gbps (3G) through the transceiver TX pins. The video
pattern generator provides the input to this instance.
Arria 10 Transceiver Native PHY The Altera Arria 10 Transceiver Native PHY IP core. The reference
design uses this PHY IP to configure the transceiver PHY for the SDI II
protocol implementation. You can select the preset settings for the
PHY IP defined for the SDI II protocol. To apply a preset to the PHY
IP, double click the preset name. When you apply a preset, the PHY
parameters are set accordingly for the instance. For example, selecting
the 3G SDI PAL preset enables all parameters and ports for triple rates,
3G-SDI single rate, and SD-SDI single rate (2.97/1.001 Gbps).
TX/RX Transceiver PHY Reset
Controller
The Altera Transceiver PHY Reset Controller IP core. This reset
controller handles the sequencing of the transceiver reset. Depending
on the status received from the transceiver PHY, TX PLL, or the reset
input, the reset controller generates the TX or RX reset signals to the
transceiver PHY and TX PLL.
Loopback FIFO Buffer
This block contains a dual-clock FIFO (DCFIFO) buffer to handle the
data transmission across asynchronous clock domains—the receiver
recovered clock and transmitter clock out. The receiver sends the
decoded RX data to the transmitter through this FIFO buffer. When
the receiver is locked, the RX data is written to the FIFO buffer. The
transmitter starts reading, encoding, and transmitting the data when
half of the FIFO buffer is filled.
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Design Components
Name
Description
RX Transceiver Reconfiguration This block contains a state machine that performs the reconfiguration
Management
process. The Avalon-MM reconfiguration interface of this block is
connected to the Arria 10 Transceiver Native PHY for the reconfigura‐
tion of the SDI II IP core. Although this block suppports both TX and
RX reconfiguration, this reference design only implements RX reconfi‐
guration.
Phase Frequency Detector
The phase frequency detector (PFD) block controls the external clock
source from the VCXO (si516) block on the development board to
minimize the difference in PPM between the data rates of the receiver
and transmitter. This control is required to prevent data overflow or
underflow.
TX PLL
The Altera Arria 10 fPLL IP core. The reference design uses this IP core
as the TX PLL for the Arria 10 Transceiver Native PHY IP.
Pattern Generator
The video pattern generator produces the color bar or pathological test
patterns. The color bar can be configured as 100% or 75% amplitude.
The color bar pattern is the preferred pattern for image generation
while the pathological pattern can be used to stress the PLL and cable
equalizer of attached video equipment. This video pattern generator
can be configured to output various video formats at SD/HD/3G rates.
Related Information
• SDI II IP Core User Guide
Provides detailed description on the SDI II IP Core.
• Arria 10 Transceiver PHY IP Core User Guide
Provides detailed description on the Arria 10 Transceiver IP PHY IP Cores.
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Hardware and Software Requirements
5
Hardware and Software Requirements
The reference design requires the following hardware and software:
•
•
•
•
•
•
Arria 10 GX FPGA Development Board (10AX115S2F45I2SGE2)(1)
M21518 Single 3G Video Cable Driver
SMA cables, BNC male to mini-SMB plug cables, and BNC cables
Video scope
SDI II MegaCore Function
Quartus® II software version 15.0
Related Information
Reference Design Files
Click to download the design files.
(1)
The support for Arria 10 ES devices in the Quartus II software version 15.0 is preliminary.
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Setting up the Hardware
Setting up the Hardware
Complete the steps in the following topics to set up the required hardware.
Connecting the Development Board to the Cable Driver
Connect the J15 and J16 connectors on the Arria 10 GX FPGA development board to the SDIp and SDIn
connector pair on the M21518 Single Video 3G cable driver using the SMA cables.
Figure 2: Hardware Connection
Setting the DIP Switches
Set the DIP switches of the development board as specified in the following table.
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Setting up the Hardware
7
Table 2: DIP Switch Control Settings
DIP Switch
Schematic
Signal Name
Description
Setting
1
X1
ON for PCIe X1
ON
SW3
2
X4
ON for PCIe X4
ON
(PCIe)
3
X8
ON for PCIe X8
ON
4
—
OFF for 1.35 V MEM_VDD power rail
OFF
1
Arria 10
OFF to enable the Arria 10 in the JTAG chain
OFF
2
MAX V
OFF to enable the MAX V in the JTAG chain
OFF
3
FMCA
ON to bypass the FMCA connector in the
JTAG chain
ON
4
FMCB
ON to bypass the FMCB connector in the
JTAG chain
ON
1
MSEL0
ON for MSEL0 = 1; for FPP standard mode
OFF
SW5
2
MSEL1
ON for MSEL1 = 0; for FPP standard mode
OFF
(Configura‐
tion)(2)
3
MSEL2
ON for MSEL2 = 0; for FPP standard mode
ON
4
VIDEN
OFF for enabling VID_EN for the Smart
Voltage ID (SmartVID) feature
ON
1
CLK_SEL
ON for 100Mhz on-board clock oscillator
selection
ON
SW4
(JTAG)
OFF for SMA input clock selection
2
CLK_EN
OFF for setting CLK_ENABLE signal high to
the MAX V
OFF
3
Si516_FS
ON for setting the SDI REFCLK frequency to
148.35Mhz
OFF
SW6
OFF for setting the SDI REFCLK frequency to
148.5Mhz
(Board
Settings)
4
FACTORY
ON to load user hardware from flash
ON
OFF to load factory from flash
5
RZQ_B2K
ON for setting RZQ resistor of Bank 2K to
99.17ohm
OFF
OFF for setting RZQ resistor of Bank 2K to 240
ohm
(2)
Set the MSEL [2:0] bits according to your chosen configuration scheme.
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Setting up the Hardware
Connecting the Hardware to the Power Supplies
Connect the following hardware to the respective power supply:
1. The development board to the 12V DC input (J13) power supply.
2. The J6 and J9 inputs of the M21518 Single Video 3G cable driver to a 3.3V power supply.
3. The J1 input of the M21518 Single Video 3G cable driver to a GND power supply.
Port Assignments
When the hardware is set up, the following physical ports are assigned to the SDI channels.
Table 3: SDI Channels and Ports
SDI
Channel
Hardware
0
Arria 10 GX development board
1
M21518 single 3G video cable driver
Altera Corporation
RX Port
SDI_RX_P
–
(J20)
TX Port
SDI_TX_P
(J21)
SDO_A (J16)
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Compiling the Design and Configuring the FPGA
9
Compiling the Design and Configuring the FPGA
You must compile the design before you can configure the FPGA. Because the design is volatile, you must
reload the design each time you power on the board.
Follow these steps to compile the design and configure the FGPA:
1. Download the reference design file (a10_top_an746.zip) and unzip the files in your local project
directory.
2. Launch the Quartus II software.
3. On the Project menu, click Restore Archived Project. Select the archive name and the destination
folder.
4. On the Processing menu, click Start Compilation.
5. Before you begin the FPGA configuration, ensure that the Quartus II Programmer and the USBBlaster II driver are installed on the host computer, the board is powered, and no other applications
that use the JTAG chain are running.
6. Connect the USB cable to the board.
7. On the Tools menu, click Programmer.
8. Click Auto Detect to display the devices in the JTAG chain and select 10AX115S2E2.
9. Right click and select Change File. Then, select the a10_top.sof file from the project directory and click
Open.
10.Turn on the Program/Configure option for the .sof file.
11.Click Start to download the .sof file to the FPGA. Configuration is complete when the progress bar
reaches 100%.
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Running the Design
Running the Design
When the board is set up and the FPGA is configured, you can start running the demonstration tests.
Subsequent topics describe the tests that you can run.
Table 4: DIP Switch
Use the SW2 DIP switches to specify the input and output type for the tests. A logical 0 indicates that the switch is
ON; a logical 1 indicates that the switch is OFF
SW2
Description
8
• 0: 75% color bars
• 1: 100% color bars
7
• 0: Output color bars
• 1: Output pathological
6
• 0: Output color
• 1: Output no color
5
Unused
4:1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0000: SD – 525i59.94
0001: SD – 625i50
0010: HD – 1080i60
0011: HD – 1080i50
0100: HD – 1080p24
0101: HD – 720p60
0110: HD – 720p30
0111: HD – 1080p30
1000: HD – 1080p25
1001: 3Ga – 1080p60
1010: 3Ga – 1080p50
1011: 3Gb – 2x1080i60
1100: 3Gb – 2x720p30
1101: 3Gb – 2x1080p30
1110: 3Gb – 1080p60
1111: 3Gb – 1080p50
Table 5: User LEDs
The User LEDs indicate the expected results. A logical 1 indicates that the LED illuminates, a logical 0 indicates
otherwise.
User LEDs
D3
Altera Corporation
Description
The heartbeat of the transmitter clock out for channel 0.
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Running the Design
User LEDs
Description
D4
The heartbeat of the receiver recovered clock out for channel 0.
D5
Frame locked for channel 0.
D6
TRS locked for channel 0.
D7, D8
RX signal standard for channel 0:
•
•
•
•
D9, D10
SD: [D7, D8]=00
HD: [D7, D8]=01
3Ga: [D7, D8]=11
3Gb: [D7, D8]=10
Internal pattern generator signal standard for channel 1:
•
•
•
•
SD: [D9, D10]=00
HD: [D9, D10]=01
3Ga: [D9, D10]=11
3Gb: [D9, D10]=10
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Test Pattern Transmitter
Test Pattern Transmitter
Follow these steps to run the test:
1. Ensure that the J15 and J16 connectors on the Arria 10 GX FPGA development board are connected to
the SDIp and SDIn connector pair on the M21518 Single Video 3G cable driver.
2. Connect an SDI signal analyzer to the SDI transmitter output, SDO_A (J16), on the M21518 single
video 3G cable driver.
3. Use the SW2 switches to change the input or output type.
4. Check the result on the SDI signal analyzer.
The test demonstrates the following operations:
• Channel 1 generates and transmits the video data from the Transceiver TX SMA connector pair J15
and J16 on the development board to the SMA connector pair SDIp and SDIn on the M21518 single
video 3G cable driver.
• The cable driver then transmits the SDI signal at the connector SDO_A (J16).
• The following user LEDs indicate the respective conditions:
Figure 3: User LEDs
D3
D4
D5
D6
D7
D8
D9
D10
Arria 10 GX Development Kit User LEDs
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Receiver
13
Receiver
To run the test, connect an SDI signal generator to the receiver input, SDI_RX_P (J20), of channel 0.
This test uses the following user LEDs to indicate the respective conditions:
• D7 and D8 indicate the receiver signal standard.
• D6 illuminates when the trs_locked signal for channel 0 is asserted.
• D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 4: User LEDs
D3
D4
D5
D6
D7
D8
D9
D10
Arria 10 GX Development Kit User LEDs
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Serial Loopback
Serial Loopback
Follow these steps to run the test:
1. Connect the transmitter output, SDO_A (J16), of channel 1 to the receiver input, SDI_RX_P (J20), of
channel 0.
2. Use the SW2 switches to change the input or output type.
This test uses the following user LEDs to indicate the respective conditions:
• D9 and D10 indicate the internal pattern generator standard, which transmits through channel 1 of the
transmitter.
• D7 and D8 indicate the receiver signal standard.
• D6 illuminates when the trs_locked signal for channel 0 is asserted.
• D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 5: User LEDs
D3
D4
D5
D6
D7
D8
D9
D10
Arria 10 GX Development Kit User LEDs
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Parallel Loopback
15
Parallel Loopback
Follow these steps to run the test:
1. Connect an SDI signal generator to the receiver input, SDI_RX_P (J20), of channel 0.
2. Connect an SDI signal analyzer to the transmitter output, SDI_TX_P (J21), of channel 0.
3. Check the result on the SDI signal analyzer.
This test uses the following user LEDs to indicate the respective conditions:
• D7 and D8 indicate the receiver signal standard.
• D6 illuminates when the trs_locked signal for channel 0 is asserted.
• D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 6: User LEDs
D3
D4
D5
D6
D7
D8
D9
D10
Arria 10 GX Development Kit User LEDs
Document Revision History
Date
Version
Changes
June 2015
2015.06.29
Initial release.
August 2015
2015.08.31
Updated the document structure.
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