User manual | TMS320C6655/57 Fixed and Floating Point

associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].

2.5 Boot Modes Supported and PLL Settings

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[2:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:

•

Public ROM Boot

- C66x CorePac0 is released from reset and begins executing from the L3 ROM base address. After performing the boot process (e.g., from I

C ROM, Ethernet, or RapidIO), C66x CorePac0 then begins execution from the provided boot entry point. For C6657 only, the other C66x CorePac is released from reset and begins executing an IDLE from the L3 ROM. It is then released from IDLE based on interrupts generated by C66x CorePac0. See the Bootloader for the C66x DSP User Guide in

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

•

Secure ROM Boot

- On secure devices, the C66x CorePac0 is released from reset and begin executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which C66x CorePac0 initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the bootloaded image prior to beginning execution.

The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the

Figure 2-2 Boot Mode Pin Decoding

12 11 10

PLL Mult I

C /SPI Ext Dev Cfg

9 8 7

Boot Mode Pins

Device Configuration

5 4 3 2 1

Boot Device

2.5.1 Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 shows the supported boot

modes.

Table 2-3

Bit

2-0

Boot Mode Pins: Boot Device Values

Field

Boot Device

Description

Device boot mode

0 = EMIF16 / UART / No Boot

1 = Serial Rapid I/O

2 = Ethernet (SGMII)

3 = NAND

4 = PCIe

5 = I

6 = SPI

7 = HyperLink

End of Table 2-3

2.5.2 Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode.

2.5.2.1 EMIF16 / UART / No Boot Device Configuration

Figure 2-3

EMIF16 / UART / No Boot

Configuration Fields

8 7

Sub-Mode Specific Configuration

6 5 4

Sub-Mode

Submit Documentation Feedback

Device Overview 25

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-4

Bit

9 - 6

5-3

EMIF16 / UART / No Boot

Configuration Field Descriptions

Field

Sub-Mode

Specific

Configuration

Sub-Mode

Description

Configures the selected sub-mode. See sections 2.5.2.1.1

‘‘No Boot Mode’’ , 2.5.2.1.2

‘‘UART Boot Mode’’ , and

2.5.2.1.3

‘‘EMIF16 Boot Mode’’

Sub mode selection.

0 = No boot

1 = UART port 0 boot

2 - 3 = Reserved

4 = EMIF16 boot

5 = UART port 1 boot

6 - 7 = Reserved

End of Table 2-4 www.ti.com

2.5.2.1.1 No Boot Mode

Figure 2-4

No Boot Configuration Fields

Table 2-5

Bit Field

9 - 6 Reserved

End of Table 2-5

No Boot Configuration Field Descriptions

Description

Reserved

2.5.2.1.2 UART Boot Mode

Figure 2-5

UART Boot Configuration Fields

Speed

Table 2-6

Bit

9 - 8

Field

Speed

7-6 Parity

UART Boot Configuration Field Descriptions

Description

UART interface speed.

0 = 115200 baud

1 = 38400 baud

2 = 19200 baud

3 = 9600 baud

UART parity used during boot.

0 = None

1 = Odd

2 = Even

4 = None

End of Table 2-6

Reserved

Parity

Submit Documentation Feedback

www.ti.com

2.5.2.1.3 EMIF16 Boot Mode

Figure 2-6 EMIF16 Boot Configuration Fields

Wait Enable

Width Select

Table 2-7

Bit

7-6

EMIF16 Boot Configuration Field Descriptions

Field

Wait Enable

Width Select

Chip Select

Description

Extended Wait mode for EMIF16.

0 = Wait enable disabled (EMIF16 sub mode)

1 = Wait enable enabled (EMIF16 sub mode)

EMIF data width for EMIF16.

0 = 8-bit wide EMIF (EMIF16 sub mode)

1 = 16-bit wide EMIF (EMIF16 sub mode)

EMIF Chip Select used during EMIF 16 boot.

0 = CS2

1 = CS3

2 = CS4

4 = CS5

End of Table 2-7

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Chip Select

2.5.2.2 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.

Figure 2-7 Serial Rapid I/O Device Configuration Fields

Lane Setup

Data Rate

7 6

Ref Clock

5 4

Reserved

Table 2-8

Bit

8-7

6-5

Serial Rapid I/O Configuration Field Descriptions

Field

Lane Setup

Data Rate

Ref Clock

4-3 Reserved

End of Table 2-8

Description

SRIO port and lane configuration

0 = Port Configured as 4 ports each 1 lane wide (4 -1× ports)

1 = Port Configured as 2 ports 2 lanes wide (2 – 2× ports)

SRIO data rate configuration

0 = 1.25 GBaud

1 = 2.5 GBaud

2 = 3.125 GBaud

3 = 5.0 GBaud

SRIO reference clock configuration

0 = 156.25 MHz

1 = 250 MHz

2 = 312.5 MHz

3 = Reserved

Reserved

In SRIO boot mode, the message mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.

Submit Documentation Feedback

Device Overview 27

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

2.5.2.3 Ethernet (SGMII) Boot Device Configuration

Figure 2-8

Ethernet (SGMII) Device Configuration Fields

8 7

SerDes Clock Mult Ext connection

6 5 4

Device ID

Table 2-9

Bit

9-8

7-6

Ethernet (SGMII) Configuration Field Descriptions

Field

SerDes Clock Mult

Ext connection

5-3 Device ID

End of Table 2-9

Description

SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.

0 = ×8 for input clock of 156.25 MHz

1 = ×5 for input clock of 250 MHz

2 = ×4 for input clock of 312.5 MHz

3 = Reserved

External connection mode

0 = MAC to MAC connection, master with auto negotiation

1 = MAC to MAC connection, slave, and MAC to PHY

2 = MAC to MAC, forced link

3 = MAC to fiber connection

This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.

2.5.2.4 NAND Boot Device Configuration

Figure 2-9

NAND Device Configuration Fields

8 7

1 st

Block

6 5 4

Table 2-10

Bit

9-5

Field

1 st

Block

NAND Configuration Field Descriptions

3 Reserved

End of Table 2-10

Description

NAND Block to be read first by the boot ROM.

0 = Block 0

...

31 = Block 31

NAND parameters read from I

C EEPROM

0 = Parameters are not read from I

1 = Parameters are read from I

Reserved

2.5.2.5 PCI Boot Device Configuration

Extra device configuration is provided in the PCI bits in the DEVSTAT register.

Figure 2-10 PCI Device Configuration Fields

Ref Clock

8 7

BAR Config

6 5 4

Reserved

3 www.ti.com

Reserved

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 2-11

Bit

8-5

PCI Device Configuration Field Descriptions

Field

Ref Clock

BAR Config

4-3 Reserved

End of Table 2-11

Description

PCIe reference clock configuration

0 = 100 MHz

1 = 250 MHz

PCIe BAR registers configuration

This value can range from 0 to 0xf. See Table 2-12 .

Reserved

Table 2-12 BAR Config / PCIe Window Sizes

BAR cfg

0b0000

0b0001

0b0010

0b0011

0b0100

0b0101

0b0110

BAR0

0b0111

0b1000

0b1001

0b1010

0b1011

0b1100

0b1101

0b1110

0b1111

End of Table 2-12

PCIe MMRs

BAR1

128

BAR2

32-Bit Address Translation

BAR3 BAR4

128

256

128

256

128

256

BAR5

Clone of BAR4

64-Bit Address Translation

BAR2/3 BAR4/5

256

512

1024

2048

256

512

1024

2048

2.5.2.6 I

C Boot Device Configuration

2.5.2.6.1 I

C Master Mode

In master mode, the I

C device configuration uses ten bits of device configuration instead of seven as used in other boot modes. In this mode, the device will make the initial read of the I

C EEPROM while the PLL is in bypass mode.

The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.

Figure 2-11 I

C Master Mode Device Configuration Bit Fields

Mode

Address

10 9

Speed

8 7 6 5

Parameter Index

4 3

Submit Documentation Feedback

Device Overview 29

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-13

Bit

Field

Mode

11 - 10 Address

8-3

Speed

C Master Mode Device Configuration Field Descriptions

Parameter Index

Description

C operation mode

0 = Master mode

1 = Passive mode (see section 2.5.2.6.2

‘‘I

C Passive Mode’’ )

C bus address configuration

0 = Boot from I

C EEPROM at I

C bus address 0x50

1 = Boot from I

C EEPROM at I

C bus address 0x51

2= Boot from I

C EEPROM at I

C bus address 0x52

3= Boot from I

C EEPROM at I

C bus address 0x53

C data rate configuration

0 = I

C slow mode. Initial data rate is SYSCLKIN / 5000 until PLLs and clocks are programmed

1 = I

C fast mode. Initial data rate is SYSCLKIN / 250 until PLLs and clocks are programmed

Identifies the index of the configuration table initially read from the I

C EEPROM

This value can range from 0 to 31.

End of Table 2-13 www.ti.com

2.5.2.6.2 I

C Passive Mode

In passive mode, the device does not drive the clock, but simply acks data received on the specified address.

Figure 2-12 I

C Passive Mode Device Configuration Bit Fields

Mode

11 10 9 8

Address

7 6 5 4

Reserved

Table 2-14

Bit

Field

Mode

11 - 5 Address

4 - 3 Reserved

End of Table 2-14

C Passive Mode Device Configuration Field Descriptions

Description

C operation mode

0 = Master mode (see section 2.5.2.6.1

‘‘I

C Master Mode’’ )

1 = Passive mode

C bus address accepted during boot. Value may range from 0x00 to 0x7F

Reserved

2.5.2.7 SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other boot modes.

Figure 2-13 SPI Device Configuration Bit Fields

Mode

11 10

4, 5 Pin

Addr Width

Chip Select

7 6 5 4

Parameter Table Index

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 2-15 SPI Device Configuration Field Descriptions

Bit

12-11

Field

Mode

4, 5 Pin

Description

Clk Pol / Phase

0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.

1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK.

2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.

3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK.

SPI operation mode configuration

0 = 4-pin mode used

1 = 5-pin mode used

9 Addr Width SPI address width configuration

0 = 16-bit address values are used

1 = 24-bit address values are used

The chip select field value 8-7 Chip Select

6-3 Parameter Table Index Specifies which parameter table is loaded

End of Table 2-15

2.5.2.8 HyperLink Boot Device Configuration

Figure 2-14

Reserved

HyperLink Boot Device Configuration Fields

8 7

Data Rate

Ref Clock

Table 2-16

Bit

8-7

Field

Reserved

Data Rate

6-5

HyperLink Boot Device Configuration Field Descriptions

Ref Clocks

4-3 Reserved

End of Table 2-16

Description

Reserved

HyperLink data rate configuration

0 = 1.25 GBaud/s

1 = 3.125 GBaud/s

2 = 6.25 GBaud/s

3 = Reserved

HyperLink reference clock configuration

0 = 156.25 MHz

1 = 250 MHz

2 = 312.5 MHz

3 = Reserved

Reserved

5 4

Reserved

Submit Documentation Feedback

Device Overview 31

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

2.5.3 PLL Boot Configuration Settings

The PLL default settings are determined by the BOOTMODE[12:10] bits. The following table shows settings for various input clock frequencies.

Table 2-17 C66x DSP System PLL Configuration

(1)

BOOTMODE

[12:10]

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

End of Table 2-17

Input Clock

Freq (MHz)

80.00 3

PLLD

850 MHz Device

PLLM DSP ƒ

850.04

850

849.92

PLLD

1000 MHz Device

PLLM

1 The PLL boot configuration table above may not include all the frequency values that the device supports.

DSP ƒ

PLLD

1250 MHz Device

PLLM DSP ƒ

1250

1250.063

124

1250

589

1250

1249.986

OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting for the device (with OUTPUT_DIVIDE=2, by default).

CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1))

The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL is controlled by chip level

MMRs. For details on how to set up the PLL see section 7.5

‘‘Main PLL and PLL Controller’’ on page 126. For details

on the operation of the PLL controller module, see the Phase Locked Loop (PLL)

Controller for KeyStone Devices User Guide in

2.6 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any level of customization to current boot methods as well as the definition of a completely customized boot.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

2.7 Terminals

2.7.1 Package Terminals

Figure 2-15

shows the TMS320C6655/57CZH and GZH ball grid area (BGA) packages (bottom view).

Figure 2-15 CZH/GZH 625-Pin BGA Package (Bottom View)

1 3 5 7 9 11 13 15 17 19 21 23 25

2 4 6 8 10 12 14 16 18 20 22 24

2.7.2 Pin Map

Figure 2-17

through Figure 2-20

show the TMS320C6655/57 pin assignments in four quadrants (A, B, C, and D).

Figure 2-16 Pin Map Quadrants (Bottom View)

A B

D C

Submit Documentation Feedback

Device Overview 33

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 2-17

Upper Left Quadrant—A (Bottom View)

2 3 4 5 6 7 8 9 10 11 12 13

VSS

SGMII0

RXN

SGMII0

RXP

VSS RIORXN2 RIORXP2 VSS RIORXP0 RIORXN0 VSS PCIERXP0 PCIERXN0 VSS

VSS VSS VSS RIORXN3 RIORXP3 VSS RIORXP1 RIORXN1 VSS PCIERXN1 PCIERXP1 VSS

SRIOSGMII

CLKP

VSS

SGMII0

TXN

SGMII0

TXP

VSS RIOTXN2 RIOTXP2 VSS RIOTXP0 RIOTXN0 VSS PCIETXP0 PCIETXN0 VSS

EMIFD14 VSS RSV19 RIOTXN3 RIOTXP3 VSS RIOTXN1 RIOTXP1 VSS PCIETXP1 PCIETXN1 VSS SPIDOUT

EMIFD13 EMIFD15 VDDR3 VSS VDDR4 VSS RSV17 VSS VDDR2 VSS RSV18 SPISCS0 SPICLK

EMIFD09 EMIFD11 DVDD18 RSV13 RSV12 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS DVDD18

EMIFD06 EMIFD08 VSS EMIFD10 EMIFD12 DVDD18 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS

EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD07 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD

EMIFA21 EMIFA22 EMIFA23 EMIFD00 EMIFD01 DVDD18 VSS CVDD1 VSS CVDD VSS CVDD VSS

EMIFA19 VSS DVDD18 EMIFA18 EMIFA20 VSS DVDD18 VSS CVDD1 VSS CVDD VSS CVDD

EMIFA17 EMIFA16 EMIFA14 EMIFA15 EMIFA13 DVDD18 VSS VSS VSS CVDD VSS CVDD VSS

EMIFA12 EMIFA11 EMIFA09 EMIFA05 EMIFA03 VSS DVDD18 VSS

EMIFA10 EMIFA08 DVDD18 VSS

EMIF

WAIT0

DVDD18 VSS CVDD

CVDD VSS CVDD VSS CVDD

VSS CVDD VSS CVDD VSS

www.ti.com

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Figure 2-18

14 15

Upper Right Quadrant—B (Bottom View)

16 17 18 19 20

SRIOSGMII

CLKN

PCIECLKN UARTCTS1 TDI

TMS CORECLKN TIMO1 TIMI1

DX1

PCIECLKP UARTRTS1 VSS

23 24 25

FSX1 CLKX1 VSS

TCK CORECLKP TDO TIMI0 DR1 FSR1 CLKR1 FSR0 EMU16

UARTRXD1 UARTTXD1 DVDD18 UARTCTS RSV04 TIMO0 DVDD18 CLKS1 DX0 CLKS0 EMU17 EMU13

SPIDIN UARTRXD MDIO UARTRTS RSV05 TRST VSS DR0 EMU15 DVDD18 VSS EMU12

SPISCS1 UARTTXD MDCLK SCL SDA SYSCLKOUT FSX0 CLKR0 RSV01 EMU14 EMU10 EMU11

VSS AVDDA1 VSS DVDD18 POR RSV08 CLKX0 EMU18 EMU09 EMU07 EMU06 EMU05

DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 GPIO14 EMU08 EMU03 EMU04 EMU02

VSS CVDD VSS CVDD VSS DVDD18 VSS GPIO15 GPIO13 GPIO10 EMU00 EMU01

CVDD VSS CVDD VSS CVDD1 VSS DVDD18 GPIO11 GPIO08 GPIO09 GPIO05 GPIO03

VSS CVDD VSS CVDD1 VSS DVDD18 VSS GPIO12 GPIO06 GPIO04 DVDD18 GPIO00

CVDD VSS CVDD VSS CVDD VSS DVDD18 GPIO07 VSS GPIO02 VSS GPIO01

VSS CVDD VSS CVDD VSS CVDD VSS VSS MCMTXN0 VSS MCMRXN0 VSS

CVDD VSS CVDD VSS CVDD VSS VDDT1 MCMTXN1 MCMTXP0 VSS MCMRXP0 MCMRXP1

Submit Documentation Feedback

Device Overview 35

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 2-19 Lower Right Quadrant—C (Bottom View)

VSS CVDD VSS CVDD VSS VDDT1 VDDR1

MCM

TXP1

VSS VSS VSS MCMRXN1

CVDD VSS CVDD VSS CVDD VSS VDDT1 VSS MCMTXP2 VSS MCMRXP3 VSS

VSS CVDD VSS CVDD1 VSS VDDT1 VSS MCMTXP3 MCMTXN2 VSS MCMRXN3 MCMRXP2

CVDD VSS CVDD VSS CVDD1 VSS RSV16 MCMTXN3 VSS VSS VSS MCMRXN2

VSS CVDD VSS CVDD VSS DVDD18 VSS VSS RSV11 VSS DVDD18 VSS

DVDD15 VSS DVDD15 VSS DVDD15 RSV0A RSV0B RSV15 RSV10 VCNTL3

MCMTX

PMDAT

MCMREF

CLKOUTP

VSS PTV15 VSS DVDD15 VSS DVDD15 AVDDA2 RSV14 RSV20 VCNTL2

MCMTX

PMCLK

MCMREF

CLKOUTN

DDRODT0 DDRA03 DDRA02 DDRA15 DDRA14 DDRA10 DDRA09 DVDD18 VCNTL0 VCNTL1

MCMRX

PMCLK

MCMTX

FLCLK

DDRCAS DVDD15 DDRA00 DDRBA1 DDRA12 DVDD15 DDRA08 VSS

DDRSL

RATE1

RSV21

MCMRX

PMDAT

MCMTX

FLDAT

DDRCE1 VSS DDRA06 DVDD15 DDRBA0 VSS DDRA13 DVDD15

DDRSL

RATE0

RSV09

MCMRX

FLDAT

MCMCLKP

DDRCLK

OUTN0

DDRCE0 DDRRESET VSS DDRA04 DDRBA2 DDRA11

DDRCLK

OUTN1

DDRCLKN RSV06

MCMRX

FLCLK

MCMCLKN

DDRCLK

OUTP0

DDRRAS DDRCKE0 DDRA05 DDRA07 DDRA01 DDRCKE1

DDRCLK

OUTP1

DDRCLKP RSV07 DVDD18 VSS

14 15 16 17 18 19 20 21 22 23 24 25 www.ti.com

Submit Documentation Feedback

www.ti.com

Figure 2-20 Lower Left Quadrant—D (Bottom View)

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

EMIFA07 EMIFA06 EMIFA01 EMIFWAIT1 EMIFCE3 VSS DVDD18 VSS CVDD

EMIFA04 EMIFA02 EMIFBE1 EMIFOE

EMIF

RNW

DVDD18 VSS CVDD

VSS CVDD VSS CVDD

VSS CVDD VSS CVDD VSS

EMIFA00 VSS DVDD18 EMIFWE EMIFCE0 VSS DVDD18 VSS CVDD1 VSS CVDD VSS CVDD

EMIFBE0 EMIFCE2 RSV02 RESETFULL CORESEL0 DVDD18 VSS CVDD1 VSS

NMI RSV03

BOOT

COMPLETE

RESET RESETSTAT VSS DVDD18 VSS CVDD

CVDD VSS CVDD VSS

VSS CVDD VSS CVDD

EMIFCE1 HOUT DVDD18 LRESET CORESEL1 DVDD18 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS

LRESET

NMIEN

DDRD25 VSS DDRD18 DDRDQM2 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15

DDRDQM3 DDRD24 DDRD31 DDRD19 DDRD16 DDRD08

DDR

DQM1

DDRD09 DDRD04 DDRD05 VSS VREFSSTL DDRWE

DDRD28 DVDD15 DDRD29 DVDD15 DDRD23 DDRD12 DDRD14 DVDD15 DDRD02

DDR

DQS0P

DDRCB00 DDRODT1 DVDD15

DDRD27 VSS DDRD30 VSS DDRD22 DVDD15 DDRD13 VSS DDRD01

DDR

DQS0N

DDRCB02 DDRDQM8 VSS

DDRD26

DDR

DQS3N

DDRD17

DDR

DQS2P

DDRD21 VSS

DDR

DQS1P

DDRD15 DDRD03 DVDD15 DDRD07 DDRCB01

DDR

DQS8P

VSS

DDR

DQS3P

DDRD20

DDR

DQS2N

DDRD11 DDRD10

DDR

DQS1N

DDR

DQM0

DDRD00 VSS DDRD06 DDRCB03

DDR

DQS8N

1 2 3 4 5 6 7 8 9 10 11 12 13

Submit Documentation Feedback

Device Overview 37

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

2.8 Terminal Functions

The terminal functions table (

Table 2-19 ) identifies the external signal names, the associated pin (ball) numbers, the

pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin

descriptions. This table is arranged by function. The power terminal functions table ( Table 2-20 ) lists the various

power supply pins and ground pins and gives functional pin descriptions.

Table 2-21 shows all pins arranged by

signal name.

Table 2-22 shows all pins arranged by ball number.

There are 73 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (†). There is one pin that has a tertiary function as well as primary and secondary functions. The tertiary function is indicated with a double dagger (‡).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and

pullup/pulldown resistors, see section 3.4

‘‘Pullup/Pulldown Resistors’’ on page 86.

Use the symbol definitions in

Table 2-18 when reading Table 2-19 .

Table 2-18 I/O Functional Symbol Definitions

Functional

Symbol

IPD or IPU

Definition

Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-k

Ω resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for

KeyStone Devices in

Analog signal

Ground

GND

Input terminal

Output terminal

S Supply voltage

End of Table 2-18

Three-state terminal or high impedance

Table 2-19

Column Heading

IPD/IPU

Type

Table 2-19

Signal Name

LENDIAN †

BOOTMODE00 †

BOOTMODE01†

BOOTMODE02 †

BOOTMODE03 †

BOOTMODE04 †

BOOTMODE05 †

BOOTMODE06 †

BOOTMODE07 †

BOOTMODE08 †

BOOTMODE09 †

BOOTMODE10 †

BOOTMODE11 †

BOOTMODE12 †

Terminal Functions — Signals and Control by Function (Part 1 of 13)

V23

U21

T21

V22

T22

R21

U22

U23

R23

U25

T23

U24

Ball No. Type IPD/IPU Description

Boot Configuration Pins

T25

R25

IOZ

Down

Endian configuration pin (Pin shared with GPIO[0])

IOZ

Down

IOZ

Down

See Section 2.5

‘‘Boot Modes Supported and PLL Settings’’

(Pins shared with GPIO[1:13])

on page 24 for more details

Submit Documentation Feedback

CORECLKP

CORECLKN

SRIOSGMIICLKP

SRIOSGMIICLKN

DDRCLKP

DDRCLKN

PCIECLKP

PCIECLKN

MCMCLKP

MCMCLKN

AVDDA1

AVDDA2

SYSCLKOUT

HOUT

NMI

LRESET

LRESETNMIEN

CORESEL0

CORESEL1

RESETFULL

RESET

POR

RESETSTAT

BOOTCOMPLETE

PTV15

www.ti.com

Table 2-19

Signal Name

PCIESSMODE0 †

PCIESSMODE1 †

PCIESSEN

‡

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRDQM8

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions — Signals and Control by Function (Part 2 of 13)

C12

Y18

F15

AA19

C25

B25

Y15

F20

A22

B22

AD14

AE15

Ball No. Type IPD/IPU Description

W21

V21

AD20 I

IOZ

Down

PCIe Mode selection pins (Pins shared with GPIO[14:15])

PCIe module enable (Pin shared with TIMI0 and GPIO16)

Clock / Reset

AD18

AE19

AD13

AE14

Core Clock Input to main PLL.

RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes

DDR Reference Clock Input to DDR PLL

PCIe Clock Input to drive PCIe SerDes

HyperLink Reference Clock to drive the HyperLink SerDes

Down

SYS_CLK PLL Power Supply Pin

DDR_CLK PLL Power Supply Pin

System Clock Output to be used as a general purpose output clock for debug purposes

Interrupt output pulse created by IPCGRH

Non-maskable Interrupt

Warm Reset

Enable for core selects

Select for the target core for LRESET and NMI. For more details see Table 7-42

Timing Requirements’’ on page 168

‘‘NMI and Local Reset

Down

Full Reset

Warm Reset of non isolated portion on the IC

Power-on Reset

Reset Status Output

Boot progress indication output

PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15 pin and ground is used to closely tune the output impedance of the DDR interface drivers to 50 Ohms.

Presently, the recommended value for this 1% resistor is 45.3 Ohms.

DDR

DDR EMIF Data Masks

Submit Documentation Feedback

Device Overview 39

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-19 Terminal Functions — Signals and Control by Function (Part 3 of 13)

DDRD08

DDRD09

DDRD10

DDRD11

DDRD12

DDRD13

DDRD14

DDRD15

DDRD00

DDRD01

DDRD02

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

Signal Name

DDRDQS0P

DDRDQS0N

DDRDQS1P

DDRDQS1N

DDRDQS2P

DDRDQS2N

DDRDQS3P

DDRDQS3N

DDRDQS8P

DDRDQS8N

DDRCB00

DDRCB01

DDRCB02

DDRCB03

DDRD16

DDRD17

DDRD18

DDRD19

DDRD20

DDRD21

DDRD22

DDRD23

DDRD24

DDRD25

DDRD26

DDRD27

DDRD28

DDRD29

IOZ

E10

A11

B11

D11

B12

C11

A12

B13

A13

Ball No. Type IPD/IPU Description

D10

C10

IOZ

DDR EMIF Data Strobe

IOZ

DDR EMIF Check Bits

DDR EMIF Data Bus

40 Device Overview

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 2-19

DDRA07

DDRA08

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRA14

DDRA15

DDRCAS

DDRRAS

DDRWE

DDRCKE0

DDRCKE1

DDRCLKOUTP0

DDRCLKOUTN0

Signal Name

DDRD30

DDRD31

DDRCE0

DDRCE1

DDRBA0

DDRBA1

DDRBA2

DDRA00

DDRA01

DDRA02

DDRA03

DDRA04

DDRA05

DDRA06

DDRCLKOUTP1

DDRCLKOUTN1

DDRODT0

DDRODT1

DDRRESET

DDRSLRATE0

DDRSLRATE1

VREFSSTL

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions — Signals and Control by Function (Part 4 of 13)

A16

A20

A14

B14

E17

D14

A15

E13

B20

D18

C20

E18

A18

D20

E20

E19

B16

C22

D22

E12

A21

B21

E14

D12

E15

B18

A17

C16

B19

D16

A19

E16

Ball No. Type IPD/IPU Description

IOZ

DDR EMIF Data Bus

B15

C14

C18

D17

DDR EMIF Chip Enables

DDR EMIF Bank Address

Down

DDR EMIF Address Bus

DDR EMIF Column Address Strobe

DDR EMIF Row Address Strobe

DDR EMIF Write Enable

DDR EMIF Clock Enable

DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)

DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDR Reset signal

DDR Slew rate control

Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)

Submit Documentation Feedback

Device Overview 41

EMIFA08

EMIFA09

EMIFA10

EMIFA11

EMIFA12

EMIFA13

EMIFA14

EMIFA15

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA04

EMIFA05

EMIFA06

EMIFA07

EMIFA16

EMIFA17

EMIFA18

EMIFA19

EMIFA20

EMIFA21

EMIFA22

EMIFA23

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-19 Terminal Functions — Signals and Control by Function (Part 5 of 13)

Signal Name Ball No. Type IPD/IPU Description

EMIF16

EMIFRW

EMIFCE0

EMIFCE1

EMIFCE2

EMIFCE3

EMIFOE

EMIFWE

EMIFBE0

EMIFBE1

EMIFWAIT0

EMIFWAIT1

Down

EMIF16 Control Signals

www.ti.com

EMIF16 Control Signal

This EMIF16 pin has a secondary function assigned to it as mentioned elsewhere in this table:

‘‘uPP’’ on page 43

Down

EMIF16 Address

These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this table:

‘‘uPP’’ on page 43

Submit Documentation Feedback

www.ti.com

Table 2-19

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions — Signals and Control by Function (Part 6 of 13)

Signal Name

EMIFD00

EMIFD01

EMIFD02

EMIFD03

EMIFD04

EMIFD05

EMIFD06

EMIFD07

EMIFD08

EMIFD09

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFD15

UPP_2XTXCLK †

UPP_CH0_CLK †

UPP_CH0_START †

UPP_CH0_ENABLE †

UPP_CH0_WAIT †

UPP_CH1_CLK †

UPP_CH1_START †

UPP_CH1_ENABLE †

UPP_CH1_WAIT †

AA1

AB1

AA2

Ball No. Type IPD/IPU Description

IOZ

Down

IOZ

Down

IOZ

Down

EMIF16 Data

These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this table:

‘‘uPP’’ on page 43.

IOZ

Down

uPP

uPP Transmit Reference Clock (2x Transmit Rate)

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 0 Clock

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 0 Start

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 0 Enable

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 0 Wait

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 1 Clock

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 1 Start

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 1 Enable

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

uPP Channel 1 Wait

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

Submit Documentation Feedback

Device Overview 43

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-19 Terminal Functions — Signals and Control by Function (Part 7 of 13)

UPPD14 †

UPPD15 †

UPPXD00 †

UPPXD01 †

UPPXD02 †

UPPXD03 †

UPPXD04 †

UPPXD05 †

UPPXD06 †

UPPXD07 †

UPPXD08 †

UPPXD09 †

UPPXD10 †

UPPXD11 †

UPPXD12 †

UPPXD13 †

UPPXD14 †

UPPXD15 †

Signal Name

UPPD00 †

UPPD01 †

UPPD02 †

UPPD03 †

UPPD04 †

UPPD05 †

UPPD06 †

UPPD07 †

UPPD08 †

UPPD09 †

UPPD10 †

UPPD11 †

UPPD12 †

UPPD13 †

www.ti.com

IOZ

AB1

AA2

AA1

Ball No. Type IPD/IPU Description

IOZ

Down

IOZ

Down

IOZ

Down

Down uPP Data

Each uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

Down

Down uPP Extended Data

Each uPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’ on page 42.

Submit Documentation Feedback

EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU00

EMU01

EMU02

EMU03

EMU04

EMU05

EMU06

EMU07

EMU16

EMU17

EMU18

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16 †

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

www.ti.com

Table 2-19

Signal Name

GPIO17 †

GPIO18 †

GPIO19 †

U22

U23

V23

U21

T21

V22

W21

V21

AD20

T23

U24

T22

R21

T25

R25

R23

U25

IOZ

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions — Signals and Control by Function (Part 8 of 13)

Ball No. Type IPD/IPU Description

EMU

W22

Y22

AA24

AA25

AB25

AC25

AA23

AB22

W24

Y25

Y24

Y23

V24

V25

W25

W23

AD25

AC24

Y21

IOZ

Emulation and Trace Port

General Purpose Input/Output (GPIO)

Down

General Purpose Input/Output

These GPIO pins have secondary functions assigned to them as mentioned elsewhere in this

table: ‘‘Boot Configuration Pins’’ on page 38.

AE21

AC19

AE20

IOZ

Down

General Purpose Input/Output

This GPIO pin has a primary function assigned to it as mentioned elsewhere in this table (

‘‘Timer’’ on page 49) and a tertiary function assigned to it as mentioned elsewhere in this table (

‘‘Boot

Configuration Pins’’ on page 38).

General Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table:

‘‘Timer’’ on page 49.

Submit Documentation Feedback

Device Overview 45

MCMRXN0

MCMRXP0

MCMRXN1

MCMRXP1

MCMRXN2

MCMRXP2

MCMRXN3

MCMRXP3

MCMTXN0

MCMTXP0

MCMTXN1

MCMTXP1

MCMTXN2

MCMTXP2

MCMTXN3

MCMTXP3

MCMRXFLCLK

MCMRXFLDAT

MCMTXFLCLK

MCMTXFLDAT

MCMRXPMCLK

MCMRXPMDAT

MCMTXPMCLK

MCMTXPMDAT

MCMREFCLKOUTP

MCMREFCLKOUTN

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-19 Terminal Functions — Signals and Control by Function (Part 9 of 13)

Signal Name

GPIO20 †

GPIO21 †

GPIO22 †

GPIO23 †

GPIO24 †

GPIO25 †

GPIO26 †

GPIO27 †

GPIO28 †

GPIO29 †

GPIO30 †

GPIO31 †

SCL

SDA

www.ti.com

K22

L22

J21

K21

P22

N22

N21

M21

J25

K25

K24

L24

P24

N24

M25

N25

E24

D24

F24

G24

B24

C24

E25

D25

G25

F25

AE16

AD15

AA12

AA14

AB14

AB13

Ball No. Type IPD/IPU Description

AB15

AA15

IOZ

Down

AC17

AB17

AC14

AC15

IOZ

Down

General Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table:

‘‘UART’’ on page 49.

IOZ

Down

General Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this

table: ‘‘SPI’’ on page 48.

HyperLink

Down

Serial HyperLink Receive Data

Serial HyperLink Transmit Data

Serial HyperLink Sideband Signals

HyperLink Reference clock output for daisy chain connection

AA17

AA18

IOZ

C Clock

C Data

Submit Documentation Feedback

CLKX1

CLKS1

FSR1

FSX1

DR1

DX1

CLKR0

CLKX0

CLKS0

FSR0

FSX0

DR0

DX0

CLKR1

www.ti.com

Table 2-19

Signal Name

TCK

TDI

TDO

TMS

TRST

MDIO

MDCLK

PCIERXN0

PCIERXP0

PCIERXN1

PCIERXP1

PCIETXN0

PCIETXP0

PCIETXN1

PCIETXP1

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions — Signals and Control by Function (Part 10 of 13)

AE12

AE11

AD10

AD11

AC12

AC11

AB11

AB10

AE24

AC21

AD22

AE23

AD21

AE22

AA21

Y20

AC23

AD24

AA20

AB21

AC22

AD23

Ball No. Type IPD/IPU Description

AD17

AE17

AD19

AE18

AB19

Down

JTAG

JTAG Clock Input

JTAG Data Input

JTAG Data Output

JTAG Test Mode Input

JTAG Reset

AB16

AA16

IOZ

Down

McBSP

McBSP Receive Clock

McBSP Transmit Clock

McBSP Slow Clock

McBSP Receive Frame Sync

McBSP Transmit Frame Sync

McBSP Receive Data

McBSP Transmit Data

McBSP Receive Clock

McBSP Transmit Clock

McBSP Slow Clock

McBSP Receive Frame Sync

McBSP Transmit Frame Sync

McBSP Receive Data

McBSP Transmit Data

MDIO

MDIO Data

MDIO Clock

PCIe

PCIexpress Receive Data (2 links)

PCIexpress Transmit Data (2 links)

Submit Documentation Feedback

Device Overview 47

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-19 Terminal Functions — Signals and Control by Function (Part 11 of 13)

Signal Name Ball No. Type IPD/IPU Description

Serial RapidIO

RIOTXN0

RIOTXP0

RIOTXN1

RIOTXP1

RIOTXN2

RIOTXP2

RIOTXN3

RIOTXP3

RIORXN0

RIORXP0

RIORXN1

RIORXP1

RIORXN2

RIORXP2

RIORXN3

RIORXP3

AC5

AC6

AB4

AB5

AC9

AC8

AB7

AB8

AE5

AE6

AD4

AD5

AE9

AE8

AD8

AD7

Serial RapidIO Receive Data (4 links)

SGMII

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

AE2

AE3

AC2

AC3

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

SmartReflex

VCNTL0

VCNTL1

VCNTL2

VCNTL3

E22

E23

F23

G23

Voltage Control Outputs to variable core power supply

SPISCS0

SPISCS1

SPICLK

SPIDIN

SPIDOUT

AA12

AA14

AA13

AB14

AB13

Down

www.ti.com

SPI

SPI Interface Enable 0

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General

SPI Interface Enable 1

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General

SPI Clock

SPI Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General

SPI Data Out

Submit Documentation Feedback

RSV09

RSV10

RSV11

RSV12

RSV13

RSV14

RSV15

RSV01

RSV02

RSV03

RSV04

RSV05

RSV06

RSV07

RSV08

www.ti.com

Table 2-19

Signal Name

TIMI0

TIMI1

TIMO0

TIMO1

UARTRXD

UARTTXD

UARTCTS

UARTRTS

UARTRXD1

UARTTXD1

UARTCTS1

UARTRTS1

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions — Signals and Control by Function (Part 12 of 13)

C23

G22

H22

F21

G21

AA22

AC18

AB18

B23

A23

Y19

IOZ

Ball No. Type IPD/IPU Description

AD20

AE21

AC19

AE20

Down

Timer

Timer Inputs

These Timer pins have secondary functions assigned to them as mentioned elsewhere in this table:

Timer Outputs

AB15

AA15

Down

These Timer pins have secondary functions assigned to them as mentioned elsewhere in this table:

UART

UART Serial Data In

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

UART Serial Data Out

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

AC17 I Down

AB17

AC14

AC15

AE16

AD15

Down

UART Clear To Send

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

UART Request To Send

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

UART Serial Data In

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

UART Serial Data Out

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

UART Clear To Send

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

UART Request To Send

This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:

which external pullup/pulldown resistors are required, see Section 3.4

Reserved

Reserved - pullup to DVDD18

Reserved - leave unconnected

Down

Reserved - leave unconnected

Reserved - connect to GND

Reserved - leave unconnected

Submit Documentation Feedback

Device Overview 49

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-19 Terminal Functions — Signals and Control by Function (Part 13 of 13)

Signal Name

RSV16

RSV17

RSV18

RSV19

RSV20

RSV21

RSV0A

RSV0B

End of Table 2-19

Ball No. Type IPD/IPU Description

J20

AA7

Reserved - leave unconnected

AA11

AB3

F22

D23

G19

G20

IOZ

Reserved - leave unconnected

www.ti.com

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 2-20 Terminal Functions — Power and Ground

Supply

AVDDA1

AVDDA2

CVDD

CVDD1

DVDD15

DVDD18

VDDR1

VDDR2

VDDR3

VDDR4

VDDT1

Ball No.

Y15

F20

Volts Description

1.8

PLL Supply - CORE_PLL

1.8

H9, H11, H13, H15, H17, J10, J12, J14, J16, K11, K13, K15, L8, L10, L12, L14, L16, L18, M9, M11,

M13, M15, M17, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, R10, R12, R14, R16,

R18, T11, T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, V17

0.85 to 1.1

J8, J18, K9, K17, T9, T17, U8, U18 1.0

PLL Supply - DDR3_PLL

SmartReflex core supply voltage

1.5

Fixed core supply voltage for memory array

DDR IO supply B10, C6, C17, C21, D2, D4, D8, D13, D15, D19, F7, F9, F11, F13, F17, F19, G8, G10, G12, G14,

G16, G18

A24, E21, G3, G6, H7, H19, H24, J6, K3, K7, L6, M7, N3, N6, P7, R6, R20, T3, T7, T19, T24, U6,

U20, V7, V19, W6, W14, W16, W18, W20, Y3, Y13, Y17, AB23, AC16, AC20

1.8

IO supply

M20

AA9

AA3

AA5

K19, L20, M19, N20

1.5

1.0

HyperLink SerDes regulator supply

PCIe SerDes regulator supply

SGMII SerDes regulator supply

SRIO SerDes regulator supply

HyperLink SerDes termination supply

VDDT2 W8, W10, W12, Y7, Y9, Y11 1.0

SGMII/SRIO/PCIe SerDes termination supply

0.75

DDR3 reference voltage VREFSSTL E12

VSS A1, A10, A25, B6, B17, C2, C4, C8, C13, C15, C19, D21, E11, F3, F6, F8, F10, F12, F14, F16, F18,

G7, G9, G11, G13, G15, G17, H6, H8, H10, H12, H14, H16, H18, H20, H21, H23, H25, J7, J9, J11,

J13, J15, J17, J19, J22, J23, J24, K2, K6, K8, K10, K12, K14, K16, K18, K20, K23, L7, L9, L11, L13,

L15, L17, L19, L21, L23, L25, M6, M8, M10, M12, M14, M16, M18, M22, M23, M24, N4, N7, N9,

N11, N13, N15, N17, N19, N23, P6, P8, P10, P12, P14, P16, P18, P20, P21, P23, P25, R7, R8, R9,

R11, R13, R15, R17, R19, R22, R24, T2, T6, T8, T10, T12, T14, T16, T18, T20, U7, U9, U11, U13,

U15, U17, U19, V6, V8, V10, V12, V14, V16, V18, V20, W3, W7, W9, W11, W13, W15, W17, W19,

Y6, Y8, Y10, Y12, Y14, Y16, AA4, AA6, AA8, AA10, AB2, AB6, AB9, AB12, AB20, AB24, AC1, AC4,

AC7, AC10, AC13, AD1, AD2, AD3, AD6, AD9, AD12, AD16, AE1, AE4, AE7, AE10, AE13, AE25

End of Table 2-20

GND Ground

Submit Documentation Feedback

Device Overview 51

Table 2-21

BOOTMODE11 †

BOOTMODE12 †

CLKR0

CLKR1

CLKS0

CLKS1

CLKX0

CLKX1

CORECLKN

CORECLKP

CORESEL0

CORESEL1

CVDD

Signal Name

AVDDA1

AVDDA2

BOOTCOMPLETE

BOOTMODE00 †

BOOTMODE01 †

BOOTMODE02 †

BOOTMODE03 †

BOOTMODE04 †

BOOTMODE05 †

BOOTMODE06 †

BOOTMODE07 †

BOOTMODE08 †

BOOTMODE09 †

BOOTMODE10 †

CVDD1

DDRA00

DDRA01

DDRA02

DDRA03

Terminal Functions

— By Signal Name

(Part 1 of 11)

T21

V22

AA21

AD23

AC23

AC21

Y20

AE24

AE19

AD18

U22

U23

V23

U21

T23

U24

T22

R21

Ball Number

Y15

F20

R25

R23

U25

H9, H11, H13, H15,

H17, J10, J12, J14,

J16, K11, K13, K15,

L8, L10, L12, L14,

L16, L18, M9, M11,

M13, M15, M17, N8,

N10, N12, N14, N16,

N18, P9, P11, P13,

P15, P17, P19, R10,

R12, R14, R16, R18,

T11, T13, T15, U10,

U12, U14, U16, V9,

V11, V13, V15, V17

J8, J18, K9, K17, T9,

T17, U8, U18

D16

A19

E16

E15

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-21 Terminal Functions

— By Signal Name

(Part 2 of 11)

Ball Number

B18

A22

B14

B21

A14

A21

C14

A16

A20

B22

B12

C11

A12

B15

B11

E10

A11

D17

B19

D14

D11

C20

E18

E17

C18

E20

E19

B20

D18

A17

C16

A18

D20

Signal Name

DDRA04

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

DDRD08

DDRD09

DDRD10

DDRD11

DDRCB01

DDRCB02

DDRCB03

DDRCE0

DDRCE1

DDRCKE0

DDRCKE1

DDRCLKN

DDRCLKOUTN0

DDRCLKOUTN1

DDRCLKOUTP0

DDRCLKOUTP1

DDRCLKP

DDRD00

DDRD01

DDRD02

DDRA05

DDRA06

DDRA07

DDRA08

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRA14

DDRA15

DDRBA0

DDRBA1

DDRBA2

DDRCAS

DDRCB00

Submit Documentation Feedback

Table 2-21 www.ti.com

Terminal Functions

— By Signal Name

(Part 3 of 11)

D10

C12

C10

Ball Number

B13

E14

D12

A15

A13

B16

C22

D22

E13

DDRD26

DDRD27

DDRD28

DDRD29

DDRD30

DDRD31

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRDQM8

DDRDQS0N

DDRDQS0P

DDRDQS1N

DDRDQS1P

DDRDQS2N

Signal Name

DDRD12

DDRD13

DDRD14

DDRD15

DDRD16

DDRD17

DDRD18

DDRD19

DDRD20

DDRD21

DDRD22

DDRD23

DDRD24

DDRD25

DDRDQS2P

DDRDQS3N

DDRDQS3P

DDRDQS8N

DDRDQS8P

DDRODT0

DDRODT1

DDRRAS

DDRRESET

DDRSLRATE0

DDRSLRATE1

DDRWE

EMIFA14

EMIFA15

EMIFA16

EMIFA17

EMIFA18

EMIFA19

EMIFA20

EMIFA21

EMIFA22

EMIFA23

EMIFBE0

EMIFBE1

EMIFCE0

EMIFCE1

EMIFA06

EMIFA07

EMIFA08

EMIFA09

EMIFA10

EMIFA11

EMIFA12

EMIFA13

DX0

DX1

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA04

EMIFA05

www.ti.com

Table 2-21

Signal Name

DR0

DR1

DVDD15

DVDD18

Terminal Functions

— By Signal Name

(Part 4 of 11)

AC22

AE22

Ball Number

AB21

AD21

B10, C6, C17, C21,

D2, D4, D8, D13,

D15, D19, F7, F9,

F11, F13, F17, F19,

G8, G10, G12, G14,

G16, G18

A24, E21, G3, G6,

H7, H19, H24, J6,

K3, K7, L6, M7, N3,

N6, P7, R6, R20, T3,

T7, T19, T24, U6,

U20, V7, V19, W6,

W14, W16, W18,

W20, Y3, Y13, Y17,

AB23, AC16, AC20

Table 2-21

EMIFWE

EMU00

EMU01

EMU02

EMU03

EMU04

EMU05

EMU06

EMIFD12

EMIFD13

EMIFD14

EMIFD15

EMIFOE

EMIFRNW

EMIFWAIT0

EMIFWAIT1

Signal Name

EMIFCE2

EMIFCE3

EMIFD00

EMIFD01

EMIFD02

EMIFD03

EMIFD04

EMIFD05

EMIFD06

EMIFD07

EMIFD08

EMIFD09

EMIFD10

EMIFD11

EMU07

EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU16

EMU17

EMU18

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-21 Terminal Functions

— By Signal Name

(Part 5 of 11)

Terminal Functions

— By Signal Name

(Part 6 of 11)

W23

W24

Y25

Y24

V24

V25

W25

AA1

AB1

AA2

Ball Number

Y23

W22

Y22

AA24

AA25

AB25

AC25

AA23

AB22

AD25

AC24

Y21

GPIO18 †

GPIO19 †

GPIO20 †

GPIO21 †

GPIO22 †

GPIO23 †

GPIO24 †

GPIO25 †

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16 †

GPIO17 †

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO08

GPIO09

Signal Name

FSR0

FSR1

FSX0

FSX1

GPIO00

GPIO01

GPIO26 †

GPIO27 †

GPIO28 †

GPIO29 †

GPIO30 †

GPIO31 †

HOUT

LENDIAN †

LRESETNMIEN

LRESET

MCMCLKN

MCMCLKP

AC19

AE20

AB15

AA15

AC17

AB17

AC14

AC15

V23

U21

T21

V22

W21

V21

AD20

AE21

T22

R21

U22

U23

R23

U25

T23

U24

Ball Number

AD24

AD22

AA20

AE23

T25

R25

B25

C25

AE16

AD15

AA12

AA14

AB14

AB13

T25

Device Overview 53

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-21 Table 2-21 Terminal Functions

— By Signal Name

(Part 7 of 11)

Terminal Functions

— By Signal Name

(Part 8 of 11)

L22

K21

F24

G24

AA16

AB16

AE15

K22

J21

N22

M21

E25

D25

P22

N21

K25

L24

E24

D24

J25

K24

N24

N25

Ball Number

F25

G25

B24

C24

P24

M25

AD14

AE12

AD10

AE11

AD11

AD20

AC12

AB11

AC11

AB10

Y18

F15

MCMTXFLCLK

MCMTXFLDAT

MCMTXN0

MCMTXN1

MCMTXN2

MCMTXN3

MCMTXP0

MCMTXP1

MCMTXP2

MCMTXP3

MCMTXPMCLK

MCMTXPMDAT

MDCLK

MDIO

NMI

PCIECLKN

PCIECLKP

PCIERXN0

PCIERXN1

PCIERXP0

Signal Name

MCMREFCLKOUTN

MCMREFCLKOUTP

MCMRXFLCLK

MCMRXFLDAT

MCMRXN0

MCMRXN1

MCMRXN2

MCMRXN3

MCMRXP0

MCMRXP1

MCMRXP2

MCMRXP3

MCMRXPMCLK

MCMRXPMDAT

PCIERXP1

PCIESSEN

‡

PCIETXN0

PCIETXN1

PCIETXP0

PCIETXP1

POR

PTV15

RSV04

RSV05

RSV06

RSV07

RSV08

RSV09

RSV0A

RSV0B

RIOTXN3

RIOTXP0

RIOTXP1

RIOTXP2

RIOTXP3

RSV01

RSV02

RSV03

Signal Name

RESETFULL

RESETSTAT

RESET

RIORXN0

RIORXN1

RIORXN2

RIORXN3

RIORXP0

RIORXP1

RIORXP2

RIORXP3

RIOTXN0

RIOTXN1

RIOTXN2

RSV10

RSV11

RSV12

RSV13

RSV14

RSV15

RSV16

RSV17

RSV18

RSV19

RSV20

RSV21

Y19

C23

G19

G20

AC18

AB18

B23

A23

AB4

AC8

AB8

AC6

AB5

AA22

AD5

AC9

AB7

AC5

AD4

AE8

AD7

AE6

Ball Number

AE9

AD8

AE5

F21

G21

J20

AA7

G22

H22

AA11

AB3

F22

D23

54 Device Overview

Table 2-21 www.ti.com

Terminal Functions

— By Signal Name

(Part 9 of 11)

TCK

TDI

TDO

TIMI0

TIMI1

TIMO0

TIMO1

TMS

TRST

UARTCTS

UARTCTS1

UARTRTS

UARTRTS1

UARTRXD

UARTRXD1

UARTTXD

Signal Name

SCL

SDA

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

SPICLK

SPIDIN

SPIDOUT

SPISCS0

SPISCS1

SRIOSGMIICLKN

SRIOSGMIICLKP

SYSCLKOUT

UARTTXD1

UPP_2XTXCLK †

AC15

UPP_CH0_CLK † R2

UPP_CH0_ENABLE † T4

UPP_CH0_START †

UPP_CH0_WAIT †

UPP_CH1_CLK † T5

UPP_CH1_ENABLE † U2

UPP_CH1_START †

UPP_CH1_WAIT †

UPPD00 †

UPPD01 †

AB19

AC17

AE16

AB17

AD15

AB15

AC14

AA15

AD17

AE17

AD19

AD20

AE21

AC19

AE20

AE18

AA13

AB14

AB13

AA12

AA14

AE14

AD13

AA19

Ball Number

AA17

AA18

AE2

AE3

AC2

AC3

Submit Documentation Feedback

www.ti.com

Table 2-21

VDDT1

Terminal Functions

— By Signal Name

(Part 10 of 11)

AA1

AB1

AA2

Ball Number

M20

AA9

AA3

AA5

E22

E23

F23

G23

K19, L20, M19, N20

W8, W10, W12, Y7,

Y9, Y11

M19

N20

UPPXD00 †

UPPXD01 †

UPPXD02 †

UPPXD03 †

UPPXD04 †

UPPXD05 †

UPPXD06 †

UPPXD07 †

UPPXD08 †

UPPXD09 †

UPPXD10 †

UPPXD11 †

UPPXD12 †

UPPXD13 †

UPPXD14 †

UPPXD15 †

VCNTL0

VCNTL1

VCNTL2

VCNTL3

VDDR1

VDDR2

VDDR3

VDDR4

VDDT1

VDDT2

Signal Name

UPPD02 †

UPPD03 †

UPPD04 †

UPPD05 †

UPPD06 †

UPPD07 †

UPPD08 †

UPPD09 †

UPPD10 †

UPPD11 †

UPPD12 †

UPPD13 †

UPPD14 †

UPPD15 †

Table 2-21

Signal Name

VDDT2

VREFSSTL

VSS

End of Table 2-21

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions

— By Signal Name

(Part 11 of 11)

Ball Number

W10

W12

Y11

E12

A1, A10, A25, B6,

B17, C2, C4, C8, C13,

C15, C19, D21, E11,

F3, F6, F8, F10, F12,

F14, F16, F18, G7,

G9, G11, G13, G15,

G17, H6, H8, H10,

H12, H14, H16, H18,

H20, H21, H23, H25,

J7, J9, J11, J13, J15,

J17, J19, J22, J23,

J24, K2, K6, K8, K10,

K12, K14, K16, K18,

K20, K23, L7, L9,

L11, L13, L15, L17,

L19, L21, L23, L25,

M6, M8, M10, M12,

M14, M16, M18,

M22, M23, M24, N4,

N7, N9, N11, N13,

N15, N17, N19, N23,

P6, P8, P10, P12,

P14, P16, P18, P20,

P21, P23, P25, R7,

R8, R9, R11, R13,

R15, R17, R19, R22,

R24, T2, T6, T8, T10,

T12, T14, T16, T18,

T20, U7, U9, U11,

U13, U15, U17, U19,

V6, V8, V10, V12,

V14, V16, V18, V20,

W3, W7, W9, W11,

W13, W15, W17,

W19, Y6, Y8, Y10,

Y12, Y14, Y16, AA4,

AA6, AA8, AA10,

AB2, AB6, AB9,

AB12, AB20, AB24,

AC1, AC4, AC7,

AC10, AC13, AD1,

AD2, AD3, AD6,

AD9, AD12, AD16,

AE1, AE4, AE7,

AE10, AE13, AE25

Device Overview 55

A24

A25

A20

A21

A22

A23

A16

A17

A18

A19

A12

A13

A14

A15

A10

A11

Ball Number

B11

B12

B13

B14

B10

B15

B16

B17

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-22

Terminal Functions

— By Ball Number

(Part 1 of 17)

DDRCKE0

DDRA05

DDRA07

DDRA01

DDRCKE1

DDRCLKOUTP1

DDRCLKP

RSV07

DVDD18

VSS

DDRD26

DDRDQS3N

DDRD17

DDRDQS2P

DDRD21

VSS

Signal Name

VSS

DDRDQS3P

DDRD20

DDRDQS2N

DDRD11

DDRD10

DDRDQS1N

DDRDQM0

DDRD00

VSS

DDRD06

DDRCB03

DDRDQS8N

DDRCLKOUTP0

DDRRAS

DDRDQS1P

DDRD15

DDRD03

DVDD15

DDRD07

DDRCB01

DDRDQS8P

DDRCLKOUTN0

DDRCE0

DDRRESET

VSS

Terminal Functions

— By Ball Number

(Part 2 of 17)

RSV09

MCMRXFLDAT

MCMCLKP

DDRD28

DVDD15

DDRD29

DVDD15

DDRD23

DDRD12

DDRD14

DVDD15

DDRD02

DDRD13

VSS

DDRD01

DDRDQS0N

DDRCB02

DDRDQM8

VSS

DDRCE1

VSS

DDRA06

DVDD15

DDRBA0

VSS

DDRA13

DVDD15

DDRSLRATE0

Signal Name

DDRA04

DDRBA2

DDRA11

DDRCLKOUTN1

DDRCLKN

RSV06

MCMRXFLCLK

MCMCLKN

DDRD27

VSS

DDRD30

VSS

DDRD22

DVDD15

C19

C20

C21

C22

C15

C16

C17

C18

C11

C12

C13

C14

C10

B24

B25

Ball Number

B18

B19

B20

B21

B22

B23

C23

C24

C25

Submit Documentation Feedback

Table 2-22 www.ti.com

Terminal Functions

— By Ball Number

(Part 3 of 17)

MCMRXPMDAT

MCMTXFLDAT

DDRDQM3

DDRD24

DDRD31

DDRD19

DDRD16

DDRD08

DDRDQM1

DDRD09

DDRD04

DDRD05

VSS

VREFSSTL

DDRWE

DDRODT0

Signal Name

DDRDQS0P

DDRCB00

DDRODT1

DVDD15

DDRCAS

DVDD15

DDRA00

DDRBA1

DDRA12

DVDD15

DDRA08

VSS

DDRSLRATE1

RSV21

DDRA03

DDRA02

DDRA15

DDRA14

DDRA10

DDRA09

DVDD18

VCNTL0

VCNTL1

MCMRXPMCLK

MCMTXFLCLK

LRESETNMIEN

E11

E12

E13

E14

E10

D24

D25

D20

D21

D22

D23

D16

D17

D18

D19

Ball Number

D10

D11

D12

D13

D14

D15

E19

E20

E21

E22

E15

E16

E17

E18

E23

E24

E25

www.ti.com

Table 2-22 Terminal Functions

— By Ball Number

(Part 4 of 17)

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

Signal Name

DDRD25

VSS

DDRD18

DDRDQM2

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

PTV15

VSS

DVDD15

VSS

DVDD15

AVDDA2

RSV14

RSV20

VCNTL2

MCMTXPMCLK

MCMREFCLKOUTN

EMIFCE1

HOUT

DVDD18

LRESET

CORESEL1

DVDD18

F24

F25

F20

F21

F22

F23

F16

F17

F18

F19

F12

F13

F14

F15

F10

F11

Ball Number

G11

G12

G13

G14

G10

G15

G16

G17

G18

Table 2-22

H20

H21

H22

H23

H16

H17

H18

H19

H12

H13

H14

H15

H10

H11

G25

Ball Number

G19

G20

G21

G22

G23

G24

H24

H25

J10

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-22 Terminal Functions

— By Ball Number

(Part 5 of 17)

Terminal Functions

— By Ball Number

(Part 6 of 17)

DVDD18

VSS

EMIFBE0

EMIFCE2

RSV02

RESETFULL

CORESEL0

DVDD18

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

DVDD18

VSS

RSV11

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

Signal Name

RSV0A

RSV0B

RSV15

RSV10

VCNTL3

MCMTXPMDAT

MCMREFCLKOUTP

NMI

RSV03

BOOTCOMPLETE

RESET

RESETSTAT

VSS

DVDD18

K11

K12

K13

K14

K10

J25

J21

J22

J23

J24

J17

J18

J19

J20

Ball Number

J11

J12

J13

J14

J15

J16

K19

K20

K21

K22

K15

K16

K17

K18

K23

K24

K25

DVDD18

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

MCMRXN2

EMIFA00

UPPXD00 †

VSS

DVDD18

EMIFWE

EMIFCE0

VSS

Signal Name

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

RSV16

MCMTXN3

VSS

CVDD

VSS

CVDD1

VSS

VDDT1

VSS

MCMTXP3

MCMTXN2

VSS

MCMRXN3

MCMRXP2

EMIFA04

Device Overview 57

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-22 Table 2-22 Terminal Functions

— By Ball Number

(Part 7 of 17)

Terminal Functions

— By Ball Number

(Part 8 of 17)

L22

L23

L24

L25

L18

L19

L20

L21

L14

L15

L16

L17

L10

L11

L12

L13

Ball Number

M10

M11

M12

CVDD

VSS

CVDD

VSS

CVDD

VSS

VDDT1

VSS

MCMTXP2

VSS

MCMRXP3

VSS

EMIFA07

UPPXD07 †

EMIFA06

UPPXD06 †

Signal Name

UPPXD04 †

EMIFA02

UPPXD02 †

EMIFBE1

EMIFOE

EMIFRNW

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

EMIFA01

UPPXD01 †

EMIFWAIT1

UPP2XTXCLK †

EMIFCE3

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

N12

N13

N14

N15

N10

N11

M23

M24

M25

M19

M20

M21

M22

Ball Number

M13

M14

M15

M16

M17

M18

N20

N21

N22

N23

N16

N17

N18

N19

N24

N25

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

UPPXD10 †

EMIFA08

UPPXD08 †

DVDD18

VSS

EMIFWAIT0

DVDD18

VSS

Signal Name

CVDD

VSS

CVDD

VSS

CVDD

VSS

VDDT1

VDDR1

MCMTXP1

VSS

MCMRXN1

EMIFA10

CVDD

VSS

CVDD

VSS

VDDT1

MCMTXN1

MCMTXP0

VSS

MCMRXP0

MCMRXP1

EMIFA12

UPPXD12 †

58 Device Overview

Table 2-22 www.ti.com

Terminal Functions

— By Ball Number

(Part 9 of 17)

Signal Name

EMIFA11

UPPXD11 †

EMIFA09

UPPXD09 †

EMIFA05

UPPXD05 †

EMIFA03

UPPXD03 †

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

MCMTXN0

VSS

MCMRXN0

VSS

EMIFA17

UPP_CH0_START †

EMIFA16

UPP_CH0_CLK †

EMIFA14

UPPXD14 †

EMIFA15

UPPXD15 †

EMIFA13

UPPXD13 †

DVDD18

VSS

P24

P25

P20

P21

P22

P23

P16

P17

P18

P19

P12

P13

P14

P15

P10

P11

Ball Number

Submit Documentation Feedback

www.ti.com

Table 2-22 Terminal Functions

— By Ball Number

(Part 10 of 17)

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

DVDD18

VSS

Signal Name

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

GPIO07

BOOTMODE06 †

VSS

GPIO02

BOOTMODE01 †

VSS

GPIO01

BOOTMODE00 †

EMIFA19

UPP_CH0_WAIT †

VSS

DVDD18

EMIFA18

UPP_CH0_ENABLE †

EMIFA20

UPP_CH1_CLK †

VSS

DVDD18

VSS

R25

R23

R24

R25

R20

R21

R22

R16

R17

R18

R19

Ball Number

R10

R11

R12

R13

R14

R15

T13

T14

T15

T16

T10

T11

T12

T17

T18

T19

T20

Table 2-22

U13

U14

U15

U16

U10

U11

U12

T24

T25

Ball Number

T21

T22

T23

U21

U22

U17

U18

U19

U20

U23

U24

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-22 Terminal Functions

— By Ball Number

(Part 11 of 17)

Terminal Functions

— By Ball Number

(Part 12 of 17)

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

UPP_CH1_WAIT †

EMIFD00

UPPD00 †

EMIFD01

UPPD01 †

DVDD18

VSS

CVDD1

Signal Name

GPIO12

BOOTMODE11 †

GPIO06

BOOTMODE05 †

GPIO04

BOOTMODE03 †

DVDD18

GPIO00

LENDIAN †

EMIFA21

UPP_CH1_START †

EMIFA22

UPP_CH1_ENABLE †

EMIFA23

VSS

CVDD1

VSS

DVDD18

GPIO11

BOOTMODE10 †

GPIO08

BOOTMODE07 †

GPIO09

BOOTMODE08 †

GPIO05

BOOTMODE04 †

V20

V21

V22

V16

V17

V18

V19

V12

V13

V14

V15

V10

V11

Ball Number

U25

V25

V22

V23

V24

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

VSS

GPIO15

PCIESSMODE1 †

GPIO13

Signal Name

GPIO03

BOOTMODE02 †

EMIFD02

UPPD02 †

EMIFD03

UPPD03 †

EMIFD04

UPPD04 †

EMIFD05

UPPD05 †

EMIFD07

UPPD07 †

VSS

DVDD18

BOOTMODE12 †

GPIO10

BOOTMODE09 †

EMU00

EMU01

EMIFD06

UPPD06 †

EMIFD08

UPPD08 †

VSS

EMIFD10

UPPD10 †

Device Overview 59

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 2-22 Table 2-22 Terminal Functions

— By Ball Number

(Part 13 of 17)

Terminal Functions

— By Ball Number

(Part 14 of 17)

W25

W21

W22

W23

W24

W18

W19

W20

W21

W10

W11

W12

W13

W14

W15

W16

W17

Ball Number

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

DVDD18

VSS

AVDDA1

VSS

DVDD18

VSS

DVDD18

GPIO14 †

PCIESSMODE0 †

EMU08

EMU03

EMU04

EMU02

EMIFD09

UPPD09 †

EMIFD11

UPPD11 †

DVDD18

RSV13

RSV12

Signal Name

EMIFD12

UPPD12 †

DVDD18

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

DVDD18

VSS

DVDD18

VSS

AA12

AA13

AA14

AA15

AA16

AA17

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA2

AA3

AA4

Y24

Y25

AA1

Ball Number

Y18

Y19

Y20

Y21

Y22

Y23

AB1

AB2

AB3

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

VDDR4

VSS

RSV17

VSS

VDDR2

VSS

RSV18

SPISCS0

GPIO28 †

SPICLK

SPISCS1

GPIO29 †

UARTTXD

GPIO21 †

MDCLK

SCL

Signal Name

POR

RSV08

CLKX0

EMU18

EMU09

EMU07

EMU06

EMU05

EMIFD13

UPPD13 †

EMIFD15

UPPD15 †

VDDR3

VSS

SDA

SYSCLKOUT

FSX0

CLKR0

RSV01

EMU14

EMU10

EMU11

EMIFD14

UPPD14 †

VSS

RSV19

60 Device Overview

Table 2-22 www.ti.com

Terminal Functions

— By Ball Number

(Part 15 of 17)

GPIO20 †

MDIO

UARTRTS

GPIO23 †

RSV05

TRST

VSS

DR0

EMU15

DVDD18

VSS

EMU12

VSS

SGMII0TXN

SGMII0TXP

VSS

Signal Name

RIOTXN3

RIOTXP3

VSS

RIOTXN1

RIOTXP1

VSS

PCIETXP1

PCIETXN1

VSS

SPIDOUT

GPIO31 †

SPIDIN

GPIO30 †

UARTRXD

RIOTXN2

RIOTXP2

VSS

RIOTXP0

RIOTXN0

VSS

PCIETXP0

PCIETXN0

VSS

UARTRXD1

GPIO24 †

UARTTXD1

AC1

AC2

AC3

AC4

AB22

AB23

AB24

AB25

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB10

AB11

AB12

AB13

AB14

AB15

Ball Number

AB4

AB5

AB6

AB7

AB8

AB9

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

Submit Documentation Feedback

www.ti.com

Table 2-22 Terminal Functions

— By Ball Number

(Part 16 of 17)

TCK

CORECLKP

TDO

TIMI0

GPIO16 †

PCIESSEN ‡

DR1

FSR1

CLKR1

FSR0

EMU16

VSS

RIORXN3

RIORXP3

VSS

RIORXP1

RIORXN1

VSS

PCIERXN1

PCIERXP1

VSS

SRIOSGMIICLKP

PCIECLKP

UARTRTS1

GPIO27 †

VSS

Signal Name

GPIO25 †

DVDD18

UARTCTS

GPIO22 †

RSV04

TIMO0

GPIO18 †

DVDD18

CLKS1

DX0

CLKS0

EMU17

EMU13

VSS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD6

AD7

AD8

AD9

AD2

AD3

AD4

AD5

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AD1

Ball Number

AC15

AC16

AC17

AC18

AC19

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AE1

Table 2-22

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Terminal Functions

— By Ball Number

(Part 17 of 17)

AE8

AE9

AE10

AE11

AE12

AE13

AE14

AE15

Ball Number

AE2

AE3

AE4

AE5

AE6

AE7

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

GPIO17 †

DX1

FSX1

CLKX1

AE25

End of Table 2-22

VSS

UARTCTS1

GPIO26 †

TDI

TMS

CORECLKN

TIMO1

GPIO19 †

TIMI1

Signal Name

SGMII0RXN

SGMII0RXP

VSS

RIORXN2

RIORXP2

VSS

RIORXP0

RIORXN0

VSS

PCIERXP0

PCIERXN0

VSS

SRIOSGMIICLKN

PCIECLKN

Device Overview 61

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

2.9 Development and Support

2.9.1 Development Support www.ti.com

In case the customer would like to develop their own features and software on the C6655/57 device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

•

Software Development Tools:

–

Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly

Code Generation, and Debug plus additional development tools.

–

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any DSP application.

•

Hardware Development Tools:

–

Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)

–

EVM (Evaluation Module)

2.9.2 Device Support

2.9.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,

TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:

TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

•

TMX:

Experimental device that is not necessarily representative of the final device's electrical specifications

•

TMP:

Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification

•

TMS:

Fully qualified production device

Support tool development evolutionary flow:

•

TMDX:

Development-support product that has not yet completed Texas Instruments internal qualification testing.

•

TMDS:

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CZH), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).

For device part numbers and further ordering information for TMS320C6655/57 in the CZH or GZH package type, see the TI website www.ti.com

or contact your TI sales representative.

Figure 2-21

provides a legend for reading the complete device name for any C66x KeyStone device.

Figure 2-21 C66x DSP Device Nomenclature (including the TMS320C6655/57)

TMX 320 C6657 ( ) ( )

CZH

( ) ( )

PREFIX

TMX = Experimental device

TMS = Qualified device

DEVICE SPEED RANGE

8 = 850 MHz

Blank = 1 GHz

25 = 1.25 GHz

DEVICE FAMILY

320 = TMS320 DSP family

DEVICE

C66x DSP: C6655 or C6657

SILICON REVISION

Blank = Initial Silicon 1.0

TEMPERATURE RANGE

Blank = 0°C to +85°C (default case temperature)

A = Extended temperature range

(-40°C to +100°C)

L = Extended low temperature range

(-55°C to +100°C)

SECURITY

Blank = General purpose device

S = Secure device

PACKAGE TYPE

CZH = 625-pin plastic ball grid array, with Pb-free die bumps and solder balls

GZH = 625-pin plastic ball grid array

Submit Documentation Feedback

Device Overview 63

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

2.10 Related Documentation from Texas Instruments

These documents describe the TMS320C6655/57 Fixed and Floating-Point Digital Signal Processor. Copies of these documents are available on the Internet at www.ti.com

64-bit Timer (Timer 64) for KeyStone Devices User Guide

Bootloader for the C66x DSP User Guide

C66x CorePac User Guide

C66x CPU and Instruction Set Reference Guide

C66x DSP Cache User Guide

DDR3 Design Guide for KeyStone Devices

DDR3 Memory Controller for KeyStone Devices User Guide

DSP Power Consumption Summary for KeyStone Devices

Embedded Trace for KeyStone Devices User Guide

Emulation and Trace Headers Technical Reference

Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide

External Memory Interface (EMIF16) for KeyStone Devices User Guide

General Purpose Input/Output (GPIO) for KeyStone Devices User Guide

Gigabit Ethernet (GbE) Subsystem for KeyStone Devices User Guide

Hardware Design Guide for KeyStone Devices

HyperLink for KeyStone Devices User Guide

Inter Integrated Circuit (I

C) for KeyStone Devices User Guide

Chip Interrupt Controller (CIC) for KeyStone Devices User Guide

Memory Protection Unit (MPU) for KeyStone Devices User Guide

Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User Guide

Multicore Navigator for KeyStone Devices User Guide

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide

Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide

Phase Locked Loop (PLL) for KeyStone Devices User Guide

Power Sleep Controller (PSC) for KeyStone Devices User Guide

Semaphore2 Hardware Module for KeyStone Devices User Guide

Serial Peripheral Interface (SPI) for KeyStone Devices User Guide

Serial RapidIO (SRIO) for KeyStone Devices User Guide

Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide

Universal Parallel Port (uPP) for KeyStone Devices User Guide

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs

Using IBIS Models for Timing Analysis

Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide

SPRUGR9

SPRUGW7

SPRUGS6

SPRUGV2

SPRUGV4

SPRUGS3

SPRUGP2

SPRUGW1

SPRUGS0

SPRUGP1

SPRA387

SPRA753

SPRA839

SPRUGV6

SPRUGV5

SPRUGY5

SPRUGW0

SPRUGH7

SPRUGY8

SPRABI1

SPRUGV8

SPRABL4

SPRUGZ2

SPRU655

SPRUGS5

SPRUGZ3

SPRUGV1

SPRUGV9

SPRABI2

SPRUGW8

SPRUGV3

SPRUGW4

SPRUGW5

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

3 Device Configuration

www.ti.com

On the TMS320C6655/57 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.

3.1 Device Configuration at Device Reset

Table 3-1

describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP can be taken out of reset.

Also, please note that most of the device configuration pins are shared with other function pins

(LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0), some time must be given following the rising edge of reset in order to drive these device configuration input pins before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that needs to be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.

Note—

If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in

‘‘Pullup/Pulldown Resistors’’ on page 86.

Table 3-1 TMS320C6655/57 Device Configuration Pins

Configuration Pin

LENDIAN

(1) (2)

Pin No.

T25

IPD/IPU

IPU

(1)

Functional Description

Device endian mode (LENDIAN).

0 = Device operates in big endian mode

1 = Device operates in little endian mode

BOOTMODE[12:0]

(1) (2)

R25, R3, U25, T23,

U24, T22, R21,

U22, U23, V23,

U21, T21, V22

IPD Method of boot.

Some pins may not be used by bootloader and can be used as general purpose config

pins. Refer to the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from

Texas Instruments’’ on page 64 for how to determine the device enumeration ID value.

PCIESSMODE[1:0]

(1) (2)

W21, V21 IPD PCIe Subsystem mode selection.

00 = PCIe in end point mode

01 = PCIe legacy end point (support for legacy INTx)

10 = PCIe in root complex mode

11 = Reserved

PCIESSEN

(1) (2)

AD20

0 = PCIE Subsystem is disabled

1 = PCIE Subsystem is enabled

End of Table 3-1

1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-k

Ω resistor can be used to oppose the IPD/IPU. For more detailed information on

pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4

‘‘Pullup/Pulldown Resistors’’ on page 86.

2 These signal names are the secondary functions of these pins.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.2 Peripheral Selection After Device Reset

Several of the peripherals on the TMS320C6655/57 are controlled by the Power Sleep Controller (PSC). By default, the PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. The software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in

3.3 Device State Control Registers

The TMS320C6655/57 device has a set of registers that are used to provide the status or configure certain parts of its

peripherals. These registers are shown in Table 3-2 .

Table 3-2 Device State Control Registers (Part 1 of 4)

Address Start

0x02620000

0x02620008

0x02620018

0x0262001C

0x02620020

0x02620024

0x02620038

0x0262003C

0x02620040

0x02620044

Address End

0x02620007

0x02620017

0x0262001B

0x0262001F

0x02620023

0x02620037

0x0262003B

0x0262003F

0x02620043

0x02620047

20B

Size

16B

Field

Reserved

JTAGID

Reserved

DEVSTAT

Reserved

KICK0

KICK1

DSP_BOOT_ADDR0

DSP_BOOT_ADDR1

Description

See section 3.3.3

See section 3.3.1

See section 3.3.4

The boot address for C66x DSP CorePac0

The boot address for C66x DSP CorePac1 (C6657) or Reserved

(C6655)

0x02620048

0x0262004C

0x02620050

0x02620054

0x02620058

0x0262005C

0x02620060

0x026200E0

0x02620110

0x0262004B

0x0262004F

0x02620053

0x02620057

0x0262005B

0x0262005F

0x026200DF

0x0262010F

0x02620117

Reserved

4B Reserved

128B Reserved

48B Reserved

8B MACID

See section 7.17

‘‘Ethernet Media Access Controller (EMAC)’’ on page 203

0x02620118

0x02620130

0x02620134

0x02620138

0x0262013C

0x02620140

0x02620144

0x02620148

0x0262012F

0x02620133

0x02620137

0x0262013B

0x0262013F

0x02620143

0x02620147

0x0262014B

24B

Reserved

LRSTNMIPINSTAT_CLR

RESET_STAT_CLR

Reserved

BOOTCOMPLETE

Reserved

RESET_STAT

LRSTNMIPINSTAT

Submit Documentation Feedback

Device Configuration 66

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 3-2 Device State Control Registers (Part 2 of 4)

0x0262019C

0x026201A0

0x026201A4

0x026201A8

0x026201AC

0x026201B0

0x026201B4

0x026201B8

0x026201BC

0x026201C0

0x026201C4

0x026201C8

0x026201CC

0x026201D0

0x02620200

0x02620204

0x02620208

Address Start

0x0262014C

0x02620150

0x02620154

0x02620158

0x0262015C

0x02620160

0x02620164

0x02620168

0x0262016C

0x02620170

0x02620184

0x02620190

0x02620194

0x02620198

0x0262020C

0x02620210

0x02620214

0x02620218

0x0262021C

0x02620220

0x02620240

0x02620244

0x02620248

0x0262024C

0x02620250

0x02620254

0x0262019F

0x026201A3

0x026201A7

0x026201AB

0x026201AF

0x026201B3

0x026201B7

0x026201BB

0x026201BF

0x026201C3

0x026201C7

0x026201CB

0x026201CF

0x026201FF

0x02620203

0x02620207

0x0262020B

Address End

0x0262014F

0x02620153

0x02620157

0x0262015B

0x0262015F

0x02620163

0x02620167

0x0262016B

0x0262016F

0x02620183

0x0262018F

0x02620193

0x02620197

0x0262019B

0x0262020F

0x02620213

0x02620217

0x0262021B

0x0262021F

0x0262023F

0x02620243

0x02620247

0x0262024B

0x0262024F

0x02620253

0x02620257

32B

48B

12B

20B

Size

Reserved

NMIGR0

NMIGR1

Reserved

Field

DEVCFG

PWRSTATECTL

SRIO_SERDES_STS

SMGII_SERDES_STS

PCIE_SERDES_STS

HYPERLINK_SERDES_STS

Reserved

UPP_CLOCK

Reserved

IPCGR0

IPCGR1

Reserved

www.ti.com

Description

(C6657) or Reserved (C6655)

See section 3.3.12

(C6657) or Reserved (C6655)

Submit Documentation Feedback

www.ti.com

Table 3-2

Address Start

0x02620258

0x0262025C

0x02620260

0x0262027C

0x02620280

0x02620284

0x02620288

0x0262028C

0x02620290

0x02620294

0x02620298

0x0262029C

0x026202A0

0x026202BC

0x026202C0

0x02620300

0x02620304

0x02620308

0x0262030C

0x02620310

0x02620314

0x02620318

0x0262031C

0x02620320

0x02620324

0x02620328

0x0262032C

0x02620330

0x02620334

0x02620338

0x0262033C

0x02620340

0x02620344

0x02620348

0x0262034C

0x02620350

0x02620354

0x02620358

0x0262035C

Device State Control Registers (Part 3 of 4)

Address End

0x0262025B

0x0262025F

0x0262027B

0x0262027F

0x02620283

0x02620287

0x0262028B

0x0262028F

0x02620293

0x02620297

0x0262029B

0x0262029F

0x026202BB

0x026202BF

0x026202FF

0x02620303

0x02620307

0x0262030B

0x0262030F

0x02620313

0x02620317

0x0262031B

0x0262031F

0x02620323

0x02620327

0x0262032B

0x0262032F

0x02620333

0x02620337

0x0262033B

0x0262033F

0x02620343

0x02620347

0x0262034B

0x0262034F

0x02620353

0x02620357

0x0262035B

0x0262035F

28B

64B

Size

28B

Field

Reserved

IPCGRH

IPCAR0

IPCAR1

Reserved

IPCARH

Reserved

TINPSEL

TOUTPSEL

RSTMUX0

RSTMUX1

Reserved

MAINPLLCTL0

MAINPLLCTL1

DDR3PLLCTL

Reserved

SGMII_SERDES_CFGPLL

SGMII_SERDES_CFGRX0

SGMII_SERDES_CFGTX0

Reserved

PCIE_SERDES_CFGPLL

Reserved

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Description

See section 3.3.14

See section 3.3.13

(C6657) or Reserved (C6655)

(C6657) or Reserved (C6655)

See section 7.5

‘‘Main PLL and PLL Controller’’ on page 126

See section 7.6

‘‘DD3 PLL’’ on page 139

See

Submit Documentation Feedback

Device Configuration 68

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 3-2 Device State Control Registers (Part 4 of 4)

0x026203BC

0x026203C0

0x026203C4

0x026203C8

0x026203CC

0x026203D0

0x026203D4

0x026203D8

0x026203DC

0x026203F8

0x026203FC

0x02620400

0x02620404

0x02620468

0x02620580

0x02620584

0x02620588

End of Table 3-2

Address Start

0x02620360

0x02620364

0x02620368

0x0262036C

0x02620370

0x02620374

0x02620378

0x0262037C

0x02620380

0x02620384

0x02620388

0x026203B0

0x026203B4

0x026203B8

0x026203BF

0x026203C3

0x026203C7

0x026203CB

0x026203CF

0x026203D3

0x026203D7

0x026203DB

0x026203F7

0x026203FB

0x026203FF

0x02620403

0x02620467

0x0262057f

0x02620583

0x02620587

0x0262058B

Address End

0x02620363

0x02620367

0x0262036B

0x0262036F

0x02620373

0x02620377

0x0262037B

0x0262037F

0x02620383

0x02620387

0x026203AF

0x026203B3

0x026203B7

0x026203BB

28B

Size

Field

SRIO_SERDES_CFGPLL

SRIO_SERDES_CFGRX0

SRIO_SERDES_CFGTX0

SRIO_SERDES_CFGRX1

SRIO_SERDES_CFGTX1

SRIO_SERDES_CFGRX2

SRIO_SERDES_CFGTX2

SRIO_SERDES_CFGRX3

SRIO_SERDES_CFGTX3

Reserved

HYPERLINK_SERDES_CFGPLL

HYPERLINK_SERDES_CFGRX0

HYPERLINK_SERDES_CFGTX0

HYPERLINK_SERDES_CFGRX1

HYPERLINK_SERDES_CFGTX1

HYPERLINK_SERDES_CFGRX2

HYPERLINK_SERDES_CFGTX2

HYPERLINK_SERDES_CFGRX3

HYPERLINK_SERDES_CFGTX3

Reserved

28B

Reserved

DEVSPEED

Reserved

PKTDMA_PRI_ALLOC

100B Reserved

280B Reserved

PIN_CONTROL_0

PIN_CONTROL_1

EMAC_UPP_PRI_ALLOC

www.ti.com

Description

See section 3.3.19

See section 4.4

‘‘Bus Priorities’’ on page 94

See section 3.3.20

See section 3.3.21

See section 4.4

‘‘Bus Priorities’’ on page 94

3.3.1 Device Status Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or

RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device Status Register is

shown in Figure 3-1

and described in Table 3-3 .

Figure 3-1 Device Status Register

Reserved

17 16

PCIESSEN

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 x indicates the bootstrap value latched via the external pin

R-x

15 14

PCIESSMODE[1:0

R/W-xx

BOOTMODE[12:0]

R/W-xxxxxxxxxxxx

1 0

LENDIAN

R-x

(1)

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 3-3 Device Status Register Field Descriptions

Bit Field

31-17 Reserved

Description

Reserved. Read only, writes have no effect.

16 PCIESSEN PCIe module enable

0 = PCIe module disabled

1 = PCIe module enabled

15-14 PCIESSMODE[1:0] PCIe Mode selection pins

00b = PCIe in End-point mode

01b = PCIe in Legacy End-point mode (support for legacy INTx)

10b = PCIe in Root complex mode

11b = Reserved

13-1

BOOTMODE[12:0]

Determines the bootmode configured for the device. For more information on bootmode, refer to Section 2.5

‘‘Boot

Modes Supported and PLL Settings’’

on page 24 and see the Bootloader for the C66x DSP User Guide in 2.10

LENDIAN Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little

Endian mode.

0 = System is operating in Big Endian mode

1 = System is operating in Little Endian mode

End of Table 3-3

3.3.2 Device Configuration Register

The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in

Figure 3-2

and described in

Table 3-4

Figure 3-2 Device Configuration Register (DEVCFG)

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

SYSCLKOUTEN

R/W-1

Table 3-4 Device Configuration Register Field Descriptions

Bit

31-1

Field

Reserved

0 SYSCLKOUTEN

Description

Reserved. Read only, writes have no effect.

0 = No clock output

1 = Clock output enabled (default)

End of Table 3-4

Submit Documentation Feedback

Device Configuration 70

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.3 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the

JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3

and

described in Table 3-5 .

Figure 3-3 JTAG ID (JTAGID) Register

31 28 27

VARIANT

R-xxxxb

PART NUMBER

R-1011 1001 0111 1010b

Legend: RW = Read/Write; R = Read only; -n = value after reset

12 11

MANUFACTURER

0000 0010 111b

1 0

LSB

R-1

Table 3-5 JTAG ID Register Field Descriptions

Bit Field

31-28 VARIANT

27-12 PART NUMBER

11-1 MANUFACTURER

0 LSB

End of Table 3-5

Value

xxxxb

Description

Variant (4-Bit) value.

1011 1001 0111 1010b Part Number for boundary scan

0000 0010 111b Manufacturer

1b This bit is read as a 1 for TMS320C6655/57

Note—

The value of the VARIANT and PART NUMBER fields depend on the silicon revision. See the Silicon

Errata for details.

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register

The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg

MMR values. When the kicker is locked (which it is initially after power on reset), none of the Bootcfg MMRs are writable (they are only readable). On the C6655/57, the exception to this are the IPC registers such as IPCGRx and

IPCARx. These registers are not protected by the kicker mechanism. This mechanism requires two MMR writes to the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See

Table 3-2 ‘‘Device State Control Registers’’ on page 66 for the address location. Once released, then all the Bootcfg

MMRs having write permissions are writable (the read only MMRs are still read only). The first KICK0 data is

0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to Bootcfg MMRs. To ensure protection of all Bootcfg MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register

The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on

CORESEL. The LRESETNMI PIN Status Register is shown and described in the following tables.

Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

15 2 31 18

Reserved

R, +0000 0000

Legend: R = Read only; -n = value after reset;

NMI1/Reserved

R-0

NMI0

R-0

Reserved

R, +0000 0000

LR1

R-0

LR0

R-0

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 3-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions

Bit Field

31-18 Reserved

NMI1/Reserved

NMI0

15-2

Reserved

LR1

0 LR0

End of Table 3-6

Description

Reserved

CorePac1 in NMI (C6657) or Reserved (C6655)

CorePac0 in NMI

Reserved

CorePac1 in Local Reset (C6657) or Reserved (C6655)

CorePac0 in Local Reset

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register

The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The

LRESETNMI PIN Status Clear Register is shown and described in the following tables.

Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

15 2 31

Reserved

R, +0000 0000

18 17

NMI1/Reserved

WC,+0

Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear

NMI0

WC,+0

Reserved

R, +0000 0000

LR1/Reserved

WC,+0

LR0

WC,+0

Table 3-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions

Bit Field

31-18 Reserved

NMI1/Reserved

NMI0

15-2

Reserved

LR1/Reserved

0 LR0

End of Table 3-7

Description

Reserved

CorePac1 in NMI Clear (C6657) or Reserved (C6655)

CorePac0 in NMI Clear

Reserved

CorePac1 in Local Reset Clear (C6657) or Reserved (C6655)

CorePac0 in Local Reset Clear

Submit Documentation Feedback

Device Configuration 72

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.7 Reset Status (RESET_STAT) Register

The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.

• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives an local reset without receiving a global reset.

• In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.

The Reset Status Register is shown and described in the following tables.

Figure 3-6 Reset Status Register (RESET_STAT)

R, +1

Legend: R = Read only; -n = value after reset

Reserved

R, + 000 0000 0000 0000 0000 0000

2 1

LR1/Reserved

R,+0

LR0

R,+0

Table 3-8

Bit

30-2

Field

LR0

Reset Status Register (RESET_STAT) Field Descriptions

Reserved

LR1/Reserved

Description

Global reset status

0 = Device has not received a global reset.

1 = Device received a global reset.

Reserved.

CorePac1 reset status (C6657) or Reserved (C6655)

0 = CorePac1 has not received a local reset.

1 = CorePac1 received a local reset.

CorePac0 reset status

0 = CorePac0 has not received a local reset.

1 = CorePac0 received a local reset.

End of Table 3-8

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The

Reset Status Clear Register is shown and described in the following tables.

Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR)

RW, +0

Reserved

R, + 000 0000 0000 0000 0000 0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

2 1

LR1/Reserved

RW,+0

LR0

RW,+0

Table 3-9

Bit

30-2

Field

LR0

Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions

Reserved

LR1/Reserved

Description

Global reset clear bit

0 = Writing a 0 has no effect.

1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.

Reserved.

CorePac1 reset clear bit (C6657) or Reserved (C6655)

0 = Writing a 0 has no effect.

1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.

CorePac0 reset clear bit

0 = Writing a 0 has no effect.

1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.

End of Table 3-9

3.3.9 Boot Complete (BOOTCOMPLETE) Register

The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the completion of the ROM booting process. The Boot Complete Register is shown and described in the following tables.

Figure 3-8 Boot Complete Register (BOOTCOMPLETE)

Reserved

R, + 0000 0000 0000 0000 0000 0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

2 1

BC1/Reserved

RW,+0

BC0

RW,+0

Table 3-10

Bit

31-2

Field

Reserved

BC1

0 BC0

Boot Complete Register (BOOTCOMPLETE) Field Descriptions

Description

Reserved.

CorePac1 boot status (C6657) or Reserved (C6655)

0 = CorePac1 boot NOT complete

1 = CorePac1 boot complete

CorePac0 boot status

0 = CorePac0 boot NOT complete

1 = CorePac0 boot complete

End of Table 3-10

Submit Documentation Feedback

Device Configuration 74

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.

Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before branching to the predefined location in memory.

3.3.10 Power State Control (PWRSTATECTL) Register

The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will

survive all other device resets. See the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from

Texas Instruments’’

on page 64 for more information. The Power State Control Register is shown in Figure 3-9

and

described in Table 3-11 .

Figure 3-9 Power State Control Register (PWRSTATECTL)

GENERAL_PURPOSE

RW, +0000 0000 0000 0000 0000 0000 0000 0

Legend: RW = Read/Write; -n = value after reset

3 2

HIBERNATION_MODE

RW,+0

HIBERNATION

RW,+0

STANDBY

RW,+0

Table 3-11 Power State Control Register (PWRSTATECTL) Field Descriptions

Bit

31-3

Field

GENERAL_PURPOSE

Description

Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User

Guide in

HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.

0 = Hibernation mode 1

1 = Hibernation mode 2

HIBERNATION Indicates whether the device is in hibernation mode or not.

0 = Not in hibernation mode

1 = Hibernation mode

STANDBY Indicates whether the device is in standby mode or not.

0 = Not in standby mode

1 = Standby mode

End of Table 3-11

3.3.11 NMI Event Generation to CorePac (NMIGRx) Register

NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6657 has two NMIGRx registers (NMIGR0 and NMIGR1) while the C6655 has only NMIGR0. The NMIGR0 register generates an NMI event to CorePac0, and the NMIGR1 register generates an NMI event to CorePac1. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and reads return 0 and have no other effect. The NMI Event

Generation to CorePac Register is shown in

Figure 3-10

and described in Table 3-12 .

Figure 3-10 NMI Generation Register (NMIGRx)

Legend: RW = Read/Write; -n = value after reset

Reserved

R, +0000 0000 0000 0000 0000 0000 0000 000

1 0

NMIG

RW,+0

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 3-12

Bit

31-1

Field

Reserved

NMIG

NMI Generation Register (NMIGRx) Field Descriptions

Description

Reserved

NMI pulse generation.

Reads return 0

Writes:

0 = No effect

1 = Sends an NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.

End of Table 3-12

3.3.12 IPC Generation (IPCGRx) Registers

IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.

The C6657 has two IPCGRx registers (IPCGR0 and IPCGR1) while the C6655 has only IPCGR0. These registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the

IPCGRx register will generate an interrupt pulse to CorePacx (0 <= x <= 1).

These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.

Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these

registers. The IPC Generation Register is shown in Figure 3-11

and described in

Table 3-13

Figure 3-11 IPC Generation Registers (IPCGRx)

SRCS27

SRCS26

SRCS25

SRCS24

RW +0 RW +0 RW +0 RW +0

SRCS23 – SRCS4

RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCS3 SRCS2 SRCS1 SRCS0

RW +0 RW +0 RW +0 RW +0

Reserved

R, +000

IPCG

RW +0

Table 3-13

Bit

31-4

Field

SRCSx

3-1

Reserved

IPCG

IPC Generation Registers (IPCGRx) Field Descriptions

Description

Interrupt source indication.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Sets both SRCSx and the corresponding SRCCx.

Reserved

Inter-DSP interrupt generation.

Reads return 0.

Writes:

0 = No effect

1 = Creates an Inter-DSP interrupt.

End of Table 3-13

Submit Documentation Feedback

Device Configuration 76

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

3.3.13 IPC Acknowledgement (IPCARx) Registers

IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.

www.ti.com

The C6657 has two IPCARx registers (IPCAR0 and IPCAR1) while the C6655 has only IPCAR0. These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are shown in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC

Acknowledgement Register is shown in Figure 3-12

and described in

Table 3-14

Figure 3-12 IPC Acknowledgement Registers (IPCARx)

SRCC27

SRCC26

SRCC25

SRCC24

RW +0 RW +0 RW +0 RW +0

SRCC23 – SRCC4

RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCC3 SRCC2 SRCC1 SRCC0

RW +0 RW +0 RW +0 RW +0

Reserved

R, +0000

Table 3-14

Bit

31-4

Field

SRCCx

IPC Acknowledgement Registers (IPCARx) Field Descriptions

3-0 Reserved

End of Table 3-14

Description

Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Clears both SRCCx and the corresponding SRCSx

Reserved

3.3.14 IPC Generation Host (IPCGRH) Register

IPCGRH register is provided to facilitate host DSP interrupt. Operation and use of IPCGRH is the same as other IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event output (HOUT).

The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6) followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle period. The IPC Generation Host Register is shown in

Figure 3-13

and described in Table 3-15 .

Figure 3-13 IPC Generation Registers (IPCGRH)

SRCS27

SRCS26

SRCS25

SRCS24

RW +0 RW +0 RW +0 RW +0

SRCS23 – SRCS4

RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCS3 SRCS2 SRCS1 SRCS0

RW +0 RW +0 RW +0 RW +0

Reserved

R, +000

IPCG

RW +0

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 3-15

Bit

31-4

Field

SRCSx

3-1

Reserved

IPCG

IPC Generation Registers (IPCGRH) Field Descriptions

Description

Interrupt source indication.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Sets both SRCSx and the corresponding SRCCx.

Reserved

Host interrupt generation.

Reads return 0.

Writes:

0 = No effect

1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)

End of Table 3-15

3.3.15 IPC Acknowledgement Host (IPCARH) Register

IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in

Figure 3-14 and described in

Table 3-16

Figure 3-14 IPC Acknowledgement Register (IPCARH)

SRCC27

SRCC26

SRCC25

SRCC24

RW +0 RW +0 RW +0 RW +0

SRCC23 – SRCC4

RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCC3 SRCC2 SRCC1 SRCC0

RW +0 RW +0 RW +0 RW +0

Reserved

R, +0000

Table 3-16

Bit

31-4

Field

SRCCx

IPC Acknowledgement Register (IPCARH) Field Descriptions

3-0 Reserved

End of Table 3-16

Description

Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Clears both SRCCx and the corresponding SRCSx

Reserved

Submit Documentation Feedback

Device Configuration 78

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.16 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown

in Figure 3-15

and described in

Table 3-17

Figure 3-15 Timer Input Selection Register (TINPSEL)

31 16

Reserved

R, +1010 1010 1010 1010

TINPH

SEL7

TINPL

SEL7 spacer

TINPH

SEL6

TINPL

SEL6

TINPH

SEL5

TINPL

SEL5

TINPH

SEL4

TINPL

SEL4

TINPH

SEL3

TINPL

SEL3

TINPH

SEL2

TINPL

SEL2

TINPH

SEL1

TINPL

SEL1

TINPH

SEL0

TINPL

SEL0

RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-17

Bit Field

31-16 Reserved

15 TINPHSEL7

TINPLSEL7

TINPHSEL6

TINPLSEL6

TINPHSEL5

TINPLSEL5

TINPHSEL4

TINPLSEL4

TINPHSEL3

TINPLSEL3

Timer Input Selection Field Description (TINPSEL) (Part 1 of 2)

TINPHSEL2

Description

Reserved

Input select for TIMER7 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER7 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER6 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER6 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER5 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER5 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER4 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER4 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER3 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER3 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER2 high.

0 = TIMI0

1 = TIMI1

Submit Documentation Feedback

www.ti.com

Table 3-17

Bit

Field

TINPLSEL2

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Timer Input Selection Field Description (TINPSEL) (Part 2 of 2)

TINPHSEL1

TINPLSEL1

TINPHSEL0

TINPLSEL0

Description

Input select for TIMER2 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER1 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER1 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER0 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER0 low.

0 = TIMI0

1 = TIMI1

End of Table 3-17

Submit Documentation Feedback

Device Configuration 80

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.17 Timer Output Selection Register (TOUTPSEL)

The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register is shown in

Figure 3-16 and described in Table 3-18 .

Figure 3-16 Timer Output Selection Register (TOUTPSEL)

Reserved

R,+000000000000000000000000

Legend: R = Read only; RW = Read/Write; -n = value after reset

10 9

TOUTPSEL1

RW,+00001

5 4

TOUTPSEL0

RW,+00000

Table 3-18

Bit

31-10

9-5

4-0

Timer Output Selection Field Description (TOUTPSEL)

Field

Reserved

TOUTPSEL1

TOUTPSEL0

Description

Reserved

Output select for TIMO1

0x0: TOUTL0

0x1: TOUTH0

0x2: TOUTL1

0x3: TOUTH1

0x4: TOUTL2

0x5: TOUTH2

0x6: TOUTL3

0x7: TOUTH3

0x8: TOUTL4

Output select for TIMO0

0x0: TOUTL0

0x1: TOUTH0

0x2: TOUTL1

0x3: TOUTH1

0x4: TOUTL2

0x5: TOUTH2

0x6: TOUTL3

0x7: TOUTH3

0x8: TOUTL4

0x9: TOUTH4

0xA: TOUTL5

0xB: TOUTH5

0xC: TOUTL6

0xD: TOUTH6

0xE: TOUTL7

0xF: TOUTH7

0x10 to 0x1F: Reserved

0x9: TOUTH4

0xA: TOUTL5

0xB: TOUTH5

0xC: TOUTL6

0xD: TOUTH6

0xE: TOUTL7

0xF: TOUTH7

0x10 to 0x1F: Reserved

End of Table 3-18

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.18 Reset Mux (RSTMUXx) Register

The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through

RSTMUX1 for each of the two CorePacs on the C6657. The C6655 has only RSTMUX0. These registers are located

in Bootcfg memory space. The Reset Mux Register is shown in Figure 3-17 and described in Table 3-19 .

Figure 3-17 Reset Mux Register RSTMUXx

Reserved

R, +0000 0000 0000 0000 0000 00

EVTSTATCLR

RC, +0

Reserved

R, +0

DELAY

RW, +100

Legend: R = Read only; RW = Read/Write; -n = value after reset; RC

= Read only and write 1 to clear

EVTSTAT

R, +0

OMODE

RW, +000

LOCK

RW, +0

Table 3-19 Reset Mux Register Field Descriptions

Bit Field

31-10 Reserved

7-5

Description

Reserved

EVTSTATCLR Clear event status

0 = Writing 0 has no effect

1 = Writing 1 clears the EVTSTAT bit

Reserved

DELAY

Reserved

Delay cycles between NMI & local reset

000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b

001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)

101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

3-1

EVTSTAT

OMODE

LOCK

Event status.

0 = No event received (Default)

1 = WD timer event received by Reset Mux block

Timer event operation mode

000b = WD timer event input to the reset mux block does not cause any output event (default)

001b = Reserved

010b = WD timer event input to the reset mux block causes local reset input to CorePac

011b = WD timer event input to the reset mux block causes NMI input to CorePac

100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay between NMI and local reset is set in DELAY bit field.

101b = WD timer event input to the reset mux block causes device reset to C6655/57

110b = Reserved

111b = Reserved

Lock register fields

0 = Register fields are not locked (default)

1 = Register fields are locked until the next timer reset

End of Table 3-19

Submit Documentation Feedback

Device Configuration 82

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.19 Device Speed (DEVSPEED) Register

The Device Speed Register indicates the device speed grade. The Device Speed Register is shown in Figure 3-18

and

described in Table 3-20 .

Figure 3-18 Device Speed Register (DEVSPEED)

Reserved

R-n

DEVSPEED

R-n

23 22

Legend: R = Read only; RW = Read/Write; -n = value after reset

Reserved

R-n

Table 3-20 Device Speed Register Field Descriptions

Bit

Field

Reserved

30-23 DEVSPEED

22-0 Reserved

End of Table 3-20

Description

Reserved. Read only

Indicates the speed of the device (Read Only)

1xxx xxxxb = 850 MHz

01xx xxxxb = 1000 MHz

001x xxxxb = 1250 MHz

0001 xxxxb = Reserved

0000 1xxxb = Reserved

0000 01xxb = 1250 MHz

0000 001xb = 1000 MHz

0000 0001b = 850 MHz

0000 0000b = 850 MHz

Reserved. Read only

3.3.20 Pin Control 0 (PIN_CONTROL_0) Register

The Pin Control 0 Register controls the pin muxing between GPIO[16:31] and TIMER / UART / SPI pins. The Pin

Control 0 Register is shown in Figure 3-19

and described in Table 3-21

Figure 3-19 Pin Control 0 Register (PIN_CONTROL_0)

31 30 29 28 27 26 25 24

GPIO31_SPIDOU

T_MUX

GPIO30_SPIDIN_

MUX

GPIO29_SPICS1_

MUX

GPIO28_SPICS0_

MUX

GPIO27_UARTRT

S1_MUX

GPIO26_UARTCT

S1_MUX

GPIO25_UARTTX

1_MUX

GPIO24_UARTRX

1_MUX

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 spacer

23 22 21 20 19

GPIO23_UARTRT

S0_MUX

GPIO22_UARTCT

S0_MUX

GPIO21_UARTTX

0_MUX

GPIO20_UARTRX

0_MUX

GPIO19_TIMO1_

MUX

RW-0 RW-0 RW-0 RW-0 RW-0 spacer

GPIO18_TIMO0_

MUX

RW-0

GPIO17_TIMI1_

MUX

RW-0

GPIO16_TIMI0_

MUX

RW-0

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Submit Documentation Feedback

www.ti.com

Table 3-21

Bit

Pin Control 0 Register Field Descriptions

Field

GPIO31_SPIDOUT_MUX

GPIO30_SPIDIN_MUX

GPIO29_SPICS1_MUX

GPIO28_SPICS0_MUX

GPIO27_UARTRTS1_MUX

GPIO26_UARTCTS1_MUX

GPIO25_UARTTX1_MUX

GPIO24_UARTRX1_MUX

GPIO23_UARTRTS0_MUX

GPIO22_UARTCTS0_MUX

GPIO21_UARTTX0_MUX

GPIO20_UARTRX0_MUX

GPIO19_TIMO1_MUX

GPIO18_TIMO0_MUX

GPIO17_TIMI1_MUX

GPIO16_TIMI0_MUX

15-0 Reserved

End of Table 3-21

Description

SPI or GPIO mux control

0 = SPIDOUT pin enabled

1 = GPIO31 pin enabled

SPI or GPIO mux control

0 = SPIDIN pin enabled

1 = GPIO30 pin enabled

SPI or GPIO mux control

0 = SPICS1 pin enabled

1 = GPIO29 pin enabled

SPI or GPIO mux control

0 = SPICS0 pin enabled

1 = GPIO28 pin enabled

UART or GPIO mux control

0 = UARTRTS1 pin enabled

1 = GPIO27 pin enabled

UART or GPIO mux control

0 = UARTCTS1 pin enabled

1 = GPIO26 pin enabled

UART or GPIO mux control

0 = UARTTX1 pin enabled

1 = GPIO25 pin enabled

UART or GPIO mux control

0 = UARTRX1 pin enabled

1 = GPIO24 pin enabled

UART or GPIO mux control

0 = UARTRTS0 pin enabled

1 = GPIO23 pin enabled

UART or GPIO mux control

0 = UARTCTS0 pin enabled

1 = GPIO22 pin enabled

UART or GPIO mux control

0 = UARTTX0 pin enabled

1 = GPIO21 pin enabled

UART or GPIO mux control

0 = UARTRX0 pin enabled

1 = GPIO20 pin enabled

TIMER or GPIO mux control

0 = TIMO1 pin enabled

1 = GPIO19 pin enabled

TIMER or GPIO mux control

0 = TIMO0 pin enabled

1 = GPIO18 pin enabled

TIMER or GPIO mux control

0 = TIMI1 pin enabled

1 = GPIO17 pin enabled

TIMER or GPIO mux control

0 = TIMI0 pin enabled

1 = GPIO16 pin enabled

Reserved

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Submit Documentation Feedback

Device Configuration 84

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.3.21 Pin Control 1 (PIN_CONTROL_1) Register

The Pin Control 0 Register controls the pin muxing between uPP and EMIF16 pins. The Pin Control 1 Register is

shown in Figure 3-20 and described in Table 3-22 .

Figure 3-20 Pin Control 1Register (PIN_CONTROL_1)

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

UPP_EMIF16_MUX

RW-0

Table 3-22 Pin Control 1 Register Field Descriptions

Bit Field

31-1 Reserved

0 UPP_EMIF_MUX

Description

Reserved uPP or EMIF16 mux control

0 = EMIF16 pins enabled

1 = uPP pins enabled

End of Table 3-22

3.3.22 uPP Clock Source (UPP_CLOCK) Register

The uPP Clock Source Register controls whether the uPP transmit clock is internally or externally sourced. The uPP

Clock Source Register is shown in Figure 3-21

and described in

Table 3-23

Figure 3-21 Pin Control 1Register (PIN_CONTROL_1)

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

UPP_TX_CLKSRC

RW-0

Table 3-23 Pin Control 1 Register Field Descriptions

Bit Field

31-1 Reserved

0 UPP_TX_CLKSRC

Description

Reserved uPP clock source selection

0 = from internal SYSCLK4 (CPU/3)

1 = from external UPP_2XTXCLK pin

End of Table 3-23

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

3.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown

(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

•

Device Configuration Pins:

If the pin is both routed out and are not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

•

Other Input Pins:

If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in

Table 3-1 ), if they are both routed out and are not driven (in Hi-Z state),

it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.

• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V

IL connected to the net. For a pullup resistor, this should be above the highest V

A reasonable choice would be to target the V

OL by definition, have margin to the V

and V

or V

levels.

level of all inputs

level of all inputs on the net.

levels for the logic family of the limiting device; which,

• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.

• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).

• Remember to include tolerances when selecting the resistor value.

• For pullup resistors, also remember to include tolerances on the DV

rail.

For most systems:

• A 1-k

Ω resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

• A 20-k

Ω resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

), and the low-level/high-level input voltages (V

and V

) for

the TMS320C6655/57 device, see Section 6.3

‘‘Electrical Characteristics’’ on page 105.

To determine which pins on the device include internal pullup/pulldown resistors, see

Table 2-19 ‘‘Terminal

Functions — Signals and Control by Function’’ on page 38.

Submit Documentation Feedback

Device Configuration 86

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

4 System Interconnect

www.ti.com

On the TMS320C6655/57 device, the C66x CorePacs, the EDMA3 transfer controller, and the system peripherals are interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contention-free internal data movement. The TeraNet allows for low-latency, concurrent data transfers between master peripherals and slave peripherals. The TeraNet also allows for seamless arbitration between the system masters when accessing system slaves.

4.1 Internal Buses and Switch Fabrics

Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus and a configuration bus interface, while others have only one type of interface. Further, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers.

The C66x CorePacs, the EDMA3 traffic controller, and the various system peripherals can be classified into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the masters to perform transfers to and from them. Examples of masters include the EDMA3 traffic controller, SRIO, and PCI Express. Examples of slaves include the SPI, UART, and I

The masters and slaves in the device are communicating through the TeraNet (switch fabric). The device contains two switch fabrics. The data switch fabric (data TeraNet) and the configuration switch fabric (configuration

TeraNet). The data TeraNet, is a high-throughput interconnect mainly used to move data across the system. The data TeraNet connects masters to slaves via data buses. The configuration TeraNet, is mainly used to access peripheral registers. The configuration TeraNet connects masters to slaves via configuration buses. Note that the

data TeraNet also connects to the configuration TeraNet. For more details see 4.2

‘‘Switch Fabric Connections

Matrix’’ on page 88.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

4.2 Switch Fabric Connections Matrix

The tables below list the master and slave end point connections.

Intersecting cells may contain one of the following:

• Y — There is a connection between this master and that slave.

• - — There is NO connection between this master and that slave.

• n — A numeric value indicates that the path between this master and that slave goes through bridge n.

Table 4-1 Switch Fabric Connection Matrix Section 1

Slaves

Masters

HyperLink_Master

EDMA3CC_TC0_RD

EDMA3CC_TC0_WR Y

EDMA3CC_TC1_RD Y

EDMA3CC_TC1_WR Y

EDMA3CC_TC2_RD Y

EDMA3CC_TC2_WR Y

EDMA3CC_TC3_RD Y

EDMA3CC_TC3_WR Y

SRIO packet DMA

SRIO_Master

PCIe_Master

EMAC

MSMC_Data_Master Y

QM packet DMA Y

QM_Second

DAP_Master

CorePac0_CFG

CorePac1_CFG

(C6657 Only)

Tracer_Master

UPP

End of Table 4-1

Y Y

Y -

3 -

Y Y

Y 1, 4 1, 4 1

Y -

Y 2, 4 2, 4 -

Y 1, 4 1, 4 -

Y 2

Y 1, 4 1, 4 1

1 Y

Submit Documentation Feedback

System Interconnect 88

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 4-2 Switch Fabric Connection Matrix Section 2

Slaves www.ti.com

Masters

HyperLink_Master

EDMA3CC_TC0_RD

EDMA3CC_TC0_WR

EDMA3CC_TC1_RD

EDMA3CC_TC1_WR

EDMA3CC_TC2_RD

EDMA3CC_TC2_WR

EDMA3CC_TC3_RD

EDMA3CC_TC3_WR

SRIO packet DMA

SRIO_Master

PCIe_Master

EMAC

MSMC_Data_Master

QM packet DMA

QM_Second

DAP_Master

EDMA3CC

CorePac0_CFG

CorePac1_CFG

(C6657 Only)

Tracer_Master

UPP

End of Table 4-2

1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1

1 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1 1,4 1,4 1,4 1,4 1,4 1

1 1, 4 1, 4 1, 4 1, 4 1, 4

1, 4

1 1, 4 1, 4 1, 4 1, 4 1, 4

1, 4

1, 4 1, 4 1, 4 1, 4 1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1

1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1

Y 4 4 4 4 4 4 4 4 4 4 Y 4 4 4 4 4 4 4

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

4.3 TeraNet Switch Fabric Connections

The figures below show the connections between masters and slaves through various sections of the TeraNet.

Figure 4-1 TeraNet 3A

XMC

EMAC

UPP

HyperLink

PCIe

SRIO_M

SRIO

Packet DMA

QM_SS

Packet DMA

QM_SS

Second

EDMA

Debug_SS

TC_0

TC_1

TC_2

TC_3

TNet_3_D

CPU/3

Bridge 3

SES

SMS

M S

MSMC

Tracer_MSMC0

Tracer_MSMC1

Tracer_MSMC2

Tracer_MSMC3

Tracer_DDR

HyperLink

CorePac_0

Tracer_L2_0

Tracer_L2_1

Tracer_QM_M

TNet_3_B

CPU/3

TNet_6P_A

CPU/3

C5557 Only

MPU_1

MPU_4

CorePac_1

QM_SS

PCIe

VCP2

TCP3d

McBSP0

McBSP1

SPI

Boot_ROM

EMIF

Tracer_TN_6P_A

To TeraNet_3P_A

DDR3

Bridge_1

Bridge_2

Submit Documentation Feedback

System Interconnect 90

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 4-2 TeraNet 3P_A

Bridge_1

Bridge_2

From TeraNet_3_A

CorePac_0

CorePac_1

C6657 Only

www.ti.com

TNet_3P_C

CPU/3

Tracer_QM_CFG

Tracer_SM

MPU_2

MPU_3

MPU_0

MPU0

MPU1

MPU2

MPU3

QM_SS

Semaphore

TETB (Debug_SS)

TETB (core) (

To TeraNet_3P_Tracer

To TeraNet_3P_B

Tracer_CFG for C6655,

Figure 4-3 TeraNet 3P_B

From TeraNet_3P_A

TNet_3P_E

CPU/3

To TeraNet_6P_B

Tracer (

SRIO

UPP

VCP2

TCP3d

Bridge_4

* for C6655,

Submit Documentation Feedback

www.ti.com

Figure 4-4 TeraNet 3P_Tracer

From TeraNet_3P_A

Tracer_

MSMC_0

Tracer_

MSMC_1

Tracer_

MSMC_2

Tracer_

MSMC_3

Tracer_CFG

Tracer_DDR

Tracer_SM

Tracer_

QM_M

Tracer_

QM_P

Tracer_L2_

* M

Tracer_TN_

6P_A

0 for C6655, 0 to 1 for C6657

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Debug_SS

STM

Debug_SS

TETB

Submit Documentation Feedback

System Interconnect 92

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 4-5 TeraNet 6P_B

Bridge_4

From TeraNet_3P_B

www.ti.com

SmartReflex

GPIO

I C

BOOTCFG

PSC

PLL_CTL

Debug_SS

MPU4

EMAC

McBSP

SEC_CTL

SEC_KEY_MGR

Efuse

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

4.4 Bus Priorities

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means higher priority - PRI = 000b = urgent, PRI = 111b = low.

Most master ports provide their priority directly and do not need a default priority setting. Examples include the

CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-based peripherals also have internal registers to define the priority level of their initiated transactions.

Some masters do not have apriority allocation register of their own. For these masters, a priority allocation register is provided for them and described in the sections below. For all other modules, see the respective User Guides in

for programmable priority registers.

4.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register

The packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in

Figure 4-6 and

Table 4-3

Figure 4-6 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)

Reserved

R/W-00000000000000000000001000011

Legend: R = Read only; R/W = Read/Write; -n = value after reset

3 2 0

PKTDMA_PRI

RW-000

Table 4-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions

Bit

31-3

Field

Reserved

2-0 PKDTDMA_PRI

End of Table 4-3

Description

Reserved.

Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.

Submit Documentation Feedback

System Interconnect 94

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

4.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register

The EMAC and uPP are master ports that do not have priority allocation registers inside the IP. The priority level for transaction from these master ports is described by EMAC_UPP_PRI_ALLOC register in

Figure 4-7 and

Table 4-4

Figure 4-7 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC)

31 27 26 24 23 19 18

Reserved

R-00000

EMAC_EPRI

RW-110

Reserved

R-00000

EMAC_PRI

RW-111

Legend: R = Read only; R/W = Read/Write; -n = value after reset

16 15

Reserved

R-00000

11 10

UPP_EPRI

RW-110

8 7

Reserved

R-00000

3 2

UPP_PRI

RW-111

Table 4-4 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions

Bit Field

31-27 Reserved

26-24 EMAC_EPRI

23-19 Reserved

18-16 EMACA_PRI

15-11 Reserved

10-8

7-3

UPP_EPRI

Reserved

2-0 UPP_PRI

End of Table 4-4

Description

Reserved.

Control the maximum priority level for the transactions from EMAC master port.

Reserved.

Control the priority level for the transactions from EMAC master port.

Reserved.

Control the maximum priority level for the transactions from uPP master port.

Reserved.

Control the priority level for the transactions from uPP master port.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

5 C66x CorePac

The C66x CorePac consists of several components:

• The C66x DSP and associated C66x CorePac core

• Level-one and level-two memories (L1P, L1D, L2)

• Data Trace Formatter (DTF)

• Embedded Trace Buffer (ETB)

• Interrupt Controller

• Power-down controller

• External Memory Controller

• Extended Memory Controller

• A dedicated power/sleep controller (LPSC)

www.ti.com

The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the

C66x CorePac) and address extension.

Figure 5-1

shows a block diagram of the C66x CorePac.

Figure 5-1 C66x CorePac Block Diagram

32KB L1P

PLLC

Boot

Controller

LPSC

GPSC

Program Memory Controller (PMC) With

Memory Protect/Bandwidth Mgmt

C66x DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

In-Circuit Emulation

Instruction Decode

Data Path A Data Path B

A Register File

A31-A16

A15-A0

B Register File

B31-B16

B15-B0

.L1

.S1

.M1

xx xx

.D1

.D2

.M2

xx xx

.S2

.L2

L2 Cache/

SRAM

1024KB

MSM

SRAM

1024KB

DDR3

SRAM

DMA Switch

Fabric

Data Memory Controller (DMC) With

Memory Protect/Bandwidth Mgmt

CFG Switch

Fabric

32KB L1D

For more detailed information on the TMS320C66x CorePac on the C6655/57 device, see the C66x CorePac User

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

5.1 Memory Architecture

Each C66x CorePac of the device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The C6655/57 devices also contain a 1024KB multicore shared memory

(MSM). All memory on the C6655/57 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map

Summary’’ on page 20.

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the

L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader

for the C66x DSP User Guide in

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in

5.1.1 L1P Memory

The L1P memory configuration for the C6655/57 device is as follows:

• 32K bytes with no wait states

Figure 5-2

shows the available SRAM/cache configurations for L1P.

Figure 5-2 L1P Memory Configurations

L1P mode bits

000 001 010 011 100 L1P memory

Block base address

00E0 0000h

All

SRAM

7/8

SRAM

3/4

SRAM

1/2

SRAM direct mapped cache dm cache direct mapped cache direct mapped cache

16K bytes

00E0 4000h

8K bytes

4K bytes

00E0 6000h

00E0 7000h

00E0 8000h

Submit Documentation Feedback

C66x CorePac 97

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

5.1.2 L1D Memory

The L1D memory configuration for the C6655/57 device is as follows:

• 32K bytes with no wait states

Figure 5-3

shows the available SRAM/cache configurations for L1D.

Figure 5-3 L1D Memory Configurations

L1D mode bits

000 001 010 011 100 L1D memory

Block base address

00F0 0000h

All

SRAM

7/8

SRAM

3/4

SRAM

1/2

SRAM

2-way cache

16K bytes

00F0 4000h

8K bytes

4K bytes

00F0 6000h

00F0 7000h

00F0 8000h

www.ti.com

5.1.3 L2 Memory

The L2 memory configuration for the C6655/57 device is as follows:

• Total memory is 1024KB (C6655) or 2048KB (C6657)

• Each core contains 1024KB of memory

• Local starting address for each core is 0080 0000h

L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register

(L2CFG) of the C66x CorePac.

Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is

configured as all SRAM after device reset.

Submit Documentation Feedback

www.ti.com

Figure 5-4

000

L2 Memory Configurations

L2 Mode Bits

001 010 011 100

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

101 110 L2 Memory

Block Base

Address

0080 0000h

1/2

SRAM

512K bytes

ALL

SRAM

31/32

SRAM

15/16

SRAM

7/8

SRAM

3/4

SRAM

4-Way

Cache

0088 0000h

256K bytes

4-Way

Cache

008C 0000h

128K bytes

4-Way

Cache

008E 0000h

4-Way

Cache

4-Way

Cache

4-Way

Cache

64K bytes

32K bytes

008F 0000h

008F 8000h

008F FFFFh

Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.

For C66x CorePac Core 0, address 0x00800000 is equivalent to 0x10800000, and for C66x CorePac Core 1 (C6657 only) address 0x00800000 is equivalent to 0x11800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.

Submit Documentation Feedback

C66x CorePac 99

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

5.1.4 MSM SRAM

The MSM SRAM configuration for the device is as follows:

• Memory size is 1024KB

• The MSM SRAM can be configured as shared L2 and/or shared L3 memory

• Allows extension of external addresses from 2GB to up to 8GB

• Has built in memory protection features

www.ti.com

The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in

L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the Multicore Shared Memory Controller

(MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

5.1.5 L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

5.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct

DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.

The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether memory pages are locally or globally accessible.

The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see

Table 5-1

Table 5-1

AIDx Bit

Available Memory Page Protection Schemes

Local Bit Description

0 No access to memory page is permitted.

Only direct access by DSP is permitted.

Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).

End of Table 5-1

Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:

• Block the access — reads return 0, writes are ignored

• Capture the initiator in a status register — ID, address, and access type are stored

• Signal event to DSP interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

5.3 Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth Management control hardware:

• Level 1 Program (L1P) SRAM/Cache

• Level 1 Data (L1D) SRAM/Cache

• Level 2 (L2) SRAM/Cache

• Memory-mapped registers configuration bus

The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x

CorePac. These operations are:

• DSP-initiated transfers

• User-programmed cache coherency operations

• IDMA-initiated transfers

The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the

Priority Allocation Register (PRI_ALLOC), see section 4.4

‘‘Bus Priorities’’ on page 94 for more details. System

peripherals with no fields in the PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the C66x CorePac can be found in the C66x CorePac

User Guide in

5.4 Power-Down Control

The C66x CorePac supports the ability to power down various parts of the C66x CorePac. The power down controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power requirements.

Note—

The C6655/57 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C66x CorePac can be found in the TMS320C66x CorePac

Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

Submit Documentation Feedback

C66x CorePac 101

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

5.5 C66x CorePac Revision

The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in

Figure 5-5

and described in

Table 5-2

. The

C66x CorePac revision is dependant on the silicon revision being used.

Figure 5-5 CorePac Revision ID Register (MM_REVID)

Address - 0181 2000h

VERSION

R-n

Legend: R = Read; -n = value after reset

16 15

REVISION

R-n

Table 5-2

Bit Field

31-16 VERSION

15-0 REVISION

End of Table 5-2

CorePac Revision ID Register (MM_REVID) Field Descriptions

Description

Version of the C66x CorePac implemented on the device.

Revision of the C66x CorePac version implemented on the device.

5.6 C66x CorePac Register Descriptions

See the C66x CorePac Reference Guide in

offsets and definitions.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

6 Device Operating Conditions

6.1 Absolute Maximum Ratings www.ti.com

Table 6-1 Absolute Maximum Ratings

(1)

Over Operating Case Temperature Range (Unless Otherwise Noted)

Supply voltage range

Input voltage (V

(2)

) range:

Output voltage (V

) range:

Operating case temperature range, T

ESD stress voltage, V

ESD

(3)

CVDD

CVDD1

DVDD15

DVDD18

VREFSSTL

VDDT1, VDDT2

VDDR1, VDDR2, VDDR3, VDDR4

AVDDA1, AVDDA2

VSS Ground

LVCMOS (1.8V)

DDR3

LVDS

LJCB

SerDes

LVCMOS (1.8V)

DDR3

SerDes

Commercial

Extended

HBM (human body model)

(4)

CDM (charged device model)

(5)

-0.3 V to 1.3 V

-0.3 V to 2.45 V

0.49 × DVDD15 to 0.51 × DVDD15

-0.3 V to 1.3 V

-0.3 V to 2.45 V

0 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 2.45 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 1.3 V

-0.3 V to CVDD1+0.3 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 2.45 V

-0.3 V to CVDD1+0.3 V

0°C to 85°C

-40°C to 100°C

±1000 V

±250 V

Overshoot/undershoot

(6)

LVCMOS (1.8V)

DDR3

20% Overshoot/Undershoot for 20% of

Signal Duty Cycle

Storage temperature range, T stg

End of Table 6-1

-65°C to 150°C

1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2 All voltage values are with respect to V

3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

4 Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.

5 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be V

- 0.20 × DVDD18

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

6.2 Recommended Operating Conditions

Table 6-2 Recommended Operating Conditions

(1) (2)

CVDD

SR Core Supply

CVDD1

DVDD18

DVDD15

1.8-V supply I/O voltage

1.5-V supply I/O voltage

VREFSSTL

DDRx

(5)

DDAx

DDTx

DDR3 reference voltage

SerDes regulator supply

PLL analog supply

SerDes termination supply

Ground

1250MHZ - Device

Core supply voltage for memory array

High-level input voltage

LVCMOS (1.8 V)

DDR3 EMIF

LVCMOS (1.8 V)

Low-level input voltage

850MHz - Device

1000MHz - Device

Operating case temperature

DDR3 EMIF

Commercial

Extended

End of Table 6-2

SRVnom

(3)

Min

× 0.95

SRVnom × 0.95

0.95

1.71

1.425

0.49 × DVDD15

1.425

1.71

0.95

0.65 × DVDD18

0.7 × DVDD18

VREFSSTL + 0.1

-0.3

-40

Nom

0.85-1.1

(4)

0.85-1.1

1.8

1.5

0.5 × DVDD15

1.5

1.8

Max Unit

SRVnom × 1.05

1.05

1.89

1.575

0.51 × DVDD15

1.575

1.89

1.05

0.35 × DVDD18

VREFSSTL - 0.1

0.3 × DVDD18

100

°C

1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE

802.3ae-2002.

2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

3 SRVnom refers to the unique SmartReflex core supply voltage between 0.85 V and 1.1 V set from the factory for each individual device.

4 The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on VCNTL pins. This is required to maintain full power functionality and reliability targets guaranteed by TI.

5 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.

Submit Documentation Feedback

Device Operating Conditions 104

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

6.3 Electrical Characteristics www.ti.com

Table 6-3 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Parameter

LVCMOS (1.8 V)

Test Conditions

(1)

= I

Min

DVDD18 - 0.45

DDR3

(2)

DVDD15 - 0.4

Typ Max Unit

(3)

Low-level output voltage

Input current [DC]

LVCMOS (1.8 V)

DDR3

LVCMOS (1.8 V)

= I

0.45

0.4

= 3 mA, pulled up to 1.8 V

No IPD/IPU

Internal pullup

Internal pulldown

-5

-170

100

-100

0.4

170

(4)

-50

0.1 × DVDD18 V < V

< 0.9 ×

DVDD18 V

-10 10

High-level output current [DC]

LVCMOS (1.8 V)

DDR3

(5)

LVCMOS (1.8 V)

Low-level output current [DC]

(6)

Off-state output current [DC]

DDR3

LVCMOS (1.8 V) -2

DDR3 -2

C -2

End of Table 6-3

-6

-8

μA mA mA

μA

1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

C uses open collector IOs and does not have a V

Minimum.

3 I

applies to input-only pins and bi-directional pins. For input-only pins, I

I off-state (Hi-Z) output leakage current.

indicates the input leakage current. For bi-directional pins, I

I includes input leakage current and

4 For RESETSTAT, max DC input current is 300

μA.

5 I

C uses open collector IOs and does not have a I

Maximum.

6 I

applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

Submit Documentation Feedback

www.ti.com

6.4 Power Supply to Peripheral I/O Mapping

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Power Supply to Peripheral I/O Mapping

(1) (2)

Table 6-4

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

CVDD

DVDD15

DVDD18

Power Supply

Supply Core Voltage

1.5-V supply I/O voltage

1.8-V supply I/O voltage

I/O Buffer Type

LJCB

Associated Peripheral

CORECLK(P|N) PLL input buffer

SRIOSGMIICLK(P|N) SerDes PLL input buffer

DDRCLK(P|N) PLL input buffer

PCIECLK(P|N) SERDES PLL input buffer

MCMCLK(P|N) SERDES PLL input buffer

All DDR3 memory controller peripheral I/O buffer

LJCB

DDR3 (1.5 V)

LVCMOS (1.8 V)

All GPIO peripheral I/O buffer

All JTAG and EMU peripheral I/O buffer

All Timer peripheral I/O buffer

All SPI peripheral I/O buffer

All RESETs, NMI, Control peripheral I/O buffer

All SmartReflex peripheral I/O buffer

All MDIO peripheral I/O buffer

All UART peripheral I/O buffer

All McBSP peripheral I/O buffer

All EMIF16 peripheral I/O buffer

All uPP peripheral I/O buffer

Open-drain (1.8V) All I

C peripheral I/O buffer

LVCMOS (1.8 V)

SerDes/CML

All Hyperlink sideband peripheral I/O buffer

Hyperlink SerDes CML IO buffer

DVDD18 1.8-V supply I/O voltage

VDDT1

VDDT2

Hyperlink SerDes termination and analogue front-end supply

SRIO/SGMII/PCIE SerDes termination and analogue front-end supply

SerDes/CML SRIO/SGMII/PCIE SerDes CML IO buffer

End of Table 6-4

1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers.

2 Please see the Hardware Design Guide for KeyStone Devices in

peripheral I/O.

Submit Documentation Feedback

Device Operating Conditions 106

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7 Peripheral Information and Electrical Specifications

www.ti.com

This chapter covers the various peripherals on the TMS320C6655/57 DSP. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.

7.1 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals

must transition between V

IH manner.

and V

(or between V

and V

) in a monotonic

7.2 Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the

C6655/57. The various power supply rails and their primary function is listed in

Table 7-1

Table 7-1 Power Supply Rails on TMS320C6655/57

Name

CVDD

CVDD1

VDDT1

VDDT2

DVDD15

VDDR1

VDDR2

VDDR3

VDDR4

Primary Function

SmartReflex core supply voltage

Core supply voltage for memory array

HyperLink SerDes termination supply

Voltage

0.85 V - 1.1 V Includes core voltage for DDR3 module

1.0 V

SGMII/SRIO/PCIE SerDes termination supply

1.0 V

1.5-V DDR3 IO supply 1.5 V

HyperLink SerDes regulator supply 1.5 V

Notes

Fixed supply at 1.0 V

Filtered version of CVDD1. Special considerations for noise. Filter is not needed if

HyperLink is not in use.

Filtered version of CVDD1. Special considerations for noise. Filter is not needed if

SGMII/SRIO/PCIE is not in use.

PCIE SerDes regulator supply

SGMII SerDes regulator supply

SRIO SerDes regulator supply

1.5 V

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if

HyperLink is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if

PCIE is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if

SGMII is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if

HyperLink is not in use.

DVDD18

AVDDA1

AVDDA2

VREFSSTL

1.8-V IO supply

Main PLL supply

DDR3 PLL supply

0.75-V DDR3 reference voltage

VSS Ground

End of Table 7-1

1.8V

1.8 V

0.75 V

GND

Filtered version of DVDD18. Special considerations for noise.

Should track the 1.5-V supply. Use 1.5 V as source.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.2.1 Power-Supply Sequencing

This section defines the requirements for a power up sequencing from a power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below.

CVDD

CVDD1, VDDT1-2

DVDD18, AVDDA1, AVDDA2

DVDD15, VDDR1-4

The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.

DVDD18, AVDDA1, AVDDA2

CVDD

CVDD1, VDDT1-2

DVDD15, VDDR1-4

The clock input buffers for CORECLK, DDRCLK, SRIOSGMIICLK, MCMCLK, and PCIECLK use only CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once

CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the clock inputs should be removed from the high impedance state shortly after CVDD is present.

If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled to ground through a 1K ohm resistor. The P leg should be tied to CVDD to ensure it won't have any voltage present until

CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device.

The device initialization is broken into two phases. The first phase consists of the time period from the activation of the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire power stabilization phase.

This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock that is used by the CorePac, see

Figure 7-7 for more details.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 108

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.2.1.1 Core-Before-IO Power Sequencing

Figure 7-1

shows the power sequencing and reset control of TMS320C6655/57 for device initialization. POR may be removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the

GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified.

SYSCLK1 must always be active before POR can be removed. Core-before-IO power sequencing is defined in

Table 7-2

Note—

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp

Figure 7-1 Core Before IO Power Sequencing

Power Stabilization Phase Device Initialization Phase

POR

RESETFULL

GPIO Config

Bits

9 10

RESET

CVDD

CVDD1

DVDD18

DVDD15

SYSCLK1P&N

DDRCLKP&N

RESETSTAT

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-2 Core Before IO Power Sequencing

Time

System State

Begin Power Stabilization Phase

• CVDD (core AVS) ramps up.

• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from

POR) is put into the reset state.

• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.

• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.

• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t6.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.

• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the voltage for DVDD15 must never exceed DVDD18.

• RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven high.

• POR must continue to remain low for at least 100 μs after power has stabilized.

End Power Stabilization Phase

• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.

• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.

• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.

• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles.

End Device Initialization Phase

9 • GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL

10 • GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL

End of Table 7-2

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 110

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.2.1.2 IO-Before-Core Power Sequencing

The timing diagram for IO-before-core power sequencing is shown in

Figure 7-2

and defined in Table 7-3 .

www.ti.com

Note—

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.

Figure 7-2 IO Before Core Power Sequencing

Power Stabilization Phase Device Initialization Phase

POR

5 7

RESETFULL

GPIO Config

Bits

9 10

RESET

CVDD

CVDD1

DVDD18

DVDD15

SYSCLK1P&N

DDRCLKP&N

RESETSTAT

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-3 IO Before Core Power Sequencing

Time

System State

Begin Power Stabilization Phase

• Because POR is low, all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must remain low through Power Stabilization Phase.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before

DVDD18 could cause damage to the device.

• RESET may be driven high anytime after DVDD18 is at a valid level.

• CVDD (core AVS) ramps up.

• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1.

• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state with one leg high and one leg low.

• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t6.

• DVDD15 (1.5 V) supply is ramped up following CVDD1.

• POR must continue to remain low for at least 100 μs after power has stabilized.

End Power Stabilization Phase

Begin Device Initialization

• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.

• POR must remain low.

• RESETFULL is held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.

• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.

8 • Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles.

End Device Initialization Phase

• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL 9

10 • GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL

End of Table 7-3

7.2.1.3 Prolonged Resets

Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.

7.2.1.4 Clocking During Power Sequencing

Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the

clocks is contingent on the state of the boot configuration pins. Table 7-4 describes the clock sequencing and the

conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until

CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the other connected to CVDD.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 112

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-4 Clock Sequencing

Clock

DDRCLK

Condition

None

Sequencing

Must be present 16 μsec before POR transitions high.

CORECLK None CORECLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.

The SGMII port will be used.

SRIOSGMIICLK must be present 16 μsec before POR transitions high.

SRIOSGMIICLK

SGMII will not be used. SRIO will not be used.

SRIOSGMIICLK is not used and should be tied to a static state.

SGMII will not be used. SRIO will be used as a boot device.

SRIOSGMIICLK

SGMII will not be used. SRIO will be used after boot.

SRIOSGMIICLK must be present 16 μsec before POR transitions high.

SRIOSGMIICLK is used as a source to the SRIO SERDES PLL. It must be present before the SRIO is removed from reset and programmed.

PCIE will be used as a boot device.

PCIECLK must be present 16 μsec before POR transitions high.

PCIECLK PCIE will be used after boot.

PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from reset and programmed.

PCIE will not be used.

HyperLink will be used as a boot device.

PCIECLK is not used and should be tied to a static state.

MCMCLK must be present 16usec before POR transitions high.

MCMCLK HyperLink will be used after boot.

MCMCLK is used as a source to the MCM SERDES PLL. It must be present before the HyperLink is removed from reset and programmed.

HyperLink will not be used.

MCMCLK is not used and should be tied to a static state.

End of Table 7-4

7.2.2 Power-Down Sequence

The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,

POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can also affect long term reliability.

7.2.3 Power Supply Decoupling and Bulk Capacitors

In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply

Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 64.

7.2.4 SmartReflex

Increasing the device complexity increases its power consumption and with the smaller transistor structures responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios.

This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the TMS320C6655/57 device is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each

TMS320C6655/57 device.

To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required to be implemented whenever the TMS320C6655/57 device is used. The voltage selection is done using 4 VCNTL pins which are used to select the output voltage of the core voltage regulator.

For information on implementation of SmartReflex see the Power Management for KeyStone Devices application

report and the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 64.

Table 7-5

(see Figure 7-3

)

SmartReflex 4-Pin VID Interface Switching Characteristics

No.

1 td(VCNTL[2:0]-VCNTL[3]) toh(VCNTL[3] -VCNTL[2:0]) td(VCNTL[2:0]-VCNTL[3])

Parameter

Delay Time - VCNTL[2:0] valid after VCNTL[3] low

Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low

Delay Time - VCNTL[2:0] valid after VCNTL[3] high

5 toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high

VCNTL being valid to CVDD being switched to SmartReflex Voltage

End of Table 7-5

(2)

1 C = 1/SYSCLK1 frequency (See Figure 7-9

)in ms

2 SmartReflex voltage must be set before execution of application code

Figure 7-3 SmartReflex 4-Pin VID Interface Timing

Min Max

300.00

0.07

172020C

(1)

0.07

300.00

172020C

Unit

ns ms ns ms ms

1.1 V

SRV*

* SRV = Smart Reflex Voltage

CVDD

VCNTL[3]

1 3

VCNTL[2:0]

LSB VID[2:0] MSB VID[5:3]

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 114

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.3 Power Sleep Controller (PSC)

The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several important power and clock operations.

For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User

Guide in

7.3.1 Power Domains

The device has several power domains that can be turned on for operation or off to minimize power dissipation. The global power/sleep controller (GPSC) is used to control the power gating of various power domains.

Table 7-6

shows the TMS320C6655/57 power domains.

Table 7-6 Power Domains

Domain

Block(s)

Most peripheral logic

Per-core TETB and System TETB

Reserved

PCIe

SRIO

HyperLink

Reserved

Note

Cannot be disabled

RAMs can be powered down

Reserved

Logic can be powered down

Reserved

MSMC RAM

Reserved

MSMC RAM can be powered down

Reserved

TCP3d

VCP2

C66x Core 0, L1/L2 RAMs

15 Reserved

End of Table 7-6

RAMs can be powered down

L2 RAMs can sleep

C66x Core 1, L1/L2 RAMs (C6657 only) L2 RAMs can sleep

Reserved

Power Connection

Always on

Software control

Reserved

Software control

Reserved

Software control

Reserved

Software control

Software control via C66x CorePac. For details, see the C66x CorePac Reference Guide.

Reserved

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.3.2 Clock Domains

Clock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls the clock gating.

Table 7-7

shows the TMS320C6655/57 clock domains.

Table 7-7

LPSC Number

No LPSC

End of Table 7-7

Clock Domains

Module(s)

Shared LPSC for all peripherals other than those listed in this table

SmartReflex

DDR3 EMIF

EMAC

VCP2_0

Debug Subsystem and Tracers

Per-core TETB and System TETB

Reserved

PCIe

SRIO

Reserved

MSMC RAM

Reserved

VCP2_1

Reserved

C66x CorePac 0 and Timer 0

C66x CorePac 1 (C6657 only) and Timer 1

Bootcfg, PSC, and PLL controller

Notes

Always on

Software control

Reserved

Software control

Reserved

Software control

Reserved

Software control

Reserved

Software control

These modules do not use LPSC

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 116

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.3.3 PSC Register Memory Map

Table 7-8

shows the PSC Register memory map.

Table 7-8 PSC Register Memory Map (Part 1 of 3)

0x318

0x31C

0x320

0x324

0x328

0x32C

0x330

0x334

0x338

0x33C

0x21C

0x220

0x224

0x228

0x22C

0x230

0x234

0x238

0x23C

0x240 - 0x2FC

0x300

0x304

0x308

0x30C

0x310

0x314

Offset

0x000

0x004 - 0x010

0x014

0x018 - 0x11C

0x120

0x124

0x128

0x12C - 0x1FC

0x200

0x204

0x208

0x20C

0x210

0x214

0x218

Reserved

PDCTL0

PDCTL1

PDCTL2

PDCTL3

PDCTL4

PDCTL5

PDSTAT7

PDSTAT8

PDSTAT9

PDSTAT10

PDSTAT11

PDSTAT12

PDSTAT13

PDSTAT14

PDCTL6

PDCTL7

PDCTL8

PDCTL9

PDCTL10

PDCTL11

PDCTL12

PDCTL13

PDCTL14

Reserved

PDSTAT0

PDSTAT1

PDSTAT2

PDSTAT3

PDSTAT4

PDSTAT5

PDSTAT6

Register

PID

Reserved

VCNTLID

Reserved

PTCMD

Reserved

PTSTAT

Description

Peripheral Identification Register

Reserved

Voltage Control Identification Register

(1)

Reserved

Power Domain Transition Command Register

Reserved

Power Domain Transition Status Register

Reserved

Power Domain Status Register 0 (AlwaysOn)

Power Domain Status Register 1 (Per-core TETB and System TETB)

Power Domain Status Register 2 (Reserved)

Power Domain Status Register 3 (PCIe)

Power Domain Status Register 4 (SRIO)

Power Domain Status Register 5 (Hyperlink)

Power Domain Status Register 6 (Reserved)

Power Domain Status Register 7 (MSMC RAM)

Power Domain Status Register 8 (Reserved)

Power Domain Status Register 9 (Reserved)

Power Domain Status Register 10 (Reserved)

Power Domain Status Register 11 (TCP3d)

Power Domain Status Register 12 (VCP2)

Power Domain Status Register 13 (C66x CorePac 0)

Power Domain Status Register 14 (C66x CorePac 1) (C6657) or Reserved (C6655)

Reserved

Power Domain Control Register 0 (AlwaysOn)

Power Domain Control Register 1 (Per-core TETB and System TETB)

Power Domain Control Register 2 (Reserved)

Power Domain Control Register 3 (PCIe)

Power Domain Control Register 4 (SRIO)

Power Domain Control Register 5 (HyperLink)

Power Domain Control Register 6 (Reserved)

Power Domain Control Register 7 (MSMC RAM)

Power Domain Control Register 8 (Reserved)

Power Domain Control Register 9 (Reserved)

Power Domain Control Register 10 (Reserved)

Power Domain Control Register 11 (TCP3d)

Power Domain Control Register 12 (VCP2)

Power Domain Control Register 13 (C66x CorePac 0)

Power Domain Control Register 14 (C66x CorePac 1) (C6657) or Reserved (C6655)

Reserved

117 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 7-8

Offset

0x340 - 0x7FC

0x800

0x804

0x808

0x80C

0x810

0x814

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

PSC Register Memory Map (Part 2 of 3)

Register

Reserved

MDSTAT0

MDSTAT1

MDSTAT2

MDSTAT3

MDSTAT4

MDSTAT5

Description

Reserved

Module Status Register 0 (Never Gated)

Module Status Register 1 (SmartReflex)

Module Status Register 2 (DDR3 EMIF)

Module Status Register 3 (EMAC)

Module Status Register 4 (VCP2_0)

Module Status Register 5 (Debug Subsystem and Tracers)

0xA14

0xA18

0xA1C

0xA20

0xA24

0xA28

0xA2C

0xA30

0x85C

0x860

0x864 - 0x9FC

0xA00

0xA04

0xA08

0xA0C

0xA10

0xA34

0xA38

0xA3C

0xA40

0x83C

0x840

0x844

0x848

0x84C

0x850

0x854

0x858

0x81C

0x820

0x824

0x828

0x82C

0x830

0x834

0x838

MDSTAT23

MDSTAT24

Reserved

MDCTL0

MDCTL1

MDCTL2

MDCTL3

MDCTL4

MDCTL5

MDCTL6

MDCTL7

MDCTL8

MDCTL9

MDCTL10

MDCTL11

MDCTL12

MDCTL13

MDCTL14

MDCTL15

MDCTL16

MDSTAT7

MDSTAT8

MDSTAT9

MDSTAT10

MDSTAT11

MDSTAT12

MDSTAT13

MDSTAT14

MDSTAT15

MDSTAT16

MDSTAT17

MDSTAT18

MDSTAT19

MDSTAT20

MDSTAT21

MDSTAT22

Module Status Register 7 (Reserved)

Module Status Register 8 (Reserved)

Module Status Register 9 (Reserved)

Module Status Register 10 (PCIe)

Module Status Register 11 (SRIO)

Module Status Register 12 (HyperLink)

Module Status Register 13 (Reserved)

Module Status Register 14 (MSMC RAM)

Module Status Register 15 (Reserved)

Module Status Register 16 (Reserved)

Module Status Register 17 (Reserved)

Module Status Register 18 (Reserved)

Module Status Register 19 (TCP3d)

Module Status Register 20 (VCP2_1)

Module Status Register 11 (Reserved)

Module Status Register 22(Reserved)

Module Status Register 23(C66x CorePac 0 and Timer 0)

Module Status Register 24(C66x CorePac 1 [C6657 only] and Timer 1)

Reserved

Module Control Register 0 (Never Gated)

Module Control Register 1 (SmartReflex)

Module Control Register 2 (DDR3 EMIF)

Module Control Register 3 (EMAC)

Module Control Register 4 (VCP2_0)

Module Control Register 5 (Debug Subsystem and Tracers)

Module Control Register 6 (Per-core TETB and System TETB)

Module Control Register 7 (Reserved)

Module Control Register 8 (Reserved)

Module Control Register 9 (Reserved)

Module Control Register 10 (PCIe)

Module Control Register 11 (SRIO)

Module Control Register 12 (HyperLink)

Module Control Register 13 (Reserved)

Module Control Register 14 (MSMC RAM)

Module Control Register 15 (Reserved)

Module Control Register 16 (Reserved)

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 118

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-8 PSC Register Memory Map (Part 3 of 3)

Offset

0xA44

0xA48

0xA4C

0xA50

0xA54

0xA58

0xA5C

0xA60

0xA5C - 0xFFC

End of Table 7-8

Register

MDCTL17

MDCTL18

MDCTL19

MDCTL20

MDCTL21

MDCTL22

MDCTL23

MDCTL24

Reserved

1 VCNTLID register is available for debug purpose only.

Description

Module Control Register 17 (Reserved)

Module Control Register 18 (Reserved)

Module Control Register 19 (TCP3d)

Module Control Register 20 (VCP2_1)

Module Control Register 21(Reserved)

Module Control Register 22(Reserved)

Module Control Register 23(C66x CorePac 0 and Timer 0)

Module Control Register 24(C66x CorePac 1 [C6657 only] and Timer 1)

Reserved

www.ti.com

7.4 Reset Controller

The reset controller detects the different type of resets supported on the TMS320C6655/57 device and manages the distribution of those resets throughout the device.

The device has several types of resets:

• Power-on reset

• Hard reset

• Soft reset

• CPU local reset

Table 7-9

explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more

information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data /

Timing’’ on page 124

Table 7-9 Reset Types

Reset Type Initiator

POR (Power on reset) POR pin active low

RESETFULL pin active low

Hard reset

Soft reset

C66x CorePac local reset

RESET pin active low

Emulation

PLLCTL register (RSCTRL)

Watchdog timers

RESET pin active low

PLLCTL register (RSCTRL)

Watchdog timers

Software (through

LPSC MMR)

Watchdog timers

LRESET pin

Effect on Device When Reset Occurs

Resets everything except for test/emu logic and reset isolation modules. Emulator and reset Isolation modules stay alive during this reset. This reset is also different from POR in that the PLLCTL assumes power and clocks are stable when device reset is asserted. Boot configurations are not latched. ROM boot process is initiated.

RESETSTAT Pin Status

Total reset of the chip. Everything on the device is reset to its default state in response to this. Activates the POR signal on chip, which is used to reset test/emu logic. Boot configurations are latched. ROM boot process is initiated.

Toggles RESETSTAT pin

Software can program these initiators to be hard or soft. Hard reset is the default, but can be programmed to be soft reset. Soft reset will behave like hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs, sticky bits in PCIe MMRs, and external memory contents are retained.

Boot configurations are not latched. ROM boot process is initiated.

Toggles RESETSTAT pin

MMR bit in LPSC controls C66x CorePac local reset. Used by watchdog timers (in the event of a timeout) to reset C66x CorePac. Can also be initiated by LRESET device pin. C66x CorePac memory system and slave

DMA port are still alive when C66x CorePac is in local reset. Provides a local reset of the C66x CorePac, without destroying clock alignment or memory contents. Does not initiate ROM boot process.

Does not toggle

RESETSTAT pin

End of Table 7-9

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.4.1 Power-on Reset

Power-on reset is used to reset the entire device, including the test and emulation logic.

Power-on reset is initiated by the following

POR pin

RESETFULL pin

During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device including the reset isolated logic. The assumption is that the device is already powered up and hence, unlike the POR pin, the RESETFULL pin will be driven by the on-board host control instead of the power-good circuitry. For power-on reset, the Main PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller.

The following sequence must be followed during a power-on reset:

Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are power managed, are disabled after a power-on reset and must be enabled through the Device State Control

Registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 66).

Clocks are reset, and they are propagated throughout the device to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.

POR must be held active until all supplies on the board are stable then for at least an additional time for the chip-level PLLs to lock.

The POR pin can now be de-asserted. Reset-sampled pin values are latched at this point. The chip level PLLs are taken out of reset and begin their locking sequence, and all power-on device initialization also begins.

After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, the

DDR3 PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide by settings.

The device is now out of reset and device execution begins as dictated by the selected boot mode.

Note—

To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted

(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the

POR pin.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 120

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.4.2 Hard Reset

A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules.

POR should also remain de-asserted during this time.

Hard reset is initiated by the following:

• RESET pin

• RSCTRL register in PLLCTL

• Watchdog timer

• Emulation

All the above initiators, by default, are configured to act as a hard reset. Except emulation, all the other three initiators can be configured as soft resets in the RSCFG register in PLLCTL.

The following sequence must be followed during a hard reset:

The RESET pin is pulled active low for a minimum of 24 input clock cycles. During this time, the RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.

Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.

After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

Note—

The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.4.3 Soft Reset

A soft reset will behave like a hard reset except that the PCIe MMR sticky bits and DDR3 EMIF MMRs contents are retained. POR should also remain de-asserted during this time.

Soft reset is initiated by the following:

• RESET pin

• RSCTRL register in PLLCTL

• Watchdog timer

All the above initiators by default are configured to act as hard reset. Except emulation, all the other three initiators can be configured as soft resets in the RSCFG register in PLLCTL.

In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.

During a soft reset, the following happens:

The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate through the system. Internal system clocks are not affected. PLLs also remain locked.

After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL controllers pause their system clocks for about 8 cycles.

At this point:

›

The state of the peripherals before the soft reset is not changed.

›

The I/O pins are controlled as dictated by the DEVSTAT register.

›

The DDR3 MMRs and PCIe MMR sticky bits retain their previous values. Only the DDR3 Memory

Controller and PCIe state machines are reset by the soft reset.

›

The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with a system reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 122

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.4.4 Local Reset

The local reset can be used to reset a particular CorePac without resetting any other chip components.

www.ti.com

Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) for KeyStone Devices User

• LRESET pin

• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG register in the PLL controller. See

‘‘Reset Configuration Register (RSTCFG)’’

on page 134 and ‘‘CIC Registers’’ on page 161:

–

Local Reset

–

NMI

–

NMI followed by a time delay and then a local reset for the CorePac selected

–

Hard Reset by requesting reset via PLLCTL

• LPSC MMRs (memory-mapped registers)

7.4.5 Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.

The reset request priorities are as follows (high to low):

• Power-on reset

• Hard/soft reset

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.4.6 Reset Controller Register

The reset controller register is part of the PLLCTL MMRs. All C6655/57 device-specific MMRs are covered in

Section 7.5.3

‘‘Main PLL Control Register’’ on page 135. For more details on these registers and how to program

them, see the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 64.

7.4.7 Reset Electrical Data / Timing

Table 7-10 Reset Timing Requirements

(see Figure 7-4

and

Figure 7-5 )

(1)

No.

1 tw(RESETFULL)

2 tw(RESET)

End of Table 7-10

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

RESETFULL Pin Reset

Pulse width - Pulse width RESETFULL low

Soft/Hard-Reset

Pulse width - Pulse width RESET low

Table 7-11 Reset Switching Characteristics Over Recommended Operating Conditions

(see Figure 7-4

and

Figure 7-5 )

(1)

No.

3 td(RESETFULLH-RESETSTATH)

Parameter

RESETFULL Pin Reset

Delay time - RESETSTAT high after RESETFULL high

Soft/Hard Reset

Delay time - RESETSTAT high after RESET high 4 td(RESETH-RESETSTATH)

End of Table 7-11

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Figure 7-4 RESETFULL Reset Timing

POR

RESETFULL

500C

Min

Max

Unit

ns ns

Max Unit

50000C ns

RESET

RESETSTAT

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 124

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-5 Soft/Hard-Reset Timing

POR

RESETFULL

RESET

RESETSTAT

Table 7-12

(See Figure 7-6

)

Boot Configuration Timing Requirements

(1)

No.

1 tsu(GPIOn-RESETFULL)

2 th(RESETFULL-GPIOn)

End of Table 7-12

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Figure 7-6

Setup time - GPIO valid before RESETFULL asserted

Hold time - GPIO valid after RESETFULL asserted

Boot Configuration Timing

POR

RESETFULL

GPIO[15:0]

www.ti.com

Min

12C

Max Unit

ns ns

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.5 Main PLL and PLL Controller

This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User Guide in

The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment, and gating for the system clocks to the device.

Figure 7-7 shows a block diagram of the main PLL and the PLL

controller.

Figure 7-7 Main PLL and PLL Controller

PLLD

PLL xPLLM

CORECLK(N|P)

PLLOUT

BYPASS

PLL Controller

0 1

PLLEN

PLLENSRC

PLLDIV1

PLLDIV2

PLLDIV3

PLLDIV4

PLLDIV5

/64

PLLDIV6

PLLDIV7

PLLDIV8

/12

PLLDIV9

PLLDIV10

PLLDIV11

SYSCLK1

C66x

CorePac

SYSCLK2

SYSCLK3

SYSCLK4

SYSCLK5

SYSCLK6

SYSCLK7

To Switch Fabric,

Peripherals,

Accelerators

SYSCLK8

SYSCLK9

SYSCLK10

SYSCLK11

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 126

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Note—

NOTE: PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the chip level MAINPLLCTL0 register. The complete 13-bit value is latched when the GO operation is initiated in the PLL controller. Only PLLDIV2, PLLDIV5, and PLLDIV8 are programmable on the C6655/57 device. See the Phase Locked Loop (PLL) for KeyStone Devices User

Guide in

the PLL controller.

The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the PLL Controller. The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter

circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related

Documentation from Texas Instruments’’ on page 64 for detailed recommendations. For the best performance, TI

recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see

Section 7.5.5

‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’ .

CAUTION—

The PLL controller module as described in the see the Phase Locked Loop (PLL) for KeyStone

Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 includes a superset of

features, some of which are not supported on the TMS320C6655/57 device. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

7.5.1 Main PLL Controller Device-Specific Information

7.5.1.1 Internal Clocks and Maximum Operating Frequencies

The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the

DDR3) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The Main

PLL’s PLL controller has several SYSCLK outputs that are listed below, along with the clock description. Each

SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.

•

SYSCLK1:

Full-rate clock for the CorePacs.

•

SYSCLK2:

1/x-rate clock for CorePac emulation. The default rate for this is 1/3. It is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.

•

SYSCLK3:

1/2-rate clock used to clock the MSMC, HyperLink, and DDR EMIF.

•

SYSCLK4:

1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs use this as well.

•

SYSCLK5:

1/y-rate clock for the system trace module only. The default rate for this is 1/5. It is configurable and the max configurable clock is 210 MHz and min configurable clock is 32 MHz. The SYSCLK5 can be turned off by software.

•

SYSCLK6:

1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT-compensated buffers for DDR3

EMIF.

•

SYSCLK7:

1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

•

SYSCLK8:

1/z-rate clock. This clock is used as slow_sysclk in the system. Default is 1/64. It is programmable from /24 to /80.

•

SYSCLK9:

1/12-rate clock for SmartReflex.

•

SYSCLK10:

1/3-rate clock for SRIO only.

•

SYSCLK11:

1/6-rate clock for PSC only.

Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on theTMS320C6655/57 device.

Note—

In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8

(SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the system.

7.5.1.2 Main PLL Controller Operating Modes

The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by BYPASS bit of the PLL Secondary Control Register (SECCTL). In PLL mode, SYSCLK1 is generated from the PLL output using the values set in PLLM and PLLD bit fields in the MAINPLLCTL0 Register. In bypass mode, PLL input is fed directly out as SYSCLK1.

All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed.

7.5.1.3 Main PLL Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup. The PLL should not be operated until this stabilization time has elapsed.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the

PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value, see

Table 7-13

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with

PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main PLL lock time is given in

Table 7-13

Table 7-13 Main PLL Stabilization, Lock, and Reset Times

PLL stabilization time

PLL lock time

PLL reset time

End of Table 7-13

1 PLLD is the value in PLLD bit fields of MAINPLLCTL0 register

2 C = SYSCLK1(N|P) cycle time in ns.

Min

100

1000

Typ Max Unit

μs

500 ×(PLLD

(1)

+1) × C

(2) ns

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 128

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.5.2 PLL Controller Memory Map

The memory map of the PLL controller is shown in Table 7-14 . TMS320C6655/57-specific PLL Controller register definitions can be found in the sections following Table 7-14 . For other registers in the table, see the Phase Locked

Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

CAUTION—

Note that only registers documented here are accessible on the TMS320C6655/57. Other addresses in the PLL controller memory map including the reserved registers should not be modified.

Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to make any changes to the valid bits in the register.

Table 7-14 PLL Controller Registers (Including Reset Controller) (Part 1 of 2)

Hex Address Range

0231 0000 - 0231 00E3

0231 00E4

0231 00E8

0231 00EC

0231 00F0

0231 00F0 - 0231 00FF

0231 0100

0231 0104

0231 0108

0231 010C

0231 0110

0231 0114

0231 0118

0231 011C

0231 0120

0231 0124

0231 0128

0231 012C - 0231 0134

0231 0138

0231 013C

0231 0140

0231 0144

0231 0148

0231 014C

0231 0150

0231 0154 - 0231 015C

0231 0160

0231 0164

0231 0168

0231 016C

0231 0170

CKSTAT

SYSTAT

PLLDIV4

PLLDIV5

PLLDIV6

PLLDIV7

PLLDIV8

PLLCMD

PLLSTAT

ALNCTL

DCHANGE

CKEN

SECCTL

PLLM

PLLDIV1

PLLDIV2

PLLDIV3

Field

RSTYPE

RSTCTRL

RSTCFG

RSISO

PLLCTL

Register Name

Reserved

Reset Type Status Register (Reset Controller)

Software Reset Control Register (Reset Controller)

Reset Configuration Register (Reset Controller)

Reset Isolation Register (Reset Controller)

Reserved

PLL Control Register

Reserved

PLL Secondary Control Register

Reserved

PLL Multiplier Control Register

Reserved

PLL Controller Divider 2 Register

Reserved

PLL Controller Command Register

PLL Controller Status Register

PLL Controller Clock Align Control Register

PLLDIV Ratio Change Status Register

Reserved

SYSCLK Status Register

Reserved

PLL Controller Divider 5 Register

Reserved

PLL Controller Divider 8 Register

Submit Documentation Feedback

www.ti.com

Table 7-14 PLL Controller Registers (Including Reset Controller) (Part 2 of 2)

Hex Address Range

0231 0174 - 0231 0193

0231 0194 - 0231 01FF

End of Table 7-14

Field

PLLDIV9 - PLLDIV16

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Register Name

Reserved

7.5.2.1 PLL Secondary Control Register (SECCTL)

The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in

Figure 7-8 and described in Table 7-15 .

Figure 7-8 PLL Secondary Control Register (SECCTL))

Reserved

R-0000 0000

Legend: R/W = Read/Write; R = Read only; -n = value after reset

24 23

BYPASS

RW-0

OUTPUT_DIVIDE

RW-0001

19 18

Reserved

RW-001 0000 0000 0000 0000

Table 7-15 PLL Secondary Control Register (SECCTL) Field Descriptions

Bit Field

31-24 Reserved

23 BYPASS

22-19 OUTPUT_DIVIDE

18-0 Reserved

End of Table 7-15

Description

Reserved

Main PLL Bypass Enable.

0 = Main PLL Bypass disabled.

1 = Main PLL Bypass enabled.

Output Divider ratio bits.

0h = ÷1. Divide frequency by 1.

1h = ÷2. Divide frequency by 2.

2h - Fh = Reserved.

Reserved

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 130

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)

The PLL Controller Divider Registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in

Figure 7-9

and described

in Table 7-16

. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different

and mentioned in the footnote of Figure 7-9

Figure 7-9 PLL Controller Divider Register (PLLDIVn)

31 16

Reserved

R-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset

1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8

2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8

(1)

R/W-1

Reserved

R-0

8 7

RATIO

R/W-n

(2)

Table 7-16 PLL Controller Divider Register (PLLDIVn) Field Descriptions

Bit Field Description

31-16 Reserved Reserved.

15 DnEN Divider

Figure 7-9

)

0 = Divider n is disabled.

1 = No clock output. Divider n is enabled.

7-0 RATIO Divider ratio bits. (see footnote of

Figure 7-9

)

0h = ÷1. Divide frequency by 1.

1h = ÷2. Divide frequency by 2.

2h = ÷3. Divide frequency by 3.

3h = ÷4. Divide frequency by 4.

4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.

End of Table 7-16

7.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)

The PLL controller clock align control register (ALNCTL) is shown in

Figure 7-10 and described in Table 7-17 .

Figure 7-10 PLL Controller Clock Align Control Register (ALNCTL)

Reserved

R-0

8 7

ALN8

R/W-1

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

Reserved

R-0

ALN5

R/W-1

Reserved

R-0

ALN2

R/W-1

Reserved

R-0

Table 7-17

Bit

31-8

6-5

3-2

Field

ALN8

ALN5

ALN2

PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Reserved

Description

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYSCLKn alignment. Do not change the default values of these fields.

0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.

The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.

End of Table 7-17

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)

When a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE Status

Register. During the GO operation, the PLL controller will change only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also needs to be aligned to other clocks.

The PLLDIV divider ratio change status register is shown in

Figure 7-11 and described in Table 7-18 .

Figure 7-11 PLLDIV Divider Ratio Change Status Register (DCHANGE)

Reserved

R-0

8 7

SYS8

R/W-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

Reserved

R-0

SYS5

R/W-0

Reserved

R-0

SYS2

R/W-0

Reserved

R-0

Table 7-18 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Description Bit

31-8

6-5

3-2

Field

Reserved

SYS8

SYS5

SYS2

End of Table 7-18

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Identifies when the SYSCLKn divide ratio has been modified.

0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.

1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.

7.5.2.5 SYSCLK Status Register (SYSTAT)

The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in

Figure 7-12 and described in Table 7-19 .

Figure 7-12

SYSCLK

Status Register (SYSTAT)

Reserved

R-n

11 10 9 8 7 6 5 4 3 2 1 0

SYS11ON SYS10ON SYS9ON SYS8ON SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON

R-1 R-1 R-1 R-1

Legend: R/W = Read/Write; R = Read only; -n = value after reset

R-1 R-1 R-1 R-1 R-1 R-1 R-1

Table 7-19 SYSCLK Status Register (SYSTAT) Field Descriptions

Bit Field Description

31-11 Reserved Reserved. reserved bit location is always read as 0. A value written to this field has no effect.

10-0 SYS[N

(1)

]ON SYSCLK[N] on status.

0 = SYSCLK[N] is gated.

1 = SYSCLK[N] is on.

End of Table 7-19

1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 132

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.5.2.6 Reset Type Status Register (RSTYPE)

The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in

Figure 7-13

and described in

Table 7-20 .

Figure 7-13 Reset Type Status Register (RSTYPE)

Reserved

29 28

EMU-RST

Reserved

R-0 R-0

Legend: R = Read only; -n = value after reset

R-0

12 11

WDRST[N]

R-0

8 7

Reserved

R-0

PLLCTRLRST

R-0

RESET

R-0

POR

R-0

Table 7-20

Bit Field

31-29 Reserved

28 EMU-RST

Reset Type Status Register (RSTYPE) Field Descriptions

27-12 Reserved

WDRST3

WDRST2

WDRST1

WDRST0

7-3

Reserved

PLLCTLRST

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by emulation.

0 = Not the last reset to occur.

1 = The last reset to occur.

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by watchdog timer[N].

0 = Not the last reset to occur.

1 = The last reset to occur.

RESET

POR

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by PLLCTL.

0 = Not the last reset to occur.

1 = The last reset to occur.

RESET reset.

0 = RESET was not the last reset to occur.

1 = RESET was the last reset to occur.

Power-on reset.

0 = Power-on reset was not the last reset to occur.

1 = Power-on reset was the last reset to occur.

End of Table 7-20

7.5.2.7 Reset Control Register (RSTCTRL)

This register contains a key that enables writes to the MSB of this register and the RSTCFG Register. The key value is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register

(RSTCTRL) is shown in Figure 7-14

and described in

Table 7-21

Figure 7-14 Reset Control Register (RSTCTRL)

Reserved

R-0x0000

Legend: R = Read only; -n = value after reset;

1 Writes are conditional based on valid key.

17 16

SWRST

R/W-0x

(1)

KEY

R/W-0x0003

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-21

Bit Field

31-17 Reserved

16 SWRST

Reset Control Register (RSTCTRL) Field Descriptions

15-0 KEY

End of Table 7-21

Description

Reserved.

Software reset

0 = Reset

1 = Not reset

Key used to enable writes to RSTCTRL and RSTCFG.

7.5.2.8 Reset Configuration Register (RSTCFG)

This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL controller’s

RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets will be hard resets. The Reset

Configuration Register (RSTCFG) is shown in

Figure 7-15 and described in Table 7-22 .

Figure 7-15 Reset Configuration Register (RSTCFG)

Reserved

R-0

14 13

PLLCTLRSTTYPE

R/W-0

(2)

RESETTYPE

R/W-0

Reserved

R-0

Legend: R = Read only; R/W = Read/Write; -n = value after reset

1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)

2 Writes are conditional based on valid key. For details, see Section 7.5.2.7

‘‘Reset Control Register (RSTCTRL)’’

WDTYPE[N

(1)

]

R/W-0

Table 7-22 Reset Configuration Register (RSTCFG) Field Descriptions

Bit Field

31-14 Reserved

Description

Reserved.

PLLCTLRSTTYPE PLL controller initiates a software-driven reset of type:

0 = Hard reset (default)

1 = Soft reset

RESETTYPE

Reserved

RESET initiates a reset of type:

0 = Hard Reset (default)

1 = Soft Reset

Reserved. 11-4

WDTYPE3

WDTYPE2

WDTYPE1

0 WDTYPE0

End of Table 7-22

Watchdog timer [N] initiates a reset of type:

0 = Hard Reset (default)

1 = Soft Reset

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 134

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.5.2.9 Reset Isolation Register (RSISO)

This register is used to select the module clocks that must maintain their clocking without pausing through non power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting module specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in PSC to reset-isolate a particular module. For more

information on MDCTLx Register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related

Documentation from Texas Instruments’’ on page 64. The Reset Isolation Register (RSTCTRL) is shown below.

Figure 7-16 Reset Isolation Register (RSISO)

Reserved

R-0

Legend: R = Read only; R/W = Read/Write; -n = value after reset

10 9

SRIOISO

R/W-0

SRISO

R/W-0

Reserved

R-0

Table 7-23

Bit Field

31-10 Reserved

9 SRIOISO

8 SRISO

Reset Isolation Register (RSISO) Field Descriptions

7-0 Reserved

End of Table 7-23

Description

Reserved.

Isolate SRIO module

0 = Not reset isolated

1 = Reset Isolated

Isolate SmartReflex

0 = Not reset isolated

1 = Reset Isolated

Reserved.

Note—

The boot ROM code will enable the reset isolation for both SRIO and SmartReflex modules during boot with the Reset Isolation Register. It is up to the user application to disable.

7.5.3 Main PLL Control Register

The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL controller for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using KICK0/KICK1 registers. For valid configurable values into the

MAINPLLCTL0 and MAINPLLCTL1 Registers, see Section 2.5.3

‘‘PLL Boot Configuration Settings’’ on page 32.

See section 3.3.4

‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 71 for the address location of the

registers and locking and unlocking sequences for accessing the registers. The registers are reset on POR only.

Figure 7-17 Main PLL Control Register 0 (MAINPLLCTL0)

31 24 23

BWADJ[7:0]

RW-0000 0101

Legend: RW = Read/Write; -n = value after reset

Reserved

RW-0000 0

19 18

PLLM[12:6]

RW-0000000

12 11

Reserved

RW-000000

5 0

PLLD

RW-000000

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-24 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions

Bit Field

31-24 BWADJ[7:0]

23-19 Reserved

18-12 PLLM[12:6]

11-6 Reserved

5-0 PLLD

End of Table 7-24

Description

BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd values. Example: PLLM=15, then BWADJ=7

Reserved

A 13-bit bus that selects the values for the multiplication factor (see Note below)

Reserved

A 6-bit bus that selects the values for the reference divider

Figure 7-18 Main PLL Control Register 1 (MAINPLLCTL1)

Reserved

RW-0000000000000000000000000

Legend: RW = Read/Write; -n = value after reset

7 6

ENSAT

RW-0

Reserved

RW-00

BWADJ[11:8]

RW-0000

Table 7-25

Bit

31-7

5-4

3-0

Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions

Field

Reserved

ENSAT

Reserved

BWADJ[11:8]

Description

Reserved

Needs to be set to 1 for proper operation of PLL

Reserved

End of Table 7-25

Note—

PLLM[5:0] bits of the multiplier are controlled by the PLLM Register inside the PLL controller and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The MAINPLLCTL0

Register PLLM[12:6] bits should be written just before writing to the PLLM Register PLLM[5:0] bits in the controller to have the complete 13-bit value latched when the GO operation is initiated in the PLL

controller. See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 for the recommended programming sequence. Output divide ratio and

bypass enable/disable of the Main PLL is controlled by the SECCTL Register in the PLL Controller. See the

7.5.2.1

‘‘PLL Secondary Control Register (SECCTL)’’ for more details.

7.5.4 Main PLL and PLL Controller Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 64 for details on the initialization sequence for Main PLL and PLL Controller.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 136

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.5.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing www.ti.com

Table 7-26 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 1 of 2)

(see Figure 7-19 and Figure 7-20 )

No.

Min Max Unit

CORECLK[P:N]

tc(CORCLKN) tc(CORECLKP) tw(CORECLKN) tw(CORECLKN)

Cycle time _ CORECLKN cycle time

Cycle time _ CORECLKP cycle time

Pulse width _ CORECLKN high

Pulse width _ CORECLKN low tw(CORECLKP) tw(CORECLKP)

Pulse width _ CORECLKP high

Pulse width _ CORECLKP low tr(CORECLKN_250mv) Transition time _ CORECLKN rise time (250 mV) tf(CORECLKN_250mv) Transition time _ CORECLKN fall time (250 mV) tr(CORECLKP_250mv) tf(CORECLKP_250mv) tj(CORECLKN) tj(CORECLKP)

Transition time _ CORECLKP rise time (250 mV)

Transition time _ CORECLKP fall time (250 mV)

Jitter, peak_to_peak _ periodic CORECLKN

Jitter, peak_to_peak _ periodic CORECLKP tc(SRIOSMGMIICLKN) tc(SRIOSMGMIICLKP)

SRIOSGMIICLK[P:N]

Cycle time _ SRIOSMGMIICLKN cycle time

Cycle time _ SRIOSMGMIICLKP cycle time tw(SRIOSMGMIICLKN) Pulse width _ SRIOSMGMIICLKN high tw(SRIOSMGMIICLKN) Pulse width _ SRIOSMGMIICLKN low tw(SRIOSMGMIICLKP) Pulse width _ SRIOSMGMIICLKP high tw(SRIOSMGMIICLKP) tr(SRIOSMGMIICLKN_25

0mv)

Pulse width _ SRIOSMGMIICLKP low

Transition time _ SRIOSMGMIICLKN rise time (250 mV)

Transition time _ SRIOSMGMIICLKN fall time (250 mV) tf(SRIOSMGMIICLKN_25

0mv) tr(SRIOSMGMIICLKP_25

0mv) tf(SRIOSMGMIICLKP_25

0mv) tj(SRIOSMGMIICLKN) tj(SRIOSMGMIICLKP) tj(SRIOSMGMIICLKN) tj(SRIOSMGMIICLKP)

Transition time _ SRIOSMGMIICLKP rise time (250 mV)

Transition time _ SRIOSMGMIICLKP fall time (250 mV)

Jitter, peak_to_peak _ periodic SRIOSMGMIICLKN

Jitter, peak_to_peak _ periodic SRIOSMGMIICLKP

Jitter, peak_to_peak _ periodic SRIOSMGMIICLKN (SRIO not used)

Jitter, peak_to_peak _ periodic SRIOSMGMIICLKP (SRIO not used)

3.2

0.45*tc(CORECLKN)

0.45*tc(CORECLKP)

0.55*tc(CORECLKN)

0.55*tc(CORECLKP)

350

100

3.2

6.4

0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)

0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)

350

350 ns ns ns ns ns ns ps ps ps ps

4 ps,RMS

8 ps,RMS

8 ps,RMS ns ns ps ps ns ns ns ns ps ps ps ps

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-26 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 2 of 2)

(see Figure 7-19 and Figure 7-20 )

No.

Min Max Unit

tc(MCMCLKN) tc(MCMCLKP) tw(MCMCLKN) tw(MCMCLKN) tw(MCMCLKP) tw(MCMCLKP) tr(MCMCLKN_250mv) tf(MCMCLKN_250mv) tr(MCMCLKP_250mv) tf(MCMCLKP_250mv) tj(MCMCLKN) tj(MCMCLKP)

1 tc(PCIECLKN) tc(PCIECLKP) tw(PCIECLKN) tw(PCIECLKN) tw(PCIECLKP) tw(PCIECLKP) tr(PCIECLKN_250mv) tf(PCIECLKN_250mv)

4 tr(PCIECLKP_250mv) tf(PCIECLKP_250mv)

5 tj(PCIECLKN)

5 tj(PCIECLKP)

End of Table 7-26

HyperLinkCLK[P:N]

Cycle time _ MCMCLKN cycle time

Cycle time _ MCMCLKP cycle time

Pulse width _ MCMCLKN high

Pulse width _ MCMCLKN low

Pulse width _ MCMCLKP high

Pulse width _ MCMCLKP low

Transition time _ MCMCLKN rise time (250mV)

Transition time _ MCMCLKN fall time (250mV)

Transition time _ MCMCLKP rise time (250mV)

Transition time _ MCMCLKP fall time (250mV)

Jitter, peak_to_peak _ periodic MCMCLKN

Jitter, peak_to_peak _ periodic MCMCLKP

PCIECLK[P:N]

Cycle time _ PCIECLKN cycle time

Cycle time _ PCIECLKP cycle time

Pulse width _ PCIECLKN high

Pulse width _ PCIECLKN low

Pulse width _ PCIECLKP high

Pulse width _ PCIECLKP low

Transition time _ PCIECLKN rise time (250 mV)

Transition time _ PCIECLKN fall time (250 mV)

Transition time _ PCIECLKP rise time (250 mV)

Transition time _ PCIECLKP fall time (250 mV)

Jitter, peak_to_peak _ periodic PCIECLKN

Jitter, peak_to_peak _ periodic PCIECLKP

3.2

0.45*tc(MCMCLKN)

0.45*tc(MCMCLKP)

3.2

0.45*tc(PCIECLKN)

0.45*tc(PCIECLKP)

6.4

0.55*tc(MCMCLKN)

0.55*tc(MCMCLKP)

350

350 ps ps

4 ps,RMS

4 ps,RMS ns ns ps ps ns ns ns ns

0.55*tc(PCIECLKN)

0.55*tc(PCIECLKP)

350

350 ps ps

4 ps,RMS

4 ps,RMS ns ns ps ps ns ns ns ns

Figure 7-19 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing

<CLK_NAME>CLKN

<CLK_NAME>CLKP

Figure 7-20 Main PLL Clock Input Transition Time

5 peak-to-peak differential input voltage (250 mV to 2 V)

Submit Documentation Feedback

250 mV peak-to-peak

T = 50 ps min to 350 ps max (10% to 90 %)

R for the 250 mV peak-to-peak centered at zero crossing

Peripheral Information and Electrical Specifications 138

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.6 DD3 PLL

The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, the DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.

DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter

circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related

Documentation from Texas Instruments’’ on page 64. For the best performance, TI recommends that all the PLL

external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

Figure 7-21

shows the DDR3 PLL.

Figure 7-21 DDR3 PLL Block Diagram

PLLD

DDR3 PLL xPLLM

DDRCLK(N|P)

PLLOUT

DDR3

PHY

BYPASS

7.6.1 DDR3 PLL Control Register

The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. The DDR3 PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 Registers located in the Bootcfg module. These

MMRs exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence

using the KICK0/KICK1 registers. For suggested configurable values, see section 3.3.4

‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 71 for the address location of the registers and locking and unlocking sequences for

accessing the registers. This register is reset on POR only.

Figure 7-22 DDR3 PLL Control Register 0 (DDR3PLLCTL0)

(1)

BWADJ[7:0]

RW,+0000 1001

24 23

BYPASS

RW,+0

22 19

Reserved

RW,+0001

PLLM

RW,+0000000010011

6 5

PLLD

RW,+000000

Legend: RW = Read/Write; -n = value after reset

1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.

Table 7-27

Bit Field

31-24 BWADJ[7:0]

23 BYPASS

DDR3 PLL Control Register 0 Field Descriptions (Part 1 of 2)

22-19 Reserved

Description

BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of

PLLM[12:0] if PLLM has odd values. Example: PLLM=15, then BWADJ=7

Enable bypass mode

0 = Bypass disabled

1 = Bypass enabled

Reserved

Submit Documentation Feedback

www.ti.com

Table 7-27

Bit

18-6

Field

PLLM

5-0 PLLD

End of Table 7-27

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

DDR3 PLL Control Register 0 Field Descriptions (Part 2 of 2)

Description

A 13-bit bus that selects the values for the multiplication factor

A 6-bit bus that selects the values for the reference divider

Figure 7-23 DDR3 PLL Control Register 1 (DDR3PLLCTL1)

12 31 14

Reserved

RW-000000000000000000

Legend: RW = Read/Write; -n = value after reset

PLLRST

RW-0

Reserved

RW-000000

7 6

ENSAT

RW-0

Reserved

R-0

BWADJ[11:8]

RW-0000

Table 7-28

Bit Field

31-14 Reserved

13 PLLRST

12-7

5-4

3-0

DDR3 PLL Control Register 1 Field Descriptions

Reserved

ENSAT

Reserved

BWADJ[11:8]

Description

Reserved

PLL reset bit.

0 = PLL reset is released.

1 = PLL reset is asserted.

Reserved

Needs to be set to 1 for proper operation of the PLL

Reserved

End of Table 7-28

7.6.2 DDR3 PLL Device-Specific Information

As shown in Figure 7-21

, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3

PLL are affected as described in Section 7.4

‘‘Reset Controller’’ on page 119. The DDR3 PLL is unlocked only

during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

7.6.3 DDR3 PLL Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 64 for details on the initialization sequence for DDR3 PLL.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 140

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.6.4 DDR3 PLL Input Clock Electrical Data/Timing

Table 7-29 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements

(see Figure 7-24

and Figure 7-20 )

No.

DDRCLK[P:N]

1 tc(DDRCLKN) tc(DDRCLKP) tw(DDRCLKN) tw(DDRCLKN) tw(DDRCLKP) tw(DDRCLKP) tr(DDRCLKN_250mv) tf(DDRCLKN_250mv)

Cycle time _ DDRCLKN cycle time

Cycle time _ DDRCLKP cycle time

Pulse width _ DDRCLKN high

Pulse width _ DDRCLKN low

Pulse width _ DDRCLKP high

Pulse width _ DDRCLKP low

Transition time _ DDRCLKN rise time (250 mV)

Transition time _ DDRCLKN fall time (250 mV)

5 tr(DDRCLKP_250mv) Transition time _ DDRCLKP rise time (250 mV) tf(DDRCLKP_250mv) Transition time _ DDRCLKP fall time (250 mV) tj(DDRCLKN) tj(DDRCLKP)

End of Table 7-29

Jitter, peak_to_peak _ periodic DDRCLKN

Jitter, peak_to_peak _ periodic DDRCLKP

Figure 7-24 DDR3 PLL DDRCLK Timing

DDRCLKN

DDRCLKP

www.ti.com

Min Max Unit

3.2

0.45*tc(DDRCLKN)

0.45*tc(DDRCLKP)

0.55*tc(DDRCLKN)

0.55*tc(DDRCLKP)

350

0.025*tc(DDRCLKN)

0.025*tc(DDRCLKP) ns ns ps ps ns ns ns ns ps ps ps ps

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.7 Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device CPU.

There is one EDMA Channel Controller on the C6655/57 device: EDMA3_CC. It has four transfer controllers: TC0,

TC1, TC2, and TC3. In the context of this document, TCx associated with CC is referred to as EDMA3_CC_TCx.

Each of the transfer controllers has a direct connection to the switch fabric. Section 4.2 ‘‘Switch Fabric Connections

Matrix’’ lists the peripherals that can be accessed by the transfer controllers.

The EDMA3 Channel Controller includes the following features:

• Fully orthogonal transfer description

–

Three transfer dimensions:

›

Array (multiple bytes)

›

Frame (multiple arrays)

›

Block (multiple frames)

–

Single event can trigger transfer of array, frame, or entire block

–

Independent indexes on source and destination

• Flexible transfer definition:

–

Increment or FIFO transfer addressing modes

–

Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention

–

Chaining allows multiple transfers to execute with one event

• 512 PaRAM entries

–

Used to define transfer context for channels

–

Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry

• 64 DMA channels

–

Manually triggered (CPU writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another)

• Eight Quick DMA (QDMA) channels

–

Used for software-driven transfers

–

Triggered upon writing to a single PaRAM set entry

• Four transfer controllers and four event queues with programmable system-level priority

• Interrupt generation for transfer completion and error conditions

• Debug visibility

–

Queue watermarking/threshold allows detection of maximum usage of event queues

–

Error and status recording to facilitate debug

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 142

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.7.1 EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases. For most applications, increment mode must be used.

On the C6655/57, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder

Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not supported by any other peripheral or internal memory in the device. Note that increment mode is supported by all peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct

Memory Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

For the range of memory addresses that include EDMA3 channel controller (EDMA3_CC) control registers and

EDMA3 transfer controller (TC) control register, see Section Table 2-2 ‘‘Memory Map Summary’’ on page 20. For

memory offsets and other details on EDMA3_CC and TC control registers entries, see the Enhanced Direct Memory

Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

7.7.2 EDMA3 Channel Controller Configuration

Table 7-30

provides the configuration of the EDMA3 channel controller present on the device.

Table 7-30 EDMA3 Channel Controller Configuration

Description

Number of DMA channels in Channel Controller

Number of QDMA channels

Number of interrupt channels

Number of PaRAM set entries

Number of event queues

Number of Transfer Controllers

Memory Protection Existence

Number of Memory Protection and Shadow Regions 8

End of Table 7-30

512

Yes

EDMA3 CC

7.7.3 EDMA3 Transfer Controller Configuration

Each transfer controller on a device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), and so on. The parameters that determine the transfer controller configurations are:

•

FIFOSIZE:

Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data.

The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.

•

BUSWIDTH:

The width of the read and write data buses, in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface.

•

Default Burst Size (DBS):

The DBS is the maximum number of bytes per read/write command issued by a transfer controller.

•

DSTREGDEPTH:

This determines the number of destination FIFO register set. The number of destination

FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.

All four parameters listed above are specified by the design of the device.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-31

provides the configuration of the EDMA3 transfer controller present on the device.

Table 7-31 EDMA3 Transfer Controller Configuration

Parameter

FIFOSIZE

TC0 TC1

EDMA3 CC

TC2 TC3

1024 bytes 512 bytes 512 bytes 1024 bytes

BUSWIDTH 16 bytes

DSTREGDEPTH 4 entries

DBS 64 bytes

End of Table 7-31

16 bytes

4 entries

64 bytes

16 bytes

4 entries

64 bytes

16 bytes

4 entries

64 bytes

7.7.4 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels for EDMA3_CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables lists the source of the synchronization event associated with each of the

EDMA3_CC DMA channels. On the C6655/57, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone

Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

Table 7-32 EDMA3_CC Events for C6655/57 (Part 1 of 2)

Event Number

UTXEVT_B

SPIINT0

SPIINT1

SEMINT0

SEMINT1

SEMINT2

SEMINT3

TINT4L

TINT4H

Event

TCP3D_AREVT0

TCP3D_AREVT1

TINT2L

TINT2H

URXEVT

UTXEVT

GPINT0

GPINT1

GPINT2

GPINT3

VCPAREVT

VCPAXEVT

VCPBREVT

VCPBXEVT

URXEVT_B

Event Description

TCP3D_A receive event0

TCP3D_A receive event1

Timer2 interrupt low

Timer2 interrupt high

UART0 receive event

UART0 transmit event

GPIO interrupt

GPIO Interrupt

GPIO interrupt

VCP2_0 receive event

VCP2_0 transmit event

VCP2_1 receive event

VCP2_1 transmit event

UART1 receive event

UART1 transmit event

SPI interrupt

Semaphore interrupt

Timer4 interrupt low

Timer4 interrupt high

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 144

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-32 EDMA3_CC Events for C6655/57 (Part 2 of 2)

Event Number

End of Table 7-32

MCBSP1_REVT

MCBSP1_XEVT

TETBHFULLINT

TETBHFULLINT0

TETBHFULLINT1

CIC1_OUT0

CIC1_OUT1

CIC1_OUT2

CIC1_OUT3

CIC1_OUT4

CIC1_OUT5

CIC1_OUT6

CIC1_OUT7

CIC1_OUT8

CIC1_OUT9

CIC1_OUT10

Event

TINT5L

TINT5H

TINT6L

TINT6H

TINT7L

TINT7H

SPIXEVT

SPIREVT

I2CREVET

I2CXEVT

TINT3L

TINT3H

MCBSP0_REVT

MCBSP0_XEVT

CIC1_OUT11

CIC1_OUT12

CIC1_OUT13

CIC1_OUT14

CIC1_OUT15

CIC1_OUT16

CIC1_OUT17

TETBFULLINT

TETBFULLINT0

TETBFULLINT1

Event Description

Timer5 interrupt low

Timer5 interrupt high

Timer6 interrupt low

Timer6 interrupt high

Timer7 interrupt low

Timer7 interrupt high

SPI transmit event

SPI receive event

I2C receive event

I2C transmit event

Timer3 interrupt low

Timer3 interrupt high

McBSP_0 receive event

McBSP_0 transmit event

McBSP_1 receive event

McBSP_1 transmit event

TETB half full interrupt

Interrupt Controller output

TETB full interrupt

145 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

www.ti.com

7.8 Interrupts

7.8.1 Interrupt Sources and Interrupt Controller

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

The CPU interrupts on the C6655/57 device are configured through the C66x CorePac Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs

(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events.

Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. In addition, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through CIC blocks, CIC[2:0]. This is clocked using CPU/6.

The event controllers consist of simple combination logic to provide additional events to the C66x CorePacs, plus the EDMA3_CC and CIC0 provide 12 additional events as well as 8 broadcast events to the C66x CorePacs. CIC1 provides 18 additional events to EDMA3_CC, and CIC2 provides 32 additional events to HyperLink.

There are a large number of events on the chip level. The chip level CIC provides a flexible way to combine and remap those events. Multiple events can be combined to a single event through chip level CIC. However, an event can be mapped only to a single event output from the chip level CIC. The chip level CIC also allows the software to trigger system events through memory writes. The broadcast events to C66x CorePacs can be used for synchronization among multiple cores, inter-processor communication purposes, etc. For more details on the CIC

features, please refer to the Chip Interrupt Controller (CIC) for KeyStone Devices User Guide in ‘‘Related

CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

Note—

Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and an EOI handshaking interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 146

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-25

shows the C6655/57 interrupt topology.

Figure 7-25 TMS320C6655/57 Interrupt Topology

26 Reserved Secondary Events

100 Core-only Secondary Events

82 Common Events

21 Reserved Secondary Events

57 EDMA3_CC-only

Secondary Events

12 Reserved Secondary Events

68 Events

CIC0

CIC1

CIC2

16 Reserved Secondary Events

106 Primary Events

12 Secondary Events

2 Reserved Primary Events

Core0

106 Primary Events

12 Secondary Events

2 Reserved Primary Events

8 Broadcast Events from CIC0

Core1

(C6657 only)

11 Reserved Secondary Events

46 Primary Events

18 Secondary Events

EDMA3

8 Reserved Secondary Events

32 Queue Events

32 Secondary Events

HyperLink

www.ti.com

Table 7-33

shows the mapping of system events. For more information on the Interrupt Controller, see the C66x

Table 7-33 TMS320C6655/57 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)

Event Number

Interrupt Event

EVT0

EVT1

EVT2

EVT3

TETBHFULLINTn

(1)

TETBFULLINTn

TETBUNFLINTn

EMU_DTDMA

MSMC_mpf_errorn

(2)

EMU_RTDXRX

EMU_RTDXTX

IDMA0

IDMA1

SEMERRn

(3)

Description

Event combiner 0 output

Event combiner 1 output

Event combiner 2 output

Event combiner 3 output

TETB is half full

TETB is full

Acquisition has been completed

Overflow condition interrupt

Underflow condition interrupt

ECM interrupt for:

1. Host scan access

2. DTDMA transfer complete

3. AET interrupt

Memory protection fault indicators for local core

RTDX receive complete

RTDX transmit complete

IDMA channel 0 interrupt

IDMA channel 1 interrupt

Semaphore error interrupt

Submit Documentation Feedback

www.ti.com

Table 7-33

Event Number

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

TMS320C6655/57 System Event Mapping — C66x CorePac Primary Interrupts (Part 2 of 4)

Interrupt Event

SEMINTn

(3)

PCIExpress_MSI_INTn

(4)

PCIExpress_MSI_INTn+4

(4)

MACINTn

(9)

INTDST(n+16)

(5)

INTDST(n+20)

(6)

CIC0_OUT(0+20*n)

CIC0_OUT(1+20*n)

CIC0_OUT(2+20*n)

CIC0_OUT(3+20*n)

CIC0_OUT(4+20*n)

CIC0_OUT(5+20*n)

CIC0_OUT(6+20*n)

CIC0_OUT(7+20*n)

CIC0_OUT(8+20*n)

CIC0_OUT(9+20*n)

QM_INT_LOW_0

QM_INT_LOW_1

QM_INT_LOW_2

QM_INT_LOW_3

QM_INT_LOW_4

QM_INT_LOW_5

QM_INT_LOW_6

QM_INT_LOW_7

QM_INT_LOW_8

QM_INT_LOW_9

QM_INT_LOW_10

QM_INT_LOW_11

QM_INT_LOW_12

QM_INT_LOW_13

QM_INT_LOW_14

QM_INT_LOW_15

QM_INT_HIGH_n

(7)

QM_INT_HIGH_(n+4)

QM_INT_HIGH_(n+8)

QM_INT_HIGH_(n+12)

QM_INT_HIGH_(n+16)

QM_INT_HIGH_(n+20)

QM_INT_HIGH_(n+24)

QM_INT_HIGH_(n+28)

CIC0_OUT40

CIC0_OUT41

CIC0_OUT42

CIC0_OUT43

Description

Semaphore interrupt

Message signaled interrupt mode

EMAC interrupt

SRIO Interrupt

Interrupt Controller Output

QM Interrupt for 0~31 Queues

QM Interrupt for 32~63 Queues

QM Interrupt for 64~95 Queues

QM Interrupt for 96~127 Queues

QM Interrupt for 128~159 Queues

QM Interrupt for 160~191 Queues

QM Interrupt for 192~223 Queues

QM Interrupt for 224~255 Queues

QM Interrupt for 256~287 Queues

QM Interrupt for 288~319 Queues

QM Interrupt for 320~351 Queues

QM Interrupt for 352~383 Queues

QM Interrupt for 384~415 Queues

QM Interrupt for 416~447 Queues

QM Interrupt for 448~479 Queues

QM Interrupt for 480~511 Queues

QM Interrupt for Queue 704+n

QM Interrupt for Queue 708+n

QM Interrupt for Queue 712+n

QM Interrupt for Queue 716+n

QM Interrupt for Queue 720+n

QM Interrupt for Queue 724+n

QM Interrupt for Queue 728+n

QM Interrupt for Queue 732+n

Interrupt Controller Output

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 148

Event Number

100

101

102

103

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-33 TMS320C6655/57 System Event Mapping — C66x CorePac Primary Interrupts (Part 3 of 4)

Interrupt Event

CIC0_OUT44

CIC0_OUT45

CIC0_OUT46

CIC0_OUT47

TINTLn

(8)

TINTHn

(8)

TINT2L

TINT2H

GPINT6

GPINT7

GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

TINT3L

TINT3H

PCIExpress_MSI_INTn+2

(4)

PCIExpress_MSI_INTn+6

(4)

GPINT2

GPINT3

MACINTn+2

(9)

MACTRESHn+2

MACRXINTn+2

GPINT4

GPINT5

GPINT14

GPINT15

IPC_LOCAL

GPINTn

(10)

MACTXINTn

MACTRESHn

INTERR

EMC_IDMAERR

Reserved

MACRXINTn

(9)

EFIINTA

EFIINTB

QM_INT_HIGH_(n+2)

QM_INT_HIGH_(n+6)

QM Interrupt for Queue 706+n

EMAC interrupt

EFI Interrupt from side A

EFI Interrupt from side B

QM Interrupt for Queue 710+n

QM Interrupt for Queue 714+n

EMAC interrupt

GPIO interrupt

Description

Interrupt Controller Output

Local timer interrupt low

Local timer interrupt high

Timer2 interrupt low

Timer2 interrupt high

Timer3 interrupt low

Timer3 interrupt high

Message signaled interrupt mode

GPIO interrupt

Inter DSP interrupt from IPCGRn

Local GPIO interrupt

Interrupt Controller Output

EMAC interrupt

Dropped CPU interrupt event

Invalid IDMA parameters

149 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 7-33

114

115

116

117

110

111

112

113

Event Number

104

105

106

107

108

109

122

123

124

125

118

119

120

121

126

127

End of Table 7-33

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

TMS320C6655/57 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)

Interrupt Event

QM_INT_HIGH_(n+10)

QM_INT_HIGH_(n+14)

QM_INT_HIGH_(n+18)

QM_INT_HIGH_(n+22)

QM_INT_HIGH_(n+26)

QM_INT_HIGH_(n+30)

MDMAERREVT

Reserved

INTDST(n+18)

(11)

PMC_ED

INTDST(n+22)

(12)

EDMA3_CC_AETEVT

UMC_ED1

UMC_ED2

PDC_INT

SYS_CMPA

PMC_CMPA

PMC_DMPA

DMC_CMPA

DMC_DMPA

UMC_CMPA

UMC_DMPA

EMC_CMPA

EMC_BUSERR

Description

QM Interrupt for Queue 718+n

QM Interrupt for Queue 722+n

QM Interrupt for Queue 726+n

QM Interrupt for Queue 730+n

QM Interrupt for Queue 734+n

details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in ‘‘Related

VbusM error event

SRIO Interrupt

Single bit error detected during DMA read

SRIO Interrupt

EDMA3 CC AET Event

Corrected bit error detected

Uncorrected bit error detected

Power down sleep interrupt

SYS CPU memory protection fault event

PMC CPU memory protection fault event

PMC DMA memory protection fault event

DMC CPU memory protection fault event

DMC DMA memory protection fault event

UMC CPU memory protection fault event

UMC DMA memory protection fault event

EMC CPU memory protection fault event

EMC bus error interrupt

1 Core

Pac

[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn

2 Core

Pac

[n] will receive MSMC_mpf_errorn.

3 Core

Pac

[n] will receive SEMINTn and SEMERRn.

4 Core

Pac

[n] will receive PCIEXpress_MSI_INTn.

5 Core

Pac

[n] will receive INTDST(n+16)

6 Core

Pac

[n] will receive INTDST(n+20)

7 n is core number.

8 Core

Pac

[n] will receive TINTLn and TINTHn.

9 Core

Pac

[n] will receive MACINTn/MACRXINTn/MACTXINTn/MACTRESHn

10 Core

Pac

[n] will receive GPINTn.

11 Core

Pac

[n] will receive INTDST(n+18)

12 Core

Pac

[n] will receive INTDST(n+22)

Table 7-34 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 1 of 6)

Input Event# on CIC

System Interrupt

GPINT16

GPINT17

GPINT18

GPINT19

GPINT20

GPINT21

GPINT22

GPINT23

Description

GPIO interrupt

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 150

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-34 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 6)

Input Event# on CIC

EDMA3_CC_GINT

Reserved

EDMA3_CC_INT0

EDMA3_CC_INT1

EDMA3_CC_INT2

EDMA3_CC_INT3

EDMA3_CC_INT4

EDMA3_CC_INT5

EDMA3_CC_INT6

EDMA3_CC_INT7

MCBSP0_RINT

MCBSP0_XINT

MCBSP0_REVT

MCBSP0_XEVT

MCBSP1_RINT

MCBSP1_XINT

System Interrupt

GPINT24

GPINT25

GPINT26

GPINT27

GPINT28

GPINT29

GPINT30

GPINT31

EDMA3_CC_ERRINT

EDMA3_CC_MPINT

EDMA3_TC_ERRINT0

EDMA3_TC_ERRINT1

EDMA3_TC_ERRINT2

EDMA3_TC_ERRINT3

MCBSP1_REVT

MCBSP1_XEVT

UARTINT_B

URXEVT_B

UTXEVT_B

Reserved

PCIEXpress_ERR_INT

PCIEXpress_PM_INT

PCIEXpress_Legacy_INTA

PCIEXpress_Legacy_INTB

Description

GPIO interrupt

EDMA3_CC error interrupt

EDMA3_CC memory protection interrupt

EDMA3_CC TC0 error interrupt

EDMA3_CC TC1 error interrupt

EDMA3_CC TC2 error interrupt

EDMA3_CC TC3 error interrupt

EDMA3_CC GINT

EDMA3_CC individual completion interrupt

McBSP0 interrupt

McBSP1 interrupt

UART_1 interrupt

Protocol error interrupt

Power management interrupt

Legacy interrupt mode

151 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 7-34

Input Event# on CIC

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 6)

System Interrupt

PCIEXpress_Legacy_CIC

PCIEXpress_Legacy_INTD

SPIINT0

SPIINT1

SPIXEVT

SPIREVT

I2CINT

I2CREVT

I2CXEVT

Reserved

Description

Legacy interrupt mode

SPI interrupt0

SPI interrupt1

Transmit event

Receive event

C interrupt

C receive event

C transmit event

Reserved

TETBHFULLINT

TETBFULLINT

TETBACQINT

TETB is half full

TETB is full

Acquisition has been completed

Overflow condition occur TETBOVFLINT

TETBUNFLINT

SEMINT2

SEMINT3

SEMERR2

SEMERR3

Reserved

Tracer_core_0_INTD

Underflow condition occur

Semaphore interrupt

Tracer_core_1_INTD

Reserved

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for individual core (C6657 only)

Reserved

Tracer_DDR_INTD

Tracer_MSMC_0_INTD

Tracer_MSMC_1_INTD

Tracer_MSMC_2_INTD

Tracer_MSMC_3_INTD

Tracer_CFG_INTD

Tracer_QM_CFG_INTD

Tracer_QM_DMA_INTD

Tracer_SEM_INTD

Tracer sliding time window interrupt for DDR3 EMIF1

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave

Tracer sliding time window interrupt for semaphore

PSC_ALLINT Power/sleep controller interrupt

MSMC_scrub_cerror

BOOTCFG_INTD po_vcon_smpserr_intr

MPU0_INTD (MPU0_ADDR_ERR_INT and

MPU0_PROT_ERR_INT combined)

Correctable (1-bit) soft error detected during scrub cycle

Chip-level MMR error register

SmartReflex VolCon error status

MPU0 addressing violation interrupt and protection violation interrupt.

Reserved

MPU1_INTD (MPU1_ADDR_ERR_INT and

MPU1_PROT_ERR_INT combined)

Reserved

MPU1 addressing violation interrupt and protection violation interrupt.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 152

125

126

127

128

121

122

123

124

117

118

119

120

113

114

115

116

109

110

111

112

105

107

108

101

102

103

104

100

133

134

135

136

129

130

131

132

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-34 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 6)

Input Event# on CIC

www.ti.com

INTDST1

INTDST2

INTDST3

INTDST4

INTDST5

INTDST6

INTDST7

INTDST8

System Interrupt

MPU2_INTD (MPU2_ADDR_ERR_INT and

MPU2_PROT_ERR_INT combined)

Description

MPU2 addressing violation interrupt and protection violation interrupt.

Reserved

MPU3_INTD (MPU3_ADDR_ERR_INT and

MPU3_PROT_ERR_INT combined)

MPU3 addressing violation interrupt and protection violation interrupt.

Reserved

MSMC_dedc_cerror

MSMC_dedc_nc_error

MSMC_scrub_nc_error

Reserved

MSMC_mpf_error8

MSMC_mpf_error9

MSMC_mpf_error10

MSMC_mpf_error11

MSMC_mpf_error12

MSMC_mpf_error13

MSMC_mpf_error14

MSMC_mpf_error15

DDR3_ERR

HyperLink_int_o

INTDST0

Correctable (1-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected during scrub cycle

Memory protection fault indicators for each system master PrivID

DDR3 EMIF error interrupt

HyperLink interrupt

RapidIO interrupt

INTDST9

INTDST10

INTDST11

INTDST12

INTDST13

INTDST14

INTDST15

Reserved

RapidIO interrupt)

RapidIO interrupt

Reserved po_vp_smpsack_intr

Reserved

QM_INT_PASS_TXQ_PEND_662

QM_INT_PASS_TXQ_PEND_663

QM_INT_PASS_TXQ_PEND_664

Indicating that Volt_Proc receives the r-edge at its smpsack input

Queue manager pend event

Submit Documentation Feedback

175

176

177

178

179

www.ti.com

Table 7-34

163

164

165

166

159

160

161

162

155

156

157

158

151

152

153

154

171

172

173

174

167

168

169

170

147

148

149

150

143

144

145

146

Input Event# on CIC

137

138

139

140

141

142

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 5 of 6)

System Interrupt

QM_INT_PASS_TXQ_PEND_665

QM_INT_PASS_TXQ_PEND_666

QM_INT_PASS_TXQ_PEND_667

QM_INT_PASS_TXQ_PEND_668

QM_INT_PASS_TXQ_PEND_669

QM_INT_PASS_TXQ_PEND_670

VCP0INT

VCP1INT

TINT4L

TINT4H

VCP0REVT

VCP0XEVT

VCP1REVT

VCP1XEVT

TINT5L

TINT5H

TINT6L

TINT6H

TCP_INTD

Description

Queue manager pend event

VCP2_0 interrupt

VCP2_1 interrupt

Timer4 interrupt low

Timer4 interrupt high

VCP2_0 interrupt

VCP2_1 interrupt

Timer5 interrupt low

Timer5 interrupt high

Timer6 interrupt low

Timer6 interrupt high

TCP3d interrupt

TCP_REVT0

TCP_XEVT0

Reserved

MSMC_mpf_error2

MSMC_mpf_error3

TINT7L

TINT7H

UARTINT_A

URXEVT_A

UTXEVT_A

EASYNCERR

Tracer_EMIF16

TCP3d interrupt

Memory protection fault indicators for each system master PrivID

Timer7 interrupt low

Timer7interrupt high

UART_0 interrupt

EMIF16 error interrupt

Tracer sliding time window interrupt for EMIF16

Reserved

MSMC_mpf_error4

MSMC_mpf_error5

MSMC_mpf_error6

MSMC_mpf_error7

MPU4_INTD (MPU4_ADDR_ERR_INT and

MPU4_PROT_ERR_INT combined)

Memory protection fault indicators for each system master PrivID

MPU4 addressing violation interrupt and protection violation interrupt.

QM_INT_PASS_TXQ_PEND_671

QM_INT_PKTDMA_0

QM_INT_PKTDMA_1

SRIO_INT_PKTDMA_0

Reserved

Queue manager pend event

QM interrupt for CDMA starvation

SRIO interrupt for CDMA starvation

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 154

199

200

201

202

195

196

197

198

191

192

193

194

187

188

189

190

203

204

205

206

207

End of Table 7-34

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-34 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 6 of 6)

Input Event# on CIC

180

181

182

183

184

185

186

System Interrupt

Reserved

SmartReflex_intrreq0

SmartReflex_intrreq1

SmartReflex_intrreq2

SmartReflex_intrreq3

VPNoSMPSAck

VPEqValue

Description www.ti.com

SmartReflex sensor interrupt

VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval

SRSINTERUPT is asserted, but the new voltage is not different from the current

SMPS voltage

The new voltage required is equal to or greater than MaxVdd.

The new voltage required is equal to or less than MinVdd.

Indicating that the FSM of voltage processor is in idle.

Indicating that the average frequency error is within the desired limit.

VPMaxVdd

VPMinVdd

VPINIDLE

VPOPPChangeDone

Reserved

MACINT4

MACRXINT4

MACTXINT4

MACTRESH4

MACINT5

MACRXINT5

MACTXINT5

MACTRESH5

MACINT6

MACRXINT6

MACTXINT6

MACTRESH6

MACINT7

MACRXINT7

MACTXINT7

MACTRESH7

EMAC interrupt

Table 7-35 CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 1 of 5)

Input Event # on CIC System Interrupt

0 GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

Reserved

Description

GPIO interrupt

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-35 CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 2 of 5)

Input Event # on CIC System Interrupt

TETBACQINT

Reserved

TETBACQINT0

Reserved

TETBACQINT1

GPINT16

GPINT17

GPINT18

GPINT19

GPINT20

GPINT21

Reserved

QM_INT_HIGH_16

QM_INT_HIGH_17

QM_INT_HIGH_18

QM_INT_HIGH_19

QM_INT_HIGH_20

QM_INT_HIGH_21

QM_INT_HIGH_22

QM_INT_HIGH_23

QM_INT_HIGH_24

QM_INT_HIGH_25

QM_INT_HIGH_26

QM_INT_HIGH_27

QM_INT_HIGH_28

QM_INT_HIGH_29

QM_INT_HIGH_30

QM_INT_HIGH_31

Reserved

Tracer_core_0_INTD

Tracer_core_1_INTD

GPINT22

GPINT23

Tracer_DDR_INTD

Tracer_MSMC_0_INTD

Tracer_MSMC_1_INTD

Tracer_MSMC_2_INTD

Tracer_MSMC_3_INTD

Description

System TETB acquisition has been completed

TETB0 acquisition has been completed

TETB1 acquisition has been completed (C6657 only)

GPIO interrupt

QM interrupt

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for individual core (C6657 only)

GPIO interrupt

Tracer sliding time window interrupt for DDR3 EMIF

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 156

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-35 CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 3 of 5)

Input Event # on CIC System Interrupt

Tracer_CFG_INTD

Tracer_QM_CFG_INTD

Tracer_QM_DMA_INTD

Tracer_SEM_INTD

SEMERR0

SEMERR1

SEMERR2

SEMERR3

BOOTCFG_INTD

UPPINT

MPU0_INTD (MPU0_ADDR_ERR_INT and

MPU0_PROT_ERR_INT combined)

MSMC_scrub_cerror

MPU1_INTD (MPU1_ADDR_ERR_INT and

MPU1_PROT_ERR_INT combined)

RapidIO_INT_PKTDMA_0

MPU2_INTD (MPU2_ADDR_ERR_INT and

MPU2_PROT_ERR_INT combined)

QM_INT_PKTDMA_0

MPU3_INTD (MPU3_ADDR_ERR_INT and

MPU3_PROT_ERR_INT combined)

QM_INT_PKTDMA_1

MSMC_dedc_cerror

MSMC_dedc_nc_error

MSMC_scrub_nc_error

Reserved

MSMC_mpf_error0

MSMC_mpf_error1

MSMC_mpf_error2

MSMC_mpf_error3

MSMC_mpf_error4

MSMC_mpf_error5

MSMC_mpf_error6

MSMC_mpf_error7

MSMC_mpf_error8

MSMC_mpf_error9

MSMC_mpf_error10

MSMC_mpf_error11

MSMC_mpf_error12

MSMC_mpf_error13

MSMC_mpf_error14

MSMC_mpf_error15

Reserved

INTDST0

INTDST1

Description

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave port

Tracer sliding time window interrupt for semaphore

Semaphore interrupt

BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT uPP interrupt

MPU0 addressing violation interrupt and protection violation interrupt.

Correctable (1-bit) soft error detected during scrub cycle

MPU1 addressing violation interrupt and protection violation interrupt.

RapidIO interrupt for packet DMA starvation

MPU2 addressing violation interrupt and protection violation interrupt.

QM interrupt for packet DMA starvation

MPU3 addressing violation interrupt and protection violation interrupt.

QM interrupt for packet DMA starvation

Correctable (1-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected during scrub cycle

Memory protection fault indicators for each system master PrivID

RapidIO interrupt

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-35

129

130

131

132

125

126

127

128

133

134

135

121

122

123

124

117

118

119

120

113

114

115

116

109

110

111

112

105

106

107

108

101

102

103

104

Input Event # on CIC System Interrupt

INTDST2

INTDST3

100

INTDST4

INTDST5

INTDST6

INTDST7

INTDST8

INTDST9

INTDST10

INTDST11

INTDST12

INTDST13

INTDST14

INTDST15

INTDST16

INTDST17

INTDST18

INTDST19

INTDST20

INTDST21

INTDST22

INTDST23

GPINT24

GPINT25

VCP0INT

VCP1INT

GPINT26

GPINT27

TCP3D_INTD

GPINT28

136

GPINT29

GPINT30

GPINT31

GPINT4

GPINT5

GPINT6

GPINT7

Hyperlink_int_o

Tracer_EMIF16

EASYNCERR

MPU4_INTD (MPU4_ADDR_ERR_INT and

MPU4_PROT_ERR_INT combined)

Reserved

137 QM_INT_HIGH_0

CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 4 of 5)

Description

RapidIO interrupt

GPIO interrupt

VCP2_0 Error interrupt

VCP2_1 Error interrupt

GPIO interrupt

Error interrupt TCP3DINT0 and TCP3DINT1

GPIO interrupt

Hyperlink interrupt

Tracer sliding time window interrupt for EMIF16

EMIF16 error interrupt

MPU4 addressing violation interrupt and protection violation interrupt.

QM interrupt

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 158

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-35 CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 5 of 5)

148

149

150

151

144

145

146

147

Input Event # on CIC System Interrupt

138

139

QM_INT_HIGH_1

QM_INT_HIGH_2

140

141

142

143

QM_INT_HIGH_3

QM_INT_HIGH_4

QM_INT_HIGH_5

QM_INT_HIGH_6

QM_INT_HIGH_7

QM_INT_HIGH_8

QM_INT_HIGH_9

QM_INT_HIGH_10

QM_INT_HIGH_11

QM_INT_HIGH_12

QM_INT_HIGH_13

QM_INT_HIGH_14

152

153

154

155

156

157

158

159

End of Table 7-35

QM_INT_HIGH_15

Reserved

DDR3_ERR

Description

QM interrupt

DDR3 error interrupt

Table 7-36 CIC2 Event Inputs (Secondary Events for HyperLink) (Part 1 of 3)

Input Event # on CIC

GPINT7

GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

System Interrupt

GPINT0

GPINT1

GPINT2

GPINT3

GPINT4

GPINT5

GPINT6

GPINT15

TETBHFULLINT

TETBFULLINT

Description

GPIO interrupt

System TETB is half full

System TETB is full

159 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-36 CIC2 Event Inputs (Secondary Events for HyperLink) (Part 2 of 3)

Input Event # on CIC

GPINT27

TINT4L

TINT4H

TINT5L

TINT5H

TINT6L

TINT6H

TINT7L

TINT7H

Reserved

Tracer_EMIF16

DDR3_ERR

System Interrupt

TETBACQINT

TETBHFULLINT0

TETBFULLINT0

TETBACQINT0

TETBHFULLINT1

TETBFULLINT1

TETBACQINT1

GPINT16

GPINT17

GPINT18

GPINT19

GPINT20

GPINT21

Tracer_core_0_INTD

Tracer_core_1_INTD

GPINT22

GPINT23

Tracer_DDR_INTD

Tracer_MSMC_0_INTD

Tracer_MSMC_1_INTD

Tracer_MSMC_2_INTD

Tracer_MSMC_3_INTD

Tracer_CFG_INTD

Tracer_QM_SS_CFG_INTD

Tracer_QM_SS_DMA_INTD

Tracer_SEM_INTD

Reserved

GPINT24

GPINT25

GPINT26

Description

System TETB acquisition has been completed

TETB0 is half full

TETB0 is full

TETB0 acquisition has been completed

TETB1 is half full

TETB1 is full

TETB1 acquisition has been completed

GPIO interrupt

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for individual core (C6657 only)

GPIO interrupt

Tracer sliding time window interrupt for DDR3 EMIF1

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave port

Tracer sliding time window interrupt for semaphore

GPIO interrupt

Timer64_4 interrupt low

Timer64_4 interrupt high

Timer64_5 interrupt low timer64_5 interrupt high

Timer64_6 interrupt low

Timer64_6 interrupt high

Timer64_7 interrupt low

Timer64_7 interrupt high

Tracer sliding time window interrupt for EMIF16

DDR3 EMIF Error interrupt

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 160

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-36 CIC2 Event Inputs (Secondary Events for HyperLink) (Part 3 of 3)

Input Event # on CIC

72-79

End of Table 7-36

System Interrupt

po_vp_smpsack_intr

EASYNCERR

GPINT28

GPINT29

GPINT30

GPINT31

TINT2L

TINT2H

TINT3L

TINT3H

Reserved

Description

Indicating that Volt_Proc receives the r-edge at its smpsack input.

EMIF16 error interrupt

GPIO interrupt

Timer2 interrupt low

Timer2 interrupt high

Timer2 interrupt low

Timer2 interrupt high

www.ti.com

7.8.2 CIC Registers

This section includes the offsets for CIC registers. The base addresses for interrupt control registers are CIC0 -

0x0260 0000, CIC1 - 0x0260 4000, and CIC2 - 0x0260 8000.

7.8.2.1 CIC0 Register Map

Table 7-37

0x214

0x218

0x280

0x284

0x288

0x28c

0x290

0x294

0x298

0x2c

0x34

0x38

0x200

0x204

0x208

0x20c

0x210

Address Offset

0x0

0x4

0xc

0x10

0x20

0x24

0x28

CIC0 Register (Part 1 of 4)

Register Mnemonic

REVISION_REG

CONTROL_REG

HOST_CONTROL_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

RAW_STATUS_REG3

RAW_STATUS_REG4

RAW_STATUS_REG5

RAW_STATUS_REG6

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENA_STATUS_REG3

ENA_STATUS_REG4

ENA_STATUS_REG5

ENA_STATUS_REG6

Register Name

Revision Register

Control Register

Host Control Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Raw Status Register 3

Raw Status Register 4

Raw Status Register 5

Raw Status Register 6

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enabled Status Register 3

Enabled Status Register 4

Enabled Status Register 5

Enabled Status Register 6

Submit Documentation Feedback

www.ti.com

Table 7-37

0x420

0x424

0x428

0x42c

0x430

0x434

0x438

0x43c

0x400

0x404

0x408

0x40c

0x410

0x414

0x418

0x41c

0x318

0x380

0x384

0x388

0x38c

0x390

0x394

0x398

Address Offset

0x300

0x304

0x308

0x30c

0x310

0x314

0x460

0x464

0x468

0x46c

0x470

0x474

0x440

0x444

0x448

0x44c

0x450

0x454

0x458

0x45c

CIC0 Register (Part 2 of 4)

CH_MAP_REG16

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG19

CH_MAP_REG20

CH_MAP_REG21

CH_MAP_REG22

CH_MAP_REG23

CH_MAP_REG24

CH_MAP_REG25

CH_MAP_REG26

CH_MAP_REG27

CH_MAP_REG28

CH_MAP_REG29

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

CH_MAP_REG15

Register Mnemonic

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_REG3

ENABLE_REG4

ENABLE_REG5

ENABLE_REG6

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

ENABLE_CLR_REG3

ENABLE_CLR_REG4

ENABLE_CLR_REG5

ENABLE_CLR_REG6

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Register Name

Enable Register 0

Enable Register 1

Enable Register 2

Enable Register 3

Enable Register 4

Enable Register 5

Enable Register 6

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Enable Clear Register 3

Enable Clear Register 4

Enable Clear Register 5

Enable Clear Register 6

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Interrupt Channel Map Register for 80 to 80+3

Interrupt Channel Map Register for 84 to 84+3

Interrupt Channel Map Register for 88 to 88+3

Interrupt Channel Map Register for 92 to 92+3

Interrupt Channel Map Register for 96 to 96+3

Interrupt Channel Map Register for 100 to 100+3

Interrupt Channel Map Register for 104 to 104+3

Interrupt Channel Map Register for 108 to 108+3

Interrupt Channel Map Register for 112 to 112+3

Interrupt Channel Map Register for 116 to 116+3

Peripheral Information and Electrical Specifications 162

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-37 CIC0 Register (Part 3 of 4)

0x800

0x804

0x808

0x80c

0x810

0x814

0x818

0x81c

0x4b0

0x4b4

0x4b8

0x4bc

0x4c0

0x4c4

0x4c8

0x4cc

0x490

0x494

0x498

0x49c

0x4a0

0x4a4

0x4a8

0x4ac

Address Offset

0x478

0x47c

0x480

0x484

0x488

0x48c

0x840

0x844

0x848

0x84c

0x850

0x854

0x820

0x824

0x828

0x82c

0x830

0x834

0x838

0x83c

CH_MAP_REG44

CH_MAP_REG45

CH_MAP_REG46

CH_MAP_REG47

CH_MAP_REG48

CH_MAP_REG49

CH_MAP_REG50

CH_MAP_REG51

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

Register Mnemonic

CH_MAP_REG30

CH_MAP_REG31

CH_MAP_REG32

CH_MAP_REG33

CH_MAP_REG34

CH_MAP_REG35

CH_MAP_REG36

CH_MAP_REG37

CH_MAP_REG38

CH_MAP_REG39

CH_MAP_REG40

CH_MAP_REG41

CH_MAP_REG42

CH_MAP_REG43

HINT_MAP_REG8

HINT_MAP_REG9

HINT_MAP_REG10

HINT_MAP_REG11

HINT_MAP_REG12

HINT_MAP_REG13

HINT_MAP_REG14

HINT_MAP_REG15

HINT_MAP_REG16

HINT_MAP_REG17

HINT_MAP_REG18

HINT_MAP_REG19

HINT_MAP_REG20

HINT_MAP_REG21

Register Name

Interrupt Channel Map Register for 120 to 120+3

Interrupt Channel Map Register for 124 to 124+3

Interrupt Channel Map Register for 128 to 128+3

Interrupt Channel Map Register for 132 to 132+3

Interrupt Channel Map Register for 136 to 136+3

Interrupt Channel Map Register for 140 to 140+3

Interrupt Channel Map Register for 144 to 144+3

Interrupt Channel Map Register for 148 to 148+3

Interrupt Channel Map Register for 152 to 152+3

Interrupt Channel Map Register for 156 to 156+3

Interrupt Channel Map Register for 160 to 160+3

Interrupt Channel Map Register for 164 to 164+3

Interrupt Channel Map Register for 168 to 168+3

Interrupt Channel Map Register for 172 to 172+3

Interrupt Channel Map Register for 176 to 176+3

Interrupt Channel Map Register for 180 to 180+3

Interrupt Channel Map Register for 184 to 184+3

Interrupt Channel Map Register for 188 to 188+3

Interrupt Channel Map Register for 192 to 192+3

Interrupt Channel Map Register for 196 to 196+3

Interrupt Channel Map Register for 200 to 200+3

Interrupt Channel Map Register for 204 to 204+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Interrupt Map Register for 32 to 32+3

Host Interrupt Map Register for 36 to 36+3

Host Interrupt Map Register for 40 to 40+3

Host Interrupt Map Register for 44 to 44+3

Host Interrupt Map Register for 48 to 48+3

Host Interrupt Map Register for 52 to 52+3

Host Interrupt Map Register for 56 to 56+3

Host Interrupt Map Register for 60 to 60+3

Host Interrupt Map Register for 64 to 64+3

Host Interrupt Map Register for 68 to 68+3

Host Interrupt Map Register for 72 to 72+3

Host Interrupt Map Register for 76 to 76+3

Host Interrupt Map Register for 80 to 80+3

Host Interrupt Map Register for 84 to 84+3

163 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 7-37 CIC0 Register (Part 4 of 4)

Address Offset

0x858

0x860

0x1500

0x1504

0x1508

End of Table 7-37

Register Mnemonic

HINT_MAP_REG22

HINT_MAP_REG23

ENABLE_HINT_REG0

ENABLE_HINT_REG1

ENABLE_HINT_REG2

7.8.2.2 CIC1 Register Map

Table 7-38

0x380

0x384

0x388

0x38c

0x390

0x400

0x404

0x408

0x40c

0x410

0x288

0x28c

0x290

0x300

0x304

0x308

0x30c

0x310

0x38

0x200

0x204

0x208

0x20c

0x210

0x280

0x284

Address Offset

0x0

0x10

0x20

0x24

0x28

0x2c

0x34

CIC1 Register (Part 1 of 3)

Register Mnemonic

REVISION_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

RAW_STATUS_REG3

RAW_STATUS_REG4

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENA_STATUS_REG3

ENA_STATUS_REG4

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_REG3

ENABLE_REG4

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

ENABLE_CLR_REG3

ENABLE_CLR_REG4

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Register Name

Host Interrupt Map Register for 88 to 88+3

Host Interrupt Map Register for 92 to 92+3

Host Int Enable Register 0

Host Int Enable Register 1

Host Int Enable Register 2

Register Name

Revision Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Raw Status Register 3

Raw Status Register 4

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enabled Status Register 3

Enabled Status Register 4

Enable Register 0

Enable Register 1

Enable Register 2

Enable Register 3

Enable Register 4

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Enable Clear Register 3

Enable Clear Register 4

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Peripheral Information and Electrical Specifications 164

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-38 CIC1 Register (Part 2 of 3)

0x46c

0x470

0x474

0x478

0x47c

0x480

0x484

0x488

0x44c

0x450

0x454

0x458

0x45c

0x460

0x464

0x468

0x42c

0x430

0x434

0x438

0x43c

0x440

0x444

0x448

Address Offset

0x414

0x418

0x41c

0x420

0x424

0x428

0x80c

0x810

0x814

0x818

0x81c

0x820

0x48c

0x490

0x494

0x498

0x49c

0x800

0x804

0x808

CH_MAP_REG19

CH_MAP_REG20

CH_MAP_REG21

CH_MAP_REG22

CH_MAP_REG23

CH_MAP_REG24

CH_MAP_REG25

CH_MAP_REG26

CH_MAP_REG27

CH_MAP_REG28

CH_MAP_REG29

CH_MAP_REG30

CH_MAP_REG31

CH_MAP_REG32

CH_MAP_REG33

CH_MAP_REG34

Register Mnemonic

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

CH_MAP_REG15

CH_MAP_REG16

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG35

CH_MAP_REG36

CH_MAP_REG37

CH_MAP_REG38

CH_MAP_REG39

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

HINT_MAP_REG8

Register Name

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Interrupt Channel Map Register for 80 to 80+3

Interrupt Channel Map Register for 84 to 84+3

Interrupt Channel Map Register for 88 to 88+3

Interrupt Channel Map Register for 92 to 92+3

Interrupt Channel Map Register for 96 to 96+3

Interrupt Channel Map Register for 100 to 100+3

Interrupt Channel Map Register for 104 to 104+3

Interrupt Channel Map Register for 108 to 108+3

Interrupt Channel Map Register for 112 to 112+3

Interrupt Channel Map Register for 116 to 116+3

Interrupt Channel Map Register for 120 to 120+3

Interrupt Channel Map Register for 124 to 124+3

Interrupt Channel Map Register for 128 to 128+3

Interrupt Channel Map Register for 132 to 132+3

Interrupt Channel Map Register for 136 to 136+3

Interrupt Channel Map Register for 140 to 140+3

Interrupt Channel Map Register for 144 to 144+3

Interrupt Channel Map Register for 148 to 148+3

Interrupt Channel Map Register for 152 to 152+3

Interrupt Channel Map Register for 156 to 156+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Interrupt Map Register for 32 to 32+3

165 Peripheral Information and Electrical Specifications

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 7-38 CIC1 Register (Part 3 of 3)

Address Offset

0x824

0x828

0x82c

0x830

0x834

0x838

0x83c

0x1500

0x1504

End of Table 7-38

Register Mnemonic

HINT_MAP_REG9

HINT_MAP_REG10

HINT_MAP_REG11

HINT_MAP_REG12

HINT_MAP_REG13

HINT_MAP_REG14

HINT_MAP_REG15

ENABLE_HINT_REG0

ENABLE_HINT_REG1

7.8.2.3 CIC2 Register Map

Table 7-39

0x40c

0x410

0x414

0x418

0x41c

0x420

0x304

0x308

0x380

0x384

0x388

0x400

0x404

0x408

0x38

0x200

0x204

0x208

0x280

0x284

0x288

0x300

Address Offset

0x0

0x10

0x20

0x24

0x28

0x2c

0x34

CIC2 Register (Part 1 of 2)

Register Mnemonic

REVISION_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Register Name

Host Interrupt Map Register for 36 to 36+3

Host Interrupt Map Register for 40 to 40+3

Host Interrupt Map Register for 44 to 44+3

Host Interrupt Map Register for 48 to 48+3

Host Interrupt Map Register for 52 to 52+3

Host Interrupt Map Register for 56 to 56+3

Host Interrupt Map Register for 60 to 60+3

Host Int Enable Register 0

Host Int Enable Register 1

Register Name

Revision Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enable Register 0

Enable Register 1

Enable Register 2

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Peripheral Information and Electrical Specifications 166

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-39 CIC2 Register (Part 2 of 2)

0x43c

0x440

0x444

0x448

0x44c

0x800

0x804

0x808

Address Offset

0x424

0x428

0x42c

0x430

0x434

0x438

0x80c

0x810

0x814

0x818

0x81c

0x1500

End of Table 7-39

Register Mnemonic

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

CH_MAP_REG15

CH_MAP_REG16

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG19

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

ENABLE_HINT_REG0

Register Name

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Int Enable Register 0

7.8.3 Inter-Processor Register Map

Table 7-40

Address Start

0x02620200

0x02620204

0x02620208

0x0262020C

0x02620210

0x02620214

0x02620218

0x0262021C

0x02620220

0x02620240

0x02620244

0x02620248

0x0262024C

0x02620250

0x02620254

0x02620258

0x0262025C

0x02620260

IPC Generation Registers (IPCGRx) (Part 1 of 2)

Address End

0x02620203

0x02620207

0x0262020B

0x0262020F

0x02620213

0x02620217

0x0262021B

0x0262021F

0x0262023F

0x02620243

0x02620247

0x0262024B

0x0262024F

0x02620253

0x02620257

0x0262025B

0x0262025F

0x0262027B

32B

Size

28B

Reserved

IPCGR0

IPCGR1

Reserved

Register Name

NMIGR0

NMIGR1

Reserved

167 Peripheral Information and Electrical Specifications

www.ti.com

Description

NMI Event Generation Register for CorePac0

NMI Event Generation Register for CorePac 1 (C6657 only)

Reserved

IPC Generation Register for CorePac 0

IPC Generation Register for CorePac 1 (C6657 only)

Reserved

Submit Documentation Feedback

www.ti.com

Table 7-40

Address Start

0x0262027C

0x02620280

0x02620284

0x02620288

0x0262028C

0x02620290

0x02620294

0x02620298

0x0262029C

0x026202A0

0x026202BC

End of Table 7-40

IPC Generation Registers (IPCGRx) (Part 2 of 2)

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Address End

0x0262027F

0x02620283

0x02620287

0x0262028B

0x0262028F

0x02620293

0x02620297

0x0262029B

0x0262029F

0x026202BB

0x026202BF

Size

28B

Register Name

IPCGRH

IPCAR0

IPCAR1

Reserved

IPCARH

Description

IPC Generation Register for Host

IPC Acknowledgement Register for CorePac 0

IPC Acknowledgement Register for CorePac 1 (C6657 only)

Reserved

IPC Acknowledgement Register for Host

7.8.4 NMI and LRESET

Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One

NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured to select between the CorePacs available as shown in

Table 7-41 .

Table 7-41 LRESET and NMI Decoding

CORESEL[1:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output

XX X X 1 No local reset or NMI assertion.

Assert local reset to CorePac 0

Assert local reset to CorePac 1 (C6657) or Reserved

(C6655)

Assert local reset to all CorePacs

De-assert local reset & NMI to CorePac 0

De-assert local reset & NMI to CorePac 1 (C6657) or

Reserved (C6655)

End of Table 7-41

De-assert local reset & NMI to all CorePacs

Assert NMI to CorePac 0

Assert NMI to CorePac 1 (C6657) or Reserved (C6655)

Assert NMI to all CorePacs

7.8.5 External Interrupts Electrical Data/Timing

Table 7-42

(see Figure 7-26 )

NMI and Local Reset Timing Requirements

(1)

No.

1 tsu(LRESET-LRESETNMIENL)

1 tsu(NMI-LRESETNMIENL)

1 tsu(CORESELn-LRESETNMIENL) th(LRESETNMIENL-LRESET) th(LRESETNMIENL-NMI)

Setup Time - LRESET valid before LRESETNMIEN low

Setup Time - NMI valid before LRESETNMIEN low

Setup Time - CORESEL[2:0] valid before LRESETNMIEN low

Hold Time - LRESET valid after LRESETNMIEN high

Hold Time - NMI valid after LRESETNMIEN high

Min

12*P

Max Unit

ns ns ns ns ns

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 168

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-42

(see Figure 7-26 )

NMI and Local Reset Timing Requirements

(1)

No.

2 th(LRESETNMIENL-CORESELn)

3 tw(LRESETNMIEN)

End of Table 7-42

1 P = 1/SYSCLK1 clock frequency in ns.

Hold Time - CORESEL[2:0] valid after LRESETNMIEN high

Pulse Width - LRESETNMIEN low width

Figure 7-26 NMI and Local Reset Timing

CORESEL[3:0]/

LRESET /

NMI

LRESETNMIEN

www.ti.com

Min

12*P

Max Unit

ns ns

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.9 Memory Protection Unit (MPU)

The C6655/57 supports five MPUs:

• One MPU is used to protect main CORE/3 CFG TeraNet (CFG space of all slave devices on the TeraNet is protected by the MPU).

• Two MPUs are used for QM_SS (one for the DATA PORT port and the other is for the CFG PORT port).

• One MPU is used for Semaphore.

• One MPU is used for EMIF16

This section contains MPU register map and details of device-specific MPU registers only. For MPU features and

Table 7-45 also shows the privilege

The following tables show the configuration of each MPU and the memory regions protected by each MPU.

Table 7-43 MPU Default Configuration

Setting

Default permission

Number of allowed IDs supported

Number of programmable ranges supported

Compare width

End of Table 7-43

MPU0

Main CFG

TeraNet

MPU1

(QM_SS DATA PORT)

Assume allowed Assume allowed

16 16

16 5

1KB granularity 1KB granularity

MPU2

(QM_SS CFG PORT)

Assume allowed

MPU3

Semaphore

MPU4

EMIF16

Assume allowed Assume allowed

16 16

1 16

1KB granularity 1KB granularity 1KB granularity

Table 7-44

MPU0

MPU1

MPU2

MPU3

MPU4

MPU Memory Regions

Memory Protection

Main CFG TeraNet

QM_SS DATA PORT

QM_SS CFG PORT

Semaphore

EMIF16

Start Address

0x01D00000

0x34000000

0x02A00000

0x02640000

0x70000000

End Address

0x026203FF

0x340BFFFF

0x02ABFFFF

0x026407FF

0x7FFFFFFF

Table 7-45

shows the privilege ID of each CORE and every mastering peripheral.

level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.

Table 7-45 Privilege ID Settings (Part 1 of 2)

Privilege ID Master

0 CorePac0

CorePac1 (C657 only)

Reserved

Reserved uPP

EMAC

Privilege Level

SW dependant, driven by MSMC

User

Security Level

SW dependant

Non-secure

Access Type

DMA

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 170

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-45 Privilege ID Settings (Part 2 of 2) www.ti.com

Privilege ID

Master

QM_PKTDMA

SRIO_PKTDMA/SRIO_M

QM_second

PCIe

DAP

HyperLink

Privilege Level

User

User/Driven by SRIO block, user mode and supervisor mode is determined on a per-transaction basis. Only the transaction with source ID matching the value in the SupervisorID Register is granted supervisor mode.

Non-secure

User

Supervisor

Driven by debug_SS

Supervisor

HyperLink Supervisor

HyperLink

End of Table 7-45

Supervisor

Security Level

Non-secure

Driven by debug_SS DMA

Non-secure DMA

Non-secure

Access Type

DMA

Table 7-46

shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters, master IDs are unique to each master.

Table 7-46 Master ID Settings (Part 1 of 3)

(1)

Master ID

Reserved

Master

CorePac0

CorePac1 (C6657) or Reserved (C6655)

Reserved

CorePac0_CFG

CorePac1_CFG (C6657) or Reserved (C6655)

Reserved

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-46 Master ID Settings (Part 2 of 3)

(1)

36 - 37

38 - 39

40 - 47

Master ID

Master

Reserved

EDMA_TC0 read

EDMA_TC0 write

EDMA_TC1 read

EDMA_TC1 write

EDMA_TC2 read

EDMA_TC2 write

EDMA_TC3 read

EDMA_TC3 write

Reserved

SRIO_PKTDMA

Reserved

DAP

Reserved

140

141

142

143

144

136

137

138

139

132

133

134

135

128

129

130

131

EDMA3_CC

Reserved

MSMC

PCIe

(2)

SRIO_Master(

HyperLink

56 EMAC

57 - 87

88 - 91

Reserved

QM_PKTDMA

92 - 93

96 - 127

QM_second

Reserved uPP

Reserved

Tracer_core_0

(3)

Tracer_core_1 (C6657) or Reserved (C6655)

Reserved

Tracer_MSMC0

Tracer_MSMC1

Tracer_MSMC2

Tracer_MSMC3

Tracer_DDR

Tracer_SEM

Tracer_QM_CFG

Tracer_QM_Data

Tracer_CFG

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 172

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-46 Master ID Settings (Part 3 of 3)

(1) www.ti.com

Master ID

145

146

147

148

End of Table 7-46

Master

Reserved

Tracer_EMIF16

1 Some of the PKTDMA-based peripherals require multiple master IDs. QMS_PKTDMA is assigned with 88,89,90,91, but only 88-89 are actually used. There are two master ID values are assigned for the QM_second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses.

2 The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.

3 All Tracers are set to the same master ID and bit 7 of the master ID needs to be 1.

7.9.1 MPU Registers

This section includes the offsets for MPU registers and definitions for device specific MPU registers.

7.9.1.1 MPU Register Map

Table 7-47

228h

230h

234h

238h

240h

244h

248h

250h

254h

258h

260h

264h

268h

200h

204h

208h

210h

214h

218h

220h

224h

14h

18h

1Ch

20h

Offset

10h

MPU0 Registers (Part 1 of 2)

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

PROG5_MPSAR

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-47 MPU0 Registers (Part 2 of 2)

290h

294h

298h

2A0h

2A4h

2A8h

2B0h

2B4h

Offset

270h

274h

278h

280h

284h

288h

2B8h

2C0h

2C4h

2C8h

2D0h

2D4h

2Dh

2E0h

PROG11_MPPA

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

2E4h

2E8h

2F0h

2F4h

PROG14_MPEAR

PROG14_MPPA

PROG15_MPSAR

PROG15_MPEAR

2F8h

300h

PROG15_MPPA

FLTADDRR

304h FLTSTAT

308h FLTCLR

End of Table 7-47

Name

PROG7_MPSAR

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

Description

Programmable range 7, start address

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Table 7-48

14h

18h

1Ch

20h

Offset

10h

200h

204h

MPU1 Registers (Part 1 of 2)

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 174

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-48 MPU1 Registers (Part 2 of 2)

Offset

208h

210h

214h

218h

220h

224h

Name

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

228h

230h

234h

238h

240h

244h

248h

300h

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

FLTADDRR

304h FLTSTAT

308h FLTCLR

End of Table 7-48

Description

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Fault address

Fault status

Fault clear

www.ti.com

Table 7-49

200h

204h

208h

210h

214h

218h

220h

224h

14h

18h

1Ch

20h

Offset

10h

228h

230h

234h

238h

240h

244h

248h

250h

MPU2 Registers (Part 1 of 2)

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

PROG5_MPSAR

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-49 MPU2 Registers (Part 2 of 2)

274h

278h

280h

284h

288h

290h

294h

298h

Offset

254h

258h

260h

264h

268h

270h

2C8h

2D0h

2D4h

2Dh

2E0h

2E4h

2E8h

2F0h

2A0h

2A4h

2A8h

2B0h

2B4h

2B8h

2C0h

2C4h

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

PROG11_MPPA

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

PROG14_MPPA

PROG15_MPSAR

2F4h

2F8h

300h

304h

PROG15_MPEAR

PROG15_MPPA

FLTADDRR

FLTSTAT

308h FLTCLR

End of Table 7-49

Name

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

Description

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Table 7-50

Offset

10h

14h

MPU3 Registers (Part 1 of 2)

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 176

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-50 MPU3 Registers (Part 2 of 2)

Offset

18h

1Ch

20h

200h

204h

208h

Name

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

300h

304h

FLTADDRR

FLTSTAT

308h FLTCLR

End of Table 7-50

Description

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Fault address

Fault status

Fault clear

www.ti.com

Table 7-51

254h

258h

260h

264h

268h

270h

274h

228h

230h

234h

238h

240h

244h

248h

250h

200h

204h

208h

210h

214h

218h

220h

224h

14h

18h

1Ch

20h

Offset

10h

MPU4 Registers (Part 1 of 2)

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

PROG5_MPSAR

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

PROG7_MPEAR

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

Programmable range 7, end address

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-51 MPU4 Registers (Part 2 of 2)

298h

2A0h

2A4h

2A8h

2B0h

2B4h

2B8h

2C0h

Offset

278h

280h

284h

288h

290h

294h

2C4h

2C8h

2D0h

2D4h

2Dh

2E0h

2E4h

2E8h

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

PROG14_MPPA

2F0h

2F4h

2F8h

300h

PROG15_MPSAR

PROG15_MPEAR

PROG15_MPPA

FLTADDRR

304h FLTSTAT

308h FLTCLR

End of Table 7-51

Name

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

PROG11_MPPA

PROG12_MPSAR

Description

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 178

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.9.1.2 Device-Specific MPU Registers

7.9.1.2.1 Configuration Register (CONFIG)

The Configuration Register (CONFIG) contains the configuration value of the MPU.

Figure 7-27 Configuration Register (CONFIG)

Reset Values

MPU0

MPU1

MPU2

MPU3

MPU4

ADDR_WIDTH

R-0

Legend: R = Read only; -n = value after reset

24 23 20

NUM_FIXED

R-0

19 16

NUM_PROG

R-16

R-5

R-16

R-1

R-16

15 12

NUM_AIDS

R-16

Reserved

R-0

www.ti.com

ASSUME_ALLOWED

R-1

Table 7-52 Configuration Register (CONFIG) Field Descriptions

Bit Field

31 – 24 ADDR_WIDTH

23 – 20 NUM_FIXED

19 – 16 NUM_PROG

15 – 12 NUM_AIDS

11 – 1 Reserved

0 ASSUME_ALLOWED

Description

Address alignment for range checking

0 = 1KB alignment

6 = 64KB alignment

Number of fixed address ranges

Number of programmable address ranges

Number of supported AIDs

Reserved. These bits will always reads as 0.

Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not.

0 = Assume disallowed

1 = Assume allowed

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.9.2 MPU Programmable Range Registers

7.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)

The Programmable Address Start Register holds the start address for the range. This register is writeable by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also writeable only by a secure entity.

The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines the width of the address field in MPSAR and MPEAR.

Figure 7-28 Programmable Range n Start Address Register (PROGn_MPSAR)

START_ADDR

R/W

Legend: R = Read only; R/W = Read/Write

10 9

Reserved

Table 7-53 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions

Bit

31 – 10

Field

START_ADDR

9 – 0 Reserved

End of Table 7-53

Description

Start address for range n.

Reserved and these bits always read as 0.

Table 7-54 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values

Register

PROG0_MPSAR

PROG1_MPSAR

PROG2_MPSAR

PROG3_MPSAR

PROG4_MPSAR

PROG5_MPSAR

PROG6_MPSAR

PROG7_MPSAR

PROG8_MPSAR

PROG9_MPSAR

PROG10_MPSAR

PROG11_MPSAR

PROG12_MPSAR

PROG13_MPSAR

PROG14_MPSAR

PROG15_MPSAR

End of Table 7-54

MPU0

0x01D0_0000

MPU1

0x3400_0000

0x01F0_0000 0x3402_0000

0x0200_0000 0x3406_0000

0x01E0_0000

0x021C_0000

0x3406_8000

0x340B_8000

0x021F_0000 N/A

0x0220_0000 N/A

0x0231_0000

0x0232_0000

0x0233_0000

0x0235_0000

0x0240_0000 N/A

0x0250_0000 N/A

0x0253_0000 N/A

0x0260_0000 N/A

0x0262_0000 N/A

N/A

MPU2

0x02A0_0000

0x02A2_0000

0x02A4_0000

0x02A6_0000

0x02A6_8000

0x02A6_9000

0x02A6_A000

0x02A6_B000

0x02A6_C000

0x02A6_E000

0x02A8_0000

0x02A9_0000

0x02AA_0000

0x02AA_8000

0x02AB_0000

0x02AB_8000

N/A

MPU3

0x0264_0000

N/A

MPU4

0x7000_0000

0x7100_0000

0x7200_0000

0x7300_0000

0x7400_0000

0x7500_0000

0x7600_0000

0x7700_0000

0x7800_0000

0x7900_0000

0x7A00_0000

0x7B00_0000

0x7C00_0000

0x7D00_0000

0x7E00_0000

0x7F00_0000

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 180

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)

The Programmable Address End Register holds the end address for the range. This register is writeable by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also writeable only by a secure entity.

The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field in MPSAR and MPEAR

Figure 7-29 Programmable Range n End Address Register (PROGn_MPEAR)

END_ADDR

R/W

Legend: R = Read only; R/W = Read/Write

10 9

Reserved

Table 7-55 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions

Bit

31 – 10

Field

END_ADDR

9 – 0 Reserved

End of Table 7-55

Description

End address for range n.

Reserved and these bits always read as 3FFh.

Table 7-56 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values

Register

PROG0_MPEAR

PROG1_MPEAR

PROG2_MPEAR

PROG3_MPEAR

PROG4_MPEAR

PROG5_MPEAR

PROG6_MPEAR

PROG7_MPEAR

PROG8_MPEAR

PROG9_MPEAR

PROG10_MPEAR

PROG11_MPEAR

PROG12_MPEAR

PROG13_MPEAR

PROG14_MPEAR

PROG15_MPEAR

End of Table 7-56

MPU0

0x01D8_007F

0x01F7_FFFF

0x0209_FFFF

0x01EB_FFFF

0x021E_0C3F

0x021F_7FFF

0x0227_007F

0x0231_03FF N/A

0x0232_03FF N/A

0x0233_03FF

0x0235_0FFF

N/A

0x0245_3FFF N/A

0x0252_03FF N/A

0x0255_03FF

0x0260_BFFF

N/A

0x0262_07FF N/A

MPU1

0x3401_FFFF

0x3405_FFFF

0x3406_7FFF

0x340B_7FFF

0x340B_FFFF

N/A

MPU2

0x02A1_FFFF

0x02A3_FFFF

0x02A5_FFFF

0x02A6_7FFF

0x02A6_8FFF

0x02A6_9FFF

0x02A6_AFFF

0x02A6_BFFF

0x02A6_DFFF

0x02A6_FFFF

0x02A8_FFFF

0x02A9_FFFF

0x02AA_7FFF

0x02AA_FFFF

0x02AB_7FFF

0x02AB_FFFF

N/A

MPU3

0x0264_07FF

N/A

MPU4

0x70FF_FFFF

0x71FF_FFFF

0x72FF_FFFF

0x73FF_FFFF

0x74FF_FFFF

0x75FF_FFFF

0x76FF_FFFF

0x77FF_FFFF

0x78FF_FFFF

0x79FF_FFFF

0x7AFF_FFFF

0x7BFF_FFFF

0x7CFF_FFFF

0x7DFF_FFFF

0x7EFF_FFFF

0x7FFF_FFFF

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

The Programmable Address Memory Protection Page Attribute Register holds the permissions for the region. This register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also only writeable by a non-debug secure entity. The NS bit is writeable only by a non-debug secure entity. For debug accesses the register is writeable only when NS = 1 or EMU = 1.

Figure 7-30 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

Reserved

26 25 24 23 22 21 20 19

AID15 AID14 AID13 AID12 AID11 AID10 AID9

R/W R/W R/W R/W R/W R/W R/W

AID8

R/W

AID7

R/W

AID6

R/W

AID5

R/W

AID4

AID3

AID2

AID1

AID0

R/W R/W R/W R/W R/W

Legend: R = Read only; R/W = Read/Write

AIDX

R/W

Reserved

R/W

EMU

R/W

Table 7-57

Bit

31 – 26

AID9

AID8

AID7

AID6

Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions

(Part 1 of 2)

Field

Reserved

AID15

AID14

AID13

AID12

AID11

AID10

Description

Reserved. These bits will always reads as 0.

Controls access from ID = 15

0 = Access denied.

1 = Access granted.

Controls access from ID = 14

0 = Access denied.

1 = Access granted.

Controls access from ID = 13

0 = Access denied.

1 = Access granted.

Controls access from ID = 12

0 = Access denied.

1 = Access granted.

Controls access from ID = 11

0 = Access denied.

1 = Access granted.

Controls access from ID = 10

0 = Access denied.

1 = Access granted.

Controls access from ID = 9

0 = Access denied.

1 = Access granted.

Controls access from ID = 8

0 = Access denied.

1 = Access granted.

Controls access from ID = 7

0 = Access denied.

1 = Access granted.

Controls access from ID = 6

0 = Access denied.

1 = Access granted.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 182

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-57 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions

(Part 2 of 2) www.ti.com

Bit

Field

AID5

AID4

AID3

AID2

AID1

AID0

AIDX

Reserved

EMU

Description

Controls access from ID = 5

0 = Access denied.

1 = Access granted.

Controls access from ID = 4

0 = Access denied.

1 = Access granted.

Controls access from ID = 3

0 = Access denied.

1 = Access granted.

Controls access from ID = 2

0 = Access denied.

1 = Access granted.

Controls access from ID = 1

0 = Access denied.

1 = Access granted.

Controls access from ID = 0

0 = Access denied.

1 = Access granted.

Controls access from ID > 15

0 = Access denied.

1 = Access granted.

Always reads as 0.

Non-secure access permission

0 = Only secure access allowed.

1 = Non-secure access allowed.

Emulation (debug) access permission. This bit is ignored if NS = 1

0 = Debug access not allowed.

1 = Debug access allowed.

Supervisor Read permission

0 = Access not allowed.

1 = Access allowed.

Supervisor Write permission

0 = Access not allowed.

1 = Access allowed.

Supervisor Execute permission

0 = Access not allowed.

1 = Access allowed.

User Read permission

0 = Access not allowed.

1 = Access allowed

User Write permission

0 = Access not allowed.

1 = Access allowed.

User Execute permission

0 = Access not allowed.

1 = Access allowed.

End of Table 7-571

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-58 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values

Register

PROG0_MPPA

PROG1_MPPA

PROG2_MPPA

PROG3_MPPA

PROG4_MPPA

PROG5_MPPA

PROG6_MPPA

PROG7_MPPA

PROG8_MPPA

PROG9_MPPA

PROG10_MPPA

PROG11_MPPA

PROG12_MPPA

PROG13_MPPA

PROG14_MPPA

PROG15_MPPA

End of Table 7-58

MPU0

0x03FF_FCB6

0x03FF_FC80

0x03FF_FCB6

0x03FF_FCB4

0x03FF_FCB6

0x03FF_FCB4

0x03FF_FCB6

0x03FF_FCB4

N/A

MPU1

0x03FF_FC80

0x000F_FCB6

0x03FF_FCB4

0x03FF_FC80

0x03FF_FCB6

N/A

MPU2

0x03FF_FCA4

0x000F_FCB6

0x03FF_FCB4

0x03FF_FCA4

0x03FF_FCB4

0x03FF_FCB6

N/A

MPU3

0x0003_FCB6

N/A

MPU3

0x03FF_FCB6

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 184

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.10 DDR3 Memory Controller

The 32-bit DDR3 Memory Controller bus of the TMS320C6655/57 is used to interface to

JEDEC-standard-compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus with any other types of peripherals.

7.10.1 DDR3 Memory Controller Device-Specific Information

The TMS320C6655/57 includes one 32-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 Mega transfers per second (MTS), 1033 MTS, and 1333 MTS.

Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit or 32-bit interface.

The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3

SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the interface:

• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)

• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)

• 32-bit: Two 16-bit SDRAMs

• 32-bit: Four 8-bit SDRAMs

• 16-bit: One 16-bit SDRAM

• 16-bit: Two 8-bit SDRAM

The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as

C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible

DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.

A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes, before signaling to master B that the message is ready, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

Perform the required write to DDR3 memory space.

Perform a dummy write to the DDR3 memory controller module ID and revision register.

Perform a dummy read from the DDR3 memory controller module ID and revision register.

Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.10.2 DDR3 Memory Controller Electrical Data/Timing

The KeyStone DSP DDR3 Implementation Guidelines in

electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

Note—

TI supports

only designs that follow the board design guidelines outlined in the application report.

7.11 I

C Peripheral

The inter-integrated circuit (I

C) module provides an interface between DSP and other devices compliant with

Philips Semiconductors Inter-IC bus (I

C bus) specification version 2.1 and connected by way of an I

C bus.

External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I

C module.

7.11.1 I

C Device-Specific Information

The TMS320C6655/57 device includes an I

C peripheral module.

Note—

When using the I

C module, ensure there are external pullup resistors on the SDA and SCL pins.

The I

C modules on the C6655/57 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface.

The I

C port is compatible with Philips I

C specification revision 2.1 (January 2000) and supports:

• Fast mode up to 400 Kbps (no fail-safe I/O buffers)

• Noise filter to remove noise 50 ns or less

• 7-bit and 10-bit device addressing modes

• Multi-master (transmit/receive) and slave (transmit/receive) functionality

• Events: DMA, interrupt, or polling

• Slew-rate limited open-drain output buffers

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 186

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-31

shows a block diagram of the I

C module.

Figure 7-31 I

C Module Block Diagram

Clock

Prescale

I CPSC

I C Clock

SCL

Noise

Filter

I C Data

SDA

Noise

Filter

Bit Clock

Generator

I CCLKL

Transmit

I CXSR

Transmit

Shift

I CDXR

Transmit

Buffer

Peripheral Clock

(CPU/6)

Control

I COAR

I CSAR

Own

Address

Slave

Address

I CEMDR

Mode

Data

Count

Extended

Mode

Receive

I CDRR

I CRSR

Receive

Buffer

Receive

Shift

Interrupt/DMA

I CIMR

I CSTR

I CIVR

Interrupt

Mask/Status

Interrupt

Status

Interrupt

Vector www.ti.com

Shading denotes control/status registers.

7.11.2 I

C Peripheral Register Description(s)

Table 7-59 I

C Registers (Part 1 of 2)

Hex Address Range

0253 0000

0253 0004

0253 0008

0253 000C

0253 0010

0253 0014

0253 0018

0253 001C

0253 0020

0253 0024

0253 0028

0253 002C

0253 0030

Register

ICOAR

ICIMR

ICSTR

ICCLKL

ICCLKH

ICCNT

ICDRR

ICSAR

ICDXR

ICMDR

ICIVR

ICEMDR

ICPSC

Register Name

C Own Address Register

C Interrupt Mask/Status Register

C Interrupt Status Register

C Clock Low-Time Divider Register

C Clock High-Time Divider Register

C Data Count Register

C Data Receive Register

C Slave Address Register

C Data Transmit Register

C Mode Register

C Interrupt Vector Register

C Extended Mode Register

C Prescaler Register

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-59 I

C Registers (Part 2 of 2)

Hex Address Range

0253 0034

0253 0038

0253 003C - 0253 007F

End of Table 7-59

Register

ICPID1

ICPID2

Register Name

C Peripheral Identification Register 1 [Value: 0x0000 0105]

C Peripheral Identification Register 2 [Value: 0x0000 0005]

Reserved

7.11.3 I

C Electrical Data/Timing

7.11.3.1 Inter-Integrated Circuits (I

C) Timing

Table 7-60

(see Figure 7-32 )

C Timing Requirements

(1)

No.

1 t c(SCL)

3 t t su(SCLH-SDAL) h(SDAL-SCLL)

Cycle time, SCL

Setup time, SCL high before SDA low (for a repeated START condition)

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

Standard Mode

Min

4.7

Max

Fast Mode

Min

2.5

0.6

Max Units

μs

4 t w(SCLL)

5 t w(SCLH)

9 t r(SDA)

10 t r(SCL)

11 t f(SDA)

12 t f(SCL)

Pulse duration, SCL low

Pulse duration, SCL high

6 t su(SDAV-SCLH)

Setup time, SDA valid before SCL high

7 t h(SCLL-SDAV)

Hold time, SDA valid after SCL low (For I

C bus devices)

8 t w(SDAH)

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

4.7

250

(3)

4.7

3.45

100

1.3

0.6

(2)

(3)

1.3

1000 20 + 0.1C

(5)

1000 20 + 0.1C

300 20 + 0.1C

300 20 + 0.1C

0.6

0.9

(4)

300

μs

μs ns

μs

μs ns ns ns ns

13 t su(SCLH-SDAH)

Setup time, SCL high before SDA high (for STOP condition)

14 t w(SP)

15 C

Figure 7-36 , Figure 7-37 , Figure 7-38

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

End of Table 7-60

400

0 50

400

μs ns pF

1 The I

C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down

2 A Fast-mode I

SDA line t r

C-bus™ device can be used in a Standard-mode I

max + t su(SDA-SCLH)

C-bus™ system, but the requirement tsu(SDA-SCLH)

≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the

= 1000 + 250 = 1250 ns (according to the Standard-mode I

C-Bus Specification) before the SCL line is released.

3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V

IHmin of SCL.

of the SCL signal) to bridge the undefined region of the falling edge

4 The maximum t h(SDA-SCLL)

has only to be met if the device does not stretch the low period [t w(SCLL)

] of the SCL signal.

5 C b

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 188

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-32 I

C Receive Timings

SDA

SCL

Stop Start Repeated

Start

Table 7-61

(see Figure 7-33 )

C Switching Characteristics

(1)

No.

16 t c(SCL)

18 t t su(SCLH-SDAL) h(SDAL-SCLL)

Parameter

Cycle time, SCL

Setup time, SCL high to SDA low (for a repeated START condition)

Hold time, SDA low after SCL low (for a START and a repeated

START condition)

19 t w(SCLL)

20 t w(SCLH)

21 t d(SDAV-SDLH)

Pulse duration, SCL low

Pulse duration, SCL high

22 t v(SDLL-SDAV)

23 t w(SDAH)

24 t r(SDA)

25 t r(SCL)

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low (For I

C bus devices)

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

Rise time, SCL

26 t f(SDA)

27 t f(SCL)

Fall time, SDA

Fall time, SCL

28 t d(SCLH-SDAH)

Delay time, SCL high to SDA high (for STOP condition)

29 C p

Capacitance for each I

C pin

End of Table 7-61

1 C b

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Standard Mode

Min Max

4.7

250

4.7

1000

300

Stop

www.ti.com

Fast Mode

Min

2.5

0.6

Max Unit

ms ms

0.6

1.3

0.6

100

1.3

20 + 0.1C

20 + 0.1C

20 + 0.1C

20 + 0.1C

0.6

ms ms ms ns

0.9

ms ms

300 ns

10 pF

Submit Documentation Feedback

www.ti.com

Figure 7-33 I

C Transmit Timings

SDA

SCL

Stop Start

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Repeated

Start

Stop

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 190

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.12 SPI Peripheral

The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot. The SPI module on the C6655/57 is supported only in master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander.

7.12.1 SPI Electrical Data/Timing

7.12.1.1 SPI Timing

Table 7-62

See

Figure 7-34

)

SPI Timing Requirements

No.

7 tsu(SDI-SPC) tsu(SDI-SPC) tsu(SDI-SPC) tsu(SDI-SPC)

8 th(SPC-SDI) th(SPC-SDI)

8 th(SPC-SDI)

End of Table 7-62

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1

Min

Max Unit

ns ns ns ns ns ns ns ns

Table 7-63 SPI Switching Characteristics (Part 1 of 2)

(See Figure 7-34 and Figure 7-35

)

No.

6 tc(SPC) tw(SPCH) tw(SPCL) td(SDO-SPC) td(SDO-SPC) td(SDO-SPC) td(SDO-SPC) td(SPC-SDO) td(SPC-SDO) td(SPC-SDO) td(SPC-SDO) toh(SPC-SDO) toh(SPC-SDO)

Parameter

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

Cycle Time, SPICLK, All Master Modes 3*P2

(1)

Min

Pulse Width High, SPICLK, All Master Modes

Pulse Width Low, SPICLK, All Master Modes

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.

Polarity = 0, Phase = 0.

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.

Polarity = 0, Phase = 1.

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK

Polarity = 1, Phase = 0

0.5*tc - 1

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK

Polarity = 1, Phase = 1

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on

SPICLK. Polarity = 0 Phase = 0

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 0 Phase = 1

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 1 Phase = 0

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 1 Phase = 1

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 0

0.5*tc - 2

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 1

0.5*tc - 2

Max Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-63 SPI Switching Characteristics (Part 2 of 2)

(See Figure 7-34 and Figure 7-35 )

No.

6 toh(SPC-SDO)

19 td(SCS-SPC)

20 td(SPC-SCS)

20 td(SPC-SCS) tw(SCSH)

Parameter

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 0

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 1

Min

0.5*tc - 2

Max Unit

ns ns

Additional SPI Master Timings — 4 Pin Mode with Chip Select Option

Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 0

Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 1

2*P2 - 5 2*P2 + 5 ns

0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns

Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 0

Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 1

2*P2 - 5 2*P2 + 5 ns

0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns

1*P2 - 5 1*P2 + 5 ns Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0

Phase = 0

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0

Phase = 1

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1

Phase = 0

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1

Phase = 1

Minimum inactive time on SPISCS[n] pin between two transfers when

SPISCS[n] is not held using the CSHOLD feature.

0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns

1*P2 - 5

0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns

2*P2 - 5

1*P2 + 5 ns ns

End of Table 7-63

1 P2 = 1/SYSCLK7

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 192

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-34 SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

2 3

SPICLK

SPIDOUT

MO(1)

SPIDIN

MO(0)

MI(0)

MI(1)

MASTER MODE

POLARITY = 0 PHASE = 0

MO(n−1)

MI(n−1)

MO(n)

MI(n) www.ti.com

SPICLK

SPIDOUT

SPIDIN

SPICLK

SPIDOUT

SPIDIN

MASTER MODE

POLARITY = 0 PHASE = 1

MO(0)

MI(0)

MO(1)

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

MO(0)

MI(0)

MO(1)

MI(1)

MASTER MODE

POLARITY = 1 PHASE = 0

MO(n−1)

MI(n−1)

MO(n)

MI(n)

MASTER MODE

POLARITY = 1 PHASE = 1

SPICLK

SPIDOUT

SPIDIN

MO(0)

MI(0)

MO(1)

MI(1)

MO(n−1)

MI(n−1)

Figure 7-35

SPICLK

SPIDOUT

SPIDIN

SPISCSx

SPI Additional Timings for 4 Pin Master Mode with Chip Select Option

MASTER MODE 4 PIN WITH CHIP SELECT

19 20

MO(0)

MI(0)

MO(1)

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

MO(n)

MI(n)

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.13 HyperLink Peripheral

The devices include the HyperLink bus for companion chip/die interfaces. This is a four-lane SerDes interface designed to operate at up to 10 Gbaud per lane. The supported data rates include 1.25 Gbaud, 3.125 Gbaud,

6.25 Gbaud, and 10 Gbaud. The interface is used to connect with external accelerators. The HyperLink links must be connected with DC coupling.

The interface includes the Serial Station Management Interfaces used to send power management and flow messages between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.

7.13.1 HyperLink Device-Specific Interrupt Event

The HyperLink has 64 input events. Events 0 to 31 come from the chip-level interrupt controller and events 32 to 63 are from queue-pending signals from the Queue Manager to monitor some of the transmission queue status.

Table 7-64

Event Number

HyperLink Events (Part 1 of 2)

CIC2_OUT24

CIC2_OUT25

CIC2_OUT26

CIC2_OUT27

CIC2_OUT28

CIC2_OUT29

CIC2_OUT30

CIC2_OUT31

CIC2_OUT32

CIC2_OUT33

CIC2_OUT34

CIC2_OUT35

CIC2_OUT36

CIC2_OUT37

CIC2_OUT38

Event

CIC2_OUT8

CIC2_OUT9

CIC2_OUT10

CIC2_OUT11

CIC2_OUT12

CIC2_OUT13

CIC2_OUT14

CIC2_OUT15

CIC2_OUT16

CIC2_OUT17

CIC2_OUT18

CIC2_OUT19

CIC2_OUT20

CIC2_OUT21

CIC2_OUT22

CIC2_OUT23

Event Description

Interrupt Controller output

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 194

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-64 HyperLink Events (Part 2 of 2)

Event Number

End of Table 7-64

Event

CIC2_OUT39

QM_INT_PEND_864

QM_INT_PEND_865

QM_INT_PEND_866

QM_INT_PEND_867

QM_INT_PEND_868

QM_INT_PEND_869

QM_INT_PEND_870

QM_INT_PEND_871

QM_INT_PEND_872

QM_INT_PEND_873

QM_INT_PEND_874

QM_INT_PEND_875

QM_INT_PEND_876

QM_INT_PEND_877

QM_INT_PEND_878

QM_INT_PEND_879

QM_INT_PEND_880

QM_INT_PEND_881

QM_INT_PEND_882

QM_INT_PEND_883

QM_INT_PEND_884

QM_INT_PEND_885

QM_INT_PEND_886

QM_INT_PEND_887

QM_INT_PEND_888

QM_INT_PEND_889

QM_INT_PEND_890

QM_INT_PEND_891

QM_INT_PEND_892

QM_INT_PEND_893

QM_INT_PEND_894

QM_INT_PEND_895

Event Description

Interrupt Controller output

Queue manager pend event

www.ti.com

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.13.2 HyperLink Electrical Data/Timing

The tables and figure below describe the timing requirements and switching characteristics of HyperLink peripheral.

Table 7-65 HyperLink Peripheral Timing Requirements

See

No.

2 tc(MCMTXFLCLK) tw(MCMTXFLCLKH) tw(MCMTXFLCLKL) tsu(MCMTXFLDAT-MCMTXFLCLKH) th(MCMTXFLCLKH-MCMTXFLDAT) tsu(MCMTXFLDAT-MCMTXFLCLKL) th(MCMTXFLCLKL-MCMTXFLDAT) tc(MCMRXPMCLK) tw(MCMRXPMCLK) tw(MCMRXPMCLK)

FL Interface

Clock period - MCMTXFLCLK (C1)

High pulse width - MCMTXFLCLK

Low pulse width - MCMTXFLCLK

Setup time - MCMTXFLDAT valid before MCMTXFLCLK high

Hold time - MCMTXFLDAT valid after MCMTXFLCLK high

Setup time - MCMTXFLDAT valid before MCMTXFLCLK low

Hold time - MCMTXFLDAT valid after MCMTXFLCLK low

PM Interface

Clock period - MCMRXPMCLK (C3)

High pulse width - MCMRXPMCLK

Low pulse width - MCMRXPMCLK tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup time - MCMRXPMDAT valid before MCMRXPMCLK high

6 th(MCMRXPMCLKH-MCMRXPMDAT) tsu(MCMRXPMDAT-MCMRXPMCLKL)

Hold time - MCMRXPMDAT valid after MCMRXPMCLK high

Setup time - MCMRXPMDAT valid before MCMRXPMCLK low

7 th(MCMRXPMCLKL-MCMRXPMDAT) Hold time - MCMRXPMDAT valid after MCMRXPMCLK low

End of Table 7-65

Min Max Unit

6.4

0.4*C1 0.6*C1 ns

1 ns

1 ns ns ns

6.4

0.4*C3 0.6*C3 ns

1 ns

1 ns ns ns

Table 7-66 HyperLink Peripheral Switching Characteristics

See

Figure 7-36 , Figure 7-37 , Figure 7-38

No.

tc(MCMRXFLCLK) tw(MCMRXFLCLKH)

Parameter

FL Interface

Clock period - MCMRXFLCLK (C2)

High pulse width - MCMRXFLCLK tw(MCMRXFLCLKL) Low pulse width - MCMRXFLCLK tosu(MCMRXFLDAT-MCMRXFLCLKH) Setup time - MCMRXFLDAT valid before MCMRXFLCLK high

2 toh(MCMRXFLCLKH-MCMRXFLDAT) Hold time - MCMRXFLDAT valid after MCMRXFLCLK high tosu(MCMRXFLDAT-MCMRXFLCLKL) Setup time - MCMRXFLDAT valid before MCMRXFLCLK low toh(MCMRXFLCLKL-MCMRXFLDAT) Hold time - MCMRXFLDAT valid after MCMRXFLCLK low

PM Interface

tc(MCMTXPMCLK) tw(MCMTXPMCLK) tw(MCMTXPMCLK)

Clock period - MCMTXPMCLK (C4)

High pulse width - MCMTXPMCLK

Low pulse width - MCMTXPMCLK tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup time - MCMTXPMDAT valid before MCMTXPMCLK high

4 toh(MCMTXPMCLKH-MCMTXPMDAT) tosu(MCMTXPMDAT-MCMTXPMCLKL)

Hold time - MCMTXPMDAT valid after MCMTXPMCLK high

Setup time - MCMTXPMDAT valid before MCMTXPMCLK low

5 toh(MCMTXPMCLKL-MCMTXPMDAT) Hold time - MCMTXPMDAT valid after MCMTXPMCLK low

End of Table 7-66

Min Max Unit

6.4

0.4*C2 0.6*C2 ns

0.25*C2-0.4

ns ns ns

6.4

0.4*C4 0.6*C4 ns

0.25*C4-0.4

ns ns ns

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 196

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-36 HyperLink Station Management Clock Timing

Figure 7-37

2 3

HyperLink Station Management Transmit Timing

4 5

MCMTX<xx>CLK

MCMTX<xx>DAT

<xx> represents the interface that is being used: PM or FL

Figure 7-38 HyperLink Station Management Receive Timing

6 7

MCMRX<xx>CLK

MCMRX<xx>DAT

<xx> represents the interface that is being used: PM or FL

4 5

6 7

www.ti.com

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.14 UART Peripheral

The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and a

UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550 asynchronous communications element, which, in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate

FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter

(UART) for KeyStone Devices User Guide in

Table 7-67 UART Timing Requirements

(see Figure 7-39 and Figure 7-40 )

No.

6 tw(RXSTART) tw(RXH) tw(RXL) tw(RXSTOP1) tw(RXSTOP15) tw(RXSTOP2)

Receive Timing

Pulse width, receive start bit

Pulse width, receive data/parity bit high

Pulse width, receive data/parity bit low

Pulse width, receive stop bit 1

Pulse width, receive stop bit 1.5

Pulse width, receive stop bit 2

Autoflow Timing Requirements

Delay time, CTS asserted to START bit transmit 8 td(CTSL-TX)

End of Table 7-67

1 U = UART baud time = 1/programmed baud rate

2 P = 1/SYSCLK7

Min

0.96U

(1)

0.96U

1.05U

1.5*(0.96U) 1.5*(1.05U)

2*(0.96U) 2*(1.05U)

(2)

Max

Unit

ns ns ns ns ns ns ns

Figure 7-39

RXD

UART Receive Timing Waveform

Stop/Idle

Start Bit 0

Bit 1 Bit N-1 Bit N

Parity

Stop Idle Start

Figure 7-40

TXD

UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform

Bit N-1 Bit N Stop Start Bit 0

CTS

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 198

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-68 UART Switching Characteristics

(See Figure 7-41 and Figure 7-42

)

No.

3 tw(TXSTART) tw(TXH) tw(TXL) tw(TXSTOP1) tw(TXSTOP15) tw(TXSTOP2)

Parameter

Transmit Timing

Pulse width, transmit start bit

Pulse width, transmit data/parity bit high

Pulse width, transmit data/parity bit low

Pulse width, transmit stop bit 1

Pulse width, transmit stop bit 1.5

Pulse width, transmit stop bit 2

Autoflow Timing Requirements

Delay time, STOP bit received to RTS deasserted 7 td(RX-RTSH)

End of Table 7-68

1 U = UART baud time = 1/programmed baud rate

2 P = 1/SYSCLK7

Figure 7-41

TXD

UART Transmit Timing Waveform

1 2

Stop/Idle

Start Bit 0 Bit 1 Bit N-1 Bit N

Parity

Figure 7-42 UART RTS (Request-to-Send Output) — Autoflow Timing Waveform

RXD Bit N-1 Bit N Stop

CTS

Stop Idle

Start

www.ti.com

Min

(2)

Max

(1)

- 2

U - 2

U + 2

1.5 * (U - 2) 1.5 * ('U + 2)

2 * (U - 2) 2 * ('U + 2) ns ns ns ns ns ns

Unit

Start

7.15 PCIe Peripheral

The two-lane PCI express (PCIe) module on the device provides an interface between the DSP and other

PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed data transfer at rates of 5.0 GBaud per lane on the serial links. For more information, see the Peripheral Component

Interconnect Express (PCIe) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64. The PCIe electrical requirements are fully specified in the PCI Express Base Specification Revision 2.0

of PCI-SIG. TI has performed the simulation and system characterization to ensure all PCIe interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.16 EMIF16 Peripheral

The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide in

7.16.1 EMIF16 Electrical Data/Timing

Table 7-69 EMIF16 Asynchronous Memory Timing Requirements

(see Figure 7-43 and Figure 7-44 )

(1)

(Part 1 of 2)

No.

Min Max

t t t w d d

(WAIT)

(WAIT-WEH)

(WAIT-OEH)

General Timing

Pulse duration, WAIT assertion and deassertion minimum time

Setup time, WAIT asserted before WE high

Setup time, WAIT asserted before OE high

Read Timing

EMIF read cycle time when ew = 0, meaning not in extended wait mode

4E + 3

4E + 3 t t

(CEL)

EMIF read cycle time when ew =1, meaning extended wait mode enabled

(RS+RST+RH+3)

*E-3

(RS+RST+RH+3)

*E-3

(RS+RST+RH+3)

*E+3

(RS+RST+RH+3)

*E+3 t osu

(CEL-OEL) t oh

(OEH-CEH) t osu

(CEL-OEL) t oh

(OEH-CEH) t osu

(BAV-OEL) t oh

(OEH-BAIV) t osu

(AV-OEL) t oh

(OEH-AIV)

Output setup time from CE low to OE low. SS = 0, not in select strobe mode

Output hold time from OE high to CE high. SS = 0, not in select strobe mode

Output setup time from CE low to OE low in select strobe mode, SS = 1

Output hold time from OE high to CE high in select strobe mode, SS = 1

Output setup time from BA valid to OE low

Output hold time from OE high to BA invalid

Output setup time from A valid to OE low

Output hold time from OE high to A invalid t w

(OEL) t w

(OEL)

OE active time low, when ew = 0. Extended wait mode is disabled.

OE active time low, when ew = 1. Extended wait mode is enabled.

t d

(WAITH-OEH) Delay time from WAIT deasserted to OE# high t su

(D-OEH) Input setup time from D valid to OE high t h

(OEH-D) Input hold time from OE high to D invalid

Write Timing

t t c c

(CEL)

(CEL) t osu

CEL-WEL) t oh

(WEH-CEH) t osu

CEL-WEL) t oh

(WEH-CEH)

Output setup time from CE low to WE low. SS = 0, not in select strobe mode

Output hold time from WE high to CE high. SS = 0, not in select strobe mode

Output setup time from CE low to WE low in select strobe mode, SS = 1

Output hold time from WE high to CE high in select strobe mode, SS = 1 t osu

(RNW-WEL) Output setup time from RNW valid to WE low t oh

(WEH-RNW) Output hold time from WE high to RNW invalid t osu

(BAV-WEL) t oh

(WEH-BAIV)

Output setup time from BA valid to WE low

Output hold time from WE high to BA invalid

Output setup time from A valid to WE low t osu

(AV-WEL) t oh

(WEH-AIV) t w

(WEL)

Output hold time from WE high to A invalid

WE active time low, when ew = 0. Extended wait mode is disabled.

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RST+1) * E - 3

0.5

EMIF write cycle time when ew = 0, meaning not in extended wait mode (WS+WST+WH+

TA+4)*E-3

EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WH+

TA+4)*E-3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WST+1) * E - 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RST+1) * E + 3

4E + 3

(WS+WST+WH+

TA+4)*E+3

(WS+WST+WH+

TA+4)*E+3

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 200

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-69 EMIF16 Asynchronous Memory Timing Requirements

(see Figure 7-43 and Figure 7-44 )

(1)

(Part 2 of 2)

No.

26 t w

(WEL) t osu

(DV-WEL)

WE active time low, when ew = 1. Extended wait mode is enabled.

Output setup time from D valid to WE low

27 t oh

(WEH-DIV) Output hold time from WE high to D invalid

25 t d

(WAITH-WEH) Delay time from WAIT deasserted to WE# high

End of Table 7-69

1 E = 1/SYSCLK7

Figure 7-43 EMIF16 Asynchronous Memory Read Timing Diagram

EM_CE[3:0]

EM_R/W

EM_BA[1:0]

EM_A[21:0]

EM_OE

EM_D[15:0]

EM_WE

Figure 7-44 EMIF16 Asynchronous Memory Write Timing Diagram

EM_CE[3:0]

EM_R/W

EM_BA[1:0]

EM_A[21:0]

EM_WE

EM_D[15:0]

EM_OE

www.ti.com

Min

(WST+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

Max

4E + 3

Unit

ns ns ns ns

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Figure 7-45 EMIF16 EM_WAIT Read Timing Diagram

Strobe

EM_CE[3:0]

Setup

EM_BA[1:0]

EM_A[21:0]

EM_D[15:0]

EM_OE

EM_WAIT

Asserted

Extended Due to EM_WAIT

EM_WAIT

Asserted

Figure 7-46 EMIF16 EM_WAIT Write Timing Diagram

Setup Strobe

EM_CE[3:0]

EM_BA[1:0]

EM_A[21:0]

EM_D[15:0]

EM_WE

Deasserted

Extended Due to EM_WAIT

Deasserted

Strobe Hold

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 202

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.17 Ethernet Media Access Controller (EMAC)

The Ethernet media access controller (EMAC) module provides an efficient interface between the TMS320C6655/57

DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and

100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple Access with

Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviating from this standard, the EMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

The EMAC control module is the main interface between the device core processor, the MDIO module, and the

EMAC module. The relationship between these three components is shown in Figure 7-47

. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC control module incorporates 8K bytes of internal RAM to hold EMAC buffer descriptors.

Figure 7-47 EMAC, MDIO, and EMAC Control Modules

Interrupt

Controller

Configuration Bus

Peripheral Bus

DMA Memory

Transfer Controller

EMAC/MDIO

Interrupt

EMAC Control Module

EMAC Module MDIO Module

Ethernet Bus

MDIO Bus

For more detailed information on the EMAC/MDIO, see Gigabit Ethernet (GbE) Subsystem for KeyStone Devices

User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

7.17.1 EMAC Device-Specific Information

The EMAC module on the device supports Serial Gigabit Media Independent Interface (SGMII). The SGMII interface conforms to version 1.8 of the industry standard specification.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.17.2 EMAC Peripheral Register Description(s)

The memory maps of the EMAC are shown in Table 7-70

through Table 7-75 .

Table 7-70 Ethernet MAC (EMAC) Control Registers (Part 1 of 3)

Hex Address

02C0 8000

02C0 8004

02C0 8008

02C0 800F

02C0 8010

02C0 8014

02C0 8018

02C0 801C

02C0 8020 - 02C0 807C

02C0 8080

02C0 8084

02C0 8088

02C0 808C

02C0 8090

02C0 8094

02C0 8098 - 02C0 819C

02C0 80A0

02C0 80A4

02C0 80A8

02C0 80AC

02C0 80B0

02C0 80B4

02C0 80B8

02C0 80BC

02C0 80C0 - 02C0 80FC

02C0 8100

02C0 8104

02C0 8108

02C0 810C

02C0 8110

02C0 8114

02C0 8118 - 02C0 811C

02C0 8120

02C0 8124

02C0 8128

02C0 812C

02C0 8130

02C0 8134

02C0 8138

02C0 813C

02C0 8140

Acronym

TXIDVER

TXCONTROL

TXTEARDOWN

RXIDVER

RXCONTROL

RXTEARDOWN

TXINTSTATRAW

TXINTSTATMASKED

TXINTMASKSET

TXINTMASKCLEAR

MACINVECTOR

MACEOIVECTOR

RXINTSTATRAW

RXINTSTATMASKED

RXINTMASKSET

RXINTMASKCLEAR

MACINTSTATRAW

MACINTSTATMASKED

MACINTMASKSET

MACINTMASKCLEAR

RXMBPENABLE

RXUNICASTSET

RXUNICASTCLEAR

RXMAXLEN

RXBUFFEROFFSET

RXFILTERLOWTHRESH

RX0FLOWTHRESH

RX1FLOWTHRESH

RX2FLOWTHRESH

RX3FLOWTHRESH

RX4FLOWTHRESH

RX5FLOWTHRESH

RX6FLOWTHRESH

RX7FLOWTHRESH

RX0FREEBUFFER

Register Name

Transmit Identification and Version Register

Transmit Control Register

Transmit Teardown register

Reserved

Receive Identification and Version Register

Receive Control Register

Receive Teardown Register

Reserved

Transmit Interrupt Status (Unmasked) Register

Transmit Interrupt Status (Masked) Register

Transmit Interrupt Mask Set Register

Transmit Interrupt Mask Clear Register

MAC Input Vector Register

MAC End of Interrupt Vector Register

Reserved

Receive Interrupt Status (Unmasked) Register

Receive Interrupt Status (Masked) Register

Receive Interrupt Mask Set Register

Receive Interrupt Mask Clear Register

MAC Interrupt Status (Unmasked) Register

MAC Interrupt Status (Masked) Register

MAC Interrupt Mask Set Register

MAC Interrupt Mask Clear Register

Reserved

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

Receive Unicast Enable Set Register

Receive Unicast Clear Register

Receive Maximum Length Register

Receive Buffer Offset Register

Receive Filter Low Priority Frame Threshold Register

Reserved

Receive Channel 0 Flow Control Threshold Register

Receive Channel 1 Flow Control Threshold Register

Receive Channel 2 Flow Control Threshold Register

Receive Channel 3 Flow Control Threshold Register

Receive Channel 4 Flow Control Threshold Register

Receive Channel 5 Flow Control Threshold Register

Receive Channel 6 Flow Control Threshold Register

Receive Channel 7 Flow Control Threshold Register

Receive Channel 0 Free Buffer Count Register

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 204

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-70 Ethernet MAC (EMAC) Control Registers (Part 2 of 3)

Hex Address

02C0 8144

02C0 8148

02C0 814C

02C0 8150

02C0 8154

02C0 8158

02C0 815C

02C0 8160

02C0 8164

02C0 8168

02C0 816C

02C0 8170

02C0 8174

02C0 81D0

02C0 81D4

02C0 81D8

02C0 81DC

02C0 81E0

02C0 81E4

02C0 81E8

02C0 81EC

02C0 8200 - 02C0 82FC

02C0 8300 - 02C0 84FC

02C0 8500

02C0 8504

02C0 8508

02C0 850C - 02C0 85FC

02C0 8600

02C0 8604

02C0 8608

02C0 860C

02C0 8610

02C0 8614

02C0 8618

02C0 861C

02C0 8620

02C0 8624

02C0 8628

02C0 862C

02C0 8630

02C0 8634

02C0 8638

02C0 863C

02C0 8640

MACSRCADDRHI

MACHASH1

MACHASH2

BOFFTEST

TPACETEST

RXPAUSE

TXPAUSE

MACADDRLO

MACADDRHI

MACINDEX

TX0HDP

TX1HDP

TX2HDP

Acronym

RX1FREEBUFFER

RX2FREEBUFFER

RX3FREEBUFFER

RX4FREEBUFFER

RX5FREEBUFFER

RX6FREEBUFFER

RX7FREEBUFFER

MACCONTROL

MACSTATUS

EMCONTROL

FIFOCONTROL

MACCONFIG

SOFTRESET

MACSRCADDRLO

TX3HDP

TX4HDP

TX5HDP

TX6HDP

TX7HDP

RX0HDP

RX1HDP

RX2HDP

RX3HDP

RX4HDP

RX5HDP

RX6HDP

RX7HDP

TX0CP

Register Name

Receive Channel 1 Free Buffer Count Register

Receive Channel 2 Free Buffer Count Register

Receive Channel 3 Free Buffer Count Register

Receive Channel 4 Free Buffer Count Register

Receive Channel 5 Free Buffer Count Register

Receive Channel 6 Free Buffer Count Register

Receive Channel 7 Free Buffer Count Register

MAC Control Register

MAC Status Register

Emulation Control Register

FIFO Control Register

MAC Configuration Register

Soft Reset Register

MAC Source Address Low Bytes Register

MAC Source Address High Bytes Register

MAC Hash Address Register 1

MAC Hash Address Register 2

Back Off Test Register

Transmit Pacing Algorithm Test Register

Receive Pause Timer Register

Transmit Pause Timer Register

See Table 7-71 ‘‘EMAC Statistics Registers’’

Reserved

MAC Address Low Bytes Register (used in Receive Address Matching)

MAC Address High Bytes Register (used in Receive Address Matching)

MAC Index Register

Reserved

Transmit Channel 0 DMA Head Descriptor Pointer Register

Transmit Channel 1 DMA Head Descriptor Pointer Register

Transmit Channel 2 DMA Head Descriptor Pointer Register

Transmit Channel 3 DMA Head Descriptor Pointer Register

Transmit Channel 4 DMA Head Descriptor Pointer Register

Transmit Channel 5 DMA Head Descriptor Pointer Register

Transmit Channel 6 DMA Head Descriptor Pointer Register

Transmit Channel 7 DMA Head Descriptor Pointer Register

Receive Channel 0 DMA Head Descriptor Pointer Register

Receive t Channel 1 DMA Head Descriptor Pointer Register

Receive Channel 2 DMA Head Descriptor Pointer Register

Receive t Channel 3 DMA Head Descriptor Pointer Register

Receive Channel 4 DMA Head Descriptor Pointer Register

Receive t Channel 5 DMA Head Descriptor Pointer Register

Receive Channel 6 DMA Head Descriptor Pointer Register

Receive t Channel 7 DMA Head Descriptor Pointer Register

Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register

www.ti.com

Submit Documentation Feedback

www.ti.com

Table 7-70 Ethernet MAC (EMAC) Control Registers (Part 3 of 3)

Hex Address

02C0 8644

02C0 8648

02C0 864C

02C0 8650

02C0 8654

02C0 8658

02C0 865C

02C0 8660

02C0 8664

02C0 8668

02C0 866C

02C0 8670

02C0 8674

02C0 8678

02C0 867C

02C0 8680 - 02C0 86FC

02C0 8700 - 02C0 877C

02C0 8780 - 02C0 8FFF

End of Table 7-70

Acronym

TX1CP

TX2CP

TX3CP

TX4CP

TX5CP

TX6CP

TX7CP

RX0CP

RX1CP

RX2CP

RX3CP

RX4CP

RX5CP

RX6CP

RX7CP

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Register Name

Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Reserved

Table 7-71 EMAC Statistics Registers (Part 1 of 2)

Hex Address

02C0 8200

02C0 8204

02C0 8208

02C0 820C

02C0 8210

Acronym

RXGOODFRAMES

RXBCASTFRAMES

RXMCASTFRAMES

RXPAUSEFRAMES

RXCRCERRORS

02C0 8214

02C0 8218

02C0 821C

02C0 8220

02C0 8224

02C0 8228

02C0 822C

02C0 8230

02C0 8234

02C0 8238

02C0 823C

02C0 8240

02C0 8244

02C0 8248

02C0 824C

02C0 8250

RXALIGNCODEERRORS

RXOVERSIZED

RXJABBER

RXUNDERSIZED

RXFRAGMENTS

RXFILTERED

RXQOSFILTERERED

RXOCTETS

TXGOODFRAMES

TXBCASTFRAMES

TXMCASTFRAMES

TXPAUSEFRAMES

TXDEFERED

TXCOLLISION

TXSINGLECOLL

TXMULTICOLL

Register Name

Good Receive Frames Register

Broadcast Receive Frames Register (Total number of Good Broadcast Frames Receive)

Multicast Receive Frames Register (Total number of Good Multicast Frames Received)

Pause Receive Frames Register

Receive CRC Errors Register (Total number of Frames Received with CRC Errors)

Receive Alignment/Code Errors register (Total number of frames received with alignment/code errors)

Receive Oversized Frames Register (Total number of Oversized Frames Received)

Receive Jabber Frames Register (Total number of Jabber Frames Received)

Receive Undersized Frames Register (Total number of Undersized Frames Received)

Receive Frame Fragments Register

Filtered Receive Frames Register

Received QOS Filtered Frames Register

Receive Octet Frames Register (Total number of Received Bytes in Good Frames)

Good Transmit Frames Register (Total number of Good Frames Transmitted)

Broadcast Transmit Frames Register

Multicast Transmit Frames Register

Pause Transmit Frames Register

Deferred Transmit Frames Register

Transmit Collision Frames Register

Transmit Single Collision Frames Register

Transmit Multiple Collision Frames Register

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 206

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-71 EMAC Statistics Registers (Part 2 of 2)

Hex Address

02C0 8254

02C0 8258

02C0 825C

02C0 8260

02C0 8264

02C0 8268

02C0 826C

02C0 8270

02C0 8274

02C0 8278

02C0 827C

02C0 8280

02C0 8284

02C0 8288

02C0 828C

02C0 8290 - 02C0 82FC

End of Table 7-71

Acronym

TXEXCESSIVECOLL

TXLATECOLL

TXUNDERRUN

TXCARRIERSENSE

TXOCTETS

FRAME64

FRAME65T127

FRAME128T255

FRAME256T511

FRAME512T1023

FRAME1024TUP

NETOCTETS

RXSOFOVERRUNS

RXMOFOVERRUNS

RXDMAOVERRUNS

Register Name

Transmit Excessive Collision Frames Register

Transmit Late Collision Frames Register

Transmit Under Run Error Register

Transmit Carrier Sense Errors Register

Transmit Octet Frames Register

Transmit and Receive 64 Octet Frames Register

Transmit and Receive 65 to 127 Octet Frames Register

Transmit and Receive 128 to 255 Octet Frames Register

Transmit and Receive 256 to 511 Octet Frames Register

Transmit and Receive 512 to 1023 Octet Frames Register

Transmit and Receive 1024 to 1518 Octet Frames Register

Network Octet Frames Register

Receive FIFO or DMA Start of Frame Overruns Register

Receive FIFO or DMA Middle of Frame Overruns Register

Receive DMA Start of Frame and Middle of Frame Overruns Register

Reserved

www.ti.com

Table 7-72 EMAC Descriptor Memory

Hex Address

02C0 A000 - 02C0 BFFF

End of Table 7-72

Acronym

Register Name

EMAC Descriptor Memory

Table 7-73 SGMII Control Registers

Hex Address

02C0 8900

02C0 8904

02C0 8910

02C0 8914

02C0 8918

02C0 891C

02C0 8920

02C0 8924 - 02C0 8948

End of Table 7-73

Acronym

IDVER

SOFT_RESET

CONTROL

STATUS

MR_ADV_ABILITY

MR_LP_ADV_ABILITY

Register Name

Identification and Version register

Software Reset Register

Control Register

Status Register

Advertised Ability Register

Reserved

Link Partner Advertised Ability Register

Reserved

Table 7-74 EMIC Control Registers (Part 1 of 2)

Hex Address

02C0 8A00

02C0 8A04

02C0 8A08

02C0 8A0C

02C0 8A10

02C0 8A14

Acronym

IDVER

SOFT_RESET

EM_CONTROL

INT_CONTROL

C0_RX_THRESH_EN

C0_RX_EN

207 Peripheral Information and Electrical Specifications

Register Name

Identification and Version register

Software Reset Register

Emulation Control Register

Interrupt Control Register

Receive Threshold Interrupt Enable Register for CorePac0

Receive Interrupt Enable Register for CorePac0

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-74 EMIC Control Registers (Part 2 of 2)

Hex Address

02C0 8A18

02C0 8A1C

02C0 8A10

02C0 8A14

02C0 8A18

02C0 8A1C

02C0 8A90

02C0 8A94

02C0 8A98

02C0 8A9C

02C0 8AA0

02C0 8AA4

02C0 8AA8

02C0 8AAC

02C0 8B10

02C0 8B14

02C0 8B18

02C0 8B1C

End of Table 7-74

Acronym

C0_TX_EN

C0_MISC_EN

C1_RX_THRESH_EN

C1_RX_EN

C1_TX_EN

C1_MISC_EN

C0_RX_THRESH_STAT

C0_RX_STAT

C0_TX_STAT

C0_MISC_STAT

C1_RX_THRESH_STAT

C1_RX_STAT

C1_TX_STAT

C1_MISC_STAT

C0_RX_IMAX

C0_TX_IMAX

C1_RX_IMAX

C1_TX_IMAX

Register Name

Transmit Interrupt Enable Register for CorePac0

Misc Interrupt Enable Register for CorePac0

Receive Threshold Interrupt Enable Register for CorePac1 (C6657 only)

Receive Interrupt Enable Register for CorePac1 (C6657 only)

Transmit Interrupt Enable Register for CorePac1 (C6657 only)

Misc Interrupt Enable Register for CorePac1 (C6657 only)

Receive Threshold Masked Interrupt Status Register for CorePac0

Receive Interrupt Masked Interrupt Status Register for CorePac0

Transmit Interrupt Masked Interrupt Status Register for CorePac0

Misc Interrupt Masked Interrupt Status Register for CorePac0

Receive Threshold Masked Interrupt Status Register for CorePac1 (C6657 only)

Receive Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)

Transmit Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)

Misc Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)

Receive Interrupts Per Millisecond for CorePac0

Transmit Interrupts Per Millisecond for CorePac0

Receive Interrupts Per Millisecond for CorePac1 (C6657 only)

Transmit Interrupts Per Millisecond for CorePac1 (C6657 only)

7.17.3 EMAC Electrical Data/Timing (SGMII)

The Hardware Design Guide for KeyStone Devices application report specifies a complete EMAC and SGMII interface solution for the C6655/57 as well as a list of compatible EMAC and SGMII devices. TI has performed the simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

Note—

TI supports

only designs that follow the board design guidelines outlined in the application report.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 208

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.18 Management Data Input/Output (MDIO) www.ti.com

The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the GbE switch subsystem, retrieve the negotiation results, and configure required parameters in the GbE switch subsystem module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. For more information, see the Gigabit Ethernet (GbE)

Subsystem for KeyStone Devices User Guide in

The EMAC control module is the main interface between the device core processor, the MDIO module, and the

EMAC module. The relationship between these three components is shown in Figure 7-47

For more detailed information on the EMAC/MDIO, see Gigabit Ethernet (GbE) Subsystem for KeyStone Devices

User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

7.18.1 MDIO Peripheral Registers

The memory map of the MDIO is shown in Table 7-75 .

Table 7-75 MDIO Registers

Hex Address

02C0 8800

02C0 8804

02C0 8808

02C0 880C

02C0 8810

02C0 8814

02C0 8818 - 02C0 881C

02C0 8820

02C0 8824

02C0 8828

02C0 882C

02C0 8830 - 02C0 887C

02C0 8880

02C0 8884

02C0 8888

02C0 888C

02C0 8890 - 02C0 8FFF

End of Table 7-75

Acronym

VERSION

CONTROL

ALIVE

LINK

LINKINTRAW

LINKINTMASKED

USERINTRAW

USERINTMASKED

USERINTMASKSET

USERINTMASKCLEAR

USERACCESS0

USERPHYSEL0

USERACCESS1

USERPHYSEL1

Register Name

MDIO Version Register

MDIO Control Register

MDIO PHY Alive Status Register

MDIO PHY Link Status Register

MDIO link Status Change Interrupt (unmasked) Register

MDIO link Status Change Interrupt (masked) Register

Reserved

MDIO User Command Complete Interrupt (Unmasked) Register

MDIO User Command Complete Interrupt (Masked) Register

MDIO User Command Complete Interrupt Mask Set Register

MDIO User Command Complete Interrupt Mask Clear Register

Reserved

MDIO User Access Register 0

MDIO User PHY Select Register 0

MDIO User Access Register 1

MDIO User PHY Select Register 1

Reserved

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.18.2 MDIO Timing

Table 7-76

See

Figure 7-48

MDIO Timing Requirements

No.

5 tc(MDCLK) tw(MDCLKH) tw(MDCLKL) tsu(MDIO-MDCLKH) th(MDCLKH-MDIO) tt(MDCLK)

End of Table 7-76

Cycle time, MDCLK

Pulse duration, MDCLK high

Pulse duration, MDCLK low

Setup time, MDIO data input valid before MDCLK high

Hold time, MDIO data input valid after MDCLK high

Transition time, MDCLK

Min

400

180

Max

Unit

ns ns ns ns ns ns

Figure 7-48 MDIO Input Timing

MDCLK

2 3

4 5

MDIO

(Input)

Table 7-77

See

Figure 7-49

MDIO Switching Characteristics

No.

6 td(MDCLKL-MDIO)

End of Table 7-77

Parameter

Delay time, MDCLK low to MDIO data output valid

Figure 7-49 MDIO Output Timing

MDCLK

MDIO

(Ouput)

Min Max

100

Unit

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 210

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.19 Timers

The timers can be used to: time events, count events, generate pulses, interrupt the CPU and send synchronization events to the EDMA3 channel controller.

7.19.1 Timers Device-Specific Information

The TMS320C6655/57 devices have eight 64-bit timers in total. On the C6657, Timer0 and Timer1 are dedicated to each of the two CorePacs as a watchdog timer and can also be used as general-purpose timers. Each of the other six timers can also be configured as a general-purpose timer only, with each timer programmed as a 64-bit timer or as two separate 32-bit timers. On the C6655, Timer0 is dedicated to the CorePac as a watchdog timer and can also be used as a general-purpose timer. Each of the other seven timers can also be configured as a general-purpose timer only, programmed as a 64-bit timer or as two separate 32-bit timers.

When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable period.

When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two

32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.

When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again. If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming

‘‘Reset

Type Status Register (RSTYPE)’’ on page 133 and the type of reset initiated can set by programming

‘‘Reset

Configuration Register (RSTCFG)’’ on page 134. For more information, see the 64-bit Timer (Timer 64) for KeyStone

Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.19.2 Timers Electrical Data/Timing

The tables and figure below describe the timing requirements and switching characteristics of Timer0 through

Timer7 peripherals.

Table 7-78

(see Figure 7-50 )

Timer Input Timing Requirements

(1)

No.

1 t w(TINPH)

2 t w(TINPL)

End of Table 7-78

Pulse duration, high

Pulse duration, low

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Min

12C

Max Unit

ns ns

Table 7-79

(see Figure 7-50 )

Timer Output Switching Characteristics

(1)

Parameter No.

3 t w(TOUTH)

4 t w(TOUTL)

End of Table 7-79

Pulse duration, high

Pulse duration, low

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Figure 7-50 Timer Timing

1 2

TIMIx

Min

12C - 3

Max Unit

ns ns

TIMOx

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 212

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

7.20 General-Purpose Input/Output (GPIO)

7.20.1 GPIO Device-Specific Information www.ti.com

On the TMS320C6655/57, the GPIO peripheral pins GP[15:0] are also used to latch configuration settings. For more

detailed information on device/peripheral configuration and the C6655/57 device pin muxing, see ‘‘Device

Configuration’’ on page 65. For more information on GPIO, see the General Purpose Input/Output (GPIO) for

KeyStone Devices User Guide

7.20.2 GPIO Electrical Data/Timing

Table 7-80 GPIO Input Timing Requirements

No.

1 t w(GPOH)

2 t w(GPOL)

End of Table 7-80

Pulse duration, GPOx high

Pulse duration, GPOx low

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Min

12C

(1)

12C

Max Unit

ns ns

Table 7-81 GPIO Output Switching Characteristics

(1)

No.

3 t w(GPOH)

4 t w(GPOL)

End of Table 7-81

1 Over recommended operating conditions.

2 C = 1 ÷ CORECLK(N|P) frequency in ns.

Parameter

Pulse duration, GPOx high

Pulse duration, GPOx low

Figure 7-51 GPIO Timing

1 2

GPIx

Min

36C

(2)

- 8

36C - 8

Max Unit

ns ns

3 4

GPOx

7.21 Semaphore2

The device contains an enhanced semaphore module for the management of shared resources of the DSP C66x

CorePac. The semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is not broken. The semaphore module has a unique interrupt to the CorePac to identify when the core has acquired the resource.

Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.

The semaphore module supports 8 masters and contains 32 semaphores to be used within the system.

There are two methods of accessing a semaphore resource:

•

Direct Access:

A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the semaphore is not granted.

•

Indirect Access:

A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt notifies the CPU that it is available.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.22 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

• Full-duplex communication

• Double-buffered data registers, which allow a continuous data stream

• Independent framing and clocking for receive and transmit

• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

• External shift clock or an internal, programmable frequency shift clock for data transfer

• Transmit & receive FIFO buffers allow the McBSP to operate at a higher sample rate by making it more tolerant to DMA latency

If an internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.

For more information, see the Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User Guide in

7.22.1 McBSP Peripheral Register

Table 7-82

McBSP0

Byte Address

McBSP/FIFO Registers (Part 1 of 2)

McBSP1

Byte Address

0x021B 4000

0x021B 4004

0x021B 4008

0x021B 400C

0x021B 4010

0x021B 4014

0x021B 4018

0x021B 401C

0x021B 4020

0x021B 4024

0x021B 4028

0x021B 402C

0x021B 4030

0x021B 4034

0x021B 4038

0x021B 403C

0x021B 6800

0x021B 6810

0x021B 6814

0x021B 6818

0x021B 681C

0x021B 8000

0x021B 8004

0x021B 8008

0x021B 800C

0x021B 8010

0x021B 8014

0x021B 8018

0x021B 801C

0x021B 8020

0x021B 8024

0x021B 8028

0x021B 802C

0x021B 8030

0x021B 8034

0x021B 8038

0x021B 803C

0x021B A800

0x021B A810

0x021B A814

0x021B A818

0x021B A81C

Acronym

DRR

DXR

SPCR

RCR

XCR

SRGR

MCR

RCERE0

XCERE0

PCR

RCERE1

XCERE1

RCERE2

XCERE2

RCERE3

XCERE3

Register Description

McBSP Registers

McBSP Data Receive Register (read-only)

McBSP Data Transmit Register

McBSP Serial Port Control Register

McBSP Receive Control Register

McBSP Transmit Control Register

McBSP Sample Rate Generator register

McBSP Multichannel Control Register

McBSP Enhanced Receive Channel Enable Register 0 Partition A/B

McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B

McBSP Pin Control Register

McBSP Enhanced Receive Channel Enable Register 1 Partition C/D

McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D

McBSP Enhanced Receive Channel Enable Register 2 Partition E/F

McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F

McBSP Enhanced Receive Channel Enable Register 3 Partition G/H

McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H

BFIFOREV

McBSP FIFO Control and Status Registers

BFIFO Revision Identification Register

WFIFOCTL

WFIFOSTS

RFIFOCTL

RFIFOSTS

Write FIFO Control Register

Write FIFO Status Register

Read FIFO Control Register

Read FIFO Status Register

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 214

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-82 McBSP/FIFO Registers (Part 2 of 2)

McBSP0

Byte Address

McBSP1

Byte Address Acronym

0x2200 0000

End of Table 7-82

0x2240 1000

RBUF

XBUF

Register Description

McBSP FIFO Data Registers

McBSP FIFO Receive Buffer

McBSP FIFO Transmit Buffer

www.ti.com

7.22.2 McBSP Electrical Data/Timing

The following tables assume testing over recommended operating conditions.

7.22.2.1 McBSP Timing

Table 7-83

(see Figure 7-52 )

McBSP Timing Requirements

(1)

No.

5 t

6 t

7 t

8 t

10 t

11 t

2 t c(CKRX)

3 t w(CKRX) su(FRH-CKRL) h(CKRL-FRH) su(DRV-CKRL) h(CKRL-DRV) su(FXH-CKXL) h(CKXL-FXH)

Cycle time, CLKR/X

Pulse duration, CLKR/X high or CLKR/X low

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

Hold time, DR valid after CLKR low

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

Min

2P or 20

(2) (3)

P-1

(4)

Max Unit

ns ns ns ns ns ns ns ns

End of Table 7-83

1 CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

2 P = SYSCLK7 period in ns. For example, when the SYSCLK7 clock domain is running at 166MHz, use 6ns.

3 Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements

4 This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

Table 7-84

(see Figure 7-52 )

McBSP Switching Characteristics

(1) (2)

No.

Parameter

1 t d(CKSH-CKRXH)

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input.

2 t c(CKRX)

Cycle time, CLKR/X CLKR/X int

Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 3 t w(CKRX)

4 t d(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

9 t

12 t d(CKXH-FXV) dis(CKXH-DXHZ)

Delay time, CLKX high to internal FSX valid

Disable time, DX Hi-Z following last data bit from CLKX high

CLKX int

CLKX ext

CLKX int

CLKX ext

13 t

14 t d(CKXH-DXV) d(FXH-DXV)

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid applies ONLY when in data delay 0

(XDATDLY = 00b) mode

CLKX int

CLKX ext

FSX int

FSX ext

End of Table 7-84

1 CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

2 Minimum delay times also represent minimum output hold times.

3 P = SYSCLK7 period in ns. For example, when the SYSCLK7 clock domain is running at 166 MHz, use 6 ns.

4 Use whichever value is greater.

5 C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK7 period)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

If CLKGDV is even:

(1) H = CLKX high pulse width = (CLKGDV/2 + 1) * S

(2) L = CLKX low pulse width = (CLKGDV/2) * S

If CLKGDV is odd:

(1) H = (CLKGDV + 1)/2 * S

(2) L = (CLKGDV + 1)/2 * S

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit.

6 Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P

7 Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P

Min

2P or 20

(3) (4)

C - 2

(5)

-4

-4 + D1

(6)

1 + D1

(6)

-4 + D1

(7)

-2 + D1

-4

Max Unit

14.5

C + 2

For more information, see the Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide in ‘‘Related

ns ns

7.5

14.5

5.5

14.5

5.5

14.5

ns ns ns ns

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 216

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-52 McBSP Timing

CLKS

CLKR

FSR (int)

FSR (ext)

Bit(n-1)

CLKX

FSX (int)

FSX (ext)

FSX (XDATDLY=00b)

DX Bit 0

(B)

Bit(n-1)

(n-2)

(n-3)

Table 7-85

(see Figure 7-53 )

McBSP Timing Requirements for FSR When GSYNC = 1

No.

1 t su(FRH-CKSH)

2 t h(CKSH-FRH)

End of Table 7-85

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

Figure 7-53 FSR Timing When GSYNC = 1

CLKS

FSR external

CLKR/X

(no need to resync)

CLKR/X

(needs resync)

Min

www.ti.com

Max Unit

ns ns

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.23 Universal Parallel Port (uPP)

The universal parallel port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bits of data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions.

The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single

I/O channel. In this mode, only one I/O channel may be used.

The features of the uPP include:

• Programmable data width per channel (from 8 bits to 16 bits inclusive)

• Programmable data justification

–

Right-justify with 0 extend

–

Right-justify with sign extend

–

Left-justify with 0 fill

• Supports multiplexing of interleaved data during SDR transmit

• Optional frame START signal with programmable polarity

• Optional data ENABLE signal with programmable polarity

• Optional synchronization WAIT signal with programmable polarity

• Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface

–

Supports multiplexing of interleaved data during SDR transmit

–

Supports demultiplexing and multiplexing of interleaved data during DDR transfers

For more information, see the Universal Parallel Port (uPP) for KeyStone Devices User Guide in

7.23.1 uPP Register Descriptions

Table 7-86

Byte Address

0x0258 0000

0x0258 0004

0x0258 0008

0x0258 0010

0x0258 0014

0x0258 0018

0x0258 001C

0x0258 0020

0x0258 0024

0x0258 0028

0x0258 002C

0x0258 0030

0x0258 0040

Universal Parallel Port (uPP) Registers (Part 1 of 2)

UPISR

UPIER

UPIES

UPIEC

UPEOI

UPID0

Acronym

UPPID

UPPCR

UPDLB

UPCTL

UPICR

UPIVR

UPTCR

Register Description

uPP Peripheral Identification Register uPP Peripheral Control Register uPP Digital Loopback Register uPP Channel Control Register uPP Interface Configuration Register uPP Interface Idle Value Register uPP Threshold Configuration Register uPP Interrupt Raw Status Register uPP Interrupt Enabled Status Register uPP Interrupt Enable Set Register uPP Interrupt Enable Clear Register uPP End-of-Interrupt Register uPP DMA Channel I Descriptor 0 Register

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 218

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Table 7-86 Universal Parallel Port (uPP) Registers (Part 2 of 2)

Byte Address

0x0258 0044

0x0258 0048

0x0258 0050

0x0258 0054

0x0258 0058

0x0258 0060

0x0258 0064

0x0258 0068

0x0258 0070

0x0258 0074

0x0258 0078

End of Table 7-86

Acronym

UPID1

UPID2

UPIS0

UPIS1

UPIS2

UPQD0

UPQD1

UPQD2

UPQS0

UPQS1

UPQS2

Register Description

uPP DMA Channel I Descriptor 1 Register uPP DMA Channel I Descriptor 2 Register uPP DMA Channel I Status 0 Register uPP DMA Channel I Status 1 Register uPP DMA Channel I Status 2 Register uPP DMA Channel Q Descriptor 0 Register uPP DMA Channel Q Descriptor 1 Register uPP DMA Channel Q Descriptor 2 Register uPP DMA Channel Q Status 0 Register uPP DMA Channel Q Status 1 Register uPP DMA Channel Q Status 2 Register

www.ti.com

Table 7-87 uPP Timing Requirements

(see Figure 7-54 , Figure 7-55

Figure 7-56

Figure 7-57 )

No.

3 t t t c(INCLK) w(INCLKH) w(INCLKL)

Cycle time, CHn_CLK

Pulse width, CHn_CLK high

Pulse width, CHn_CLK low

4 t su(STV-INCLKH)

5 t h(INCLKH-STV)

6 t su(ENV-INCLKH)

7 t h(INCLKH-ENV)

8 t su(DV-INCLKH)

9 t h(INCLKH-DV)

10 t su(DV-INCLKL)

11 t h(INCLKL-DV)

19 t su(WTV-OUTCLKL)

20 t h(INCLKL-WTV)

21 t c(2xTXCLK)

End of Table 7-87

Setup time, CHn_START valid before CHn_CLK high

Hold time, CHn_START valid after CHn_CLK high

Setup time, CHn_ENABLE valid before CHn_CLK high

Hold time, CHn_ENABLE valid after CHn_CLK high

Setup time, CHn_DATA/XDATA valid before CHn_CLK high

Hold time, CHn_DATA/XDATA valid after CHn_CLK high

Setup time, CHn_DATA/XDATA valid before CHn_CLK low

Hold time, CHn_DATA/XDATA valid after CHn_CLK low

Setup time, CHn_WAIT valid before CHn_CLK high

Hold time, CHn_WAIT valid after CHn_CLK high

Cycle time, 2xTXCLK input clock

(1)

SDR mode

DDR mode

SDR mode

DDR mode

SDR mode

DDR mode

Min

13.33

26.66

0.8

6.66

Max Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns

1 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is divided down by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.

Submit Documentation Feedback

www.ti.com

Table 7-88 uPP Switching Characteristics

(see Figure 7-56 , Figure 7-57

)

No.

Parameter

12 t c(OUTCLK)

Cycle time, CHn_CLK

13 t w(OUTCLKH)

Pulse width, CHn_CLK high

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

14 t w(OUTCLKL)

Pulse width, CHn_CLK low

15 t d(OUTCLKH-STV)

16 t d(OUTCLKH-ENV)

17 t d(OUTCLKH-DV)

18 t d(OUTCLKL-DV)

End of Table 7-88

Delay time, CHn_START valid after CHn_CLK high

Delay time, CHn_ENABLE valid after CHn_CLK high

Delay time, CHn_DATA/XDATA valid after CHn_CLK high

Delay time, CHn_DATA/XDATA valid after CHn_CLK low

Figure 7-54

CHx_CLK

uPP Single Data Rate (SDR) Receive Timing

4 5

CHx_START

CHx_ENABLE

SDR mode

DDR mode

SDR mode

DDR mode

SDR mode

DDR mode

Min

13.33

26.66

Max Unit

ns ns ns

11 ns

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9

Figure 7-55

CHx_CLK

uPP Double Data Rate (DDR) Receive Timing

4 5

CHx_START

CHx_ENABLE

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

I1 Q1 I2 Q2 I3 Q3

I4 Q4

2 3

I5 Q5 I6 Q6

I7 Q7 I8 Q8 I9

Submit Documentation Feedback

Peripheral Information and Electrical Specifications 220

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

Figure 7-56 uPP Single Data Rate (SDR) Transmit Timing

CHx_CLK

CHx_START

CHx_ENABLE

19 20

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

Data1 Data2 Data3 Data4

13 14

www.ti.com

Data5 Data6 Data7 Data8 Data9

Figure 7-57

CHx_CLK

uPP Double Data Rate (DDR) Transmit Timing

CHx_START

CHx_ENABLE

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

I1 Q1 I2 Q2 I3 Q3 I4 Q4

I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9

7.24 Serial RapidIO (SRIO) Port

The SRIO port is a high-performance, low pin-count interconnect aimed for embedded markets. The use of the

RapidIO interconnect in a baseband board design can create a homogeneous interconnect environment, providing even more connectivity and control among the components. RapidIO is based on the memory and device addressing concepts of processor buses where the transaction processing is managed completely by hardware. This enables the

RapidIO interconnect to lower the system cost by providing lower latency, reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless interfaces. For more information, see the

Serial RapidIO (SRIO) for KeyStone Devices User Guide in

7.25 Turbo Decoder Coprocessor (TCP3d)

The C6655 and C6657 have one high-performance embedded Turbo-Decoder Coprocessor (TCP3d) that significantly speeds up channel-decoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and

WiMAX. Operating at CPU clock divided-by-2, the TCP3d is capable of processing data channels at a throughput of >100 Mbps. For more information, see the Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide

Submit Documentation Feedback

TMS320C6655/57

Fixed and Floating-Point Digital Signal Processor

ZHCS967A—August 2012

www.ti.com

7.26 Enhanced Viterbi-Decoder Coprocessor (VCP2)

The devices have two high-performance embedded Viterbi Decoder Coprocessors (VCP2) that significantly speed up channel-decoding operations on-chip. Each VCP2, operating at CPU clock divided-by-3, can decode more than

694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths

K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP2 and the CPU are carried out through the EDMA3 controller.

The VCP2 supports:

• Unlimited frame sizes

• Code rates 3/4, 1/2, 1/3, 1/4, and 1/5

• Constraint lengths 5, 6, 7, 8, and 9

• Programmable encoder polynomials

• Programmable reliability and convergence lengths

• Hard and soft decoded decisions

• Tail and convergent modes

• Yamamoto logic

• Tail biting logic

• Various input and output FIFO lengths