phyCORE -MPC5676/57xx Hardware Manual

phyCORE -MPC5676/57xx Hardware Manual
®
phyCORE -MPC5676/57xx
Hardware Manual
Document No.:
L-807e_0
SOM Prod. No.:
SOM PCB. No.:
KSP-0180-0
2367.0
CB Prod. No.:
CB PCB. No.:
KSP-0180-B0
2373.0
Edition:
March 2015
A product of a PHYTEC Technology Holding company
phyCORE®- MPC5676/57xx [KSP-0180-0]
Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™, or ®)
and copyright (©) symbols does not imply that a product is not protected. Additionally, registered
patents and trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is considered to be entirely reliable.
However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik
GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the
right to alter the information contained herein without prior notification and accepts no responsibility for
any damages that might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising
from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH
further reserves the right to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
© Copyright 2015 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and
storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur
without the express written consent from PHYTEC Messtechnik GmbH.
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Preliminary Edition March 2015
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Contents
List of Figures ........................................................................................................... iii
List of Tables ............................................................................................................ iv
Conventions, Abbreviations and Acronyms ..................................................................... v
Preface .................................................................................................................. viii
1
Introduction....................................................................................................... 1
1.1 Features of the phyCORE-MPC5676/57xx ........................................................... 1
1.1.1 Internal Features of the MPC5676R........................................................ 2
1.2 Memory configuration of the phyCORE-MPC5676/57xx......................................... 2
1.3 Other Board-Level Features............................................................................. 2
1.4 Block Diagram.............................................................................................. 3
1.5 phyCORE-MPC5676/57xx Component Placement ................................................. 4
1.6 Minimum Requirements to operate the phyCORE-MPC5676/57xx ............................ 6
2
Pin Description ................................................................................................... 7
3
Jumpers .......................................................................................................... 24
4
Power Requirements.......................................................................................... 34
4.1 Voltage Supervisor and Reset .........................................................................35
5
System Configuration and Booting....................................................................... 36
6
System Memory................................................................................................. 37
6.1 External Standard Flash Memory (U100,U101)...................................................37
6.2 Synchronous Burst SRAM(U102,U103) .............................................................38
6.3 SPI EEPROM (U6) .........................................................................................39
6.3.1 EEPROM Write Protection Control (J30) .................................................39
6.4 SPI Flash Memory (U19) ) ..............................................................................39
7
FPGA System Logic Device U18 ............................................................................ 40
7.1 Addressing the FPGA from MPC .......................................................................40
7.2 Configuration of the FPGA..............................................................................40
7.3 FPGA connector X3 .......................................................................................40
8
Serial Interfaces ............................................................................................... 41
8.1 Universal Asynchronous Interface ...................................................................41
8.2 CAN Interface..............................................................................................42
8.3 SPI Interface...............................................................................................42
9
LAN9221I Ethernet Controller............................................................................. 43
9.1.1 Ethernet Transformer ........................................................................43
9.1.2 Addressing the Ethernet Controller e ....................................................44
9.1.3 Software Reset of the Ethernet Controller ..............................................44
9.1.4 MAC Address ....................................................................................44
10 Real-Time Clock M41T93 (U7) ............................................................................. 45
11 JTAG/OnCE/Nexus Debufg Interface ..................................................................... 46
12 Technical Specifications ..................................................................................... 47
13 Hints for Integrating and Handling the phyCORE-MPC5676/57xx ............................. 50
13.1 Integrating the phyCORE-MPC5676/57xx..........................................................50
13.2 Handling the phyCORE-MPC5676/57xx.............................................................50
© PHYTEC Messtechnik GmbH 2015
L-807e_0
i
phyCORE®- MPC5676/57xx [KSP-0180-0]
14
The phyCORE- MPC5676R on the phyCORE Carrier Board........................................... 51
14.1 Concept of the phyCORE Carrier Board ............................................................. 51
14.2 Overview of the phyCORE Carrier Board Peripherals ............................................ 52
14.2.1 Connectors and Pin Header ................................................................ 53
14.2.2 Switches ........................................................................................ 54
14.2.3 LEDs.............................................................................................. 54
14.2.4 Analog Input Potentiometer............................................................... 55
14.2.5 Jumpers......................................................................................... 55
14.3 Functional Components on the phyCORE Carrier Board........................................ 58
14.3.1 phyCORE- MPC5676R SOM Connectivity (X1, X2, X3) ............................... 58
14.3.2 Power (X8, X9) ................................................................................ 59
14.3.2.1 Wall Adapter Input (X8)........................................................ 60
14.3.3 First Serial Interface at Socket P2A ..................................................... 61
14.3.4 Second Serial Interface at Socket P2B .................................................. 61
14.3.5 First CAN Interface at Plug P1A ........................................................... 62
14.3.6 Second CAN Interface at Plug P1B........................................................ 62
14.3.7 Ethernet Connectivity (X28) ............................................................... 63
14.3.8 User programmable LEDs ................................................................... 63
14.3.9 Boot Mode Selection (BOOTCFG1)........................................................ 64
14.3.10 System Reset Button (RESET1)............................................................ 65
14.3.11 FPGA_JTAG Connector....................................................................... 66
14.3.12 JTAG/Once/Nexus Debug Interface...................................................... 66
14.3.13 Reduced JTAG/OnCE/NEXUS Pin Header Connector X ............................... 66
14.3.14 Full JTAG/OnCE/NEXUS Pin Header Connector X10 .................................. 67
14.3.15 phyCORE-MPC5676/57xx Expansion Connector...................................... 68
14.3.16 Schematic of Carrier Board KSP-0180-Bx .............................................. 69
15 Revision History................................................................................................ 74
Index ...................................................................................................................... 75
ii
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Contents
List of Figures
Figure 1:
Block Diagram of the phyCORE-MPC5676/57xx.................................................. 3
Figure 2:
phyCORE-MPC5676/57xx Component Placement (top view) ................................. 4
Figure 3:
phyCORE-MPC5676/57xx Component Placement (top view) ................................. 5
Figure 4:
Pinout of the phyCORE-Connector (top view) .................................................... 8
Figure 5:
Typical Jumper Pad Numbering Scheme ..........................................................24
Figure 6:
Jumper Locations (top view) ........................................................................25
Figure 7:
Jumper Locations (bottom view)...................................................................26
Figure 8:
Physical Dimensions (top view).....................................................................47
Figure 9:
phyCORE Carrier Board Overview of Connectors, LEDs and Buttons (top view) .........52
Figure 10: Typical Jumper Numbering Scheme................................................................55
Figure 11: phyCORE Carrier Board Jumper Locations (top view) .........................................56
Figure 12: phyCORE- MPC5676R SOM Connectivity to the Carrier Board................................58
Figure 13: Powering Scheme.......................................................................................59
Figure 14: Power Connector corresponding to Wall Adapter Input X12.................................60
Figure 15: Pin Assignment of P2A as First RS-232 (Front View)...........................................61
Figure 16: Pin Assignment of P2B as Second RS-232 (Front View).......................................61
Figure 17: Pin Assignment of the DB-9 Plug P1A
(CAN Transceiver on carrier Board, Front View).................................................62
Figure 18: Pin Assignment of the DB-9 Plug P1B
(CAN Transceiver on carrier Board, Front View).................................................62
Figure 19: Expansion Connector location on the Development Board KSP-0150-B0................68
Figure 20: page 2/5 of KSP-0150-B0 schematic ..............................................................70
Figure 21: page 3/5 of KSP-0150-B0 schematic ..............................................................71
Figure 22: page 4/5 of KSP-0150-B0 schematic ..............................................................72
Figure 23: page 5/5 of KSP-0150-B0 schematic ..............................................................73
© PHYTEC Messtechnik GmbH 2015
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iii
phyCORE®- MPC5676/57xx [KSP-0180-0]
List of Tables
Table 1:
Signal Types used in this Manual ................................................................... vi
Table 2:
Abbreviations and Acronyms used in this Manual ..............................................vii
Table 3:
Pinout of the phyCORE-Connector X1, Row A ..................................................... 9
Table 4:
Pinout of the phyCORE-Connector X1, Row B ................................................... 11
Table 5:
Pinout of the phyCORE-Connector X2, Row A ................................................... 14
Table 6:
Pinout of the phyCORE-Connector X2, Row B ................................................... 16
Table 7:
Pinout of the FPGA Connector X3, Row A ........................................................ 19
Table 8:
Pinout of the FPGA Connector X3, Row B ........................................................ 21
Table 9:
Jumper Settings ....................................................................................... 27
Table 10:
Boot Modes of the phyCORE-MPC5676/57xx ................................................... 36
Table 11:
Choice of Standard Flash Memory Devices and Manufacturers ............................. 37
Table 12:
Memory Options for the Synchronous Burst SRAM ............................................ 38
Table 13:
EEPROM write protection states via J30 and GPIO463........................................ 39
Table 14:
Location of the UART Signals ....................................................................... 41
Table 15:
Location of the UART Signals ....................................................................... 42
Table 16:
Location of the Ethernet Signals .................................................................. 44
Table 17:
14-Pin JTAG/OnCE Connector (X8) and Corresponding Pins on the phyCOREConnector (X2) ......................................................................................... 46
Table 18:
phyCORE Carrier Board Connectors and Pin Headers ......................................... 53
Table 19:
phyCORE Carrier Board Push Buttons Descriptions............................................ 54
Table 20:
phyCORE Carrier Board LEDs Descriptins......................................................... 54
Table 21:
phyCORE Carrier Board Jumper Descriptions ................................................... 57
Table 22:
User Programmable LEDs on the Carrier Board................................................. 63
Table 23:
phyCORE Carrier Board DIP Switch S3 Descriptions ........................................... 64
Table 24:
Pin Assignment of the JTAG_FPGA connector X6 .............................................. 66
Table 25:
Pin Assignment of the Reduced JTAG/OnCE/Nexus Pin Header X7........................ 66
Table 26:
Pin Assignment of the Full JTAG/OnCE/Nexus Pin Header X10............................. 67
iv
© PHYTEC Messtechnik GmbH 2015
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Conventions, Abbreviations and Acronyms
Conventions, Abbreviations and Acronyms
This hardware manual describes the KSP-0180-0 System on Module in the following
referred
to
as
phyCORE®-MPC5676/57xx.
The
manual
specifies
the
®
phyCORE -MPC5676/57xx's design and function. Precise specifications for the Freescale
Semiconductor MPC5676R microcontrollers can be found in the enclosed microcontroller
Data Sheet/User's Manual.
Note: We refrain from providing detailed part specific information within this manual,
which can be subject to continuous changes, due to part maintenance for our products.
Please read the paragraph "Product Change Management and information in this
manual on parts populated on the SOM" within the Preface.
Conventions
The conventions used in this manual are as follows:
ƒ Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or
that have a dash on top of the signal name (e.g.: RD) are designated as active low
signals. That is, their active state is when they are driven low, or are driving low.
ƒ A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or
high-level signal.
ƒ The MSB and LSB of the data and address busses shown in the circuit diagram are
based on the conventions of Freescale. Accordingly, D31 and A31 represent the LSB,
while D0 and A0 represent the MSB.
These conventions are also valid for the parallel I/O signals.
ƒ Tables which describe jumper settings show the default position in bold, blue text.
ƒ Text in blue italic indicates a hyperlink within, or external to the document. Click these
links to quickly jump to the applicable URL, part, chapter, table, or figure.
ƒ References made to the phyCORE-Connector always refer to the high density Samtec
connector on the undersides of the phyCORE-MPC5676/57xx System on Module.
© PHYTEC Messtechnik GmbH 2015
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phyCORE®- MPC5676/57xx [KSP-0180-0]
Types of Signals
Different types of signals are brought out at the phyCORE-Connector. The following table
lists the abbreviations used to specify the type of a signal.
Signal Type
Power
Ref-Voltage
Input
Output
IO
IPU
OC-Bidir PU
OC-Output
5V Input PD
ETHERNET
Input
ETHERNET
Output
Table 1:
vi
Description
Supply voltage input
Reference voltage output
Digital input
Digital output
Bidirectional input/output
Digital input with pull-up, must only be connected to GND.
(jumper or open-collector output)
Open collector input/output with pull up
Open collector output without pull up, requires an external
pull up
5 V tolerant input with pull down
Differential line pairs 100 Ohm Ethernet level input
Abbr.
PWR_I
REF_O
I
O
I/O
IPU
Differential line pairs 100 Ohm Ethernet level output
ETH_O
OC-BI
OC
5V_PD
ETH_I
Signal Types used in this Manual
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Conventions, Abbreviations and Acronyms
Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to
navigate unfamiliar terms used in this document.
Abbreviation
CB
DFF
EMB
EMI
GPI
GPIO
GPO
IRAM
J
JP
PCB
PDI
PEB
POR
RTC
SMT
SOM
Sx
Sx_y
Table 2:
Definition
Carrier Board; used in reference to the phyCORE Development Kit Carrier
Board.
D flip-flop.
External memory bus.
Electromagnetic Interference.
General purpose input.
General purpose input and output.
General purpose output.
Internal RAM; the internal static RAM on the Freescale Semiconductor
MPC5676R microcontroller.
Solder jumper; these types of jumpers require solder equipment to
remove and place.
Solderless jumper; these types of jumpers can be removed and placed by
hand with no special tools.
Printed circuit board.
PHYTEC Display Interface; defined to connect PHYTEC display adapter
boards, or custom adapters
PHYTEC Extension Board
Power-on reset
Real-time clock.
Surface mount technology.
System on Module; used in reference to the KSP-0180-0
/phyCORE®-MPC5676/57xx module
User button Sx (e.g. S1, S2, etc.) used in reference to the available user
buttons, or DIP-Switches on the carrier board.
Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the
carrier board.
Abbreviations and Acronyms used in this Manual
© PHYTEC Messtechnik GmbH 2015
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vii
phyCORE®- MPC5676/57xx [KSP-0180-0]
Preface
As a member of PHYTEC's phyCORE® product family the phyCORE-MPC5676/57xx is one of a
series of PHYTEC System on Modules (SOMs) that can be populated with different
controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1)
as the basis for Rapid Development Kits which serve as a reference and evaluation
platform
(2)
as insert-ready, fully functional phyCORE® OEM modules, which can be embedded
directly into the user’s peripheral hardware design.
Implementation of an OEM-able SOM subassembly as the "core" of your embedded design
allows you to focus on hardware peripherals and firmware without expending resources to
"re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE®
module lies in its layout and test.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware
will further reduce your development time and risk and allow you to focus on your product
expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With this new innovative
full system solution you will be able to bring your new ideas to market in the most timely
and cost-efficient manner.
For more information go to:
http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
www.phytec.eu/europe/oem-integration/evaluation-start-up.html
or
Ordering Information
The part numbering of the phyCORE has the following structure:
KSP-0180-x (x=Version)
viii
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Preface
Product Specific Information and Technical Support
In order to receive product specific information on changes and updates in the best way
also in the future, we recommend to register at
http://www.phytec.de/de/support/registrierung.html or
http://www.phytec.eu/europe/support/registration.html
For technical support and additional information concerning your product, please visit the
support section of our web site which provides product specific information, such as errata
sheets, application notes, FAQs, etc.
http://www.phytec.de/de/support/faq/faq-phyCORE-MPC56xx_57xx.html or
http://www.phytec.eu/europe/support/faq/faq-phyCORE-MPC56xx_57xx.html
Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE®-MPC5676/57xx
PHYTEC System on Module (henceforth products) are designed for installation in electrical
appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform
for hardware/software development) in laboratory environments.
Caution!
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence,
may only be unpacked, handled or operated in environments in which sufficient
precautionary measures have been taken in respect to ESD-dangers. It is also necessary
that only appropriately trained personnel (such as electricians, technicians and engineers)
handle and/or operate these products. Moreover, PHYTEC products should not be operated
without protection circuitry if connections to the product's pin header rows are longer
than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic
Conformity only in accordance to the descriptions and rules of usage indicated in this
hardware manual (particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and
extensions of PHYTEC products, is subject to renewed establishment of conformity to, and
certification of, Electro Magnetic Directives. Users should ensure conformance following
any modifications to the products as well as implementation of the products into target
systems.
© PHYTEC Messtechnik GmbH 2015
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ix
phyCORE®- MPC5676/57xx [KSP-0180-0]
Product Change Management and information in this manual on parts populated on
the SOM / SBC
When buying a PHYTEC SOM / SBC, you will, in addition to our HW and SW offerings, receive
a free obsolescence maintenance service for the HW we provide.
Our PCM (Product Change Management) Team of developers, is continuously processing,
all incoming PCN's (Product Change Notifications) from vendors and distributors
concerning parts which are being used in our products.
Possible impacts to the functionality of our products, due to changes of functionality or
obsolesce of a certain part, are being evaluated in order to take the right masseurs in
purchasing or within our HW/SW design.
Our general philosophy here is: We never discontinue a product as long as there is
demand for it.
Therefore we have established a set of methods to fulfill our philosophy:
Avoiding strategies
•
•
•
Avoid changes by evaluating long-livety of parts during design in phase.
Ensure availability of equivalent second source parts.
Stay in close contact with part vendors to be aware of roadmap strategies.
Change management in rare event of an obsolete and non replaceable part
•
•
Ensure long term availability by stocking parts through last time buy management
according to product forecasts.
Offer long term frame contract to customers.
Change management in case of functional changes
•
•
•
Avoid impacts on product functionality by choosing equivalent replacement parts.
Avoid impacts on product functionality by compensating changes through HW redesign
or backward compatible SW maintenance.
Provide early change notifications concerning functional relevant changes of our
products.
Therefore we refrain from providing detailed part specific information within this
manual, which can be subject to continuous changes, due to part maintenance for our
products.
In order to receive reliable, up to date and detailed information concerning parts used
for our product, please contact our support team through the contact information
given within this manual.
x
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Introduction
1
Introduction
The phyCORE-MPC5676/57xx belongs to PHYTEC’s phyCORE System on Module family. The
phyCORE SOMs represent the continuous development of PHYTEC System on Module
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards
integrate all core elements of a microcontroller system on a subminiature board and are
designed in a manner that ensures their easy expansion and embedding in peripheral
hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic
Interference) problems stem from insufficient supply voltage grounding of electronic
components in high frequency environments approximately 20 % of all pin header
connectors on the phyCORE bus are dedicated to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer
design. In accordance with the complexity of the module, 0402-packaged SMD
components and laser-drilled microvias are used on the boards, providing phyCORE users
with access to this cutting edge miniaturization technology for integration into their own
design.
The phyCORE-MPC5676/57xx is a subminiature (58 mm x 82 mm) insert-ready System on
Module populated with the Freescale Semiconductor MPC5676R microcontroller. Its
universal design enables its insertion in a wide range of embedded applications.
Precise specifications for the controller populating the board can be found in the
applicable controller reference manual or datasheet. The descriptions in this manual are
based on the Freescale Semiconductor MPC5676R. No description of compatible
microcontroller derivative functions is included, as such functions are not relevant for the
basic functioning of the phyCORE-MPC5676/57xx.
1.1
Features of the phyCORE-MPC5676/57xx
The phyCORE-MPC5676/57xx offers the following features:
•
•
•
•
Subminiature System on Module (58 mm x 82 mm) achieved through modern SMD
technology
Populated with the Freescale Semiconductor MPC5676R/MPC5674F/MPC57xx
microcontroller (BGA516 packaging)
Controller signals and ports extend to two high-density (0.5 mm) Samtec connectors
aligning two sides of the board enabling the phyCORE-MPC5676/57xx to be plugged
like a "big chip" into target application
FPGA ports extend to a third high-density (0.5 mm) Samtec connector placed on short
side of the Module
© PHYTEC Messtechnik GmbH 2015
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phyCORE®- MPC5676/57xx [KSP-0180-0]
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
1.2
Internal Features of the MPC5676R
32-bit Dual Power Architecture® 200z7 cores, up to 2 x 180MHz clock frequency
6 MB int. Flash memory
32ch eMIOS
3x +32 eTPU
64 channel 12-bit quad ADC
4 x FlexCAN
3-ch.eSCI
5-ch.DSPI
2-ch. FlexRay
12 decimation filters
384KB SRAM
EBI ( External Bus Interface )
Memory configuration of the phyCORE-MPC5676/57xx
• SRAM: 2 MByte to 8 MByte Synchronous Flow-Through Burst-RAM,
32-bit access
• Flash: 2 MByte to 8 MByte asynchronous standard Flash,
32-bit acces
• 32k kB SPI EEPROM
• 16Mbyte Dual/Quad SPI NOR-Flash (FPGA configuration memory)
1.3
•
•
•
•
•
•
•
•
•
•
•
•
2
Other Board-Level Features
All controller and FPGA required supplies are generated on board
Voltage Supervisor IC
UART: two RS-232 transceivers for channel A and B (RxD/TxD), also usable as TTL
Ethernet: 10/100 Mbit/s LAN9221I , 16-bit EBI access from CPU
Bootconfig pins for boot source selection (int. Flash (standard), ext. Flash)
Support of standard 14 pin debug interface through JTAG connector
Xilinx Artix7 FPGA (XC7A35T…XCA100T)
FPGA configuration memory programmable via JTAG
SPI-RTC battery-buffered
Watchdog
Industrial temperature range (-40 °C to +85 °C)
Free I/Os from CPU and 101 I/Os FPGA (Bank14/15/34) available on phyCOREconnector
© PHYTEC Messtechnik GmbH 2015
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Introduction
1.4
Figure 1:
Block Diagram
Block Diagram of the phyCORE-MPC5676/57xx
© PHYTEC Messtechnik GmbH 2015
L-807e_0
3
phyCORE®- MPC5676/57xx [KSP-0180-0]
1.5
phyCORE-MPC5676/57xx Component Placement
C69
B2
C124
L1
C31
RN4
R53
C49
U10
R65
C48
R52
R9
R14R15 J32
R90
R3
XT1
R66
C118
C119
R32
R13
R27
C24
R10
R8
R7
C123
R23
R43
R41
U1
X8
R89
C9
R19 R20 R39 J18
R38
R6
J35
R95 C163
R96R94
C6 R97 C5
J2
C7R45 C8
U102
R98
C18
C161
C23
R59
J10
J11
J12
C138
J34
RN1
R28
C4
C2
C164
L2
J6
J5
C116
C107
C106
C110
L9
C37
C108C112C111
R47
R46
R67R18R42
C105
C38
C109
U9
J15
C36
C104
J20
C103
C63 J19
C102
Figure 2:
C101
R50
C3
Q1
U101
Q2
C171
C75C78
C77
C35 R62 J3 C33
C73 C79
C76
J4 L3
C170
R86 R85
R87
C173
C128
U21
J37
R34R26
J14
C176 C166 J36
J38
C150
L13
C153
C172
C127
C169
U20
C175
C167
R83 R84
L12
B4
4
U7b
U7
C66 C65 C67
R35 C22 R30 R29
U18
C113
U6
U17
C19
C139
C32
R48 J30
C20
XT2
U2
C126
C58
C51
C60C50
L5 R60
J16
C140
J24
C100
C125
C53 C52
J25
J26
C54
J23
C21
R12
R31 C59
L6 C68
C61
R11
J17 R58
R55
R54
R57
R56 C56
R61 C55
C57
U3
B1
U13
R36R4
R103
J22
B3
J21
phyCORE-MPC5676/57xx Component Placement (top view)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Introduction
C72
R77
R70
U19
R78
R71
X2
RN3
C93
C86
C94
C81
C89
TP2
R22
C85
C95
J1
C1
U5
R21
C17
U100
C40
C39
C141
C117
R44
R24
R1 R2
C74
C34
C97
C96
C160
R63
R5 R37 C62
C10
C87
R64
RN2
C47 C83
J39
C142J7
R17
C43 R16
R40
U11
C11
C82
C91
C120
C122
C41
C42
R51
C92
C90
TP1
C12
C162
R75
C136
C14
C144J9C145
C134
C155 C151
R73
R74
R79
C15
L8
R100
C154 L7
J8 C157
C70
C132
C156
C149
C129
C148C146 C147
C168
C158
X3
C143
C165 C159 C115 R80
C137
C152
R99
C135
U103
J27
J28
J29
R101
C88
C84
U12
R76
C30 C13
R68
R82
C64
R49
C29
C71
C46
C45C174
C80
C121 C44
R72
C99
C98
L4
J33 L11 L10
C27
C26 C25
J13 R25
U14
R92
R91
R93
J31
R33C28
C114
R81
R69
RN7
RN6
C16
U4
C130
RN5
R102
R88
X1
Figure 3:
phyCORE-MPC5676/57xx Component Placement (top view)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
5
phyCORE®- MPC5676/57xx [KSP-0180-0]
1.6
Minimum Requirements to operate the phyCORE-MPC5676/57xx
Basic operation of the phyCORE-MPC5676/57xx only requires supply of a +3.3 V and a +5 V
input voltage with TBD A load and the corresponding GND connection.
These supply pins are located at the phyCORE-Connector X1,X3:
VCC_3V3:
VCC_5V
X2
X3
X2
A1, B1, B2,
B1, B2, B3
A4
Connect all +3.3 V VCC input pins to your power supply and at least the matching number of
GND pins.
Corresponding GND: X2
Corresponding GND: X3
A2, A7,B3,B8
B4, B9,B14
Please refer to section 2 for information on additional GND Pins located at the phyCOREConnector X1.
Caution!
We recommend connecting all available +3.3 V and +5V input pins to the power supply
system on a custom carrier board housing the phyCORE-MPC5676/57xx and at least the
matching number of GND pins neighboring the +3.3 V pins and +5V.
In addition, proper implementation of the phyCORE-MPC5676/57xx module into a target
application also requires connecting all GND pins neighboring signals that are being used
in the application circuitry.
Please refer to section 4 for more information.
6
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
2
Pin Description
Please note that all module connections are not to exceed their expressed maximum
voltage or current. Maximum signal input values are indicated in the corresponding
controller manuals/data sheets. As damage from improper connections varies according to
use and application, it is the user's responsibility to take appropriate safety measures to
ensure that the module connections are protected from overloading through connected
peripherals.
As Figure 4 indicates, all controller signals selected extend to surface mount technology
(SMT) connectors (0.5 mm) lining two sides of the module (referred to as
phyCORE-Connector). This allows the phyCORE-MPC5676/57xx to be plugged into any
target application like a "big chip".
The numbering scheme for the phyCORE-Connector is based on a two dimensional matrix in
which column positions are identified by a letter and row position by a number.
The numbering scheme for the phyCORE-Connector is based on a two dimensional matrix in
which column positions are identified by a letter and row position by a number with
prefixed Connector Reference (X1, X2, and X3). Pin X1A1, for example, is located in the
upper left hand corner of the matrix looking down through the top of the SOM (refer to
Figure 4).
The numbered matrix can be aligned with the phyCORE-MPC5676/57xx (viewed from
above; phyCORE-Connector pointing down) or with the socket of the corresponding
phyCORE Carrier Board/user target circuitry. The numbering scheme is always in relation to
the PCB as viewed from above, even if all connector contacts extend to the bottom of the
module.
The numbering scheme is thus consistent for both the module’s phyCORE-Connector as well
as the mating connector on the phyCORE Carrier Board or target hardware, thereby
considerably reducing the risk of pin identification errors.
The following figure illustrates the numbered matrix system. It shows a
phyCORE-MPC5676/57xx with all three SMT phyCORE-Connectors on its underside (defined
as dotted lines) mounted on a carrier board. In order to facilitate understanding of the pin
assignment scheme, the diagram presents a cross-view of the phyCORE-MPC5676/57xx
module showing the phyCORE-Connector mounted on the underside of the module’s PCB.
Table 3 to Table 8 provide an overview of the pinout of the different phyCORE-Connectors
X1,X2,X3 with signal names and descriptions specific to the phyCORE-MPC5676/57xx. It
also provides the appropriate voltage domain, signal type (ST) and a functional grouping
of the signals. The signal type includes also information about the signal. A description of
the signal types can be found in Table 1.
© PHYTEC Messtechnik GmbH 2015
L-807e_0
7
phyCORE®- MPC5676/57xx [KSP-0180-0]
X2B90
X2B1
X2
X3B90
X2A1
X2A90
X1B1
X1B90
X3
X3A90
X3B1
X3A1
X1
X1A1
Figure 4:
X1A90
Pinout of the phyCORE-Connector (top view)
The Freescale Semiconductor MPC5676R is a multi-voltage operated microcontroller and as
such special attention should be paid to the interface voltage levels to avoid unintentional
damage to the microcontroller and other on-board components. Please refer to the
Freescale Semiconductor MPC5676R Reference Manual for details on the functions and
features of controller signals and port pins.
Caution:
Most of the controller pins have multiple multiplexed functions. Because most of these
pins are connected directly to the phyCORE-Connector the functions are also available
there. Signal names and descriptions in Table 3 to Table 8 however, are in regard to the
specification of the phyCORE-MPC5676/57xx and the functions defined therein. Please
refer to the MPC5676R Reference Manual, or the schematic to get to know about alternative
functions. In order to utilize a specific pin's alternative function the corresponding
registers must be configured within the appropriate driver of the BSP. To support all
features of the phyCORE-MPC5676/57xx Carrier Board a few changes have been made in
the BSP delivered with the module.
8
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
X1A1
X1A2
Signal
EXTCLK
DGND
ST
I
-
X1A3
IRQ2 RQ2
I/O
X1A4
X1A5
X1A6
X1A7
X1A8
X1A9
X1A10
X1A11
X1A12
X1A13
X1A14
X1A15
X1A16
X1A17
X1A18
X1A19
X1A20
X1A21
X1A22
X1A23
X1A24
X1A25
X1A26
X1A27
X1A28
X1A29
X1A30
X1A31
X1A32
X1A33
X1A34
X1A35
IRQ3
IRQ4
IRQ5
DGND
TCRCLKB_IRQ6
ETPUB26
ETPUB28
ETPUB30
DGND
ETPUB24
ETPUB22
ETPUB20
ETPUB18
DGND
ETPUB16
ETPUB14
ETPUB12
ETPUB10
DGND
ETPUB8
ETPUB6
ETPUB4
ETPUB2
DGND
GPIO441
GPIO443
GPIO445
GPIO447
DGND
GPIO457
GPIO459
EQADC_ANB23
EQADC_ANB21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
IRQ3 interrupt (GPIO212)
IRQ4 interrupt (GPIO208)
IRQ5 interrupt (GPIO212)
Ground 0 V
eTPU B TCR clock (GPIO146)
eTPU B channel 26 (GPIO173)
eTPU B channel 28 (GPIO175)
eTPU B channel 30 (GPIO177)
Ground 0 V
eTPU B channel 24 (GPIO171)
eTPU B channel 22 (GPIO169)
eTPU B channel 20 (GPIO167)
eTPU B channel 18 (GPIO165)
Ground 0 V
eTPU B channel 16 (GPIO163)
eTPU B channel 14 (GPIO161)
eTPU B channel 12 (GPIO159)
eTPU B channel 10 (GPIO157)
Ground 0 V
eTPU B channel 8 (GPIO155)
eTPU B channel 6 (GPIO153)
eTPU B channel 4 (GPIO151)
eTPU B channel 2 (GPIO149)
Ground 0 V
GPIO441
GPIO443
GPIO445
GPIO447
Ground 0 V
GPIO457
GPIO459
eQADC B analog input 23
eQADC B analog input 21
AGND
-
Analog Ground 0 V
X1A36
X1A37
Table 3:
Voltage domain
Description
Optional external clock input (R72)
Ground 0 V
IRQ2 interrupt (GPIO212)
used for onboard Ethernet -PHY U2)
Pinout of the phyCORE-Connector X1, Row A
© PHYTEC Messtechnik GmbH 2015
L-807e_0
9
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin #
X1A38
X1A39
X1A40
X1A41
X1A42
X1A43
X1A44
X1A45
X1A46
X1A47
X1A48
X1A49
Signal
EQADC_ANB19
EQADC_ANB17
EQADC_ANB15
EQADC_ANB13
AGND
EQADC_ANB11
EQADC_ANB9
EQADC_ANB7
EQADC_ANB5
AGND
EQADC_ANB3
EQADC_ANB1
ST
I
I
I
I
I
I
I
I
I
I
X1A50 EQADC_VRHB
I
X1A51 EQADC_VRLB
I
X1A52
X1A53
X1A54
X1A55
X1A56
X1A57
X1A58
X1A59
X1A60
X1A61
X1A62
X1A63
X1A64
X1A65
X1A66
X1A67
X1A68
X1A69
X1A70
X1A71
X1A72
X1A73
X1A74
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Table 3:
10
AGND
EQADC_AN39
EQADC_AN37
EQADC_AN35
EQADC_AN33
AGND
EQADC_AN31
EQADC_AN29
EQADC_AN27
EQADC_AN25
AGND
EQADC_AN23
EQADC_AN21
EQADC_AN19
EQADC_AN17
AGND
EQADC_AN15
EQADC_AN13
EQADC_AN11
EQADC_AN9
AGND
EQADC_AN7
EQADC_AN5
Voltage Domain
Description
eQADC B analog input 19
eQADC B analog input 17
eQADC B analog input 15
eQADC B analog input 13
Analog Ground 0 V
eQADC B analog input 11
eQADC B analog input 9
eQADC B analog input 7
eQADC B analog input 5
Analog Ground 0 V
eQADC B analog input 3
eQADC B analog input 1
ADC B Voltage reference high
refer to jumper J3-6
ADC B Voltage reference low
refer to jumper j3-6
Analog Ground 0 V
eQADC analog input 39 (GPIO451)
eQADC analog input 37 (GPIO450)
eQADC analog input 35 (GPIO449)
eQADC analog input 33 (GPIO448)
Analog Ground 0 V
eQADC analog input 31 (GPIO465)
eQADC analog input 29 (GPIO464)
eQADC analog input 27 (GPIO463)
eQADC analog input 25 (GPIO466)
Analog Ground 0 V
eQADC analog input 23
eQADC analog input 21
eQADC analog input 19
eQADC analog input 17
Analog Ground 0 V
eQADC analog input 15
eQADC analog input 13
eQADC analog input 11
eQADC analog input 9
Analog Ground 0 V
eQADC analog input 7
eQADC analog input 5
Pinout of the phyCORE-Connector X1, Row A (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
X1A75
X1A76
X1A77
X1A78
X1A79
X1A80
X1A81
X1A82
X1A83
X1A84
X1A85
X1A86
X1A87
X1A88
X1A89
X1A90
Table 3:
Signal
EQADC_AN3
EQADC_AN1
AGND
TCRCLKA_IRQ7
ETPUA30
ETPUA28
ETPUA26_IRQ14
DGND
ETPUA24_IRQ12
ETPUA22_IRQ10
ETPUA20_IRQ8
ETPUA18
DGND
ETPUA16
ETPUA14
ETPUA12
ST
I
I
-
Voltage Domain
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
eQADC analog input 3
eQADC analog input 1
Analog Ground 0 V
eTPU A TCR clock (GPIO113)
eTPU A channel 30 (GPIO144)
eTPU A channel 28 (GPIO142)
eTPU A channel 26 (GPIO140)
Ground 0 V
eTPU A channel 24 (GPIO138)
eTPU A channel 22 (GPIO136)
eTPU A channel 20 (GPIO134)
eTPU A channel 18 (GPIO132)
Ground 0 V
eTPU A channel 16 (GPIO130)
eTPU A channel 14 (GPIO128)
eTPU A channel 12 (GPIO1126)
Pinout of the phyCORE-Connector X1, Row A (continued)
Pin #
X1B1
X1B2
X1B3
Signal
ENGCLK
DGND
CLKOUT
ST
O
O
X1B4
BOOTCFG0
I
Description
EBI engineering clock output
Ground 0 V
EBI system clock output
Boot configuration Input0
X1B5
BOOTCFG1
I
Boot configuration Input1
X1B6
X1B7
X1B8
X1B9
X1B10
X1B11
X1B12
X1B13
X1B14
X1B15
X1B16
X1B17
ETPUB31
ETPUB29
ETPUB27
DGND
NC
ETPUB25
ETPUB23
ETPUB21
DGND
ETPUB19
ETPUB17
ETPUB15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 4:
Voltage Domain
refer to Jumper J21, J22 for bootmodes
refer to Jumper J21, J22 for bootmodes
eTPU B channel 31 (GPIO178)
eTPU B channel 29 (GPIO176)
eTPU B channel 27 (GPIO174)
Ground 0 V
Not connected
eTPU B channel 25 (GPIO172)
eTPU B channel 23 (GPIO170)
eTPU B channel 21 (GPIO168)
Ground 0 V
eTPU B channel 19 (GPIO166)
eTPU B channel 17 (GPIO164)
eTPU B channel 15 (GPIO162)
Pinout of the phyCORE-Connector X1, Row B
© PHYTEC Messtechnik GmbH 2015
L-807e_0
11
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin #
X1B18
X1B19
X1B20
X1B21
X1B22
X1B23
X1B24
X1B25
X1B26
X1B27
X1B28
X1B29
X1B30
X1B31
X1B32
X1B33
X1B34
X1B35
X1B36
X1B37
X1B38
X1B39
X1B40
X1B41
X1B42
X1B43
X1B44
X1B45
X1B46
X1B47
X1B48
X1B49
X1B50
X1B51
X1B52
Table 4:
12
Signal
ETPUB13
DGND
ETPUB11
ETPUB9
ETPUB7
ETPUB5
DGND
ETPUB3
ETPUB1
ETPUB0
GPIO440
DGND
GPIO442
GPIO444
GPIO446
GPIO456
DGND
GPIO458
EQADC_ANB22
EQADC_ANB20
EQADC_ANB18
AGND
EQADC_ANB16
EQADC_ANB14
EQADC_ANB12
EQADC_ANB10
AGND
EQADC_ANB8
EQADC_ANB6
EQADC_ANB4
EQADC_ANB2
AGND
EQADC_ANB0
EQADC_AN38
EQADC_AN36
ST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Voltage Domain
Description
eTPU B channel 13 (GPIO160)
Ground 0 V
eTPU B channel 11 (GPIO158)
eTPU B channel 9 (GPIO156)
eTPU B channel 7 (GPIO154)
eTPU B channel 5 (GPIO152)
Ground 0 V
eTPU B channel 3 (GPIO150)
eTPU B channel 1 (GPIO148)
eTPU B channel 0 (GPIO147)
GPIO440
Ground 0 V
GPIO442
GPIO444
GPIO446
GPIO456
Ground 0 V
GPIO458
eQADC B analog input 22
eQADC B analog input 20
eQADC B analog input 18
Analog Ground 0 V
eQADC B analog input 16
eQADC B analog input 14
eQADC B analog input 12
eQADC B analog input 10
Analog Ground 0 V
eQADC B analog input 8
eQADC B analog input 6
eQADC B analog input 4
eQADC B analog input 2
Analog Ground 0 V
eQADC B analog input 0
eQADC analog input 38(GPIO460)
eQADC analog input 36(GPIO461)
Pinout of the phyCORE-Connector X1, Row B (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
X1B53
X1B54
X1B55
X1B56
X1B57
X1B58
X1B59
X1B60
X1B61
X1B62
X1B63
X1B64
X1B65
X1B66
X1B67
X1B68
X1B69
X1B70
X1B71
X1B72
X1B73
X1B74
X1B75
X1B76
X1B77
X1B78
X1B79
X1B80
X1B81
X1B82
X1B83
X1B84
X1B85
X1B86
X1B87
X1B88
X1B89
X1B90
Table 4:
Signal
EQADC_AN34
AGND
EQADC_AN32
EQADC_AN30
EQADC_AN28
EQADC_AN26
AGND
EQADC_VRHA
EQADC_VRLA
EQADC_AN24
EQADC_AN22
AGND
EQADC_AN20
EQADC_AN18
EQADC_AN16
EQADC_AN14
AGND
EQADC_AN12
EQADC_AN10
EQADC_AN8
EQADC_AN6
AGND
EQADC_AN4
EQADC_AN2
EQADC_AN0
ETPUA31
DGND
ETPUA29
ETPUA27_IRQ15
ETPUA25_IRQ13
ETPUA23_IRQ11
DGND
ETPUA21_IRQ9
ETPUA19
ETPUA17
ETPUA15
DGND
ETPUA13
ST
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Voltage Domain
Description
eQADC analog input 34(GPIO462)
Analog Ground 0 V
eQADC analog input 32 (GPIO455)
eQADC analog input 30 (GPIO454)
eQADC analog input 28 (GPIO453)
eQADC analog input 26 (GPIO452)
Analog Ground 0 V
ADC A Voltage ref. high refer to Jumper J3-6
ADC A Voltage ref. low refer to Jumper J3-6
eQADC analog input 24
eQADC analog input 22
Analog Ground 0 V
eQADC analog input 20
eQADC analog input 18
eQADC analog input 16
eQADC analog input 14
Analog Ground 0 V
eQADC analog input 12
eQADC analog input 10
eQADC analog input 8
eQADC analog input 6
Analog Ground 0 V
eQADC analog input 4
eQADC analog input 2
eQADC analog input 0
eTPU A channel 31 (GPIO145)
Ground 0 V
eTPU A channel 29 (GPIO143)
eTPU A channel 27 (GPIO141)
eTPU A channel 25 (GPIO139)
eTPU A channel 23 (GPIO137)
Ground 0 V
eTPU A channel 21 (GPIO135)
eTPU A channel 19 (GPIO133)
eTPU A channel 17 (GPIO131)
eTPU A channel 15 (GPIO129)
Ground 0 V
eTPU A channel 13 (GPIO127)
Pinout of the phyCORE-Connector X1, Row B (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
13
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin #
X2A1
X2A2
X2A3
X2A4
Signal
VCC_3V3
DGND
VCC_5V
VBAT
ST
PWR_I
PWR_I
PWR_I
X2A5
PWRGOOD
O
X2A6
X2A7
X2A8
X2A9
X2A10
X2A11
X2A12
X2A13
WKPCFG
DGND
/RESET
/RSTOUT
EMIOS1
EMIOS3
DGND
EMIOS6
I
OC-Bidir PU
I
I/O
I/O
Voltage domain
Description
+3,3 V Primary Voltage Supply Input
Ground 0 V
5 V Primary Voltage Supply Input
external battery input (for RTC U7)
Power Good logic output signal U10
(VCC_1V2 , VCC_3V3 , VCC_5V , opt. V3V3F)
X2A14 SCIB_RX
I
WKPCFG_NMI_GPIO213 (R16/R40)
Ground 0 V
Reset I/O of the phyCORE supervisor U10
Reset output of the MPC
eMIOS channel 1 (GPIO180)
eMIOS channel 3 (GPIO182)
Ground 0 V
eMIOS channel 6 (GPIO185)
Receive line of eSCI channel B (GPIO92)
X2A15
X2A16
X2A17
X2A18
X2A19
X2A20
X2A21
X2A22
X2A23
X2A24
X2A25
X2A26
X2A27
X2A28
X2A29
X2A30
X2A31
X2A32
X2A33
X2A34
X2A35
O
O
O
I
I
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
Transmit line of eSCI channel B (GPIO91)
FlexCAN A transmit line (GPIO83)
Ground 0 V
FlexCAN B transmit line (GPIO85)
FlexCAN B receive line (GPIO86)
FlexCAN D receive line (GPIO247)
FlexCAN D transmit line (GPIO246)
Ground 0 V
TxD eSCI B RS232 (U17)
RxD eSCI B RS232 (U17) refer to J24
eMIOS channel 9 (GPIO188)
eMIOS channel 11 (GPIO190)
Ground 0 V
eMIOS channel 14 (GPIO193)
eMIOS channel 16 (GPIO195)
eMIOS channel 17 (GPIO196)
eMIOS channel 20 (GPIO199)
Ground 0 V
eMIOS channel 22 (GPIO201)
eMIOS channel 23 (GPIO202)
ETH output signal for SPEED-LED
eQADC trigger input (GPIO101)
-
Ground 0 V
SCIB_TX
CANA_TX
DGND
CANB_TX
CANB_RX
CAND_RX
CAND_TX
DGND
TXDB_RS232
RXDB_RS232
EMIOS9
EMIOS11
DGND
EMIOS14_IRQ0
EMIOS16
EMIOS18
EMIOS20
DGND
EMIOS22
EMIOS23
ETH_SPEED
X2A36 EQADC_ETRIG1
X2A37 DGND
Table 5:
14
I/O
refer to J24
Pinout of the phyCORE-Connector X2, Row A
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
X2A38
X2A39
X2A40
X2A41
X2A42
X2A43
X2A44
X2A45
X2A46
X2A47
X2A48
X2A49
X2A50
X2A51
X2A52
X2A53
X2A54
X2A55
X2A56
X2A57
X2A58
X2A59
X2A60
X2A61
X2A62
X2A63
X2A64
X2A65
X2A66
X2A67
X2A68
X2A69
X2A70
X2A71
X2A72
X2A73
X2A74
Table 5:
Signal
/RTC_IRQ
GPIO204
GPIO433
GPIO435
DGND
GPIO437
SPIA_SIN
SPIA_SOUT
SPIA_CS1
DGND
SPIA_CS4
SPIB_SIN
SPIB_SOUT
SPIB_CS2_SOUTC
DGND
NC
SPIB_CS4_SCKC
SPIC_SCK
SPIC_SIN
DGND
SPIC_SOUT
GPIO241
GPIO243
EQADC_ETRIG0/TXDC
DGND
ETPUA10
ETPUA8
ETPUA6
ETPUA4
DGND
ETPUA2
ETPUA0
NEX_JCOMP
NEX_TDO
DGND
NEX_TCK
NEX_/MSEO0
ST
OC
I/O
I/O
I/O
I/O
I
O
O
O
I
O
O
O
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
O
Voltage Domain
Description
Open Drain RTC IRQ Output (U7)
GPIO204
GPIO433
GPIO435
Ground 0 V
GPIO437
DSPI A data input (GPIO94)
DSPI A data output (GPIO95)
DSPI A chip select 1 (GPIO97)
Ground 0 V
DSPI A chip select 4 (GPIO100)
DSPI B data input (GPIO103)
DSPI B data output (GPIO104)
DSPI B chip select 2 (GPIO107)
Ground 0 V
Not connected
DSPI B chip select 4 (GPIO109)
DSPI C clock (GPIO235)
DSPI C data input (GPIO236)
Ground 0 V
DSPI C data output (GPI237)
GPIO241
GPIO243
eQADC trigger input (GPIO244)
Ground 0 V
eTPU B channel 10 (GPIO124)
eTPU B channel 8 (GPIO1122)
eTPU B channel 6 (GPIO120)
eTPU B channel 4 (GPIO118)
Ground 0 V
eTPU B channel 2 (GPIO116)
eTPU B channel 0 (GPIO114)
JTAG TAP controller enable
JTAG test data output
Ground 0 V
JTAG test clock input
Nexus message start/end out
Pinout of the phyCORE-Connector X2, Row A (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
15
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin #
Signal
ST
X2A75
X2A76
X2A77
X2A78
X2A79
X2A80
X2A81
X2A82
X2A83
X2A84
X2A85
X2A86
X2A87
X2A88
X2A89
X2A90
NEX_/MSEO1
NEX_MDO0
DGND
NEX_MDO2
NEX_MDO4
NEX_MDO6
NEX_MDO8
DGND
NEX_MDO10
NEX_MDO12
NEX_MDO14
ETH_LINK (MPC_AC5)
DGND
FR_B_TX_EN
FR_B_TX
FR_B_RX
O
O
O
O
O
O
O
O
O
O
O
O
I
Table 5:
Voltage
Domain
Description
Nexus message start/end out
Nexus message data out 0 (GPIO220)
Ground 0 V
Nexus message data out 2 (GPIO222)
Nexus message data out 4 (GPIO75)
Nexus message data out 6 (GPIO77)
Nexus message data out 8 (GPIO79)
Ground 0 V
Nexus message data out 10 (GPIO81)
Nexus message data out12 (GPIO231)
Nexus message data out14 (GPIO233)
ETH out signal LINK-LED refer to J31
Ground 0 V
FlexRay B transfer enable (GPIO253)
FlexRay B transfer (GPIO251)
FlexRay B receive (GPIO252)
Pinout of the phyCORE-Connector X2, Row A (continued)
Pin #
Signal
ST
X2B1
X2B2
X2B3
X2B4
X2B5
X2B6
X2B7
X2B8
X2B9
X2B10
X2B11
X2B12
X2B13
X2B14
VCC_3V3
VCC_3V3
DGND
NC
MPC_VSTBY
/WDO
WDI
DGND
EMIOS0
EMIOS2
EMIOS4
EMIOS5
DGND
EMIOS7
PWR_I
PWR_I
PWR_I
OC- PU
I
I/O
I/O
I/O
I/O
I/O
Voltage
Domain
Description
X2B15 SCIA_RX
I
+3,3 V Primary Voltage Supply Input
+3,3 V Primary Voltage Supply Input
Ground 0 V
Not connected
MPC- SRAM stby power range 1V – 5V
Watchdog timeout signal (U10)
Watchdog trigger input signal (U10)
Ground 0 V
eMIOS channel 0 (GPIO179)
eMIOS channel 2 (GPIO181)
eMIOS channel 4 (GPIO183)
eMIOS channel 5 (GPIO184)
Ground 0 V
eMIOS channel 7 (GPIO186)
Receive of eSCI channel A (GPIO90)
X2B16 SCIA_TX
X2B17 CANA_RX
O
I
Transmit of eSCI channel A (GPIO91)
FlexCAN A receive line (GPIO84)
Table 6:
16
refer to J23
Pinout of the phyCORE-Connector X2, Row B
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
X2B18
X2B19
X2B20
X2B21
X2B22
X2B23
X2B24
X2B25
X2B26
X2B27
X2B28
X2B29
X2B30
X2B31
X2B32
X2B33
Signal
DGND
CANC_TX
CANC_RX
RXDA_RS232
TXDA_RS232
DGND
EMIOS8
EMIOS10
EMIOS12
EMIOS13
DGND
EMIOS15_IRQ1
EMIOS17
EMIOS19
EMIOS21
DGND
ST
O
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
X2B34
ETH_TXN
ETH_O
X2B35
ETH_TXP
ETH_O
X2B36
ETH_RXP
ETH_I
X2B37
ETH_RXN
ETH_I
X2B38
X2B39
X2B40
X2B41
X2B42
X2B43
X2B44
X2B45
X2B46
X2B47
X2B48
X2B49
X2B50
X2B51
X2B52
DGND
GPIO203
GPIO432
GPIO434
GPIO436
DGND
SPIA_SCK
SPIA_CS0
SPIA_CS2
SPIA_CS3
DGND
SPIB_SCK
SPIB_CS0
SPIB_CS1
SPIB_CS3_SINC
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
Table 6:
Voltage Domain Description
Ground 0 V
FlexCAN C transmit line (GPIO87)
FlexCAN C receive line (GPIO88)
RxD eSCI A RS232 (U17) refer to J23
TxD eSCI A RS232 (U17)
Ground 0 V
eMIOS channel 8 (GPIO187)
eMIOS channel 10 (GPIO189)
eMIOS channel 12 (GPIO191)
eMIOS channel 13 (GPIO192)
Ground 0 V
eMIOS channel 15 (GPIO194)
eMIOS channel 17 (GPIO196)
eMIOS channel 19 (GPIO198)
eMIOS channel 21 (GPIO200)
Ground 0 V
negative transmit output of Ethernet
controller LAN9221I (U2)
Positive transmit output of Ethernet
controller LAN9221I (U2)
positive receive input of Ethernet
controller LAN9221I (U2)
negative receive input of Ethernet
controller LAN9221I (U2)
Ground 0 V
GPIO203
GPIO432
GPIO434
GPIO436
Ground 0 V
DSPI A clock (GPIO93)
DSPI A chip select 0 (GPIO96)
DSPI A chip select 2 (GPIO98)
DSPI A chip select 3 (GPIO99)
Ground 0 V
DSPI B clock (GPIO102)
DSPI B chip select 0 (GPIO105)
DSPI B chip select 1 (GPIO106)
DSPI B chip select 3 (GPIO108)
Pinout of the phyCORE-Connector X2, Row B (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
17
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin #
X2B53
X2B54
X2B55
X2B56
X2B57
X2B58
X2B59
X2B60
X2B61
X2B62
X2B63
X2B64
X2B65
X2B66
X2B67
X2B68
X2B69
X2B70
X2B71
X2B72
X2B73
X2B74
X2B75
X2B76
X2B77
X2B78
X2B79
X2B80
X2B81
X2B82
X2B83
X2B84
X2B85
X2B86
X2B87
X2B88
X2B89
X2B90
Table 6:
18
Signal
DGND
SPIB_CS5_CS0C
SPIC_CS0
GPIO239
GPIO240
DGND
GPIO242
GPIO245
ETPUA11
ETPUA9
DGND
ETPUA7
ETPUA5
ETPUA3
ETPUA1
DGND
NEX_/TEST
NEX_TDI
NEX_TMS
NEX_/RDY
DGND
NEX_MCKO
NEX_/EVTI
NEX_/EVTO
NEX_MDO1
DGND
NEX_MDO3
NEX_MDO5
NEX_MDO7
NEX_MDO9
DGND
NEX_MDO11
NEX_MDO13
NEX_MDO15
FR_A_TX_EN
DGND
FR_A_TX
FR_A_RX
ST
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
I
O
O
O
O
O
O
O
O
O
O
O
I
Voltage Domain
Description
Ground 0 V
DSPI A chip select 5 (GPIO110)
DSPI C chip select 0 (GPIO238)
GPIO239
GPIO240
Ground 0 V
GPIO242
GPIO245
eTPU A channel 11 (GPIO125)
eTPU A channel 9 (GPIO123)
Ground 0 V
eTPU A channel 7 (GPIO121)
eTPU A channel 5 (GPIO119)
eTPU A channel 3 (GPIO117)
eTPU A channel 1 (GPIO115)
Ground 0 V
Test mode select (do not use this pin !)
JTAG test data input
JTAG test mode select input
Nexus ready output
Ground 0 V
Nexus message clock out
Nexus event in
Nexus event out (refer to JP6 basboard)
Nexus message data out 1 (GPIO221)
Ground 0 V
Nexus message data out 3 (GPIO223)
Nexus message data out 5 (GPIO76)
Nexus message data out 7 (GPIO78)
Nexus message data out 9 (GPIO80)
Ground 0 V
Nexus message data out 11 (GPIO82)
Nexus message data out 13 (GPIO223)
Nexus message data out 15 (GPIO232)
FlexRay A transfer enable (GPIO250)
Ground 0 V
FlexRay A transfer (GPIO248)
FlexRay A receive (GPIO249)
Pinout of the phyCORE-Connector X2, Row B (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
Signal
ST
X3A1
V1V0F
PWR_OUT
Description
1,0V FPGA supply (generated on Board U20)
PWR_OUT
PWR_OUT
OC- PU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground 0 V
1,0V FPGA supply (generated on Board U20)
1,0V FPGA supply (generated on Board U20)
V1V0F Power Good logic output signal U20
FPGA user I/O Pin 0 BANK 15
Ground 0 V
FPGA user I/O Pin 1P BANK 15
FPGA user I/O Pin 1N BANK 15
FPGA user I/O Pin 3P BANK 15
FPGA user I/O Pin 3N BANK 15
Ground 0 V
FPGA user I/O Pin 5P BANK 15
FPGA user I/O Pin 5N BANK 15
FPGA user I/O Pin 7P BANK 15
FPGA user I/O Pin 7N BANK 15
Ground 0 V
FPGA user I/O Pin 9P BANK 15
FPGA user I/O Pin 9N BANK 15
FPGA user I/O Pin 11P BANK 15
FPGA user I/O Pin 11N BANK 15
Ground 0 V
FPGA user I/O Pin 13P BANK 15
FPGA user I/O Pin 13N BANK 15
FPGA user I/O Pin 15P BANK 15
FPGA user I/O Pin 15N BANK 15
Ground 0 V
FPGA user I/O Pin 17P BANK 15
FPGA user I/O Pin 17N BANK 15
FPGA user I/O Pin 19P BANK 15
FPGA user I/O Pin 19N BANK 15
Ground 0 V
FPGA user I/O Pin 21P BANK 15
FPGA user I/O Pin 21N BANK 15
FPGA user I/O Pin 23P BANK 15
FPGA user I/O Pin 23N BANK 15
-
Ground 0 V
X3A2
X3A3
X3A4
X3A5
X3A6
X3A7
X3A8
X3A9
X3A10
X3A11
X3A12
X3A13
X3A14
X3A15
X3A16
X3A17
X3A18
X3A19
X3A20
X3A21
X3A22
X3A23
X3A24
X3A25
X3A26
X3A27
X3A28
X3A29
X3A30
X3A31
X3A32
X3A33
X3A34
X3A35
DGND
V1V0F
V1V0F
PG_V1V0F
F_B15_IO0
DGND
F_B15_IO1P
F_B15_IO1N
F_B15_IO3P
F_B15_IO3N
DGND
F_B15_IO5P
F_B15_IO5N
F_B15_IO7P
F_B15_IO7N
DGND
F_B15_IO9P
F_B15_IO9N
F_B15_IO11P
F_B15_IO11N
DGND
F_B15_IO13P
F_B15_IO13N
F_B15_IO15P
F_B15_IO15N
DGND
F_B15_IO17P
F_B15_IO17N
F_B15_IO19P
F_B15_IO19N
DGND
F_B15_IO21P
F_B15_IO21N
F_B15_IO23P
X3A36 F_B15_IO23N
X3A37 DGND
Table 7:
Voltage domain
(use pin X3A1/A3/A4 onl for sensing the 1,0V)
Pinout of the FPGA Connector X3, Row A
© PHYTEC Messtechnik GmbH 2015
L-807e_0
19
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin # Signal
X3A38 F_B15_IO25
ST
I/O
X3A39 F_PROGRAM_B
I
X3A40 F_INIT_B
OC
X3A41
X3A42
X3A43
X3A44
X3A45
X3A46
X3A47
X3A48
X3A49
X3A50
X3A51
X3A52
X3A53
X3A54
X3A55
X3A56
X3A57
X3A58
X3A59
X3A60
X3A61
X3A62
X3A63
X3A64
X3A65
X3A66
X3A67
X3A68
X3A69
X3A70
X3A71
X3A72
X3A73
X3A74
I/O
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 7:
20
F_DONE
F_GNDADC
DXN_0
DXP_0
F_VP
F_VN
DGND
F_B14_IO3P
F_B14_IO3N
F_B14_IO5P
F_B14_IO5N
DGND
F_B14_IO7P
F_B14_IO7N
F_B14_IO9P
F_B14_IO9N
DGND
F_B14_IO11P
F_B14_IO11N
F_B14_IO13P
F_B14_IO13N
DGND
F_B14_IO15P
F_B14_IO15N
F_B14_IO17P
F_B14_IO17N
DGND
F_B14_IO19P
F_B14_IO19N
F_B14_IO21P
F_B14_IO21N
DGND
F_B14_IO23P
F_B14_IO23N
Voltage Domain Description
FPGA user I/O Pin 0 BANK 15
FPGA reset to configuration logic
active LOW signal
indicates initialization of configuration
memory active LOW signal
indicates successful completion of config.
FPGA XADC analog ground reference.
FPGA Temperature-sensing diode pins
FPGA Temperature-sensing diode pins
XADC dedicated differential analog input
XADC dedicated differential analog input
Ground 0 V
FPGA user I/O Pin 3P BANK 14
FPGA user I/O Pin 3N BANK 14
FPGA user I/O Pin 5P BANK 14
FPGA user I/O Pin 5N BANK 14
Ground 0 V
FPGA user I/O Pin 7P BANK 14
FPGA user I/O Pin 7N BANK 14
FPGA user I/O Pin 9P BANK 14
FPGA user I/O Pin 9N BANK 14
Ground 0 V
FPGA user I/O Pin 11P BANK 14
FPGA user I/O Pin 11N BANK 14
FPGA user I/O Pin 13P BANK 14
FPGA user I/O Pin 13N BANK 14
Ground 0 V
FPGA user I/O Pin 15P BANK 14
FPGA user I/O Pin 15N BANK 14
FPGA user I/O Pin 17P BANK 14
FPGA user I/O Pin 17N BANK 14
Ground 0 V
FPGA user I/O Pin 19P BANK 14
FPGA user I/O Pin 19N BANK 14
FPGA user I/O Pin 21P BANK 14
FPGA user I/O Pin 21N BANK 14
Ground 0 V
FPGA user I/O Pin 23P BANK 14
FPGA user I/O Pin 23N BANK 14
Pinout of the FPGA Connector X3, Row A (continued)
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Pin Description
Pin #
X3A75
X3A76
X3A77
X3A78
X3A79
X3A80
Table 7:
Signal
F_B14_IO25
F_B34_IO7N
DGND
NC
F_B34_IO9P
F_B34_IO9N
ST
I/O
I/O
-
Voltage Domain
I/O
I/O
Description
FPGA user I/O Pin 25 BANK 14
FPGA user I/O Pin 7N BANK 34
Ground 0 V
Not connected
FPGA user I/O Pin 9P BANK 34
FPGA user I/O Pin 9N BANK 34
Pinout of the FPGA Connector X3, Row A (continued)
Pin #
X3B1
X3B2
X3B3
X3B4
Signal
VCC_3V3
VCC_3V3
VCC_3V3
DGND
ST
PWR_I
PWR_I
PWR_I
-
X3B5
V1V8F
PWR_OUT
Description
+3,3 V Supply when FPGA U18 is populated
+3,3 V Supply when FPGA U18 is populated
+3,3 V Supply when FPGA U18 is populated
Ground 0 V
1,8V FPGA supply (generated on Board U21)
X3B6
X3B7
X3B8
X3B9
X3B10
X3B11
X3B12
X3B13
X3B14
X3B15
X3B16
X3B17
X3B18
X3B19
X3B20
X3B21
X3B22
X3B23
X3B24
X3B25
X3B26
X3B27
X3B28
V1V8F
PG_V1V8F
VCCO_15F
DGND
F_B15_IO2P
F_B15_IO2N
F_B15_IO4P
F_B15_IO4N
DGND
F_B15_IO6P
F_B15_IO6N
F_B15_IO8P
F_B15_IO8N
DGND
F_B15_IO10P
F_B15_IO10N
F_B15_IO12P
F_B15_IO12N
DGND
F_B15_IO14P
F_B15_IO14N
F_B15_IO16P
F_B15_IO16N
PWR_OUT
OC- PU
PWR_I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1,8V FPGA supply (generated on Board U21)
V1V8F Power Good logic output signal U21
Optional BANK15 1,5 supply refer to J34
Ground 0 V
FPGA user I/O Pin 2P BANK 15
FPGA user I/O Pin 2N BANK 15
FPGA user I/O Pin 4P BANK 15
FPGA user I/O Pin 4N BANK 15
Ground 0 V
FPGA user I/O Pin 6P BANK 15
FPGA user I/O Pin 6N BANK 15
FPGA user I/O Pin 8P BANK 15
FPGA user I/O Pin 8N BANK 15
Ground 0 V
FPGA user I/O Pin 10P BANK 15
FPGA user I/O Pin 10N BANK 15
FPGA user I/O Pin 12P BANK 15
FPGA user I/O Pin 12N BANK 15
Ground 0 V
FPGA user I/O Pin 14P BANK 15
FPGA user I/O Pin 14N BANK 15
FPGA user I/O Pin 16P BANK 15
FPGA user I/O Pin 16NBANK 15
Table 8:
Voltage Domain
(use pin X3B5/B6 onl for sensing the 1,8V)
Pinout of the FPGA Connector X3, Row B
© PHYTEC Messtechnik GmbH 2015
L-807e_0
21
phyCORE®- MPC5676/57xx [KSP-0180-0]
Pin #
X3B29
X3B30
X3B31
X3B32
X3B33
X3B34
X3B35
X3B36
X3B37
X3B38
X3B39
X3B40
X3B41
X3B42
X3B43
X3B44
Signal
DGND
F_B15_IO18P
F_B15_IO18N
F_B15_IO20P
F_B15_IO20N
DGND
F_B15_IO22P
F_B15_IO22N
F_B15_IO24P
F_B15_IO24N
DGND
F_TDI
F_TDO
F_TMS
F_TCK
DGND
ST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
-
X3B45
F_VREFN
I
X3B46
F_VREFP
I
X3B47
F_VCCBATT
I
X3B48
X3B49
X3B50
X3B51
X3B52
X3B53
X3B54
X3B55
X3B56
X3B57
X3B58
X3B59
X3B60
X3B61
X3B62
X3B63
F_B14_IO0
DGND
F_B14_IO4P
F_B14_IO4N
F_B14_IO6N
NC
DGND
F_B14_IO8P
F_B14_IO8N
F_B14_IO10P
F_B14_IO10N
DGND
F_B14_IO12P
F_B14_IO12N
F_B14_IO14P
F_B14_IO14N
I/O
I/O
I/O
I/O
Table 8:
22
Voltage Domain
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Ground 0 V
FPGA user I/O Pin 18P BANK 15
FPGA user I/O Pin 18N BANK 15
FPGA user I/O Pin 20P BANK 15
FPGA user I/O Pin 20N BANK 15
Ground 0 V
FPGA user I/O Pin 22P BANK 15
FPGA user I/O Pin 22N BANK 15
FPGA user I/O Pin 24P BANK 15
FPGA user I/O Pin 24N BANK 15
Ground 0 V
FPGA JTAG data input
FPGA JTAG data output
FPGA JTAG mode select
FPGA JTAG clock
Ground 0 V
1.25V reference input
refer to J8
1.25V reference GND reference
refer to J9
FPGA Decryptor key memory
backup supply refer to J36
FPGA user I/O Pin 0 BANK 14
Ground 0 V
FPGA user I/O Pin 4P BANK 14
FPGA user I/O Pin 4N BANK 14
FPGA user I/O Pin 6N BANK 14
not connected
Ground 0 V
FPGA user I/O Pin 8P BANK 14
FPGA user I/O Pin 8N BANK 14
FPGA user I/O Pin 10P BANK 14
FPGA user I/O Pin 10N BANK 14
Ground 0 V
FPGA user I/O Pin 12P BANK 14
FPGA user I/O Pin 12N BANK 14
FPGA user I/O Pin 14P BANK 14
FPGA user I/O Pin 14N BANK 14
Pinout of the FPGA Connector X3, Row B (continued)
© PHYTEC Messtechnik GmbH 2015
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Pin Description
Pin #
X3B64
X3B65
X3B66
X3B67
X3B68
X3B69
X3B70
X3B71
X3B72
X3B73
X3B74
X3B75
X3B76
X3B77
X3B78
X3B79
X3B80
Table 8:
Signal
DGND
F_B14_IO16P
F_B14_IO16N
F_B14_IO18P
F_B14_IO18N
DGND
F_B14_IO20P
F_B14_IO20N
F_B14_IO22P
F_B14_IO22N
DGND
F_B14_IO24P
F_B14_IO24N
F_B34_IO8P
F_B34_IO8N
DGND
F_B34_IO10P
ST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Voltage Domain
I/O
I/O
I/O
I/O
I/O
Description
Ground 0 V
FPGA user I/O Pin 16P BANK 14
FPGA user I/O Pin 16N BANK 14
FPGA user I/O Pin 18P BANK 14
FPGA user I/O Pin 18N BANK 14
Ground 0 V
FPGA user I/O Pin 20P BANK 14
FPGA user I/O Pin 20N BANK 14
FPGA user I/O Pin 22P BANK 14
FPGA user I/O Pin 22N BANK 14
Ground 0 V
FPGA user I/O Pin 24P BANK 14
FPGA user I/O Pin 24N BANK 14
FPGA user I/O Pin 8P BANK 34
FPGA user I/O Pin 8N BANK 34
Ground 0 V
FPGA user I/O Pin 10P BANK 34
Pinout of the FPGA Connector X3, Row B (continued)
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23
phyCORE®- MPC5676/57xx [KSP-0180-0]
3
Jumpers
For configuration purposes, the phyCORE-MPC5676/57xx has several solder jumpers, some
of which have been installed prior to delivery. Figure 5 illustrates the numbering of the
solder jumper pads, while
Figure 6 and
Figure 7 indicate the location of the solder jumpers on the board. Figure 5 below provides a
functional summary of the solder jumpers which can be changed to adapt the
phyCORE-MPC5676/57xx to your needs. It shows their default positions, and possible
alternative positions and functions. A detailed description of each solder jumper can be
found in the applicable chapter listed in the table.
Note:
Jumpers not listed should not be changed as they are installed with regard to the
configuration of the phyCORE-MPC5676/57xx.
closed
e.g.: J4
Figure 5:
e.g.: J4
e.g.: J5
Typical Jumper Pad Numbering Scheme
If manual jumper modification is required please ensure that the board as well as
surrounding components and sockets remain undamaged while de-soldering. Overheating
the board can cause the solder pads to loosen, rendering the module inoperable. Carefully
heat neighboring connections in pairs. After a few alternations, components can be
removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and
loosen the bonds.
24
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Jumpers
J23
J24
J30
J17
J25
J26
J32
J16
J2
J35
J10
J11
J12
J18
J34
J6
J4
J15
J37
J19
J22
Figure 6:
J5
J14
J3
J36
J38
J20
J21
Jumper Locations (top view)
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25
phyCORE®- MPC5676/57xx [KSP-0180-0]
X2
J31
J13
J33
J27
J28
J29
J39
J8
X3
J9
J1
X1
Figure 7:
Jumper Locations (bottom view)
Please pay special attention to the “TYPE” column to ensure you are using the correct type
of jumper (0 Ohms, 10k Ohms, etc…). The jumpers are either 0805 package or 0402
package with a 1/8 W or better power rating.
The jumpers (J = solder jumper) have the following functions:
26
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Jumpers
Jumper
Description
Type
J1
Connects /CS0 directly /FL_CS
Chapter
0 Ω (0402)
closed /CS0 directly connected to Flash
( U5 must be unpopulated )
open /CS0 decoded with address A9 from MPC
for generation of /FPGA_CS and /FL_CS
J2 connects the ZZ lines of SRAM memory devices
U102-103 to the MPC GPIO460. ZZ is also
connected to ball R2 of the FPGAU18B.
This enables the phyCORE SRAM banks to be 0 Ω (0402)
switched to an energy saving state via software.
During this state, the memory cannot be read or
written to. ZZ has a pull-down resistor.
J2
closed Connects ZZ to the MPC GPIO460.
open Disconnects ZZ from the MPC GPIO460.
Connects ADC B Voltage reference high with
ADC A Voltage reference high from MPC
J3
0 Ω (0402)
closed EQADC_VRHA connected with EQADC_VRHB
open EQADC_VRHA not connected with EQADC_VRHB
Connects ADC B Voltage reference low with
ADC A Voltage reference low from MPC
J4
0 Ω (0402)
closed EQADC_VRLA connected with EQADC_VRLB
open EQADC_VRLA not connected with EQADC_VRLB
Connects VRL_A and VRL_B(J4) with AGND
J5
0 Ω (0402)
closed EQADC_VRLA and EQADC_VRLB(J4) connected
with AGND
open EQADC_VRLA and EQADC_VRLB(J4) of MPC must be
connected extern from via phyCORE-Connector
Table 9:
1
:
Jumper Settings 1
Default settings are in bold blue text
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27
phyCORE®- MPC5676/57xx [KSP-0180-0]
Jumper
Description
J6
Connects VDDA
EQADC_VRHB (J3)
Type
with
EQADC_VRHA
and
Chapter
0 Ω (0402)
closed EQADC_VRLA and EQADC_VRLB(J4) connected with
VDDA
open EQADC_VRLA and EQADC_VRLB(J4) of MPC must be
connected extern from phyCORE-Connector
Connects MPC_VSTBY to DGND
(buffering of int. 48KB SRAM disabled)
J7
0 Ω (0402)
closed MPC_VSTBY connected with DGND
(buffering of int. 48KB SRAM disabled)
open MPC_VSTBY must be connected extern from
phyCORE –Connector with 2V – 5V volts
J8
Connects F_VREFN to F_GNDADC
int. reference enabled
0 Ω (0402)
Connects F_VREFP to F_GNDADC
int. reference enabled
0 Ω (0402)
closed
open
J9
closed Connects F_VREFN to F_GNDADC
int. reference enabled
open
Connects GPIO452 of MPC
to F_PROGRAMM_B of FPGA
J10
0 Ω (0402)
closed GPIO452 connected to FPGAs F_PROGRAMM_B
open GPIO452 not connected to FPGAs F_PROGRAMM_B
Table 9:
2
:
28
Jumper Settings 2
Default settings are in bold blue text
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Jumpers
Jumper
Description
Type
J11
Connects GPIO453 of MPC
to F_INIT_B of FPGA
Chapter
0 Ω (0402)
closed GPIO453 connected to FPGAs F_INIT_B
open GPIO453 not connected to FPGAs F_F_INIT_B
Connects GPIO454 of MPC
to F_DONE of FPGA
J12
0 Ω (0402)
closed GPIO454 connected to FPGAs F_DONE
open GPIO454 not connected to FPGAs F_DONE
Connects GPIO455 of MPC
to multiplexer U14 select input
J13
0 Ω (0402)
closed GPIO455 connected to to multiplexer U14 select
input U14 select input
open GPIO455 not connected to to multiplexer U14
select input
J14
J14 connects the memory bank address signal to
the corresponding address lines of the processor.
The configuration of these jumper is dependent on
the memory size of the Synchronous Burst SRAM
populating the module (U102 and U103). The
0 Ω (0402)
factory setting of J14 is in accordance with the
memory configuration of each individual module.
The two memory banks are typically equipped with
the same devices.
1+2 A9: 32 MBit memory devices at U102/U103
2+3 A11: 8 MBit memory devices at U102/U103
2+4 A10: 16 MBit memory devices at U102/U103
Table 9:
3
:
Jumper Settings 3
Default settings are in bold blue text
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29
phyCORE®- MPC5676/57xx [KSP-0180-0]
Jumper
Description
Type
J15
Connects Enable Pin of U9 to DGND or VCC_3V3
Chapter
0 Ω (0402)
1+2 Voltage Regulator U9 is enabled
2+3 Voltage Regulator U9 is disabled
Enables Auto-MDIX Ethernet U2 (int pull Up)
J16
10k Ω
(0402)
1+2
2+3
Connects GPIO461 or /RSTOUT of MPC to
/Reset Input of Ethernet Controller LAN9221I
J17
0 Ω (0402)
1+2 /RSTOUT of MPC connected to /Reset Input
2+3 GPIO461 of MPC connected to /Reset Input
Connects pull-UP or pull-DOWN to PLLCFG2 of MPC
J18
4.7k Ω
(0402)
1+2 Pull-UP connected to PLLCFG2 of MPC
(40Mhz crystal used)
2+3 Pull-DOWN connected to PLLCFG2 of MPC
Connects pull-UP or pull-DOWN to PLLCFG1 of MPC
J19
4.7k Ω
(0402)
1+2 Pull-UP connected to PLLCFG1 of MPC
2+3 Pull-DOWN connected to PLLCFG1 of MPC
Connects pull-UP or pull-DOWN to PLLCFG0 of MPC
J20
4.7k Ω
(0402)
1+2 Pull-UP connected to PLLCFG0 of MPC
2+3 Pull-DOWN connected to PLLCFG0 of MPC
Connects pull-UP or pull-DOWN to BOOTCFG1
of MPC
J21
4.7k Ω
(0402)
1+2 Pull-UP connected to BOOTCFG1 of MPC
2+3 Pull-DOWN connected to BOOTCFG1 of MPC
open BOOTCFG1 must be pulled High or Low
via phyCORE connector X1B5 for MPC Bootmode
Table 9:
4
:
30
Jumper Settings 4
Default settings are in bold blue text
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Jumpers
Jumper
Description
J22
Connects pull-UP or pull-DOWN to BOOTCFG0
of MPC
Type
Chapter
4.7k Ω
(0402)
1+2 Pull-UP connected to BOOTCFG0 of MPC
2+3 Pull-DOWN connected to BOOTCFG0 of MPC
open BOOTCFG0 must be pulled High or Low
via phyCORE connector
X1B4 for MPC
Bootmode
J23 and J24 disconnect the receive lines of
MPC UART from the RS-232 transceiver at U17.
This makes the controller's SCI/UART TTL level
0 Ω (0402)
signals available at pins X2B15 (RXDA) and
X2A14 (RXDB). This is useful, for instance, for
galvanic isolation of the RS-232 interface.
J23,J24
open The SCI/UART receive signals RXDA and RXDB
are disconnected from the RS-232 transceiver.
closed The SCI/UART receive signals RXDA and RXDB
are connected to the RS-232 transceiver.
Connects SPID_SOUT of MPC to F_SPI_DIN of
0 Ω (0402)
FPGA
J25
1+2
2+3 F_SPI_DOUT connected to F_SPI_DIN
(for usage of FPGA Serial Slave Mode)
J26
Connects pull-UP or pull-DOWN to PUDC_B of
FPGA
4.7k Ω
(0402)
1+2 Pull-UP connected to PUDC_B
(int. pull-UP disabled)
2+3 Pull-DONW connected to PUDC_B
(int. pull-UP enabled)
J27,J28, J29 FPGA Configuration mode selection.
4.7k Ω
(0402)
1+2,2+3,2+3 FPGA Master SPI configuration Mode
Configuration is loaded from SPI-Flash U19
Table 9:
5
:
Jumper Settings 5
Default settings are in bold blue text
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31
phyCORE®- MPC5676/57xx [KSP-0180-0]
Jumper
Description
Type
J30
Connects GPIO463 of MPC or pull-UP to write
0 Ω (0402)
Protect input /WP of SPI EEPROM U6
Chapter
1+2 GPIO463 of MPC is connected to /WP of U6
U6 write protected until GPIO is set to high
2+3 Pull-UP is connected to /WP of U6
U6 is NOT write protected
J31
Connects ETH_LINK LED signal from Ethernet
Controller U2 or Ball AC5 of MPC to phyCORE 0 Ω (0402)
connector pin X2A86
1+2 ETH_LINK is connected to phyCORE connector
pin X2A86
2+3 Ball AC5 of MPC is connected to phyCORE
connector pin X2A86 (for future MPC devices)
J32
Connects VCC_3V3 to Ball AC5 or makes Ball AC5
available at J31
0 Ω (0402)
1+2 VCC_3V3 connected to MPC_AC5
2+3 MPC_AC5 available at J31 (for future MPC devices)
J33
Connects Ball AA23 with VCC_5V or
(VCC_3V3)
VDDSYN
0 Ω (0402)
1+2 VDDSYN connected to MPC_AA23
2+3 VCC_5V connected to MPC_AA23
J34
3.3V or 1.5V IO Supply Voltage für BANK15 of FPGA
Ferrit 2A
(0805)
1+2 3.3V IO Supply Voltage for BANK15 of FPGA
2+3 1.5V IO Supply Voltage for BANK15 of FPGA
1.5V must then be supplied via FPGA connector
X3B8
Table 9:
6
:
32
Jumper Settings 6
Default settings are in bold blue text
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Jumpers
Jumper
Description
Type
J35
Connects FPGAs F_EMCCLK14 to F_CCLK
to enable SPI access to the SPI flash while the
board is running in non-configuration mode
0 Ω (0402)
EMCCLK14 pin is in tri-state mode during
configuration
Chapter
open EMCCLK14 not connected to F_CCLK
close EMCCLK14 connected to F_CCLK
J36
Connects VCCBATT_0 of FPGA to 1.8V or
FPGA connector X3B47 for external supply
Description of VCCBATT_0:
0 Ω (0402)
Decryptor key memory backup supply;
this pin should be tied to the appropriate VCC or
GND when not used.
1+2 VCCBATT_0 is connected to 1.8V supply
(Decryptor key memory not used)
2+3 VCCBATT_0 can be connected
via FPGA connector X3B47
J37
Enable/Disable V1V0F Regulator U20
0 Ω (0402)
1+2 V1V0F Regulator U20 enabled
2+3 V1V0F Regulator U20 disabled
J38
Enable/Disable V1V8F Regulator U21
0 Ω (0402)
1+2 V1V8F Regulator U21 enabled
2+3 V1V8F Regulator U21 disabled
J39
Connects VCC_5V or VCC_3V3 VDDEH1 of MPC
0 Ω (0402)
1+2 VCC_3V3 connected to VDDEH1 of MPC
2+3 VCC_5V connected to VDDEH1 of MPC
Table 9:
7
:
Jumper Settings 7
Default settings are in bold blue text
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33
phyCORE®- MPC5676/57xx [KSP-0180-0]
4
Power Requirements
The phyCORE-MPC5676/57xx must be supplied with two different supply voltages:
Supply voltage VCC_3V3 +3.3 V ± 5 % with tbdA **
Pins at Connector X2
A1, B1, B2
Pins at Connector X3
B1, B2,B3 (if FPGA is populated)
Supply voltage VDD5V
Pins at Connector X2
+5 V ± 5 % with tbdA **
A4
** without external loads
Connect all +3.3 V VCC input pins to your power supply and at least the matching number of
GND pins.
Corresponding GND: X2
A2, A7,B3,B8
Corresponding GND: X3
B4, B9,B14
Caution:
Both supply voltages are required for proper operation of the phyCORE-MPC5676/57xx.
The module must never be put into operation whit only one of the supply voltages
connected to the device! This might render the module inoperable.
Connect all power input pins to your power supply and at least the matching number of
DGND pins neighboring the power pins.
As a general design rule we recommend connecting all GND pins neighboring signals which
are being used in the application circuitry. For maximum EMI performance all GND pins
should be connected to a solid ground plane.
The load of the supplies depends on the external periphery attached to the phyCORE
module.
34
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Power
Optional supply input VBAT
Pin at Connector X2
+3V
A4
VBAT is the input pin that supplies the the Real-Time Clock U7 VBAT should be supplied
from a 3 V source.
Optional supply input MPC_VSTBY
Pin at Connector X2
+2V to +5V
B5
MPC_VSTBY is the power supply input that is used to maintain a portion of the contents of
internal SRAM during power down.
If not used, tie VSTBY to VSS. (refer to J7 in Table 9 )
Optional supply input F_VCCBATT
1.0V to 1.89V
F_VCCBATT is Decryptor key memory backup supply;
this pin should be tied to the 1.8V or GND when not used (refer to J36 in Table 9 )
On-board generated voltages: VDD1V5, VDDFPGA
VCC_1V2 5 MPC5676/57xx core voltage
V1V0F
XILINX FPGA core voltage
V1V8F
XILINX FPGA auxiliary/ VCCADC
4.1
Voltage Supervisor and Reset
The input voltages VCC_3V3 and VCC_5V as well as the on-board generated operation
voltage VCC_1V2 are monitored by a voltage supervisor device at U10. This circuitry is
responsible for generation of the system reset signal /RESET. The voltage supervisor IC
initiates a reset cycle if any operating voltage drops below its minimum threshold value.
After all voltages reach their required value, the supervisor chip adds an additional 200 ms
delay until the /RESET line will be inactive (high). /RESET connects to the processor reset
input.
/RESET is a bi-directional (open-collector) signal that can be connected to more then one
source. For instance, /RESET is also connected to the JTAG/OnCE connector of the phyCORE
module. /RESET has a 10kOhm pull-up resistor.
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35
phyCORE®- MPC5676/57xx [KSP-0180-0]
5
System Configuration and Booting
Although most features of the MPC5676R microcontroller are configured and/or programmed during the initialization routine, other features, which impact program
execution, must be configured prior to initialization via pin termination.
The phyCORE- MPC5676/57xx supports the following start-up modes:
•
•
•
Internal Flash Memory
SCI UART
FlexCAN
The phyCORE-MPC5676/57xx provides two boot configuration pins BOOT[1:0]. The setting
of these pins configures the boot device which is selected by the microcontroller Table 10
shows the possible settings of pins BOOTCFG0 and BOOTCFG1 and the resulting boot
configuration of the MPC5676R.
BOOTCFG0
pinX1B4
BOOTCFG1
pinX1B5
Bootsource
0
0
Boot from internal flash memory
0
1
FlexCAN / eSCI boot
Table 10:
36
Boot Modes of the phyCORE-MPC5676/57xx
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System Memory
6
System Memory
The system memory consist of internal MPC5676/57xx Flash memory, external standard
Flash memory, Synchronous Burst SRAM, SPI-Flash (FPGA configuration) and a small nonvolatile memory device:
•
•
•
•
•
6 MByte internal MPC5676R Flash
2 MByte to 8MByte asynchronous standard Flash
1 MByte to 8MByte synchronous SRAM
SPI -EEPROM: 32 KByte
SPI Flash (FPGA configuration Flash): 16 MB
The external Flash and sync. SRAM are connected to the MPC5676R 32-bit data bus.
The Flash is controlled by /CS0
The Synchronous Burst SRAM is controlled by /CS1
Communication with the small non-volatile memory device (EPROM) is established over the
SPI bus. This memory device can be used for storage of system parameters or configuration
data.
The following sections of this chapter detail each memory type used on the
phyCORE-MPC5676/57xx.
6.1
External Standard Flash Memory (U100,U101)
The Flash memory devices used on the phyCORE- MPC5676/57xx operate in 16-bit mode
and are organized in 32-bit data bus with. The device at U100 connects to the low data bus
while device U101 connects to the high data bus.
Type
S29AL016J
Table 11:
Size per Manufacturer Device
device
Code
2 MByte Spansion
22C4
Manufacturer
Code
01
Choice of Standard Flash Memory Devices and Manufacturers
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37
phyCORE®- MPC5676/57xx [KSP-0180-0]
The access speed depends on the MPC5676/57xx processor frequency and the speed grade
of populated flash devices. The speed grade varies due to production deviations. To
provide for a worst case scenario take the value for the highest access time into
consideration. With assuming of tbd MHz processor frequency and tbd MHz bus speed take
the following wait state values:
70 ns access time
tbd wait states
The external Flash controlled by /CS0 with 32-bit bus width (address/Data muxed mode).
When the FPGA is populated the 8MByte address space of /CS0 is shared between FPGA
and external Flash as follows:
MPC /CS0 to FPGA
address space from 0x000000 to 3F.FFFF (size 4MByte)
MPC /CS0 to external Flash
address space from 0x400000 to 7F.FFFF (size 4MByte)
6.2
Synchronous Burst SRAM(U102,U103)
Use of synchronous Flow-Through Burst SRAM supports the fastest mode of the MPC5676R
memory interface. The memory is organized in 32-bit width and consists of two banks.
These banks appear to the processor as linear address spaces and do not require special
activation. The memory is generally accessed via /CS1
The phyCORE-MPC5676R can be populated with memory devices of various capacities.
Generally, each memory bank can only be populated with memory devices of a consistent
size. Solder jumper J14 is used to configure the memory capacity and pre-installed at time
of delivery.
Table 12 shows all of the possible memory configurations.
Capacity
1 MByte
2 MByte
4 MByte
8 MByte
Table 12:
Type
256k x 32/36-bit
256k x 32/36-bit
512k x 32/36-bit
512k x 32/36-bit
1M x 32/36-bit
1M x 32/36-bit
Device
U5
U5-6
U5
U5-6
U5
U5-6
J14
2+3
2+3
2+4
2+4
1+2
1+2
Memory Options for the Synchronous Burst SRAM
The SRAM is controlled by /CS1 with 32-bit bus width (address/Data muxed mode)..
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System Memory
6.3
SPI EEPROM (U6)
The phyCORE-MPC5676/57xx is populated with a non-volatile 32 kB SPI 8 EEPROM at U6.
This memory can be used to store configuration data or other general purpose data. This
device is accessed through SPI ”D” on the MPC5676R.
Write protection to the device is accomplished via jumper J30 and MPC GPIO463. Refer to
section 6.3.1 for further details.
6.3.1
EEPROM Write Protection Control (J30)
Jumper J30 connects the /WP pin of the EEPROM (U6) to a pull-up resistor or to GPIO463 of
the MPC to control the write protection of the EEPROM from the MPC.
The following configurations are possible:
EEPROM Write Protection State
Write access permanently allowed
Write protection controlled by GPIO463
Table 13:
6.4
J30
2+3
1+2
EEPROM write protection states via J30 and GPIO463 9
SPI Flash Memory (U19) )
The SPI Flash Memory of the phyCORE-MPC5676/57xx at U19 is the configuration memory
for the XILINX FPGA.
The configuration file for the FPGA can be programmed in two way.
1. ) programming the SPI Flash U19 indirect via JTAG interface of the XLINX FPGA
The JTAG Signals of the FPGA are available at the FPGA connector X3 pin B40 to B43
2.) programming the SPI Flash U19 directly from the MPC using SPID with SPID_CS2
In order to connect MPC SPI Signals to the SPI-Flash U19 via the multiplexer U14
GPIO455 must be programmed high.
9
:
:
9
See the manufacturer’s data sheet for interfacing and operation.
Defaults are in bold blue text
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39
phyCORE®- MPC5676/57xx [KSP-0180-0]
7
FPGA System Logic Device U18
The phyCORE-MPC5676/57xx is populated with Xilinx Artix-7 “XC7A50T-XFTG256X”
FPGA at U18 The FPGA is connected to the MPC External Data Adress Bus.
7.1
Addressing the FPGA from MPC
Due to the fact that chip selcts of the MPC are used in the default configuration of the
phyCORE-MPC5676/57xx, the FPGA shares the address space of /CS0 with the populated
external Flash U100/U101 via multiplexer U5.
The addresses space is are split as follows
MPC /CS0 to FPGA
MPC /CS0 to external Flash
7.2
address space from 0x000000 to 3F.FFFF (size 4MByte)
address space from 0x400000 to 7F.FFFF (size 4MByte)
Configuration of the FPGA
The FPGA configuration mode is master SPI (default). Refer to Jumper J27 to 29
For the FPGA configuration mode “master SPI mode” the phyCORE-MPC5676/57xx is
equipped with a SPI Flash U19.
Refer to section 6.4
7.3
FPGA connector X3
The phyCORE-MPC5676/57xx provides 101 free usable I/Os from the FPGA on the FPGAconnector X3
( 45 free I/Os BANK14 + free 50 I/Os BANK15 + free 6 I/Os BANK34 = 101 I/Os)
Furthermore the FPGA JTAG Signals and control Pins for the FPGA configuration are
available at X3
Refer to Table 7 and Table 8 for the pinout of X3.
40
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Serial Interfaces
8
Serial Interfaces
8.1
Universal Asynchronous Interface
A dual-channel RS-232 transceiver is located on the phyCORE- MPC5676/57xx at U17. This
device adjusts the signal levels of the TXDA/RXDA and TXDB/RXDB lines (MPC5676R eSCI
UART). The RS-232 interface enables connection of the module to a COM port on a host-PC
or other peripheral devices. In this instance, the RXDA_RS232 or RXDB_RS232 line
(X2B21/X2A24) of the transceiver is connected to the corresponding TXD line of the COM
port; while the TXDA_RS232 or TXDB_RS232 line (X2B22/X2A23) is connected to the RXD
line of the COM port. The ground circuitry of the phyCORE- MPC5676/57xx must also be
connected to the applicable ground pin on the COM port.
Furthermore it is possible to use the TTL signals of the eSCI UART channels externally.
These signals are available at X2B15, X2B16 (RXDA, TXDA) and X2A14, X2A15 (RXDB, TXDB)
on the phyCORE-connector. External connection of TTL signals is required for galvanic
separation of the interface signals or for connection of different interface standards
(RS485 etc.). Using the solder jumpers J23 and J24, the TTL transceiver outputs of the onboard RS-232 transceiver devices can be disconnected from the receive lines RXDA and
RXDB. This is required so that the external transceiver does not drive signals against the
on-board transceiver. The transmit lines TXDA / TXDB can be connected parallel to the
transceiver input without causing any signal conflicts.
Pin #
X2B22
X2B21
X2A23
X2A24
X2B16
X2B15
X2A15
X2A14
Table 14:
Signal
TXDA_RS232
RXDA_RS232
TXDB_RS232
RXDB_RS232
SCIA_TX
SCIA_RX
SCIB_TX
SCIB_RX
ST
O
I
O
I
O
I
O
I
Volatge
RS232
RS232
RS232
RS232
TTL
TTL
TTl
TTL
Description
RS232 serial transmit signal
RS232 serial data receive signal
RS232 serial transmit signal
RS232 serial data receive signal
serial transmit signal SCIA
serial data receive signal SCIA
serial transmit signal SCIB
serial data receive signal SCIB
Location of the UART Signals
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phyCORE®- MPC5676/57xx [KSP-0180-0]
8.2 CAN Interface
4x CAN Nodes (directly from MPC) are available at the phyCORE-connector X2
as shown in table 15
Pin #
X2A16
X2B17
X2A18
X2A19
X2B19
X2B20
X2A21
X2A20
Table 15:
8.3
Signal
CANA_TX
CANA_RX
CANB_TX
CANB_RX
CANC_TX
CANC_RX
CAND_TX
CAND_RX
ST
O
I
O
I
O
I
O
I
Voltage
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Description
CAN A transmit
CAN A receive
CAN B transmit
CAN B receive
CAN C transmit
CAN C receive
CAN D transmit
CAN D receive
Location of the UART Signals
SPI Interface
The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that
provides a simple and efficient method for data exchange among devices. The MPC5676
provides up to five SPI interfaces that are available on the phyCORE-connector.
Note:
The phyCORE-MPC5676/57xx uses the SPI Interface SPID on board for the following
devices:
SPI EEPROM U6 (SPID_/CS1)
SPI-RTC U7 (SPID_/CS0)
SPI-Flash (FPGA config. Flash ) (SPID_/CS2)
42
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Serial Interfaces
9
LAN9221I Ethernet Controller
Connection of the phyCORE-MPC5676/57xx to the world wide web or a local network is
possible if the optional LAN9221I 10/100 Mbit/s Ethernet controller populates the
module at U2.
The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY
9.1.1
Ethernet Transformer
In order to connect the module to an existing 10/100Base-T network some external
circuitry is required. The required termination resistors on the analog signals (ETH_TXN,
ETH_TXP, ETH_RXN, ETH_RXP) are populated on the phyCORE-MPC5676/57xx, so there is
no need to connect external termination resistors to these signals. Connection to an
external Ethernet magnetics should be done using very short signal traces.
The ETH_TXN /TXP, ETH_RXN/RXP signals should be routed as 100 Ohm differential pairs.
The carrier board layout should avoid any other signal lines crossing the Ethernet signals.
If you are using the applicable carrier board for the phyCORE-MPC5676/57xx (part number
KSP-0180-B0), the external circuitry mentioned above is already integrated on the board
(refer to section 14.3.7).
Caution!
Please see the datasheet of the Ethernet Controller when designing the Ethernet
transformer circuitry.
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phyCORE®- MPC5676/57xx [KSP-0180-0]
9.1.2
Addressing the Ethernet Controller e
The Ethernet device LAN9221I is controlled by the MPC Chip Select signal /CS3. Prior to
accessing the LAN device the Chip Select has to be initialized by the application software.
The Ethernet device is accessed via 16Bit external Data Bus
(16bit address/data muxed mode )
9.1.3
Software Reset of the Ethernet Controller
The Ethernet Controller at U2 can be reset by software if Jumper J17=2+3 (default).
With J17=2+3 the reset input of the Ethernet is permanently connected to GPIO461
of the MPC5676R.
9.1.4
MAC Address
In a computer network such as a local area network (LAN), the MAC (Media Access Control)
address is a unique computer hardware number. For a connection to the Internet, a table
is used to convert the assigned IP number to the hardware’s MAC address.
In order to guarantee that the MAC address is unique, all addresses are managed in a
central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the
phyCORE-MPC5676/57xx is located on the bar code sticker attached to the module. This
number is a 12-digit HEX value.
Pin #
Signal
ST
Description
Positive transmit output of Ethernet
X2A16 ETH_TXP
ETH_O controller LAN9221I (U2)
X2B17 ETH_TXN
ETH_O controller LAN9221I (U2)
X2A18 ETH_RXP
ETH_I controller LAN9221I (U2)
X2A19 ETH_RXN
ETH_I Controller LAN9221I (U2)
Table 16:
44
Negative transmit output of Ethernet
Positive receive input of Ethernet
Negative receive input of Ethernet
Location of the Ethernet Signals
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General Purpose I/O
10
Real-Time Clock M41T93 (U7)
On the phyCORE-MPC5676/57xx the Real-Time Clock M41T93 is populated at U7
Communication between MPC and RTC is done via SPID Interface and /CS0 from MPC
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phyCORE®- MPC5676/57xx [KSP-0180-0]
11
JTAG/OnCE/Nexus Debufg Interface
The MPC5676 offers an on-chip JTAG/OnCE/Nexus debug interface. This interface allows
external debug access to the controller without requiring a service software or firmware,
such as a Monitor program, running on the chip. This internal debug interface also
contains hardware features supporting use with common cross development systems and
debug environments, such as Metrowerks' CodeWarrior. For instance, the MPC5676
features internal breakpoint registers enabling debugging in Flash memory.
A reduced set of the on-chip JTAG/OnCE/Nexus interface extends from the MPC5676 to a
14-pin connector X8 (card edge) at which an external interface signal converter circuitry
can be attached. Such signal converters enable connection of the MPC5676 to a host-PC for
debugging purposes.
The footprint of X8 is designed for a 14-pin header with 2.0 mm pin spacing. The pin
assignment is shown in Table 17. Pin header X8 is not installed on the standard
phyCORE-MPC5676/57xx module.
phyCORE Pin X2 Signal
B70
A71
A73
A8
B1, B2...
B72
Table 17:
NEX_TDI
NEX_TDO
NEX_TCK
NC
/RESET
VCC_3V3
NEX_/RDY
JTAG/OnCE
Connector
1
3
5
7
9
11
13
o
o
o
o
o
o
o
o
o
o
o
o
o
o
2
4
6
8
10
12
14
Signal
phyCORE Pin X2
DGND
DGND
DGND
NC
NEX_TMS
DGND
NEX_JCOMP
B68, B73, A72
B68, B73, A72
B68, B73, A72
B71
B68, B73, A72
A70
14-Pin JTAG/OnCE Connector (X8) and Corresponding Pins on the phyCORE-Connector (X2)
In order to connect a true Nexus port, an external 38-pin connector must be located on the
customer application board. The PHYTEC phyCORE-MPC5676/57xx Development Board
(part number KSP-0180-B0) features such Nexus connector at X10 and can be used as an
example.
46
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Technical Specifications
12
Technical Specifications
Figure 8:
Physical Dimensions (top view)
The physical dimensions of the phyCORE-MPC5676/57xx are represented in Figure 8. The
module’s profile is max. 10 mm thick, with a maximum component height of 3.0 mm on the
bottom (connector) side of the PCB and approximately 5.0 mm on the top
(microcontroller) side. The board itself is approximately 1.5 mm thick.
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47
phyCORE®- MPC5676/57xx [KSP-0180-0]
Additional specifications:
Dimensions:
Weight:
Storage temperature:
Operating temperature:
Humidity:
Operating voltage:
Power consumption:
58 mm x 82 mm
32g
-40°C to +125°C
0°C to +70°C (commercial)
-40°C to +85°C (industrial)
-40°C to +125°C (automotive)
95% r.F. not condensed
VCC 3.3 V +/- 5%
VCC 5 V +/- 5%
TBD
These specifications describe the standard configuration of the phyCORE-MPC5676/57xx as
of the printing of this manual.
48
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Technical Specifications
Connectors on the phyCORE-MPC5676/57xx:
Manufacturer
Samtec
Number of pins per contact rows
Samtec part number (lead free)
phyCORE-Connector X1 / X2:
180 pins (2 rows of 90 pins each)
REF-177858-01
Number of pins per contact rows
Samtec part number (lead free)
FPGA -Connector X3:
160 pins (2 rows of 80 pins each)
REF-178708-03
The following list shows the receptacle sockets that correspond to the connectors
populating the underside of the phyCORE—MPC5676R. The given connector height
indicates the distance between the two connected PCBs when the module is mounted on
the corresponding carrier board. In order to get the exact spacing, the maximum
component height (3 mm) on the bottom side of the phyCORE must be subtracted.
Connector height 5 mm
Manufacturer
Number of pins per contact row
Samtec part number (lead free)
PHYTEC part number (lead free)
Samtec
180 pins (2 rows of 90 pins each)
REF-177863-03
VM248
Manufacturer
Number of pins per contact row
Samtec part number (lead free)
PHYTEC part number (lead free)
Samtec
160 pins (2 rows of 80 pins each)
REF-178709-03
VM245
Please refer to the corresponding data sheets and mechanical specifications provided by
Samtec (www.samtec.com).
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phyCORE®- MPC5676/57xx [KSP-0180-0]
13
Hints for Integrating and Handling the phyCORE-MPC5676/57xx
13.1 Integrating the phyCORE-MPC5676/57xx
Besides this hardware manual much information is available to facilitate the integration of
the phyCORE-MPC5676/57xx into customer applications.
1.
2.
the design of the standard phyCORE Carrier Board can be used as a reference for any
customer application
many answers to common questions can be found at
http://www.phytec.de/de/support/faq/faq-phyCORE-MPC56xx_57xx.html, or
http://www.phytec.eu/europe/support/faq/faq-phyCORE-MPC56xx_57xx.html
13.2 Handling the phyCORE-MPC5676/57xx
•
Modifications on the phyCORE Module
Removal of various components, such as the microcontroller and the standard quartz, is
not advisable given the compact nature of the module. Should this nonetheless be
necessary, please ensure that the board as well as surrounding components and sockets
remain undamaged while de-soldering. Overheating the board can cause the solder pads
to loosen, rendering the module inoperable. Carefully heat neighboring connections in
pairs. After a few alternations, components can be removed with the solder-iron tip.
Alternatively, a hot air gun can be used to heat and loosen the bonds.
Caution!
If any modifications to the module are performed, regardless of their nature, the
manufacturer guarantee is voided.
•
Integrating the phyCORE into a Target Application
Successful integration in user target circuitry greatly depends on the adherence to the
layout design rules for the GND connections of the phyCORE module. For maximum EMI
performance we recommend as a general design rule to connect all GND pins to a solid
ground plane. But at least all GND pins neighboring signals which are being used in the
application circuitry should be connected to GND.
50
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14
The phyCORE- MPC5676R on the phyCORE Carrier Board
PHYTEC phyCORE Carrier Boards are fully equipped with all mechanical and electrical
components necessary for the speedy and secure start-up and subsequent communication
to and programming of applicable PHYTEC System on Module (SOM) modules. phyCORE
Carrier Boards are designed for evaluation, testing and prototyping of PHYTEC System on
Module in laboratory environments prior to their use in customer designed applications.
The phyCORE Carrier Board supports the following features for the phyCORE-MPC5676/57xx
modules:
• Power supply circuits to supply the phyCORE-MPC5676/57xx and the peripheral devices
of the carrier board
• 5V Power Supply Input (X9)
• all Signals of X1/X2/3 phyCORE-MPC5676/57xx are available on expansion connector
X1A, X1B and X1B1, X1B2 for phyCORE-connector signals X1
X2A, X2B and X2B1, X2B2 for phyCORE-connector signals X2
X2, X3 for FPGA-Connector X3
• Switch (BOOTCFG1) to configure the boot mode of the MPC5676R
• 2 x DB9-Female (P2) for RS232 Interface (SCIA bottom/ SCI B top)
• 2 x DB9-male (P1) for High integrated CAN Interface (CANA bottom/ CANB top)
• 10/100Mbit Ethernet interface (L3)
• 4 x user LEDs (D1-D4) connected to MPC GPIOs
• 1 x user push button (S1) connected to IRQ of MPC
• 1x Resesitor (Poti) (RT1) connected to a Analog Input of MPC
• 1 x Reset push button (RESET1)
• 1x 38-pin MICTOR connector for Nexus Trace (X10)
• JTAG interface for programming and debugging MPC
• JTAG_FPGA interface for programming and debugging FPGA
14.1
Concept of the phyCORE Carrier Board
The phyCORE Development Board KSP-0180-B0 provides a flexible development platform
enabling quick and easy start-up and subsequent programming of the
phyCORE-MPC5676/57xx System on Module (SOM). The Development Board design allows
easy connection of additional expansion boards featuring various functions that support
fast and convenient prototyping and software evaluation.
The following sections contain specific information relevant to the operation of the
phyCORE-MPC5676/57xx mounted on the phyCORE Development Board PCM-979.
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.2 Overview of the phyCORE Carrier Board Peripherals
The phyCORE Carrier Board is depicted in Figure 9. It is equipped with the components and
peripherals listed in Table 18, Table 19, Table 20 and Table 21. For a more detailed
description of each peripheral refer to the appropriate chapter listed in the applicable
table. The following figures highlight the location of each peripheral for easy
identification.
X2A2
X2A1
X8
X2B2
X2B1
C22
C1
JP6
R7
R8
D4
JP1
JP2
JP3
JP4
C14
R11
JP5
R20
TP1
C20
R21
L5
C19
R17
U3
C17
C18
R26
C11
C15
C13
C12
C16
L4
R27
L3
D3
R14 R12
D2
D5
C10
R16
D1
X10
R15 R13
R6
R25 R24
R5
RESET1
S1
C2
R19
X9
X2
L1
C7
C4
C5
C21
X7
P2
R1
Q2
X4
F
R4
X3
X5
X6
Q1
L2
R9
U2
R10
C9
U1
C8
J1
C3
P1
X1
M
RT1
R3
R2
X1A2
R23
C6
R22
BOOTCFG1
X1A1
X1B2
X1B1
Figure 9:
52
phyCORE Carrier Board Overview of Connectors, LEDs and Buttons (top view)
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.2.1
Connectors and Pin Header
Table 18 lists all available connectors on the phyCORE Carrier Board. Figure 9 highlights
the location of each connector for easy identification.
Reference
Designator
See
Section
Description
X6
X7
X8
X9
phyCORE-Connector for mounting the
phyCORE-MPC5676/57xx
phyCORE-Connector for mounting the
phyCORE-MPC5676/57xx
Expansion connector with signals from FPGA
Connector
Expansion connector with signals from FPGA
Connector
FPGA-Connector for mounting the
phyCORE-MPC5676/57xx
FPGA JTAG Connector
MPC JTAG Connector
5V Wall-Adapter Input
Optional 5V Power input connector
X10
38-pin MICTOR connector for Nexus Trace
L3
P2
P1
X1A2, X1A1,
X1B2, X1B1
X2A2,X2A1,
X2B2, X2B1
RJ45 Input Jack 10/100 Mbit Ethernet Interface
RS232 interface, DB-9F
CAN interface, DB-9M
Expansion connector with signals from phyCOREConnector X1
Expansion connector with signals from phyCOREConnector X2
X1
X2
X3
X4
X5
Table 18:
phyCORE Carrier Board Connectors and Pin Headers
Caution!
Ensure that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller User's
Manual/Data Sheets. As damage from improper connections varies according to use and
application, it is the user‘s responsibility to take appropriate safety measures to ensure
that the module connections are protected from overloading through connected
peripherals.
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.2.2
Switches
The phyCORE Carrier Board is populated with some switches which are essential for the
operation of the phyCORE-MPC5676/57xx module on the carrier board. Figure 9 shows the
location of the switches and push buttons.
Button
See
Section
Description
S1
RESET1
user push button (S1) connected to IRQ of MPC
System Reset Button – system reset signal
generation
BOOTCFG1 DIP-switch – boot mode selection
Table 19:
S1
phyCORE Carrier Board Push Buttons Descriptions
Pressing this button will toggle the EMIOS14_IRQ0 pin (X2A28) of the phyCORE
microcontroller LOW and a interrupt can be detected
RESET1
S3
Issues a system reset signal. Pressing this button will toggle the /RESET pin
(X2A8) of the phyCORE microcontroller LOW, causing the controller to reset.
This DIP-switch allows to change the booting mode of the phyCORE-MPC5676/57xx.
14.2.3
LEDs
The phyCORE Carrier Board is populated with numerous LEDs to indicate the status of the
various USB-Host interfaces, as well as the different supply voltages. Figure 9 shows the
location of the LEDs. Their function is listed in the table below:
LED
Color
Description
D1
red
user LEDs connected to MPC GPIO179
D2
red
user LEDs connected to MPC GPIO180
D3
red
user LEDs connected to MPC GPIO181
D4
red
user LEDs connected to MPC GPIO182
Table 20:
54
See
Section
phyCORE Carrier Board LEDs Descriptins
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.2.4
Analog Input Potentiometer
The Analog Input Potentiometer RT1 enables variation of a Volatge (0V-5V),
that can be measured with MPC Analog Input EQADC_ANB1 pin X1A49 of the phyCOREConnector
The Poti is connected with
EQADC_VRHB = 5V pin X1A50 of the phyCORE-Connector
EQADC_VRLB = 0V pin X1A51 of the phyCORE-Connector
14.2.5
Jumpers
The phyCORE Carrier Board comes pre-configured with removable jumpers (JP) and solder
jumpers (J). The jumpers allow the user flexibility of configuring a limited number of
features for development constraint purposes. Table 21 below lists the jumpers, their
default positions, and their functions in each position. Figure 10 depicts the jumper pad
numbering scheme for reference when altering jumper settings on the development board.
Figure 11provides a detailed view of the phyCORE Carrier Board jumpers and their default
settings. In these diagrams a beveled edge indicates the location of pin 1.
Before making connections to peripheral connectors it is advisable to consult the
applicable section in this manual for setting the associated jumpers.
removable jumper
e.g.: JP1
Figure 10:
e.g.: JP14
solder jumper
e.g.: J9
e.g.: J32
Typical Jumper Numbering Scheme
Table 21 provides a comprehensive list of all carrier board jumpers. The table only provides
a concise summary of jumper descriptions. For a detailed description of each jumper see
the applicable chapter listing in the right hand column of the table.
If manual modification of the solder jumpers is required please ensure that the board as
well as surrounding components and sockets remain undamaged while de-soldering.
Overheating the board can cause the solder pads to loosen, rendering the board
inoperable. Carefully heat neighboring connections in pairs. After a few alternations,
components can be removed with the solder-iron tip. Alternatively, a hot air gun can be
used to heat and loosen the bonds.
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55
phyCORE®- MPC5676/57xx [KSP-0180-0]
X2A2
X2A1
X8
X2B2
X2B1
C22
C1
JP6
D1
R7
D2
R8
D3
D4
X10
R26
JP5
L3
R11
C20
R20
R21
L5
C19
R17
U3
C17
C18
R14 R12
C14
JP1 JP2 JP3 JP4
TP1
C11
C15
C13
C12
C16
L4
R27
C10
R16
D5
R15 R13
R6
R25 R24
R5
RESET1
S1
C2
R19
X9
X2
L1
C7
C4
C5
C21
X7
P2
R1
Q2
X4
F
R4
X3
X5
X6
Q1
L2
R9
U2
R10
C9
U1
C8
J1
C3
P1
X1
M
RT1
R3
R2
X1A2
R23
C6
R22
BOOTCFG1
X1A1
X1B2
X1B1
Figure 11:
56
phyCORE Carrier Board Jumper Locations (top view)
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
The following conventions are used in the Jumper column of jumper Table 21.
• J = solder jumper
• JP = removable jumper
Jumper/
Setting
Description
See
Section
JP1
Connects red user LED1 to MPC GPIO179
1+2 Connects red user LED1 to MPC GPIO179
open LED1 not connected to MPC GPIO179
Connects red user LED2 to MPC GPIO180
JP2
1+2 Connects red user LED2 to MPC GPIO180
open LED2 not connected to MPC GPIO180
Connects red user LED3 to MPC GPIO181
JP3
1+2 Connects red user LED3 to MPC GPIO181
open LED3 not connected to MPC GPIO181
Connects red user LED4 to MPC GPIO182
JP4
1+2 Connects red user LED4 to MPC GPIO182
open LED4 not connected to MPC GPIO182
Connects pull down to NEX_/EVTO
JP6
1+2
Pull down conneted to NEX_/EVTO
Enables “Baud Rate Detection serial boot mode”
Open NEX_/EVTO not connected to pull down
J1
Connection of Clock for 38-PinMictor Connector X10_6
1+2 ENGCLK from MPC is connected to X10_6
2+3 CLKOUT from MPC is connected to X10_6
Table 21:
phyCORE Carrier Board Jumper Descriptions
Note:
Detailed descriptions of the assembled connectors, jumpers and switches can be found in
the following chapters.
© PHYTEC Messtechnik GmbH 2015
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.3 Functional Components on the phyCORE Carrier Board
This section describes the functional components of the phyCORE Carrier Board supporting
the phyCORE-MPC5676/57xx. Each subsection details a particular connector/interface and
associated jumpers for configuring that interface.
14.3.1
phyCORE- MPC5676R SOM Connectivity (X1, X2, X3)
X2A2
X2A1
X8
X2B2
X2B1
C22
C1
JP6
R7
R8
D4
JP1
JP2
JP3
JP4
C14
R11
R26
C20
JP5
R20
R21
X2
L5
C19
R17
U3
C17
C18
TP1
C11
C15
C13
C12
C16
L4
R27
C7
L1
C4
C5
C21
L3
D3
R14 R12
D2
D5
C10
R16
D1
X10
R15 R13
R6
R25 R24
R5
RESET1
S1
C2
R19
X9
X7
P2
R1
Q2
X6
X5
X4
F
R4
X3
Q1
L2
R9
U2
R10
C9
U1
C8
J1
C3
P1
X1
M
RT1
R3
R2
X1A2
R23
C6
R22
BOOTCFG1
X1A1
X1B2
X1B1
Figure 12:
phyCORE- MPC5676R SOM Connectivity to the Carrier Board
Connectors X1 , X2 and X5 on the carrier board provide the phyCORE System on Module
connectivity. The connector is keyed for proper insertion of the SOM.
Figure 12 above shows the location of connectors X1 , X2, X5 along with the pin numbering
scheme as described in section 2.
Caution!
Samtec connectors guarantee optimal connection and proper insertion of the phyCOREMPC5676R. Please make sure that the phyCORE-MPC5676/57xx is fully plugged into the
matting connectors of the carrier board. Otherwise individual signals may have a bad, or
no contact.
58
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.3.2
Power (X8, X9)
X2A2
X2A1
X8
X2B2
X2B1
C22
C1
R7
R8
D4
JP1
JP2
JP3
JP4
C14
R11
JP5
R20
TP1
C20
R21
L5
C19
R17
U3
C17
C18
R26
C11
C15
C13
C12
C16
L4
R27
L3
D3
R14 R12
D2
D5
C10
R16
D1
X10
R15 R13
R6
R25 R24
R5
R19
JP6
C2
RESET1
S1
X9
X2
L1
C7
C4
C5
C21
X7
P2
R1
Q2
X4
F
R4
X3
X5
X6
Q1
L2
R9
U2
R10
C9
U1
C8
J1
C3
P1
X1
M
RT1
R3
R2
X1A2
R23
C6
R22
BOOTCFG1
X1A1
X1B2
X1B1
Figure 13:
Powering Scheme
The primary input power of the phyCORE-MPC5676/57xx Carrier Board comes from either
the wall adapter jack X8 (+5 V @3A), or connector X9 (+5V input current @3A).
The phyCORE MPC5676/57xx and and periphery components are supplied with 5V
from X8 or X9 and 3.3V. The 3.3 are generated from an Switching regulator U3 on the
carrier board.
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.3.2.1 Wall Adapter Input (X8)
Caution!
Do not use a laboratory adapter to supply power to the carrier board! Power spikes during
power-on could destroy the phyCORE module mounted on the carrier board! Do not change
modules or jumper settings while the carrier board is supplied with power!
Permissible input voltage at X8: 5 V DC regulated (3A).
The required current load capacity of the power supply depends on the specific
configuration of the phyCORE mounted on the carrier board An adapter with a minimum
supply of 3A is recommended.
Polarity:
+5 VDC
≥ 3000 mA
--
Center Hole
2.5 mm
+
5.0 mm
GND
Figure 14:
60
Power Connector corresponding to Wall Adapter Input X12
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.3.3
First Serial Interface at Socket P2A
Socket P2A is the bottom socket of the double DB-9 connector at P2. The following
description is based on a module configuration that utilizes the on-board RS-232
transceivers for the first serial interface.
1
6
2
7
3
8
4
9
5
Figure 15:
14.3.4
Pin 2 TXDA
Pin 3 RXDA
Pin 5 GND
Pin Assignment of P2A as First RS-232 (Front View)
Second Serial Interface at Socket P2B
Socket P2B is the top socket of the double DB-9 connector at P2.
1
6
Pin 2 TXDB
2
7
Pin 3 RXDB
3
8
4
9
Pin 5 GND
5
Figure 16:
Pin Assignment of P2B as Second RS-232 (Front View)
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.3.5
First CAN Interface at Plug P1A
Plug P1A is the bottom plug of the double DB-9 connector at P1.
P1A is connected to the first FlexCAN interface (FlexCAN A)
The carrier Board is populated with the CAN transceiver for FlexCAN A
1
6
2
7
3
8
4
9
5
Figure 17:
Pin 6 GNDPin 2 CANLA
Pin 7 CANHA
Pin 3 GND
Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on carrier Board, Front View)
14.3.6 Second CAN Interface at Plug P1B
Plug P1B is the upper plug of the double DB-9 connector at P1.
P1B is connected to the second FlexCAN interface (FlexCAN B)
The carrier Board is populated with the CAN transceiver for FlexCAN B
1
6
2
7
3
8
4
9
5
Figure 18:
62
Pin 6 GND
Pin 2 CANLB
Pin 7 CANHB
Pin 3 GND
Pin Assignment of the DB-9 Plug P1B (CAN Transceiver on carrier Board, Front View).
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.3.7
Ethernet Connectivity (X28)
The Ethernet interface of the phyCORE is accessible at the RJ-45 connector (L3) on the
carrier board. Due to its characteristics this interface is hard-wired and can not be
configured via jumpers. The LEDs for LINK (green) and SPEED (yellow) indication are
integrated in the connector.
14.3.8
User programmable LEDs
The phyCORE Carrier Board provides 4 red user programmable LEDs.
The following table lists all user programmable LEDs.
LED
D1
D2
D3
D4
Table 22:
Color
red
red
red
red
Description
User LED connected to MPC GPIO179 (see
User LED connected to MPC GPIO180 (see
User LED connected to MPC GPIO181 (see
User LED connected to MPC GPIO182 (see
JP1, Table 21)
JP1, Table 21)
JP1, Table 21)
JP1, Table 21)
User Programmable LEDs on the Carrier Board
© PHYTEC Messtechnik GmbH 2015
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.3.9
Boot Mode Selection (BOOTCFG1)
The boot mode DIP Switch BOOTCFG1 is provided to configure the boot mode of the
phyCORE-MPC5676/57xx after reset. This DIP Switch allows choosing different boot
sources. The following table gives an overview of the different boot sources. Refer to
section 5 for more information on the boot configuration.
Note:
The following table describes only settings suitable for the phyCORE-MPC5676/57xx. Other
settings must not be used with the phyCORE-MPC5676/57xx.
DIP Switch
BOOTCFG0
pinX1B4 BOOTCFG1 pinX1B5
Bootsource
1=ON;2=ON
0
0
Boot from internal flash memory
1=ON;2=OFF
0
1
FlexCAN / eSCI boot
Table 23:
10
:
64
phyCORE Carrier Board DIP Switch S3 Descriptions 10
Default settings are in bold blue text
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.3.10
System Reset Button (RESET1)
The phyCORE Carrier Board is equipped with a system reset button RESET1.
Pressing this button will toggle the /RESET pin (X2A8) of the phyCORE microcontroller
LOW, causing the controller to reset.
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.3.11
FPGA_JTAG Connector
The development board KSP-0180-Bx provides a JTAG 14-pin connector X6 for the XILINX
FPGA on the phyCORE-MPC5676/57xx.
Signal
DGND
DGND
DGND
DGND
DGND
DGND
DGND
Pin
Number
1
3
5
7
9
11
13
JTAG FPGA
Connector
o o
o o
o o
o o
o o
o o
o o
Signal
2 VCC_3V3
4
F_TMS
6
F_TCK
8
F_TDO
10 F_TDI
12
NC
14
NC
Table 24:
Pin Assignment of the JTAG_FPGA connector X6
14.3.12
JTAG/Once/Nexus Debug Interface
The development board KSP-0180-Bx provides two debug connectors.
X7 - reduced JTAG/OnCE/Nexus port to a 14-pin header connector (2.54 mm pin spacing)
X10 - full JTAG/OnCE/Nexus port to a 38-pol Mictor AMP 767054-1
14.3.13
Reduced JTAG/OnCE/NEXUS Pin Header Connector X
The 14-pin header connector at X7 on the Development Board enables connection of a
simple external debug interface device (e.g. P&E Wiggler).
Signal
Pin
Number
NEX_TDI
1
NEX_TDO
3
NEX_TCK
5
NC
7
/RESET
9
VCC_3V3
11
NEX_/RDY
13
Table 25:
66
JTAG/OnCE
Connector
o o
o o
o o
o o
o o
o o
o o
Signal
2
DGND
4
DGND
6
DGND
8
NC
10 NEX_TMS
12
DGND
14 NEX_JCOM
P
Pin Assignment of the Reduced JTAG/OnCE/Nexus Pin Header X7
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.3.14
Full JTAG/OnCE/NEXUS Pin Header Connector X10
The pin header connector at X3 supports a standard 38-pin NEXUS debug connection
(connector type AMP 767054-1) to various emulator probes (e.g. iSystem IC3000)
MPC Signal
NEX_MDO12
NEX_MDO14
NEX_MDO9
Vendor
/RESET
NEX_TDO
NEX_MDO10
NEX_TCK
NEX_TMS
NEX_TDI
NEX_JCOMP
NEX_MDO11
Vendor
NC
NC
NC
NC
NC
NC
Table 26:
Pin Number Pin Number MPC Signal
1
2
NEX_MDO13
3
4
NEX_MDO15
5
6
ENGCLK
refer to
Jumper J1
7
8
NEX_MDO8
9
10
NEX_/EVTI
11
12
VCC_3V3
13
14
NEX_/RDY
15
16
NEX_MDO7
17
18
NEX_MDO6
19
20
NEX_MDO5
21
22
NEX_MDO4
23
24
NEX_MDO3
25
26
NEX_MDO2
27
28
NEX_MDO1
29
30
NEX_MDO0
31
32
NEX_/EVTO
33
34
NEX_MCKO
35
36
NEX_/MSEO
1
37
38
NEX_/MSEO
0
Pin Assignment of the Full JTAG/OnCE/Nexus Pin Header X10
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phyCORE®- MPC5676/57xx [KSP-0180-0]
14.3.15
phyCORE-MPC5676/57xx Expansion Connector
Most of the phyCORE-MPC5676/57xx Signals are available at the Expansion Connector of
the The Development Board KSP-0180-B0.
The Expansion connectors on the Devolpment Board are ( see Figure 19):
X1A2, X1A1, X1B2, X1B1 Expansion connector with signals from phyCORE-Connector X1
X2A2,X2A1, X2B2, X2B1 Expansion connector with signals from phyCORE-Connector X2
X3,X4 Expansion connector with signals from FPGA Connector
Please refer to section 14.3.16 for the Pin Assignment of the Expansion connectors
X8
X2A2
X2A1
X2B2
X2B1
C22
C1
JP6
R7
R8
D4
JP1
JP2
JP3
JP4
C14
R11
JP5
R20
TP1
C20
R21
L5
C19
R17
U3
C17
C18
R26
C11
C15
C13
C12
C16
L4
R27
L3
D3
R14 R12
D2
D5
C10
R16
D1
X10
R15 R13
R6
R25 R24
R5
RESET1
S1
C2
R19
X9
X2
L1
C7
C4
C5
C21
X7
P2
R1
F
R4
Q2
X5
X6
X3 X4
Q1
L2
R9
U2
R10
C9
U1
C8
J1
C3
P1
X1
M
RT1
R3
68
R23
C6
Figure 19:
R22
BOOTCFG1
R2
X1A2
X1A1
X1B2
X1B1
Expansion Connector location on the Development Board KSP-0150-B0
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
14.3.16
Schematic of Carrier Board KSP-0180-Bx
This section shows the schematic of the Development Board KSP-0150-B0.
© PHYTEC Messtechnik GmbH 2015
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phyCORE®- MPC5676/57xx [KSP-0180-0]
Figure 20:
70
page 2/5 of KSP-0150-B0 schematic
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
Figure 21:
page 3/5 of KSP-0150-B0 schematic
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phyCORE®- MPC5676/57xx [KSP-0180-0]
Figure 22:
72
page 4/5 of KSP-0150-B0 schematic
© PHYTEC Messtechnik GmbH 2015
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The phyCORE®- MPC5676/57xx on the phyCORE Carrier Board
Figure 23:
page 5/5 of KSP-0150-B0 schematic
© PHYTEC Messtechnik GmbH 2015
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73
phyCORE®- MPC5676/57xx [KSP-0180-0]
15
Date
Revision History
Version
numbers
09.03.2015 Manual
L-807e_0
74
Changes in this manual
First draft, Preliminary documentation.
Describes the phyCORE-MPC5676/57xx
with phyCORE Carrier Board.
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Index
Index
Full JTAG/OnCE/NEXUS Connector X10 ..... 67
/
/CS0 ................................................. 38
/CS1 ................................................. 38
/CS3 ................................................. 44
/RESET .............................................. 35
GND Connection .................................. 50
H
Humidity............................................ 48
1
10/100 Mbit/s Ethernet ........................ 43
I
Internal Flash ..................................... 37
iSystem IC3000 ................................... 67
3
3.3V Supply .......................................... 6
5
5V Supply............................................. 6
B
Block Diagram....................................... 3
Boot Configuration .............................. 36
Boot Mode Selection ............................ 36
Booting ............................................. 36
Burst SRAM ........................................ 37
C
CAN Interface ..................................... 42
D
Device U18 ......................................... 40
Dimensions ........................................ 48
E
EEPROM ........................................ 37, 39
EEPROM Write Protection....................... 39
EMC ................................................... ix
Ethernet Controller .............................. 43
Ethernet Transformer ........................... 43
Expansion Connector............................ 68
External Flash ..................................... 37
F
F_VCCBATT ......................................... 35
Features .............................................. 1
First CAN Interface ............................... 62
First Serial Interface............................. 61
FPGA connector................................... 40
FPGA System Logic Device...................... 40
© PHYTEC Messtechnik GmbH 2015
G
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J
J1 27
J10 ................................................... 28
J11 ................................................... 29
J12 ................................................... 29
J13 ................................................... 29
J14 ................................................... 29
J15 ................................................... 30
J16 ................................................... 30
J17 ................................................... 30
J18 ................................................... 30
J19 ................................................... 30
J2 27
J20 ................................................... 30
J21................................................... 30
J22 ................................................... 31
J23,24............................................... 31
J25 ................................................... 31
J26 ................................................... 31
J27,J28,J29 ....................................... 31
J3 27
J30 .............................................. 32, 39
J31 ................................................... 32
J32 ................................................... 32
J34 ................................................... 32
J35 ................................................... 33
J36 ................................................... 33
J37 ................................................... 33
J38 ................................................... 33
J39 ................................................... 33
J4 27
J5 27
J6 28
75
phyCORE®- MPC5676/57xx [KSP-0180-0]
J7 28
J8 28
J9 28
JTAG ................................................. 46
JTAG/OnCE Connector........................... 46
JTAG/OnCE/Nexus................................ 46
JTAG/OnCE/Nexus Debug Interface ......... 66
JTAG_FPGA ......................................... 66
K
KSP-0180-B0 ...................................... 51
L
LAN................................................... 44
LAN921I ............................................ 43
LINK LED ............................................ 63
M
MAC .................................................. 44
MAC Address ....................................... 44
Memory Banks..................................... 38
Memory Configuration .......................... 29
MPC_VSTBY......................................... 35
N
Nexus ................................................ 46
NEXUS ............................................... 67
O
OnCE ................................................. 46
Operating Temperature ......................... 48
Operating Voltage................................ 48
P
P&E Wiggler........................................ 66
phyCORE Carrier Board
BOOTCFG1....................................... 64
Connectors ..................................... 53
Features ......................................... 51
Peripherals ..................................... 52
RESET1........................................... 65
schematic....................................... 69
Switches......................................... 54
X1 58
X2 58
X28 ............................................... 63
X5 58
X8 59
X9 59
76
phyCORE-Connector ...............................7
Physical Dimensions ............................. 47
Pin Description......................................7
Pinout
X1 9, 10, 11, 12, 13
X2 14, 15, 16, 17, 18
X3 19, 20, 21, 22, 23
Plug P1A ............................................ 62
Plug P1B ............................................ 62
Power Consumption.............................. 48
Power Requirements............................. 34
Power Supply ........................................6
R
Real-Time Clock ................................... 45
Reduced JTAG/OnCE/NEXUS Connector X7 66
Reset................................................. 35
RS-232 .............................................. 61
TTL Signals...................................... 31
S
Second CAN Interface ........................... 62
Second Serial Interface ......................... 61
Serial Interfaces .................................. 41
SMT Connector ......................................7
Socket P2A (First RS-232)...................... 61
Socket P2B (Second RS-232) .................. 61
SPEED LED .......................................... 63
SPI EEPROM ........................................ 39
SPI Flash ....................................... 37, 39
SPI Interface....................................... 42
SRAM ................................................ 38
SRAM, Capacity.................................... 38
Standard Flash Memory
External ......................................... 37
Start-up System Configuration ............... 36
Storage Temperature ............................ 48
Supply Voltage .................................... 34
Synchronous Burst SRAM....................... 38
System Memory ................................... 37
T
Technical Specifications ........................ 47
U
U100/U101 ........................................ 37
U102 ................................................. 38
U102/U103 ........................................ 38
U103 ................................................. 38
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Index
U17 .................................................. 41
U19 .................................................. 39
U6 .................................................... 39
UART................................................. 41
W
V
X3 67
X7 66
X8 46
VBAT ................................................. 35
Voltage Supervisor............................... 35
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Weight .............................................. 48
X
77
phyCORE®- MPC5676/57xx [KSP-0180-0]
78
© PHYTEC Messtechnik GmbH 2015
L-807e_0
Suggestions for Improvement
Document:
Document number:
phyCORE®-MPC5676/57xx
L-807e_0, March 2015
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Fax : +49 (6131) 9221-33
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Ordering No. L-807e_0
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