Data Transfer to On-chip Peripheral Modules with DMAC

APPLICATION NOTE
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
Introduction
This application note provides an example of transferring data to on-chip peripheral modules with the direct memory
access controller (DMAC) of the SH7263/SH7203.
Target Device
SH7263/SH7203
Contents
1.
Introduction ....................................................................................................................................... 2
2.
Description of Sample Application .................................................................................................... 3
3.
Sample Program ............................................................................................................................... 9
4.
Documents for Reference ............................................................................................................... 15
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Data Transfer to On-chip Peripheral Modules with DMAC
1.
1.1
Introduction
Specification
• DMAC channel 1 is used to transfer data from external memory to the transmit FIFO data register (SCFTDR) in the
serial communication interface with FIFO (SCIF channel 0) in order to transmit character string data.
• SCIF transmit FIFO data empty transfer requests (on-chip peripheral module request) are used to request DMA
transfer.
1.2
Modules Used
• Direct memory access controller (DMAC channel 1)
• Serial communication interface with FIFO (SCIF channel 0)
1.3
Applicable Conditions
• Microcontroller:
• Operating Frequency:
• C Compiler:
• Compile Option:
1.4
SH7263/SH7203
Internal clock
200 MHz
Bus clock
66.67 MHz
Peripheral clock 33.33 MHz
SuperH RISC engine family C/C++ compiler package Ver.9.01, from Renesas
Technology
-cpu = sh2afpu -fpu = single -include = "$(WORKSPDIR)\inc"
-object = "$(CONFIGDIR)\$(FILELEAF).obj" -debug -gbr = auto -chgincpath
-errorpath -global_volatile = 0 -opt_range = all -infinite_loop = 0 -del_vacant_loop = 0
-struct_alloc = 1 -nologo
Related Application Notes
• The operation of the reference program for this document was confirmed with the setting conditions described in
the application note: SH7263/SH7203 Initialization Example. Please refer to the application note in combination
with this one.
• Details on SCIF UART transmission are described in the application: SH7263/SH7203 Example Settings for UART
Transmission by the SCIF.
Please refer to the above application notes in combination with this one.
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Data Transfer to On-chip Peripheral Modules with DMAC
2.
Description of Sample Application
In this sample application, the DMAC and on-chip peripheral module requests are used to transfer data from external
memory to the SCIF.
2.1
Operational Overview of Modules Used
When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of
channels, and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC
are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable
as burst mode or cycle-stealing mode.
An overview of the DMAC is given in table 1. Also, a block diagram of the DMAC is shown in figure 1.
Table 1
Overview of DMAC
Item
Number of channels
Address space
Length of transfer data
Maximum transfer
count
Address mode
Transfer request
Bus mode
Priority level
Interrupt request
Description
8 (CH0 to CH7)
Only 4 (CH0 to CH3) can receive external requests.
4 Gbytes
Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)
16,777,216 (24 bits) transfers
Single address mode and dual address mode
Auto request, external request, and on-chip peripheral module request
• SH7203/SH7263
(SCIF: 8 sources, I2C3: 8 sources, ADC: 1 source, MTU2: 5 sources, CMT: 2
sources, USB: 2 sources, FLCTL: 2 sources, RCAN-TL1: 2 sources, SSI: 4
sources, SSU: 4 sources)
• SH7263
(SRC: 2 sources, ROM-DEC: 1 source, SDHI: 2 sources)
Cycle-stealing mode and burst mode
Channel priority fixed mode and round-robin mode
An interrupt request to the CPU is made when half or all of a transfer process is
completed.
DREQ input low/high level detection, rising/falling edge detection
External request
detection
Active levels for DACK and TEND can be set independently
Transfer request
acknowledge
signal/transfer end
signal
Note: For details on the DMAC, refer to the section on the direct memory access controller in the
SH7263/SH7203 Group Hardware Manual.
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Data Transfer to On-chip Peripheral Modules with DMAC
DMAC module
RDMATCR_n
On-chip
memory
Iteration
control
RSAR_n
Register
control
Internal bus
Peripheral bus
On-chip
peripheral
module
DMATCR_n
SAR_n
RDAR_n
Start-up
control
DAR_n
DMA transfer
request signal
CHCR_n
DMA transfer acknowledge signal
HEIn
Interrupt controller
DEIn
Request
priority
control
DMAOR
DMARS0 to DMARS3
External ROM
Bus
interface
External RAM
External device
(memory mapped)
External device
(with acknowledge)
Bus state
controller
DREQ0 to DREQ3
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR:
DMATCR:
RSAR:
SAR:
RDAR:
DAR:
DMA reload transfer count register
DMA transfer count register
DMA reload source address register
DMA source address register
DMA reload destination address register
DMA destination address register
CHCR:
DMAOR:
DMARS0 to DMARS3:
HEIn:
DEIn:
n:
DMA channel control register
DMA operation register
DMA extension resource selectors 0 to 3
DMA transfer half-end interrupt request to the CPU
DMA transfer end interrupt request to the CPU
0, 1, 2, 3, 4, 5, 6, 7
Figure 1 Block Diagram of DMAC
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2.2
Procedure for Setting Used Modules
This section describes the procedure for making initial settings when the DMAC is to be used to transfer data from
memory to on-chip peripheral modules. On-chip peripheral module requests are used for transfer requests. A flowchart
of DMAC initialization is shown in figure 2. For details on registers, refer to the SH7263/SH7203 Group Hardware
Manual.
[1] • Enabling clock supply to the DMAC (STBCR2)
Clear the MSTP8 (module stop 8) bit to 0
[Function] Clock supply to the DMAC
START
[2] • Disabling DMA transfer (CHCRn)
Set standby control register 2
(STBCR2)
[1]
Clear the DE (DMA enable) bit to 0
[Function] Disable DMA transfer
[3] • Setting DMA transfer source address (SARn)
[Function]
Set DMA channel control register
(CHCRn)
[2]
Specify DMA transfer source address
[4] • Setting DMA transfer source reload address (RSARn)
[Function]
Specify DMA transfer source address to be reloaded
[5] • Setting DMA transfer destination address (DARn)
[Function]
Set DMA source address control
register (SARn)
[3]
Specify DMA transfer destination address
[6] • Setting DMA transfer destination reload address (RDARn)
[Function]
Specify DMA transfer destination address to be reloaded
[7] • Setting the DMA transfer count (DMATCRn)
Set DMA reload source
address register (RSARn)
[4]
[Function]
Set the DMA transfer count
[8] • Setting the DMA transfer reload count (RDMATCRn)
[Function]
Set the DMA transfer count to be reloaded
[9] • Setting the DMA transfer mode (CHCRn)
Set DMA destination address
register (DARn)
[5]
Set DMA reload destination
address register (RDARn)
[6]
Set DMA transfer count register
(DMATCRn)
[7]
Set DMA reload transfer
count register (RDMATCRn)
[8]
Set DMA channel control register
(CHCRn)
[9]
Set DMA extension resource selector [10]
registers (DMARS0 to DMARS3)
Set the TC (transfer count mode) bit
[Function] "0": Transfer data once for each transfer request
(When the SCIF or IIC3 is selected as the transfer
request source)
"1": Transfer data for the count specified in DMATCRn for
each transfer requests
Set the RLDSAR (SAR reload function enable/disable) bit
[Function] Enables/disables reload function to SAR and DMATCR
Set the RLDDAR (DAR reload function enable/disable) bit
[Function] Enables/disables reload function to DAR and DMATCR
Set the DM (destination address mode) bits
[Function] Select whether the DMA transfer destination address is
incremented or decremented
Fix/increment/decrement the DMA transfer destination address
Set the SM (source address mode) bits
[Function] Select whether the DMA transfer source address is
incremented or decremented
Fix/increment/decrement the DMA transfer source address
Set the RS (resource select) bits to B'1000.
[Function] Select DMA extension resource selector (DMA transfer
request source)
Set the TB (transfer bus mode) bit
[Function] Select a DMA transfer bus mode.
Cycle-stealing mode/burst mode
Note: When TC is set to 0, select cycle-stealing mode
Set the TS (transfer size) bits
[Function] Specify the DMA transfer size
Set the IE (interrupt enable) bit
[Function] Enable/disable interrupt requests
[10] • Specifying settings for DMA transfer requests from on-chip peripheral
Set DMA operation register
(DMAORn)
[11]
modules (DMARS0 to DMARS3)
[Function] Select the DMA transfer request source
SCIF, IIC3, A/D converter, MTU2, or CMT
[11] • Setting the DMA operation register (DMAOR)
Set DMA channel control register
(CHCRn)
END
[12]
Read from the AE (address error flag) bit and then clear it to 0
[Function] Clear the address error flag
Read from the NMIF (NMI flag) bit and then clear it to 0
[Function] Clear the NMI flag
Set the DME (DMA master enable) bit to 1
[Function] Enable DMA transfer on all the channels
[12] • Enablling DMA transfer (CHCRn)
Set the DE (DMA enable) bit to 1
[Function] Start DMA transfer
Figure 2 Flowchart of Initializing DMAC
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2.3
Operation of Sample Program
In this sample program, SCIF transmit FIFO data empty transfer requests are made to activate DMAC channel 1, and to
transfer data from external memory to the transmit FIFO data register (SCFTDR) on SCIF channel 0. The data written
to SCFTDR on SCIF channel 0 are transmitted in UART mode. An operation timing of the sample program is shown in
figure 3.
DMA transfer using SCIF transmit FIFO data empty transfer requests
(Timing of requesting data transfer from external memory to the SCIF transmit FIFO data register: a
transfer request is made when the number of data in transmit FIFO becomes 0)
One data
transfer
One data
transfer
Read
DMAC1
One data
transfer
Read
Write
Bus
mastership
Read
One data
transfer
Read
Write
Write
Write
Internal signal
Internal signal
Internal signal
CPU
Write to SCIF transmit FIFO data register (SCFTDR)
Write
Internal bus
Read
External bus
Write
Read
Write
Read
Write
Read
DMA transfer request
(When the DMA master
enable bit is 1)
SCIF transmit FIFO data empty transfer request (on-chip peripheral request)
DMA transfer count
register (DMATCR)
H'29
H'28
H'27
H'00
Transfer end flag (TE)
[Legend]
: DMA request acknowledge
Figure 3 Operation Timing of Sample Application
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2.4
Processing Procedure of Sample Program
In this sample program, character string data stored in external memory are transferred by DMA to the transmit FIFO
data register (SCFTDR) on SCIF channel 0, and then are transmitted in UART mode.
The register settings for the sample program are listed in table 2. The macro definitions used in this sample program are
also listed in table 3. A flowchart of the sample program is illustrated in figure 4.
Table 2
Register Settings for Sample Program
Register Name
Standby control
register 2 (STBCR2)
DMA channel control
register 1 (CHCR1)
Address
H'FFFE 0018
Setting Value
H'00
Description
MSTP8 = "0": DMAC operates
H'FFFE 101C
H'0000 0000
H'0000 1800
DE = "0": Disables DMA transfer
TC = "0": Transfers data once for each
DMA transfer request
RLDSAE = "0":
Disables SAR reload function
RLDDAR = "0":
Disables DAR reload function
DM = "B'00": Fixes destination address
SM = "B'01": Increments source address
RS = "B'1000": Extension resource selector
TB = "0": Cycle-stealing mode
TS = "B'00": Byte transfer
IE = "0": Disables interrupt request
DE = "1": Enables DMA transfer
Start address of transfer source:
Start address of character string stored in
external memory
Start address of transfer destination:
Address of the SCIF transmit FIFO data
register_1 (SCFTDR_1)
Transfer count: the number of character
string data
H'0000 1801
Address where
character string
data are stored
H'FFFE 800C
DMA source address
register_1 (SAR1)
H'FFFE 1010
DMA destination
address register_1
(DAR1)
DMA transfer count
register_1 (DMATCR1)
H'FFFE 1014
DMA operation register
(DMAOR)
DMA extension
resource selector
(DMARS0)
H'FFFE 1200
Number of
character string
data
H'0001
H'FFFE 1300
H'0081
H'FFFE 1018
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DME = "1": Enables DMA transfer on all the
channels
MID = "B'100000"
RID = "B'01"
Set to SCIF_0 transmit FIFO data empty
transfer request
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Data Transfer to On-chip Peripheral Modules with DMAC
Table 3
Macro Definitions Used in Sample Program
Macro Definition
DMA_SIZE_BYTE
DMA_SIZE_WORD
DMA_SIZE_LONG
DMA_SIZE_LONGx4
DMA_INT_DISABLE
DMA_INT_ENABLE
Setting Value
H'0000
H'0001
H'0002
H'0003
H'0000
H'0010
Description
Byte transfer
Word transfer
Longword transfer
16-byte transfer
DMA transfer end interrupt disabled
DMA transfer end interrupt enabled
START
Initialize DMAC/enable transfer
io_init_dma1()
Initialize SCIF/enable
transmission and transmission
interrupts
io_init_scif()
No
DMA transfer
completed?
Yes
END
Figure 4 Flowchart of Sample Program
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3.
Sample Program
1. Sample Program Listing "main.c" (1)
1 /*""FILE COMMENT""**************************************************************
2 *
3 *
System Name : SH7203 Sample Program
4 *
File Name : main.c
5 *
Contents
: Data transfer to on-chip peripheral modules with DMAC
6 *
Version
: 1.00.00
7 *
Model
: M3A-HS30
8 *
CPU
: SH7203
9 *
Compiler
: SHC9.1.1.0
10 *
note
: Sample program for transferring data from the SCIF by DMAC1
11 *
12 *
<CAUTION>
13 *
This sample program is for reference
14 *
and its operation is not guaranteed.
15 *
Customers should use this sample program for technical reference
16 *
in software development.
17 *
18 *
The information described here may contain technical inaccuracies or
19 *
typographical errors. Renesas Technology Corporation and Renesas Solutions
20 *
assume no responsibility for any damage, liability, or other loss rising
21 *
from these inaccuracies or errors.
22 *
23 *
Copyright(C) 2007 Renesas Technology Corp. All Rights Reserved
24 *
AND Renesas Solutions Corp. All Rights Reserved
25 *
26 *
history
: 2007.12.27 ver.1.00.00
27 *""FILE COMMENT END""*********************************************************/
28 #include <string.h>
29 #include "iodefine.h"
/* iodefine.h is automatically created by HEW */
30
31 /* ==== Macro declaration ==== */
32 /* ==== DMAC Settings ==== */
33 #define DMA_SIZE_BYTE
0x0000u
34 #define DMA_SIZE_WORD
0x0001u
35 #define DMA_SIZE_LONG
0x0002u
36 #define DMA_SIZE_LONGx4
0x0003u
37 #define DMA_INT_DISABLE
0x0000u
38 #define DMA_INT_ENABLE
0x0010u
39 #define DMA_INT
(DMA_INT_ENABLE >> 4u)
40
41 /* ==== Prototype declaration ==== */
42 void main(void);
43 void io_init_dma1(void *src, void *dst, size_t size, unsigned int mode);
44 void io_dma1_stop(void);
45 void io_init_scif0(int);
46
47 /* ==== Type declaration ==== */
48 /* SCIF baud rate setting */
49 typedef struct
{
50
unsigned char scbrr;
51
unsigned short scsmr;
52 } SH7203_BAUD_SET;
53
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2. Sample Program Listing "main.c" (2)
54 /* ---- Values for baud rate specification ---- */
55
enum{
56
CBR_1200,
57
CBR_2400,
58
CBR_4800,
59
CBR_9600,
60
CBR_19200,
61
CBR_31250,
62
CBR_38400,
63
CBR_57600,
64
CBR_115200
65
};
66
67 /* ==== Table of register setting values ==== */
68
static SH7203_BAUD_SET scif_baud[] = {
69
{214, 1},
/* 1200bps (-0.07%) */
70
{106, 1},
/* 2400bps ( 0.39%) */
71
{214, 0},
/* 4800bps (-0.07%) */
72
{106, 0},
/* 9600bps ( 0.39%) */
73
{ 53, 0},
/* 19200bps (-0.54%) */
74
{ 32, 0},
/* 31250bps ( 0.00%) */
75
{ 26, 0},
/* 38400bps (-0.54%) */
76
{ 17, 0},
/* 57600bps (-0.54%) */
77
{ 8, 0}
/*115200bps (-0.54%) */
78
};
79
/* Character string to be transmitted */
80
const signed char data[] = "SCIF request DMAC Sample Software SH7203.¥r¥n";
81
82
/*""FUNC COMMENT""*******************************************************
83
* Outline
: Sample Program Main (UART transmission with use of DMAC)
84
*----------------------------------------------------------------------85
* Include
: #include <string.h>
86
*----------------------------------------------------------------------87
* Declaration
: void main(void);
88
*----------------------------------------------------------------------89
* Function
: The character string data stored in external memory is DMA transferred
90
*
: to the SCIF transmit FIFO data register. The DMAC is activated
91
*
: by an SCIF transmit interrupt request.
92
*----------------------------------------------------------------------93
* Argument
: void
94
*----------------------------------------------------------------------95
* Return Value
: void
96
*----------------------------------------------------------------------97
* Notice
:
98
*""FUNC COMMENT END""***************************************************/
99
void main(void)
100 {
101
/* ==== Enabling DMAC initialization/transfer ==== */
102
io_init_dma1(data, (void *)&SCIF0.SCFTDR.BYTE ,sizeof(data),
103
DMA_SIZE_BYTE | DMA_INT_DISABLE);
104
/* On-chip peripheral module request (SCIF transmit interrupt request) */
105
/* Data transfer from external memory to SCIF transmit */
106
/* Data transfer to data registers */
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3. Sample Program Listing "main.c" (3)
107
/* ==== Enabling SCIF0 initialization/transfer ==== */
108
io_init_scif0(CBR_115200);
109
/* Communication mode :UART mode */
110
/* Bit rate :115.2Kbps */
111
/* TXI interrupt is generated when data in transmit FIFO is one byte */
112
/* ==== Disabling DMA transfer ==== */
113
io_dma1_stop();
114
while(1){
115
/* Program end */
116
}
117
}
118 /*""FUNC COMMENT""*******************************************************
119 * Outline
: Initialization for DATA transfer between memory areas with DMAC
120 *----------------------------------------------------------------------121 * Include
: #include "iodefine.h"
122 *----------------------------------------------------------------------123 * Declaration : io_init_dma1(void *src, void *dst, size_t size, int mode);
124 *----------------------------------------------------------------------125 * Function
: The DMAC transfers the amount of data specified by “size”.
126 *
: from the source address “src” to the destination address “dst.”
127 *
: Transfer is performed using requests from the SCIF1.
128 *
: “mode” is specified for transfer size and interrupt used/not used.
129 *----------------------------------------------------------------------130 * Argument
: void *src
: Source address
131 *
: void *dst
: Destination address
132 *
: size_t size
: Transfer size (byte)
133 *
: unsigned int mode: Transfer mode, specifies the following with logical OR.
134 *
:
DMA_SIZE_BYTE (0x0000) Byte transfer
135 *
:
DMA_SIZE_WORD (0x0001) Word transfer
136 *
:
DMA_SIZE_LONG (0x0002) Longword transfer
137 *
:
DMA_SIZE_LONGx4(0x0003) 16-byte transfer
138 *
:
DMA_INT_DISABLE(0x0000) DMA transfer end interrupt disabled
139 *
:
DMA_INT_ENABLE (0x0010) DMA transfer end interrupt disabled
140 *----------------------------------------------------------------------141 * Return Value : void
142 *----------------------------------------------------------------------143 * Notice
: Operation is not guaranteed when the alignment of the source/destination.
144 *
: address is inconsistent.
145 *
: When interrupts are used, interrupt routines must be registered.
146 *""FUNC COMMENT END""***************************************************/
147 void io_init_dma1(void *src, void *dst, size_t size, unsigned int mode)
148 {
149
unsigned int ts;
150
unsigned long ie;
151
152
ts = mode & 0x3u;
153
ie = (mode & 0x00f0u ) >> 4u;
154
155
/* ====Setting standby control register 2(STBCR2) ==== */
156
CPG.STBCR2.BIT.MSTP8 = 0x0;
/* Cancel DMAC module top mode */
157
158
/* ---- Setting DMA channel control register ---- */
159
DMAC.CHCR1.BIT.DE = 0ul;
/* Disable DMA transfer */
160
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4. Sample Program Listing "main.c" (4)
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/* ----Setting DMA source address register---- */
DMAC.SAR1.LONG = (unsigned long)src;
/* ----Setting DMA reload source address register---- */
DMAC.RSAR1.LONG = (unsigned long)src;
/* ----Setting DMA destination address register---- */
DMAC.DAR1.LONG = (unsigned long)dst;
/* ----Setting DMA reload destination address register---- */
DMAC.RDAR1.LONG = (unsigned long)dst;
/* ----Setting DMA transfer count register---- */
/* ----Setting DMA reload transfer count register---- */
switch(ts){
case DMA_SIZE_BYTE:
DMAC.DMATCR0.LONG = size;
DMAC.RDMATCR0.LONG = size;
break;
case DMA_SIZE_WORD:
DMAC.DMATCR0.LONG = size >> 1u;
DMAC.RDMATCR0.LONG = size >> 1u;
break;
case DMA_SIZE_LONG:
DMAC.DMATCR0.LONG = size >> 2u;
DMAC.RDMATCR0.LONG = size >> 2u;
break;
case DMA_SIZE_LONGx4:
DMAC.DMATCR0.LONG = size >> 4u;
DMAC.RDMATCR0.LONG = size >> 4u;
break;
default:
break;
}
/* Specify transfer count (1/1) */
/* Specify transfer count (1/2) */
/* Specify transfer count (1/4) */
/* Specify transfer count (1/16) */
/* ----Setting DMA channel control register---- */
DMAC.CHCR1.LONG = 0x00001800ul | (ts << 3u) | (ie << 2u) ;
/*
bit31
: TC DMATCR transfer0--------Transfer once
bit30
: reserve 0
bit29
: RLDSAR OFF : 0------------Disable SAR reload function
bit28
: RLDDAR OFF : 0------------Disable DAR reload function
bit27-24 : reserve 0
bit23
: DO over run0 : 0---------Unused
bit22
: TL TEND low active : 0---Unused
bit21
: reserve 0
bit20
: TEMASK : TE set mask : 0-Disable DMA transfer when TE bit is set
bit19
: HE :0--------------------Unused
bit18
: HIE :0-------------------Unused
bit17
: AM :0--------------------Unused
bit16
: AL :0--------------------Unused
bit15-14 : DM1:0 DM0:0--------------Fix destination address
bit13-12 : SM1:0 SM0:1--------------Increment source address
bit11-8
: RS : auto request : B'1000DMA extension resource selector
bit7
: DL : DREQ level : 0 ------Unused
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5. Sample Program Listing "main.c" (5)
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bit6
bit5
bit4-3
bit2
bit1
bit0
*/
:
:
:
:
:
:
DS
TB
TS
IE
TE
DE
:
:
:
:
:
:
DREQ select :0 Low level
cycle :0--------------transfer size:B'00--interrupt enable:0--transfer end---------DMA enable bit:0-----
Unused
Cycle-stealing mode
Byte transfer
Disable interrupt
DMA
/* ----Setting DMA extension resource selector 0---- */
DMAC.DMARS0.BIT.CH1MID = 0x20;
/* MID = SCIF0 */
DMAC.DMARS0.BIT.CH1RID = 0x01;
/* RID = Transmission
/* ----Setting DMA operation register---- */
DMAC.DMAOR.WORD &= 0xfff9u;
/* Clear AE,NMI bits
if(DMAC.DMAOR.BIT.DME == 0ul){
DMAC.DMAOR.BIT.DME = 1ul;
}
*/
*/
/* Enable DMA transfer on all channels
*/
/* ----DMA transfer execution---- */
DMAC.CHCR1.BIT.DE = 1ul;
/* Enable DMA transfer
*/
}
/*""FUNC COMMENT""*******************************************************
* Outline
: DMAC stop
*----------------------------------------------------------------------* Include
: #include "iodefine.h"
*----------------------------------------------------------------------* Declaration : void io_dma1_stop(void);
*----------------------------------------------------------------------* Function : Detects the end of DMA transfer and disables DMA transfer
*----------------------------------------------------------------------* Argument : void
*----------------------------------------------------------------------* Return Value: void
*----------------------------------------------------------------------* Notice
:
*""FUNC COMMENT END""***************************************************/
void io_dma1_stop(void)
{
/* Detecting end of transfer */
while(DMAC.CHCR1.BIT.TE == 0ul){
/* Wait until the TE bit is set*/
}
/* ----Stopping DMA transfer---- */
DMAC.CHCR1.BIT.DE = 0ul;
/* Disable DMA1 transfer */
}
/*""FUNC COMMENT""*******************************************************
* Outline
: Initial setting of SCIF0 as an asynchronous (UART) transmit module
*----------------------------------------------------------------------* Include
: #include "iodefine.h"
*----------------------------------------------------------------------* Declaration : void io_init_scif0(int bps);
*-----------------------------------------------------------------------
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Page 13 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
6. Sample Program Listing "main.c" (7)
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* Function
: Initializes SCIF0
*
: Asynchronous (UART)/ 8 bits/ No parity/ 1 stop bit/ RTS/CTS disabled
*
: Baud rate is specified by argument bps
*
:
*----------------------------------------------------------------------* Argument : int bps : Value for baud rate specification
*----------------------------------------------------------------------* Return Value: void
*----------------------------------------------------------------------* Notice
: The baud rate setting values given in this program are those when
*
: the peripheral module clock (Pf) frequency is 33 MHz. If a different
*
: clock is used, the baud rate setting values must be changed.
*""FUNC COMMENT END""***************************************************/
void io_init_scif0(int bps)
{
/* ====Power-down mode cancellation==== */
/* ----Setting standby control register 4 (STBCR4)---- */
CPG.STBCR4.BIT.MSTP47 = 0;
/* Start clock supply to SCIF0 */
/* ====SCIF0 initialization==== */
/* ----Setting serial control register (SCSCRi)---- */
SCIF0.SCSCR.WORD = 0x0000;
/* Stop transmission/reception by SCIF0
*/
/* ----Setting FIFO control register (SCFCRi)---- */
SCIF0.SCFCR.BIT.TFRST = 1;
/* Reset transmit FIFO */
/* ----Setting serial control register (SCSCRi)---- */
SCIF0.SCSCR.BIT.CKE = 0x0;
/* B'00: Internal clock */
/* ----Setting serial mode register (SCSMRi)---- */
SCIF0.SCSMR.WORD = scif_baud[bps].scsmr;
/* Communication mode
/* Character length
/* Parity enable
/* Parity mode
/* Stop bit length
/* Clock select
0:
0:
0:
0:
0:
:
Asynchronous mode
*/
8-bit data
*/
Disable addition and check */
Even parity
*/
1 stop bit
*/
Table value
*/
/* ----Setting bit rate register (SCBRRi)---- */
SCIF0.SCBRR.BYTE = scif_baud[bps].scbrr;
/* ----Setting FIFO control register (SCFCRi)---- */
SCIF0.SCFCR.WORD = 0x0030;
/* Transmit FIFO data count trigger
: Number of data
/* Modem control enable
:
/* Transmit FIFO data register reset :
/* Loopback test
:
bytes = 0 */
Disabled */
Disabled */
Disabled */
/* ====Setting pin function controller (PFC)==== */
PORT.PECRL1.BIT.PE1MD = 0x3; /* Switch to TxD0 pin */
/* ----Setting serial control register (SCSCRi) ---- */
SCIF0.SCSCR.BIT.TIE = 1;
/* Enable SCIF0 transmit interrupt */
SCIF0.SCSCR.BIT.TE = 1;
/* Enable SCIF0 transmission */
}
/* End of File */
REJ06B0734-0100/Rev.1.00
April 2008
Page 14 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
4.
Documents for Reference
• Software Manual
SH-2A, SH2A-FPU Software Manual
The most up-to-date version of this document is available on the Renesas Technology Website.
• Hardware Manual
SH7203 Group Hardware Manual
SH7263 Group Hardware Manual
The most up-to-date version of this document is available on the Renesas Technology Website.
REJ06B0734-0100/Rev.1.00
April 2008
Page 15 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
Website and Support
Renesas Technology Website
http://www.renesas.com/
Inquiries
http://www.renesas.com/inquiry
csc@renesas.com
Revision Record
Rev.
1.00
Date
Apr.17.08
Description
Page
Summary
—
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
REJ06B0734-0100/Rev.1.00
April 2008
Page 16 of 17
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
This document is provided for reference purposes only so that Renesas customers may select the appropriate
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programs, algorithms, and application circuit examples.
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application circuit examples, is current as of the date this document is issued. Such information, however, is
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 2008. Renesas Technology Corp., all rights reserved.
REJ06B0734-0100/Rev.1.00
April 2008
Page 17 of 17