Canon | VM E 2 | Introduction to VME / VXI / VXS Standards - W-IE-NE

Introduction to VME / VXI / VXS Standards
ANSI VITA VME Standard (VME32/VME64)
The number of connectors used determines the address
space of the card and the card size. Uncommitted pins on
the connectors provide support for application specific
busses and rear transition modules. 9-U modules may
provide a third connector for application specific use.
VME bus is a computer bus standard, originally developed
for the Motorola 68000 line of CPUs, but later widely used
for many applications and standardized by the IEC as
ANSI/IEEE 1014-1987. It is physically based on the
Eurocard sizes, mechanics and connectors, but uses its own
signaling system. It was first developed in 1981 and
continues to see widespread use today.
Since it’s creation 25 years ago the original VME bus
standard has seen a number of extensions and add-ons.
Year
1982
Standard
VME32
rev.A
1987
1987
ANSI/IEEE
1014-1987
VXI
1990
VME430
1982
VME64
1996
VME64x
1998
VME64xP
2003
2003
VME 2eSST
VXS
Features
32bit parallel bus, A32, D32
max 40MB/s
3 row DIN connectors P1, P2
Standard adopted based on
VME Rev. C
VME extension for
instrumentation
CERN nuclear VME
30 pin Paux connector
additional -5.2V, -2V, +/-15V
Multiplexed 64 bit, A64, D64
max 80MB/s
New 160 pin connectors,
metric P0 connector
EMC, ESD (IEEE 1101.10)
additional +3.3V (opt. 48V)
VIPA (Physics), redefined P0
add. 9U x 400mm size
Up to 320MB/s
Serial high speed fabric (P0)
Page
22
22
25
28
22
29
30
30
31
VME card sizes and connector positions
VME modules come in three sizes. 3U x160mm cards have
one backplane connector (J1) and have a 24-bit/16-bit
address/data space. 6U x 160mm cards are the most
common ones and have two backplane connectors (J1 &
J2) allowing for 32 bits of address/data space. Large 9U x
400mm cards also have 32 address/data lines and 2
connectors (J1 & J2).
History
In 1979 Jack Kister and John Black, engineers at Motorola,
began creating a new processor bus system to go with the
MC68000 CPU. As more designers became involved and
the system was further refined, it later became known as
the VME bus.
The new VME bus had many advantages and was soon
adopted as a standard for a number of other companies
that were involved with the Motorola 68000.
The first
Official VME bus standard was released by the IEC as IEC
821 and by ANSI and IEEE as ANSI/IEEE 1014-1987.
Development continues today primarily driven by the VME
International Trade Association (VITA).
Each VME card is 20.3mm wide. Twenty-one cards will fit
into a 19 rack mounted VME crate.
VME crates, or chassis, provide the mechanical support
with card guides and the VME bus backplane into which
the modules are plugged. The crate typically has a power
supply, which provides power to the backplane. Standard
VME voltages are 5V and +/-12V. For proper cooling the
crate should be outfitted with a cooling fan or fan tray.
VME originally featured a 24-bit address bus and 16-bit
data bus. Several updates to the system allow wider bus
widths. The current VME64 standard defines a full 64-bit
bus in 6U-sized cards and 32-bit in 3U cards. The VME64
protocol has a maximum data transfer rate of 80 MByte/s.
Bus Description
Address Lines
The VME bus has 31 address lines. The first 23 lines are
present on J1 and the remainder being on J2. The lowest
address bit (A0) is implied by the transfer cycle and is not
present on the backplane. VME64 can multiplex address
and data lines allowing 31 address bits on J1 and an
additional 32 address bits on J2.
In the late 1990's, VITA defined synchronous protocols to
improve the data transfer bandwidth on existing VME64
backplanes. A new 2eSST protocol was approved in
ANSI/VITA 1.5 in 1999, which allows up to 320 Mbytes/s.
Many extensions have been added to the VME interface,
providing 'sideband' channels of communication in parallel
to VME itself. Some examples are IP Module, RACEway
Interlink, SCSA, Gigabit Ethernet on VME64x Backplanes,
PCI Express, RapidIO, StarFabric and InfiniBand and VXI.
Data Lines
The VME bus has 32 data lines. The low order 16 data
lines are on J1, the high order 16 on J2. VME modules
with only J1 can only do 16 bit wide transfers, while those
with both J1 and J2 can do 32 bit wide transfers. VME64
modules multiplex address and data allowing 32 bit
transfers on J1, and 64 bit wide transfers when both
connectors are present.
VME is a multi-master bus. A bus arbiter, in the left-most
slot (slot 1) determines which of several competing
masters acquires the bus. Arbitration can be prioritized
with 7 bus request levels or round robin. VME also defines
a flexible prioritized interrupt subsystem.
Hardware Description
VME card mechanical dimensions meet the Eurocard
Standard. The connection between the module and the
backplane is made by two 96-pin DIN 41612 connectors.
22
J1/P1 (top)
Pin No.
Row A
D00
D01
D02
D03
D04
D05
D06
D07
GND
SYSCLK
GND
DS1*
DS0*
WRITE*
GND
DTACK*
GND
AS*
GND
IACK*
IACKIN*
IAOUT*
AM4
A07
A06
A05
A04
A03
A02
A01
-12 V
+5 V
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
J2/P2 (bottom)
Row B
BBSY*
BCLR
ACFAIL*
BG0IN*
BG0OUT*
BG1IN*
BG1OUT*
BG2IN*
BG2OUT*
BG1IN*
BG3OUT*
BR0*
BR1*
BR2*
BR3*
AM0
AM1
AM2
AM3
GND
SERCLK
SERDAT
GND
IRQ7*
IRQ6*
IRQ5*
IRQ4*
IRQ3*
IRQ2*
IRQ1*
+5V STDBY
+5V
Row C
D08
D09
D10
D11
D12
D13
D14
D15
GND
SYSFAIL*
BERR*
SYSRESET*
LWORD*
AM5
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
+ 12 V
+5V
Row A
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
Row B
+5 V
GND
Reserved
A24
A25
A26
A27
A28
A29
A30
A31
GND
+5 V
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
GND
+5V
Row C
User defined
ABC
User defined
User defined
User defined
User defined 1
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined 32
User defined
User defined
User defined DIN 41612
User defined
96-pin
VME Backplane connectors and pin layout
Address Strobe Line
The Address strobe Line (AS*) is driven low by a master to
indicate it is driving a valid address.
Bus Arbitration
A VME Bus master requests the bus by asserting one of
the bus request lines BR0*-BR3*. The slot 1 bus arbiter
(some masters include bus arbitration logic) will grant the
bus by asserting the corresponding bus grant signal
(BG0OUT-BG3OUT). The arbiter can cyclically scan the
BRn* lines (round robin arbitration), or treat higher
numbered BRn* lines as being a higher priority request
(prioritized arbitration).
Data Acknowledge Line
DTACK* is an open-collector signal generated by slaves.
The falling edge of this signal indicates that valid data is
available on the data bus during a read cycle, or that the
slave has accepted data during a write cycle. The rising
edge of DTACK indicates when the slave’s data is no
longer present at the end of a read cycle.
The bus grant forms a daisy chain. Each module monitors
BG0IN-BG3IN if it is not requesting the bus it reproduces
these signals on BG0OUT-BG3OUTwhich are inputs to the
next slot to the right on the backplane. If the module is
requesting the bus on the corresponding BRn* it claims
the bus by driving BBSY*.
Controller
Module 1
BG0OUT
BR 0
BG0IN
Module 2
BG0OUT
BG0IN
Interrupt Handling
Any module on the VME bus may request an interrupt by
driving one of the interrupt request lines IRQ1*-IRQ7*.
Any bus master module can respond to any of the
interrupt request lines by arbitrating for the bus, asserting
IACK* and echoing the interrupt level on A1-A3. The bus
arbiter places the IACKOUT* on an interrupt daisy chain
(similar to the bus grant daisy chain). The interrupting
module will then provide a status-id on the data bus that
allow the interrupt handler to distinguish between
interrupters sharing the same interrupt request level.
Requestor
BG0OUT
BR 0
BG0IN
VME Backplane
Controller
Bus request and grant daisy chain
Data Strobe Lines
DS0* and DS1* are tri-state signals used in conjunction
with LWORD* to indicate how many byte locations are
being accessed (1, 2, 3, or 4). For byte transfers these
signals imply bit zero of the address. During a write cycle,
the falling edge of the first data strobe indicates that valid
data is available on the data bus. For read cycles, the
rising edge of the first data strobe indicates that data has
been accepted from the Addressed slave.
Module 1
IACKOUT
Module 2
IACKOUT
IACKOUT
IRQ 0
IRQ 0
IACKIN
IACKIN
A1-A3
IRQ 0
VME Backplane
VME Interrupt handling
23
Requestor
IACKIN
System Fail Line
The SYSFAIL* line is an open-collector signal that indicates
when a failure has occurred in the system. Any board in
the system can generate this signal.
Bus Busy and Bus Clear
The master that has been granted the bus assert BBSY* to
indicate the bus is in use. In priority arbitration, the bus
arbiter can assert BCLR* if a bus request at a higher
priority than the currently granted master is present. The
current bus master is then expected to release the bus
when convenient by releasing BBSY, to allow the new
arbitration cycle to complete.
System Reset
The SYSRESET requests that all bus modules perform
power-up initialization.
AC FAIL
The ACFAIL line is driven low when there is an AC failure
for the VME power supply.
Write Line
WRITE* is a three-state signal generated by the master to
indicate whether the data transfer cycle is a read or write.
A high level indicates a read operation; a low level
indicates a write operation.
Bus Errors
The bus arbiter often implements address timeout logic
and asserted BERR* if no module responds to an address
cycle within the timeout. Slaves may also assert BERR* if
they are not able to honor a requested cycle (e.g. they do
not support the requested address modifier).
Clock
SYSCLK is a totem pole signal that provides a constant 16
MHz clock signal from the system controller.
Address Modifiers
VME provides for large number of data transfer types. The
VME Address modifier lines (AM0*-AM5*) are asserted by
a bus master during an address cycle to indicate the type
of data transfer requested.
VME Bus Timing
Address Cycle
AM Address Description
0x3F
24
A24 supervisory block transfer (BLT)
0x3E
24
A24 supervisory program access
0x3D
24
A24 supervisory data access
0x3C
24
A24 supervisory 64-bit block transfer (MBLT)
0x3B
24
A24 non-privileged block transfer (BLT)
0x3A
24
A24 non-privileged program access
0x39
24
A24 non-privileged data access
0x38
24
A24 non-privileged 64-bit block transfer, MBLT
0x37
40
A40BLT [MD32 data transfer only]
0x35
40
A40 lock command (LCK)
0x34
40
A40 access
0x32
24
A24 lock command (LCK)
0x2F
24
CR / CSR space
0x2D
16
A16 supervisory access
0x2C
16
A16 lock command (LCK)
0x29
16
A16 non-privileged access
2eVME for 3U bus modules (address size in
0x21 32/64
XAM code)
2eVME for 6U bus modules (address size in
0x20 32/64
XAM code)
0x0F
32
A32 supervisory block transfer (BLT)
0x0E
32
A32 supervisory program access
0x0D
32
A32 supervisory data access
0x0C
32
A32 supervisory 64-bit block transfer (MBLT)
0x0B
32
A32 non-privileged block transfer (BLT)
0x0A
32
A32 non-privileged program access
0x09
32
A32 non-privileged data access
0x08
32
A32 non-privileged 64-bit block transfer MBLT
0x05
32
A32 lock command (LCK)
0x04
64
A64 lock command (LCK
0x03
64
A64 block transfer (BLT)
0x01
64
A64 single access transfer
0x00
64
A64 64-bit block transfer (MBLT)
During an address cycle, a VME bus master holds IACK
high and places the address and AM [0-5] codes on the
bus. Once the lines have been valid for at least 35ns the
Master drives the Address Strobe [AS*] indicating a valid
address is on the bus. For interrupt acknowledge cycles
the IACK line is driven low, the interrupt priority is
encoded on A1-A3 and the AM lines are ignored.
Data Cycle
VME Data cycles can be writes (Master to Slave) or reads
(Slave to Master).
Regardless of the cycle type, the
Master uses LWORD*, DS0* and DS1*to indicate the width
of the transfer. At least one of DS0*, DS1* will be driven.
For a write cycle, DS0* and DS1* also indicate that the
Master has stable data on the data bus for the slave. In a
read cycle, DS0* and DS1* indicate the master is ready to
receive data from the slave. In a write cycle, DTACK* is
asserted by the slave when it has accepted the data
transfer. In a read cycle DTACK* indicates the slave has
stable data on the bus for the master. Regardless of the
cycle type, the release of both DS0* and DS1*, and
subsequent release of DTACK* by the slave indicates
completion of the cycle.
List of VME address modifiers
Long Word
The LWORD* line is used in conjunction with DS0*, DS1*,
to specify the width of a data transfer.
Serial Data
The SERCLK and SERDAT lines implement a serial data
bus. SERCLK provides a synchronization clock for the
serial data that can be transferred on SERDAT.
24
enhancements towards data acquisition and automated
test applications. Especially the VXI mechanical and power
supply specifications provide an excellent electrical
environment for low-level, high accuracy analog circuitry.
Data Transfer
Larger card size to increase VXI board space, provides
space for sophisticated analog circuits, signal
conditioning and better analog to digital isolation
1.2” module spacing, fully shielded mechanical design
of modules to minimize noise pickup and provides
more front panel space,
3 different module sizes (B, C, D-size)
Mandatory analog power supply voltages (-5.2V, -2V,
+/-24V) and strict limits for power supply noise
Specifications for cooling and measurement of cooling
performance (VXI-8) to allow use of high power
electronic circuits in VXI modules.
VXI Backplane provides precision clocks and trigger
lines for common clocking and triggering / event
handling across VXI modules
Geographic addressing, dynamic address allocation
Local bus for inter-module communication
Power-up self test (status register bit indicates
whether the module passed self-test or not).
Definition of module standard registers including:
manufacturer ID, Serial Number, Module Hardware /
Firmware Revision Level
Data transfer requires an address and a data cycle.
Address cycles may overlap the previous data cycle.
Block Transfers
VXI System and Sub-system
A VXI bus system can have up to 256 devices, including
one or more VXI bus subsystems. A VXI bus subsystem
consists of a central timing /controller module in Slot 0
(Slot-0 controller) with up to twelve additional instrument
modules. The Slot 0 module is responsible for managing
system resources such as the VXI bus mandated timing
generation, the VME bus system controller functions and a
possible data communication ports such as Ethernet,
RS232 or IEEE 488.
A VME bus BLock Transfer [BLT] consists of a single
Address cycle followed by up to 256 bytes of Data transfer
before another address cycle is required. VME64 adds the
Multiplexed Block Transfer [MBLT]. MBLT transfer data on
both the address and data lines to achieve a 64 bit
transfer width.
Bus Request
The master requesting the bus does so by driving a Bus
Request (BR#*) line low. The VME bus arbiter hands
control of the bus to a master by asserting the
corresponding BG#* line.
VXI Standard (IEEE 1155)
The VXI bus architecture is an open standard platform for
automated test instruments based upon VMEbus, the
Eurocard standards, and other instrumentation standards
such as IEEE-488.2. VXI's core market is in
Telcecommunication, Military and Aerospace automatic
test systems and data acquisition applications.
The original standard for ”VME eXtensions for
Instrumentation System Specification” VXI-1 Revision 1
was introduced in August 1987 by the VXI Bus Consortium
which included companies as Colorado Data Systems,
Hewlett-Packard, Racal Dana, and Tektronix. Revision 3
added VME64 64-bit transfers and features. The VXI-1
specification has been adopted by the IEEE as IEEE Std
1155-1992.
For
more
information
see
http://www.vxibus.org/.
VXI implements the VME bus protocol for data transfers
between modules but implements a number of significant
25
A typical VXI crate has 13 slots (numbered 0 through 12
from the left as viewed from the front). The VXI crate has
provides power for the following DC voltages:
J2/P2 (SLOT 0)
Pin No.
Row A
Row B
01
ECLTRG0
+5 V
02
-2 V
GND
03
ECLTRG1 Reserved
04
GND
A24
05
LBUSA00
A25
06
LBUSA01
A26
07
-5.2 V
A27
08
LBUSA02
A28
09
LBUSA03
A29
10
GND
A30
11
LBUSA04
A31
12
LBUSA05
GND
13
-5.2 V
+5 V
14
LBUSA06
D16
15
LBUSA07
D17
16
GND
D18
17
LBUSA08
D19
18
LBUSA09
D20
19
-5.2 V
D21
20
LBUSA10
D22
21
LBUSA11
D23
22
GND
GND
23
TTLTRG0*
D24
24
TTLTRG2*
D25
25
+5 V
D26
26
TTLTRG4*
D27
27
TTLTRG6*
D28
28
GND
D29
29
RSV2
D30
30
MODID
D31
31
GND
GND
32
SUMBUS
+5V
J2/P2 Pin Layout (Slot 0)
+5V, +/-12V (as per VME spec.),
-5.2V, -2V (for ECL devices / termination),
+/-24V (for analog circuits)
Maximum allowed power supply DC noise levels at 10MHz
bandwidth are 50mVpp with the exception of +/-24V line
(150mVpp). All WIENER VXI crates have lowest noise
power supplies with <10mVpp .
To guarantee proper cooling of all plugged in modules the
VXI crate has to be outfitted with a fan tray. The provided
airflow and distribution has to comply with VXI-8
specification.
There are 3 sizes of VXI modules: B, C and D. B-size
modules are the same size as standard 6U VME modules
and have identical 96-pin DIN connectors P1 and P2. Most
popular is the C-size with the same 6U height but 340mm
deep modules. The D-size module is a triple height
Eurocard (9U) and can be outfitted with an additional P3
connector, which requires a special 9U backplane.
The VXI backplane for B- and C-size applications is a 6U
high monolithic backplane with 13 slots. The pin layout is
identical to VME for the top J1 connector as well as the
center row of the lower J2 connector.
On the J2/P2 outer A and C rows (not used by VME) VXI
adds a 10 MHz ECL clock, ECL and TTL trigger lines, an
analog summing bus, a module identification line, the local
bus and additional DC voltages:
-5.2 V, -2 V, ±24 V and additional +5 V power
10 MHz differential clock
2 parallel ECL trigger lines
8 parallel TTL trigger lines
12 lines of defined local bus (daisy chain)
50
terminated analog summing bus
Module identification pin
VXI D-sized modules have a third connector J3/P3 on the
bottom of the 9U high backplane. This J3/P3 connector
adds of the similar resources as J2/P2. To support higher
performance instrumentation it also includes a 100 MHz
clock and sync signal as well as high precision star" trigger
system where ECL trigger signals are routed through Slot
0 acting as a cross point switch. Further 24 additional lines
of daisy chain local bus are defined on P3/J3.
Additional +5V, -5.2V, -2V, ±24V and ±12V power.
100 MHz differential clock (synchronous with CLK10)
Synchronizing signal for 100 MHz clock edge selection
4 additional ECL trigger lines, (total of 6)
24 additional local bus lines (total of 36)
Star Trigger lines for precision module to module
timing
CLK10 - Differential Clock
CLK10 is a 10 MHz system clock. It is sourced from Slot 0
and distributed to Slots 1-12 on P2. The Slot 0 output is
differential ECL, which is buffered on the backplane and
distributed to each module slot as a single source, single
destination differential ECL signal.
CLK100 – Differential Clock (D-size only)
CLK100 is a 100 MHz system clock distributed via J3/P3. It
is sourced from Slot 0, buffered on the backplane and
distributed to each module slot as a single source, single
destination differential ECL signal. Distribution delays have
to be matched to provide a tight timing relationship
between modules. CLK100 has to be synchronous to
CLK10.
J2/P2 (SLOT 1-12)
Pin
No.
Row A
Row B
Row C
01
02
03
04
05
06
07
08
09
10
ECLTRG0
-2 V
ECLTRG1
GND
LBUSA00
LBUSA01
-5.2 V
LBUSA02
LBUSA03
GND
+5 V
GND
Reserved
A24
A25
A26
A27
A28
A29
A30
CLK10+
CLK10GND
-5.2 V
LBUSC00
LBUSC01
GND
LBUSC02
LBUSC03
GND
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LBUSA04
LBUSA05
-5.2 V
LBUSA06
LBUSA07
GND
LBUSA08
LBUSA09
-5.2 V
LBUSA10
LBUSA11
GND
TTLTRG0*
TTLTRG2*
+5 V
TTLTRG4*
TTLTRG6*
GND
RSV2
MODID
GND
SUMBUS
A31
GND
+5 V
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
GND
+5V
LBUSC04
LBUSC05
-2 V
LBUSC06
LBUSC07
GND
LBUSC08
LBUSC09
-5.2 V
LBUSC10
LBUSC11
GND
TTLTRG1*
TTLTRG3*
GND
TTLTRG5*
TTLTRG7*
GND
RSV3
GND
+24 V
-24 V
J2/P2 Pin Layout (Slot 1-12)
26
Row C
CLK10+
ABC
CLK10GND
-5.2 V
LBUSC00
1
LBUSC01
GND
LBUSC02
LBUSC03
GND
LBUSC04
LBUSC05
-2 V
LBUSC06
LBUSC07
GND
LBUSC08
LBUSC09
-5.2 V
LBUSC10
LBUSC11
GND
TTLTRG1*
TTLTRG3*
GND
TTLTRG5*
TTLTRG7*
GND
32
RSV3
GND
+24 V
DIN 41612
-24 V
96-pin
ABC
1
32
DIN 41612
96-pin
Pin
No.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
J3/P3
Pin
No.
ECLTRG0-5 - ECL Trigger lines
The 6 ECLTRG lines (C-size:0, 1 only) are used as an intermodule timing resource and can be accessed by any VXI
module. These lines are single-ended ECL with 50 ohm
impedance (terminated with 50 to -2 V on backplane).
ECLTRG lines have a set of defined protocols
corresponding to the TTLTRG* protocols.
J3/P3 (SLOT 0)
Row A
Row B
ECLTRG2
+24 V
GND
-24 V
ECLTRG3
GND
-2 V
RSV5
ECLTRG4
-5.2 V
GND
RSV7
ECLTRG5
+5 V
-2 V
GND
STARY12+
+5 V
STARY12- STARY01STARY12+ STARY12STARY11+
GND
STARY11- STARY02STARY11+ STARY11STARY10+
+5 V
STARY10- STARY03STARY10+ STARY10STARY09+
-2 V
STARY09- STARY04STARY09+ STARY09STARY08+
GND
STARY08- STARY05STARY08+ STARY08STARY07+
+5 V
STARY07- STARY06STARY07+ STARY07GND
GND
STARY+
-5.2 V
STARYGND
GND
-5.2 V
CLK100+
-2 V
CLK 100GND
Pin Layout (Slot 0)
Row C
+12 V
-12 V
RSV4
+5 V
RSV6
GND
-5.2 V
GND
STARX01+
STARX01STARX01+
STARX02+
STARX02STARX02+
STARX03+
STARX03STARX03+
STARX04+
STARX04STARX04+
STARX05+
STARX05STARX05+
STARX06+
STARX06STARX06+
GND
STARY+
STARY-5.2 V
SYNC100+
SYNC100-
ABC
1
LOCAL BUS
The Local Bus is a daisy chained bus structure with 36
lines (C-size:12 lines only) which allows several types of
signal levels to be transmitted via this bus. For protection
a keying mechanism is provided. The Local Bus key
provides support for TTL, ECL and analog communication.
Number
1
2
3
4
5
6
Row B
01
ECLTRG2
+24 V
02
GND
-24 V
03
ECLTRG3
GND
04
-2 V
RSV5
05
ECLTRG4
-5.2 V
06
GND
RSV7
07
ECLTRG5
+5 V
08
-2 V
GND
09
LBUSA12
+5 V
10
LBUSA13 LBUSC15
11
LBUSA14 LBUSA15
12
LBUSA16
GND
13
LBUSA17 LBUSC19
14
LBUSA18 LBUSA19
15
LBUSA20
+5 V
16
LBUSA21 LBUSC23
17
LBUSA22 LUBSA23
18
LBUSA24
-2 V
19
LBUSA25 LBUSC27
20
LBUSA26 LBUSA27
21
LBUSA28
GND
22
LBUSA29 LBUSC31
23
LBUSA30 LBUSA31
24
LBUSA32
+5 V
25
LBUSA33 LBUSC35
26
LBUSA34 LBUSA35
27
GND
GND
28
STARX+
-5.2 V
29
STARXGND
30
GND
-5.2 V
31
CLK100+
-2 V
32
CLK100GND
J3/P3 Pin Layout (Slot 1 - 12)
32
DIN 41612
96-pin
SUMBUS
The SUMBUS is an analog summing node that is bussed on
the VXI backplane. Any module can drive it via an analog
current source or receive from this line using a high
impedance receiver. The SUMBUS is terminated to ground
through 50ohm on both ends of the backplane.
Row C
+12 V
-12 V
RSV4
+5 V
RSV6
GND
-5.2 V
GND
LBUSC12
LBUSC13
LBUSC14
LBUSC16
LBUSC17
LBUSC18
LBUSC20
LBUSC21
LBUSC22
LBUSC24
LBUSC25
LBUSC26
LBUSC28
LBUSC29
LBUSC30
LBUSC32
LBUSC33
LBUSC34
GND
STARY+
STARY-5.2 V
SYNC100+
SYNC100-
Range
-0.5 V ... +5.5 V
-5.46 V ... 0.0 V
-5.5 V ... +5.5 V
-16.0 V ... +16.0 V
-42.0 V ... +42.0 V
TTLTRG0-7* - TTL Trigger Lines
These open collector TTL lines are used for inter-module
communication as trigger, handshake, clock or logic state
transmission. Any module, including Slot 0, can drive these
lines and receive information on these lines. Some
standard allocation procedures and protocols as
synchronous (SYNC), asynchronous (ASYNC) and
start/stop (STST) are defined.
J3/P3 (SLOT 1 – 12)
Row A
Class
TTL
ECL
ANALOG LOW
ANALOG MED
ANALOG HIGH
RESERVED
ABC
STARX and STARY
Bi-directional STAR trigger lines provide inter-module
asynchronous communication. Two STAR lines are
connected between each module slot and Slot 0. Slot 0
may provide a cross-point switch that can be programmed
to route signals between any two STARX or STARY lines. It
may also broadcast a signal to a group of STAR lines.
1
SYNC100
Is used to synchronize multiple devices with respect to a
given rising edge of CLK100 in order to provide very tight
time coordination between modules. SYNC100 is
distributed from Slot 0 to slots 1-12, with individual
backplane buffers for each slot.
A Slot 0 module
implementing the SYNC100 function must provide an
arbiter to synchronize external events to CLK100 that
meets the guaranteed setup and hold times for the
SYNC100 signal. This guarantees that all affected modules
will trigger on the same CLK100 clock edge. SYNC100 is
nominally a 10 ns pulse and may be initiated by any type
of external or internal event.
VXI Address Space Definition
VXI assigns non-conflicting portions of the VME bus
address space to its devices. 256 devices may exist in a
VXI system and are referred to by logical device addresses
0 through 255. The VXI bus system configuration space is
the upper 16k of the 64k A16 address space. Each device
is granted a total of 64 bytes in this space.
32
DIN 41612
96-pin
If a device needs more space a dynamic memory
assignment is performed at power-on. The "resource
manager" reads the requirements and assigns the
requested memory space by writing the module's new
27
CL - Clear
Is a bussed differential line terminated like CK lines.
CL
positive logic
CL*
negative logic
VME bus address into the device's offset register. This
method positions a device's additional memory space in
the A24, A32, or A64 address space.
VXI bus Registers
VXI defines standard registers for use as configuration,
communication and memory. VXI modules also have standard
registers to provide manufacturer ID, Serial Number, Module
Hardware / Firmware Revision Level.
Geographical address
VME430 provides geographical addressing on the Jaux
connector via SN1... SN5. The addresses are binary coded
according to the slot numbers as shown in the following
table (NC = No Connection represents H- level and can be
generated by 5k6 resistor on VME module for TTL, e.g.):
The VXI bus specification defines further protocols, command
and event formats and is supplemented by additional
standards such as VXI plug & play to simplify it’s use.
Slot
01
02
03
04
05
06
…
20
21
CERN VME 430 / “Nuclear VME” Standard
In order to make the VME bus suitable for data acquisition
systems in nuclear and high energy physics experiments
and to standardize used electronic equipment the
European Physics Laboratory CERN developed in 1990
several VME crate specifications. These standards defined
the VME crate design; mechanics, power supply and
cooling.
The VME 430 backplane is a monolithic 6U backplane with
3 connector rows J1/Jaux/J2. Both J1 and J2 are outfitted
with 3-row DIN-96pin type connectors with standard VME
pinouts. This provides backwards compatibility, i.e. any
standard VME / VME64 module will work in a CERN VME
430 compliant crate. The CERN VME 430 backplane adds a
third dataway and connector row Jaux. Jaux was added in
the middle between J1 and J2 to provide additional pins
for DC power, geographic addressing and 3 differential
bussed signals (clocks / timing).
01
02
03
04
05
06
07
08
09
10
Row B
GND
GND
GND
GND
GND
GND
-2 V
CE
-5,2 V
- 5,2 V
Row C
SN2
SN4
GND
CK
SG
CL
-2 V
+ 15 V
- 5,2V
- 5,2V
SN4
GND
GND
GND
GND
GND
GND
…
GND
GND
SN5
GND
GND
GND
GND
GND
GND
…
NC
NC
VME 430 DC / Power Supply Requirements
In addition to the regular VME DC voltages of 5V and +/12V the CERN VME 430 specifies also –5.2V and –2V (for
fast ECL logic) as well as optionally +/-15V. These
voltages are supplied via the Jaux/Paux connectors.
VME430 compliant modules often require these voltages
for proper operation and may not function in a standard
VME crate.
+5V, +/-12V (as per VME spec.),
-5.2V, -2V (for ECL devices / termination),
+/-15V (optional, for analog circuits)
As of today the original V422/V430 crates are not
produced anymore however, there are still many modules
and VME crates available and in use, which comply with
the VME430 backplane.
Jaux/Paux (middle)
SN3
GND
GND
GND
NC
NC
NC
…
NC
NC
SG - Start / Stop Gate
Is a bussed differential line terminated like CK lines for
timing applications:
SG
positive logic
SG*
negative logic
The CERN V422 standard described a 21 slot standard
VME (VME64) crate. The V430 “VME 430 - nuclear
VME” specification used a modified backplane to add bus
lines and DC voltages needed for data acquisition
applications.
Row A
SN1
SN3
SN5
CK*
SG*
CL*
-2 V
- 15 V
- 5,2 V
- 5,2 V
SN2
GND
NC
NC
GND
GND
NC
…
GND
GND
Geographic address coding
CERN VME crates were a modular designed, consisting of a
VME bin with backplane and card cage with plug-in fan
tray and power supply. This modularity made it easy to
quickly exchange failing fan trays and power supplies.
Pin No.
SN1
NC
GND
NC
GND
NC*
GND
…
GND
NC
VME Fan tray / cooling
A front side plug-in fan tray provides air flow for VME
module cooling. The air temperature increase shall not
exceed 10C. The fan tray has to be equipped with a fan
fail detection system, which issues on a fan fail a local and
remote warning and also can shut down the DC.
ABC
CERN Monitoring and Remote Control
According to the CERN V 430 specification for remote
control and monitoring the following signal lines are
available at a monitoring and control connector (CANON
Type DAC 15-S-FO), which is placed at the bin backside
1
Line
STATUS
FAN FAILURE
A.C.POWER INHIBIT
SYSRESET
0V SIGNAL
DISABLE
GND
CERN V430 remote control
10
30-pin
DIN 41612
CERN V430 Jaux Pin Layout
CE - Clean Earth
Un-bussed line without termination
Description
status monitor output
fan failure output
remote on / off
manual system reset
common control return line
global trip-off disable input
ground
& monitoring signals
STATUS and FAN FAILURE are switched by relay contacts.
In correct operation, they are close to the return lines. The
system-reset circuit is activated by a short circuit between
the SYSRESET and the GND signal line. For trouble
shooting purposes the global trip-off can be disabled by a
jumper connection between INHIBIT and 0V SIGNAL lines.
CK - Clock signal
Is a bussed differential line terminated on both sides of
the backplane (2 resistors to ground and 1 resistor in
between the two lines according to the impedance).
CK
positive logic /
CK*
negative logic
28
ANSI / VITA VME64x Standard
incompatibilities with older VME card cages outfitted
according to the CERN VME430 standard.
In 1997 the VITA Standards Organization (VSO) adopted a
superset to the VME64 standard called the VME64
Extensions (VITA 1.1, VME64x). VME64x adds new features
and capabilities such as:
Pin Assignment for the VME64x P1/J1 Connector
Pin Row z Row A
Row B
Row C
Row d
1
MPR
D00
BBSY*
D08
VPC
2
GND
D01
BCLR
D09
GND
3
MCLK
D02
ACFAIL*
D10
+V1
4
GND
D03
BG0IN*
D11
+V2
5
MSD
D04
BG0OUT*
D12
RsvU
6
GND
D05
BG1IN*
D13
-V1
7
MMD
D06
BG1OUT*
D14
-V2
8
GND
D07
BG2IN*
D15
RsvU
9
MCTL
GND
BG2OUT*
GND
GAP*
10 GND
SYSCLK
BG1IN*
SYSFAIL*
GA0*
11 RESP*
GND
BG3OUT*
BERR*
GA1*
12 GND
DS1*
BR0*
SYSRESET*
+3.3V
13 RsvBus
DS0*
BR1*
LWORD*
GA2*
14 GND
WRITE*
BR2*
AM5
+3.3V
15 RsvBus
GND
BR3*
A23
GA3*
16 GND
DTACK*
AM0
A22
+3.3V
17 RsvBus
GND
AM1
A21
GA4*
18 GND
AS*
AM2
A20
+3.3V
19 RsvBus
GND
AM3
A19
RsvBus
20 GND
IACK*
GND
A18
+3.3V
21 RsvBus IACKIN*
SERA
A17
RsvBus
22 GND
IAOUT*
SERB
A16
+3.3V
23 RsvBus
AM4
GND
A15
RsvBus
24 GND
A07
IRQ7*
A14
+3.3V
25 RsvBus
A06
IRQ6*
A13
RsvBus
26 GND
A05
IRQ5*
A12
+3.3V
27 RsvBus
A04
IRQ4*
A11
LI/I*
28 GND
A03
IRQ3*
A10
+3.3V
29 RsvBus
A02
IRQ2*
A09
LI/O*
30 GND
A01
IRQ1*
A08
+3.3V
31 RsvBus
-12 V +5V STDBY
+ 12 V
GND
32 GND
+5 V
+5V
+5V
VPC
A new 160 pin connector family.
A 95 pin P0/J0 connector.
3.3 V power supply pins.
More +5 VDC power supply pins.
Geographical addressing.
Higher bandwidth (up to 160 Mbytes/sec).
141 more user-defined I/O pins.
Rear plug-in units (transition modules).
Live insertion / hot-swap capability.
Injector / ejector locking handles.
EMC (Electro Magnetic Compatible) front panels.
ESD (Electrostatic Discharge) features.
Backplane
The main and obvious difference is the use of new 160-pin
connectors, which are backwards compatible to the “old”
96-pin DIN connector. The 3 row “core” is identical to the
VME/VME64 specification. All new bus and power lines are
routed to the outer “z” and “d” rows. This makes all legacy
VME and VME64 modules forward compatible to VME64x
backplanes and sub-racks; i.e. these modules can be
plugged into and used in VME64x crates.
P1/J1 Pin Layout (row ABC identical to VME/VME64)
Pin Assignment for the VME-64x
Pin Row z
Row a
Row b
1
UsrDef
UsrDef
+5 VDC
2
GND
UsrDef
GND
3
UsrDef
UsrDef
RETRY*
4
GND
UsrDef
A24
5
UsrDef
UsrDef
A25
6
GND
UsrDef
A26
7
UsrDef
UsrDef
A27
8
GND
UsrDef
A28
9
UsrDef
UsrDef
A29
10
GND
UsrDef
A30
11 UsrDef
UsrDef
A31
12
GND
UsrDef
GND
13 UsrDef
UsrDef
+5 VDC
14
GND
UsrDef
D16
15 UsrDef
UsrDef
D17
16
GND
UsrDef
D18
17 UsrDef
UsrDef
D19
18
GND
UsrDef
D20
19 UsrDef
UsrDef
D21
20
GND
UsrDef
D22
21 UsrDef
UsrDef
D23
22
GND
UsrDef
GND
23 UsrDef
UsrDef
D24
24
GND
UsrDef
D25
25 UsrDef
UsrDef
D26
26
GND
UsrDef
D27
27 UsrDef
UsrDef
D28
28
GND
UsrDef
D29
29 UsrDef
UsrDef
D30
30
GND
UsrDef
D31
31 UsrDef
UsrDef
GND
32
GND
UsrDef
+5 VDC
VME64x 5-row connectors
The reverse of plugging a VME64x module into an older
VME backplane or crate is mechanically possible however,
will work only if the VME64x module does not make use of
the 3.3VDC power. Further none of the new VME64x
features as geographic addressing live insertion, or 64 bit
transfer widths would be available. The monolithic
backplane PCB must include both J1 and J2 connectors.
The VME64x standard also adds a new metric style P0/J0
connector in the middle between the top and bottom
connectors. All pins except the outer rows (GND) are feedthrough connections for I/O. The P0 connector is optional
on the backplane.
IEEE1101.10 Mechanics
With VME64x new card rail and front panel mechanics with
enhanced EMC/EMD features according to the IEEE
1101.10 standard are used:
Front panel with guiding and coding pins, EMC strip
Card guides with ground ESD clips
Injector / ejector locking handles
EMC strips on chassis
P2/J2 Connector
Row c
Row d
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
GND
UsrDef
VPC
P2/J2 Pin Layout (row ABC identical to VME/VME64)
The new EMC style front panels/handles can have
29
Pin Row f
1
GND
2
GND
3
GND
4
GND
5
GND
6
GND
7
GND
8
GND
9
GND
10 GND
11 GND
15 GND
16 GND
17 GND
18 GND
19 GND
Increased Bandwidth
Pin Assignment for the VME64x
P0/J0/RJ0/RP0 Connector
Row e Row d Row c Row b Row a Row z
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
GND
VME64x defines new protocols that increase the bandwidth
of the parallel VME bus. The 2eVME protocol allows peak
block data rate of up to 160 MB/sec by using master and
slave terminated two-edge handshaking for each VME
transfer.
A further improvement was introduced with 2eSST (VME
320 / VITA 1.5-2003), which defines a synchronous data
strobe mode and achieves 320 Mbyte/s bandwidth.
These new protocols have to be implemented in the
master and slave modules. The VME crate must be
outfitted with a backplane capable of high-speed data
transfers. All WIENER VME64x crates are tested for 2eVME
and 2eSST transfers.
P0/J0 Pin Layout
Transition Card Cage
For I/O a rear side card cage can house 6U x 80mm
transition modules (101.11 rear I/O transition board
standard). These use the feed-through pins of J0/RJ0 and
J2/RJ2 to connect to the front side VME64x modules.
Topology
Bus Cycle
VMEbus / IEEE-1014
BLT
Maximum Speed
40 Mbyte/sec
VME64
MBLT
80 Mbyte/sec
VME64x
2eVME
160 Mbyte/sec
VME64x /VME320
2eSST
320 — 500+ Mbyte/sec
VME64xP - VIPA
In 1998, the “VME-bus International Physics Association”
defined an extension for VME64x for use in nuclear and
high energy physics experiments. This standard, VITA 23
(see also DOE/SC-0013 “Designer and User Guide”), uses
a 9U x 400mm card size and defines some user-defined
pins of the VME64x connector.
Further VME64xP adds 4 more DC voltages (Vw, Vx, Vy,
Vz), which can be defined by the user. These should be
used for low voltages as –2V or –5.2V. The VME64x V1
and V2 voltages should be used for +48V to power on
board dc-to-dc converter.
VME64xP introduced the CBLT (chained Block Transfer)
and MCST (multi cast writes). These modes allow
consecutive read-out of several adjacent modules with one
large block transfer. The end of the CBLT cycle is indicated
by a BERR, which has to be processed accordingly by the
VME master.
VME64x front and rear card/connector scheme
As of today the VME64xP standard is only used in a few
applications however the CBLT and MCST protocols can be
used on regular VME64x bus systems if they have a CBLT
compatible backplane. WIENER VME64x backplanes can be
ordered CBLT capable.
DC Voltages
In addition to the standard VME voltages (+5V, +/-12V)
VME64x provides +3.3V. Two optional voltages V1 and V2
can be defined and used (mostly for +48V). Additional
pins are foreseen for +5V (VPC) and Ground.
The resulting maximum power per board can be up to
200W with a total of 4kW per crate. This may require high
performance power supplies and efficient, temperature
controlled cooling.
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
Geographic Addressing
VME64x introduces 6 Geographic Addressing pins
GA(4:0)*, GAP* on the J1/P1 d row allowing modules to
be addressed by their slot (Geographically). This can
replace the switches or jumpers that define base
addresses on older VME modules. In order to be
compatible to legacy VME bus systems VME64x may have
both geographic and switch selectable base addressing.
Live Insertion
The VME64x standard also meets High Availability and Live
Insertion (Hot Swap) standards. In combination with
Geographic Addressing this makes it possible to remove
and insert modules without shutting down the crate and
supports automatically recognizing and configuring the
modules in a “plug and play” way.
30
Pin Assignment for the VME64xP / VIPA
P0/J0/RJ0/RP0 Connector
Row f Row e Row d Row c Row b Row a
COM
+5V
+5V
+5V
+5V
+5V
COM RET_WX UD
+5V TBUS1+ TBUS1COM RET_WX UD
UD TBUS2+ TBUS2COM
Vw
UD user I/O user I/O user I/O
COM
Vw
UD user I/O user I/O user I/O
COM RET_WX UD user I/O user I/O user I/O
COM AREF_WX UD user I/O user I/O user I/O
COM RET_WX UD user I/O user I/O user I/O
COM
Vx
UD user I/O user I/O user I/O
COM
Vx
UD user I/O user I/O user I/O
COM
Vy
UD user I/O user I/O user I/O
COM
Vy
UD user I/O user I/O user I/O
COM RET_YZ
UD user I/O user I/O user I/O
COM AREF_YZ UD user I/O user I/O user I/O
COM RET_YZ
UD user I/O user I/O user I/O
COM
Vz
UD user I/O user I/O user I/O
COM
Vz
UD
UD
Tbus3+ Tbus3COM RET_yz
UD
UD
Tbus4+ Tbus4COM RET_yz
UD
UD Tbusoc1 Tbusoc2
Row z
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
ANSI / VITA VXS Standard
is a bi-directional serial port. Ports can be used in parallel
(trunked) for higher performance.
“VME-bus switched serial” VXS is a new ANSI / VITA
standard which combines the 32-bit parallel VME-bus with
high speed switched serial interconnect fabrics in order to
increase the data transfer bandwidth to several GB/s.
Switch Cards
A VXS compliant chassis can have one or two switch cards
which have point-to-point connections to all payload cards.
and allow all or a subset of the payload boards connected
to it to intercommunicate.
VITA 41 / VXS was approved in May 2006 and consist of
the base standard ANSI/VITA 41.0-2006 and additional,
layered sub-specifications. VXS offers the following
enhancements and new features:
Switch slots/boards are 6U x 160mm and have a new
connector setup with 5 high speed MultiGig RT connectors
(Tyco: 1410421-1, 1410137-1, 1410138-1 and 1410139-1
types for P1-P5) which is not compatible to the “VME
P1/P2”. The lower P1 is defined as sideband connector for
lower speed signals provides sideband communication
between boards in the chassis.
Standardized multi-GB/s switched serial interconnects
to the parallel bus VME bus
Standard open technology for the serial switched links
Payload Modules with high speed differential RT2
connectors at J0/P0
Switch modules with high-speed differential RT
connectors (no VME J1/J2!)
Additional D.C. power onto each VME module
Backward compatibility with VME/VME64x
Further switch cards are outfitted with a special, dedicated
power connector (PWR1) and keying/alignment (A1-2, K12). The top rear above A2 and K2 is for user defined I/O.
Switch cards shall conform to the VITA 41.10 live insertion
standard.
VITA 41.0 VXS provides the following specifications
VXS.0:
base specification for mechanics, power, switch
slot and payload card definitions
VXS.1:
InfiniBand™ 4X link technology specification
VXS.2:
Serial RapidIO™ 4X link technology specification
VXS.3:
1/10 Gigabit Ethernet technology
VXS.4:
PCI Express 4X technology
VXS.5:
Aurora Link 4X technology
VXS.6:
1 Gigabit Ethernet Control Channel Layer
VXS.7:
Redundant Processor Mesh
VXS.10: Live Insertion Specification
VXS.11: Rear transition module Specification
Switch Fabric Architecture
VXS defines an interconnected network (fabric) of
switched serial input and output ports with point-to-point
connection with differential signals. An active switching
device manages data transfers from inputs to outputs. For
VXS all active switching devices are located on a special
switch card. Depending on the VXS backplane size and
configuration one or two switch card slots may be used.
All other modules that connect to the switch cards are
called payload cards.
The following tables show the pin assignment for the pairs
of differential connections. The actual pin usage is defined
in the appropriate protocol layer definition.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
Dual Star configuration example
The switch fabric architecture supports connections from
every payload card to one or two switch cards in a star,
dual star or mesh topology. The availability of 2 switch
boards supports redundant connections for high availability
applications. This centralized switching scheme uses 16
pairs of differential signals, which are assigned, each pair
31
L/K
GND
D5-6-/+
GND
D5-12-/+
GND
D5-18-/+
GND
D5-24-/+
GND
D5-30-/+
GND
D5-36-/+
GND
D5-42-/+
GND
D5-48-/+
Switch Board P5 Connector
J/I
H/G
F/E
D/C
D5-3-/+ GND
D5-2-/+
GND
GND
D5-5-/+
GND
D5-4-/+
D5-9-/+ GND
D5-8-/+
GND
GND
D5-11-/+ GND
D5-10-/+
D5-15-/+ GND
D5-14-/+ GND
GND
D5-17-/+ GND
D5-16-/+
D5-21-/+ GND
D5-20-/+ GND
GND
D5-23-/+ GND
D5-22-/+
D5-27-/+ GND
D5-26-/+ GND
GND
D5-29-/+ GND
D5-28-/+
D5-33-/+ GND
D5-32-/+ GND
GND
D5-35-/+ GND
D5-34-/+
D5-39-/+ GND
D5-38-/+ GND
GND
D5-41-/+ GND
D5-40-/+
D5-45-/+ GND
D5-44-/+ GND
J/I
D5-47-/+ GND
D5-46-/+
B/A
D5-1-/+
GND
D5-7-/+
GND
D5-13-/+
GND
D5-19-/+
GND
D5-25-/+
GND
D5-31-/+
GND
D5-37-/+
GND
D5-43-/+
GND
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
L/K
GND
D4-6-/+
GND
D4-12-/+
GND
D4-18-/+
GND
D4-24-/+
GND
D4-30-/+
GND
D4-36-/+
GND
D4-42-/+
GND
D4-48-/+
Switch Board P4 Connector
J/I
H/G
F/E
D/C
D4-3-/+ GND
D4-2-/+
GND
GND
D4-5-/+
GND
D4-4-/+
D4-9-/+ GND
D4-8-/+
GND
GND
D4-11-/+ GND
D4-10-/+
D4-15-/+ GND
D4-14-/+ GND
GND
D4-17-/+ GND
D4-16-/+
D4-21-/+ GND
D4-20-/+ GND
GND
D4-23-/+ GND
D4-22-/+
D4-27-/+ GND
D4-26-/+ GND
GND
D4-29-/+ GND
D4-28-/+
D4-33-/+ GND
D4-32-/+ GND
GND
D4-35-/+ GND
D4-34-/+
D4-39-/+ GND
D4-38-/+ GND
GND
D4-41-/+ GND
D4-40-/+
D4-45-/+ GND
D4-44-/+ GND
J/I
D4-47-/+ GND
D4-46-/+
B/A
D4-1-/+
GND
D4-7-/+
GND
D4-13-/+
GND
D4-19-/+
GND
D4-25-/+
GND
D4-31-/+
GND
D4-37-/+
GND
D4-43-/+
GND
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
L/K
GND
D3-6-/+
GND
D3-12-/+
GND
D3-18-/+
GND
D3-24-/+
GND
D3-30-/+
GND
D3-36-/+
GND
D3-42-/+
GND
D3-48-/+
Switch Board P3 Connector
J/I
H/G
F/E
D/C
D3-3-/+ GND
D3-2-/+
GND
GND
D3-5-/+
GND
D3-4-/+
D3-9-/+ GND
D3-8-/+
GND
GND
D3-11-/+ GND
D3-10-/+
D3-15-/+ GND
D3-14-/+ GND
GND
D3-17-/+ GND
D3-16-/+
D3-21-/+ GND
D3-20-/+ GND
GND
D3-23-/+ GND
D3-22-/+
D3-27-/+ GND
D3-26-/+ GND
GND
D3-29-/+ GND
D3-28-/+
D3-33-/+ GND
D3-32-/+ GND
GND
D3-35-/+ GND
D3-34-/+
D3-39-/+ GND
D3-38-/+ GND
GND
D3-41-/+ GND
D3-40-/+
D3-45-/+ GND
D3-44-/+ GND
J/I
D3-47-/+ GND
D3-46-/+
B/A
D3-1-/+
GND
D3-7-/+
GND
D3-13-/+
GND
D3-19-/+
GND
D3-25-/+
GND
D3-31-/+
GND
D3-37-/+
GND
D3-43-/+
GND
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
L/K
GND
D2-6-/+
GND
D2-12-/+
GND
D2-18-/+
GND
D2-24-/+
GND
D2-30-/+
GND
D2-36-/+
GND
D2-42-/+
GND
D2-48-/+
Switch Board P2 Connector
J/I
H/G
F/E
D/C
D2-3-/+ GND
D2-2-/+
GND
GND
D2-5-/+
GND
D2-4-/+
D2-9-/+ GND
D2-8-/+
GND
GND
D2-11-/+ GND
D2-10-/+
D2-15-/+ GND
D2-14-/+ GND
GND
D2-17-/+ GND
D2-16-/+
D2-21-/+ GND
D2-20-/+ GND
GND
D2-23-/+ GND
D2-22-/+
D2-27-/+ GND
D2-26-/+ GND
GND
D2-29-/+ GND
D2-28-/+
D2-33-/+ GND
D2-32-/+ GND
GND
D2-35-/+ GND
D2-34-/+
D2-39-/+ GND
D2-38-/+ GND
GND
D2-41-/+ GND
D2-40-/+
D2-45-/+ GND
D2-44-/+ GND
J/I
D2-47-/+ GND
D2-46-/+
B/A
D2-1-/+
GND
D2-7-/+
GND
D2-13-/+
GND
D2-19-/+
GND
D2-25-/+
GND
D2-31-/+
GND
D2-37-/+
GND
D2-43-/+
GND
H
01 SYS
RST*
02 S1-16
03 S1-24
04 S1-32
05 S1-40
06 S1-48
07 S1-56
08 S1-64
09 S1-72
10 S1-80
11 S1-88
12 S1-96
13 S1-104
14 S1-112
15 S1-120
16 S1-128
G
SYS
FAIL*
LI/I
S1-23
S1-31
S1-39
S1-47
S1-55
S1-63
S1-71
S1-79
S1-87
S1-95
S1-103
S1-111
S1-119
S1-127
Switch Board P1 Connector
F
E
D
C
AC
+5V
SERB
SERA
FAIL* STBY
GAP*
GA4* GA3* GA2*
S1-22 S1-21 S1-20 S1-19
S1-30 S1-29 S1-28 S1-27
S1-38 S1-373 S1-363 S1-35
S1-46 S1-453 S1-443 S1-43
S1-54 S1-533 S1-523 S1-51
S1-62 S1-613 S1-603 S1-59
S1-70 S1-693 S1-683 S1-67
S1-78 S1-773 S1-763 S1-75
S1-863 S1-853 S1-843 S1-83
S1-94 S1-93 S1-92 S1-91
S1-102 S1-101 S1-100 S1-99
S1-110 S1-109 S1-108 S1-107
S1-118 S1-117 S1-116 S1-115
S1-126 S1-125 S1-124 S1-123
B
RFU
A
PEN*
GA1*
S1-18
S1-26
S1-34
S1-42
S1-50
S1-58
S1-66
S1-74
S1-82
S1-90
S1-98
S1-106
S1-114
S1-122
GA0*
S1-17
S1-25
S1-33
S1-41
S1-49
S1-57
S1-65
S1-73
S1-81
S1-89
S1-97
S1-105
S1-113
S1-121
32
To provide DC to the switch board a 6-pin power
connector (type Positronic PWR-6P-R, 10A current/pin
rated) is used with the following pin assignment :
Pin 1:
VPC
Pin 2-4:
+5V
Pin 5-6:
GND
Payload Cards
Payload cards are outfitted with VME P1 and P2
connectors as well as with a new high-speed connector
for switched serial at the P0 position. Payload cards can
use the VME bus only, both the VME bus and switched
serial lines or only use the switched serial interconnects.
The VME-bus connectors P1 and P2 are as specified in the
VME64x standard 5-row 160-pin connectors with identical
pin layout (see VME64x section). All board mechanics as
front panels and handles have to comply with IEEE
1101.10 (ESD / EMC enhanced).
The high-speed P0 connector (Tier 2, 7-Row, Tyco
1410147-1) has both differential pairs (DP) as well as
single ended (SE) and ground (GND) lines. The individual
pin usage depends on the implemented switched
technology and is given in the protocol layer standards.
From the remaining P0 pins, one pin is defined to support
live insertion (PEN*). Other pins are reserved for Future
Use (RFU).
G
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
SE1
GND
SE2
GND
RFU
GND
RFU
GND
RFU
GND
PEN*
GND
SE7
GND
SE8
F
Payload P0 Pin layout
E
D
C
GND
DP4GND
DP8GND
RFU
GND
RFU
GND
RFU
GND
DP24GND
DP28GND
DP2DP4+
DP6DP8+
RFU
RFU
RFU
RFU
RFU
RFU
RFU
DP24+
DP26DP28+
DP30-
DP2+
GND
DP6+
GND
RFU
GND
RFU
GND
RFU
GND
RFU
GND
DP26+
GND
DP30+
GND
DP3GND
DP7GND
RFU
GND
RFU
GND
RFU
GND
DP23GND
DP27GND
B
DP1DP3+
DP5DP7+
RFU
RFU
RFU
RFU
RFU
RFU
RFU
DP23+
DP25DP27+
DP29-
A
DP1+
GND
DP5+
GND
RFU
GND
RFU
GND
RFU
GND
RFU
GND
DP25+
GND
DP29+
Each payload card is outfitted with one keying (K0) and
alignment (A0) pin receptacle.
VXS Backplane
A 19” sub rack can hold a backplane with a maximum
configuration of 18 payload slots and 2 switch slots.
Backplanes with fewer payload or switch slots are allowed
and can be configured in different topologies.
VXS Power and Cooling
ANSI/VITA 1.7-2003 increased the maximum allowed
currents for the 96 pin & 160 pin DIN/IEC connectors from
the original 1A to 2A per pin. This allows higher crate
power supply currents, and consequently higher power
dissipation on the VXS boards which will be needed to fully
utilize the high performance switch fabric capabilities.
The VXS backplane design depends on the switch fabric
topology, which can be one of:
Star: each of up to 18 payload cards connects to a
single switch card, no redundancy
This requires a better-designed chassis with improved
ventilation that can adequately cool the higher power VXS
boards. All WIENER crates can provide maximum DC
power and are outfitted with high efficiency temperature
controlled and monitored cooling fans.
Dual Star: each of up to 18 payload cards
connects to two separate switch cards, switch cards
are interconnected, provides redundancy, most
common configuration
VXS Layered Switch Fabric Standards
Mesh: each payload card is directly connected to
every other card, with the 2 available ports up to 3
cards can be connected in a mesh without using a
switch, used only on small backplanes
InfiniBand (VITA 41.1): with data rates of 16 Gb/s per
4x link, full duplex is designed for servers with ultra-high
bandwidth. Infiniband operates at 2.5 Gb/s per pair.
Serial RapidIO (VITA 41.2): is a new high-speed serial
physical layer using the “old” parallel RapidIO protocol.
RapidIO is designed for communications inside a system
rather than between systems. Serial RapidIO operates at
1.25 Gb/s, 2.5 Gb/s, or 3.125 Gb/s per pair. VITA 41.2
draft standard supports data rates of up to 20 Gbps per 4x
link, full duplex.
Daisy Chain: each payload card is connected to its
nearest neighbors, no switch is required however
low (shared) bandwidth and limited reliability
In a Dual Star configuration the VXS backplane requires
two switch cards and a maximum of 18 payload cards
resulting in a maximum of 20 slots. However, a standard
VME64x slot can be added to get a full size 21-slot
backplane.
Gigabit Ethernet (VITA 41.3): Gigabit Ethernet is a
well-established serial protocol. VITA 41.3 supports data
rates of up to 8 Gb/s per 4x link, full duplex.
PCI Express (VITA 41.4): PCI Express has been
selected by the PCI-SG as the next generation successor
to the PCI bus. PCI Express operates at 3.125 Gb/s per
pair. The VXS VITA 41.4 draft standard supports data
rates of up to 20 Gb/s per 4x link, full duplex.
21-slot VXS backplane
WIENER VME/VXI/VXS crate configurations and options
WIENER crates feature a modular design so that we can
provide any required configuration of mechanics,
backplanes or power supply based on standard WIENER
components and parts.
9U VME-430 6023 crate example:
1)
UEL6020 EX fan tray with combo interface,
plugged in from front
2)
Optional air dust filter
3)
1U Plenum chamber for homogeneous air
distribution (6023 style)
4)
Optional Vario divider with 6 slots 6Ux160mm
5)
Optional J3 backplane
6)
Optional rear side card cage
7)
UEP 6021 power supply plugged in from rear
WIENER VME / VXI / VXS Products:
Powered crates
VME Controllers
VME modules
33
Download PDF