Philips | Q552.2L | Specifications | Philips Q552.2L Specifications

Color Television
Chassis
Q552.2L
LA
19111_000_110519.eps
110711
Contents
Page
1.
2.
3.
4.
5.
6.
7.
8.
9.
Revision List
2
Technical Specifications, Diversity, and Connections2
Precautions, Notes, and Abbreviation List
5
Mechanical Instructions
9
Service Modes, Error Codes, and Fault Finding 22
Alignments
41
Circuit Descriptions
48
IC Data Sheets
54
Block Diagrams
Wiring diagram Blockbuster/Emmy 32"
65
Wiring diagram Blockbuster/Emmy 40" - 46"
66
Wiring diagram Sundance 42" - 47"
67
Block Diagram Video
68
Block Diagram Audio
69
Block Diagram Control & Clock Signals
70
Block Diagram I2C
71
Supply Lines Overview
72
10. Circuit Diagrams and PWB Layouts
Drawing
B01 313912365213
73
B02 313912365213
84
B03 313912365213
93
B04 313912365213
101
B05 313912365213
106
B06 313912365213
107
B09 313912365213
111
313912365213 SSB Layout
112
B01 313912365214
114
B02 313912365214
126
B03 313912365214
135
B04 313912365214
143
B05 313912365214
148
B06 313912365214
149
B09 313912365214
153
313912365214 SSB Layout
154
11. Styling Sheets
Blockbuster/Emmy 32"
Blockbuster/Emmy 40" - 46"
Sundance 42" - 47"
177
178
179
©
Copyright 2011 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Published by ER/TY 1167 BU TV Consumer Care, the Netherlands
Subject to modification
EN 3122 785 19112
2011-Jul-15
EN 2
1.
Revision List
Q552.2L LA
1. Revision List
Manual xxxx xxx xxxx.0
• First release.
Manual xxxx xxx xxxx.1
• Chapter 2: Table 2-1 updated (added CTNs).
• Chapter 4: added wiring diagrams; see section 4.1.
• Chapter 7: updated power supply connector overview; see
Table 7-1.
• Chapter 7: added Ambilight; see section 7.8.
Manual xxxx xxx xxxx.2
• Chapter 2: Table 2-1 updated (added CTNs).
• Chapter 4: added wiring diagrams; see section 4.1.
• Chapter 6: added white tone values; see section 6.3.1.
2. Technical Specifications, Diversity, and Connections
2.1
Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections
2.4 Chassis Overview
Technical Specifications
For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
started, user manuals, frequently asked questions and
software & drivers.
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).
Table 2-1 Described Model Numbers and Diversity
2.2
10
E (IR/LED/Keyboard)
B09 (non-DVBS-conn.)
B06 (non-DVBS-LVDS)
B05 (DDR)
B04 (I/O)
B03 (DC/DC / Class D)
B02 (PNX85500)
32PFL6606D/77 Blockbuster 65213
11-1
65214
-
2.3
4-1
4.3
4.3.7
7.2
7.4.1
9-1
-
10-1
10-9
10-2 10-3 10-4 10-5 10-6 10-7 10-17
10-10 10-11 10-12 10-13 10-14 10-15
32PFL7606D/78 Emmy
11-1
64833
2.3
4-2
4.3
4.3.7
7.2
7.4.1
9-1
10-21 10-23 10-1
10-9
10-2 10-3 10-4 10-5 10-6 10-7 10-18
10-10 10-11 10-12 10-13 10-14 10-15
40PFL6606D/77 Blockbuster 65213
11-2
65214
-
2.3
4-3
4.3
4.3.7
7.2
7.4.1
9-2
-
-
10-1
10-9
10-2 10-3 10-4 10-5 10-6 10-7 10-17
10-10 10-11 10-12 10-13 10-14 10-15
40PFL6606D/78 Blockbuster 65213
11-2
65214
-
2.3
4-3
4.3
4.3.7
7.2
7.4.1
9-2
-
-
10-1
10-9
10-2 10-3 10-4 10-5 10-6 10-7 10-17
10-10 10-11 10-12 10-13 10-14 10-15
40PFL7606D/77 Emmy
11-2
65213
65214
64853
2.3
4-4
4.3
4.3.7
7.2
7.4.1
9-2
10-21 10-24 10-1
10-9
10-2 10-3 10-4 10-5 10-6 10-7 10-18
10-10 10-11 10-12 10-13 10-14 10-15
40PFL7606D/78 Emmy
11-2
65214
64853
2.3
4-4
4.3
4.3.7
7.2
7.4.1
9-2
10-21 10-24 10-9
10-10 10-11 10-12 10-13 10-14 10-15 10-18
42PFL8606D/77 Sundance
11-3
65214
64853
2.3
4-5
4.4
4.4.8
7.2
7.4.1
9-3
10-22 10-26 10-9
10-10 10-11 10-12 10-13 10-14 10-15 10-20
42PFL8606D/78 Sundance
11-3
65214
64853
2.3
4-5
4.4
4.4.8
7.2
7.4.1
9-3
10-22 10-26 10-9
10-10 10-11 10-12 10-13 10-14 10-15 10-20
46PFL7606D/77 Emmy
11-2
65214
64873
2.3
4-6
4.3
4.3.7
7.2
7.4.1
9-2
10-21 10-25 10-9
10-10 10-11 10-12 10-13 10-14 10-15 10-19
46PFL7606D/78 Emmy
11-2
65213
65214
64873
2.3
4-6
4.3
4.3.7
7.2
7.4.1
9-2
10-21 10-25 10-1
10-9
10-2 10-3 10-4 10-5 10-6 10-7 10-19
10-10 10-11 10-12 10-13 10-14 10-15
47PFL8606D/78 Sundance
11-3
65214
64812
2.3
4-7
4.4
4.4.8
7.2
7.4.1
9-3
10-22 10-27 10-9
10-10 10-11 10-12 10-13 10-14 10-15 10-20
65213
65214
Directions for Use
You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
2011-Jul-15
back to
div. table
-
B01 (Tuner)
AL3 (Ambilight)
AL1 (Ambilight)
Schematics
Wiring Diagram
PSU
LCD Removal
9
Tuner
7
Descriptions
Assembly Removal
4
Mechanics
Wire Dressing
Dressing
Connection Overview
Styling
2
3104 313 xxxxx
CTN
Ambilight
3139 123 xxxxx
SSB
Technical Specifications, Diversity, and Connections
2.3
Q552.2L LA
2.
EN 3
Connections
REAR CONNECTORS
SIDE CONNECTORS
1
2
13
3
10
(optional)
3
11
4
BOTTOM REAR CONNECTORS
5
6
7
11
7
8
7
(optional)
9
12
(3)
(optional)
(2)
(1) ARC
HDMI
19110_051_110421.eps
110716
Figure 2-1 Connection overview
2.3.2
Note: The following connector colour abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow.
2.3.1
Rear Connections - Bottom
5 - RJ45: Ethernet
12345678
Rear Connections
1 - CVI: Cinch: Video YPbPr - In, Audio - In
Gn - Video Y
1 VPP / 75 ohm
Bu - Video Pb
0.7 VPP / 75 ohm
Rd - Video Pr
0.7 VPP / 75 ohm
Rd - Audio - R
0.5 VRMS / 10 kohm
Wh - Audio - L
0.5 VRMS / 10 kohm
2 - Service Connector (UART)
1 - Ground
Gnd
2 - UART_TX
Transmit
3 - UART_RX
Receive
3 - Cinch: Audio - In (VGA/DVI)
Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm
jq
jq
jq
jq
jq
10000_025_090121.eps
090121
Figure 2-2 Ethernet connector
1
2
3
4
5
6
7
8
H
k
j
jq
jq
4 - AV IN: Cinch: Video CVBS - In, Audio - In
Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm
Ye - Video CVBS
1 VPP / 75 ohm
jq
jq
jq
13 - Head phone (Output) (optional)
Bk - Head phone
32 - 600 ohm / 10 mW
ot
- TD+
- TD- RD+
- CT
- CT
- RD- GND
- GND
Transmit signal
Transmit signal
Receive signal
Centre Tap: DC level fixation
Centre Tap: DC level fixation
Receive signal
Gnd
Gnd
6 - Cinch: S/PDIF - Out
Bk - Coaxial
0.4 - 0.6VPP / 75 ohm
k
k
j
j
H
H
kq
7 - HDMI 2: Digital Video, Digital Audio - In
19
18
1
2
10000_017_090121.eps
090428
Figure 2-3 HDMI (type A) connector
1
2
3
4
5
6
7
8
back to
div. table
- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
j
H
j
j
H
j
j
H
2011-Jul-15
EN 4
9
10
11
12
13
14
15
16
17
18
19
20
2.
Q552.2L LA
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- n.c.
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground
Technical Specifications, Diversity, and Connections
Data channel
Data channel
Gnd
Data channel
Control channel
j
j
H
j
jk
DDC clock
DDC data
Gnd
j
jk
H
j
j
H
Hot Plug Detect
Gnd
10
11
12
13
14
15
2.3.3
- Ground Sync
- n.c.
- DDC_SDA
- H-sync
- V-sync
- DDC_SCL
H
Gnd
Side Connections
10 - SD-Card: Secure Digital Card - In/Out (optional)
14
GND
7 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/
Out
19
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
10
8
DAT1/IRQ
DAT0/D0
GND2
5
CLOCK
Figure 2-4 HDMI (type A) connector
4
VDD
3
GND1
2
CMD/DI
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Control channel
Audio Return Channel
DDC clock
DDC data
Gnd
Hot Plug Detect
Gnd
j
H
j
j
H
j
j
H
j
j
H
j
jk
k
j
jk
H
j
j
H
Coax, 75 ohm
1
DAT3/CS
9
DAT2/NC
GND
13
10000_049_100210.eps
100210
Figure 2-6 SD-Card connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D
- DAT3/CS
- CMD/DI
- GND1
- Vdd
- CLOCK
- GND2
- DAT0/D0
- DAT1/IRQ
- DAT2/NC
- CD
- GND
- WP
- GND
- GND
jk
k
H
k
k
H
jk
jk
jk
j
H
j
H
H
Signal
Signal
Gnd
Supply
Signal
Gnd
Signal
Signal
Signal
Signal
Gnd
Signal
Gnd
Gnd
11 - USB2.0
10
6
1
15
2
3
4
10000_022_090121.eps
090121
10000_002_090121.eps
090127
Figure 2-5 VGA Connector
- Video Red
- Video Green
- Video Blue
- n.c.
- Ground
- Ground Red
- Ground Green
- Ground Blue
- +5VDC
1
5
11
Figure 2-7 USB (type A)
0.7 VPP / 75 ohm
0.7 VPP / 75 ohm
0.7 VPP / 75 ohm
j
j
j
Gnd
Gnd
Gnd
Gnd
+5 V
H
H
H
H
j
1
2
3
4
- +5V
- Data (-)
- Data (+)
- Ground
Gnd
12- HDMI : Digital Video, Digital Audio - In
See 7 - HDMI 2: Digital Video, Digital Audio - In
Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.
2011-Jul-15
11
CD
6
9 - VGA: Video RGB - In
2.4
12
7
8 - Aerial - In
- - F-type
1
2
3
4
5
6
7
8
9
WP
GND
10000_017_090121.eps
090428
- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- ARC
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground
j
j
j
j
DDC data
0-5V
0-5V
DDC clock
back to
div. table
k
jk
jk
H
Precautions, Notes, and Abbreviation List
Q552.2L LA
3.
EN 5
3. Precautions, Notes, and Abbreviation List
•
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1
3.3.2
Safety Instructions
•
•
•
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
• Route the wire trees correctly and fix them with the
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage.
• Check the strain relief of the Mains/AC Power cord for
proper function.
• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
•
•
3.3.3
All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an “E” or an “R” (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads (  10-6),
nano-farads (n  10-9), or pico-farads (p  10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An “asterisk” (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.
Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4
BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
“Magazine”, then go to “Repair downloads”. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5
3.2
Schematic Notes
•
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
• Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
Lead-free Soldering
Warnings
•
•
•
•
3.3
Notes
3.3.1
General
•
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
– To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched “on”.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
3.3.6
Alternative BOM identification
It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
back to
div. table
2011-Jul-15
EN 6
3.
Q552.2L LA
Precautions, Notes, and Abbreviation List
3.4
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number “1”
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a “2” (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
indicated by the third digit of the serial number.
Abbreviation List
0/6/12
AARA
ACI
ADC
AFC
AGC
Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g.
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M.
code, digit 4 refers to the Service version change code, digits 5
and 6 refer to the production year, and digits 7 and 8 refer to
production week (in example below it is 2010 week 10 / 2010
week 17). The 6 last digits contain the serial number.
AM
AP
AR
ASF
ATSC
ATV
Auto TV
AV
AVC
AVIP
B/G
BDS
BLR
BTSC
B-TXT
C
CEC
10000_053_110228.eps
110228
Figure 3-1 Serial number (example)
3.3.7
CL
Board Level Repair (BLR) or Component Level Repair
(CLR)
CLR
ComPair
CP
CSM
CTI
If a board is defective, consult your repair procedure to decide
if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
3.3.8
CVBS
Practical Service Precautions
•
•
2011-Jul-15
DAC
DBE
It makes sense to avoid exposure to electrical shock.
While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.
DCM
DDC
D/K
DFI
back to
div. table
SCART switch control signal on A/V
board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
format
Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
Analogue to Digital Converter
Automatic Frequency Control: control
signal used to tune to the correct
frequency
Automatic Gain Control: algorithm that
controls the video input of the feature
box
Amplitude Modulation
Asia Pacific
Aspect Ratio: 4 by 3 or 16 by 9
Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information
Advanced Television Systems
Committee, the digital TV standard in
the USA
See Auto TV
A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
External Audio Video
Audio Video Controller
Audio Video Input Processor
Monochrome TV system. Sound
carrier distance is 5.5 MHz
Business Display Solutions (iTV)
Board-Level Repair
Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
Blue TeleteXT
Centre channel (audio)
Consumer Electronics Control bus:
remote control bus on HDMI
connections
Constant Level: audio output to
connect with an external amplifier
Component Level Repair
Computer aided rePair
Connected Planet / Copy Protection
Customer Service Mode
Color Transient Improvement:
manipulates steepness of chroma
transients
Composite Video Blanking and
Synchronization
Digital to Analogue Converter
Dynamic Bass Enhancement: extra
low frequency amplification
Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
See “E-DDC”
Monochrome TV system. Sound
carrier distance is 6.5 MHz
Dynamic Frame Insertion
Precautions, Notes, and Abbreviation List
DFU
DMR
DMSD
DNM
DNR
DRAM
DRM
DSP
DST
DTCP
DVB-C
DVB-T
DVD
DVI(-d)
E-DDC
EDID
EEPROM
EMI
EPG
EPLD
EU
EXT
FDS
FDW
FLASH
FM
FPGA
FTV
Gb/s
G-TXT
H
HD
HDD
HDCP
HDMI
HP
I
I2 C
I2 D
I2 S
IF
IR
IRQ
ITU-656
Directions For Use: owner's manual
Digital Media Reader: card reader
Digital Multi Standard Decoding
Digital Natural Motion
Digital Noise Reduction: noise
reduction feature of the set
Dynamic RAM
Digital Rights Management
Digital Signal Processing
Dealer Service Tool: special remote
control designed for service
technicians
Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394
Digital Video Broadcast - Cable
Digital Video Broadcast - Terrestrial
Digital Versatile Disc
Digital Visual Interface (d= digital only)
Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
Extended Display Identification Data
(VESA standard)
Electrically Erasable and
Programmable Read Only Memory
Electro Magnetic Interference
Electronic Program Guide
Erasable Programmable Logic Device
Europe
EXTernal (source), entering the set by
SCART or by cinches (jacks)
Full Dual Screen (same as FDW)
Full Dual Window (same as FDS)
FLASH memory
Field Memory or Frequency
Modulation
Field-Programmable Gate Array
Flat TeleVision
Giga bits per second
Green TeleteXT
H_sync to the module
High Definition
Hard Disk Drive
High-bandwidth Digital Content
Protection: A “key” encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a “snow vision” mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP “software key”
decoding.
High Definition Multimedia Interface
HeadPhone
Monochrome TV system. Sound
carrier distance is 6.0 MHz
Inter IC bus
Inter IC Data bus
Inter IC Sound bus
Intermediate Frequency
Infra Red
Interrupt Request
The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
iTV
LS
LATAM
LCD
LED
L/L'
LPL
LS
LVDS
Mbps
M/N
MHEG
MIPS
MOP
MOSFET
MPEG
MPIF
MUTE
MTV
NC
NICAM
NTC
NTSC
NVM
O/C
OSD
OAD
OTC
P50
PAL
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div. table
Q552.2L LA
3.
EN 7
SDI), is a digitized video format used
for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
Institutional TeleVision; TV sets for
hotels, hospitals etc.
Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
Latin America
Liquid Crystal Display
Light Emitting Diode
Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I
LG.Philips LCD (supplier)
Loudspeaker
Low Voltage Differential Signalling
Mega bits per second
Monochrome TV system. Sound
carrier distance is 4.5 MHz
Part of a set of international standards
related to the presentation of
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services
Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor
Matrix Output Processor
Metal Oxide Silicon Field Effect
Transistor, switching device
Motion Pictures Experts Group
Multi Platform InterFace
MUTE Line
Mainstream TV: TV-mode with
Consumer TV features enabled (iTV)
Not Connected
Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe.
Negative Temperature Coefficient,
non-linear resistor
National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
Non-Volatile Memory: IC containing
TV related data such as alignments
Open Circuit
On Screen Display
Over the Air Download. Method of
software upgrade via RF transmission.
Upgrade software is broadcasted in
TS with TV channels.
On screen display Teletext and
Control; also called Artistic (SAA5800)
Project 50: communication protocol
between TV and peripherals
Phase Alternating Line. Color system
mainly used in West Europe (colour
carrier = 4.433619 MHz) and South
America (colour carrier
2011-Jul-15
EN 8
3.
PCB
PCM
PDP
PFC
PIP
PLL
POD
POR
PSDL
PSL
PSLS
PTC
PWB
PWM
QRC
QTNR
QVCP
RAM
RGB
RC
RC5 / RC6
RESET
ROM
RSDS
R-TXT
SAM
S/C
SCART
SCL
SCL-F
SD
SDA
SDA-F
SDI
SDRAM
SECAM
SIF
SMPS
SoC
SOG
SOPS
SPI
S/PDIF
SRAM
SRP
SSB
SSC
STB
STBY
2011-Jul-15
Q552.2L LA
Precautions, Notes, and Abbreviation List
SVGA
SVHS
SW
SWAN
PAL M = 3.575612 MHz and
PAL N = 3.582056 MHz)
Printed Circuit Board (same as “PWB”)
Pulse Code Modulation
Plasma Display Panel
Power Factor Corrector (or Preconditioner)
Picture In Picture
Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency
Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set)
Power On Reset, signal to reset the uP
Power Supply for Direct view LED
backlight with 2D-dimming
Power Supply with integrated LED
drivers
Power Supply with integrated LED
drivers with added Scanning
functionality
Positive Temperature Coefficient,
non-linear resistor
Printed Wiring Board (same as “PCB”)
Pulse Width Modulation
Quasi Resonant Converter
Quality Temporal Noise Reduction
Quality Video Composition Processor
Random Access Memory
Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
Remote Control
Signal protocol from the remote
control receiver
RESET signal
Read Only Memory
Reduced Swing Differential Signalling
data interface
Red TeleteXT
Service Alignment Mode
Short Circuit
Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
Serial Clock I2C
CLock Signal on Fast I2C bus
Standard Definition
Serial Data I2C
DAta Signal on Fast I2C bus
Serial Digital Interface, see “ITU-656”
Synchronous DRAM
SEequence Couleur Avec Mémoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
Sound Intermediate Frequency
Switched Mode Power Supply
System on Chip
Sync On Green
Self Oscillating Power Supply
Serial Peripheral Interface bus; a 4wire synchronous serial data link
standard
Sony Philips Digital InterFace
Static RAM
Service Reference Protocol
Small Signal Board
Spread Spectrum Clocking, used to
reduce the effects of EMI
Set Top Box
STand-BY
SXGA
TFT
THD
TMDS
TS
TXT
TXT-DW
UI
uP
UXGA
V
VESA
VGA
VL
VSB
WYSIWYR
WXGA
XTAL
XGA
Y
Y/C
YPbPr
YUV
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800 × 600 (4:3)
Super Video Home System
Software
Spatial temporal Weighted Averaging
Noise reduction
1280 × 1024
Thin Film Transistor
Total Harmonic Distortion
Transmission Minimized Differential
Signalling
Transport Stream
TeleteXT
Dual Window with TeleteXT
User Interface
Microprocessor
1600 × 1200 (4:3)
V-sync to the module
Video Electronics Standards
Association
640 × 480 (4:3)
Variable Level out: processed audio
output toward external amplifier
Vestigial Side Band; modulation
method
What You See Is What You Record:
record selection that follows main
picture and sound
1280 × 768 (15:9)
Quartz crystal
1024 × 768 (4:3)
Luminance signal
Luminance (Y) and Chrominance (C)
signal
Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
Component video
Mechanical Instructions
Q552.2L LA
4.
EN 9
4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing
4.2 Service Positions
4.3 Assy/Panel Removal Blockbuster/Emmy Styling (xxPFL6/
7xxx/xx series)
4.4 Assy/Panel Removal Sundance Styling (xxPFL8xxx/xx
series)
4.5 Set Re-assembly
4.1
Notes:
• Figures below can deviate slightly from the actual situation,
due to the different set executions.
Cable Dressing
Tape (150 m.m.) 2 ×
Tape (80 m.m.) 9 ×
Clamp (11 m.m.) 2 ×
19111_012_110519.eps
110519
Figure 4-1 Cable dressing 32PFL6606D/7x (Blockbuster)
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2011-Jul-15
EN 10
4.
Q552.2L LA
Mechanical Instructions
Tape (150 m.m.) 4 ×
Tape (80 m.m.) 15 ×
Clamp (11 m.m.) 2 ×
19111_016_110520.eps
110520
Figure 4-2 Cable dressing 32PFL7606D/7x (Emmy)
2011-Jul-15
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Mechanical Instructions
Q552.2L LA
4.
EN 11
Tape (150 m.m.) 1 ×
Tape (80 m.m.) 6 ×
Tape (50 m.m.) 2 ×
Clamp (11 m.m.) 2 ×
Stick-on Clamp 1 ×
19111_013_110519.eps
110519
Figure 4-3 Cable dressing 40PFL6606D/7x (Blockbuster)
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2011-Jul-15
EN 12
4.
Q552.2L LA
Mechanical Instructions
Tape (150 m.m.) 3 ×
Tape (80 m.m.) 16 ×
Tape (50 m.m.) 2 ×
Clamp (11 m.m.) 2 ×
Stick-on Clamp 1 ×
19111_014_110519.eps
110519
Figure 4-4 Cable dressing 40PFL7606D/7x (Emmy)
2011-Jul-15
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Mechanical Instructions
Q552.2L LA
4.
EN 13
19112_100_110712.eps
110712
Figure 4-5 Cable dressing 42PFL8606D/7x (Sundance)
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2011-Jul-15
EN 14
4.
Q552.2L LA
Mechanical Instructions
Tape (150 m.m.) 5 ×
Tape (80 m.m.) 16 ×
Clamp (11 m.m.) 2 ×
Stick-on Clamp 1 ×
19111_015_110519.eps
110519
Figure 4-6 Cable dressing 46PFL7606D/7x (Emmy)
2011-Jul-15
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Mechanical Instructions
Q552.2L LA
4.
EN 15
19112_101_110712.eps
110712
Figure 4-7 Cable dressing 47PFL8606D/7x (Sundance)
4.2
Service Positions
Note: it is not necessary to remove the stand while removing
the rear cover.
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.
4.3
1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
Additional instructions 40" and 46" sets
40"and 46" sets have a dedicated method to open the bottom
catches when removing the rear cover.
Refer to Figure 4-8 and Figure 4-9 for details.
Assy/Panel Removal Blockbuster/Emmy
Styling (xxPFL6/7xxx/xx series)
For the 40" and 46" sets, additional instructions (rear cover
removal) apply. Refer to subsection Additional instructions 40"
and 46" sets.
The instructions apply to the 37PFL6606H/12 (Blockbuster European model) - without Ambilight. At time of publishing of
this manual, no data was available for the Ambilight models
(series xxPFL7606D/xx - Emmy).
1
1
19100_048_110216.eps
110216
4.3.1
Rear Cover
Figure 4-8 Bottom catches 40" and 46" sets -1Warning: Disconnect the mains power cord before you remove
the rear cover.
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2011-Jul-15
EN 16
4.
Q552.2L LA
Mechanical Instructions
2
2
1
1
2
19100_049_110216.eps
110216
2
Figure 4-9 Bottom catches 40" and 46" sets -2It is advised to lay the set with front facing down before
executing this operation.
1. Remove all screws from the rear cover.
2. Use a round rod (diameter 2 mm) and insert it in one of the
holes [1].
3. Push the catch located inside the rear cover away by
inserting the rod [2] through the hole and lifting the rear
cover at the same time.
4. Repeat the same procedure on the other hole.
4.3.2
19101_008_110407.eps
110407
Figure 4-11 Main Power Supply
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.
Speakers
4.3.5
Tweeters
Each tweeter unit is mounted with two screws.
When defective, replace the whole unit.
Small Signal Board (SSB)
Refer to Figure 4-12 for details.
Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.
4.3.3
2
2
2
1
Mains Switch
Refer to Figure 4-10 for details.
2
2
2
2
1
19101_007_110407.eps
110407
Figure 4-12 SSB
19100_047_110216.eps
110216
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When remounting, ensure that the side shielding is positioned
correctly.
Figure 4-10 Mains switch
The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.
4.3.6
Keyboard Control, IR & LED Board
Refer to Figure 4-13 and Figure 4-14 for details.
4.3.4
Main Power Supply
Refer to Figure 4-11 for details.
2011-Jul-15
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Mechanical Instructions
1
1
1
1
4.3.7
3
3
2
LCD Panel
1. Remove the SSB as described earlier.
2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -subframe as described earlier.
5. Remove the cables [1].
6. Remove the mains switch subframe [2].
7. Remove the keyboard control-, and IR & LED board as
described earlier.
8. Remove all remaining cables and subframes.
9. Use a screwdriver to release the catches [3] that secure the
panel.
10. Use a screwdriver to release the catches and remove the
sidewings [4] that secure the panel.
11. Take the panel out.
Remove the clamps from the panel before sending the panel in
for Service.
2
2
EN 17
Refer to Figure 4-15 to Figure 4-17 for details.
Figure 4-13 Keyboard control, IR & LED board [1/2]
2
4.
1. Remove the stand [1].
2. Remove the stand subframe [2].
3. Remove the screws [3], unplug the connector and take the
board out.
When defective, replace the whole unit.
19101_009_110407.eps
110407
2
Q552.2L LA
2
19101_006_110407.eps
110407
Figure 4-14 Keyboard control, IR & LED board [2/2]
1
2
19101_005_110407.eps
110407
Figure 4-15 LCD panel [1/3]
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2011-Jul-15
EN 18
4.
Mechanical Instructions
Q552.2L LA
When defective, replace the whole unit.
Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.
3
4.4.3
Mains Switch
Refer to Figure 4-18 for details.
19101_004_110407.eps
110407
1
Figure 4-16 LCD panel [2/3]
19100_047_110216.eps
110216
Figure 4-18 Mains switch
The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.
4
4.4.4
Main Power Supply
Refer to Figure 4-19 for details.
1
19101_003_110407.eps
110407
2
2
Figure 4-17 LCD panel [3/3]
1
4.4
Assy/Panel Removal Sundance Styling
(xxPFL8xxx/xx series)
The instructions apply to the 32PFL7406K/02 - European
model.
4.4.1
2
Rear Cover
1
Warning: Disconnect the mains power cord before you remove
the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.
19100_050_110216.eps
110216
Figure 4-19 Main Power Supply
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.
1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
4.4.2
2
4.4.5
Speakers
Refer to Figure 4-20 for details.
Tweeters
Each tweeter unit is mounted with one screw.
2011-Jul-15
Small Signal Board (SSB)
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Mechanical Instructions
Q552.2L LA
4.
EN 19
3. Remove the screws [3] and take the board out.
When defective, replace the whole unit.
4.4.7
2
The Ambilight units can be lifted from the subframes without
the use of tools.
Refer to Figure 4-23 for details.
2
1
2
Ambilight Units
2
2
2
1
2
19100_051_110216.eps
110216
Figure 4-20 SSB
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When remounting, ensure that the side shielding is positioned
correctly.
4.4.6
19100_054_110216.eps
110216
Figure 4-23 Ambilight units
1. Unplug the connector [1].
2. Carefully lift the board [2] and take the board out.
When defective, replace the whole unit.
Keyboard Control, IR & LED Board
Refer to Figure 4-21 and Figure 4-22 for details.
1
1
1
1
1
1
19100_052_110216.eps
110216
Figure 4-21 Keyboard control, IR & LED board [1/2]
2
2
3
2
19100_053_110216.eps
110216
Figure 4-22 Keyboard control, IR & LED board [2/2]
1. Remove the stand and the plastic support [1].
2. Unplug the connector [2].
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2011-Jul-15
EN 20
4.4.8
4.
Q552.2L LA
Mechanical Instructions
LCD Panel
Refer to Figure 4-24 and Figure 4-25 for details.
4
4
4
2
2
2
1
4
4
4
4
2
2
19100_055_110216.eps
110216
Figure 4-24 LCD panel [1/2]
1. Remove the SSB as described earlier.
2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -support as described earlier.
5. Remove the cables [1].
6. Remove the stand subframe [2].
7. Remove the mains switch subframe [3].
8. Remove the Ambilight units together with their subframes
as described earlier.
9. Unplug the connector from the keyboard control-, and IR &
LED board as described earlier.
10. Remove all remaining cables and subframes.
11. Use a screwdriver to release the clamps [4] that secure the
panel and take the panel out.
Remove the clamps from the panel before sending the panel in
for Service.
2011-Jul-15
4
19100_056_110217.eps
110217
Figure 4-25 LCD panel [2/2]
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Mechanical Instructions
4.5
Q552.2L LA
4.
EN 21
Set Re-assembly
To re-assemble the whole set, execute all processes in reverse
order.
Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
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2011-Jul-15
EN 22
5.
Q552.2L LA
Service Modes, Error Codes, and Fault Finding
5. Service Modes, Error Codes, and Fault Finding
•
Index of this chapter:
5.1 Test Points
5.2 Service Modes
5.3 Stepwise Start-up
5.4 Service Tools
5.5 Error Codes
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading
5.1
How to Activate SDM
For this chassis there are two kinds of SDM: an analogue SDM
and a digital SDM. Tuning will happen according Table 5-1.
• Analogue SDM: use the standard RC-transmitter and key
in the code “062596”, directly followed by the “MENU” (or
“HOME”) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it “off”, push the “MENU” (or
"HOME") button again.
Analogue SDM can also be activated by grounding for a
moment the solder path on the SSB, with the indication
“SDM” (see Service mode pad).
• Digital SDM: use the standard RC-transmitter and key in
the code “062593”, directly followed by the “MENU” (or
"HOME") button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it “off”, push the “MENU” (or
"HOME") button again.
Test Points
As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
Perform measurements under the following conditions:
• Service Default Mode.
• Video: Color bar signal.
• Audio: 3 kHz left, 1 kHz right.
5.2
All service-unfriendly modes (if present) are disabled, like:
– (Sleep) timer.
– Child/parental lock.
– Picture mute (blue mute or black mute).
– Automatic volume levelling (AVL).
– Skip/blank of non-favorite pre-sets.
Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
SDM
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section “5.4.1 ComPair”).
19100_057_110217.eps
110217
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
5.2.1
Figure 5-1 Service mode pad
After activating this mode, “SDM” will appear in the upper right
corner of the screen (when a picture is available).
Service Default Mode (SDM)
How to Navigate
When the “MENU” (or “HOME”) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
normal user menu.
Purpose
• To create a pre-defined setting, to get the same
measurement results as given in this manual.
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
section “5.3 Stepwise Start-up”.
• To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section “5.5 Error Codes”).
How to Exit SDM
Use one of the following methods:
• Switch the set to STAND-BY via the RC-transmitter.
• Via a standard customer RC-transmitter: key in “00”sequence.
Specifications
5.2.2
Service Alignment Mode (SAM)
Table 5-1 SDM default settings
Freq. (MHz)
Default
system
Europe, AP(PAL/Multi)
475.25
PAL B/G
Europe, AP DVB-T
DVB-T
546.00 PID
Video: 0B 06 PID
PCR: 0B 06 PID
Audio: 0B 07
Region
•
•
2011-Jul-15
Purpose
• To perform (software) alignments.
• To change option settings.
• To easily identify the used software version.
• To view operation hours.
• To display (or clear) the error code buffer.
How to Activate SAM
Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” or “OK” button. After activating
SAM with this method a service warning will appear on the
screen, continue by pressing the “OK” button on the RC.
All picture settings at 50% (brightness, color, contrast).
Sound volume at 25%.
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Service Modes, Error Codes, and Fault Finding
Contents of SAM
• Hardware Info.
– A. SW Version. Displays the software version of the
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z).
• AAAA= the chassis name.
• B= the SW branch version. This is a sequential
number (this is no longer the region indication, as
the software is now multi-region).
• X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
– B. STBY PROC Version. Displays the software
version of the stand-by processor.
– C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
• Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched “on/off”, 0.5 hours is added to this number.
• Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section “5.5 Error Codes”).
• Reset Error Buffer. When “cursor right” (or “OK” button)
pressed here, followed by the “OK” button, the error buffer
is reset.
• Alignments. This will activate the “ALIGNMENTS” submenu. See Chapter 6. Alignments.
• Dealer Options. Extra features for the dealers.
• Options. Extra features for Service. For more info
regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the “OK” button before
the options are stored, otherwise changes will be lost.
• Initialize NVM. The moment the processor recognizes a
corrupted NVM, the “initialize NVM” line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
– Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
– Initialize the NVM.
Q552.2L LA
5.
EN 23
Display Option
Code
39mm
27mm
PHILIPS
040
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
(CTN Sticker)
10000_038_090121.eps
090819
Figure 5-2 Location of Display Option Code sticker
•
•
•
•
•
•
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, it’s advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code “062598” directly followed by the “MENU” (or "HOME")
button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zero’s. If the above action is
successful, the front LED will go out as an indication that the
RC sequence was correct. After the display option is changed
in the NVM, the TV will go to the Stand-by mode. If the NVM
was corrupted or empty before this action, it will be initialized
first (loaded with default values). This initializing can take up to
20 seconds.
•
•
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Store - go right. All options and alignments are stored
when pressing “cursor right” (or the “OK” button) and then
the “OK”-button.
Operation hours display. Displays the accumulated total
of operation hours of the screen itself. In case of a display
replacement, reset to “0” or to the consumed operation
hours of the spare display.
SW Maintenance.
– SW Events. In case of specific software problems, the
development department can ask for this info.
– HW Events. In case of specific software problems, the
development department can ask for this info :
- Event 26: refers to a power dip, this is logged after
the TV set reboots due to a power dip.
- Event 17: refers to the power OK status, sensed even
before the 3 x retry to generate the error code.
Test settings. For development purposes only.
Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
“Channel list”, “Personal settings”, “Option codes”,
“Alignments”, “Identification data” (includes the set type
and prod code + all 12NC like SSB, display, boards),
“History list”. The “All” item supports to upload all several
items at once.
First a directory “repair\” has to be created in the root
of the USB stick.
To upload the settings, select each item separately, press
“cursor right” (or the “OK” button), confirm with “OK” and
wait until the message “Done” appears. In case the
download to the USB stick was not successful, “Failure” will
be displayed. In this case, check if the USB stick is
connected properly and if the directory “repair” is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customer’s
TV settings and to store them into another SSB.
Download from USB. To download several settings from
the USB stick to the TV, same way of working needs to be
followed as described in “Upload to USB”. To make sure
that the download of the channel list from USB to the TV is
executed properly, it is necessary to restart the TV and
tune to a valid preset if necessary. The “All” item supports
to download all several items at once.
NVM editor. For NET TV the set “type number” must be
entered correctly.
Also the production code (AG code) can be entered here
via the RC-transmitter.
Correct data can be found on the side/rear sticker.
2011-Jul-15
EN 24
5.
Q552.2L LA
Service Modes, Error Codes, and Fault Finding
How to Navigate
By means of the “CURSOR-DOWN/UP” knob on the RCtransmitter, can be navigated through the menus.
How to Navigate
• In SAM, the menu items can be selected with the
“CURSOR UP/DOWN” key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the “CURSOR UP/DOWN” key to
display the next/previous menu items.
• With the “CURSOR LEFT/RIGHT” keys, it is possible to:
– (De) activate the selected menu item.
– (De) activate the selected sub menu.
• With the “OK” key, it is possible to activate the selected
action.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
General
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this. The update
can also be done via the NVM editor available in SAM.
• Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee in a possibility to
do this. The update can also be done via the NVM editor
available in SAM.
• Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
• Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
• Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
• 12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
• 12NC display. Shows the 12NC of the display.
• 12NC supply. Shows the 12NC of the power supply.
• 12NC 200Hz board. Shows the 12NC of the 200Hz Panel
(when present).
• 12NC AV PIP. Shows the 12NC of the AV PIP board
(when present).
How to Exit SAM
Use one of the following methods:
• Switch the TV set to STAND-BY via the RC-transmitter.
• Via a standard RC-transmitter, key in “00” sequence, or
select the “BACK” key.
5.2.3
Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
When in this chassis CSM is activated, a test pattern will be
displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second
Green). This test pattern is generated by the PNX51X0
(located on the 200Hz board as part of the display). So if this
test pattern is shown, it could be determined that the back end
video chain (PNX51X0 and display) is working.For TV sets
without the PNX51X0 inside, every menu from CSM will be
used as check for the back end chain video.
Software versions
• Current main SW. Displays the build-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
• Stand-by SW. Displays the build-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
Upgrading).
Example: STDBY_83.84.0.0.
• e-UM version. Displays the electronic user manual SWversion (12NC version number). Most significant number
here is the last digit.
• AV PIP software.
• 3D dongle software version.
When CSM is activated and there is a USB stick connected to
the TV set, the software will dump the CSM content to the USB
stick. The file (CSM_model number_serial number.txt) will be
saved in the root of the USB stick. This info can be handy if no
information is displayed.
When in CSM mode (and a USB stick connected), pressing
“OK” will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.txt)
contains:
• The normal CSM dump information,
• All items (from SAM “load to USB”, but in readable format),
• Operating hours,
• Error codes,
• SW/HW event logs.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the “red”
button and key in serial digits ‘2679’ (same keys to form the
word ‘COPY’ with a cellphone). A file “Dump_model
number_serial number.bin” will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped.
Quality items
• Signal quality. Bad / average /good (not for DVB-S).
• Ethernet MAC address. Displays the MAC address
present in the SSB.
• Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
• BDS key. Indicates if the set is in the BDS status.
• CI module. Displays status if the common interface
module is detected.
• CI + protected service. Yes/No.
• Event counter :
S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)
S : 0000 000X (number of software events : SW EVENTLOG #(events)
H : 000X 0000(number of hardware errors)
Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED. Only the latest error is displayed (see also
section 5.5 Error Codes).
How to Activate CSM
Key in the code “123654” via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
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Service Modes, Error Codes, and Fault Finding
5.
EN 25
in this mode with a faulty FET 7U0X is done, you can destroy
all IC’s supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET
7U0X or others FET’s on shortcircuit before activating SDM via
the service pads.
H : 0000 000X (number of hardware events : SW EVENTLOG #(events).
How to Exit CSM
Press “MENU” (or "HOME") / “Back” key on the RC-transmitter.
5.3
Q552.2L LA
Stepwise Start-up
The abbreviations “SP” and “MP” in the figures stand for:
• SP: protection or error detected by the Stand-by
Processor.
• MP: protection or error detected by the MIPS Main
Processor.
When the TV is in a protection state due to an error detected by
stand-by software (error blinking is displayed) and SDM is
activated via shortcutting the SDM solder path on the SSB, the
TV starts up until it reaches the situation just before protection.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up
Mains
off
Mains
on
- WakeUp requested
- Acquisition needed
- Tact switch pushed
St by
WakeUp
requested
Semi
St by
- stby requested and
no data Acquisition
required
Active
- St by requested
- tact SW pushed
Tact switch
pushed
Hibernate
WakeUp
requested
(SDM)
- Tact switch pushed
- last status is hibernate
after mains ON
GoToProtection
GoToProtection
Protection
18770_250_100216.eps
100402
Figure 5-3 Transition diagram
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2011-Jul-15
EN 26
5.
Service Modes, Error Codes, and Fault Finding
Q552.2L LA
Off
Stand by or
Protection
Mains is applied
Standby Supply starts running.
All standby supply voltages become available.
st-by µP resets
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.
Initialise I/O pins of the st-by µP:
- Switch reset-AVC LOW (reset state)
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH
- Switch Audio-Reset high.
It is low in the standby mode if the standby
mode lasted longer than 10s.
start keyboard scanning, RC detection. Wake up reasons are
off.
Switch ON Platform and display supply by switching
LOW the Standby line.
+12V, +24Vs, AL and Bolt-on power
is switched on, followed by the +1V2 DCDC converter
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval.
Detect2 high received
within 2 seconds?
Yes
12V error:
Layer1: 3
Layer2: 16
No
Enter protection
Enable the DCDC converters
(ENABLE-3V3n LOW)
Wait 50ms
Enable the supply detection algorithm
Set I²C slave address
of Standby µP to (A0h)
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
An EJTAG probe (e.g. WindPower ICE probe) can be
connected for Linux Kernel debugging purposes.
EJTAG probe
connected ?
Yes
No
No
No
Cold boot?
Yes
Release AVC system reset
Feed warm boot script
Release AVC system reset
Feed cold boot script
Release AVC system reset
Feed initializing boot script
disable alive mechanism
18770_251_100216.eps
100216
Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)
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Service Modes, Error Codes, and Fault Finding
Q552.2L LA
5.
Reset-system is switched HIGH by the
AVC at the end of the bootscript
Reset-system is switched HIGH by the
AVC at the end of the bootscript
AVC releases Reset-Ethernet, Reset-USB and
Reset-DVBs when the end of the AVC bootscript is detected
AVC releases Reset-Ethernet, Reset-USB and
Reset-DVBs when the end of the AVC bootscript is detected
Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the
startup process
Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the
startup process
EN 27
No
This cannot be done through the bootscript,
the I/O is on the standby µP
Timing need to be updated if
more mature info is available.
Bootscript ready
in 1250 ms?
No
Yes
Set I²C slave address
of Standby µP to (60h)
RPC start (comm. protocol)
Timing needs to
be updated if more
mature info is
available.
Flash to Ram
image transfer succeeded
within 30s?
No
Code =
Layer1: 2
Layer2: 15
Yes
Switch AVC PNX85500 in
reset (active low)
Code =
Layer1: 2
Layer2: 53
No
SW initialization
succeeded
within 20s?
Wait 10ms
Timing needs to be
updated if more
mature info is
available.
Yes
Enable Alive check mechanism
Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.
MIPS reads the wake up reason
from standby µP.
Wait until AVC starts to
communicate
Wait 5ms
switch off the remaining DC/DC
converters
3-th try?
Startup screen shall only be visible when there is a coldboot to
an active state end situation. The startup screen shall not be
visible when waking up for reboot reasons or waking up to semistandby conditions or waking up to enter Hibernate mode..
Wake up reason
coldboot & not semistandby?
yes
Switch Standby I/O line high
and wait 4 seconds
The first time after the option turn on of the startup screen or
when the set is virgin, the cfg file is not present and hence
the startup screen will not be shown.
Startup screen cfg file
present?
Yes
yes
Blink Code as
error code
200Hz set?
yes
No
Enter protection
85500 sends out startup screen
85500 sends out startup screen
85500 starts up the display.
200Hz Tcon has started up the
display.
Startup screen visible
85500 requests Lamp on
No
No
To keep this flowchart readable, the exact
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid.
Startup screen visible
Initialize audio
initialize tuner and channel decoders
Initialize source selection
Initialize video processing IC’s
initialize AutoTV by triggering CHS AutoTV Init interface
Initialize Ambilight with Lights off.
Semi-Standby
18770_252_100216.eps
100216
Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)
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2011-Jul-15
EN 28
5.
Q552.2L LA
Service Modes, Error Codes, and Fault Finding
Constraints taken into account:
- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.
Semi Standby
The assumption here is that a fast toggle (<2s) can
only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s.
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
Assert RGB video blanking
and audio mute
CPipe already generates a valid output
clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.
Display already on?
(splash screen)
No
Switch on the display power by
switching LCD-PWR-ON low
The exact timings to
switch on the
display (LVDS
delay, lamp delay)
are defined in the
display file.
Yes
Wait x ms
Initialize audio and video
processing IC's and functions
according needed use case.
Switch on LVDS output in the 85500
Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file
Switch off the dimming backlight feature, set
the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM
Switch on LCD backlight (Lamp-ON)
Start POK line
detection algorithm
Wait until valid and stable audio and video, corresponding to the
requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
return
Switch Audio-Reset low and wait 5ms
A LED set does not normally need a
preheat time. The preheat remains present
but is set to zero in the display file.
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
Restore dimming backlight feature, PWM and BOOST output
and unblank the video.
The higher level requirement is that audio and video
should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.
Switch on the Ambilight functionality according the last status
settings.
Startup screen Option
and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash
Active
18770_253_100216.eps
100216
Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)
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Service Modes, Error Codes, and Fault Finding
The assumption here is that a fast toggle (<2s)
can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI>STBY->SEMI->ON can be made in less than 2s,
we have to delay the semi -> stby transition until
the requirement is met.
Q552.2L LA
5.
EN 29
Semi Standby
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
Assert RGB video blanking
and audio mute
There is no need to define the
display timings since the timing
implementation is part of the Tcon.
Backlight already on?
(splash screen)
Yes
Initialize audio and video
processing IC's and functions
according needed use case.
No
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED
Start POK line
detection algorithm
Wait until valid and stable audio and video, corresponding to
the requested output is delivered by the AVC.
return
Switch Audio-Reset low and wait 5ms
The higher level requirement is that audio and
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
unblank the video.
Switch on the Ambilight functionality according the last status
settings.
Startup screen Option
and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash
Active
18770_254_100216.eps
100216
Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)
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2011-Jul-15
EN 30
5.
Q552.2L LA
Service Modes, Error Codes, and Fault Finding
Active
Mute all sound outputs via softmute
Wait 100ms
Set main amplifier mute (I/O: audio-mute)
Force ext audio outputs to ground
(I/O: audio reset)
And wait 5ms
switch off Ambilight
Wait until Ambilight has faded out: Output power
Observer should be zero
Switch off POK line
detection algorithm
switch off LCD backlight
(I/O or I²C)
Mute all video outputs
Yes
200Hz set?
No
Wait x ms (display file)
Instruct 200Hz
Tcon to turn off
the display
Switch off LVDS output in 85500
Wait x ms
The exact timings to
switch off the
display (LVDS
delay, lamp delay)
are defined in the
display file.
Switch off the display power by
switching LCD-PWR-ON high
Semi Standby
18770_255_100216.eps
100216
Figure 5-8 “Active” to “Semi Stand-by” flowchart
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Service Modes, Error Codes, and Fault Finding
Q552.2L LA
5.
EN 31
Semi Stand by
If ambientlight functionality was used in semi-standby
(lampadaire mode), switch off ambient light (see CHS
ambilight)
Delay transition until ramping down of ambient light is
finished. *)
*) If this is not performed and the set is
switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.
transfer Wake up reasons to the Stand by µP.
Switch Memories to self-refresh (this creates a more
stable condition when switching off the power).
Switch AVC system in reset state (reset-system and
reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW
Wait 10ms
Disable all supply related protections and switch off
the DC/DC converters (ENABLE-3V3n)
Wait 5ms
Switch OFF all supplies by switching HIGH the
Standby I/O line
Important remarks:
release reset audio 10 sec after entering
standby to save power
Also here, the standby state has to be
maintained for at least 4s before starting
another state transition.
Stand by
18770_256_100216.eps
100216
Figure 5-9 “Semi Stand-by” to “Stand-by” flowchart
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EN 32
5.
Service Modes, Error Codes, and Fault Finding
Q552.2L LA
5.4
Service Tools
5.5
Error Codes
5.4.1
ComPair
5.5.1
Introduction
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the µP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.
New in this chassis is the way errors can be displayed:
•
•
•
How to Connect
This is described in the chassis fault finding database in
ComPair.
•
TO TV
TO
UART SERVICE
CONNECTOR
ComPair II
RC in
RC out
TO
I2C SERVICE
CONNECTOR
•
TO
UART SERVICE
CONNECTOR
•
Multi
function
Optional Power Link/ Mode
Switch
Activity
I2C
•
RS232 /UART
If no errors are there, the LED should not blink at all in
CSM or SDM. No spacer must be displayed as well.
There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2).
– LAYER 1 errors are one digit errors.
– LAYER 2 errors are 2 digit errors.
In protection mode.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
In CSM mode.
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
In SDM mode.
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
PC
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
• Errors detected by the Stand-by software which not
lead to protection. In this case the front LED should blink
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer”. Note that it can take up several minutes
before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
• Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.
ComPair II Developed by Philips Brugge
HDMI
I2C only
Optional power
5V DC
10000_036_090121.eps
091118
Figure 5-10 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be
blown!
5.5.2
Use one of the following methods:
• On screen via the SAM (only when a picture is visible).
E.g.:
– 00 00 00 00 00: No errors detected
– 23 00 00 00 00: Error code 23 is the last and only
detected error.
– 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
– Note that no protection errors can be logged in the
error buffer.
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• Software is available via the Philips Service web portal.
• ComPair UART interface cable for Q55x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: When you encounter problems, contact your local
support desk.
2011-Jul-15
How to Read the Error Buffer
back to
div. table
Service Modes, Error Codes, and Fault Finding
•
•
5.5.3
5.
EN 33
content, as this history can give significant information). This to
ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
• Via error bits in the status registers of ICs.
• Via polling on I/O pins going to the stand-by processor.
• Via sensing of analog values on the stand-by processor or
the PNX8550.
• Via a “not acknowledge” of an I2C communication.
Via the blinking LED procedure. See section 5.5.3 How to
Clear the Error Buffer.
Via ComPair.
How to Clear the Error Buffer
Use one of the following methods:
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu.
• If the content of the error buffer has not changed for 50+
hours, it resets automatically.
5.5.4
Q552.2L LA
Error Buffer
Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.
In case of non-intermittent faults, clear the error buffer before
starting to repair (before clearing the buffer, write down the
Table 5-2 Error code overview
Description
Monitored Error/ Error Buffer/
Layer 1 Layer 2 by
Prot Blinking LED Device
Defective Board
I2C3
2
13
MIPS
E
BL / EB
SSB
SSB
I2C2
2
14
MIPS
E
BL / EB
SSB
SSB
I2C4
2
18
MIPS
E
BL / EB
SSB
SSB
PNX doesn’t boot (HW cause) 2
15
Stby µP
P
BL
PNX8550
SSB
12V
3
16
Stby µP
P
BL
/
Supply
Inverter or display supply
3
17
MIPS
E
EB
/
Supply
PNX51X0
2/9
21
MIPS
E
EB
PNX51X0
200 Hz board
HDMI mux
2
23
MIPS
E
EB
Sil9x87A
SSB
I2C switch
2
24
MIPS
E
EB
PCA9540
SSB
Channel dec DVB-S
2
28
MIPS
E
EB
STV0903
SSB
Lnb controller
2
31
MIPS
E
EB
LNBH23
SSB
Tuner
2
34
MIPS
E
EB
DTT 71300
SSB
Main nvm
2
35
MIPS
E
EB
STM24C64
SSB
Tuner DVB-S
2
36
MIPS
E
EB
STV6110
SSB
T° sensor SSB/set
2
42
MIPS
E
EB
LM 75
T° sensor
T° sensor LED driver/Tcon
7
42
MIPS
E
EB
LM 75
T° sensor
PNX doesn’t boot (SW cause) 2
53
Stby µP
P
BL
PNX8550
SSB
Display
64
MIPS
E
BL / EB
Altera
Display
5
Extra Info
• Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section “5.8 Fault Finding and Repair Tips, 5.8.7
Logging). It’s shown that the loggings which are generated
by the main software keep continuing. In this case
diagnose has to be done via ComPair.
• Error 13 (I2C bus 3, SSB bus blocked). Current situation:
when this error occurs, the TV will constantly reboot due to
the blocked bus. The best way for further diagnosis here, is
to use ComPair.
• Error 14 (I2C bus 2, TV set bus blocked). Current
situation: when this error occurs, the TV will constantly
reboot due to the blocked bus. The best way for further
diagnosis here, is to use ComPair.
• Error 18 (I2C bus 4, Tuner bus blocked). In case this bus
is blocked, short the “SDM” solder paths on the SSB during
startup, LAYER error 2 = 18 will be blinked.
• Error 15 (PNX8550 doesn’t boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8550
(supplies not OK, PNX 8550 completely dead, I2C link
between PNX and Stand-by Processor broken, etc...).
When error 15 occurs it is also possible that I2C1 bus is
blocked (NVM). I2C1 can be indicated in the schematics as
follows: SCL-UP-MIPS, SDA-UP-MIPS.
•
•
•
•
•
•
back to
div. table
Other root causes for this error can be due to hardware
problems regarding the DDR’s and the bootscript reading
from the PNX8550.
Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
LAYER 2 error = 16.
Error 17 (Invertor or Display Supply). Here the status of
the “Power OK” is checked by software, no protection will
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
Error 21 (PNX51X0). When there is no I2C communication
towards the PNX51X0 after start-up, LAYER 2 error = 21
will be logged and displayed via the blinking LED
procedure if SDM is switched on. This device is located on
the 200 Hz panel from the display.
Error 23 (HDMI). When there is no I2C communication
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark: this only
works for TV sets with an I2C controlled screen included.
Error 28 (Channel dec DVB-S). When there is no I2C
communication towards the DVB-S channel decoder,
2011-Jul-15
EN 34
•
•
•
•
•
•
•
5.
Q552.2L LA
Service Modes, Error Codes, and Fault Finding
2.
3.
4.
5.
6.
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 31 (Lnb controller). When there is no I2C
communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
procedure when SDM is switched “on”. All service modes
(CSM, SAM and SDM) are accessible during this failure,
observed in the Uart logging as follows: "<< ERRO >>>
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Error 36 (Tuner DVB-S). When there is no I2C
communication towards the DVB-S tuner during start-up,
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched “on”.
Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
Error 53. This error will indicate that the PNX8550 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
Error 64. Only applicable for TV sets with an I2C controlled
screen.
5.6
The Blinking LED Procedure
5.6.1
Introduction
5.6.2
How to Activate
Use one of the following methods:
• Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in “normal operation”
mode or automatically when the error/protection is
monitored by the Stand-by processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether “error devices” are
mentioned. (see section “5.8 Fault Finding and Repair
Tips, 5.8.7 Logging”).
• Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
“normal operation” mode or when SDM (via hardware pins)
is activated when the tv set is in protection.
5.7
Protections
5.7.1
Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
• Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.
• Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
The blinking LED procedure can be split up into two situations:
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
• Blinking LED procedure LAYER 2 error. Via this
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
2 digits (see table “5-2 Error code overview”) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
regarding the failure of the defective board.
Important remark:
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section “5.3 Stepwise Start-up”).
5.7.2
When one of the blinking LED procedures is activated, the front
LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).
6. The sequence starts again.
Hardware Protections
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D audio amplifier (item
7D10; see diagram B03A) and puts the amplifier in a
continuous burst mode (cyclus approximately 2 seconds).
Repair Tip
• There still will be a picture available but no sound. While
the Class D amplifier tries to start-up again, the cone of the
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again. The headphone amplifier will
also behaves similar.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2011-Jul-15
Two short blinks of 250 ms followed by a pause of 3 s
Eight short blinks followed by a pause of 3 s
Six short blinks followed by a pause of 3 s
One long blink of 3 s to finish the sequence (spacer).
The sequence starts again.
back to
div. table
Service Modes, Error Codes, and Fault Finding
5.8
Fault Finding and Repair Tips
•
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info”.
5.8.1
Ambilight
Audio Amplifier
Description DVB-S2:
• LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC. It provides
supply voltage that feeds the outdoor satellite reception
equipment.
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
via a 5V to 1V DC-DC converter and is stabilized at the
point of load (channel decoder) by means of feedback
signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
are generated via linear stabilizers from +5V-DVBS that by
itself is generated via the first conversion channel of 7T03.
AV PIP
CSM
At start-up, +24V becomes available when STANDBY signal is
"low" (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
inside 7T03 are activated. Initially only the 24V to 5V converter
(channel 1 of 7T03 generating +5V-DVBS) will effectively work,
while +V-LNB is held at a level around 11V7 via diode 6T55.
After 7T05 is initialized, the second channel of 7T03 will start
and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small
delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)
5.8.5
+5V-TUN supply voltage (5V nominal) for tuner and IF
amplifier.
+12V is considered OK (=> DETECT2 signal becomes "high",
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
can be started up) if it rises above 10V and doesn’t drop below
9V5. A small delay of a few milliseconds is introduced between
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.
To check the AV PIP board (if present) functionality, a
dedicated testpattern can be invoked as follows: select the
“multiview” icon in the User Interface and press the “OK”
button. Apply for the main picture an extended source, e.g.
HDMI input. Proceed by entering CSM (push ‘123654’ on the
remote control) and press the yellow button. A colored
testpattern should appear now, generated by the AV PIP board
(this can take a few seconds).
5.8.4
EN 35
Supply voltage +1V1 is started immediately when +12V voltage
becomes available (+12V is enabled by STANDBY signal when
"low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
are switched "on" by signal ENABLE-3V3 when "low", provided
that +12V (detected via 7U40 and 7U41) is present.
The Class D-IC 7D10 has a powerpad for cooling. When the IC
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.
5.8.3
5.
+3V3-STANDY (3V3 nominal) is the permanent voltage,
supplying the Stand-by microprocessor inside PNX855xx.
Due to degeneration process of the LED’s fitted on the ambi
module, there can be a difference in the color and/or light
output of the spare ambilight modules in comparison with the
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted.
5.8.2
Q552.2L LA
DC/DC Converter
Description basic board
If +24V drops below +15V level then the DVB-S2 supply will
stop, even if +3V3 is still present.
The basic board power supply consists of 4 DC/DC converters
and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver:
• +1V1 supply voltage (1.15V nominal), for the core voltage
of PNX855xx, stabilized close to the point of load;
SENSE+1V1 signal provides the DC-DC converter the
needed feedback to achieve this.
• +1V8 supply voltage, for the DDR2 memories and DDR2
interface of PNX855xx.
• +3V3 supply voltage (3.30V nominal), overall 3.3 V for
onboard IC’s, for non-5000 series SSB diversities only.
• +5V (5.15V nominal) for USB, WIFI and Conditional
Access Module and +5V5-TUN for +5V-TUN tuner
stabilizer.
Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power “on” via the mains cord,
presuming that the stand-by microprocessor and the external
supply are operational. Take STANDBY signal "high"-to-"low"
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes "low") then +1V1 is started immediately.
After ENABLE-3V3 goes "low", all the other supply voltages
should rise within a few milliseconds.
Tips
• Behavior comparison with a reference TV550 platform can
be a fast way to locate failures.
• If +12V stays "low", check the integrity of fuse 1U40.
• Check the integrity (at least no short circuit between drain
and source) of the power MOS-FETs before starting up the
platform in SDM, otherwise many components might be
damaged. Using a ohmmeter can detect short circuits
between any power rail and ground or between +12V and
any other power rail.
• Short circuit at the output of an integrated linear stabilizer
(7UC0, 7UD2 or 7UD3) will heat up this device strongly.
• Switching frequencies should be 500 kHz ...600 kHz for
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
The linear stabilizers are providing:
• +1V2 supply voltage (1.2V nominal), stabilized close to
PNX855xx device, for various other internal blocks of
PNX855xx; SENSE+1V2 signal provides the needed
feedback to achieve this.
• +2V5 supply voltage (2.5V nominal) for LVDS interface and
various other internal blocks of PNX855xx; for 5000 series
SSB diversities the stabilizer is 7UD2 while for the other
diversities 7UC0 is used.
• +3V3 supply voltage (3V3 nominal) for 5000 series SSB
diversities, provided by 7UD3; in this case the 12V to 3V3
DC-DC converter is not present.
back to
div. table
2011-Jul-15
EN 36
5.
Q552.2L LA
Service Modes, Error Codes, and Fault Finding
Uart loggings reporting fault conditions, error messages, error
codes, fatal errors:
• Failure messages should be checked and investigated.For
instance fatal error on the PNX51x0: check startup of the
back-end processor, supplies..reset, I2C bus. => error
mentioned in the logging as: *51x0 failed to start by itself*.
• Some failures are indicated by error codes in the logging,
check with error codes table (see Table “5-2 Error code
overview”).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).
•
I2C bus error mentioned as e.g.: “ I2C bus 4 blocked”.
• Not all failures or error messages should be interpreted as
fault.For instance root cause can be due to wrong option
codes settings => e.g. “DVBS2Suppoprted : False/True.
In the Uart log startup script we can observe and check the
enabled loaded option codes.
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
to 1.1 V DC-DC converter 900 kHz is used.
5.8.6
Exit “Factory Mode”
When an “F” is displayed in the screen’s right corner, this
means the set is in “Factory” mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode).
Then push the “SOURCE” button for 10 seconds until the “F”
disappears from the screen.
5.8.7
Logging
Defective sectors (bad blocks) in the Nand Flash can also be
reported in the logging.
When something is wrong with the TV set (f.i. the set is
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a “ComPair UART”cable (3138 188 75051) from the service connector in the TV to
the “multi function” jack at the front of ComPair II box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.
- Select the correct database (open file “Q55X.X”, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. “logging”)
in the “Connection Description” box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the “Display Option Code” (useful when there is no picture),
look for item “DisplayRawNumber” in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for “error devices” in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.8
Startup in the SW upgrade application and observe the Uart
logging:
Starting up the TV set in the Manual Software Upgrade mode
will show access to USB, meant to copy software content from
USB to the DRAM.Progress is shown in the logging as follows:
“cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
40505344 of 40607744 bytes programmed”.
Startup in Jett Mode:
Check Uart logging in Jet mode mentioned as : “JETT UART
READY”.
Uart logging changing preset:
=> COMMAND: calling DFB source = RC6, system=0, key = 4”.
5.8.9
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!
5.8.10 PSL
In case of no picture when CSM (test pattern) is activated and
backlight doesn’t light up, it’s recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).
Guidelines Uart logging
5.8.11 Tuner
Description possible cases:
Uart loggings are displayed:
• When Uart loggings are coming out, the first conclusion we
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The PNX855xx is able to read and write in the DRAMs.
• We can not yet conclude : Flash RAM and DRAMs are fully
operational/reliable.There still can be errors in the data
transfers, DRAM errors, read/write speed and timing
control.
Attention: In case the tuner is replaced, always check the tuner
options!
5.8.12 Display option code
Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.
No Uart logging at all:
• In case there is no Uart logging coming out, check if the
startup script can be send over the I2C bus (3 trials to
startup) + power supplies are switched on and stable.
• No startup will end up in a blinking LED status : error
LAYER 1 = “2”, error LAYER 2 = “53” (startup with SDM
solder paths short).
• Error LAYER 2 = “15” (hardware cause) is more related to
a supply issue while error LAYER 2 = “53” (software cause)
refers more to boot issues.
2011-Jul-15
Loudspeakers
New in this chassis:
While in the download application (start up in TV mode + “OK”
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).
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5.
EN 37
5.8.13 SSB Replacement
Follow the instructions in the flowchart in case a SSB has to be
exchanged. See figure “SSB replacement flowchart”.
In st ru ct io n n o t e SSB rep lacem en t Q543.x, Q548.x, Q549.x, and Q55x.x
ST AR T
Before starting:
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in
case there are more than one "autorun.upg" files on the USB stick.
Set is still oper ating?
No
Yes
C onnect the U SB stick to the set,
go to SAM and save the current TV settings via “Upload to USB”
1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.
Start-up the set
Due to a possible wrong display option code in the received Service
SSB (NVM), it’s possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback).
No pictur e displayed
1) Start up the TV set, equiped with the Service SSB,
and enable the UART logging on the PC.
Set behaviour?
Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen
Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.
3) Plug the prepared USB stick into the TV set. Follow the
instructions in the UART log file, press “Right” cursor key to enter
the list. Navigate to the “autorun.upg” file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press “Ok”.
1) Plug the USB stick into the TV set and select
the “autorun .upg” file in the displayed browser.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and “Ok” to start flashing the main
TV software. Printouts like: “L: 1-100%, V: 1-100% and
P: 1-100%” should be visible now in the UART logging.
5) Wait until the message “Operation successful !” is logged in
the UART log and remove all inserted media. Restart the TV set.
3) Wait until the message “Operation successful !” is displayed
and remove all inserted media. Restart the TV set.
Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)
After entering the “Display Option” code, the set is going to
Standby
(= validation of code)
No
Connect PC via the ComPair interface to Service connector.
Restart the set
Saved settings
on USB stick?
Yes
Start TV in Jett mode (DVD I + (OSD))
Open ComPair browser Q54x
Go to SAM and reload settings
via “Download from USB” function.
In case of settings reloaded from USB, the set type,
serial number, display 12 NC, are automatically stored
when entering display options.
Program set type number, serial number, and display 12 NC
Program E - DFU if needed.
If not already done:
Check latest software on Service website.
Update main and Stand-by software via USB.
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
- Check if correct “display option” code is programmed.
- Verify “option codes” according to sticker inside the set.
- Default settings for “white drive” > see Service Manual.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.
Final check of all menus in CSM.
Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.
End
Q54x.E SSB Board swap – VDS
Updated 22-03-2010
H_16771_007a.eps
100402
Figure 5-11 SSB replacement flowchart
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Service Modes, Error Codes, and Fault Finding
Set is st art in g u p in F act o ry m o d e
Set is starting up in F actory m ode?
Noisy picture with bands/lines is visible and the
RED LED is continuous on.
An “F” is displayed (and the HDMI 1
input is displayed).
- Press the “volume minus” button on the TVs local keyboard for 5 ~10
seconds
- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”
The noise on the screen is replaced
with the blue mute or the “F” is disappeared!
Unplug the mains cord to verify the correct
disabling of the Factory mode.
Program display option code
via “062598 MENU”, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).
After entering “display option” code, the set is
going in stand-by mode (= validation of code)
R estart the set
H_16771_007b.eps
100322
Figure 5-12 SSB replacement flowchart - Factory mode
2011-Jul-15
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5.
EN 39
18753_211_100811.eps
100811
Figure 5-13 SSB start-up
5.9
Software Upgrading
For the correct order number of a new SSB, always refer to the
Spare Parts list!
Attention!
Software version numbers for 2011 sets are all defined below
number 0.40.x.x. This might confuse servicers who store
software versions for more than one set and/or platform on the
same storage device (USB stick).
5.9.2
•
The “UpgradeAll.upg” file is only used in the factory.
Automatic Software Upgrade
In “normal” conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the “AUTORUN.UPG”
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_prod.zip). This can also be done by the
consumers themselves, but they will have to get their software
from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The “autorun.upg” file
must be placed in the root of the USB stick.
How to upgrade:
1. Copy “AUTORUN.UPG” to the root of the USB stick.
2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.
Always check the latest software version on the servicer
website in relation to the correct CTN!!!
5.9.1
Main Software Upgrade
Introduction
The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the electronic User Manual.
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if the CI + key, MAC address.. are valid.
Manual Software Upgrade
In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the “OK” button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use
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a TV remote in “DVD” mode). Keep the “OK” button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.
Attention!
In case the download application has been started manually,
the “autorun.upg” will maybe not be recognized.
What to do in this case:
1. Create a directory “UPGRADES” on the USB stick.
2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.
5. The renamed “upg” file will be visible and selectable in the
upgrade application.
Back-up Software Upgrade Application
If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the “back-up software upgrade
application”.
How to start the “back-up software upgrade application”
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the “CURSOR DOWN”-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.
3. The back-up software upgrade application will start.
5.9.3
Stand-by Software Upgrade via USB
In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory “UPGRADES” on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbyFactory_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section “
Manual Software Upgrade”.
5. Select the appropriate file and press the “OK” button to
upgrade.
5.9.4
Content and Usage of the One-Zip Software File
Below the content of the One-Zip file is explained, and
instructions on how and when to use it.
• AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the
program instruction and software content, needed to
upgrade the ambilight CPLD on the TV550 platform.
• BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the
BalanceFPGA software in “upg” format.
• FUS_Q555X_x.x.x.x_prod.zip. Contains the
“autorun.upg” which is needed to upgrade the TV main
software and the software download application.
• PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the
PNX5130 software in “upg” format.
• StandbySW_Q555X_x.x.x.x_prod.zip. Contains the
StandbyFactory software in “upg” format.
• ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM
content. Must be programmed via ComPair or can be
loaded via USB, be aware that all alignments stored in
NVM are overwritten here.
5.9.5
UART logging 2K10 (see section “5.8 Fault Finding and
Repair Tips, 5.8.7 Logging)
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6.
EN 41
6. Alignments
•
Index of this chapter:
6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 Option Settings
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes
6.1
•
•
General Alignment Conditions
6.3.1
Perform all electrical adjustments under the following
conditions:
• Power supply voltage (depends on region):
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
– AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
– EU: 230 VAC / 50 Hz ( 10%).
– LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
– US: 120 VAC / 60 Hz ( 10%).
• Connect the set to the mains via an isolation transformer
with low internal resistance.
• Allow the set to warm up for approximately 15 minutes.
• Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heat sinks as ground.
• Test probe: Ri > 10 M, Ci < 20 pF.
• Use an isolated trimmer/screwdriver to perform
alignments.
White Point
•
Contrast
100
Brightness
50
Colour
0
Light Sensor
Off
Picture format
Unscaled
•
•
•
Picture Setting
Dynamic Contrast
Off
Dynamic Backlight
Off
Colour Enhancement
Off
Gamma
0
Go to the SAM and select “Alignments”-> “White point”.
White point alignment LCD screens:
• Use a 100% white screen (format: 720p50) to the HDMI
input and set the following values:
– “Color temperature”: “Cool”.
– All “White point” values to: “127”.
First, set the correct options:
– In SAM, select “Option numbers”.
– Fill in the option settings for “Group 1” and “Group 2”
according to the set sticker (see also paragraph 6.4
Option Settings).
– Press OK on the remote control before the cursor is
moved to the left.
– In submenu “Option numbers” select “Store” and press
OK on the RC.
OR:
– In main menu, select “Store” again and press OK on
the RC.
– Switch the set to Stand-by.
Warming up (>15 minutes).
In case you have a color analyzer:
• Measure, in a dark environment, with a calibrated
contactless color analyzer (Minolta CA-210 or Minolta CS200) in the centre of the screen and note the x, y value.
• Change the pattern to 90% white screen. If a Quantum
Data generator is used, select the “GreyAll” test pattern at
level = 230.
• Adjust the correct x, y coordinates (while holding one of the
White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
correct x, y coordinates (see Table 6-1 White D alignment
values - LED - Minolta CA-210, or 6-2 White D alignment
values - LED - Minolta CS-200). Tolerance: dx:  0.002, dy:
 0.002.
• Repeat this step for the other color temperatures that need
to be aligned.
• When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
NVM.
• Restore the initial picture settings after the alignments.
Hardware Alignments
Not applicable.
6.3
In menu “Picture”, choose “Pixel Plus HD” and set picture
settings as follows:
Alignment Sequence
•
6.2
Choose “TV menu”, “Setup”, “More TV Settings” and then
“Picture” and set picture settings as follows:
Picture Setting
•
6.1.1
EU/AP-PAL models: a PAL B/G TV-signal with a signal
strength of at least 1 mV and a frequency of 475.25 MHz
US/AP-NTSC models: an NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25
MHz (channel 3).
LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).
Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error
Codes, and Fault Finding). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
The following items can be aligned:
• White point
• Ambilight.
Table 6-1 White D alignment values - LED - Minolta CA-210
To store the data:
• Press OK on the RC before the cursor is moved to the
left
• In main menu select “Store” and press OK on the RC
• Switch the set to stand-by mode.
Value
Cool (9420K)
Normal (8120K)
Warm (6080K)
x
0.282
0.292
0.320
y
0.298
0.311
0.345
Table 6-2 White D alignment values - LED - Minolta CS-200
For the next alignments, supply the following test signals via a
video generator to the RF input:
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Value
Cool (11000K)
Normal (9000K)
Warm (6500K)
x
0.276
0.287
0.313
y
0.282
0.296
0.329
2011-Jul-15
EN 42
6.
Alignments
Q552.2L LA
If you do not have a color analyzer, you can use the default
values. This is the next best solution. The default values are
average values coming from production.
• Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
• Set the RED, GREEN and BLUE default values according
to the values in Table 6-3.
• When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.
6.4
Option Settings
6.4.1
Introduction
The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these
PNX51XX ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes.
Table 6-3 White tone default setting 32" sets (Blockbuster)
White Tone
e.g. 32PFL6606/xx
Colour Temp
R
G
Notes:
• After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left,
select STORE in the SAM root menu and press OK on the
RC.
• The new option setting is only active after the TV is
switched “off” / “stand-by” and “on” again with the mains
switch (the NVM is then read again).
B
Normal
t.b.d.
t.b.d.
t.b.d.
Cool
t.b.d.
t.b.d.
t.b.d.
Warm
t.b.d.
t.b.d.
t.b.d.
Table 6-4 White tone default setting 40" sets (Blockbuster)
White Tone
e.g. 40PFL6606/xx
Colour Temp
R
G
B
Normal
117
127
95
Cool
113
127
111
Warm
126
125
60
6.4.2
For dealer options, in SAM select “Dealer options”.
See Table 6-11 SAM mode overview.
6.4.3
Table 6-5 White tone default setting 32" sets (Emmy)
White Tone
e.g. 32PFL7606/xx
Colour Temp
R
G
B
Normal
112
127
85
Cool
106
127
100
Warm
125
126
53
Dealer Options
(Service) Options
From 2011 onwards, it is not longer possible to change
individual option settings in SAM. Options can only be changed
all at once by using the option codes as described in section
6.4.4.
6.4.4
Opt. No. (Option numbers)
Table 6-6 White tone default setting 40" sets (Emmy)
White Tone
e.g. 40PFL7606/xx
Colour Temp
R
G
B
Normal
115
127
84
Cool
111
127
99
Warm
125
127
49
Select this sub menu to set all options at once (expressed in
two long strings of numbers).
An option number (or “option byte”) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
Example: The options sticker gives the following option
numbers:
• 08192 00133 01387 45160
• 12232 04256 00164 00000
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
Table 6-7 White tone default setting 46" sets (Emmy)
White Tone
e.g. 46PFL7606/xx
Colour Temp
R
G
B
Normal
124
127
98
Cool
120
127
121
Warm
127
121
58
Table 6-8 White tone default setting 42" sets (Sundance)
White Tone
e.g. 42PFL8606/xx
Colour Temp
R
G
B
Normal
125
125
127
Cool
106
108
127
Warm
127
110
79
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Refer to Chapter 2. Technical Specifications, Diversity, and
Connections.
Table 6-9 White tone default setting 47" sets (Sundance)
White Tone
e.g. 47PFL8606/xx
Colour Temp
R
G
B
Normal
t.b.d.
t.b.d.
t.b.d.
Cool
t.b.d.
t.b.d.
t.b.d.
Warm
t.b.d.
t.b.d.
t.b.d.
6.4.5
Option Code Overview
Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!
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6.
EN 43
Caution
When manipulating option codes, know what you’re doing.
Wrong option codes could damage the set.
Prescribed option codes below are an example, not valid for all
sets and are subject to modification.
The correct option codes are always present on a sticker inside
the set!
Option Bit Overview
For test purposes, please find below an overview of the Option
Codes on bit level. With a bin/dec converter, you can calculate
the Option Code.
Table 6-10 Option codes at bit level (Option 1 - Option 8)
Option Name
Prescribed Value1)
Description
Option 1 (prescribed value 327761))
Bit 15 (MSB)
32768
Video Store Streaming
11)
0 = OFF
1 = ON
Bit 14
16384
Multi App
001)
Bit 13
8192
00 = none
01 = multi app (Multiview BASIC)
10 = AVPIP + multi app (Multiview ENHANCED)
11 = future use
Bit 12
4096
Perfect Pixel
001)
Bit 11
2048
00 = Pixel Plus HD
01 = Pixel Precise HD
10 = Perfect Pixel HD
11 = future use
Bit 10
1024
Tuner Type
0001)
Bit 9
512
Bit 8
256
000 = TH2603 (Europe/AP)
001 = FA2307 (Brazil)
010 = VA1E1ED2411
011 = future use
100 = future use
101 = future use
110 = future use
111 = future use
Bit 7
128
PQ Profiles
0001)
Bit 6
64
Bit 5
32
000 = profile 0
001 = profile 1
010 = profile 2
011 = profile 3
100 = profile 4
101 = profile 5
110 = profile 6
111 = profile 7
Bit 4
16
DNM
011)
Bit 3
8
00 = Perfect Natural Motion
01 = HD Natural Motion
10 = future use
11 = future use
Option & Bit
Dec. Value
Bit 2
4
MOP AL
01)
CPLD, not used in 2011
Bit 1
2
AL Optical Syst
001)
Bit 0 (LSB)
1
00 = 140 nit
01 = 200 nit
10 = future use
11 = future use
Option 2 (prescribed value 000011))
Bit 15 (MSB)
32768
AL Shop Mode
01)
0 = boost mode in shop is OFF
1 = boost mode in shop is ON
Bit 14
16384
AL settings storage location
01)
0 = stored in AL modules
1 = stored in SSB
Bit 13
8192
Wall Adaptive AL
01)
0 = OFF
1 = ON
0 = OFF
1 = ON
Bit 12
4096
Sunset
01)
Bit 11
2048
Ambient Light
00001)
Bit 10
1024
Bit 9
512
Bit 8
256
0000 = none
0001 = 2-sided (3/3)
0010 = 2-sided (4/4)
0011 = 2-sided (5/5)
0100 = 2-sided (6/6)
0101 = 2-sided (7/7)
0110 = 3-sided (5/5/5)
0111 = 3-sided (6/6/6)
1000 = 3-sided (3/6/3)
1001 = 3-sided (6/9/6)
1010 = 2-sided (8/8)
1011 = 3-sided (4/4/4)
1100 = 2-sided (1/1)
1101 = 2-sided (2/2)
1110 = future use
1111 = future use
Bit 7
128
FPGA3Dact/1Ddimm
01)
0 = OFF
1 = ON
Bit 6
64
AL Select
01)
0 = AL2k10
1 = AL2k11
Bit 5
32
3D Passive
01)
0 = 2D
1 = 3D passive
Bit 4
16
Smart Bit Enhancement (SBE)
01)
0 = off
1 = on (200 Hz board present)
0 = Super Resolution SD
1 = Super Resolution HD
Bit 3
8
Super Resolution
01)
Bit 2
4
Light Sensor LUT
001)
Bit 1
2
00 = Lut 0
01 = Lut 1
10 = Lut 2
11 = Lut 3
Bit 0 (LSB)
1
Light Sensor
11)
0 = OFF
1 = ON
Side IO
01)
0 = not present
1 = present
Option 3 (prescribed value 154211))
Bit 15 (MSB)
32768
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2011-Jul-15
EN 44
6.
Option & Bit
Q552.2L LA
Dec. Value
Bit 14
16384
Bit 13
8192
Bit 12
4096
Bit 11
2048
Bit 10
1024
Bit 9
512
Bit 8
256
Bit 7
128
Alignments
Option Name
Prescribed Value1)
Description
AV3
0111)
000 = none
001 = CVBS
010 = YPbPr
011 = YPbPr/LR
100 = YPbPr/HV/LR
101 = CVBS/LR
110 = CVBS/Yc/LR
111 = future use
AV2
111)
00 = Scart/CVBS/RGB/LR
01 = CVBS/LR
10 = YPbPr/LR
11 = none
AV1
001)
00 = Scart/CVBS/RGB/LR
01 = CVBS/YC/YPbPr/HV/LR
10 = CVBS/YC/YPbPr/LR
11 = YPbPr/LR
3D Prepared
01)
0 = not prepared
1 = prepared
0 = Sound in Cabinet
1 = Sound in Stand
Bit 6
64
Sound in Stand
01)
Bit 5
32
Headphone
11)
0 = OFF
1 = ON
Bit 4
16
Seamless System
11)
0 = OFF
1 = ON
Bit 3
8
ViewPort 21_9/PQL
11)
0 = OFF
1 = ON
0 = OFF
1 = ON
Bit 2
4
HDMI Side
11)
Bit 1
2
HDMI 3
01)
0 = OFF
1 = ON
Bit 0 (LSB)
1
HDMI 2
11)
0 = OFF
1 = ON
Cabinet
000011)
Cabinet type
(no detailed info available)
Region
0001)
000 = Europe (/02, /05 & /12)
001 = AP PAL multi
010 = AP NTSC
011 = Russian (/60)
100 = Latam (/78 & /77)
101 = Australia
110 = China (/93)
111 = future use
Option 4 (prescribed value 022351))
Bit 15 (MSB)
32768
Bit 14
16384
Bit 13
8192
Bit 12
4096
Bit 11
2048
Bit 10
1024
Bit 9
512
Bit 8
256
Bit 7
128
Display MSB
11)
0 = display option =< 255
1 = display option > 255
Bit 6
64
S Video
01)
0 = OFF
1 = ON
1)
0 = OFF
1 = ON
Bit 5
32
Video Store SD Card
1
Bit 4
16
Internet SW Upgrade
11)
0 = OFF
1 = ON (automatic software upgradable via internet)
Bit 3
8
Online Service
11)
0 = OFF
1 = ON (connection to internet provider Philips)
Bit 2
4
WiFi
01)
0 = OFF
1 = ON (wireless connection to ethernet; no link with “Ethernet option” bit “0”)
Bit 1
2
DLNA
11)
0 = OFF
1 = PC link
Ethernet
11)
0 = OFF
1 = Ethernet vonnector and HW present
8 Days EPG
11)
0 = OFF
1 = ON (country dependent)
DVBC Installation
011)
00 = OFF
01 = Country dependent
10 = ON
11 = future use
DVBT Installation
011)
00 = OFF
01 = Country dependent
10 = ON
11 = future use
Bit 0 (LSB)
1
Option 5 (prescribed value 438471))
Bit 15 (MSB)
32768
Bit 14
16384
Bit 13
8192
Bit 12
4096
Bit 11
2048
Bit 10
1024
DVB-S
01)
0 = OFF
1 = ON (ATSC/DVB should be ON)
Bit 9
512
DVB-C
11)
0 = OFF
1 = ON (ATSC/DVB should be ON)
0 = analogue only
1 = DVBT (and C/S depending DVBC/S option)
Display Type (ex.: 327)
Bit 8
256
DVB
11)
Bit 7
128
Display Type
010001111)
Bit 6
64
Bit 5
32
Bit 4
16
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0 (LSB)
1
2011-Jul-15
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Alignments
Q552.2L LA
6.
EN 45
Option Name
Prescribed Value1)
Description
32768
E-sticker
11)
0 = OFF
1 = ON
Bit 14
16384
Hotel Mode
001)
Bit 13
8192
00 = OFF
01 = 1V1
10 = 1V2
11 = future use
Bit 12
4096
Virgin
01)
0 = ON
1 = OFF
Bit 11
2048
USB Time Shift
11)
0 = OFF
1 = ON
Bit 10
1024
Auto Store Mode
111)
Bit 9
512
00 = none
01 = PDC_VPS
10 = TXT page
11 = PDC_VPS_TXT
Bit 8
256
PVR
11)
0 = OFF
1 = ON
Bit 7
128
Ginga
001)
Bit 6
64
00 = OFF
01 = Country dependent
10 = ON
11 = future use
Bit 5
32
MHP
001)
Bit 4
16
00 = OFF
01 = Country dependent
10 = ON
11 = future use
Bit 3
8
Over the Air Download
011)
Bit 2
4
00 = OFF
01 = Country dependent
10 = ON
11 = future use
Bit 1
2
DVBC light
11)
0 = OFF
1 = ON (when DVBC Installation is OFF or when ON but selected
country is OFF, this option is used)
Bit 0 (LSB)
1
DVBT light
11)
0 = OFF
1 = ON (when DVBT Installation is OFF or Country depend to a
country is OFF, this option is used)
Option & Bit
Option 6 (prescribed value
Bit 15 (MSB)
Dec. Value
366151))
Option 7 (prescribed value 330241))
Bit 15 (MSB)
32768
Visual Identity
11)
0 = User Interface 2k10
1 = User Interface 2k11
Bit 14
16384
Red LED Config LUT
0001)
Bit 13
8192
Bit 12
4096
000 = LED config LUT 0
001 = LED config LUT 1
010 = LED config LUT 2
011 = LED config LUT 3
100 = LED config LUT 4
101 = LED config LUT 5
110 = LED config LUT 6
111 = LED config LUT 7
Board Identifier
001)
not used, should always be “00”
Bit 11
2048
Bit 10
1024
Bit 9
512
Manet
01)
0 = all sets except Manet
1= Manet
Bit 8
256
Auto Power Down
11)
0 = OFF
1 = ON
Bit 7
128
Light Guide
01)
0 = OFF
1 = ON
0 = integrated set
1 = e-box/monitor
Bit 6
64
E-box
01)
Bit 5
32
Temp LUT
0001)
Bit 4
16
Bit 3
8
000 = temp lut 0
001 = temp lut 1
010 = temp lut 2
011 = temp lut 3
100 = future use
101 = future use
110 = future use
111 = future use
Temp Sensor
001)
00 = no temp sensor
01 = temp sensor in display
10 = temp sensor on additional board
11 = temp sensor in AL module
FAN
01)
0 = no fan
1 = fan(s) present)
Bit 2
4
Bit 1
2
Bit 0 (LSB)
1
Option 8 (prescribed value
Bit 15 (MSB)
000121))
32768
Test 8
01)
-
Bit 14
16384
Test 7
01)
-
Bit 13
8192
Test 6
01)
-
Bit 12
4096
Test 5
01)
-
Bit 11
2048
Test 4 (Trick Mode)
01)
0 = OFF
1 = ON
Bit 10
1024
Test 3 (XRay)
01)
0 = OFF
1 = ON
0 = OFF
1 = ON
Bit 9
512
Test 2 (DBV-T light)
01)
Bit 8
256
Test 1 (Monitor out)
01)
0 = OFF
1 = ON
Bit 7
128
not used
00001)
-
Bit 6
64
Bit 5
32
Bit 4
16
Bit 3
8
WM DRM10
11)
0 = OFF
1 = ON
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2011-Jul-15
EN 46
6.
Q552.2L LA
Alignments
Option Name
Prescribed Value1)
Description
Bit 2
4
HBBTV
11)
0 = OFF
1 = ON
Bit 1
2
DVB-T2 Installation
01)
0 = OFF
1 = ON
1)
0 = OFF
1 = ON
Option & Bit
Dec. Value
Bit 0 (LSB)
1
DVB-T2
0
In case of a display replacement, reset the “Operation hours
display” to “0”, or to the operation hours of the replacement
display.
Note
1). Example
6.5
Reset of Repaired SSB
6.5.1
A very important issue towards a repaired SSB from a Service
repair shop (SSB repair on component level) implies the reset
of the NVM on the SSB.
A repaired SSB in Service should get the service Set type
“00PF0000000000” and Production code “00000000000000”.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool or use the “NVM editor” and “Dealer options”
items in SAM (do not forget to “store”).
SSB identification
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of a “Service” SSB is the same as the ordering
number of an initial “factory” SSB.
After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this, you can use the NVM editor in SAM. This action also
ensures the correct functioning of the “Net TV” feature and
access to the Net TV portals. The loading of the CTN and
production code can also be done via ComPair (Model number
programming).
After a SSB repair, the original channel map can be restored,
provided that the original channel map was stored on a USB
stick before repair was commenced and that basic functionality
of the TV, needed for this procedure, was not hampered as a
result of the defect. The procedure of “channel map cloning” is
clearly described in the (electronic) user manual.
6.6
18310_221_090318.eps
090319
Total Overview SAM modes
Table 6-11 SAM mode overview
Main Menu
Sub-menu 1
Sub-menu 2
Hardware Info
A. SW version
e.g. “Q5551_0.9.1.0
Sub-menu 3
B. Stand-by processor version e.g. “STDBY_83.84.0.0”
C. Production code
Description
Display TV & Stand-by SW version and CTN serial
number
e.g. “see type plate”
Operation hours
Displays the accumulated total of operation hours.TV
switched “on/off” & every 0.5 hours is increase one
Errors
Displayed the most recent errors
Reset error buffer
Alignment
Clears all content in the error buffer
White point
Colour temperature
Normal
Warn
3 different modes of colour temperature can be
selected
Cool
White point red
LCD White Point Alignment. For values,
see Table 6-3 White tone default setting 32" sets
(Blockbuster)
White point green
White point blue
Ambilight
Select module
Brightness
Select matrix
Dealer options
Virgin mode
Off/On
Select Virgin mode On/Off. TV starts up / does not
start up (once) with a language selection menu after
the mains switch is turned “on” for the first time (virgin
mode)
E-sticker
Off/On
Select E-sticker On/Off (USP’s on-screen)
Auto store mode
None
PDC/VPS
TXT page
PDC/VPS/TXT
Option numbers
Group 1
e.g. “00008.00001.15421.02239”
The first line (group 1) indicates hardware options 1
to 4
Group 2
e.g. “44816.34311.33024.00000”
The second line (group 2) indicates software options
5 to 8
Store
Store after changing
Initialise NVM
2011-Jul-15
N.A.
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Alignments
Main Menu
Sub-menu 1
Sub-menu 2
Sub-menu 3
Store
6.
EN 47
Description
Select Store in the SAM root menu after making any
changes
Operation hours display
Software maintenance
Q552.2L LA
Software events
0003
In case the display must be swapped for repair, you
can reset the “”Display operation hours” to “0”. So,
this one does keeps up the lifetime of the display
itself (mainly to compensate the degeneration
behaviour)
Display
Display information is for development purposes
Clear
Test reboot
Test cold reboot
Test application crash
Hardware events
Display
Display information is for development purposes
Clear
Test setting
Digital info
Current frequency: 538
QAM modulation: 64-qam
Display information is for development purposes
Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency
000
Install start frequency from “0” MHz
Install end frequency
999
Install end frequency as “999” MHz
Digital only
Digital + Analogue
Select Digital only or Digital + Analogue before
installation
Display parameters DISPT5.0.9.29
Display information is for development purposes
Default install frequency
Installation
Development file
versions
Development 1 file version
Acoustics parameters ACSTS
5.0.6.20
PQ - TV550 1.0.27.22
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.5.2
Development 2 file version
12NC one zip software
Display information is for development purposes
Initial main software
NVM version Q55x1_0.4.5.0
Flash units software
Temp com file version none
Upload to USB
Channel list
To upload several settings from the TV to an USB
stick
Personal settings
Option codes
Alignments
Identification data
History list
All (options included)
Download from USB
Channel list
To download several settings from the USB stick to
the TV
Personal settings
Option codes
Alignments
Identification data
All (options included)
NVM editor
Type number
see type plate
AG code
see type plate
NVM editor; re key-in type number and production
code after SSB replacement
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2011-Jul-15
EN 48
7.
Circuit Descriptions
Q552.2L LA
7. Circuit Descriptions
•
•
•
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 DC/DC Converters
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
7.5 Front-End DVB-S(2) reception
7.6 HDMI
7.7 Video and Audio Processing - PNX855xx
The Q552.2L LA chassis comes with the following stylings:
• Berlinale (series xxPFL58xx),
• Blockbuster (series xxPFL66xx),
• Emmy (series xxPFL76xx),
• Sundance (series xxPFL86xx).
Notes:
• Only new circuits (circuits that are not published recently)
are described.
• Figures can deviate slightly from the actual situation, due
to different set executions.
• For a good understanding of the following circuit
descriptions, please use the wiring-, block- (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.
7.1
removal of TCON from the SSB (comes with the display)
changed power architecture
new USB hub (where applicable).
7.1.1
Implementation
Key components of this chassis are:
• PNX855xx System-On-Chip (SOC) TV Processor
• TX26xx Hybrid Tuner (DVB-T/C, analogue)
• STV6110AT DVB-S Satellite Tuner
• SII9x87 HDMI Switch
• TPA312xD2PWP Class D Power Amplifier
• LAN8710 Dual Port Gigabit Ethernet media access
controller.
Introduction
7.1.2
The Q552.2L LA is part of the TV550 platform and uses the
(same) PNX855xx chipset.
The major deltas versus its predecessor Q551 are:
• support of DVB-T2 (“second generation” DVBT)
• implementation of “passive” 3D
TV550 Architecture Overview
For details about the chassis block diagrams refer to chapter 9.
Block Diagrams. An overview of the TV550 2011 architecture
can be found in Figure 7-1.
19110_053_110421.eps
110421
Figure 7-1 Architecture of TV550 platform 2011
2011-Jul-15
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Circuit Descriptions
7.1.3
Q552.2L LA
7.
EN 49
SSB Cell Layout
19110_052_110421.eps
110421
Figure 7-2 SSB layout cells (top view)
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2011-Jul-15
EN 50
7.
Circuit Descriptions
Q552.2L LA
7.2
Power Supply
7.2.1
Power Supply Unit
Stand-by microcontroller and ENABLE-3V3n is the signal
coming from the Stand-by microcontroller.
Diagram B03D contains the following linear stabilizers:
• +2V5 stabilizer, built around item no. 7UCO
• +5V-TUN stabilizer, built around items no. 7UA6 and 7UA7
• +1V2 stabilizer, built around items no. 7UA3 and 7UA4.
All power supplies are a black box for Service. When defective,
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct
specifications! This part is available in the regular market.
Consult the Philips Service web portal for the order codes of the
boards.
Diagram B08A contains the DVB-S2-related DC/DC
converters and -stabilizers:
• a +24V under-voltage detection circuitry is built around
item no. 7T04
• the switching frequency of the 24 to 14...20V switched
mode converter is 350 kHz (item no. 7T03 and +V-LNB
lines)
• the output signal on the +V-LNB line goes to the LNBH23Q
(item no. 7T50)
• the LNBH23Q (item no. 7T50) sends a feedback signal via
the V0-CNTRL line
• the switching frequency of the +5V-DVBS to +1-DVBS
switched mode converter is 900 kHz (item no. 7T00)
• a delay line for the +2V5-DVBS and +1V-DVBS lines is
created with item no. 3T03 (R=10k) and 2T06 (C=100n)
• a 3.3V to 2.5V linear stabilizer is built around item no. 7T01
• a 5V to 3.3V linear stabilizer is built around item no. 7T02.
In this manual, no detailed information is available because of
design protection issues.
7.2.2
Connector overview
Table 7-1 Connector overview
Connector
no.
1308
1316
1M95
Descr.
Mains
to display
to SSB
Pin
CN1
CN2
CN4
1
N
Anode 1
+3V3stdby
2
L
n.c.
Standby
3
-
Cathode 1
GND1
4
-
n.c.
GND1
5
-
Anode 2
+12V
6
-
n.c.
+12V
7
-
Cathode 2
+Vsnd
8
-
n.c.
GND_SND
9
-
Anode 3
BL-ON-OFF
10
-
n.c.
BL-DIM1 (Vsync)
11
-
Cathode 3
BL-I-CTRL
12
-
n.c.
POK
13
-
Anode 4
+24V (AL2_DVBS)
14
-
n.c.
GND1
15
-
Cathode 4
-
Diagram B08B contains the DVB-S2 LNB supply:
• the +V-LNB signal comes from item no. 7T03
• the V0-CTRL signal goes to item no. 7T03
• the LNB-RF1 goes to the LNB.
Figures gives a graphical representation of the DC/DC
converters with its current consumptions:
+ 5V 5-TUN
196 m A
+ 5V
dc -dc
+ 12V
+ 3V 3
dc -dc
2919 m A
7.3
DC/DC Converters
The on-board DC/DC converters deliver the following voltages
(depending on set execution):
• +3V3-STANDBY, permanent voltage for the Stand-by
controller, LED/IR receiver and controls; connector 1M95
pin 1
• +12V, input from the power supply for TV550 common
(active mode); connector 1M95 pins 6, 7 and 8
• +24V, input from the power supply for DVB-S2 (in active
mode); connector 1M09 pins 1 and 2
• +1V1, core voltage supply for PNX855xx; has to be started
up first and switched "off" last (diagram B03B)
• +1V2, supply voltage for analogue blocks inside PNX855xx
• +1V8, supply voltage for DDR2 (diagram B03B)
• +2V5, supply voltage for analogue blocks inside PNX855xx
(see diagram B03E)
• +3V3, general supply voltage (diagram B03E)
• +5V, supply voltage for USB and CAM (diagram B03E)
• +5V-TUN, supply voltage for tuner (diagram B03E)
• +V-LNB, input voltage for LNB supply IC (item no. 7T50)
• +5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
• +3V3-DVBS, clean voltage for silicon tuner and DVB-S2
channel decoder
• +2V5-DVBS, clean voltage for DVB-S2 channel decoder
• +1V-DVBS, core voltage for DVB-S2 channel decoder.
+ 1V 8
dc -dc
+ 1V 1
dc -dc
2179 m A
+ 3V 3
+ 3V 3
2371 m A
+ 1V 8
+ 1V 8
2450 m A
+ 5V -TUN
s tabiliz er
+ 2V 5
s tabiliz er
+ 1V 2
s tabiliz er
+ 5V -TUN
196 m A
+ 2V 5
450 m A
+ 1V 2
550 m A
+ 1V 1
5100 m A
18770_226_100127.eps
100426
Figure 7-3 DC/DC converters
7.4
Front-End Analogue and DVB-T, DVB-C;
ISDB-T reception
7.4.1
Brazil region
The Front-End for the Brazil region consist of the following key
components:
•
•
•
•
•
A +12 V under-voltage detector (see diagram B03C) enables
the 12V to 3.3V and 12V to 5V DC/DC converters via the
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
via the ENABLE-1V8 line. DETECT2 is the signal going to the
2011-Jul-15
+ 5V 5-TUN
+ 5V
Hybrid Tuner with integrated SAW filter and amplifier
External ISDB-T channel decoder covering the Brazilian
digital terrestrial TV standard
Bandpass filter
Amplifier
PNX85500 SoC TV with integrated analogue demodulator.
Below find a block diagram of the front-end application for this
region.
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Circuit Descriptions
Q552.2L LA
7.
EN 51
18770_236_100127.eps
100219
Figure 7-4 Front-End block diagram Brazil region
7.5
Front-End DVB-S(2) reception
The Front-End for the DVB-S(2) application consist of the
following key components:
•
•
•
•
•
Satellite Tuner; I2C address 0xC6 (bridged via channel
decoder)
Channel decoder; I2C address 0xD0
LNB switching regulator; I2C address 0x14
Amplifier
PNX855xx SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.
18770_243_100203.eps
100203
Figure 7-6 HDMI input configuration
The following multiplexers can be used:
• Sil9187A (does not support “Instaport” technology for fast
switching between input signals)
• Sil9287B (supports “Instaport” technology for fast
switching between input signals).
The hardware default I2C addresses are:
• Sil9187A: 0xB0/0xB2 (random: software workaround)
• Sil9287B: 0xB2 (fixed).
Below find a block diagram of the front-end application for
DVB-S(2) reception.
The Sil9x87 has the following specifications:
• +5V detection mechanism
• Stable clock detection mechanism
• Integrated EDID
• RT control
• HPD control
• Sync detection
• TMDS output control
• CEC control
• EDID stored in Sil9x87, therefore there are no EDID pins
on the SSB.
18770_237_100127.eps
100219
Figure 7-5 Front-End block diagram DVB-S(2) reception
7.7
This application supports the following protocols:
• Polarization selection via supply voltage (18V = horizontal,
13V = vertical)
• Band selection via “toneburst” (22 kHz): tone “on” = “high”
band, tone “off” = “low” band
• Satellite (LNB) selection via DiSEqC 1.0 protocol
• Reception of DVB-S (supporting QPSK encoded signals)
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and
32APSK encoded signals), introducing LDPC low-density
parity check techniques.
7.6
Video and Audio Processing - PNX855xx
The PNX855xx is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:
•
•
•
•
•
•
•
•
•
•
HDMI
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is
implemented. Refer to figure 7-6 HDMI input configuration for
the application.
•
Multi-standard digital video decoder (MPEG-2, H.264,
MPEG-4)
Integrated DVB-T/DVB-C channel decoder
Integrated CI+
Integrated motion accurate picture processing (MAPP2)
High definition ME/MC
2D LED backlight dimming option
Embedded HDMI HDCP keys
Extended colour gamut and colour booster
Integrated USB2.0 host controller
Improved MPEG artefact reduction compared with
PNX8543
Security for customers own code/settings (secure flash).
The TV550 combines front-end video processing functions,
such as DVB-T channel decoding, MPEG-2/H.264 decode,
analog video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
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2011-Jul-15
EN 52
7.
Circuit Descriptions
Q552.2L LA
combination with LED backlights for optimum contrast and
power savings up to 50%.
and vivid colour management. High flat panel screen
resolutions and refresh rates are supported with formats
including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @
100Hz/120Hz. The combination of Ethernet, CI+ and H.264
supports new TV experiences with IPTV and VOD. On top of
that, optional support is available for 2D dimming in
PNX85500x
MEMORY
CONTROLLER
TS input
DVB
MPEG
SYSTEM
PROCESSOR
CI/CA
TS out/in for
PCMCIA
For a functional diagram of the PNX855xx, refer
to Figure 7-7.
PRIMARY
VIDEO
OUTPUT
LVDS
LVDS for
flat panel display
(single, dual or
quad channel)
DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
DECODER
CVBS, Y/C,
RGB
3D COMB
SECONDARY
VIDEO
OUTPUT
Low-IF
SSIF, LR
DIGITAL IF
MPEG/H.264
VIDEO
DECODER
VIDEO
ENCODER
analog CVBS
AUDIO DACS
analog audio
Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DEMOD
AND DECODE
AUDIO IN
SPDIF
AUDIO DSP
AUDIO OUT
HDMI
RECEIVER
HDMI
450 MHz
AV-DSP
560 MHz
MIPS32
24KEf CPU
SYSTEM
CONTROLLER
(8051)
I 2S
SPDIF
DRAWING
ENGINE
DMA BLOCK
I2C
PWM GPIO
IR
ADC
SPI
UART
I2C
GPIO Flash USB 2.0 SD Ethernet
Memory MAC
x8
Card
18770_241_100201.eps
100219
Figure 7-7 PNX855xx functional diagram
7.8
Ambilight
with the CPLD located on the SSB whereas the Slave Ambilight
module communicates via the PWM communication protocol
with the Master Ambilight module.
Sets in the xxPFL7606D/xx range are equipped with Ambilight.
The supply voltage of the modules is +24 V.
For the implementation of Ambilight, refer to Figure 7-8.
PNX85500
CPLD
SPI
1
M
9
5
SPI
1
M
8
3
AmbiLight
1
M
8
5
PWM
1
M
8
6
Refer to Figure 7-9 and Figure 7-10 for the Ambilight board
implementation.
AmbiLight
SSB
19111_009_110519.eps
110519
Figure 7-8 Ambilight configuration
The Ambilight implementation consists of 2 separate units in
the set, where the Ambilight module located on the right (seen
from the back of the set) acts as a Master and the module on
the left acts as a Slave.
The NVM is located on the Master Ambilight module. This
module communicates via the SPI communication protocol
2011-Jul-15
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div. table
Circuit Descriptions
Q552.2L LA
7.
EN 53
AMBI-SPI-SDI
AMBI-SPI-SDO
+24 V
LED
Driver
AMBI-SPI-CLK
AMBI-SPI-CLK
CS-Local
OR
PWM-R3
PWM-G3
PWM-B3
PWM-R4
PWM-G4
PWM-B4
1M85
1M83
EEPROM
AMBI-PWM-CLK
AMBI-BLANK
AMBI-PROG
AMBI-LATCH
19111_010_110519.eps
110519
1M86
Figure 7-9 Master Ambilight module
PWM-R3
+24 V
PWM-G3
+24 V
PWM-B3
+24 V
PWM-R4
+24 V
PWM-G4
+24 V
PWM-B4
+24 V
19111_011_110519.eps
110519
Figure 7-10 Slave Ambilight module
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div. table
2011-Jul-15
EN 54
8.
IC Data Sheets
Q552.2L LA
8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as “black boxes” in the
8.1
electrical diagrams (with the exception of “memory” and “logic”
ICs).
Diagram USB Hub B01C, USB2513B (IC 7F25)
Block diagram
To Upstream
VBUS
Upstream
USB Data
To EEPROM or
SMBus Master
24 MHz
Crystal
SDA SCL
3.3 V
BusPower
Detect/
Vbus Pulse
Upstream
PHY
Regulator
Serial
Interface
PLL
Serial
Interface
Engine
Repeater
3.3 V
...
TT
#1
Regulator
Controller
TT
#x
Port
Controller
CRFILT
Routing & Port Re-Ordering Logic
Port #1
PHY#1
OC Sense
Switch Driver/
LED Drivers
...
Port #x
OC Sense
Switch Driver/
LED Drivers
PHY#x
USB Data
OC
Port
Downstream Sense Power
Switch/
LED
Drivers
OC
USB Data
Port
Downstream Sense Power
Switch/
LED
Drivers
The ‘x’ indicates the number of available downstream ports: 2, 3, 4, or 7.
NC
NC
NC
21
19
SCL / SMBCLK / CFG_SEL[0]
24
20
HS_IND / CFG_SEL[1]
25
VDD33
RESET_N
26
SDA / SMBDATA / NON_REM[1]
VBUS_DET
27
Pinning information
22
The LED port indicators only apply to USB2513i.
23
SUSP_IND / LOCAL_PWR / NON_REM[0]
28
18
NC
VDD33
29
17
OCS_N[2]
USBDM_UP
30
16
PRTPWR[2] / BC_EN[2]*
USBDP_UP
31
15
VDD33
XTALOUT
32
14
CRFILT
XTALIN / CLKIN
33
13
OCS_N[1]
PLLFILT
34
12
PRTPWR[1] / BC_EN[1]*
11
TEST
10
VDD33
9
6
NC
NC
5
VDD33
7
4
USBDP_DN[2]
8
3
USBDM_DN[2]
NC
2
36
1
VDD33
USBDP_DN[1]
35
Ground Pad
(must be connected to VSS)
USBDM_DN[1]
RBIAS
SMSC
USB2512/12A/12B
USB2512i/12Ai/12Bi
(Top View QFN-36)
NC
Note :
Indicates pins on the bottom of the device.
18770_301_100217.eps
100217
Figure 8-1 Internal block diagram and pin configuration
2011-Jul-15
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div. table
IC Data Sheets
8.2
Q552.2L LA
8.
EN 55
Diagram Temp sensor & headphone B01J, LM75BDP (IC 7FD1)
Block diagram
VCC
LM75B
BIAS
REFERENCE
POINTER
REGISTER
CONFIGURATION
REGISTER
BAND GAP
TEMP SENSOR
COUNTER
TEMPERATURE
REGISTER
TIMER
TOS
REGISTER
COMPARATOR/
INTERRUPT
THYST
REGISTER
11-BIT
SIGMA-DELTA
A-to-D
CONVERTER
OSCILLATOR
POWER-ON
RESET
OS
LOGIC CONTROL AND INTERFACE
A2
A1
A0
SCL SDA
GND
Pinning information
SDA
1
8
VCC
SCL
2
7
A0
6
A1
5
A2
OS
3
GND
4
LM75BDP
18770_300_100217.eps
100217
Figure 8-2 Pin configuration
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2011-Jul-15
EN 56
8.3
8.
IC Data Sheets
Q552.2L LA
Diagram NANDflash - conditional access B02A, PNX855xx (IC7S00)
Block diagram
PNX8550x
MEMORY
CONTROLLER
TS input
MPEG
SYSTEM
PROCESSOR
CI/CA
TS out/in for
PCMCIA
PRIMARY
VIDEO
OUTPUT
LVDS
LVDS for
flat panel display
(single, dual or
quad channel)
DVB-T/C
channel decoder
DVB
AV-PIP
SUB-PICTURE
VIDEO
DECODER
CVBS, Y/C,
RGB
3D COMB
SECONDARY
VIDEO
OUTPUT
Low-IF
MULTISTANDARD
VIDEO
DECODER
DIGITAL IF
Direct-IF
SPDIF
AUDIO IN
HDMI
HDMI
RECEIVER
analog CVBS
AUDIO DACS
analog audio
analog Y/C
Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DEMOD
AND DECODE
SSIF, LR
VIDEO
ENCODER
AUDIO DSP
AUDIO OUT
450 MHz
AV-DSP
500 MHz
MIPS32
24KEf CPU
SYSTEM
CONTROLLER
(8051)
I2S
SPDIF
DRAWING
ENGINE
Scatter/Gather
TS Demux
I2C
PWM Px_x
IR
ADC
SPI
UART
I2C
GPIO Flash USB 2.0 SD Ethernet
Memory MAC
x 10
Card
Pinning information
ball A1
index area
PNX8550xE
2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Transparent top view
18770_308_100217.eps
100217
Figure 8-3 Internal block diagram and pin configuration
2011-Jul-15
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IC Data Sheets
8.4
Q552.2L LA
8.
EN 57
Diagram Audio B03A, TPA312xD2PWP (IC7D10)
Block diagram
TPA3120D2
1 F
0.22 F
LIN
BSR
RIN
ROUT
1 F
22 H
0.68 F
PGNDR
0.68 F
PGNDL
1 F
BYPASS
AGND
470 F
LOUT
22 H
BSL
470 F
0.22 F
PVCCL
AVCC
PVCCR
VCLAMP
Shutdown
Control
SD
1 F
MUTE
}
GAIN0
GAIN1
Pinning information
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
Control
PWP (TSSOP) PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
I_18020_142.eps
100402
Figure 8-4 Internal block diagram and pin configuration
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2011-Jul-15
EN 58
8.5
8.
IC Data Sheets
Q552.2L LA
Diagram DC/DC B03B, TPS53126PW (IC7U03)
Block diagram
Pinning information
VBST1
1
28
NC
2
27
LL1
EN1
3
26
DRVL1
PGND1
DRVH1
4
25
5
24
TRIP1
NC
6
23
VIN
22
VREG5
GND
7
TEST1
8
NC
9
TPS53124
VO1
VFB1
21
V5FILT
20
TEST2
TRIP2
VFB2
10
19
VO2
11
18
PGND2
17
DRVL2
EN2
12
NC
13
16
LL2
VBST2
14
15
DRVH2
18310_300_090319.eps
100416
Figure 8-5 Internal block diagram and pin configuration
2011-Jul-15
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IC Data Sheets
8.6
Q552.2L LA
8.
EN 59
Diagram DC/DC B03E, ST1S10PH (IC 7UD0)
Block diagram
ST1S10PH
Pinning information
DFN8 (4 × 4)
PowerSO-8
I_18010_083.eps
110601
Figure 8-6 Internal block diagram and pin configuration
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2011-Jul-15
EN 60
8.7
8.
IC Data Sheets
Q552.2L LA
Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)
Block diagram
LD1117DT
Pinning information
DPAK
F_15710_166.eps
100402
Figure 8-7 Internal block diagram and pin configuration
2011-Jul-15
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IC Data Sheets
8.
EN 61
Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)
Block diagram
MODE0
MODE1
MODE2
nRST
MODE Control
AutoNegotiation
10M Tx
Logic
Reset
Control
SMI
RMIISEL
HP Auto-MDIX
10M
Transmitter
TXP / TXN
Transmit Section
100M Tx
Logic
Management
Control
RXP / RXN
100M
Transmitter
MDIX
Control
TXD[0:3]
TXEN
TXER
TXCLK
CRS
COL/CRS_DV
RMII / MII Logic
RXD[0:3]
RXDV
RXER
RXCLK
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
PLL
Analog-toDigital
Interrupt
Generator
nINT
100M PLL
Receive Section
LED Circuitry
10M Rx
Logic
Squelch &
Filters
10M PLL
MDC
MDIO
XTAL1/CLKIN
XTAL2
LED1
LED2
Central
Bias
RBIAS
PHY
Address
Latches
PHYAD[0:2]
TXP
TXN
VDD1A
RXDV
TXD3
27
26
25
RXN
30
29
RXP
28
RBIAS
32
31
Pinning information
VDD2A
1
24
TXD2
LED2/nINTSEL
2
23
TXD1
LED1/REGOFF
3
22
TXD0
21
TXEN
20
TXCLK
19
nRST
18
nINT/TXER/TXD4
17
MDC
13
14
15
16
CRS
COL/CRS_DV/MODE2
MDIO
VSS
12
8
VDDIO
RXD3/PHYAD2
RXER/RXD4/PHYAD0
7
11
6
RXD0/MDE0
VDDCR
RXCLK/PHYAD1
10
5
9
4
RXD1/MODE1
XTAL2
XTAL1/CLKIN
SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)
RXD2/RMIISEL
8.8
Q552.2L LA
18770_302_100217.eps
100217
Figure 8-8 Internal block diagram and pin configuration
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2011-Jul-15
EN 62
8.9
8.
IC Data Sheets
Q552.2L LA
Diagram HDMI B04D, SII9x87B (IC 7EC1)
Block diagram
Pinning information
18770_303_100217.eps
100217
Figure 8-9 Internal block diagram and pin configuration
2011-Jul-15
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IC Data Sheets
Q552.2L LA
8.
EN 63
8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)
Block diagram
VDD 8
VDD/2
2
IN 1−
3
BYPASS
VO1 1
−
+
TPA6111A2
6
IN 2−
5
SHUTDOWN
VO2 7
−
+
4
Bias
Control
Pinning information
D OR DGN PACKAGE
(TOP VIEW)
VO1
IN1−
BYPASS
GND
1
8
2
7
3
6
4
5
VDD
VO2
IN2−
SHUTDOWN
18770_309_100217.eps
110602
Figure 8-10 Internal block diagram and pin configuration
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2011-Jul-15
EN 64
8.
Q552.2L LA
IC Data Sheets
Personal Notes:
10000_012_090121.eps
090121
2011-Jul-15
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Block Diagrams
Q552.2L LA
9.
EN 65
9. Block Diagrams
9-1 Wiring diagram Blockbuster/Emmy 32"
WIRING DIAGRAM 32" BLOCKBUSTER / EMMY
8M85
10P
14P
8M59
1G50
41P
1D38
3P
1G51
51P
8P
(5213)
1M19
LOUDSPEAKER
1M95
1M59
14P
26P
1M85
18P
1M95
18P
1M86
1316
TO DISPLAY
SUPPLY
8M95
SSB
B
3139 123 6521.x
(1150)
MAIN POWER SUPPLY
32" PLDC-P005A
51P
2P
TO DISPLAY
HDMI
HDMI
AL
(1161)
*AMBILIGHT MODULE
SD-CARD
READER
USB
HDMI
HDMI
TUNER
41P
PHONE
1M83
26P
LCD DISPLAY
(1004)
SPDIF
TO DISPLAY
SPDIF
8G51
ETHER
NET
(1162)
8G50
AL
*AMBILIGHT MODULE
(1005)
VGA
C2
(8308)
*AMBILIGHT ONLY APLICABLE FOR EMMY STYLING
1316 (PSU)
1. ANODE 1
2. NC
3. CATHODE 1
4. GND
5. ANODE 2
6. NC
7. CATHODE 2
8. NC
9. ANODE 3
10. NC
11. CATHODE 3
12. NC
13. ANODE 4
14. NC
15. CATHODE 4
1M95 (PSU)
1308 (PSU)
1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. +12V
6. +12V
7. +VSND
8. GND_SND
9. BL-ON-OFF
10. BL-DIM1
11. BL-I-CTRL
12. POK
13. +24V
14. GND1
1. N
2. L
C1
IR/LED/CONTROL BOARD
J1
(1108)
8P
1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
14. GND
LEADING EDGE
1735 (B03A)
1D38
(B03A)
1M19 (B09A)
1M59 (B09A)
1.
2.
3.
4.
1.
2.
3.
4.
5.
6.
7.
8.
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP
LEFT-SPEAKER
GND-AUDIO
RIGHT-SPEAKER
GND-AUDIO
RIGHT-SPEAKER
1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. CTRL-DISP
LIGHT-SENSOR
GND
RC
LED-2
+3V3-STANDBY
LED-1
KEYBOARD
+5V
(5216)
LOUDSPEAKER
MAINS
SWITCH
INLET
8308
(5216)
LOUDSPEAKER
130
8
15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +24V
22. +24V
23. +24V
24. +24V
25. +24V
26. +24V
19110_008_110323.eps
110711
2011-Jul-15 back to
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Block Diagrams
Q552.2L LA
9.
EN 66
9-2 Wiring diagram Blockbuster/Emmy 40" - 46"
WIRING DIAGRAM 40"- 46" BLOCKBUSTER / EMMY
TO DISPLY
SUPPLT
1316
HDMI
AL
VGA
1M83
HDMI
18P
USB
HDMI
SPDIF
SPDIF
8G50
HDMI
TUNER
8G51
(5213)
ETHER
NET
(1162)
LOUDSPEAKER
PHONE
TO DISPLAY
51P
LCD DISPLAY
(1004)
26P
3P
51P
8P
3139 123 6521.x
(1150)
SD-CARD
READER
1D38
1G51
1M19
SSB
1M85
26P
(1161)
1M59
14P
2P
1308
B
AL
*AMBILIGHT MODULE 24 LED
(1005)
1M95
8M59
1G50
MAIN POWER SUPPLY
40" PLDE-P008A
46" PLDG-P010A
*AMBILIGHT MODULE 24 LED
8M95
41P
14P
1M99
1M86
18P
10P
TO DISPLAY
41P
8308
INLET
LOUDSPEAKER
LOUDSPEAKER
(5216)
(5216)
MAINS
SWITCH
C2
C1
(8308)
*AMBILIGHT ONLY APLICABLE FOR EMMY STYLING
1316 (PSU)
1M95 (PSU)
1308 (PSU)
1. ANODE 1
2. NC
3. CATHODE 1
4. GND
5. ANODE 2
6. NC
7. CATHODE 2
8. NC
9. ANODE 3
10. NC
11. CATHODE 3
12. NC
13. ANODE 4
14. NC
15. CATHODE 4
1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. +12V
6. +12V
7. +VSND
8. GND_SND
9. BL-ON-OFF
10. BL-DIM1
11. BL-I-CTRL
12. POK
13. +24V
14. GND1
1. N
2. L
IR/LED/CONTROL BOARD
J1
(1108)
8P
LEADING EDGE
2011-Jul-15 back to
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1M95 (B03C)
1D38 (B03A)
1G51 (B06B)
1M59 (B09A)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
14. GND
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. CTRL-DISP
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP
1M19 (B09A)
1.
2.
3.
4.
5.
6.
7.
8.
LIGHT-SENSOR
GND
RC
LED-2
+3V3-STANDBY
LED-1
KEYBOARD
+5V
15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +24V
22. +24V
23. +24V
24. +24V
25. +24V
26. +24V
19110_009_110323.eps
110711
Block Diagrams
Q552.2L LA
9.
EN 67
9-3 Wiring diagram Sundance 42" - 47"
WIRING DIAGRAM 42"- 47" SUNDANCE
LED
POWER
8M84
SSB
3139 123 6521.x
(1150)
3P
USB
HDMI
USB
TUNER
51P
11P
ETHER
NET
1G51
1M20
2P
(1163)
1308
1D38
(5213)
8G50
26P
26P
1M84
1M59
4P
(1163)
1M71
4P
AMBILIGHT MODULE
1M99
14P
41P
1G50
LOUDSPEAKER
AL
AMBILIGHT MODULE
(1005)
1M95
HDMI
HDMI HDMI
VGA
AL
B
8M59
26P
MAIN POWER SUPPLY
42" - 47" PLDHP018A
(1027)
1M83
14P
1M99
8M95
TEMP. SENSOR
4P
1T02
8M99
8M71
10P
4P
1319
10P
1M09
1316
1M83
26P
TS
8G51
8308
8M21
INLET
TO DISPLAY
41P
LCD DISPLAY
(1004)
TO DISPLAY
51P
LOUDSPEAKER
LOUDSPEAKER
(5216)
CN1
(5217)
CN2
MAINS
SWITCH
(8308)
IR/LED/CONTROL BOARD
(1108)
1D38 (B03A)
(1115)
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER
1735 (B03A)
1M71 (B09A)
1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL
1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. N.C.
WIFI MODULE
J1
11P
1.
2.
3.
4.
SCL-BL
GND
SDA-BL
+3V3
2011-Jul-15 back to
div. table
1.
2.
3.
4.
LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER
1M20 (B09A)
1. LIGHT-SENSOR
2. LED-1
3. LED-2
4. GND
5. KEYBOARD
6. +3V3-STANDBY
7. RC
8. +5V
9. SCL-SET
10. GND
11. SDA-SET
1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
14. GND
1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP
15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +12V_AL
22. +12V_AL
23. +12V_AL
24. +12V_AL
25. +12V_AL
26. +12V_AL
19110_063_110711.eps
110711
Block Diagrams
Q552.2L LA
9.
EN 68
Block Diagram Video
VIDEO
B01F TUNER
B02 PNX85500
B01K TUNER BRASIL
9
9
3F80
IF-
29
3F81
IF+
30
TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK
60
TS-FE-DATA
2
B02F LVDS
R23
TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21
TNR_SER1_DATA
18
3
19
PX1
LOUT1
TO DISPLAY
25M4
LOUT2
PX2
3
RF IN
2F75
TUN-IF-N
2F79
AE12
PNX-IF-P
BANDPASS
FILTER
N.C.
AF12
PNX-IF-N
PNX-IF-AGC
B04D HDMI
AD12
9
10
DRX0-
21
DRXC+
20
12
DRXC-
19
TO DISPLAY
YPBPR1-PR
3E90
YPBPR1-SYNCIN1
3E87
YPBPR1-PB
3E89
AV3-PR
AC15
YPBPR
AV3-Y
AE15
AV3-PB
AD15
HDMI
SWITCH
ARX2+
72
3
ARX2ARX1+
71
70
ARX1ARX0+
69
RXA
68
19
18
9
10
ARX0-
67
ARXC+
66
HDMI 3
CONNECTOR
12
ARXC-
65
Y_G1
PB_B1
B04B ANALOGUE EXTERNALS B
1
1E08
2
VIDEO
AV2-CVBS
AB14
CVBS-_Y2
B01I VGA
OPTIONAL
1P03
5
RXB
4
9
10
BRX0-
3
BRXC+
2
12
BRXC-
1
10
BRX1BRX0+
1
R-VGA
2
G-VGA
B-VGA
5
7
6
1
BRX2BRX1+
15
1E05
B01C USB HUB
+5V-USB1
1P08
1
B02E CONROL
USB_DN
USB_DP
3
13
14
H-SYNC-VGA
V-SYNC-VGA
17
XIO_D
XIO-D(00-07)
E21 NAND-CE1n
F21 NAND-RDY1n
NAND-WPn
A21
9
7
19
NAND
FLASH
USB
HUB
9
+5V-USB2
1P07
1
10
18
13
21
14
4
SIDE USB
CONNECTOR
22
RESET-USBn
42
21,37
VREF_1
VREF_2
VGA
CONNECTOR
2
3
USB2-DM
USB2-DP
VCC
A2
V1
SIDE USB
CONNECTOR
7FL5
CY7C65631
7F20
H27U4G8F2DTR-BC
B02B MEMORY
2
3
USB1-DM
USB1-DP
9F25
4
B02G
+3V3
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
ONLY FOR 8000 SERIE
B05A DDR
CRX2CRX1+
17
16
CRX1CRX0+
15
14
9
10
CRX0-
13
CRXC+
12
12
CRXC-
11
+3V3-HDMI
9,27,64
B02C HDMI_DV
RXC
VCC33
62
TXC_P
63
TXC_N
60
TX0_P
61
TX0_N
58
TX1_P
59
TX1_N
56
TX2_P
57
TX2_N
HDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX2+
HDMIA-RX23S0W
+3V3
W24
DDR2-D(0-31)
DQ
W25
RXC_A_P
W26
RXC_A_N
V25
RX2_A_P
V26
RX2_A_N
U25
RX1_A_P
U26
RX1_A_N
T25
RX0_A_P
T26
RX0_A_N
HDMIA-RXC+
HDMIA-RXC-
7B00
H5PS1G83E
SDRAM
128Mx8
RREF
A1 E2
A
7B02
H5PS1G83E
SDRAM
128Mx8
A1 E2
7B03
H5PS1G83E
SDRAM
128Mx8
A1 E2
7B01
H5PS1G83E
SDRAM
128Mx8
VDDL
VREF
18
D(24-31)
CRX2+
3
VDDL
VREF
1
D(0-7)
1
2
19
18
HDMI 1
CONNECTOR
R25
B01B FLASH
1P02
4
6
7
9F26
USB-DM
USB-DP
R26
B02A FLASH
NAND_CE1
NAND_RDY1
NAND_WP_
AF16 VGA_R
AD16
VGA_G
AE16
VGA_B
AB18
HSYNC_IN
AC18
VSYNC_IN
1
+VDISP
VDDL
VREF
HDMI 2
CONNECTOR
4
6
7
3
2
8
11
19
18
1
2
3
BRX2+
6
1
40
4
D(16-23)
4
6
7
PR_R_C1
VDDL
VREF
1
2
1P04
PX4
1
23
RXD
22
LOUT4
3 2
DRX1DRX0+
4
6
7
PX3
4
25
24
LOUT3
1
26
DRX2DRX1+
49
40
IF_AGC
D(8-15)
1
2
19
18
HDMI SIDE
CONNECTOR
DRX2+
I2C
1E01
1P05
3
50
TUNER_N
B04A ANALOGUE EXTERNALS A
*7EC1
SII9187BC
SII9287BC
1
1G51
51
3 2
B01H HDMI
TUNER_P
24M
11
TUN-IF-P
1FL5
IF-OUT2
10
B02E
PNX85537
IF-OUT1
RESET-SYSTEMn
41
N.C.
B02I ANALOG VIDEO
42
4
4MHZ_REF
IF AGC
1G50
1
B02A VIDEO STREAM
58
59
61
1FE0
MAIN HYBRID
TUNER
DEMODULATOR
(ISDB-T)
7FE0
TC90517FG
1T01
FA2327
B06B VIDEO OUT - LVDS
7S00
PNX85537EB
A1 E2
DDR2-A(0-14)
+1V8
DDR2-VREF-DDR
*6000/7000 SERIE MUX SII9187 NON INSTAPORT
8000 SERIE MUX SII9287 INSTAPORT
19110_005_110309.eps
110321
2011-Jul-15 back to
div. table
Block Diagrams
Q552.2L LA
9.
EN 69
9-4 Block Diagram Audio
AUDIO
B01K TUNER BRASIL
B02D PNX85500: AUDIO B03A AUDIO
B02 PNX85500
7S00
PNX85537EB
7FE0
TC90517FG
29
3F81
IF+
30
18
ADAC_1
19
ADAC_2
ADAC(2)
AE7
7D15
RESET-SYSTEMn
2F75
11
TUN-IF-N
2F79
PO_7
PNX-IF-P
AE12
PNX-IF-N
AF12
PNX-IF-AGC
B04D HDMI
AC19
AUDIO-MUTE-UP
A-STBY
TUNER_P
TUNER_N
26
3
DRX2DRX1+
25
24
DRX1DRX0+
23
RXD
22
9
10
DRX0-
21
DRXC+
20
12
DRXC-
19
72
ARX2ARX1+
71
ARX1ARX0+
69
68 RXA
67
AE9
4
AUDIO-IN3-R
AF9
VGA
AUDIO
65
70
2
AUDIO-IN4-L
3
AUDIO-IN4-R
AD9
AC9
AIN3_L
AIN3_R
AIN4_L
AIN4_R
1
OPTIONAL
8
3
BRX2BRX1+
7
6
BRX1BRX0+
5
RXB
4
9
10
BRX0-
3
BRXC+
2
12
BRXC-
1
SPDIF-OPT
8000 SERIES
1E07
1
7S09
74LVC00
2
3 &
1
SPDIF-OUT-PNX
AF5
9,27,64
5
SEL-HDMI-ARC
AF18
VO_2
AMP1
2
7
AMP2
3
1
AD6
ADAC(4)
6
ADAC4
IN-2
VDD
8
B01C USB HUB
+5V-USB1
1P08
1
USB_DN
USB_DP
R26
9F26
USB-DM
USB-DP
R25
USB1-DM
USB1-DP
9F25
B01B FLASH
7FL5
CY7C65631
7F20
H27U4G8F2DTR-BC
9
17
USB
HUB
E21 NAND-CE1n
F21 NAND-RDY1n
NAND-WPn
A21
9
7
19
USB2-DM
USB2-DP
14
NAND
FLASH
VCC
+5V-USB2
1P07
1
10
13
18
XIO-D(00-07)
21
21,37
3
CRX2CRX1+
17
16
CRX1CRX0+
15
RXC
14
9
10
CRX0-
13
CRXC+
12
12
CRXC-
11
ARC-eHDMI+
5EC2
HDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX2+
HDMIA-RX2-
eHDMI+
3S0W
+3V3
W24
USB 1 SIDE
CONNECTOR
2
3
4
USB 2 SIDE
CONNECTOR
22
+3V3
RESET-USBn
B02G
ONLY FOR 8000 SERIE
B05A DDR
B02B MEMORY
DDR2-D(0-31)
DQ
7B00
H5PS1G83EFR
SDRAM
128Mx8
RREF
A1 E2
7B02
H5PS1G83EFR
SDRAM
128Mx8
A1 E2
7B03
H5PS1G83EFR
SDRAM
128Mx8
A1 E2
7B01
H5PS1G83EFR
SDRAM
128Mx8
VDDL
VREF
18
W25
RXC_A_P
W26
RXC_A_N
V25
RX2_A_P
V26
RX2_A_N
U25
RX1_A_P
U26
RX1_A_N
T25
RX0_A_P
T26
RX0_A_N
HDMIA-RXC+
HDMIA-RXC-
2
3
4
42
62
TXC_P
63
TXC_N
60
TX0_P
61
TX0_N
58
TX1_P
59
TX1_N
56
TX2_P
57
TX2_N
HEADPHONE
OUT 3.5mm
+3V3
B02E CONROL
NAND_CE1
NAND_RDY1
NAND_WP_
P0_4
IN-1
1
B02C HDMI_DV
CRX2+
14
2
VCC33
1
4
6
7
SPDIF_OUT
B02G STANDBY
8
ADAC(3)
AF7
XIO_D
4
SPDIF-OUT
ADAC3
1328
SHUTDOWN
VO_1
B02A FLASH
+3V3
B03A
HEADPHONE
AMPLIFIER
5
D(24-31)
1
2
19
18
+3V3
6000/7000 SERIES
+3V3-HDMI
1P02
HDMI 1
CONNECTOR
DIGITAL
AUDIO
OUT
2
1
3
SPEAKERS
B04A
VDDL
VREF
4
6
7
1E10
2
7EE0-2
A-PLOP
D(16-23)
HDMI 2
CONNECTOR
BRX2+
5D03
B01J TEMP SENSOR + HEADPHONE
VDDL
VREF
19
18
1
2
1P03
1
1D38
1
7EE1
TPA6111A2DGN
D(8-15)
ARXC-
AUDIO-IN3-L
1E09
66
ARXC+
AIN1_R
B02D PNX85500: AUDIO
6
RES
A-STBY
RESET-AUDIO
VDDL
VREF
12
ARX0-
AF10
AUDIO-IN1-R
AB19
D(0-7)
1
2
19
18
HDMI 3
CONNECTOR
AUDIO IN
L+R
ARX2+
AE10 AIN1_L
1E08
HDMI
SWITCH
3
9
10
2
B04B ANALOGUE EXTERNALS B
1
4
6
7
PO_6
AUDIO-IN1-L
4
7D03
STANDBY &
PROTECTION
B04E HEADPHONE
1E02
AUDIO IN
L+R
1P04
DETECT2
RIGHT-SPEAKER
15
SD
3
PNX85537
1
2
19
18
DRX2+
7D11
MAINS SWITCH
DETECT
2
IF_AGC
B02D AUDIO
4
1
3
4 MUTE
7EE0-1
1P05
HDMI SIDE
CONNECTOR
AD12
B04A ANALOGUE EXTERNALS A
*7EC1
SII9187BCNU
SII9287BCNU
2
B02I ANALOG VIDEO
B02E
B03C
B01H HDMI
IN-R
B04E
OUT-R
BANDPASS
FILTER
1735
1
LEFT-SPEAKER
22
1
TUN-IF-P
6
+24V-AUDIO-POWER
1
IF-OUT2
10
A-PLOP
A-PLOP
1FL5
IF-OUT1
5D07
10,12 5D08
1,3
PVCC_L
IN-L
OUT-L
-AUDIO-R
8
10
B02G STANDBY
42
5
+AUDIO-L
PVCC_R
RF IN
4
6
7
14
12
ADAC(1)
AD7
3 2
IF-
B02D AUDIO
4
3F80
TS-FE-DATA
3 2
9
60
7S05
LM324P
R23
TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21
TNR_SER1_DATA
24M
9
TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK
25M4
4MHZ_REF
IF AGC
58
59
61
1FE0
MAIN HYBRID
TUNER
CLASS D
POWER
AMPLIFIER
B02A VIDEO STREAM
DEMODULATOR
(ISDB-T)
1T01
FA2327
7D10
TPA3123D2PWP
4
B01F TUNER
A1 E2
DDR2-A(0-14)
A
+1V8
VREF_1
VREF_2
A2
V1
DDR2-VREF-DDR
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
*6000/7000 SERIE MUX SII9187 NON INSTAPORT
8000 SERIE MUX SII9287 INSTAPORT
19110_006_110309.eps
110321
2011-Jul-15 back to
div. table
Block Diagrams
Q552.2L LA
9.
EN 70
9-5 Block Diagram Control & Clock Signals
CONTROL + CLOCK SIGNALS
CLK_N
CLK_P
7
ETH-RXCLK
AA3
31
30
20
ETH-TXCLK
AA2
B06C
RXCLK
TXCLK
25M
TS-FE-DATA
19
RESET-SYSTEMn
FLASH
7F20
H27U4G8F2DTR
B02A FLASH
9
7
19
NAND-CE1n
NAND-RDY1n
NAND-WPn
E21
NAND_CE1
F21
NAND_RDY1
A21
NAND_WP_
XIO_D
XIO-D(00-07)
VCC
12,37
B03C
CONNECTORS COMP
2
3
4
6
5
2
6
5
7
8
8
CLK_54_OUT
GPI0_7
9U41
AE26
P5_1
AD19
AC25
P1_0
LED2
LED1
AD26
PWM_0
KEYBOARD
P5_0
AD23
+5V
SUNDANCE / INFINITY
BL_PWM
USB_DN
USB_DP
AA22
LCD-PWR-ONn
AC20
7EC0
EF
P3_2
P3_3
AB22
AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
11
12
13
32
AMBI-TEMP
14
43
3
9GA0
P2_0
AF19
P1_2
B02C HDMI_DV
RX
HDMIA-RX
3S0W
+3V3
TO AMBILIGHT
MODULE
VIO
BACKLIGHT-PWM_BL-VS
B03C
OPTIONAL
B01C
USB HUB
9F26
USB-DM
USB-DP
R25
4
RESET-SYSTEMn
SELECT-SAW
B01F
7FL5
CY7C65631
ETHERNET + SERVICE
9
USB
HUB
+5V-USB2
1P07
1
10
GPI0_3
RXD1-MIPS
2
Y24
TXD1-MIPS
3
21
UART
SERVICE
CONNECTOR
1
2
3
USB-DM2
USB-DP2
13
14
1E06
Y23
SIDE USB
CONNECTOR
ONLY FOR 6000/7000 SERIE
B01K B02G
18
GPI0_2
2
3
USB-DM1
USB-DP1
9F25
17
B02G
GPIO_10
4
SIDE USB
CONNECTOR
22
W24
PNX85500-CONTROL
9CH0
BOOST-PWM
V23
B01E
BACKLIGHT-BOOST
B03C
7F52
M25P05-AVMN6P
SPI_CLK
P6_5
SPI_CSB
SPI_SDO
SPI_SDI
P1_7
RESET_IN
P6_4
AF24
PNX-SPI-CLK
6
AE22
AF23
AE23
PNX-SPI-WPn
3
PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI
1
5
2
AF25
P2_7
P0_4
P2_2
P0_3
P2_6
P0_6
P0_7
FLASH
VCC
8
+3V3-STANDBY
512K
1F51
3
RXD-UP
AE21
AF21
AB20
AA26
1 LEVEL SHIFTED
2
FOR
DEBUG USE
4
ONLY
5
TXD-UP
FF04
SDM
RESET-STBYn
SPI-PROG
AF22
SDM
FF29
+3V3-STANDBY
P2_3
RREF
PNX85500: STANDBY CONTROLLER
B06C
P1_1
CEC-HDMI
7EC1
SII9187BCNU
SII9287BCNU
45
7
20
19
28
PNX85500: MIPS
R26
AF17
2
3
INP OUTP
GND
AD18
RESET-USBn
AD21
ENABLE-3V3n
AF18
AE20
SEL-HDMI-ARC
AE18
RESET-ETHERNETn
AC21
POWER-OK
AF20
STANDBY
RESET-AUDIO
AUDIO-MUTE-UP
LAMP-ON
AB19
AC19
2011-Jul-15 back to
div. table
SPI-PROG
7S20
NCP303LSN28G
AE17
1S02
1
2
19
18
4x HDMI
CONNECTOR
9
3D-LR
BACKLIGHT-PWM
AD5
HDMI
41
AMBI-LATCH1_G2
VCCIO
B04C
XTAL_OUT
HDMI
SWITCH
31
PNX-SPI-SDO
AE4
RESET_SYS
U23
GPI0_11
XTAL_IN
31
35
AMBI-SPI-CS-OUTn_R2
39
41
+5V-USB1
1P08
1
P3_1
DETECT2
RESET-SYSTEMn
B03H
ARX-HOTPLUG
1P02-19
BRX-HOTPLUG
1P03-19
CRX-HOTPLUG
1P04-19
DRX-HOTPLUG
1P05-19
40
4
6
8
PNX-SPI-CLK
PNX-SPI-SDI
PXCLK54
PNX-SPI-CS-BLn
AC5
V22
B02E
P3_0
PNX85500: STANDBY CONTROLLER
TO PIN:
1P02-13
1P03-13 PCEC-HDMI
1P04-13
1P05-13
3
AMBI-SPI-SDI-OUT_G1
AMBI-PWM-CLK_B2
26
PWM_1
7U43
LED-1
B03C
B02E
Y22
B02G STANDBY
DC / DC
RC
+3V3-STANDBY
AMBI-SPI-SDO-OUT
23
29
30
CPLD
ONLY FOR 8000 SERIE
LIGHT-SENSOR
LED-2
27
5
+3V3
1M19
1
4
7
3
1M59
1
AMBI-SPI-CLK-OUT
22
PNX-SPI-CSBn
B02G
54M
NAND
FLASH
PNX85537
7
18
B03D
4
1E70
29
4
3
5
R23
TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21
TNR_SER1_DATA
25M4
IF-
NON DVBS CONNECTOR BOARD
B02G
TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK
1FE0
30
DEMODULATOR
(ISDB-T)
IF+
B09A
7GA0
XC9572XL
B03B
SENSE+1V2
B02E CONTROL
RESET-ETHERNETn
GPIO_1
B02E
AMBILIGHT CPLD
SENSE+1V1
4
TUNER BRASIL
B01F
DDR-CLK_N
DDR-CLK_P
N5
N4
B02H POWER
AF1
VDD_1V1
AA15
VDDA_1V2
5
F8 E8
1
28
B02A VIDEO STREAM
B01F
B04D
F8 E8
DDR2-A(0-13)
RXD
TXD
7FJ0
CXD2820R
B02G
F8 E8
SDRAM
128Mx8
3 2
ETH-RXD
ETH-TXD
ETHERNET
19
TO IR / LED BOARD AND
KEYBOARD CONTROL
F8 E8
SDRAM
128Mx8
4
29
ETHERNET
CONNECTOR
RJ45
*1M20
1
SDRAM
128Mx8
7B01
H5PS1G83EFR
1
RESET-STBYn
B01C
B03C
+12V
+3V3-STANDBY
B02D
B06C
B04C
B01E
RES
DC / DC
CONTROL
ETH-TXP
ETH-TXN
ETH-RXP
ETH-RXN
3
6
B09A
SDRAM
128Mx8
7B03
H5PS1G83EFR
24M
1N00
1
2
B01B
7B02
H5PS1G83EFR
A
ETHERNET + SERVICE
7E10
LAN8710A-EZK
B1K
7B00
H5PS1G83EFR
1
SDIO-DAT2
SDIO-CDn
SDIO-WP
DDR2-D(0-31)
DQ
3 2
SDIO-DAT1
9
10
12
B02B MEMORY
W2
CC_DAT3
W6
CMD
W1
CLK
W5
DAT_0
W4
DAT_1
W3
DAT_2
U6
SDCD
V6
SDWP
1FL5
Pin6 Pin5
Pin4
Pin3
Pin2
5
7
8
Pin8 Pin7
B04C
SDIO-DAT3
SDIO-CMD
SDIO-CLK
SDIO-DAT0
D(24-31)
Pin1
Pin9
1
2
DDR
D(16-23)
1P09
SD-CARD
CONNECTOR
B05A
PNX85500
7S00
PNX85537EB
B02E ETHERNET
D(8-15)
B02A
SD-CARD
D(0-7)
B01D
BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST
ENABLE-3V3-5V
ENABLE-1V8
DETECT2
B03E
B03B B03D
B02G B03A
1M95
9
10
TO
11 POWER SUPPLY
12
2
B04E
B03A
19110_007_110318.eps
110321
Block Diagrams
Q552.2L LA
9.
EN 71
9-6 Block Diagram I2C
I²C
B01E
PNX85500: MIPS
B01J
PNX85500-CONTROL
P3_0
P3_1
FLASH
(4Gx16)
B02A
B02C
AF21
Y25
XIO_D
XIO-D(00-07)
DDC_A_SCL
RXD-UP
3F65
TXD-UP
3F64
3S84
3S83
Y23
Y24
B02I
B02I
VGA_EDID_SCL
44
DRX-DDC-SCL
3E53-4
3E53-3
TXD1-MIPS
3E53-2
3E53-1
1
PNX85500: ANALOG VIDEO
47
UART
SERVICE
CONNECTOR
2
EDID
SW
48
D(0-7)
1
2
VGA-SDA-EDID-HDMI
9FC1
VGA-SCL-EDID-HDMI
9FC3
VGA-SDA-EDID
9FC2
3S5V-3
VGA-SCL-EDID
9FC4
1E05
12
15
VGA
CONNECTOR
RES
+3V3
B02B
MEMORY
DDR2-A(0-13)
A
DDR2-D(0-31)
DQ
B24
3S60
A23
3S61
4_SDA
4_SCL
B01F
RES
TUNER
SDA-TUNER
3F75
TUN-P7
SCL-TUNER
3F76
TUN-P6
ERR
18
7
6
1T01
TH2627
D(24-31)
SDRAM
128Mx8
HDMI
CONNECTOR
SIDE
+5V-VGA
3S5V-1
7B03
H5PS1G83EFR
D(16-23)
7B02
H5PS1G83EFR
16
VGA
+5V-EDID
3
1P05
15
AD24
3S6F
SDRAM
128Mx8
1
2
19
18
DRX-DDC-SDA
1E06
3FE8
3FE9
3EC1-3
3EC1-1
43
ETHERNET + SERVICE
RXD1-MIPS
DIN-5V
AD25
3S6G
SDRAM
128Mx8
HDMI
ANALOGUE
VIDEO
D(8-15)
7B01
H5PS1G83EFR
SDRAM
128Mx8
+3V3
VGA_EDID_SDA
7B00
H5PS1G83EFR
B01H
HDMI
CONNECTOR 1
B01I
B04C
GPIO_2
DDR
15
DDCA-SCL
MAIN
SW
B05A
CRX-DDC-SCL
+3V3
HDMI_DV
GPIO_3
uP
LEVEL SHIFTED
FOR DEBUG
1
USE ONLY
DDCA-SDA
Y26
40
16
1F51
3
RES
DDC_A_SDA
FLASH
1
CRX-DDC-SDA
11
7F20
H27U4G8F2DTR
39
DEBUG
ONLY
HDMI
CONNECTOR 2
1P02
1
2
3S1H
3S1G
AE21
3F62
MAIN NVM
SW
1F52
3
19
18
+3V3-STANDBY
FLASH
3F63
10
ERR
35
15
3S2G
6
AC24
1
MC_SCL
15
CIN-5V
RES
5
EEPROM
(NVM)
3FBF-1
3S2F
MC_SDA
16
BRX-DDC-SCL
3FBF-2
AC23
1P03
BRX-DDC-SDA
3FC2
ERR
53
33
19
18
ERR
15
ERR
23
DEMODULATOR
HDMI
CONNECTOR 3
34
RES
B01B
ERR
42
15
3FC1
STANDBY
SW
6
7F58
M24C64
16
ARX-DDC-SCL
1
2
PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI
5
+3V3-STANDBY
STANDBY
ARX-DDC-SDA
BIN-5V
HDMI
MUX
45
7FE0
TC90517FG
19
18
1
5
2
AF24
SPI_CLK
AE22
P6_5
AF23
SPI_CSB
AE23
SPI_SDO
AF25 SPI_SDI
30
3ECP-1
PNX-SPI-WPn
TEMP
SENSOR
29
3ECP-3
PNX-SPI-CLK
3
3S6V
512K
6
PNX85500: STANDBY
CONTROLER
3S6W
FLASH
VCC
B02G
B02G
SCL-UP-MIPS
46
1P04
3ECA-2
SDA-UP-MIPS
3ECA-1
3S57
AIN-5V
54
7EC1
SII9287B
SII9187A
7FD1
LM75BDP
3F60
1_SCL
53
2
3ECA-4
C26
1_SDA
1
3ECA-3
3S56
3F59
C25
3S69
CONTROL
3S6A
ERR
13
PNX85537
3EC3
SCL-SSB
+3V3
8
TUNER BRAZIL
SDA-SSB
3EC5
3S5Z
3FD3
3_SCL
+3V3-STANDBY
B01K
HDMI
3ECU-4
3S5Y
A24
3_SDA
3ECU-2
B25
3S6D
B02E
7F52
M25P05-AVMN6P
B04D
TEMP SENSOR +
HEADPHONE
+3V3
7S00
PNX85537EB
3FD4
B02E
PNX85500: CONTROL
3S6E
B01E
MAIN
TUNER
ERR
34
ETHERNET + SERVICE
A25
3S5W
3S6B
3S58
AA3
22
23
24
25
ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
AA1
AA4
AB1
AB2
20
ETH-TXCLK
AA2
9S11
SCL-DISP
3G2Y
49
LVDS
CONNECTOR
3C83
1M71
3
1T02
3
3124
SDA-TEMP1
1
3123
SCL-TEMP1
+3V3
ERR
14
RXD_2
RXD_3
RXCLK
W21
GPIO_2
TXD_2
TXD_3
50
SCL-SET
+3V3
RXD_0
RXD_1
TXD_0
TXD_1
3G2W
GPIO_3
W22
2
RXD2-MIPS
TXD2-MIPS
1
7S01
PCA9540B
2 CHAN.
MULTIPLEX.
ERR
24
4
ERR
64
3S66
AC1
SDA-DISP
3S68
ETH-RXD(3)
ETH-RXCLK
2_SCL
9S12
3S65
8
ETH-RXD(2)
Y5
Y6
AB4
SDA-SET
3S67
ETH-RXD(0)
ETH-RXD(1)
3S80
11
10
9
VIDEO OUT - LVDS
1G51
2_SDA
7
ETHERNET
CONNECTOR
RJ45
B26
3S6C
7E10
LAN8710A-EZK
ETHERNET
B06B
+3V3
3S81
B04C
B09A
TS1
DVBS CONNECTOR BOARD
5
3C81
7
1
TEMP SENSOR
8
TXCLK
1
2
RES
9S13
SDA-BL
9S10
SCL-BL
7104
LM75ADP
TEMP
SENSOR
SW
OPTIONAL
2011-Jul-15 back to
div. table
Programmable via USB
19110_004_110309.eps
110321
Block Diagrams
Q552.2L LA
9.
EN 72
9-7 Supply Lines Overview
SUPPLY LINES OVERVIEW
GND1
+12V3
7
7
8
9
8
9
STANDBY
GND1
GND1
B01I
+12V3
+12V3
2
3
4
5
6
6
B04d
STANDBY
B02G
TEMP SENSOR + HEADPHONE
+3V3
+VSND
GND1
7
8
9
BL-ON-OFF
10
BL-DIM1
11
BL-I-CTRL
12
POK
+24V
GND1
+12V
7
8
T 3.0A
9
10
LAMP-ON
B02G
BACKLIGHT-PWM_BL-VS
B06C
BACKLIGHT-BOOST
B01E
POWER-OK
B02G
+1V2-BRA-VDDC
13
14
14
+24V-AUDIO-POWER
7U02-1
12
Dual
Synchronous
7U02-2
Step-Down
Controller
14
+1V2-BRA-VDDC
+1V2-BRA-DR1
+3V3
B03e
5FE4
B03e
1
B02A
B02h,g,B03e +3V3-STANDBY
+5V
DC / DC
+1V8
+1V2
7UA3
B02g,h,
B03e
+3V3
+5V
B03e
PNX85500: SDRAM
+1V8
B03b
+3V3
3U16
+3V3
3U15
3S20
AIN-5V
1P03
18
BIN-5V
1P02
18
CIN-5V
DIN-5V
DIN-5V
B01h
+2V5
IN OUT
COM
DDR2-VREF-CTRL3
3S06
HDMI 2
CONNECTOR
1P04
18
7UC0
+1V8
+3V3
TO
AMBILIGHT
MODULE
+5V
HDMI 1
CONNECTOR
+12V
B03e
5
+5V-VGA
HDMI 3
CONNECTOR
B03b
PNX85500: NANDFLASH
CONDITIONAL ACCESS
+5V
B02B
10
+3V3-STANDBY
+5V-VGA
+5V
COMMON INTERFACE
V-AMBI
B03f
+5V-EDID
B03e
B01A
+3V3-HDMI
1M59
21
B03e
+3V3
B03e
+5V
5EC0
T 2.0A
B03c
+1V8
+3V3
+24V
1C86
+3V3
ONLY 8000 SERIES
B01I
B03D
B03e
HDMI
B03e
+2V5-BRA
IN OUT
COM
+24V
B03c
+1V1
5U01
TO
IR/LED
BOARD
+12V_AL
T 2.0A
+3V3-ET-ANA
+3V3
23
+3V3-BRA-FLT
5E08
B02b,h,B03d,
B05a
7FE3
B09a
8
1C87
+3V3
B04D
12V/1V1
COVERSION
+12V_AL
B03c
ETHERNET + SERVICE
+3V3
+5V
5FE9
+24V
+3V3
8
B03e
7U04
+3V3-BRA
+5V
+5V
1M19 1M20
5
6
+3V3
B04C
+1V8
5U00
7U01
+3V3
5FE7
+3V3-STANDBY
+5V
B03e
+3V3
12V/1V8
COVERSION
TEMP
SENSOR
(OPTIONAL)
B03c
ANALOGUE EXTERNALS B
+12V
B01g
B03b,d,e,g,
B09a
1M71
4
+3V3
B03e
B01g
B02d,B03a
11
12
13
B03c
TUNER BRAZIL
+1V2-BRA-DR1
1U40
+3V3-STANDBY
7U03
TPS53126PW
B03h
+3V3
+3V3
B03e
DC / DC
+3V3
+12VIN
+12VD
B03B
+12V
B01e,B02e,
g,h,B03a,b,h,
B04d,e,B09a
B01K
+AVCC
+3V3-STANDBY
B03c
B01J
B03e
+24V-AUDIO-POWER
B04B
+5V-VGA
+12VIN
+3V3-STANDBY
+24V-AUDIO-POWER
CONNECTORS COMP
+3V3
+3V3-STANDBY
1E05
9
VGA
CONNECTOR
B02E
1M95
1
B04d
B09A
ANALOGUE EXTERNALS A
+3V3-STANDBY
VGA
GND_AL
3D-LR
B03c
B03c
B04A
AUDIO
+3V3-STANDBY
3D09
B03e
2
3
4
5
DIN-5V
B09a
ONLY 8000 SERIES
1M95
1
1P05
18
HDMI SIDE
CONNECTOR
+12V_AL
PSU
3V3SB
HDMI
6EC1
N.C.
B01H
2
3
4
5
6
B03A
DC / DC
1M99
1
5U02
B03C
1M99
1
GND1
2
+12V3
3
GND1
4
+12V3
5
GND1
6
+12V3
B02d,h
+2V5-LVDS
CUA0
DDR2-VREF-CTRL2
B02h
B04E
HEADPHONE
+3V3
+3V3
B03e
+5V5-TUN
+5V5-TUN
B03e
B01B
B02C
FLASH
+3V3
+3V3
B03c
B01f
+3V3
B03e
3UA0
USB HUB
B02D
+3V3
+3V3
B03d
B03e
+5V
+5V
B03e
3F32
B03e
PNX85500: AUDIO
+2V5
+2V5
+3V3
+3V3
3S11
+5V-USB1
+5V-USB2
IN OUT
COM
+T
+24V-AUDIO-POWER
B03c
B01D
3S0Z
SD-CARD
+2V5-AUDIO
+3V3
B03b
B03c
B02h
B02E
B03e
+1V1
+12V
+12V
5UD3
IN OUT
COM
+24V-AUDIO-VDD
5UD2
+3V3
5UD1
+5V5-TUN
IN OUT
COM
B01,a,b,c,d,e,
g,j,k,
B02a,c,d,e,h,
B03c,f,g,h,
B04a,c,d,e,
B06b,c,d,
B09a
+3V3-STANDBY
TEMPSENSOR + AMBILIGHT
+3V3
B03e
+3V3-STANDBY
+3V3-STANDBY
1UM0
V-AMBI
B09a
T 1.0A
+5V
+3V3-STANDBY
B03G
B03c
TUNER
B06C
B03c
+5V-TUN
9F71
B02H
+5V-TUN-PIN
B03b
B03d
B03b
B01G
TOSHIBA SUPPLY
+3V3
7FA3
IN OUT
COM
+3V3
+12V
+12V
5FA3
+1V2-BRA-VDDC
5FA4
+1V2-BRA-DR1
+1V2
+1V2
+1V8
+1V8
B03c
+2V5
B03c
B01k
+3V3
B01k
+3V3-STANDBY
B03e
B03H
+1V1
+2V5-LVDS
B03d
+3V3
+1V1
+2V5-AUDIO
B02d
B06D
PNX85500: POWER
+2V5
B03d
+3V3
B03e
FAN - CONTROL
+3V3
AMBILIGHT CPLD
+3V3
5GA0
VINT
5GA1
VIO
B03e
+5V-TUN
B03d
+3V3
+VDISP
+3V3
B03e
B03e
B01F
VIDEO OUT - LVDS
+3V3
+3V3
+1V1
+3V3-STANDBY
B06b
B03b
5UM1
+1V1
B03b
+5V
PNX85500: STANDBY CONTROLLER
B06B
+VDISP
B06a
PNX85500: CONTROL
B02G
+VDISP
B03e
B03F
+3V3
1G03
T 3.0A
B03d
B01,c,e,k,
B03c,d,e,
B04d,B09a
+5V
+3V3
B03c
+3V3
+VDISP-INT
B03h
7UD1
+24V-AUDIO-POWER
6UD0
+3V3-STANDBY
DISPLAY INTERFACING-VDISP
+VDISP-INT
PNX85500: MIPS
+3V3
DDR2-VREF-DDR
DC / DC
5UD0
+3V3-SD
+1V8
3B20
+2V5-REF
+1V1
+3V3
3F40
+T
B03c
7UA0
VOLT.
REG.
DDR
+1V8
B03b
7UD0
B03e
B01E
+12V
B06A
B03E
+3V3-ARC
7S08
+T
3FL2
B05A
ENABLE-1V8
+12V
B03c
B01C
+3V3-STANDBY
+5V-TUN
7UA6
PNX85500: DIGITAL VIDEO IN
+3V3
B03e
+3V3-STANDBY
+2V5-AUDIO
+3V3
B03e
SPI-BUFFER
+3V3
B03e
VDISP - SWITCH
+3V3
+3V3-STANDBY
+12VD
+3V3-STANDBY
+12VD
7UU0
+VDISP-INT
B06a
+2V5-LVDS
+3V3
7UU2
LCD-PWR-ONn
+3V3-STANDBY
B03c
19110_003_110309.eps
110321
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 73
10. Circuit Diagrams and PWB Layouts
10-1 B01 313912365213
Common Interface
B01A
Common Interface
B01A
CA-CD1n
CA-CD2n
FF05
FF06
3
6
10K
5
10K
3F07-1
1
8
10K
3F07-2
2
7
10K
4
1
CA-MOCLK
CA-MOVAL
CA-MOSTRT
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
CA-RDY
FF08
FF09
CA-VS1n
1X07
REF EMC HOLE
3F07-3
+3V3
3F07-4
3F08-1
8
10K
5
10K
FF07
3F08-3
3
6
10K
3F08-2
2
7
10K
4
3F08-4
RES 1 3F09-1 8
10K
RES 2 3F09-2 7
10K
RES 3 3F09-3 6
10K
RES 4 3F09-4 5
10K
+3V3
IF04
RES 4 3F10-4 5
10K
RES 3 3F10-3 6
10K
RES 2 3F10-2 7
10K
RES 1 3F10-1 8
10K
3F12
10K
2 3F11-2 7
10K
3 3F11-3 6
10K
4 3F11-4 5
10K
8 3F11-1 1
10K
1X04
EMC HOLE
+3V3
IF08
+3V3
1X08
REF EMC HOLE
1X01
REF EMC HOLE
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 74
Flash
Flash
B01B
12
7F20
NAND04GW3B2DN6F
Φ
37
100n
100n
2F21
2F20
+3V3
VCC
[FLASH]
4G × 16
3F20-1 1
8
3F20-3 3
6
3F21-1 1
8
3F21-3 3
6
100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4
2
7
100R
4
5
100R
2
7
100R
4
5
100R
3F22-2
+3V3
XIO-OEn
XIO-WEn
NAND-WPn
2
7
3F23
3F22-4
4
100R
3F22-3 3
10K
3F22-1 1
5 100R
6
100R
8
100R
16
17
9
8
18
19
7
IF22
3F24
+3V3
NC
2K2
CLE
ALE
CE
RE
WE
WP
R
B
IF23
VSS
13
3F19
10K
NAND-RDY1n
0
1
2
3
IO
4
5
6
7
IF21
NAND-CE1n
NAND-CLE
NAND-ALE
29
30
31
32
41
42
43
44
36
XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48
+3V3
B01B
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 75
USB Hub
USB Hub
B01C
B01C
+3V3
USB-OVR1
3FL2
8
26
IFLA
IFL1
IFL2
9F26
9F25
100K
9FLC
9FLD
100K
3FLE-3
6
9
10
3FLF
9FLF
9FLG
10K
IFL3
9FLK
9FLL
USB2-DM
USB2-DP
10K
USB-OVR1
53
51
5
6
42
41
54
1
2
44
43
52
3FLG
+3V3
3FLH
+3V3
10K
GREEN2
AMBER2
SELFPWR
VBUSPOWER
PWR1
OVR1
RESET
PWR2
OVR2
DD+
SPI_CS
SPI_SCK
SPI_SD
DD1DD1+
DD2DD2+
VIA
RES
NC
1P08
Y
Y
Y
Y
1F24
N
Y
N
Y
3FLG
N
Y
Y
N
3FL2
N
N
Y
Y
3FL4
N
N
Y
Y
3FL7
N
Y
N
Y
3F32
Y
Y
Y
Y
3F34
N
Y
Y
Y
7FL5
CY7C65621
CY7C65621
CY7C65631
9FLE 9FLC/D 9F25/6 9FL2
N
N
N
Y
Y
N
N
N
Y
Y
N
N
N
N
N
Y
2FLB 1n0
2FL3
2FLC 1n0
10n
2FLD
2FLA 1n0
10n
100n
10n
100n
2FL2
2FL5
100n
2FL1
2
3FL4-2
FL32
1
2
3
4
5
6 IFLF
7
100K
USB-16-PBT-B-30-CU1-BRF
37
38
IFLB
3F32
+5V
9FLE
4
31
32
25
48
49
3
IFLC
IFLD
IFLE
3FLA
3FLB
3FLC
+T 0R3
3F34-4
100K
3F34-3
USB2
1P07
+5V-USB1
+5V-USB2
6
FL40
FL41
USB2-DM
USB2-DP
100K
10K
15K
10K
+3V3
+3V3
2
3F34-2
7
1
2
3
4
5
6
100K
1 3F34-1 8
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
USB-16-PBT-B-30-CU1-BRF
100K
+3V3
+5V
RES
RES
RES
RES
1
2
3
4
9FL1-1
9FL1-2
9FL1-3
9FL1-4
8
7
6
5
1
2
3
4
9FL2-1
9FL2-2
9FL2-3
9FL2-4
8
7
6
5
(WIFI)
RES 3FLJ
RES
1F24
+T 0R3
FL38
FL39
FL30
USB-WIFI-DDn
USB-WIFI-DDp
1
2
3
4
5
6
7
502386-0570
GND
HS
4
8
12
16
20
24
28
34
40
47
50
56
1P07
N
N
Y
Y
35
36
29
30
USB1-DM
USB1-DP
100K
9FL3
XOUT
GND
SCENARIO
1x USB
1x USB + WIFI
2x USB
2x USB + WIFI
+3V3
GREEN1
AMBER1
9FLH
9FLJ
+3V3
17
18
13
14
100K
RESET-USBn
USB1-DM
USB1-DP
USB-DM
USB-DP
USB2-DM
USB2-DP
USB-WIFI-DDn
USB-WIFI-DDp
46
7
4 3FLE-4 5
3
1P08
FL43
FL36
FL37
+5V-USB1
FL42
3FLE-2
USB1
6
1 3FL4-1 8
10K
45
100K
2
22
VCC
XIN
3FL7
3FLE-1
+5V-USB2
FL31
1
3
3FL4-3
9FL3
N
N
N
Y
57
+5V
10K
21
3
7
11
15
19
23
27
33
39
55
12p
2FL7
7FL5
CY7C65621-56LTXCT
IFLG
3FLD
FL33
100K
100K
IFL4
+3V3
2FL4
2FL8
3
+T 0R3
4 3FL4-4 5
24M
12p
2FL6
4
2
1
1FL5
2FL9
1u0
100n
+5V
9FLF/G 9FLH/J 9FLK/L
N
N
N
N
Y
N
Y
N
N
N
Y
Y
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 76
SD Card
SD-Card
B01D
3F40
+3V3
22u 16V
+T
2F40
B01D
FF45
+3V3-SD
0R3
+3V3
4
3F41-4
IF47
5
47K
SDIO-DAT3
3
3F41-3
6
SDIO-DAT3
2
3F44-2
SDIO-CMD
FF47
7
100R
3
SDIO-CMD
3F43-3
1P09-1
6
FF48
100R
47K
3F45 RES
SDIO-CLK
SDIO-CLK
10K
1
3F44-1
+3V3-SD
8
FF49
100R
2 3F41-2 7
47K
1 3F41-1 8
1 3F42-1 8
47K
SDIO-DAT0
SDIO-DAT0
SDIO-DAT1
SDIO-DAT1
SDIO-DAT2
SDIO-DAT2
47K
2 3F43-2 7
FF41
100R
1 3F43-1 8
3 3F44-3 6
100R
FF42
3F42-2
FF46
SCDA7A0200
1P09-2
7
SDIO-CDn
SDIO-CDn
FF44
SDIO-WP
SDIO-WP
FF50
47K
3 3F42-3 6
14
16
FF43
100R
2
13
15
1
2
3
4
5
6
7
8
9
10
11
12
SCDA7A0200
47K
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 77
PNX85500 Control
PNX85500 Control
+3V3-STANDBY
B01E
+3V3-STANDBY
Q
IF50
512K
FLASH
5
D
BACKLIGHT-BOOST
7F53 RES
PDTA114EU
PNX-SPI-SDO
IF52
6
C
10K
RES
10K
3F67
Φ
3F66
IF53
1
S
PNX-SPI-CSBn
IF54
3
W
7
HOLD
+5V
PNX-SPI-CLK
PNX-SPI-WPn
+3V3-STANDBY
FF29
VSS
IF55
BOOST-PWM
IF61
47K
2
+3V3
+3V3
3F68 RES
PNX-SPI-SDI
3F52
8
7F52
M25P05-AVMN6
VCC
IF51
+3V3
100n
RES
100p
2F52
2F49
+3V3-STANDBY
10K
B01E
7F54-1 RES
BC847BPN(COL) 6
7F54-2 RES
BC847BPN(COL)
SPI-PROG
IF56
4
IF57
2
1
4
FF04
5
IF62
SDM
3
FF58
1K0
RES
RES
3F69
10K
1u0
2F53
MAIN NVM
+3V3
RES
9CH0
10K
3F54
3F53
DEBUG ONLY
IF58
2F58 RES
SCL-SSB
1
2
3
0
1
2
8
WC
ADR
SDA
100R
SDA-SSB
FF63
SCL
3F63
4
100R
SCL
1
2
3
SDA
5
7
6
5
FF55
3F59
100R
3F60
SCL-UP-MIPS
FF56
SDA-UP-MIPS
100R
4
IF59
10K
3F58
Φ
(8K × 8)
EEPROM
RES
1F52
3F62
FF62
100n
7F58
FF61
FF57
LEVEL
DEBUG / RS232 INTERFACE
TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG
FF65
3F64
FF66
100R
SHIFTED
RES
1F51
FF64
3F65
100R
7
6
1
2
3
4
5
UP
FOR
DEBUG
USE ONLY
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 78
Tuner
Tuner
B01F
B01F
IF10
1T01
IF11
*
*
15p
2F65 RES
2F73
AF73
820R
*
1p0
*
*
*
220R
IF16
330n
3F82 RES
4
RES 5F76
AGC CONTROL
10n
3F79-4
5
VAGC
8
4
GND2
10n
IF80
2F70 RES
2F79
2F62
220R
2F72
9F02
IF78
5F74
6
2F82
OUTPUT2
2p2
2F77
INPUT2
*
2F80
3
RES
2F76
1
*
AF72
3F79-1
5F71
IF77
220R
3F81
220R
2
1
IF13
IF-
10n
IF14
2F64
IF15
IF+
10n
* For BR NIM Tuner only
3K3
5F73
3F78
TUN-IF-P
4
470n
3
2F63
2F90
IF86
TUN-IF-N
IF12
15p
10n
1K0
2F92
3F72
BA591
6F72
4K7
9F06
*
3F71
9F05
*
+5V-TUN-PIN
680n
2F66
3F80
IF72
5F66
4K7
5F70
+5V-TUN-PIN
IF74
7
IF76
10n
10n
FF81
FF82
OUTPUT1
9F03
1
VCC
INPUT1
FF01
IF-AGC
RES 2F95
100n
2F93
2F61
2F60
2F59
RES 2F81
IF81
GND
2
2F75
PNX-IF-N
47n
IF-AGC
FF75
TUN-P6
TUN-P7
10n
2F78
*
IF79
2F85
*
9F04
5
4
IF73
*
3F77
100p
100n
4n7
4n7
FF00
TUN-IF-N
TUN-IF-P
IF82
PNX-IF-AGC
RES 2F96
FF76
O1
O2
2F74
X7251M
36M17
100p
AF71
AF70
*
I
ISWI
RES 2F9D
RES 2F9C
RES 2F9B
RES 2F9A
RES 2F99
RES 2F97
RES 2F98
3
FF74
10n
GND1
1
2
6p8
6p8
6p8
6p8
6p8
6p8
6p8
1F75
TUN-P1
+5V-TUN-PIN
7F75
UPC3221GV-E1
IF75
PNX-IF-P
2F71
9F01
9F00
NC
IF_OUT2
13
12
IF_OUT1
11
4MHZ_REF
14
10
B+_TUN
9
8
I2C_SCL
I2C_SDA
7
TUN
5
RF_AGC
4
B+_LNA
3
RF_IO
2
1
16
I2C_ADR
TUNER
15
6
*
FF71
2F91 RES
ATB2012
10n
IF89
47R
2F86
3F75
15p
47R
IF87
SCL-TUNER
IF88
SDA-TUNER
IF90
SELECT-SAW
2F94
TUN-P6
TUN-P7
7F70
PDTC114EU
10n
3F76
15p
RES
2F84
* For EU Hybrid Tuner Only
9F71
5F72 RES
1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74
30R
Component
Europe
Brazil
FA23X7
TH26X3
RES
4u7
5p6
10p
Used
RES
Used
RES
Used
RES
Used
RES
Used
RES
RES
1p0
RES
1p0
12p
15p
12p
15p
18p
22p
560n
680n
680n
820n
22u
Item No.
+5V-TUN-PIN
+5V-TUN
2F88
* Remarks
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 79
Toshiba Supply
Toshiba supply
B01G
+1V2-BRA-DR1
+3V3
5FA4
30R
10u
2
2FA4
OUT
30R
IN
100n
3
5FA3
7FA3
LD1117DT12
2FA3
+1V2-BRA-VDDC
FFAF
1
100n
COM
2FA2
B01G
FFA2
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 80
HDMI
HDMI
B01H
HDMI CONNECTOR SIDE
1P05
DRX2+
DIN-5V
DRX2DRX1+
DRX1DRX0+
DRX0DRXC+
DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22
DRX-DDC-SCL
DRX-DDC-SDA
DRX-DDC-SCL
DRX-DDC-SDA
47K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23
1 3FBF-1 8
B01H
2 3FBF-2 7
DIN-5V
47K
DIN-5V
DRX-HOTPLUG
FFB6
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 81
VGA
VGA
B01I
FFC1
CDS4C12GTA
12V
RES 6FC1
1FC1
100p
RES 2FC1
3FC5
CDS4C12GTA
12V
RES 6FC2
1FC2
100p
G-VGA
18R
1FC3
RES 6FC3
FFC4
100p
RES 2FC3
FFC3
CDS4C12GTA
12V
3FC7
9FC5
H-SYNC-VGA
9FC6
V-SYNC-VGA
4K7
3FC3
CDS4C12GTA
12V
RES 6FC4
1FC4
FFC6
1216-02D-15L-2EC
B-VGA
18R
FFC5
47p
CDS4C12GTA
12V
RES 6FC6
47p
2FC6
10K
RES
3FC2
FFC9
RES 6FC7
47p
2FC7
10K
4K7
3FC4
CDS4C12GTA
12V
RES 6FC5
1FC5
FFC8
CDS4C12GTA
12V
RES
3FC1
47p
2FC5
FFC7
9FC1
VGA-SDA-EDID-HDMI
9FC2
VGA-SDA-EDID
RES
9FC3
VGA-SCL-EDID-HDMI
9FC4
RES
VGA-SCL-EDID
RES 6FC8
1FC6
47p
+5V-VGA
CDS4C12GTA
12V
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2FC4
VGA
CONNECTOR
3FC6
RES 2FC2
1E05
R-VGA
18R
FFC2
2FC8
B01I
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 82
Temp sensor & headphone
Temp sensor & headphone
B01J
SCL
A2
1K0
3FD2
9FD2 RES
9FD1 RES
100n
IFD3
IFD5
5
RES
A1
6
9FD5
+VS
SDA
IFD1
7
A0
1K0
2
8
2FD1
1K0
IFD4
OS
4
100R
100R
1
1K0
3FD7
SCL-SSB
3FD4
3
3FD6
SDA-SSB
IFD2
7FD1
LM75BDP
GND
3FD3
LTST-C190KGKT
RES
RES
3FD1
+3V3
6FD1
RES
1329
5
4
1
2
3
502382-0370
1328
2MSJ-035-69A-B-RF-PBT-BRF
FFDA
AMP1
3
22n
FFDB
22n
2FDD
CDS4C12GTA
12V
2FDC
RES
6FD3
CDS4C12GTA
12V
1FD3
6FD2
1FD2
RES
1
1K0
1K0
3FDG-1
3FDG-2
7
8
AMP2
2
B01J
1
FFDC
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 83
Tuner Brazil
Tuner Brazil
B01K
B01K
5FE0
IF63
IF64
+2V5-BRA
+1V2-BRA-VDDC
+3V3-BRA-FLT
1u0
100n
2FF1
100n
2FF0
100n
2FE5
100n
2FE4
2FE3
1u0
2FE0
30R
AGND
5FE3
IF65
IF66
+3V3-BRA-FLT
5FE4
+3V3-BRA
30R
1u0
100n
2FF6
100n
2FF5
100n
2FF4
100n
2FF3
2FF2
1u0
2FE6
30R
AGND
5FE5
IF67
IF68
+1V2-BRA-DR1
IF48
5FE7
+3V3-BRA
+3V3
1u0
100n
2FF9
100n
2FF8
2FF7
1u0
2FE8
30R
30R
5FE8
IF69
+2V5-BRA
7FE3
LD3985M25
5FE9
1
+5V
30R
18p
4 2
2FG3
18p
2FG2
25M4
1u0
3
100n
2FG1
1
2FG0
30R
1FE0
3
IN
OUT
INH
BP
FF03
5
+2V5-BRA
4
10n
2FG6
2FG7
AGND
2FG9
100n
2FG8
10n
100n
IF17
IF18
30
29
BFE2
28
27
BFE3
100n
2FH6
100n
24
25
2FH7
100n
26
AGND
39
AGND
0
XSEL
1
FIL
PBVAL
RERR
RLOCK
P
ADI_AI
N
RSEORF
SBYTE
P
ADQ_AI
N
SLOCK
P
AD_VREF
N
SRCK
AD_VREF
SRDT
DTCLK
STSFLG1
DTMB
AGCCNTI
21
58
53
54
55
3FG6-4
4
5
33R
TS-BR-VALID
1
9F27-1
8
*
TS-FE-VALID
3FG6-3
3
6
33R
TS-BR-SOP
2
9F27-2
7
*
TS-FE-SOP
*
TS-FE-CLOCK
*
TS-FE-DATA
DFE9
5FG0
3FG7
60
3FG6-2
3FE8
100R
3FE9
IF49
100R
45
46
SCL
SDA
AGND
PLLVSS
SCL-SSB
SDA-SSB
SLADRS
CKI
TN
VSS
0
1
SCL
SDA
33R
2
7
9F28
TS-BR-CLOCK
33R TS-BR-DATA
4
9F27-4
5
30R
5FG2
DFF1
30R
9
3FE5
18K
10
51
1u0
DFE8
DFF2
IF28
IF-AGC
AGND
42
6
5
12
14
3FG2-1
RESET-SYSTEMn
10K
3FG2-2
10K
3FG4-2
4K7
3FG4-1
4K7
+3V3-BRA-FLT
4
15
33
37
44
47
50
57
62
11
SYRSTN
AGCI
17
7
AD_DVSS
10K IF29
STSFLG0
0
TSMD
1
AD_AVSS
3FE7
AGCCNTR
S_INFO
31
1
41
10K
23
8
3FE6
10n
DFE7
IF27
40
+3V3-BRA-FLT
2
DFE6
61
38
1u0
AGND
1n5
59
52
2FH4
* To be drawn near PNX85500
2FH3
2FH5
2FH2
43
DR2VDD
34
48
VDDS
DR1VDD
16
36
56
63
13
35
49
64
Φ
10n
2FG4
IF+
IF-
O
VDDC
2FH8
3
2
X
PLLVDD
18
I
AD_AVDD
19
32
AGND
22
AGND
AD_DVDD
AGND
20
COM
7FE0
TC90517FG
AGND
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_020_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 84
10-2 B02 313912365213
NANDflash - conditional access
PNX85500: NANDflash - conditional access
IS25
00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15
XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO
B22
OE_
C22
WE_
XIO-OEn
XIO-WEn
CLK_BURST
CE1_
CE2_
NAND RDY2
RDY1
WP_
XIO-D10
INPACK
3S15
10K
B21
E21
D21
A20
F21
A21
IS26
INPACK
+3V3
NAND-CE1n
NAND-RDY1n
NAND-WPn
9S08
10K
RES
D22
ALE
NAND
C21
CLE
J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23
D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24
00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15
3S1V
FLASH
10K
3S1W
7S00-5
PNX85500
NAND-ALE
NAND-CLE
B02A
+3V3
IS00
7S00-11
PNX85500
P21
P22
P23
P24
P25
P26
N21
N22
J22
K25
K26
N23
CA-MOCLK
L25
N24
N25
CA-MOSTRT
L22
CA-MOVAL
L23
J21
CA-RDY
L24
L26
J23
J24
VIDEO_STREAM
0
1
2
3
MDI
4
5
6
7
0
1
2
3
MDO
4
5
6
7
10K
+3V3
3S1X
B02A
N26
M21
M22
M23
M24
M25
M26
L21
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
ADD_EN
DATA_DIR
VS
K23
1
K24
2
CD
K21
1
K22
2
DATA_EN
I
MCLK
O
9S00
CA-VS1n
CA-MOCLK
CA-CD1n
CA-CD2n
CA
+3V3
MISTRT
MIVAL
TS-FE-DATA
3S1R
MOSTRT
TS-FE-CLOCK
3S1S
MOVAL
TS-FE-VALID
3S1T
OOB_EN
TS-FE-SOP
3S1U RES
560R
560R
RES
560R
560R
RDY
RST
VCCEN
VPPEN
T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP
TS-FE-DATA
TS-FE-DATA
3S23
TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK
3S24
TS-FE-VALID
3S28
TS-FE-SOP
470R
3S29 RES
TS-FE-ERR
470R
470R
RES 470R
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_021_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 85
SDRAM
PNX85500: SDRAM
B02B
F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5
N
P
DQS0
N
P
DQS1
N
P
DQS2
N
P
DQS3
N
P
CASB
CKE
CSB
ODT
PCAL
RASB
WEB
1
VREF
2
N5
N4
3S30
10R
DDR2-CLK_N
DDR2-CLK_P
3S33
10R
E2
E3
DDR2-DQS0_N
DDR2-DQS0_P
D3
D4
DDR2-DQS1_N
DDR2-DQS1_P
R1
R2
DDR2-DQS2_N
DDR2-DQS2_P
T3
T4
DDR2-DQS3_N
DDR2-DQS3_P
K3
K4
L5
M4
M1
M5
H3
DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE
A2
V1
DDR2-CKE
3S6Q
10K
DDR2-ODT
3S6P
10K
RES
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
3S0V
180R 1%
3S07
3S22
180R 1%
DDR2-VREF-CTRL2
CLK
2S24
FS01
DDR2-VREF-CTRL3
100u 2.0V
FS02
2S12
180R 1%
3S06
3S20
180R 1%
+1V8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
M0
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14
IS42
261R
DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29
0
1
DM
2
3
J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5
1%
D1
D5
R3
T5
0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14
100p
DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3
MEMORY
0
1 BA
2
100n
2S25
DDR2-BA2
H1
H2
G1
DDR2-BA0
DDR2-BA1
100n
2S17
7S00-8
PNX85500
100p
2S20
B02B
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_022_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 86
Digital video in
PNX85500: Digital video in
B02C
7S00-6
PNX85500
T25
T26
HDMIA-RX1+
HDMIA-RX1-
U25
P
U26
RX1_A
N
P
RX0_A
N
HDMIA-RX0+
HDMIA-RX0-
Y26
SCL
DDC_A
Y25
SDA
V25
P
RX2_A
V26
T24
N
HOT_PLUG_A
HDMIA-RXC+
HDMIA-RXC-
W25
P
W26
RXC_A
N
DDCA-SCL
DDCA-SDA
IS10
IS01
3S0W
W24
RREF
12K
10u
+3V3
HDMI_DV
HDMIA-RX2+
HDMIA-RX2-
RES
2S2E
B02C
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_023_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 87
Audio
B02D
PNX85500: Audio
B02D
3S0Z
+24V-AUDIO-POWER
+2V5-AUDIO
3S53-1
4R7
100R
220n
2S3J
2S2S
10u RES
1u0 RES
2S34
2
100u 4V
1u0
2S41
4R7
2S42
10K
7
8
4
IS1S
3S3G-4
100n
DBS8
AE5
10
4
7S05-3
LM324 8
3S39
-AUDIO-R
100R
11
ADAC(3)
33R
5
ADAC(4)
3
3S36-3
10K
6
5
10K
3S3H
ADAC(5)
33R
3S3U
3S36-4
2S2H
4
47p
ADAC(6)
+24V-AUDIO-VDD
33R
SPDIF_OUT
2S3D
AF5
56R
1
33R
AE1
1
AF2
VREF_AADC
2
AE3
I2S_OUT_SD 3
AF3
AC8
VCOM_AADC
4
3S3F
3S36-1
2S2G
9
3S3G-2
2
7
AD8
IS1A
IS03
ADAC(2)
SPDIF_IN1
1n0
IS1B
1u0
AD7
AE7
AF7
AD6
AE6
AF6
AD4
OSCLK
AD1
SCK
AD2
WS
I2S_OUT
AB9
POS
VR_AADC
AB8
NEG
ADAC(2)
33R
1n0
2S38
2S2L
AF8
L
AE8
AIN5
R
6
1n0
2S39
3S10
100R
3S3G-3
1n0
2S3A
1u0
IS07
3
ADAC(5)
4
7S05-1
LM324
1
AUDIO-OUT-L
2
11
3S37
3S6L
10K
22K
2S2K
+3V3
47p
+3V3-ARC
+24V-AUDIO-VDD
3S11
IS1L
1R0
100n
5
ADAC(6)
4
IS06
7S05-2
LM324 7
AUDIO-OUT-R
6
3S6N
14
&
3
2
1 3S18-1 8
IS1G
SPDIF-OUT
220R
RES
100n
2
+3V3
3S32
10K
22K
2S2J
7S09-3
74LVC00APW
9
&
6
14
14
+3V3-ARC
&
5
8
10
2S3L
180R
100n
3S6M
IS1K
2S3M
IS44
eHDMI+
100n
3S25
7
+3V3
14
+3V3-ARC
7S09-4
74LVC00APW
12
&
11
+3V3
13
7
SEL-HDMI-ARC
IS1E
3S34
47p
+3V3-ARC
7S09-2
74LVC00APW
4
11
SPDIF-OPT
47R
7
+3V3
RES
2S3K
7
7S09-1
74LVC00APW
1
IS1D
RES
3S18-2
SPDIF-OUT-PNX
7
SPDIF-OUT-PNX
68R
IS19
3S36-2
ADAC(1)
3
AC6
P
AB6
N
1
2
3
ADAC
4
5
6
AD9
L
AIN4
AC9
R
2S32
33R
1n0
2S3B
7
10K
1 3S3G-1 8
IS1N
1u0
1n0
2S3C
3S17-2
ADACR
AE9
L
AIN3
AF9
R
7
10u
2S3G
22K
AD10
L
AIN2
AC10
R
1u0
IS1Q
3S13-2
+AUDIO-L
47p
2S36
AUDIO
AE10
AC7
L
P
AIN1
ADACL
AF10
AB7
R
N
2S33
8
100n
2S3H
2
3S38
100R
+24V-AUDIO-VDD
6
2S30
8
10K
2
7S05-4
LM324 14
13
11
220R
6
10K
3S17-1
10u
2S3E
AUDIO-IN4-R
22K
2S3F
1
1
IS02
7S00-2
PNX85500
1u0
IS1P
4
12
ADAC(1)
3
2S31
22K
3S13-1
+2V5
10K
RES
3S18-3
5
10K
1u0
6
AUDIO-IN4-L
3S51
1u0
2S3Q
3
4S14
2
2S2Y
3S17-4
3
3S17-3
3
1u0
IS0V
5
3S13-3
INH
IS13
IS1M
10K
AUDIO-IN3-R
22K
4
IS0R
BP
FS03
1
2S2Z
10K
3S13-4
IN
COM
2S2T
100R
6
3S16-4 5
4
10K
OUT
4
1u0
3S16-3 3
4
5
IS12
2S2V
22K
AUDIO-IN3-L
FS08
3S53-4
7
10K
7
100R
220R
2
3S16-2
1u0
3S19
AUDIO-IN1-R
IS1J
2 3S12-2
100R
3S53-3
100n
22K
2S2W
2S2R
8
10u
1 3S16-1 8
10K
IS1H
3S12-1
7S08
LD3985M25
9S06
RES
1
AUDIO-IN1-L
+24V-AUDIO-VDD
+3V3
3S53-2
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_024_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 88
MIPS
B02E
PNX85500: MIPS
B02E
+3V3
7S00-3
PNX85500
CONTROL
+3V3
+3V3
3S80
3S81
10K
RES 3S21
+3V3
10K
3S62
10K
10K
FS10 TXD2-MIPS
FS11 RXD2-MIPS
IS04
GPIO6
PNX-SPI-CS-BLn
+3V3
9S09
GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW
3S55
SELECT-SAW
5K6 1%
+3V3
FS64
B25
SDA
A24
SCL
TRSTN
TMS
TCK
TDO
TDI
RESET_SYS
BL_PWM
10K
CLK_54_OUT
3S83
+3V3
RXD1-MIPS
3S60
B24
SDA
A23
4
SCL
R26
DN
R25
USB
IS4Z R24 DP
RREF
USB-DM
USB-DP
10K
3S64
3
1
100R
1 3S5Y 2
100R
1
100R
1
100R
SDA-UP-MIPS
SCL-UP-MIPS
2 3S5W
SDA-SET
SCL-SET
SDA-SET
SCL-SET
3S6C
4K7
3S5Z
SDA-SSB
SCL-SSB
SDA-SSB
SCL-SSB
3S6E
2K2
3S61
SDA-TUNER
SCL-TUNER
2
2
1
100R
2
AA25
AA24
AA23
AB26
AB25
EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500
3S00
AE4
RES
1F10
3S69
2 3S57
SDA-UP-MIPS
SCL-UP-MIPS
3S6A
SDA-TUNER
SCL-TUNER
4K7
3S6G
4K7
3S6B
4K7
3S6D
2K2
3S6F
2K2
FS44
EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500
FS49
FS50
FS51
FS52
EJTAG-DETECTn
FS53
10 9
1
2
3
4
5
6
7
8
FOR FACTORY
USE ONLY
2K2
3S6K
EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500
1
10K
8 3S6H-1
10K
3
6 3S6H-3
10K
2
10K
FS57
+3V3-STANDBY
+3V3
BM08B-SRSS-TBT
7 3S6H-2
5 3S6H-4
4
10K
RESET-SYSTEMn
33R
AD5
BACKLIGHT-PWM
AC5
10K
BOOST-PWM
+3V3
IS17
1
100R
3S58
1
2
100R
B26
SDA
A25
2
SCL
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11
2
3S27
3D-LR
DS52
10K
3S82
Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23
3S56
10K
+3V3
BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS
1
100R
3S6J
10K
3S40
C25
SDA
C26
SCL
3S26
1
BOOTMODE
RES 10K
IS05
3S45
+3V3
10K
+3V3
3S72
+3V3
IS40
PXCLK54
47R
RES
+3V3
2S89
100n
+3V3
3
TXD1-MIPS
10K
7S01
PCA9540B
VDD
SCL-SET
1
SCL
SDA-SET
2
SDA
INP
FIL
I2 C
-BUS
CTRL
SC0
5
SCL-DISP
SC1
8
SCL-BL
SD0
4
SDA-DISP
SD1
7
SDA-BL
SCL-DISP
SCL-BL
SDA-DISP
SDA-BL
2
3S65
1
4K7
1
4K7
3S67
2
1
4K7
3S68
2
1
4K7
2
3S66
VSS
6
3S84
+3V3
FS31
9S10
IS08
SCL-SET
SDA-SET
IS09
SCL-BL
9S11
FS2W
SCL-DISP
9S12
FS2Y
SDA-DISP
9S13
SDA-BL
7S00-4
PNX85500
ETHERNET
ETH-RXCLK
AA3
ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)
Y5
0
Y6
1
AB4
RXD ETH
2
AC1
3
ETH-RXDV
ETH-RXER
SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
IS50
RXCLK
TXCLK
0
1
AC2
TXD
2
RXDV
Y4
RXER
3
ETH
TXEN
W2
CC_DAT3
TXER
W1
COL
CLK
W6
CMD
CRS
W5
0
MDC
W4
SDIO
1 DAT
MDIO
W3
2
U6
SDCD
V6
SDWP
SPB SSB TV550
2K11 4DDR BR SD
AA2
ETH-TXCLK
AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1
ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_025_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 89
Video out - LVDS
B02F
PNX85500: Video out - LVDS
B02F
7S00-7
PNX85500
PX1APX1A+
A7
B7
PX1BPX1B+
C8
B8
PX1CLKPX1CLK+
9S90
9S91
N
A
P
LVDS
N
B
P
C10
N
CLK
B10
P
A
N
P
B
N
P
CLK
LOUT1 LOUT3
D7
E7
PX3APX3A+
E8
D8
PX3BPX3B+
E10
N
D10
P
9S94
9S95
PX3CLKPX3CLK+
C
N
P
D9
E9
PX3CPX3C+
A11
N
D
B11
P
D
D11
N
E11
P
PX3DPX3D+
PX1EPX1E+
C12
N
E
B12
P
E
E12
N
D12
P
PX3EPX3E+
PX2APX2A+
A14
N
A
B14
P
A
D14
N
E14
P
PX4APX4A+
PX2BPX2B+
C15
N
B
B15
P
B
E15
N
D15
P
PX4BPX4B+
CLK
E17
N
D17
P
C
D16
N
E16
P
PX4CPX4C+
D
D18
N
E18
P
PX4DPX4D+
E
E19
N
D19
P
PX4EPX4E+
PX1CPX1C+
A9
B9
PX1DPX1D+
PX2CLKPX2CLK+
PX2CPX2C+
PX2DPX2D+
PX2EPX2E+
9S92
9S93
N
C
P
C17
N
CLK
B17
P
A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P
LOUT2 LOUT4
9S96
9S97
PX4CLKPX4CLK+
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_026_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 90
Standby controller
PNX85500: Standby controller
B02G
POL
+1V1
B02G
2S13
100n
1u0
2S10
30R
RES
5S04
IS3B
10K
+3V3-STANDBY
3S1H
10K
3S1G
RXD-UP
TXD-UP
10K
3S2A
RXD-UP
TXD-UP
DETECT2
AE21
0
AF21
1
AA22
2
P3
AB22
3
AC22
4
AD22
5
RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS
AD23
0
AE26
1
AE25
P5
2
AE24
3
DETECT2
10K
RES
3S1K
10K
RES
RESET-SYSTEMn
3S1J
100K
RES
KEYBOARD
2S4E
100n
3S1L
10K
SPI-PROG
SPI-PROG
PNX-SPI-WPn
AF22
4
AE22
P6
5
AF26
AC17
EA
ALE
PSEN
MC
EA
AB23
AC23
SDA
AC24
SCL
AD26
0
PWM AC25
1
PSEN
100R
3S2G
3S2F
100R
100R
3S2K
3S2H
100R
AE23
SDO
AF25
SDI
AF24
SPI
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
AF18
P0
4
AA19
5
AB19
6
AC19
7
ALE
ALE
AC26
IS3F
3S44
IS3E
10K
3S43
IS3D
10K 3S42
10K
EA
PSEN
SDA-UP-MIPS
SCL-UP-MIPS
RES
SDA-UP-MIPS
SCL-UP-MIPS
3S6V
4K7
RES
LED1
LED1
LED2
IS2V
CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP
RES
3S41
10K
LED2
10K
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn
IS2Z
3S6W
4K7
3S1P
RES
10K
RES 3S3Y
10K
CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP
10K
3S2L
3S2S
RES
3S3W
4K7
RES
10K
RES
10K
10K
3S46
+3V3-STANDBY
3S47
3S2M
RES
3S49
4K7
+3V3-STANDBY
+3V3-STANDBY
7S20
NCP303LSN28
2
FS45
1
IS2U
5
INP
OUTP
CD
1K0
10K
3S3T
STANDBY
1 3S2V 2
10K
RES 3S3S
AC20
0
AD20
1
AE20
2
AF20
3
AA21
P2
4
AB21
5
AC21
6
AD21
7
RESET-STBYn
FS0Z
RESET-STBYn
1
NC GND
3
3S3P
LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n
AA26
AB24
4
10K
LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n
RESET_IN
100n
3S3M
RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES
XTAL_OUT
+3V3-STANDBY
10p
AF17
2S4K
10K
1
AE17
10p
2S4F
9S0E
3S3L
RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM
2
4
RES
+3V3-STANDBY
RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM
7S00-9
PNX85500
XTAL_IN
2S4G
3
1
9S0D
3S1E
10K
10K
3S1D
27K
DS50
VDD_XTAL
RES
10K
RES
3S1F
AD17
3S1C
AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7
VDDA_ADC2V5
2S4D
1n0
3S1B
VSS_XTAL
+3V3-STANDBY
VDDA_1V1_DCS
AA17
IS20
54M
100n
1S02
9S24
1u0
2S11
RES
2S37
SPB SSB TV550
2K11 4DDR BR SD
4
2011-03-09
2
2010-12-23
3139 123 6521
19110_027_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 91
Power
PNX85500: Power
B02H
5S80
IS3Q
1
100n
2S5A
RES 10u
2
+1V1
2S6A
B02H
30R
5S81
2S5B
RES 10u
1
100n
2S6B
2
+2V5
30R
5S82
IS3S
100n
+3V3
VDD_3V3_SBY
2S5D
2S4M
100n
1
10u
2S4P
100n
2S4N
VSSA_USB
VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB
100n
2S4Y
10u
2S50
100n
2S4Z
6.3V
10u
100n
10u
+1V2
30R
c000
SENSE+1V2
Y17
D13
POL
T20
Y13
+2V5-AUDIO
Y10
100n
VDDA_2V5_USB
30R
R21
R20
100n
2S45
+2V5-AUDIO
5S87
+2V5
1u0
2S56
100n
2S55
30R
5S88
30R
10u
100n
2S57
2S5M
+2V5-LVDS
10u
100n
2S58
100n
2S6K
2
+2V5
30R
1
1
2S6H
2
5S89
5S90
+2V5
10u
100n
100n
2S53
2S4T
30R
2SHW
5S92
1
1u0
100n
2S59
100n
2S6L
2
+3V3
30R
3
2011-03-09
2
2010-12-23
1
2
IS58
2S6M
VDD_1V1_DDR
VSSA_1V1_LVDS_PLL
VDDA_2V5_LVDS_BG
AA7
+2V5
30R
5S84
AA9
2S46
VDDA_2V5_DCS
5S95
Y12
RES 1u0
2S4W
+1V1
IS3L
2S52
VDDA_2V5_ADAC
5S83
B13
2S51
VDDA_2V5_AADC
2S6P
100n
1
100n
Y19
Y18
AA15
Y15
VDDA_1V2
AA13
VDDA_2V5
30R
+3V3-STANDBY
IS3K
VDDA_1V1_LVDS_PLL
+3V3
2
2
100n
2S6C
100n
2S6N
1
2
W20
P20
M20
K20
V7
Y8
100n
1 2S6G 2
5S85
10u
2S4U
VDD_1V1
C7
C9
C11
C14
C16
C18
2S4V
VDD_3V3
+2V5-LVDS
N6
N7
2S6F
VDD_2V5_LVDS
U22
1
VDD_2V5
220u 6.3V
2
100n
2S6E 2
U20
U21
2S6D
HDMI_VDDA_2V5
+2V5
30R
1
HDMI_VDDA_1V1
V20
V21
HDMI_VDDA_3V3_TERM
VSSA_2V5_LVDS_BG
1u0
2S21
100n
2
1
2S5P
VDD
A13
2S29
220u 2.5V
J7
30R
VDD_1V8
C13
100u
2S23
5
100n
5
100n
4
100n
2S5J-4
7
2
1
5S94
+1V1
10u
RES
VSS
2S4S
VSS
VSS
M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20
AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9
U24
V24 HDMI_AGND
3
4
6
100n
2S5H-3
2
100n
2S5J-2
100n
2S5J-1
8
6
100n
2S5J-3
3
3
100n
2S5H-4
8
100n
2S5H-2
100n
2S5H-1
1
6
5
100n
2S5G-4
5
6
7
AA16
AA8
Y11
Y14
Y16
Y9
VSS
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6
A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12
100n
2S5K-4
4
100n
2S5K-3
100n
2S5K-2
2
1
2S5K-1
8
4
3
100n
2S5G-3
7
2
100n
2S5G-2
2S5G-1
1
22u
22u
2S4R
100n
2S4Q
100n
2S27
2S28
100n
2S43
8
7
+1V1
30R
5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7
7S00-10
PNX85500
VSSA
RES 10u
c001
SENSE+1V1
7S00-12
PNX85500
100n
2S5C
2
100n
2S68
100n
2S67
100n
2S66
100n
2S65
100n
2S64
100n
2S63
100n
2S62
100n
2S61
100u
2S60
2S26
+1V8
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
19110_028_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 92
Analog video
PNX85500: Analog video
B02I
2S87
AV1-CVBS
2S8A
Y-SVHS
47R
3S5B
22n
56R
Connectivity
3S59
47R
22n
3S05
B02I
2S7J
AV1-R
C-SVHS
2S22
3S4J
56R
22n
22n
EU: SCART1
CVBS-MON-OUT1
22n
560R
3S5E
2S7K
AV1-B
56R
-
3S4L
AP:
3S08
560R
47p
2S7H
2S40
IS4V
22n
8K2
IS4W
3S09
56R
3S4K
AV1-G
2S7M
YPBPR1-SYNCIN1
10n
2S7L
56R
3S4P
AV3-Y
22n
2S7N
AP:
56R
YPBPR1
YPBPR1
3S4R
AV3-PR
EU:
22n
7S00-1
PNX85500
ANALOG_VIDEO
2S7P
2S8G
AV2-CVBS
*
9S18
22n
AB14
AF14
AE14
AC14
AD14
2S7R
AV4-Y
SCART2
YPBPR2
22n
9S19
EU:
AP:
AF15
AE15
AC15
AD15
AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25
P
SCL VGA_EDID
TUNER N
SDA
AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12
IS5E
3S5S
10K
IS5D
IS5F
IS5G
IS5H
IS5J
3S75
BS15
PNX-IF-AGC
10K
BS10
IS11
3S76
10n
2S76
AA14
PNX-RF-AGC
47K
9S20
22n
2S14
BS13
AGND
AV4-PR
2S15
22n
AD11
AC11
+CVBS
2S7U
2S16
22n
22n
22n
IS5C
2S18
22n
AC12
AF13
2S19
CVBS_Y1 ATV_CVBS_Y3
C3
R
B AV1
CVBS_Y7
G
C7
SYNCIN1
CVBS1_OUT
Y_G1
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CURREF
CVBS_Y2
SYNCIN2
1
Y_G2
2
PR_R_C2
3
PB_B2
REF
4
5
R
G VGA
6
B
IF_AGC
HSYNC_IN
RF_AGC
IN
VSYNC
OUT
10n
AB15
AC13
AD13
AE13
22n
2S75
56R
3S4T
AV3-PB
2S77
PNX-IF-P
10n
2S7E
AV4-PB
9S21
22n
2S78
PNX-IF-N
10n
2S84
56R
3S50
R-VGA
22n
2S85
56R
3S52
G-VGA
22n
2S86
7
100R
100R
3S5V-2
2
4
3S5V-4
5
7
5
4
8
100R
100R
V-SYNC-VGA
3 3S5T-3 6
3S5T-2
1
2
3S5T-1
H-SYNC-VGA
100R
AP: VGA
22n
3S5T-4
56R
EU: VGA
3S54
B-VGA
100R
VGA-SCL-EDID
VGA-SDA-EDID
RES
RES
3
1
3S5V-3
100R
3S5V-1
* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ
6
8
100R
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_029_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 93
10-3 B03 313912365213
Audio
Audio
B03A
+AVCC
7D03-1
BC847BS(COL)
+24V-AUDIO-POWER
6
3D09
+24V-AUDIO-POWER
FD14
1
B03A
220R
3
6
3D02-3
5
3
7D15-2
BC847BS(COL)
4
4K7
ID19
ID18
6
L
2D16
2D17
ID29
ID30
1u0
AUDIO-MUTE-UP
2D26
RES
1
2D22
220n
3D14-1
220n
8
7
3D14-2
22K
2
6
3
3D14-3
22K
5
3D14-4
22K
22K
R
BSR
R
OUT
L
0
GAIN
1
BSL
16
ID32
2D10
5D05
ID06
22u
22
21
5D02
ID10
220n
15
5D01
ID09
ID31
2D09
22u
ID05
2D12
220R
ID08
35V 220u
5D04
ID07
2D11
220R
RIGHT-SPEAKER
LEFT-SPEAKER
35V 220u
220n
11
7
4
2
1u0
7D10-1
TPA3123D2PWP
PVCC
CLASS-D
AUDIO AMP
IN
5
L
Φ
R
18
17
GND-AUDIO
1
3
AVCC
47n
4K7
1u0
GND-AUDIO
10
12
2D23
ID15
19
20
2D29
3D02-1
1
8
FD03
220n
4
GND-AUDIO
+AUDIO-L
2D08
4
7D15-1
BC847BS(COL)
1
220u 35V
2
4K7
ID28
2D19
7 3D02-2 2
47n
ID27
2D07
FD08
3D02-4
A-PLOP
6
4K7
1u0
220u 35V
2D24
ID14
2D20
2D28
5
FD01
GND-AUDIO
220n
2D05
10u 35V
22K
-AUDIO-R
220R
5D08
5D07
ID12
220n
3D16
ID11
2D06
2
4R7
VCLAMP
BYPASS
MUTE
SD
ID37
PGND
3
ID34
2D21
220n
3D10-1
220n
1
2D27
RES
8
7
3D10-2
22K
2
6
3D10-3
22K
3
4
FD10
3D10-4
22K
CD10
22K
4K7
5
8
9
MAINS SWITCH DETECT
GND_HS
3
2
7D11-1
BC847BS(COL)
1
3D15
6
+3V3-STANDBY
3D01-3
47K
6
R
25
L
23
24
AGND
13
14
FD09
A-STBY
GND-AUDIO
+3V3-STANDBY
ID35
5
5
DETECT2
GND-AUDIO
LEFT-SPEAKER
VIA
VIA
VIA
VIA
37
36
35
34
GND-AUDIO
10n
26
27
28
29
V_NOM
2D14
GND-AUDIO
GND-AUDIO
GND-AUDIO
40
39
38
7D10-2
TPA3123D2PWP
1D50
GND-AUDIO
3D01-4
47K
100p
GND-AUDIO
4
2D03
7D11-2
BC847BS(COL)
4
VIA
1D38
30
31
32
33
1735
LEFT-SPEAKER
3
100K
6
7
100K
100K
10n
4
RIGHT-SPEAKER
ID33
1D52
GND-AUDIO
3D06-4
2041145-3
2041145-4
5
100K
4
1
2
3
2
8 3D06-1 1
RIGHT-SPEAKER
10n
2D13
3D06-2
FD02
1
2
3
4
2D02
V_NOM
3D06-3 FD07
GND-AUDIO
2D01
220R
GND-AUDIO
3 7D03-2
BC847BS(COL)
FD05
FD06
5D03
5
10u
GND-AUDIO
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_030_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 94
DC/DC
B03B
DC/DC
B03B
5U03 RES
30R
5U02
+12V
1u0
2U20
10u
10u
*
IU22
30R
0402 Jumper
7 8
IU10
12V/1V8 CONVERSION
1
2
3R3
3U11
2U19
2U25
7U02-1
SI4952DY
10u
10u
2U23
2U24
FU05
FU02
2U21
5U00
FU03
22u
47u
2U16
1
47R
2U15
8
7
2
47R
3U23-1
3U23-2
3u6
5 6
IU23
4
1n0
2U17
3
IU09
3
4
7U02-2
SI4952DY
47R
3U23-4
47R
3U23-3
5
220p
6
+1V8
IU11
IU15
IU08
5 6 7 8
IU12
4
3U14
IU07
GND-SIG
20
3U28
GND-SIG
18
19
FU04
1u0
2U05
10u
2U04
6
10K
100n
2U14
RES 100u 2.0V
22u
IU17
IU25
GND
+1V1
IU18
GND-SIG
1u0
1n0
2U10
GND-SIG
2U09
3U21
FU00
SENSE+1V1
IU19
IU04
GND-SIG
2U07
22K
3U10
GND-SIG
RES 100p
FU09
1K0 1%
3U09
330R 1%
CU00
5K6
3U19
3U22
+1V8
1K0 1%
3U08
2U08
IU20
FU08
100n
RES
2U29
3U17
1% 330R
3U18
1% 1K0
100R 1%
100p RES
10K
V5FILT
VREG5
VIN
7
17
2U13
1
2
47u
TEST
2U12
1
TRIP
2
22
15
10R
RES
1
2
+1V1
3U20
PGND
FU01
2u0
47R
1
VFB
2
5U01
FU06
24
13
47R
3U24-1
1
2
3U24-2
SW
12V/1V1 CONVERSION
1
12
47R
1
VO
2
1 2 3
3U24-4
1
2
4
IU14
47R
3U24-3
21
16
DRVH
5 6 78
IU16
23
14
1n0
IU02
1
EN
2
2U06
3U00
3U01
3U03
12K
GND-SIG
1
2
2U11
22K
3
1
2
+3V3-STANDBY
5
8
IU01
DRVL
7U04
SI4778DY
6U00
1n0 RES
2U03
IU03
4
9
+1V1
+1V8
1
VBST
2
220p
STPS2L30A
3
10
ENABLE-1V8
3R3
2U01
100n
2
11
IU24
GND-SIG
3U02
3U05
7U03
TPS53126PW
IU13
10R
2U02
100n
7U00
BC847BW
3R3
2U22
IU06
IU05
RES
1 2 3
3R3
10u
2U00
10R
3U04
1n0
3U27
2U18
7U01
SI4778DY
IU21
CU01
CU02
CU03
CU04
CU05
GND-SIG
GND-SIG
GND-SIG
GND-SIG
GND-SIG
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 65213
19110_031_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 95
DC/DC
B03C
DC/DC
B03C
+3V3-STANDBY
+3V3
RES 10K
+5V +3V3-STANDBY
3U75
3U74
RES 10K
LED-2
**
IU43
*
RES 10K
3U69
10K
3U68
9U41
optionally 1M99 is a 9 pin connector
IU44
3U41
IU45
9U42
RES
LED-1
LED2
LED2
10K RES
4U00
4U01
1M99
1M95
2U56
3U59
IU47
7U43
BC847BW
Emmy
( +24V AL)
yes
yes
no
yes
no
Sundance / Infinity
( +12V AL)
no
no
yes
yes
yes
BlockBuster
(For non-Amblight sets)
no
no
no
yes
no
***
Optional table for Styling
Dream Catcher
Core Range
1M95
2U44
3U43
0R
open
13 POLE
100p
100R
14 POLE
10K RES
7U42 RES
BC847BW
*
Optional table for Ambilight
Items
+3V3
3U70
LED1
LED1
10K
3U53
10K
**
1M99
1K0 RES
4
3D-LR
100R
FU56
FU57
FU74
FU68
RES 3U66
100R
BL-SPI-SDO
RES 3U67
100R
BL-SPI-CSn
RES 3U84
100R
BL-SPI-CLK
100K
IU41
100p
100p
100p
100p
2U71
MAINS-OK
+3V3-STANDBY
100R
4
RES 2U43
RES 2U52
RES 2U51
RES 2U72
1n0
RES 3U76
RES 2U48
2U56
**
1n0
RES 2U57
1-2041145-3
100p
+12VIN
2
FU77
100R
7U48-2
BC857BS(COL)
STANDBY
5
5
3U71
3U62-4
100R
FU53
10K
2
2
FU72
DETECT2
7
3
5
4
IU50
6
10K 1
7U41-1
BC847BS(COL)
1
3U60-4
7U41-2
BC847BS(COL)
5
22K
IU62
4K7
3U62-1
RES 10K
7
3U61
10K
6
3U60-2
4
8
3U60-1
IU57
1
ENABLE-3V3n
22K
IU52
8
2
BACKLIGHT-PWM_BL-VS
***
3U43
BACKLIGHT-BOOST
100R
FU55
IU55
3U64
POWER-OK
100p
1n0
10n
2U45
2U46
100K
***
2U44
+12VD
1n0
GND_AL
2U53
1K0
3U65
**
3U42
3U62-2
ENABLE-1V8
RES 10K
100n
100R
FU52
LAMP-ON
FU73
22K
IU63
3U73
+3V3-STANDBY
3K3
3U45
FU51
IU49
6
7U40-1
BC847BPN(COL)
3U80
2U55
IU56
10K
4U00
2
100K
IU40
3U63
+3V3
GND-AUDIO
3U81
3 3U60-3 6
IU61
1
1K0
3U72
100n
2U49
+24V
4U01
3U83-2
3
2
10n
+24V-AUDIO-POWER
2U50
T 3.0A 32V
FU66
FU76
**
7
6
100K
22K
IU51
3U62-3
3
+12V
+12VIN
FU67
1-2041145-4
+12VIN
1U40
2U54
BZX384-C6V2
10n
1u0 RES
+3V3-STANDBY
6U40
FU58
FU59
FU60
FU61
FU63
FU75
FU62
4
IU48
3U83-3
5
10n
2U58
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
4
1u0
2U47
***
7U40-2
BC847BPN(COL)
10K
2U68
1M95
ENABLE-3V3-5V
8
RES 3U44
7U48-1
BC857BS(COL)
5
1
FU07
FU54
3U83-4
6
FU50
100K
10K
3U83-1
GND_AL
RES 3U56
+3V3
+12V_AL
1
FU49
100n
GND_AL
IU64
3U82
FU48
3
GND_AL
1
2
3
4
5
6
7
8
9
10
11
12
13
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 96
DC/DC
B03D
DC/DC
B03D
+3V3
*
7UC0
LF25ABDT
+12V
1
IN
3
OUT
2
1u0
2UA4
*
2K2
3UA0
COM
FUA0
+2V5-REF
R
7UA0
TS2431
K
1
A
2
3
FUA4
+2V5
CUA0
IUB6
+2V5-LVDS
+5V-TUN
2
*
+3V3
8
+5V
1
3U16-1
100R
3UB0
2
2
1u0
2UB0
7UA3
PHD38N02LT
IUB4
IUA5
3
22R
4
FUA3
3U15-2
100R
3U15-3
100R
3U15-4
+1V2
8
+3V3
100R
2
7
6
3
5
4
3U16-2
100R
3U16-3
100R
3U16-4
100R
7
6
5
100R
1u0
2UB1
470R
2
470R
3UB7-3
3
3UB7-1470R
8
1
3U15-1
IU26
7UA7-1
BC847BS(COL)
3U13
6
3UB7-2
7
2UB8
7UA7-2
4
BC847BS(COL)
1
+5V
2UB2
5
*
+1V8
1
470R
22u
+2V5-REF
6
1K0 IUB2
3UB6-2
2
7
6
1K0
3UB6-1
1
8
1K0
IUB5
3 1
RES 1u0
3UB6-4
4
5
1K0
3UB7-4
4
5
3UB6-3
330R
1%
3
+12V
7UA6
BC817-25W
3U12
IUB3
330R
1%
+5V5-TUN
*
NOT FOR 5000 SERIES
ENABLE-1V8
5
+12V
RES
7UA4
TS431AILT
5
RES
2
A
K
NC
REF
470R
NC
470R
3U26-2
7
3
4
3U26-3
470R
3U26-4
IUB1
1
3UB3
RES
470R
+3V3
BP
+5V-TUN
4
COM
3
1 3U26-1 8 RES
2
INH
5
1u0
470R
3U29-4
3
OUT
100n
2UB6
4
5
3UB2
IN
2UB5
3 3U29-3 6 RES
IU30
1
+5V5-TUN
470R
2
7UA5
LDS3985M50
2
RES
7U06-1
BC847BS(COL)
1
7
RES
1u0
5
+3V3
470R
3U29-2
8
2UB7
6
8
3
RES
7U06-2
BC847BS(COL)
4
2
3U29-1
4K7
1
3U25-1
RESERVED
5UA0
1K0
30R
1
IU29
SENSE+1V2
4K7
7
3U25-2
6
IUA6
4
3U25-3
2
3
100K RES
100K RES
3UB1
100K RES
100K RES
4
3U25-4
3UB5
3UB4
100K
1K0
IUB0
2UB3
+5V
6
5
RES
1n0
2UB4
330p
RES
RES
470R
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 97
DC/DC
DC/DC
B03E
5UD0
FUD3
4n7
3UD2
33K
1%
12
68K
3UD1
1%
3UD0
15
13
VIA
10
2
7U05-1
BC847BS(COL)
RES 1
22u
100n
IU27
3U06
120K
10K
2UD6
2UD7
IUD6
7UD0-2
ST1S10PH
RES 2U27
6
RES
8
+1V1
220u 16V
SS36
RES 2UE9
+5V
3u6
3
VFB
GND
P HS
A
6UD0
IUD7
22u
SYNC
5UD1
22u
2UD5
5
VIN
IUD3
7
SW
2UD4
INH
9
2
4
RES 1n0
2UD3
ENABLE-3V3-5V
SW
A
6
1
7UD0-1
ST1S10PH
10u
2UD2
10u
2UD1
+5V5-TUN
10u
*
IUD0
30R
0402 Jumper
2UD0
+12V
14
11
5UD3
+3V3
7U05-2
RES
4
3U07
100n
IU28
RES
33K
1%
12
1M0
3UD5
3UD4
VIA
10
5
15
13
IUD2
7UD1-2
ST1S10PH
BC847BS(COL)
10K
3
RES 2U28
2UE4
22u
22u
2UE3
+1V1
220u 16V
4
FUD2
3u6
3
VFB
GND
P HS
8
A
5UD2
2UE2
SYNC
IUD4
7
SW
VIN
1% 100K
5
INH
2UE1
2
9
ENABLE-3V3-5V
4n7
3UD3
A
SW
6
1
7UD1-1
ST1S10PH
10u
14
11
7UD2
LD1117DT25
3
IN
S1D
OUT
2
+2V5
2UE6
1
100n
2UE5
COM
22u 16V
IUD5
(*) FOR 5000 SERIES ONLY
(**) NOT FOR 5000 SERIES
7UD3
LD1117DT33
IN
OUT
2
+3V3
100n
COM
22u 16V
3
2UE8
6UD1
+5V
1
*
2UE7
10u
2UD9
10u
*
IUD1
30R
0402 Jumper
2UE0
* *
+12V
2UD8
B03E
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 98
Temperature sensor & AmbiLight
B03F
Temperature sensor & AmbiLight
B03F
5UM1
IUM0
1UM0
+3V3
30R
FUM0
V-AMBI
T 1.0A 63V
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 65213
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2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 99
Fan control
Fan control
B03G
+12V
+12V
1K0
FAN-CTRL1
IUS3 3US5-1
8
1
8
IUT1
100n
7US1-1
LM339P
14
2US3
3
10K 7
10K
9
2
3US7
+12V
3US5-2
10K
3US2
1 3US4-1 8
+3V3
IUS6
10K
7US2
BC807-25W
12
+12V
IUS7
3
IUT2
FAN-CTRL2
7US1-2
LM339P
13
IUS4 3US5-4
5
4
10
10K
22R
BC807-25W
7US3
IUS8
12
3US6
IUS9
47R
11
3
+12V
3US3
10K
3US5-3
6
3US9
+3V3
10K
FAN-DRV
+3V3
3
10K
7US1-3
LM339P
2
10K
3US4-3
3
5
4
+12V
6
IUS5
3US4-4
5
+12V
4
12
TACH01
RES
+12V
3
7
2
10K
7
+12V
3US4-2
9US0
TACH02
7US1-4
LM339P
1
6
FUS0
12
B03G
TACHO
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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110415
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 100
Vdisp switch
Vdisp switch
B03H
1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES
RES
7UU0
SI4835DDY
6
RES 3UU0-4
+3V3-STANDBY
5
47K
2
4
RES
7UU2-1
PUMD12
1
7
6
FUU0
5
2
IUU2
1u0
3UU3-2
22n
+VDISP-INT
1
47K RES
RES 2UU1
47R
IUU1
RES 3UU0-1
8
1
47K
8
IUU3
7
47K RES
RES
7UU3
BC847BW
3
VDISP-SWITCH
1
IUU4 3UU3-3 IUU5 3UU3-4
4
5
6
3
47K RES
2
FUU1
3UU2
+3V3
47K RES
RES 100n
3
IUU0
5
47K
RES 3UU1
5
3UU3-1
6
2UU0
8
4
7
RES 2UU2
+12VD
RES
7UU2-2
PUMD12
8
RES
7UU1
SI3441BDV
RES 3UU0-2
7
2
B03H
+3V3
4K7 RES
LCD-PWR-ONn
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 101
10-4 B04 313912365213
Analogue externals A
Analogue externals A
B04A
IE22
CDS4C12GTA
12V
1E31
2E88
1n0
CDS4C12GTA
12V
1E54
2E91
1n0
8
RES 6E03
FE23
3E07-4
1K0 5
RES
2
** 4E02
YPBPR1-PB
3E17
IE05
100p
**
FE74
+3V3
1E01-2
MSP-8033SH-02-NI-FE-RF-PBT-BRF
BLUE
3
4E04
RES
3E44
RES
2E15
150p
18R
2E80
150p
2E79
AV2-STATUS
4
3E75
1E12
BEC3
1u8
CDS4C12GTA
12V
5E73
RES 6E23
IE53
RES
FE73
EU 3E74 18R
AV1-B
1E02-2
MSP-8032SH-01-NI-FE-RF-PBT-BRF
WHITE
3
4K7
3E32
** 4E01
IE18
AV1-STATUS
4K7
1E02-1
MSP-8032SH-01-NI-FE-RF-PBT-BRF
RED
1
**
4
4K7
RES
100p
4
2E04
1K0
100p
2E06
1
AUDIO-IN1-L
FE71
3E07-1
AUDIO-IN1-R
6E09
B04A
IE48
AV1-BLK
YPBPR1-SYNCIN1
1E01-3
MSP-8033SH-02-NI-FE-RF-PBT-BRF
GREEN
5
EU 3E76 18R
** 4E05
1E01-1
MSP-8033SH-02-NI-FE-RF-PBT-BRF
RED
1
RES
4E03
RES
2
100p
2E12
1E19
18R
CDS4C12GTA
12V
FE81
RES 6E28
2E86
150p
2E85
1u8
**
EU 3E78
18R
BEC5
3E79
5E76
150p
IE55
CVBS-MON-OUT1
18p
YPBPR1-PR
AV1-R
4K7
3E73
100p
2E14
IE51
AV2-BLK
FE85
2E98
RES
6
FE80
1E18
18R
CDS4C12GTA
12V
1u8
+3V3
RES
RES 6E26
3E77
150p
5E74
2E84
150p
2E83
AV1-G
FE86
GND_A
3E07-2
2
1K0
7
3E07-3
3
1K0
6
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_038_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 102
Analogue externals B
B04B
Analogue externals B
B04B
SPDIF out
YPBPR
GND_A
GND_A
30R
AV2-CVBS
3E89
IE75
RES
6E46
IE73
RES
1E07
MTJ-032-68B-46-NI-FE
1
FE59
CDS4C12GTA
12V
SPDIF-OUT
RES
5E06
2
FE41
AV3-PB
18R
YPBPR1-PB
IE76
9E58
3E90
IE77
AV3-PR
18R
CDS4C12GTA
12V
FE42
RES
IE74
9E57
EU
RES 6E52
1E39
100p
2E68
1
** 4E22
IE15
27R
FE48
MTJ-032-21B-42 NI FE
2
1E04
3E88
9E04
CDS4C12GTA
12V
1E28
100p
RES
2E67
1
** 4E21
AP
EU
2
1E03
AV3-Y
YPBPR1-SYNCIN1
FE51
MTJ-032-21B-45 NI FE (PBT)
FE72
10p
RES 1E44
RES
3E87
18R
CDS4C12GTA
12V
RES 6E40
4E20
RES 6E51
**
1E43
100p
YELLOW
2E27
1
IE71
9E29
RES 2E22
1E08-1
*
MSP-8033SH-05-NI-FE-RF-PBT-BRF
EU
FE54
2
YPBPR1-PR
GND_A
Provision for
Dreamcatcher
YPBPR AUDIO
+3V3
MSP-8033SH-05-NI-FE-RF-PBT-BRF
6
FE49
GND_A
100p
2E72
3E96
RES 6E38
1E42
1n0
**
2E40
4
1E08-2
3
*
MSP-8033SH-05-NI-FE-RF-PBT-BRF
RES
WHITE
4E24
AV3-Y
AV1-CVBS
9E15
9E16
RES
RES
AV3-PR
RXD1-MIPS
9E19
9E12
RES
RES
AV3-PB
TXD1-MIPS
9E17
9E14
RES
RES
AUDIO-IN3-R
AV1-B
9E11
9E18
RES
RES
AUDIO-IN3-L
AV1-G
9E13
9E20
RES
RES
AV1-R
9E22
RES
AV1-STATUS
AUDIO-IN1-R
AV1-BLK
9E24
9E25
9E26
RES
RES
RES
AUDIO-IN1-L
9E28
RES
IE29
AUDIO-IN3-L
1K0
100p
GND_A
IE31
2E71
FE43
RES
RES
1E32
AUDIO-IN3-R
1K0
CDS4C12GTA
12V
RED
1E29
1n0
** 4E23
CDS4C12GTA
12V
FE50
5
RES 6E06
1E08-3
2E39
*
3E97
VGA ( OR DVI ) AUDIO
AUDIO-IN4-L
1K0
100p
CDS4C12GTA
12V
3E21
RES 6E19
V_NOM
1n0
1E37
2E36
FE02
IE09
2E35
1E09
MSJ-035-69A-B-RF-PBT-BRF
2
3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
31
DF50-30DP
FE01
AUDIO-IN4-R
100p
1K0
2E38
CDS4C12GTA
12V
RES 6E20
V_NOM
1n0
1E38
2E37
IE10
3E20
FE03
1E10
3150-831-030-H1
2
VCC
FE44
SPDIF-OPT
CDS4C12GTA
12V
RES 6E53
V_NOM
100p
1E80
100n
3
RES 2E77
GND
MT
7 6 5 4
1
2E73
VIN
1R0
3E9C
+3V3
* SOC Cinch V 3P 1L3 YEWHRDY at 1E08 for Brazil
** Provision for ESD
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 103
Ethernet & Service
3E53-2
IE49
RXD1-MIPS
IE07
3E53-3
IE50
47R
6E43
+3V3-ET-ANA
100n
10u
2E63
100n
2E66
30R
6E44
+3V3
2E62
4
3
BZX384-C5V1
5E08
6
1
2
47R
3E53-1
47R
3E53-4
FE56
8
5
MSJ-035-69A-B-RF-PBT-BRF
FE58
PROVISION FOR iTV
IE38
IE32
10u
2E48
2E49
100n
ETH-TXD(3)
ETH-TXER
12
20
ETH-TXCLK
ETH-RXDV
IE63
+3V3
10K
3E34
10K
3E72
3E68
RES
3E35
RES
10K
1
1
X1
+3V3
ETH-INTSEL
10K
+3V3
9E42
14
2
RXD-UP
ETH-REGOFF
ETH-CRS
32
RBIAS
IE39
MDC
MDIO
3
RXD1-MIPS
1
1
X1
VSS
13
RES
7E11-2
74HC4066PW
4
RES
7E12
PDTC144EU
RES
7E13
PDTC144EU
AV2-BLK
5
33
+3V3
RES
7E11-1
74HC4066PW
1
10K
10K
RES
2
CRS
ETH-RXCLK
RES
3E9E
3E65
3
REGOFF
1
LED
2
INTSEL
+3V3
10K
10K
RES
RES
3E9D
3E64
IE64
7
provision for iTV
ETH-RXER
14
13
BAS316
ETH-TXP
ETH-TXN
RES
6E48
29
28
26
RXER
RXD4
0
PHYAD
1
RXCLK
0
1
2 TXD
3
4
INT
TXER
ETH-RXP
ETH-RXN
100n
P
N
RXDV
TXEN
17
16
ETH-MDC
ETH-MDIO
TX
31
30
7
22
23
24
25
18
4
7
21
ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
P
N
14
+3V3
ETH-TXEN
RX
TXCLK
COL
CRS_DV
MODE2
1
2
3
5
502382-0370
RES
2E69
0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>
15
10K
10K
IO
RST
10K
RES 3E71
RES 3E80
1A 2A
VDD
3E40
19
+3V3
12K1
1%
CLKIN
1
XTAL
2
10p
1
27
CR
RES 2E70
1K5
6
10p
2E54
10p
2E55
RES
RES
RES
RES
7E10-1
LAN8710A-EZK
11
10
9
8
3E51
4n7
100n
2E53
2E52
TXD
RXD
ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)
3E70
RES
RES
1E71
25M
5
4
ETH-COL
IE06
IE33
1M0
1E70
NX3225GA
3E33
3E66
3E67
3E81
3E82
10K
10K
10K
10K
10K
3E30
3E69
RES
10K
B04C
+3V3
+3V3-ET-ANA
IE26
UART
SERVICE
CONNECTOR
47R
+3V3
RESET-ETHERNETn
1E06
2
3
1
FE57
1E85
7
1E86
TXD1-MIPS
BZX384-C5V1
Ethernet & Service
B04C
34
35
36
14
7E10-2
LAN8710A-EZK
VIA
40
41
42
VIA
9
TXD-UP
1
1
X1
6
14
37
38
39
7
VIA
RES
7E11-3
74HC4066PW
8
10
TXD1-MIPS
1
1
12
7
X1
RES
7E11-4
74HC4066PW
11
+3V3-ET-ANA
+3V3-ET-ANA
22R
22R
3E98
3E26
3E99
49R9
1%
3E95
49R9
1%
3E25
49R9
1%
3E22
49R9
1%
CONFIGURATION RESISTOR SETTINGS
Resistor
POP
EMPTY
ETHERNET CONNECTOR
ETH-TXP
1E87
3 ACM2012 2
FE27
1N00
FE60
1
ETH-RXP
FE29
1E88
3 ACM2012 2
ETH-RXN
FE31
4
FE30
FE61
22n
9 11
10 12
2E60
5
CDA5C16GTH
16V
6E47-4
4
CDA5C16GTH
16V
RES
6
6E47-3
3
7
2
CDA5C16GTH
16V
RES
6E47-1
15p
1
RES
RES
2E59
5E04
RES 27n
2E09
RES 15p
0 ohm
RES
15p
3E39
RES
2E58
5E03
RES 27n
2E08
RES 15p
0 ohm
RES
15p
3E29
2E57
RES
5E02
RES 27n
2E07
RES 15p
0 ohm
RES
15p
3E28
2E56
RES
5E01
RES 27n
2E05
0 ohm
RES
3E27
RES 15p
8
1
6E47-2
4
FE28
CDA5C16GTH
16V
RES
ETH-TXN
FE34
1
2
3
4
5
6
7
8
3E64 (RES)
PHYADD(0) = 1
PHYADD(0) = 0
3E65 (RES)
PHYADD(1) = 1
PHYADD(1) = 0
3E66 (RES)
PHYADD(2) = 1
PHYADD(2) = 0
3E67 (RES)
RMII mode selected
MII mode selected
5450-323-183-H3
3E68 (RES)
Internal 1.2V reg. disabled
Internal 1.2V reg. enabled
3E69 (RES)
MODE(0) = 0
MODE(0) = 1
3E70 (RES)
MODE(1) = 0
MODE(1) = 1
3E71 (RES)
MODE(2) = 0
MODE(2) = 1
FE32
3E72
ETH-INTSEL
ETH-REGOFF
FE33
INTERRUPT FUNCTION
INTERRUPT FUNCTION
DISABLED ON
ENABLED ON
nINT/TXER/TXD4 SIGNAL
nINT/TXER/TXD4 SIGNAL
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_040_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 104
HDMI
HDMI
B04D
ARX2+
10K
1u0
10u
100n
2ECV
FEC0
2EC0
220u 16V
RES 2EC1
1P04
3ECH
ARX1ARX0+
ARXCARXC+
65
66
BRX2+
ARX0ARX0+
67
68
BRX2BRX1+
ARX1ARX1+
69
70
BRX1BRX0+
ARX2ARX2+
71
72
AIN-5V
HDMI CONNECTOR 2
BIN-5V
BRX-HOTPLUG
47K
3ECM-3
6
10R
7
100K
1u0
BRX-DDC-SDA
BRX-DDC-SCL
IE43
2ECN
35
36
33
34
CEC_D
N
R0X0
P
FECC
FECD
BRX-DDC-SCL
BRX-DDC-SDA
FECE
FECF
BIN-5V
47K
BRX-HOTPLUG
1
20
22
3ECA-1
8
BRX-DDC-SCL
BRX-DDC-SDA
BIN-5V
HDMI CONNECTOR 1
2
CIN-5V
CRX2+
3ECM-2
7
3
3ECN-3
10R
CRX-DDC-SDA
CRX-DDC-SCL
1u0
PCEC-HDMI
4
47K
3E23
100R
IEC4
3ECM-1
8
10R
1u0
DRX-DDC-SDA
DRX-DDC-SCL
5
6
BRX2BRX2+
7
8
IE44
41
42
39
40
CRXCCRXC+
11
12
CRX0CRX0+
13
14
CRX1CRX1+
15
16
CRX2CRX2+
17
18
5
100K
30R
ARC-eHDMI+
2ECC
IE45
2ECQ
5EC2
eHDMI+
CIN-5V
7EC0
BC847BW
3ECD
+3V3-STANDBY
22K
RES
RES
7E02
BC847BW
1
DIN-5V
4
3ECN-4
10p
20
22
47K
CRX-HOTPLUG
3ECA-3
CIN-5V
3
FECM
FECN
BRX1BRX1+
DRX-HOTPLUG
CRX-DDC-SCL
CRX-DDC-SDA
6
FECK
FECL
3ECA-4
FECA
5
CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA
FECJ
3
4
2ECP
CIN-5V
CRX0CRXC+
BRX0BRX0+
6
100K
CRX2CRX1+
CRX1CRX0+
1
2
CRX-HOTPLUG
1P02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23
BRXCBRXC+
45
46
43
44
DRXCDRXC+
19
20
DRX0DRX0+
21
22
DRX1DRX1+
23
24
DRX2DRX2+
25
26
IEC6
9EC0
CEC-HDMI
IEC5
100n
49
6
10K
8
DSCL4
DSDA4
N
R0XC
P
2EC3
38
37
9
27
64
R4PWR5V
48
47
VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI
9EC2
RES
51
CEC-HDMI
N
R0X1
P
N
R0X2
P
(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1
TX2
N
P
TX1
N
P
TX0
N
P
TXC
N
P
7
3ECA-2
BRXCPCEC-HDMI
3
BIN-5V
2
BRX0BRXC+
2
3ECN-2
DSDA0
DSCL0
+5V-EDID
3
29
30
(CBUS) HPD0
R0PWR5V
N
R1XC
P
N
R1X0
P
57
56
HDMIA-RX2HDMIA-RX2+
59
58
HDMIA-RX1HDMIA-RX1+
61
60
HDMIA-RX0HDMIA-RX0+
63
62
HDMIA-RXCHDMIA-RXC+
3ECJ RES
N
R1X1
P
TPWR_CI2CA
N
R1X2
P
CEC_A
(CBUS) HPD2
R2PWR5V
INT
4K7
55
50
52
IE12
FECR
RES
3ECK
MICOM-VCC33
4K7
9EC3
RES
FECY
PCEC-HDMI
3ECL RES
+3V3
4K7
DSDA2
DSCL2
N
R2XC
P
CSCL
CSDA
N
R2X0
P
RSVDL
N
R2X1
P
54
53
10
28
N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA
N
R3X0
P
N
R3X1
P
N
R3X2
P
3EC3
3EC5
100R
100R
SCL-SSB
SDA-SSB
10p
2ECM
31
32
10K
3ECP-3
1u0
IE42
1
10R
ARX-DDC-SDA
ARX-DDC-SCL
8
100K
30R
10p
RES 2ECY
1
3ECN-1
RES 2ECX
5
SBVCC33
AIN-5V
3ECM-4
3ECP-1
8
4
MICOM_VCC33
1
47K
ARX-HOTPLUG
3EC1-1
ARX-HOTPLUG
10u
RES 2ECW
100n
100n
2EC8
VCC33
AIN-5V
20
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23
100n
2EC7
2EC6
6
47K
3EC1-3
3
7EC1
SII9187B
ARX-DDC-SCL
ARX-DDC-SDA
FEC4
FEC5
+3V3
+3V3-HDMI
ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA
RES
5EC3
FEC7
AIN-5V
ARX0ARXC+
FEC1
FEC2
SII9187B = 0xB2
FECB
ARX2ARX1+
1P03
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
73
EPAD
3ECE
22K
IEC7
FECW
+3V3-STANDBY
6EC1
+5V
7EC1
3ECN
3ECF
NON-INSTAPORT
9187B
4X 100K
100K
BLOCKBUSTER
INSTAPORT
9287B
4X 100K
100K
SUNDANCE
+5V-VGA
BAT54
IE11
3ECG
3ECF
4R7
FECP
30R
MICOM-VCC33
2EC2
5EC0
+3V3
HDMI CONNECTOR 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23
B04D
I2C Address
FEC3
FECZ
100K
DDCA-SDA
IE65
2
3ECU-2
7
+3V3
10K
2ECU
DDCA-SCL
IE66
4 3ECU-4 5
10K
1u0
SPB SSB TV550
2K11 4DDR BR SD
+5V-EDID
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_041_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 105
Headphone
Headphone
B04E
+3V3-STANDBY
5
4
PUMD12
7EE0-2
A-PLOP
3
6
A-STBY
FEE0
2
RESET-AUDIO
7EE0-1
PUMD12
1
2EE0
22K
3EE1-3
5
22K
3EE1-2
3EE1-4
2
4
6
8
22K
3
47p
3EE1-1
7
1
22K
2EE5
7EE1
TPA6111A2DGN
100n
2EE1
47p +3V3
8
3
IEE2
ADAC(4)
2EE3
1u0
IEE1
2EE4
1u0
8
3EE0-1
10K
Φ
IEE3
1
2
5
3EE0-4
4
10K
6
IEE4
5
2EE2
3
AMPLIFIER
2EE6
1
IEE7
4
33R
3EE2-4
6
FE36
5
VO
SHUTDOWN
BYPASS
2
VIA
GND GND_HS
2EE7
7
IEE8
2
4V 100u
10
11
AMP1
33R
4V 100u
2
3EE2-3
1
3EE2-2
33R
3EE2-1
FE35
7
AMP2
8
33R
3 3EE0-3 6
10K
22K
A-PLOP
1
IN-
4
1u0
IEE6
IEE5
1
VDD
9
IEE0
ADAC(3)
RES
3EE3
B04E
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_042_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 106
10-5 B05 313912365213
DDR
DDR2-CLK_P
DDR2-CLK_N
3B28
DDR2-CLK_P
240R
DDR2-CLK_N
DDR2-BA2
DDR2-ODT
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2
F9
E8
F8
F2
G8
F7
G7
F3
B3
RES
240R
3B01
3B23
NU|RDQS
2
6 3B02-3
33R 3
8 3B02-1
33R 2
3B02-2
5
33R
3B02-4
4
8
33R
C8
3
C2
D7
1
D3
D1
D93B00-4 4
B1
B9 3B00-11
B7
A8
3B00-2
7
33R
6 3B00-3
33R
7
33R
5
33R
2p2
DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23
3B12
33R
3B13
2B44
RES
0
1 BA
2
DDR2-DQS2_P
DDR2-DQS2_N
33R
A2
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
G2
G3
G1
DDR2-BA0
DDR2-BA1
DDR2-BA2
DDR2-ODT
ODT
3B03
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
NC
L3
L7
DDR2-A14
VSSQ
VSSDL
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3
RES
240R
F9
E8
F8
F2
G8
F7
G7
F3
B3
3B24
33R
2B17
100n
2B37
100p
VDD
VDDL
VDDQ
E2
A9
C1
C3
C7
C9
E1
A1
E9
L1
H9
100n
100n
2B16
100n
2B15
100n
2B14
100n
2B13
100n
2B12
100n
2B11
100n
2B10
E2
A9
C1
C3
C7
C9
E1
DQS
A3
E3
J1
K9
33R
2B41
2B36
100p
2B08
100n
G2
G3
G1
DDR2-BA0
DDR2-BA1
DQ
0
1
2
3
4
5
6
7
VREF
Φ
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
SDRAM
DQ
0
1
2
3
4
5
6
7
DQS
C8
3B05-3
C2
D7
3B04-3
D3
D1
D93B04-4
B1
B93B04-1
3
3
4
1
B7
A8
2B45
0
1 BA
2
NU|RDQS
3B04-2
2
7
6
33R
6 33R
33R
7 3B05-2
33R 2
1
8 3B05-1
33R
5
5 3B05-4
33R
4
8
33R
33R
3B15
RES
2p2
3B14
33R
DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31
DDR2-DQS3_P
DDR2-DQS3_N
33R
A2
ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
+1V8
NC
L3
L7
DDR2-A14
VSSQ
VSSDL
A7
B2
B8
D2
D8
3B27
240R
Φ
SDRAM
B05A
DDR2-VREF-DDR
E7
DDR2-CLK_N
7B03
EDE1108AGBG-1J-F
VREF
VDDQ
A3
E3
J1
K9
DDR2-CLK_P
240R
VDDL
A7
B2
B8
D2
D8
3B22
VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
E7
AT T-POINT
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A1
E9
L1
H9
7B02
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
+1V8
DDR2-VREF-DDR
100n
100n
2B07
100n
2B06
100n
2B05
100n
2B04
100n
2B03
100n
2B02
100n
2B01
47u
2B00
2B40
+1V8
47u
2B09
DDR
B05A
+1V8
DDR2-VREF-DDR
3B25
33R
FB00
1X20
HOOK1
1X21
HOOK1
1X22
HOOK1
1X23
HOOK1
DQS
C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1
B7
A8
2B46
0
1 BA
2
NU|RDQS
2
5
33R
7
33R
5
33R
8
33R
3B17
RES
2p2
3
1
3
3B07-2
7
33R
6 3B07-3
33R
8 3B08-1
33R
6 3B08-3
33R
3B16
33R
DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7
DDR2-DQS0_P
DDR2-DQS0_N
33R
A2
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
G2
G3
G1
DDR2-BA0
DDR2-BA1
DDR2-BA2
DDR2-ODT
ODT
3B09
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
NC
VSSDL
L3
L7
DDR2-A14
VSSQ
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1
RES
240R
3B26
33R
F9
E8
F8
F2
G8
F7
G7
F3
B3
2B35
100n
2B39
100p
VDD
VDDL
VDDQ
E2
A9
C1
C3
C7
C9
E1
A1
E9
L1
H9
100n
100n
2B34
100n
2B33
100n
2B32
100n
2B31
100n
2B30
100n
2B29
100n
2B28
47u
2B27
2B43
2B26
100n
2B38
100p
E2
DQ
0
1
2
3
4
5
6
7
180R 1%
3B21
E1
SDRAM
A3
E3
J1
K9
DDR2-VREF-DDR
Φ
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
VREF
Φ
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
SDRAM
DQ
0
1
2
3
4
5
6
7
DQS
C8
C2
3B11-3 3
3B10-3 33R 3
D7
D3
D1
D93B10-4 4
B1
B9 3B10-1 1
B7
A8
2B47
0
1 BA
2
NU|RDQS
6
6 33R
2 3B10-2 7
33R
2
1
5 3B11-1
33R
4
8
33R
3B19
RES
2p2
7 3B11-2
8 33R
33R
5 3B11-4
33R
3B18
33R
DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15
DDR2-DQS1_P
DDR2-DQS1_N
33R
A2
ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
NC
VSSDL
L3
L7
DDR2-A14
VSSQ
A7
B2
B8
D2
D8
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0
F9
E8
F8
F2
G8
F7
G7
F3
B3
RES
240R
3B06
7B01
EDE1108AGBG-1J-F
VREF
E7
3B20
180R 1%
DDR2-ODT
VDDQ
A3
E3
J1
K9
DDR2-BA2
+1V8
VDDL
A7
B2
B8
D2
D8
DDR2-BA0
DDR2-BA1
G2
G3
G1
VDD
E7
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A1
E9
L1
H9
7B00
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
A9
C1
C3
C7
C9
100n
100n
2B25
100n
2B24
100n
2B23
100n
2B22
100n
2B21
100n
2B20
100n
2B19
47u
2B18
2B42
DDR2-VREF-DDR
1X24
HOOK1
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_043_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 107
10-6 B06 313912365213
Display interfacing-Vdisp
Display interfacing-Vdisp
B06A
1G03
T 3.0A 32V
5G01
FG0H
1G00
+VDISP-INT
100n
T 3.0A 32V
RES
2G43
+VDISP
30R
RES
5G02
22u
RES
30R
RES
2G44
B06A
RES
3G28
2K2
IG11
RES
6G00
LTST-C190KGKT
For Development use only
SPB SSB TV550
2K11 4DDR BR SD
3
2010-03-09
2
2010-12-23
3139 123 6521
19110_044_110415.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 108
Video out - LVDS
Video out - LVDS
B06B
47p
47p
47p
2G27
2G24
2G25
47p
2G7A
2G26
47p
47p
2G78
2G79
47p
47p
2G76
47p
47p
10K
RES 3G35
2G75
10K
9G0K-4
9G0K-3
9G0K-2
9G0K-1
5
6
7
8
RES
2G77
10K
RES 3G34
+VDISP
RES 3G33
+3V3
FI-RE51S-HF
60 61
58 59
56 57
54 55
52 53
4
3
2
1
100n
2G93
100n
2G94
100n
FG2J
2G95
100n
FG30
FG31
FG32
FG33
2G96
2G99
2G97
2G98
PX3APX3A+
PX3BPX3B+
PX3CPX3C+
PX3CLKPX3CLK+
47p
47p
47p
47p
FG11
FG1J
PX3DPX3D+
PX3EPX3E+
PX4APX4A+
PX4BPX4B+
PX4CPX4C+
FG12
FG13
FG14
PX4CLKPX4CLK+
FG18
FG15
FG16
FG17
FG19
FG1A
FG1B
FG1Q
FG1P
CTRL-DISP
SDA-DISP
SCL-DISP
RES 3G32
3G2W
3G2Y
CTRL-DISP
RES 3G38
RES 3G37
BACKLIGHT-BOOST
3D-LR
CTRL-DISP
CTRL-DISP
3D-VS-DISP
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FG1C
FG1D
FG1E
FG1F
FG1G
FG1H
FG1K
FG1L
FG1M
FG1N
PX4DPX4D+
PX4EPX4E+
FI-RE41S-HF
51
50
48
49
46
47
44
45
42
43
RES 3G2Z
FG04 RES 3G30
RES 3G31
RES 3G36
100R
100R
100R
FG34
FG2H
FG2G
100R
100R
FG35
FG2R
100R
100R
100R
100R
FG2K
FG2L
FG2M
FG2E
FG2F
FG1Y
PX1APX1A+
PX1BPX1B+
PX1CPX1C+
FG21
PX1CLKPX1CLK+
FG22
FG23
PX1DPX1D+
PX1EPX1E+
FG24
FG25
FG26
FG27
FG1Z
FG20
10p
10p
2G28
2G29
PX2APX2A+
PX2BPX2B+
PX2CPX2C+
FG28
FG29
FG2A
FG2B
FG2C
FG2D
PX2CLKPX2CLK+
FG1R
FG1S
PX2DPX2D+
PX2EPX2E+
FG1T
FG1U
FG1W
FG1V
FG2P
+VDISP
100n
2G92
2G91
B06B
RES 9G0G
FG2N
1G50
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1G51
TO DISPLAY
TO DISPLAY
1X05
REF EMC HOLE
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 109
AmbiLight CPLD
AmbiLight CPLD
B06C
B06C
5GA0
FGA0
+3V3
VINT
5GA1
100n
100n
2GA2
2GA1
1u0
2GA0
30R
DEBUG ONLY
FGA1
+3V3
VIO
+3V3
100n
10K
RES
4
3
2
1
5
6
7
8
100R
100R
100R
100R
RES
RES
RES
RES
26
IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR
IGA2
IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28
IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38
IGA1
CPLED2
CPLED3
5
6
7
8
12
13
14
16
18
19
20
21
22
23
27
28
TCK
TDI
TDO
TMS
PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK
9GA1 RES
3GA1
4
3G10-4
2
3G10-2
3G12
4
3G11-4
RES
47R
5
33R
3
7 3G10-3
33R
3G13
1
10R
5 3G10-1
33R
IGA3
GCK2
+3V3
3
+3V3
AMBI-SPI-CS-EXTLAMPSn
6
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS
33R
8
33R
RES
7GA1-1
BC847BS(COL)
1
2
GTS1
+3V3
3
RES
7GA2-2
BC847BS(COL)
4
5
GTS2
GND
4
17
25
+3V3
RES
7GA1-2
BC847BS(COL)
4
5
GCK3
AMBI-PROG_B1
AMBI-BLANK_R1
6
33R
10p
11
9
24
10
3GA5-4
3GA5-3
3GA5-2
3GA5-1
SD51022
10p
2G19
29
30
31
32
37
38
IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18
10p
2G18
33R
3
33R
10p
10p
2G12
10p
2G11
10K
2G10
3G14
1
6
33R
3G11-3
8
3G11-1
IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42
10p
2G16
36
34
33
GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2
3G15
33R
GCK3
GTS1
GTS2
GSR
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R
10p
2G15
3GA3
VCCIO
10p
2G14
PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
2
3
39
40
41
42
VCCINT Φ
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3
2G13
43
44
1
15
35
7GA0
XC9572XL-10VQG44C0100
PXCLK54
GCK2
GCK3
VIO
1
2
3
4
5
6
+3V3
10p
RES
VINT
2GA6
3GA4
RES
1G37
10p
2G17
2GA5
1u0
2GA3
30R
+3V3
6
6 330R 3
RES
3GA6-3
5 330R 4
RES
3GA6-4
RES
3GA6-1
FGA3
+3V3
SD51022
BACKLIGHT-PWM
9GA0
LTST-C190KGKT
FGA5
FGA2
RES
6GA3
FGA4
LTST-C190KGKT
FGA6
RES
6GA2
1
2
3
4
5
6
LTST-C190KGKT
100R
100R
100R
100R
RES
6GA1
8
7
6
5
RES
6GA0
1
2
3
4
LTST-C190KGKT
2GA4
8
100n RES
RES 3GA2-1
RES 3GA2-2
RES 3GA2-3
RES 3GA2-4
8 330R 1
RES
1G36
1
2
3
4
5
6
7
RES
3GA6-2
DEBUG ONLY
RES
1G35
RES
7GA2-1
BC847BS(COL)
1
2
7 330R 2
GSR
BACKLIGHT-PWM_BL-VS
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
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110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 110
SPI buffer
SPI buffer
B06D
RES
+3V3
20
3EN1
3EN2
G3
PNX-SPI-CLK
PNX-SPI-SDO
RES
7GE0
74LVC245A
1
PNX-SPI-CSBn
IGE0
19
3
2
1
2
17
16
15
14
13
12
11
3GE0-3
47R
3
4
5
6
7
8
9
3GE1-3 6
3GE4
RES
3 RES
47R
3GE3
47R
6 RES
1
BL-SPI-CLK
3GE0-1
5
8 RES
47R
4 3GE1-4
47R RES
BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI
RES
47R
10
AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI
18
RES
7GE1
PDTC114EU
10K
100n
RES
3GE2
+3V3
RES
2GE0
B06D
PNX-SPI-CLK
8
RES
9GE0-1
1
BL-SPI-CLK
PNX-SPI-SDO
7
RES
9GE0-2
2
BL-SPI-SDO
BL-SPI-SDI
RES 9GE1
PNX-SPI-CS-BLn
RES 9GE2
RES
5 9GE0-4
IGE1
PNX-SPI-SDI
*
** 4
BL-SPI-CSn
Buffer
*
**
Direct
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_047_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 111
10-7 B09 313912365213
Connectors comp
Connectors comp
B09A
FC67
+3V3
30R
1M59
FC78
3C70
100R
FC79
100n
2C70
FC81
GND_AL
*
1C86
FC83
+24V
FC82
AMBI-POWER
100n
RES
2C95
FC84
100n
* 1C87
2C94
T 2.0A 63V
+12V_AL
100p
IC73
100R
2C78
IC74
3C77
100p
LED-2
100R
LED-1
FC91
FC92
3C78
100p
100R
2C80
FC95
KEYBOARD
FC93
FC94
+5V
3C79
100p
FH34SRJ-26S-0.5SH(50)
T 2.0A 63V
FC90
100p
28
1
2
3
4
5
6
7
8
FC89
2C79
IC75
1M19
FC88
+3V3-STANDBY
10R
2C96
TO
LED PANEL
100n
FC76
RC
2C81
FC77
47n RES
6C02
AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP
2C77
3C76
2C93
2C82
100n
RES
RES
V-AMBI
100p
100R
6C05
FC75
3C75
LIGHT-SENSOR
RES
BZX384-C5V6
FC74
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
2C76
FC87
BZX384-C5V6
FC73
AMBI-PWM-CLK_B2
6C03 RES
FC72
V-AMBI
BZX384-C5V6
FC71
AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
3C74
FC70
AMBI-SPI-CLK-OUT
100K
RES
5C55
**
B09A
GND_AL GND_AL
RES 3C96
+T
ITEMS
BLOCKBUSTER
EMMY
SUNDANCE
/ INFINITY
1C86
N
Y
N
1C87
N
N
Y
1
2
3
4
SDA-SET
FC64
* RES 3C92
FH52-11S-0.5SH
RES
1M71
FC96
FC97
FC98
1
2
3
4
2041145-4
TEMPERATURE
SENSOR
100R
* RES 3C93
10K
RES 5C54
RES 5C53
+12V
30R
T 1.0A 63V
RES
1C85
30R
IC78
1u0
FC99
+3V3
FC66
1u0
100R
RES 3C83
47R
RES
**
FC86
FC65
1u0
2C91
RES 3C82
RES
0R3
2C90
FC63
3C95
+T
47R
**
100R
RES3C81 100R
+3V3
FAN-DRV
8
7
6
5
10p
FC85
3C94
10p
2C87 RES
RES 3C80
9C00
RES
9C01
RES
2C86 RES
FC62
100R
FAN-CTRL2
*
* RES 3C91
100R
iTV
100p
SDA-BL
* RES 3C90
10K
RES 2C85
TACH02
+3V3
FC61
100p
RES 2C84
SCL-BL
9C02-1
9C02-2
9C02-3
9C02-4
1M20
1
2
3
4
5
6
7
8
9
10
11
12
3C97
RES 2C83
TACH01
0R3
+5V
SCL-SET
FAN-CTRL1
**
*
+3V3-STANDBY
Option table for Ambilight
**
Option table for Leading Edge
Items
BlockBuster / Emmy
1M19
Yes
No
1M20
No
Yes
Sundance / Infinity
RESERVED
SPB SSB TV550
2K11 4DDR BR SD
3
2011-03-09
2
2010-12-23
3139 123 6521
19110_048_110415.eps
110415
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 112
10-8 313912365213 SSB Layout
Overview top side
7US2
3UB1
9S93
9S91
3B16
3UD5
3B17
3B07
5UD2
3UD3
2U28
2UD8
2UD7
5UD1
3S1B
9F27
9F28
3S1L
3UD1
2S4D
3S3N
3S2A
3B13
3S3R
3S3T
2UD4
7UD0
3UD2
3S1K
3S1J
3B12
3UD0
2UD1
3B00
3S1C
2UD2
3S3L
3B05
3S6K
5UD0
IF62
3S81
3S3F
3S54
3S50
2S7U
2S8G
2S7N
2S87
9S20
9S18
3S4R
3S59
2S77
2S78
3S84
3S83
6F72
7F70
3FLE
IF89
2FL6
2FL7
1P08
7FL5
2F9D
9E15
9FLK
9FLL
9FLG
1FD3
3E20
2E37
3FL2
2FDD
3FDG
2FDC
2F88
3F64
3F65
1FD2
2E38
2F86
3F75
6FC5
2E67
3ECF
6E53
2E73
3E9C
1P03
1P02
3FC2
1FC6
9FC4
1FC3 1FC4 1FC2
6FC2
6FC1
3FC5
3FC6
2FC6
2FC1
2FC2
9FC5
3FC7
2FC4
2FC3
2FC7
9FC6
2FC5
9FC3
6FC6
6FC8
2FC8
1FC1
1P04
2ECC
1FC5
1N00
5EC2
1P05
6FC3
6FC4
3FC3
IEE3
3FC4
2F81
2ECP
6FC7
2F97
2E77
1E10
3U59
2F60
2ECM
3ECM
3FC1
2EE1
7EC1
3F623F63
2ECN
1E80
9U41
1E07
3U75
3U74
3U53
3U41
9U42
1329
3ECN IE42
2EC1
2EE2
7EE1
1F52
3EC5
9EC3
3U69
7U42
1T01
3ECP
9E57
3E89
IEE6
IEE5
3EE0
9E17
2EE5
2EE0
4E24
4E21
6E51
3EE2
2EE4
3EE3
6E46
IEE4
3EC3
1E44
3U70
3U68
7U43
2EE7
3EE1
2E22
3C95
4E20
2EE6
2C87
2C81
2EE3
5E06
2C90
3C94
6EC1
1E38
1P07
2ECU
6C05
2C86
IE11
1328
2E05
3E27
6E47
IC74
3C79
2C91
1E03 1E04
2F9A
2F99
6FD3
1E08
3FL4
1F51
6FD2
5E01
1E87
1E88
2E62
2E60
3C77
6C03
2C82
5E02
3E28
3E26
2C78
IC75
3E98
3C78
5E08
1M20
1M19
2C80
2E63
2E56
IE10
2F98
2E57
2C93
1E28
3E25 3E22
7EE0
2E66
2E07
3C76
3E40
3C74
6C02
2C77
1E43
6E20
1E42
1E29
3E72
3C75
1E37
3E35
2C76
1E09
3E21
3E68
3ECG
3E34
1E39
IE07
2E35
2E36
6E19
2E54
2G75
2G77
5F72
IE09
4E23
2E27
9F71
2F9B
3E88
9E29
4E22
6E38
3E87
6E40
2E40
3E96
9E13
2E71
9E11
2E72
3E30
7E10
2G76
2E39
1E70
3E33
2G27
2E55
6E06
2E52
3E51
4E01
1E32
3E97
2G24
9E04
4E04
2E53
4E05
3E67
3E70
3E65
3E66
3E69
2E49
2E48
3E64
9E42
9E43
3E71
2F93
2G79
2G78
9FL3
3FL7
3F34
9FLE
2F9C
9FLF
9F00 9F01
IF86
5F73
9F04
3G38
9FLD
5F70
1E85
1E01
9FLC
1FL5
3F78
9F05 9F06
2G28
1E18
1E12
1E02
2G29
1E86
1E54
1E19
1E31
9FLH
9FLJ
1F75
3FLC
9E22
2F92 2F94
2F90 3F71
4E02
4E03
9E24
IF61
2F91
3F72
9E18
1E06 1E71
3E32
7F58
2F58
2S4M
3F59
3F60
BS13
3F58
3S12
1F10
2S41
3S13
9E20
5D05
1P09
2F40
BS10
3S4J 2S7J
2S7E
2S7L
2S7R
2S7P
9S19
9S21
3S4T
3S4P
2S7H
3S4K
2S7K
3S4L
2S7M
3S6H
3S42
7S00
3S44
3S2M
2S2Z
2S2W
2S2S
3S3W
3E17
2S2Y
2S32
4S14
7S08
2S30
IS13
2S34
2S31
2S33
3S00
2S2R
3S6J
3S3M
3S43
3S3G
2S2V
9S06
3S3U
3S3H
DBS8
1S02
2S2T
3S26
2D09
5D02 5D01
2D12 2D11
DS50
2S4G
2D06
5D04
3S52
BS15
3B14
3B04
2B45
2D07
7B03
3S6N
3S80
2S4F
3B15
3S53
2G26
6GA2
6UD0
IUD0
2UD3
3S3S
3B23
3S27
2G25
6GA0
5UD3
2U27
2UD5
3S21
2UD9
3U06
2UD0
3S24
3S23
3S29
3S28
3F09
3F10
3S3Q
3B02
7S00
2S4E
2B44
7B02
3S62
7U05
2UE9
3F11
3F08
9S00
3S3Y
7D10
2G7A
6GA3
6GA1
7GA2
IUD4
IUD2
2UE1
2UD6
7UD1
3UD4
2B46
1C86
1C87
IUD1
3B25
2D23
2D24
2GA4
2UE2
2UE4
2UE0
3B24
2D10
1G35
2UE3
3U07
2D20
1D52
2D08
2D17
1D50
1735 1D38
3GA2
IGA1
7F20
3B08
9S90
9S92
2S4P
3B10
2D19
5D08
2D05
2UE8
3UB0
3UB2
3UB3
7UA4
3UB4
3UB5
7GA1
1G36
IGA3
2UE6
2UB0
2UB4
7UA3
3GA5
IGA2
2G97
5D07
1G51
2C96
7GA0
2G98
7B00
1G37
3GA6
2UB1
3B19
2G96
2C94
3US7
3US4
9US0
7US1
2UB2
3B18
2G99
3C70
2C70
5UM1
IUS5
IUT2
3US3
2UB3
7B01
2U15
5U00
3B11
5U01
3B26
2B47
1G50
IU17
2U16
2U09
6U00
3U24
9GA0
3GA1
IU18
2U11
2C95
5C55
2G16
3G14
3G12
3C83
3G13
1UM0
2C84
3C92
3C82
3C81
3C80
3C91
3C93
2C83
3C90
5C54
5C53
3G11
3US2
2US3
3US5 IUS6
2C85
3US6
3US9
2U56
3U23
IUS4
IU23
1M59
3G10
IUT1
IUS3
7U01 7U04 7U02
IUS9
2U18
2U17
IU15
2U19
5U03
5U02
2U23
2U25
2U24
2U20
7US3
3U56
2U50
2U43
3U44
3U66
2U52
2U72
3U67
2U47
2U48
2U68
2U51
2U54
3U76
3U71
3U42
1C85
1F24 1M71
1M99
3U84
3U81
2U46
2U45
3U45
3U43
2U49
2U58
2U53
2U44
3U64
4U00
4U01
3U65
1M95
1E05
2
SSB Layout Top
2011-03-07
3139 123 6521
19110_001_110307.eps
110309
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 113
Overview bottom side
CXXX
FC96
FC81
FL38
FC67
FC82
FC78
FC71
9FL1
9FL2
FC79
FC99
CU00
FU52
FU53
FU55
FU62
FU76
7UU2
FS2W
FS2Y
3U05
3U27
IU64
IU21
FG1P
FU00
3U02
2U10
7UD2
FB00
2G44
2B34
5G01
IS1J
FE57
IF90
IFLG
C000
FE56
1G03
FG12
FG13
2G43
9G0K
2G94
2G95
2B26
2S17
3B20
2B19
3S6P
2B21
2B14
3D06
3D09
2B11
2B12
2S29
2B08
2B36
2B03
2B02
2B04
2D16
ID29
2B16
2S24
3S20
2S4Q
CD10
2S4R
C001
2B07
2B05
2B06
2S3B
3S72
3S51
2S3J
3S39
2S2H
2S2G
2D01
2D14
5D03
FD06
2D13
2S42
FD02
3S0Z
3S1D
3S49
3S3P
FD05
ID32
FD14
IS1D
IE15
BEC5
5E74
3E77
IU43
6E44
3E53
FD10
ID09
ID31
3S38
FS57
3E9E
2B41
IS12
BEC3
FL36
ID28
2B00
3B03
3E76
FE80
2E14
2E84
6E26
2E80
3E75
2E98
2E15
2E86
5E73
3E74
2E79
IE53
IE55
6E23
FE74
5E76
3E78
2E85
2E12
FE81
3D10
ID07
IE18
ID05
FE23
9E25
9E28
3E79
IE22
3E07
2E04
6E28
6E09
IE49
2D21
IE50
2F96
ID19
2D27
IF80
2F49
FF57
ID37
ID10
FS03
3F79
IF54
ID15
ID30
ID18
2B01
FS52
2E83
IF72
IF52
IFL1
5F71
IF58
3F52
3S36
IS0R
3B28
9E12
IF50
IF79
IF59
FL32
IFL2
2F52
IFLF
2E69
7F52
FF29
FL39
FL30
IS1H
IS1P
7E11
2F73 2F80
2F72 2F82
2F77
2F76 AF73
FF55
3S5E
FS53
9E14
IF53
5F74
2F95
3E9D
FF56
IS11
6E43
FF42
6E48
5F76
7E13 7E12
AF72
2F62
2F70
3F43
3F41
IF16
2F65
3F82
FF41
IS02
7D15
FD09
IS07
IS1Q
FF46
9F25
9F26
2S3A
2S3D
3S32
3S34
2S2J
3S37
3S6L
2S2K
3S05
FE86
IF47
FD08
2D29
ID27
IS03
7S05
3S16 3S17
IS0V
FL37
IS1N
IS06
3S47
3F40
2D28
FD01
FS08
2S3C
3S5B
IS5C
IS20
FS50
ID33
2B09
FD03
IS1S
2S8A
9S24
IS50
2S38
2S16
IS5G
IS2V
IE05
FF48
3S6Q
2S4S
2S5P
2S64
2S60
5S93
2S68
2S3H
3S10
2S3F
IS1B
IS1M
IS4V
IS44
FF45
2D02
ID14
2B40
2S3E
3S09
IS5J
3S08
2S40
2S19
IS2Z
3S5T
2S3K
IS19
3F45
FF49
2B13
2S36
IS5H
3S46
3S2S
IS3E
FS44
2S2L
3S75
3S2L
IS1A
IS4W
2S18
3S1H
IS3D
2S14
3S5V
FS11
2S86
FS49
2S3G
2S76
2S22
3S25
FF44
2S45
2S4Z
2S15
2S50
IS5E
3S5S
IS3F
3S18
2S23
2S53
2S55
IS3B
FD07
ID11
2S46
5S84
2S13
3S2V
9S0E
2S3L
3S11
3S6M
3S19
IS1E
2S3M
IS1K
3F42
IS3L
2S75
2S85
FS02
2S6G
3S76
IS5D
3S1G
2S84
IS1G
2B17
2S6N
2S51
ID12
2B37
3B01
2S10
FS10
IS42
2B15
IS5F
FS45
7S09
IFD4
3D15
2B10
3S0V
2S65
3S22
FS51
FF50
3F44
3S40
3S45
3F53
FS0Z
IS2U
2S6E
2S6D
2S20
2S4U
DS52
IS4Z
9S0D
3S2H
3S55
7S20
2S4K
3S1F
9CH0
IF51
FF04
IF56
3F68
2S3Q
FF47
9S09
IS16
3S2K
3S41
3S1P
IS1L
FF43
IS05
FC95
IF57
3F69
6FD1
3FD1
7F54
7F53
2F53
9FD5
3FD7
3FD2
9FD2
IFD2
3FD3
IFD1
3F67
FF58
3F66
3F54
ID34
2SHW
2S4T
IFD5
7FD1
9FD1
3FD6
IUB6
3FD4
5UA0
2FD1
2S52
2S6B
2S6C
ID35
7D11
3S30
3S33
2S5K
2S43
2S11
2S6A
3S0W
IS01
3B22
2S5G
5S95
2S4V
2S2E
FS64
2S5B
IF55
IFD3
2UB6
3S64
3U13
3U12
2UB7
7UA6
IUD6
2S21
FG32
FG31
2B18
2D03
2S4Y
5S83
3B06
3D01
5S88
2S5H
2S28
5S92
2S5A
2S59
2S6M
2S58
2S6K
2S27
IS10
IUD7
2UB5
2S6H
IS3S
2S5D
IS04
IU26
IUB1
2S6L
2S5C
5S82
3S1U
3S1T
3S1S
3S1R
IUD3
2UB8
3S82
IUB2
7UA7
2S4W
2S5J
5S80
3UB6
IUB5
5S94
2S57
IS3Q
5S89
3S1X
FF05
5S87
FF06
3F07
IS58
5S81
3S1W
FF09
5S90
5S85
3S56
3S69
5S04
3S6V
3S1E
2S56
3S6W
IU27
3UA0
2S62
IS3K
2S5M
2S6P
3S2F
IUB3
3S6A
IS25
2S37
3S57
2S6F
3U25
2S63
IS26
3S5Y
2S39
3S6D
FF07
3S2G
2S25
2S67
3S5Z
IU28
2B20
2S26
3S15
2S61
3S6F
IU29
FG1F
FG1D
2G93
FS01
3S07
2S66
IU30
3G28
1G00
2B22
2S4N
3S1V
3S60
FG1E
2G92
3B27
2B24
3D16
IF87
2B42
9S08
3S61
3S6E
FG1G
IG11
FG30
3S58
3S5W
IS00
3D02
3S6C
7D03
3S6B
9C00
FG1H
3B21
2S89
9C01
3S6G
7UA5
FG1L
6G00
FG1C
2B38
3F19
IF88
IUB4
FG1M
FG1J
FG33
3S06
3F20
IF22
2B28
2B29
9S12
IS09
3U15
FUD3
3UB7
FG1N
FG1K
FG0H
2B25
3S67
2B31
2S12
3S65
9S97
FF08
3B09
2B30
IS08
9S11
9S96
3F22
9S13
2F20
3F12
7S01
9S10
3F21
3F23
IF23
FC86
FS31
FC85
IF08
IF21
2B23
IUB0
3S68
3S66
IF04
2F21
FUA0
FG16
FG11
3F24
7UA0
FUU0
FG14
5G02
FL31
7U06
9UU1 9UU0
2B27
2B32
2U14
2UU2
2B39
2B43
IUA6
2UE7
3U16
FG18
FG15
2B35
IU40
2U71
2B33
IU41
9S94
2UE5
FG1A
FG19
FG17
2U13 2U12
9S95
CUA0
IGE0
IS40
IUD5
FG1B
7UU0
2U29
CU05
3U83
6UD1
3GE3
IUA5
7UD3
FGA3
FGA6
FGA2
FGA4
3GA3
FUA4
FG1Q
3U21
IU19
IU01
3U20
CU02
IU02
3U03
2GA1
IUU2
IU14
IU25
2U05
2U04
IU57
FU03
3GE2
3GE4
2UU0
FU04
IU09
IU61
IU52
7U48
9GE1
IUU4
FG2J
3UU3
7UU1
FU06
FUA3
7GE1
3UU2
2UU1
FU02
3U60
FUU1
3UU1
IUU1
IU12
FU05
IU48
IUU3
7UU3
IUU0
IU07
IUU5
3U19
2U08
3U10
3U18
7U03
IU16
IU11
3U80
7U41
3U26
3U29
FU51
2U02
IU13
3U14
IU10
3U61
FU67
3UU0
2U01
FU73
3U82
FU66
IU56
IU55
IU08
FU72
7UC0
FU61
3U17
IU06
CU03
IUS8
2GA3
5GA1
3G15
IS17
2GA0
FGA0
FU60
IU20
2U22
3U04
3U62
3U63
FU59
7U00
IU49
IU62
FUD2
2GE0
9GE2
FU58
IU24
2UA4
IU50
FU08
IU05
IU22
3U73
FGA1
5GA0
9GA1
IGE1
2GA5
7GE0
9GE0
2U55
IU63
FU09
IU04
2U21
FUS0
FU68
3U09
3U00
IU03
2U07
2U06
2U00
IUS7
2GA6
FU74
FU01
CU04
IUM0
FGA5
3GA4
1U40
7U40
3GE0
FU57
2U57
6U40
IU51
3GE1
2GA2
FU56
FU75
3U01
FU63
FU77
FU07
3U08
FU54
3U22
FU49
FC63
CU01
FC61
3U11
FU50
3U72
FC62
FUM0
3U28
FU48
FC72
2U03
IC78
FC70
FC64
FC83
FC98
FC97
2G18
2G17
2G11
2G12
FC73
FC74
2G15
2G19
FC84
2G10
FC75
FC77
2G14
2G13
FC76
FE73
2E91
2E06
6E03
FE71
2E88
IU45
2G91
IF75
IFL4
AF71
2F66
5F66
2F63
2F64
IF14
2FF3
2FE5
3FG4
7FE0
2FH5
2FE6
FL40
2FH6
5FE7
2FH7
DFE8
IF18
9E16
FE72
FE43
FE31
FC89
FE29
FC88
2E08
2C79
FC91
FC92
FE60
3E90
FE51
9E19
FC93
IE74
IE75
FC65
FEE0
3ECK
IE12
FC94
6E52
2E68
3ECJ
2EC7
FECR
9E58
2ECX
2ECY
IE76
2EC3
FECY
5EC3
3ECL
2ECW
FEC7
IEE1
FE41
9EC2
FC66
IU47
IEE2
2EC0
FE44
FFC7
FFC2
2ECV
5EC0
IU44
IE65
IE66
FEC0
3ECU
IEC6
IEC5
7EC0 7E02
3ECE
FECJ
3E23
FEC2
3ECD
9EC0
FE35
FECA
FECW
FFC8
IEC7
FE36
IEC4
FECE
FEC4
FEC5
FEC1
FECM
3ECA
FECF
3EC1
FECD
FEC6
FECK
FECL
FECP
FECC
FECN
FECG
9FC1
FC90
FE59
FE61
IE77
IE44
IE45
FEC3
2EC2
IE43
3ECH
2ECQ
2FA2
2F59
2F61
FFC4
7FA3
2EC8
FFC1
FFC6
FE48
FECB
FFA2
2EC6
3FBF
9FC2
FFB2
FFC3
FFC5
FFB4
IEE8
5FA4
2FA4
2FF9
FE02
FE03
FF76
3E39
FE30
FECZ
FF74
2E59
5E04
FFAF
FFDB
FFDA
5E03
IC73
IEE7
2FA3
FE28
FE01
FF63
5FA3
2E58
3E29
FE27
3E99
2E09
2FF8
IEE0
FFC9
FE34
FC87
3E95
2FF4
3FE8
3FE9
2FE3
5FE8
IF69
FG2H
FE33
FE32
DFF1
2FG0
2FF2
2FF1
2FG1
FF61
3G2Y
3G2W
FL42
FFB5
FG2G
3G32
3G35
IE39
IF68
2FH4
7FE3
2FH2
FF62
2FF7
FF03
2FH3
FG1Z
FG2F
FG35
IE32
DFF2
5FE9
FG1Y
FG2E
3G37
FG2K
IE06
2FE4
IF49
IF67
FG2L
FG2R
DFE6
IF17
5FE5
FG20
3G2Z
IE31
FE54
IE51
DFE9
2FG6
2FG4
3G36
IE29
2FE8
FF81
FG21
3G30
IE63
IE38
FE49
FE85
IE33
2FG8
2F84 3F76
IE71
DFE7
BFE2
2FG7
9E26
FG34
2FE0
FF82
5FE3
FG24
FG22
3G33
3G34
IE73
IE48
FE42
FG04
5FE0
FF65
IF65
FFB3
FG29
FG25
FG23
IE26
IE64
FE50
2FF0
BFE3
FF66
2FF5
3FG7
3E73
IF48
3E44
IF63
2FG3
FF00
FF64
2FG9
FFB1
FG28
FG2M
3G31
3FG6
5FE4
3FG2
1FE0
2FG2
2FF6
IF66
FL43
FL41
FFB6
9G0G
FG26
IF27
IF64
FL33
3F32
3FE5
5FG0
5FG2
AF70
IFLD
IFLB
FFDC
IF28
3FLD
3FLB
FG27
3FE6
2FH8
3FLG
FG2A
FG2B
ID08
IF82
3FE7
2FL2
IFL3
3D14
ID06
3F77
IF15
IFLA
3FLH
IF76
2F75
2F79
3F80
3F81
FG1R
IF29
3FLF
IFLE
2FLC
IF78
IF12
IF13
FG1S
FG2D
IF11
2FL8
2FL1
2FL3
FG1T
FG1U
FG2C
2D22
2FL4
9F03
9F02
FG1W
FG1V
FG2P
2D26
IF10
2F71
FF01
IF74
2FLB
FG2N
FE58
IF73
7F75
2F85
2FL9
3FLA
2FLD
2FL5
IF77
FF71
2F78
2F74
IF81
FF75
IFLC
2FLA
2
SSB Layout Bottom
2011-03-07
3139 123 6521
19110_002_110307.eps
110307
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 114
10-9 B01 313912365214
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 115
Common Interface
B01A
Common Interface
B01A
CA-CD1n
CA-CD2n
FF05
FF06
3
6
10K
5
10K
3F07-1
1
8
10K
3F07-2
2
7
10K
4
1
CA-MOCLK
CA-MOVAL
CA-MOSTRT
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
CA-RDY
FF08
FF09
CA-VS1n
1X07
REF EMC HOLE
3F07-3
+3V3
3F07-4
3F08-1
8
10K
5
FF07
10K
3F08-3
3
6
10K
3F08-2
2
7
10K
4
3F08-4
RES 1 3F09-1 8
10K
RES 2 3F09-2 7
10K
RES 3 3F09-3 6
10K
RES 4 3F09-4 5
10K
+3V3
IF04
RES 4 3F10-4 5
10K
RES 3 3F10-3 6
10K
RES 2 3F10-2 7
10K
RES 1 3F10-1 8
10K
3F12
10K
2 3F11-2 7
10K
3 3F11-3 6
10K
4 3F11-4 5
10K
8 3F11-1 1
10K
1X04
EMC HOLE
+3V3
IF08
+3V3
1X08
REF EMC HOLE
1X01
REF EMC HOLE
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_002_110628.eps
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 116
Flash
Flash
B01B
12
7F20
NAND04GW3B2DN6F
Φ
37
100n
100n
2F21
2F20
+3V3
VCC
[FLASH]
4G × 16
3F20-1 1
8
3F20-3 3
6
3F21-1 1
8
3F21-3 3
6
100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4
2
7
100R
4
5
100R
2
7
100R
4
5
100R
3F22-2
+3V3
XIO-OEn
XIO-WEn
NAND-WPn
2
7
3F23
3F22-4
4
100R
3F22-3 3
10K
3F22-1 1
5 100R
6
100R
8
100R
16
17
9
8
18
19
7
IF22
3F24
+3V3
NC
2K2
CLE
ALE
CE
RE
WE
WP
R
B
IF23
VSS
13
3F19
10K
NAND-RDY1n
0
1
2
3
IO
4
5
6
7
IF21
NAND-CE1n
NAND-CLE
NAND-ALE
29
30
31
32
41
42
43
44
36
XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48
+3V3
B01B
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-11
3
2011-03-09
2
2010-12-23
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div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 117
USB Hub
USB Hub
B01C
B01C
+3V3
USB-OVR1
3FL2
8
26
IFLA
IFL1
IFL2
9F26
9F25
100K
9FLC
9FLD
100K
3FLE-3
6
9
10
3FLF
9FLF
9FLG
10K
IFL3
9FLK
9FLL
USB2-DM
USB2-DP
10K
USB-OVR1
53
51
5
6
42
41
54
1
2
44
43
52
3FLG
+3V3
3FLH
+3V3
10K
GREEN2
AMBER2
SELFPWR
VBUSPOWER
PWR1
OVR1
RESET
PWR2
OVR2
DD+
SPI_CS
SPI_SCK
SPI_SD
DD1DD1+
DD2DD2+
VIA
RES
NC
1P08
Y
Y
Y
Y
1F24
N
Y
N
Y
3FLG
N
Y
Y
N
3FL2
N
N
Y
Y
3FL4
N
N
Y
Y
3FL7
N
Y
N
Y
3F32
Y
Y
Y
Y
3F34
N
Y
Y
Y
7FL5
CY7C65621
CY7C65621
CY7C65631
9FLE 9FLC/D 9F25/6 9FL2
N
N
N
Y
Y
N
N
N
Y
N
Y
N
N
N
N
Y
2FLB 1n0
2FL3
2FLC 1n0
10n
2FLD
2FLA 1n0
10n
100n
10n
100n
2FL2
2FL5
100n
2FL1
2
3FL4-2
FL32
1
2
3
4
5
6 IFLF
7
100K
USB-16-PBT-B-30-CU1-BRF
37
38
IFLB
3F32
+5V
4
9FLE
31
32
25
48
49
3
IFLC
IFLD
IFLE
3FLA
3FLB
3FLC
+T 0R3
3F34-4
100K
3F34-3
USB2
1P07
+5V-USB1
+5V-USB2
6
FL40
FL41
USB2-DM
USB2-DP
100K
10K
15K
10K
+3V3
+3V3
2
3F34-2
7
1
2
3
4
5
6
100K
USB-16-PBT-B-30-CU1-BRF
1 3F34-1 8
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
100K
+3V3
+5V
RES
RES
RES
RES
1
2
3
4
9FL1-1
9FL1-2
9FL1-3
9FL1-4
8
7
6
5
1
2
3
4
9FL2-1
9FL2-2
9FL2-3
9FL2-4
8
7
6
5
(WIFI)
RES 3FLJ
RES
1F24
+T 0R3
FL38
FL39
FL30
USB-WIFI-DDn
USB-WIFI-DDp
1
2
3
4
5
6
7
502386-0570
GND
HS
4
8
12
16
20
24
28
34
40
47
50
56
1P07
N
N
Y
Y
35
36
29
30
USB1-DM
USB1-DP
100K
9FL3
XOUT
GND
SCENARIO
1x USB
1x USB + WIFI
2x USB
2x USB + WIFI
+3V3
GREEN1
AMBER1
9FLH
9FLJ
+3V3
17
18
13
14
100K
RESET-USBn
USB1-DM
USB1-DP
USB-DM
USB-DP
USB2-DM
USB2-DP
USB-WIFI-DDn
USB-WIFI-DDp
46
7
4 3FLE-4 5
3
1P08
FL43
FL36
FL37
+5V-USB1
FL42
3FLE-2
USB1
6
1 3FL4-1 8
10K
45
100K
2
22
VCC
XIN
3FL7
3FLE-1
+5V-USB2
FL31
1
3
3FL4-3
9FL3
N
N
N
Y
57
+5V
10K
21
3
7
11
15
19
23
27
33
39
55
12p
2FL7
7FL5
CY7C65621-56LTXCT
IFLG
3FLD
FL33
100K
100K
IFL4
+3V3
2FL4
2FL8
3
+T 0R3
4 3FL4-4 5
24M
12p
2FL6
4
2
1
1FL5
2FL9
1u0
100n
+5V
9FLF/G 9FLH/J 9FLK/L
N
N
N
N
Y
N
Y
N
N
N
Y
Y
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 118
SD Card
SD-Card
B01D
3F40
+3V3
22u 16V
+T
2F40
B01D
FF45
+3V3-SD
0R3
+3V3
4
3F41-4
IF47
5
47K
SDIO-DAT3
3
3F41-3
6
SDIO-DAT3
2
3F44-2
SDIO-CMD
FF47
7
100R
3
SDIO-CMD
47K
3F43-3
1P09-1
6
FF48
100R
3F45 RES
SDIO-CLK
SDIO-CLK
10K
1
3F44-1
+3V3-SD
8
FF49
100R
2 3F41-2 7
47K
1 3F41-1 8
1 3F42-1 8
47K
SDIO-DAT0
SDIO-DAT0
SDIO-DAT1
SDIO-DAT1
SDIO-DAT2
SDIO-DAT2
47K
2 3F43-2 7
FF41
100R
1 3F43-1 8
3 3F44-3 6
100R
FF42
3F42-2
FF46
SCDA7A0200
1P09-2
7
SDIO-CDn
SDIO-CDn
FF44
SDIO-WP
SDIO-WP
FF50
47K
3 3F42-3 6
14
16
FF43
100R
2
13
15
1
2
3
4
5
6
7
8
9
10
11
12
SCDA7A0200
47K
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 119
PNX85500 Control
PNX85500 Control
+3V3-STANDBY
B01E
+3V3-STANDBY
Q
IF50
512K
FLASH
5
D
BACKLIGHT-BOOST
7F53 RES
PDTA114EU
PNX-SPI-SDO
IF52
6
C
10K
RES
10K
3F67
Φ
3F66
IF53
1
S
PNX-SPI-CSBn
IF54
3
W
7
HOLD
+5V
PNX-SPI-CLK
PNX-SPI-WPn
+3V3-STANDBY
FF29
VSS
IF55
BOOST-PWM
IF61
47K
2
+3V3
+3V3
3F68 RES
PNX-SPI-SDI
3F52
8
7F52
M25P05-AVMN6
VCC
IF51
+3V3
100n
RES
100p
2F52
2F49
+3V3-STANDBY
10K
B01E
7F54-1 RES
BC847BPN(COL) 6
7F54-2 RES
BC847BPN(COL)
SPI-PROG
IF56
4
IF57
2
1
4
FF04
5
IF62
SDM
3
FF58
1K0
RES
RES
3F69
10K
1u0
2F53
MAIN NVM
+3V3
RES
9CH0
10K
3F54
3F53
DEBUG ONLY
IF58
2F58 RES
SCL-SSB
1
2
3
0
1
2
8
WC
ADR
SDA
100R
SDA-SSB
FF63
SCL
3F63
4
100R
SCL
1
2
3
SDA
5
7
6
5
FF55
3F59
100R
3F60
SCL-UP-MIPS
FF56
SDA-UP-MIPS
100R
4
IF59
10K
3F58
Φ
(8K × 8)
EEPROM
RES
1F52
3F62
FF62
100n
7F58
FF61
FF57
LEVEL
DEBUG / RS232 INTERFACE
TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG
FF65
3F64
FF66
100R
SHIFTED
RES
1F51
FF64
3F65
100R
7
6
1
2
3
4
5
UP
FOR
DEBUG
USE ONLY
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_006_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 120
Tuner
Tuner
B01F
B01F
IF10
1T01
IF11
*
*
15p
2F65 RES
2F73
AF73
820R
*
1p0
*
*
*
220R
IF16
330n
3F82 RES
4
RES 5F76
AGC CONTROL
10n
3F79-4
5
GND1
VAGC
8
4
GND2
10n
IF80
2F70 RES
2F79
2F62
220R
2F72
9F02
IF78
5F74
6
2F82
OUTPUT2
2p2
2F77
INPUT2
*
2F80
3
RES
2F76
1
*
AF72
3F79-1
5F71
IF77
220R
3F81
220R
2
1
IF13
IF-
10n
IF14
2F64
IF15
IF+
10n
* For BR NIM Tuner only
3K3
5F73
3F78
TUN-IF-P
4
470n
3
2F63
2F90
IF86
TUN-IF-N
IF12
15p
10n
1K0
2F92
3F72
BA591
6F72
4K7
9F06
*
3F71
9F05
*
+5V-TUN-PIN
680n
2F66
3F80
IF72
5F66
4K7
5F70
+5V-TUN-PIN
IF74
7
IF76
10n
10n
FF81
FF82
OUTPUT1
9F03
1
VCC
INPUT1
FF01
IF-AGC
RES 2F95
100n
2F93
2F61
2F60
2F59
RES 2F81
IF81
GND
2
2F75
PNX-IF-N
47n
IF-AGC
FF75
TUN-P6
TUN-P7
10n
2F78
*
IF79
2F85
*
9F04
5
4
IF73
*
3F77
100p
100n
4n7
4n7
FF00
TUN-IF-N
TUN-IF-P
IF82
PNX-IF-AGC
RES 2F96
FF76
O1
O2
2F74
X7251M
36M17
100p
AF71
AF70
*
I
ISWI
RES 2F9D
RES 2F9C
RES 2F9B
RES 2F9A
RES 2F99
RES 2F97
RES 2F98
3
FF74
10n
12
1
2
6p8
6p8
6p8
6p8
6p8
6p8
6p8
1F75
TUN-P1
+5V-TUN-PIN
7F75
UPC3221GV-E1
IF75
PNX-IF-P
2F71
9F01
9F00
13
NC
IF_OUT2
IF_OUT1
11
4MHZ_REF
14
10
B+_TUN
8
9
I2C_SDA
I2C_SCL
7
TUN
5
RF_AGC
4
B+_LNA
3
RF_IO
2
1
16
I2C_ADR
TUNER
15
6
*
FF71
2F91 RES
ATB2012
10n
IF89
47R
2F86
3F75
15p
47R
IF87
SCL-TUNER
IF88
SDA-TUNER
IF90
SELECT-SAW
2F94
TUN-P6
TUN-P7
7F70
PDTC114EU
10n
3F76
15p
RES
2F84
* For EU Hybrid Tuner Only
9F71
5F72 RES
1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74
30R
Component
Europe
Brazil
FA23X7
TH26X3
RES
4u7
5p6
10p
Used
RES
Used
RES
Used
RES
Used
RES
Used
RES
RES
1p0
RES
1p0
12p
15p
12p
15p
18p
22p
560n
680n
680n
820n
22u
Item No.
+5V-TUN-PIN
+5V-TUN
2F88
* Remarks
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_007_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 121
Toshiba Supply
Toshiba supply
B01G
+1V2-BRA-DR1
+3V3
5FA4
30R
10u
2
2FA4
OUT
30R
IN
100n
3
5FA3
7FA3
LD1117DT12
2FA3
+1V2-BRA-VDDC
FFAF
1
100n
COM
2FA2
B01G
FFA2
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2010-03-09
2
2010-12-23
19112_008_110628.eps
110628
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 122
HDMI
HDMI
B01H
HDMI CONNECTOR SIDE
1P05
DRX2+
DIN-5V
DRX2DRX1+
DRX1DRX0+
DRX0DRXC+
DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22
DRX-DDC-SCL
DRX-DDC-SDA
DRX-DDC-SCL
DRX-DDC-SDA
47K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23
1 3FBF-1 8
B01H
2 3FBF-2 7
DIN-5V
47K
DIN-5V
DRX-HOTPLUG
FFB6
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_009_110628.eps
110628
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 123
VGA
VGA
B01I
FFC1
CDS4C12GTA
12V
RES 6FC1
1FC1
100p
RES 2FC1
3FC5
CDS4C12GTA
12V
RES 6FC2
1FC2
100p
G-VGA
18R
1FC3
RES 6FC3
FFC4
100p
RES 2FC3
FFC3
CDS4C12GTA
12V
3FC7
9FC5
H-SYNC-VGA
9FC6
V-SYNC-VGA
4K7
3FC3
CDS4C12GTA
12V
RES 6FC4
1FC4
FFC6
1216-02D-15L-2EC
B-VGA
18R
FFC5
47p
CDS4C12GTA
12V
RES 6FC6
47p
2FC6
10K
RES
3FC2
FFC9
RES 6FC7
47p
2FC7
10K
4K7
3FC4
CDS4C12GTA
12V
RES 6FC5
1FC5
FFC8
CDS4C12GTA
12V
RES
3FC1
47p
2FC5
FFC7
9FC1
VGA-SDA-EDID-HDMI
9FC2
VGA-SDA-EDID
RES
9FC3
VGA-SCL-EDID-HDMI
9FC4
RES
VGA-SCL-EDID
RES 6FC8
1FC6
47p
+5V-VGA
CDS4C12GTA
12V
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2FC4
VGA
CONNECTOR
3FC6
RES 2FC2
1E05
R-VGA
18R
FFC2
2FC8
B01I
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_010_110628.eps
110628
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 124
Temp sensor & headphone
Temp sensor & headphone
B01J
SCL
A2
1K0
3FD2
9FD2 RES
9FD1 RES
100n
IFD3
IFD5
5
RES
A1
6
9FD5
+VS
SDA
IFD1
7
A0
1K0
2
8
2FD1
1K0
IFD4
OS
4
100R
100R
1
1K0
3FD7
SCL-SSB
3FD4
3
3FD6
SDA-SSB
IFD2
7FD1
LM75BDP
GND
3FD3
LTST-C190KGKT
RES
RES
3FD1
+3V3
6FD1
RES
1329
5
4
1
2
3
502382-0370
1328
2MSJ-035-69A-B-RF-PBT-BRF
FFDA
AMP1
3
22n
FFDB
22n
2FDD
CDS4C12GTA
12V
2FDC
RES
6FD3
CDS4C12GTA
12V
1FD3
6FD2
1FD2
RES
1
1K0
1K0
3FDG-1
3FDG-2
7
8
AMP2
2
B01J
1
FFDC
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_011_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 125
Tuner Brazil
Tuner Brazil
B01K
B01K
5FE0
IF63
IF64
+2V5-BRA
+1V2-BRA-VDDC
+3V3-BRA-FLT
1u0
100n
2FF1
100n
2FF0
100n
2FE5
100n
2FE4
2FE3
1u0
2FE0
30R
AGND
5FE3
IF66
IF65
+3V3-BRA-FLT
5FE4
+3V3-BRA
30R
1u0
100n
2FF6
100n
2FF5
100n
2FF4
100n
2FF3
2FF2
1u0
2FE6
30R
AGND
5FE5
IF68
IF67
+1V2-BRA-DR1
IF48
5FE7
+3V3-BRA
+3V3
1u0
100n
2FF9
100n
2FF8
2FF7
1u0
2FE8
30R
30R
5FE8
IF69
+2V5-BRA
7FE3
LD3985M25
5FE9
1
+5V
30R
18p
4 2
2FG3
18p
2FG2
25M4
1u0
3
100n
2FG1
1
2FG0
30R
1FE0
3
IN
OUT
INH
BP
FF03
5
+2V5-BRA
4
10n
2FG6
2FG7
AGND
2FG9
100n
2FG8
10n
100n
IF17
IF18
30
29
BFE2
28
27
BFE3
100n
2FH6
100n
24
25
2FH7
100n
26
AGND
39
AGND
0
XSEL
1
FIL
PBVAL
RERR
RLOCK
P
ADI_AI
N
RSEORF
SBYTE
P
ADQ_AI
N
SLOCK
P
AD_VREF
N
SRCK
AD_VREF
SRDT
DTCLK
STSFLG1
DTMB
AGCCNTI
21
58
53
54
55
3FG6-4
4
5
33R
TS-BR-VALID
1
9F27-1
8
*
TS-FE-VALID
3FG6-3
3
6
33R
TS-BR-SOP
2
9F27-2
7
*
TS-FE-SOP
*
TS-FE-CLOCK
*
TS-FE-DATA
DFE9
5FG0
3FG7
60
3FG6-2
3FE8
100R
3FE9
IF49
100R
45
46
SCL
SDA
AGND
PLLVSS
SCL-SSB
SDA-SSB
SLADRS
CKI
TN
VSS
0
1
SCL
SDA
33R
2
7
9F28
TS-BR-CLOCK
33R TS-BR-DATA
4
9F27-4
5
30R
5FG2
DFF1
30R
9
3FE5
18K
10
51
1u0
DFE8
DFF2
IF28
IF-AGC
AGND
42
6
5
12
14
3FG2-1
RESET-SYSTEMn
10K
3FG2-2
10K
3FG4-2
4K7
3FG4-1
4K7
+3V3-BRA-FLT
4
15
33
37
44
47
50
57
62
11
SYRSTN
AGCI
17
7
AD_DVSS
10K IF29
STSFLG0
0
TSMD
1
AD_AVSS
3FE7
AGCCNTR
S_INFO
31
1
41
10K
23
8
3FE6
10n
DFE7
IF27
40
+3V3-BRA-FLT
2
DFE6
61
38
1u0
AGND
1n5
59
52
2FH4
* To be drawn near PNX85500
2FH3
2FH5
2FH2
43
DR2VDD
34
48
VDDS
DR1VDD
16
36
56
63
13
35
49
64
Φ
10n
2FG4
IF+
IF-
O
VDDC
2FH8
3
2
X
PLLVDD
18
I
AD_AVDD
19
32
AGND
22
AGND
AD_DVDD
AGND
20
COM
7FE0
TC90517FG
AGND
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_012_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 126
10-10 B02 313912365214
NANDflash - conditional access
PNX85500: NANDflash - conditional access
IS25
00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15
XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO
B22
OE_
C22
WE_
XIO-OEn
XIO-WEn
CLK_BURST
XIO-D10
INPACK
3S15
10K
+3V3
B21
E21
CE1_
D21
CE2_
A20
NAND RDY2
F21
RDY1
A21
WP_
IS26
INPACK
NAND-CE1n
NAND-RDY1n
NAND-WPn
9S08
10K
RES
D22
ALE
C21
NAND
CLE
J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23
D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24
00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15
3S1V
FLASH
10K
3S1W
7S00-5
PNX85500
NAND-ALE
NAND-CLE
B02A
+3V3
IS00
7S00-11
PNX85500
P21
P22
P23
P24
P25
P26
N21
N22
J22
K25
K26
N23
CA-MOCLK
L25
N24
N25
CA-MOSTRT
L22
CA-MOVAL
L23
J21
CA-RDY
L24
L26
J23
J24
VIDEO_STREAM
0
1
2
3
MDI
4
5
6
7
0
1
2
3
MDO
4
5
6
7
10K
+3V3
3S1X
B02A
N26
M21
M22
M23
M24
M25
M26
L21
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
ADD_EN
DATA_DIR
VS
K23
1
K24
2
CD
K21
1
K22
2
DATA_EN
I
MCLK
O
9S00
CA-VS1n
CA-MOCLK
CA-CD1n
CA-CD2n
CA
+3V3
MISTRT
MIVAL
TS-FE-DATA
3S1R
MOSTRT
TS-FE-CLOCK
3S1S
MOVAL
TS-FE-VALID
3S1T
OOB_EN
TS-FE-SOP
3S1U RES
560R
560R
RES
560R
560R
RDY
RST
VCCEN
VPPEN
T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP
TS-FE-DATA
TS-FE-DATA
3S23
TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK
3S24
TS-FE-VALID
3S28
TS-FE-SOP
470R
3S29 RES
TS-FE-ERR
470R
470R
RES 470R
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
4
2011-05-10
3
2011-03-09
2
2010-12-23
19112_013_110628.eps
110628
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 127
SDRAM
PNX85500: SDRAM
B02B
F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5
N
P
DQS0
N
P
DQS1
N
P
DQS2
N
P
DQS3
N
P
CASB
CKE
CSB
ODT
PCAL
RASB
WEB
1
VREF
2
N5
N4
3S30
10R
DDR2-CLK_N
DDR2-CLK_P
3S33
10R
E2
E3
DDR2-DQS0_N
DDR2-DQS0_P
D3
D4
DDR2-DQS1_N
DDR2-DQS1_P
R1
R2
DDR2-DQS2_N
DDR2-DQS2_P
T3
T4
DDR2-DQS3_N
DDR2-DQS3_P
K3
K4
L5
M4
M1
M5
H3
DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE
A2
V1
DDR2-CKE
3S6Q
10K
DDR2-ODT
3S6P
10K
RES
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
3S0V
180R 1%
3S07
3S22
180R 1%
DDR2-VREF-CTRL2
CLK
2S24
FS01
DDR2-VREF-CTRL3
100u 2.0V
FS02
2S12
180R 1%
3S06
3S20
180R 1%
+1V8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
M0
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14
IS42
261R
DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29
0
1
DM
2
3
J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5
1%
D1
D5
R3
T5
0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14
100p
DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3
MEMORY
0
1 BA
2
100n
2S25
DDR2-BA2
H1
H2
G1
DDR2-BA0
DDR2-BA1
100n
2S17
7S00-8
PNX85500
100p
2S20
B02B
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 128
Digital video in
PNX85500: Digital video in
B02C
7S00-6
PNX85500
T25
T26
HDMIA-RX1+
HDMIA-RX1-
U25
P
U26
RX1_A
N
P
RX0_A
N
HDMIA-RX0+
HDMIA-RX0-
Y26
SCL
Y25
DDC_A
SDA
V25
P
V26
T24
RX2_A
N
HOT_PLUG_A
HDMIA-RXC+
HDMIA-RXC-
W25
P
W26
RXC_A
N
DDCA-SCL
DDCA-SDA
IS10
IS01
3S0W
W24
RREF
12K
10u
+3V3
HDMI_DV
HDMIA-RX2+
HDMIA-RX2-
RES
2S2E
B02C
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 129
Audio
B02D
PNX85500: Audio
B02D
3S0Z
+24V-AUDIO-POWER
+2V5-AUDIO
3S53-1
4R7
100R
220n
2S3J
2S2S
10u RES
1u0 RES
2S34
2
100u 4V
1u0
2S41
4R7
2S42
10K
7
8
4
IS1S
3S3G-4
100n
DBS8
AE5
10
4
7S05-3
LM324 8
3S39
-AUDIO-R
100R
11
ADAC(3)
33R
5
ADAC(4)
3
3S36-3
10K
6
5
10K
3S3H
ADAC(5)
33R
3S3U
3S36-4
2S2H
4
47p
ADAC(6)
+24V-AUDIO-VDD
33R
SPDIF_OUT
2S3D
AF5
56R
1
33R
AE1
1
AF2
2
VREF_AADC
AE3
I2S_OUT_SD 3
AF3
AC8
VCOM_AADC
4
3S3F
3S36-1
2S2G
9
3S3G-2
2
7
AD8
IS1A
IS03
ADAC(2)
SPDIF_IN1
1n0
IS1B
1u0
AD7
AE7
AF7
AD6
AE6
AF6
AD4
OSCLK
AD1
SCK
AD2
WS
I2S_OUT
AB9
POS
VR_AADC
AB8
NEG
ADAC(2)
33R
1n0
2S38
2S2L
AF8
L
AE8
AIN5
R
6
1n0
2S39
3S10
100R
3S3G-3
1n0
2S3A
1u0
IS07
3
ADAC(5)
4
7S05-1
LM324
1
AUDIO-OUT-L
2
11
3S37
3S6L
10K
22K
2S2K
+3V3
47p
+3V3-ARC
+24V-AUDIO-VDD
3S11
IS1L
1R0
100n
5
ADAC(6)
4
IS06
7S05-2
LM324 7
AUDIO-OUT-R
6
3S6N
14
&
3
2
1 3S18-1 8
IS1G
SPDIF-OUT
220R
RES
100n
2
+3V3
3S32
10K
22K
2S2J
7S09-3
74LVC00APW
9
&
6
14
14
+3V3-ARC
&
5
8
10
2S3L
180R
100n
3S6M
IS1K
2S3M
IS44
eHDMI+
100n
3S25
7
+3V3
14
+3V3-ARC
7S09-4
74LVC00APW
12
&
11
+3V3
13
7
SEL-HDMI-ARC
IS1E
3S34
47p
+3V3-ARC
7S09-2
74LVC00APW
4
11
SPDIF-OPT
47R
7
+3V3
RES
2S3K
7
7S09-1
74LVC00APW
1
IS1D
RES
3S18-2
SPDIF-OUT-PNX
7
SPDIF-OUT-PNX
68R
IS19
3S36-2
ADAC(1)
3
AC6
P
AB6
N
1
2
3
ADAC
4
5
6
AD9
L
AIN4
AC9
R
2S32
33R
1n0
2S3B
7
10K
1 3S3G-1 8
IS1N
1u0
1n0
2S3C
3S17-2
ADACR
AE9
L
AIN3
AF9
R
7
10u
2S3G
22K
AD10
L
AIN2
AC10
R
1u0
IS1Q
3S13-2
+AUDIO-L
47p
2S36
AUDIO
AE10
AC7
L
P
AIN1
ADACL
AF10
AB7
R
N
2S33
8
100n
2S3H
2
3S38
100R
+24V-AUDIO-VDD
6
2S30
8
10K
2
7S05-4
LM324 14
13
11
220R
6
10K
3S17-1
10u
2S3E
AUDIO-IN4-R
22K
2S3F
1
1
IS02
7S00-2
PNX85500
1u0
IS1P
4
12
ADAC(1)
3
2S31
22K
3S13-1
+2V5
10K
RES
3S18-3
5
10K
1u0
6
AUDIO-IN4-L
3S51
1u0
2S3Q
3
4S14
2
2S2Y
3S17-4
3
3S17-3
3
1u0
IS0V
5
3S13-3
INH
IS13
IS1M
10K
AUDIO-IN3-R
22K
4
IS0R
BP
FS03
1
2S2Z
10K
3S13-4
IN
COM
2S2T
100R
6
3S16-4 5
4
10K
OUT
4
1u0
3S16-3 3
4
5
IS12
2S2V
22K
AUDIO-IN3-L
FS08
3S53-4
7
10K
7
100R
220R
2
3S16-2
1u0
3S19
AUDIO-IN1-R
IS1J
2 3S12-2
100R
3S53-3
100n
22K
2S2W
2S2R
8
10u
1 3S16-1 8
10K
IS1H
3S12-1
7S08
LD3985M25
9S06
RES
1
AUDIO-IN1-L
+24V-AUDIO-VDD
+3V3
3S53-2
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 130
MIPS
B02E
PNX85500: MIPS
B02E
+3V3
7S00-3
PNX85500
CONTROL
+3V3
+3V3
3S80
3S81
10K
RES 3S21
+3V3
10K
3S62
10K
10K
FS10 TXD2-MIPS
FS11 RXD2-MIPS
IS04
GPIO6
PNX-SPI-CS-BLn
+3V3
9S09
GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW
3S55
SELECT-SAW
5K6 1%
+3V3
FS64
B25
SDA
A24
SCL
TRSTN
TMS
TCK
TDO
TDI
RESET_SYS
BL_PWM
10K
CLK_54_OUT
3S83
+3V3
RXD1-MIPS
3S60
B24
SDA
4
A23
SCL
R26
DN
R25
USB
IS4Z R24 DP
RREF
USB-DM
USB-DP
10K
3S64
3
1
100R
1 3S5Y 2
100R
1
100R
1
100R
SDA-UP-MIPS
SCL-UP-MIPS
2 3S5W
SDA-SET
SCL-SET
SDA-SET
SCL-SET
3S6C
4K7
3S5Z
SDA-SSB
SCL-SSB
SDA-SSB
SCL-SSB
3S6E
2K2
3S61
SDA-TUNER
SCL-TUNER
2
2
1
100R
2
AA25
AA24
AA23
AB26
AB25
EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500
3S00
AE4
RES
1F10
3S69
2 3S57
SDA-UP-MIPS
SCL-UP-MIPS
3S6A
SDA-TUNER
SCL-TUNER
4K7
3S6G
4K7
3S6B
4K7
3S6D
2K2
3S6F
2K2
FS44
EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500
FS49
FS50
FS51
FS52
EJTAG-DETECTn
FS53
10 9
1
2
3
4
5
6
7
8
FOR FACTORY
USE ONLY
2K2
3S6K
EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500
1
10K
8 3S6H-1
10K
3
6 3S6H-3
2
10K
10K
FS57
+3V3-STANDBY
+3V3
BM08B-SRSS-TBT
7 3S6H-2
5 3S6H-4
4
10K
RESET-SYSTEMn
33R
AD5
BACKLIGHT-PWM
AC5
10K
BOOST-PWM
+3V3
IS17
1
100R
3S58
1
2
100R
B26
SDA
2
A25
SCL
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11
2
3S27
3D-LR
DS52
10K
3S82
Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23
3S56
10K
+3V3
BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS
3S6J
10K
3S40
1
100R
C25
SDA
C26
SCL
3S26
1
BOOTMODE
RES 10K
IS05
3S45
+3V3
10K
+3V3
3S72
+3V3
IS40
PXCLK54
47R
RES
+3V3
2S89
100n
+3V3
3
TXD1-MIPS
10K
7S01
PCA9540B
VDD
SCL-SET
1
SCL
SDA-SET
2
SDA
INP
FIL
I2 C
-BUS
CTRL
SC0
5
SCL-DISP
SC1
8
SCL-BL
SD0
4
SDA-DISP
SD1
7
SDA-BL
SCL-DISP
SCL-BL
SDA-DISP
SDA-BL
2
3S65
1
4K7
1
4K7
3S67
2
1
4K7
3S68
2
1
4K7
2
3S66
VSS
6
3S84
+3V3
FS31
9S10
IS08
SCL-SET
SDA-SET
IS09
SCL-BL
9S11
FS2W
SCL-DISP
9S12
FS2Y
SDA-DISP
9S13
SDA-BL
7S00-4
PNX85500
ETHERNET
ETH-RXCLK
AA3
ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)
Y5
0
Y6
1
AB4
RXD ETH
2
AC1
3
ETH-RXDV
ETH-RXER
SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
IS50
RXCLK
TXCLK
0
1
AC2
TXD
2
RXDV
Y4
RXER
3
ETH
TXEN
W2
CC_DAT3
TXER
W1
COL
CLK
W6
CMD
CRS
W5
0
MDC
W4
SDIO
1 DAT
MDIO
W3
2
U6
SDCD
V6
SDWP
SPB SSB TV550
2K11 4DDR BR SD
AA2
ETH-TXCLK
AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1
ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO
3139 123 6521
4
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 131
Video out - LVDS
B02F
PNX85500: Video out - LVDS
B02F
7S00-7
PNX85500
PX1APX1A+
A7
B7
PX1BPX1B+
C8
B8
PX1CLKPX1CLK+
9S90
9S91
N
A
P
LVDS
N
B
P
C10
N
CLK
B10
P
A
N
P
B
N
P
CLK
LOUT1 LOUT3
D7
E7
PX3APX3A+
E8
D8
PX3BPX3B+
E10
N
D10
P
9S94
9S95
PX3CLKPX3CLK+
C
N
P
D9
E9
PX3CPX3C+
A11
N
D
B11
P
D
D11
N
E11
P
PX3DPX3D+
PX1EPX1E+
C12
N
E
B12
P
E
E12
N
D12
P
PX3EPX3E+
PX2APX2A+
A14
N
A
B14
P
A
D14
N
E14
P
PX4APX4A+
PX2BPX2B+
C15
N
B
B15
P
B
E15
N
D15
P
PX4BPX4B+
CLK
E17
N
D17
P
C
D16
N
E16
P
PX4CPX4C+
D
D18
N
E18
P
PX4DPX4D+
E
E19
N
D19
P
PX4EPX4E+
PX1CPX1C+
A9
B9
PX1DPX1D+
PX2CLKPX2CLK+
PX2CPX2C+
PX2DPX2D+
PX2EPX2E+
9S92
9S93
N
C
P
C17
N
CLK
B17
P
A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P
LOUT2 LOUT4
9S96
9S97
PX4CLKPX4CLK+
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_018_110628.eps
110628
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 132
Standby controller
PNX85500: Standby controller
B02G
POL
+1V1
B02G
2S13
100n
1u0
2S10
30R
RES
5S04
IS3B
10K
+3V3-STANDBY
3S1H
10K
3S1G
RXD-UP
TXD-UP
10K
3S2A
RXD-UP
TXD-UP
DETECT2
AE21
0
AF21
1
AA22
2
AB22
P3
3
AC22
4
AD22
5
RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS
AD23
0
AE26
1
AE25
P5
2
AE24
3
DETECT2
10K
RES
3S1K
10K
RES
RESET-SYSTEMn
3S1J
100K
RES
KEYBOARD
2S4E
100n
3S1L
10K
SPI-PROG
SPI-PROG
PNX-SPI-WPn
AF22
4
AE22
P6
5
AF26
AC17
EA
ALE
PSEN
MC
EA
AB23
AC23
SDA
AC24
SCL
AD26
0
PWM AC25
1
PSEN
100R
3S2G
3S2F
100R
100R
3S2K
3S2H
100R
AE23
SDO
AF25
SDI
AF24
SPI
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
AF18
P0
4
AA19
5
AB19
6
AC19
7
ALE
ALE
AC26
IS3F
3S44
IS3E
10K
3S43
IS3D
10K 3S42
10K
EA
PSEN
SDA-UP-MIPS
SCL-UP-MIPS
RES
SDA-UP-MIPS
SCL-UP-MIPS
3S6V
4K7
RES
LED1
LED1
LED2
IS2V
CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP
RES
3S41
10K
LED2
10K
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn
IS2Z
3S6W
4K7
3S1P
RES
10K
RES 3S3Y
10K
CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP
10K
3S2L
3S2S
RES
3S3W
4K7
RES
10K
RES
10K
10K
3S46
+3V3-STANDBY
3S47
3S2M
RES
3S49
4K7
+3V3-STANDBY
+3V3-STANDBY
7S20
NCP303LSN28
2
FS45
1
IS2U
5
INP
OUTP
CD
1K0
10K
3S3T
STANDBY
1 3S2V 2
10K
RES 3S3S
AC20
0
AD20
1
AE20
2
AF20
3
AA21
P2
4
AB21
5
AC21
6
AD21
7
RESET-STBYn
FS0Z
RESET-STBYn
1
NC GND
3
3S3P
LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n
AA26
AB24
4
10K
LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n
RESET_IN
100n
3S3M
RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES
XTAL_OUT
+3V3-STANDBY
10p
AF17
2S4K
10K
1
AE17
10p
2S4F
9S0E
3S3L
RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM
2
4
RES
+3V3-STANDBY
RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM
7S00-9
PNX85500
XTAL_IN
2S4G
3
1
9S0D
3S1E
10K
10K
3S1D
27K
DS50
VDD_XTAL
RES
10K
RES
3S1F
AD17
3S1C
AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7
VDDA_ADC2V5
2S4D
1n0
3S1B
VSS_XTAL
+3V3-STANDBY
VDDA_1V1_DCS
AA17
IS20
54M
100n
1S02
9S24
1u0
2S11
RES
2S37
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2010-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 133
Power
PNX85500: Power
B02H
5S80
IS3Q
1
100n
2S5A
RES 10u
2
+1V1
2S6A
B02H
30R
5S81
2S5B
RES 10u
1
100n
2S6B
2
+2V5
30R
5S82
IS3S
100n
100n
2S68
+3V3
VDD_3V3_SBY
2S5D
2S4M
100n
1
10u
2S4P
100n
2S4N
VSSA_USB
VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB
100n
2S4Y
10u
2S50
100n
2S4Z
6.3V
10u
100n
10u
+1V2
30R
c000
SENSE+1V2
Y17
D13
POL
T20
Y13
+2V5-AUDIO
Y10
100n
VDDA_2V5_USB
30R
R21
R20
100n
2S45
+2V5-AUDIO
5S87
+2V5
1u0
2S56
100n
2S55
30R
5S88
30R
10u
100n
2S57
2S5M
+2V5-LVDS
10u
100n
2S58
100n
2S6K
2
+2V5
30R
1
1
2S6H
2
5S89
5S90
+2V5
10u
100n
100n
2S53
2S4T
30R
2SHW
5S92
+3V3
1u0
100n
2S59
2
100n
2S6L
2
IS58
2S6M
30R
1
4
2011-05-10
1
VDD_1V1_DDR
VSSA_1V1_LVDS_PLL
VDDA_2V5_LVDS_BG
AA7
+2V5
30R
5S84
AA9
2S46
VDDA_2V5_DCS
5S95
Y12
RES 1u0
2S4W
+1V1
IS3L
2S52
VDDA_2V5_ADAC
5S83
B13
2S51
VDDA_2V5_AADC
2S6P
100n
1
100n
Y19
Y18
AA15
Y15
VDDA_1V2
AA13
VDDA_2V5
30R
+3V3-STANDBY
IS3K
VDDA_1V1_LVDS_PLL
+3V3
2
2
100n
2S6C
100n
2S6N
1
2
W20
P20
M20
K20
V7
Y8
100n
1 2S6G 2
5S85
10u
2S4U
VDD_1V1
C7
C9
C11
C14
C16
C18
2S4V
VDD_3V3
+2V5-LVDS
N6
N7
2S6F
VDD_2V5_LVDS
U22
1
VDD_2V5
220u 6.3V
2
100n
2S6E 2
U20
U21
2S6D
HDMI_VDDA_2V5
+2V5
30R
1
HDMI_VDDA_1V1
V20
V21
HDMI_VDDA_3V3_TERM
VSSA_2V5_LVDS_BG
1u0
2S21
100n
2
1
2S5P
VDD
A13
2S29
220u 2.5V
J7
30R
VDD_1V8
C13
100u
2S23
5
100n
5
100n
4
100n
2S5J-4
7
2
1
5S94
+1V1
10u
RES
VSS
2S4S
VSS
VSS
M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20
AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9
U24
V24 HDMI_AGND
3
4
6
100n
2S5H-3
2
100n
2S5J-2
100n
2S5J-1
8
6
100n
2S5J-3
3
3
100n
2S5H-4
8
100n
2S5H-2
100n
2S5H-1
1
6
5
100n
2S5G-4
5
6
7
AA16
AA8
Y11
Y14
Y16
Y9
VSS
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6
A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12
100n
2S5K-4
4
100n
2S5K-3
100n
2S5K-2
2
1
2S5K-1
8
4
3
100n
2S5G-3
7
2
100n
2S5G-2
2S5G-1
1
22u
22u
2S4R
100n
2S4Q
100n
2S27
2S28
100n
2S43
8
7
+1V1
30R
5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7
7S00-10
PNX85500
VSSA
RES 10u
c001
SENSE+1V1
7S00-12
PNX85500
100n
2S5C
2
100n
2S67
100n
2S66
100n
2S65
100n
2S64
100n
2S63
100n
2S62
100n
2S61
100u
2S60
2S26
+1V8
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
3
2011-03-09
2
2010-12-23
19112_020_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 134
Analog video
PNX85500: Analog video
B02I
2S87
AV1-CVBS
2S8A
Y-SVHS
47R
3S5B
22n
56R
Connectivity
3S59
47R
22n
3S05
B02I
2S7J
AV1-R
C-SVHS
2S22
3S4J
56R
22n
22n
EU: SCART1
CVBS-MON-OUT1
22n
560R
3S5E
2S7K
AV1-B
56R
-
3S4L
AP:
3S08
560R
47p
2S7H
2S40
IS4V
22n
8K2
IS4W
3S09
56R
3S4K
AV1-G
2S7M
YPBPR1-SYNCIN1
10n
2S7L
56R
3S4P
AV3-Y
22n
2S7N
AP:
56R
YPBPR1
YPBPR1
3S4R
AV3-PR
EU:
22n
7S00-1
PNX85500
ANALOG_VIDEO
2S7P
2S8G
AV2-CVBS
*
9S18
22n
AB14
AF14
AE14
AC14
AD14
2S7R
AV4-Y
SCART2
YPBPR2
22n
9S19
EU:
AP:
AF15
AE15
AC15
AD15
AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25
P
SCL VGA_EDID
TUNER N
SDA
AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12
IS5E
3S5S
10K
IS5D
IS5F
IS5G
IS5H
IS5J
3S75
BS15
PNX-IF-AGC
10K
BS10
IS11
3S76
10n
2S76
AA14
PNX-RF-AGC
47K
9S20
22n
2S14
BS13
AGND
AV4-PR
2S15
22n
AD11
AC11
+CVBS
2S7U
2S16
22n
22n
22n
IS5C
2S18
22n
AC12
AF13
2S19
CVBS_Y1 ATV_CVBS_Y3
C3
R
B AV1
CVBS_Y7
G
C7
SYNCIN1
CVBS1_OUT
Y_G1
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CURREF
CVBS_Y2
SYNCIN2
1
Y_G2
2
PR_R_C2
3
PB_B2
REF
4
5
R
6
G VGA
B
IF_AGC
HSYNC_IN
RF_AGC
IN
VSYNC
OUT
10n
AB15
AC13
AD13
AE13
22n
2S75
56R
3S4T
AV3-PB
2S77
PNX-IF-P
10n
2S7E
AV4-PB
9S21
22n
2S78
PNX-IF-N
10n
2S84
56R
3S50
R-VGA
22n
2S85
56R
3S52
G-VGA
22n
2S86
7
100R
100R
3S5V-2
2
4
3S5V-4
5
7
5
4
8
100R
100R
V-SYNC-VGA
3 3S5T-3 6
3S5T-2
1
2
3S5T-1
H-SYNC-VGA
100R
AP: VGA
22n
3S5T-4
56R
EU: VGA
3S54
B-VGA
100R
VGA-SCL-EDID
VGA-SDA-EDID
RES
RES
3
1
3S5V-3
100R
3S5V-1
* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ
6
8
100R
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_021_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 135
10-11 B03 313912365214
Audio
Audio
B03A
+AVCC
7D03-1
BC847BS(COL)
+24V-AUDIO-POWER
6
3D09
+24V-AUDIO-POWER
FD14
1
B03A
220R
3
6
3D02-3
3
5
7D15-2
BC847BS(COL)
4
4K7
ID19
ID18
6
2D16
2D17
ID29
L
ID30
1u0
AUDIO-MUTE-UP
2D26
RES
1
2D22
220n
3D14-1
220n
8
7
3D14-2
22K
2
3
3D14-3
22K
6
5
3D14-4
22K
22K
7D10-1
TPA3123D2PWP
1
3
R
PVCC
BSR
CLASS-D
AUDIO AMP
IN
5
R
OUT
L
0
GAIN
1
BSL
16
ID32
2D10
ID06
22u
22
21
5D05
5D02
ID10
220n
15
5D01
ID09
ID31
2D09
22u
ID05
2D12
220R
ID08
35V 220u
5D04
ID07
2D11
220R
RIGHT-SPEAKER
LEFT-SPEAKER
35V 220u
220n
11
7
4
2
1u0
Φ
R
18
17
GND-AUDIO
L
AVCC
47n
4K7
1u0
GND-AUDIO
10
12
2D23
ID15
19
20
2D29
3D02-1
1
8
FD03
220n
4
GND-AUDIO
+AUDIO-L
2D08
4
7D15-1
BC847BS(COL)
1
220u 35V
2
4K7
ID28
2D19
7 3D02-2 2
47n
ID27
2D07
FD08
3D02-4
A-PLOP
6
4K7
1u0
220u 35V
2D24
ID14
2D20
2D28
5
FD01
GND-AUDIO
220n
2D05
10u 35V
22K
-AUDIO-R
220R
5D08
5D07
ID12
220n
3D16
ID11
2D06
2
4R7
VCLAMP
BYPASS
MUTE
SD
ID37
PGND
3
ID34
2D21
220n
1
2D27
RES
8
3D10-1
220n
7
6
3D10-3
22K
3D10-2
22K
2
4
FD10
3D10-4
22K
CD10
22K
4K7
5
25
8
9
MAINS SWITCH DETECT
GND_HS
3
2
7D11-1
BC847BS(COL)
1
3D15
6
+3V3-STANDBY
3D01-3
47K
6
R
3
L
23
24
AGND
13
14
FD09
A-STBY
GND-AUDIO
+3V3-STANDBY
ID35
5
5
DETECT2
GND-AUDIO
LEFT-SPEAKER
VIA
VIA
VIA
VIA
37
36
35
34
GND-AUDIO
10n
26
27
28
29
V_NOM
2D14
GND-AUDIO
GND-AUDIO
GND-AUDIO
40
39
38
7D10-2
TPA3123D2PWP
1D50
GND-AUDIO
3D01-4
47K
100p
GND-AUDIO
4
2D03
7D11-2
BC847BS(COL)
4
VIA
1D38
30
31
32
33
1735
LEFT-SPEAKER
3
100K
6
7
100K
100K
10n
4
RIGHT-SPEAKER
ID33
1D52
GND-AUDIO
3D06-4
2041145-3
2041145-4
5
100K
4
1
2
3
2
8 3D06-1 1
RIGHT-SPEAKER
10n
2D13
3D06-2
FD02
1
2
3
4
2D02
V_NOM
3D06-3 FD07
GND-AUDIO
2D01
220R
GND-AUDIO
3 7D03-2
BC847BS(COL)
FD05
FD06
5D03
5
10u
GND-AUDIO
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
4
2011-05-10
3
2011-03-09
2
2010-12-23
19112_022_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 136
DC/DC
B03B
DC/DC
B03B
5U03 RES
30R
5U02
+12V
1u0
2U20
10u
10u
*
IU22
30R
0402 Jumper
7 8
IU10
12V/1V8 CONVERSION
1
2
3R3
3U11
2U19
2U25
7U02-1
SI4952DY
10u
10u
2U23
2U24
FU05
FU02
2U21
5U00
FU03
22u
47u
2U16
1
47R
2U15
8
7
2
47R
3U23-1
3U23-2
3u6
5 6
IU23
4
1n0
2U17
3
IU09
3
4
7U02-2
SI4952DY
47R
3U23-4
47R
3U23-3
5
220p
6
+1V8
IU11
IU15
IU08
5 6 7 8
IU12
4
3U14
IU07
GND-SIG
20
VIN
3U28
GND-SIG
18
19
FU04
1u0
2U05
10u
2U04
6
10K
100n
2U14
RES 100u 2.0V
22u
IU17
IU25
GND
+1V1
IU18
GND-SIG
1u0
1n0
2U10
GND-SIG
2U09
3U21
FU00
SENSE+1V1
IU19
IU04
GND-SIG
2U07
22K
3U10
GND-SIG
RES 100p
FU09
1K0 1%
3U09
330R 1%
CU00
5K6
3U19
3U22
+1V8
1K0 1%
3U08
2U08
IU20
FU08
100n
RES
2U29
3U17
1% 330R
3U18
1% 1K0
100R 1%
100p RES
10K
V5FILT
VREG5
7
17
2U13
1
2
47u
TEST
2U12
1
TRIP
2
22
15
10R
RES
1
2
+1V1
3U20
PGND
FU01
2u0
47R
1
VFB
2
5U01
FU06
24
13
47R
3U24-1
1
2
3U24-2
SW
12V/1V1 CONVERSION
1
12
47R
1
VO
2
1 2 3
3U24-4
1
2
4
IU14
47R
3U24-3
21
16
DRVH
5 6 78
IU16
23
14
1n0
IU02
1
EN
2
2U06
3U00
3U01
3U03
12K
GND-SIG
1
2
2U11
22K
3
1
2
+3V3-STANDBY
5
8
IU01
DRVL
7U04
SI4778DY
6U00
1n0 RES
2U03
IU03
4
9
+1V1
+1V8
1
VBST
2
220p
STPS2L30A
3
10
ENABLE-1V8
3R3
2U01
100n
2
11
IU24
GND-SIG
3U02
3U05
7U03
TPS53126PW
IU13
10R
2U02
100n
7U00
BC847BW
3R3
2U22
IU06
IU05
RES
1 2 3
3R3
10u
2U00
10R
3U04
1n0
3U27
2U18
7U01
SI4778DY
IU21
CU01
CU02
CU03
CU04
CU05
GND-SIG
GND-SIG
GND-SIG
GND-SIG
GND-SIG
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 65213
2011-05-10
3
2011-03-09
2
2010-12-23
19112_023_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 137
DC/DC
B03C
DC/DC
B03C
+3V3-STANDBY
+3V3
RES 10K
+5V +3V3-STANDBY
3U75
3U74
RES 10K
LED-2
**
IU43
*
RES 10K
3U69
10K
3U68
9U41
optionally 1M99 is a 9 pin connector
IU44
3U41
IU45
9U42
RES
LED-1
LED2
LED2
10K RES
4U00
4U01
1M99
1M95
2U56
3U59
IU47
7U43
BC847BW
Emmy
( +24V AL)
yes
yes
no
yes
no
Sundance / Infinity
( +12V AL)
no
no
yes
yes
yes
BlockBuster
(For non-Amblight sets)
no
no
no
yes
no
***
Optional table for Styling
Dream Catcher
Core Range
1M95
2U44
3U43
0R
open
13 POLE
100p
100R
14 POLE
10K RES
7U42 RES
BC847BW
*
Optional table for Ambilight
Items
+3V3
3U70
LED1
LED1
3U53
10K
10K
**
1M99
1K0 RES
4
100R
FU56
FU57
FU74
FU68
RES 3U66
100R
BL-SPI-SDO
RES 3U67
100R
BL-SPI-CSn
RES 3U84
100R
BL-SPI-CLK
3D-LR
100K
IU41
100p
100p
100p
100p
2U71
MAINS-OK
+3V3-STANDBY
100R
4
RES 2U43
RES 2U52
RES 2U51
RES 2U72
1n0
RES 3U76
RES 2U48
2U56
**
1n0
RES 2U57
1-2041145-3
100p
+12VIN
2
FU77
100R
7U48-2
BC857BS(COL)
STANDBY
5
5
3U71
3U62-4
100R
FU53
10K
2
2
FU72
DETECT2
7
3
5
4
IU50
6
10K 1
7U41-1
BC847BS(COL)
1
3U60-4
7U41-2
BC847BS(COL)
8
5
22K
IU62
4K7
3U62-1
RES 10K
7
3U61
10K
6
3U60-2
4
3U60-1
IU57
1
ENABLE-3V3n
22K
IU52
8
2
BACKLIGHT-PWM_BL-VS
***
3U43
BACKLIGHT-BOOST
100R
FU55
IU55
3U64
POWER-OK
100p
1n0
10n
2U45
2U46
100K
***
2U44
+12VD
1n0
GND_AL
2U53
1K0
3U65
**
3U42
3U62-2
ENABLE-1V8
RES 10K
100n
100R
FU52
LAMP-ON
FU73
22K
IU63
3U73
+3V3-STANDBY
3K3
3U45
FU51
IU49
6
7U40-1
BC847BPN(COL)
3U80
2U55
IU56
10K
4U00
2
100K
IU40
3U63
+3V3
GND-AUDIO
3U81
3 3U60-3 6
IU61
1
1K0
3U72
100n
2U49
+24V
4U01
3U83-2
3
2
10n
+24V-AUDIO-POWER
2U50
T 3.0A 32V
FU66
FU76
**
7
6
100K
22K
IU51
3U62-3
3
+12V
+12VIN
FU67
1-2041145-4
+12VIN
1U40
2U54
BZX384-C6V2
10n
1u0 RES
+3V3-STANDBY
6U40
FU58
FU59
FU60
FU61
FU63
FU75
FU62
4
IU48
3U83-3
5
10n
2U58
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
4
1u0
2U47
***
7U40-2
BC847BPN(COL)
10K
2U68
1M95
ENABLE-3V3-5V
8
RES 3U44
7U48-1
BC857BS(COL)
5
1
FU07
FU54
3U83-4
6
FU50
100K
10K
3U83-1
GND_AL
RES 3U56
+3V3
+12V_AL
1
FU49
100n
GND_AL
IU64
3U82
FU48
3
GND_AL
1
2
3
4
5
6
7
8
9
10
11
12
13
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_024_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 138
DC/DC
B03D
DC/DC
B03D
+3V3
*
7UC0
LF25ABDT
+12V
1
IN
3
OUT
2
1u0
2UA4
*
2K2
3UA0
COM
FUA0
+2V5-REF
R
7UA0
TS2431
K
1
A
2
3
FUA4
+2V5
CUA0
IUB6
+2V5-LVDS
+5V-TUN
2
*
+3V3
8
+5V
1
3U16-1
100R
3UB0
2
2
1u0
2UB0
7UA3
PHD38N02LT
IUB4
IUA5
3
22R
4
FUA3
3U15-2
100R
3U15-3
100R
3U15-4
+1V2
8
+3V3
100R
7
2
6
3
4
5
3U16-2
100R
3U16-3
100R
3U16-4
7
6
5
100R
100R
1u0
2UB1
470R
2
470R
3UB7-3
3
3UB7-1470R
8
1
3U15-1
IU26
7UA7-1
BC847BS(COL)
3U13
6
3UB7-2
7
2UB8
7UA7-2
4
BC847BS(COL)
1
+5V
2UB2
5
*
+1V8
1
470R
22u
+2V5-REF
6
1K0 IUB2
3UB6-2
2
7
6
1K0
3UB6-1
1
8
1K0
IUB5
3 1
RES 1u0
3UB6-4
4
5
1K0
3UB7-4
5
4
3UB6-3
330R
1%
3
+12V
7UA6
BC817-25W
3U12
IUB3
330R
1%
+5V5-TUN
*
NOT FOR 5000 SERIES
ENABLE-1V8
5
+12V
RES
7UA4
TS431AILT
5
RES
2
A
K
NC
REF
470R
NC
3
470R
3U26-2
7
3
4
3U26-3
470R
3U26-4
IUB1
1
3UB3
RES
470R
+3V3
BP
+5V-TUN
4
COM
1 3U26-1 8 RES
2
INH
5
1u0
470R
3U29-4
3
OUT
100n
2UB6
4
5
3UB2
IN
2UB5
3 3U29-3 6 RES
IU30
1
+5V5-TUN
470R
2
7UA5
LDS3985M50
2
RES
7U06-1
BC847BS(COL)
1
7
RES
1u0
5
+3V3
470R
3U29-2
8
2UB7
6
8
3
RES
7U06-2
BC847BS(COL)
4
2
3U29-1
4K7
1
3U25-1
RESERVED
5UA0
1K0
30R
1
IU29
SENSE+1V2
4K7
7
3U25-2
6
IUA6
4
3U25-3
2
3
100K RES
100K RES
3UB1
100K RES
100K RES
4
3U25-4
3UB5
3UB4
100K
1K0
IUB0
2UB3
+5V
6
5
RES
1n0
2UB4
RES
330p
RES
470R
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_025_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 139
DC/DC
DC/DC
B03E
5UD0
FUD3
4n7
3UD2
33K
1%
12
68K
3UD1
1%
3UD0
15
13
VIA
10
2
7U05-1
BC847BS(COL)
RES 1
22u
100n
IU27
3U06
120K
10K
2UD6
2UD7
IUD6
7UD0-2
ST1S10PH
RES 2U27
6
RES
8
+1V1
220u 16V
SS36
RES 2UE9
+5V
3u6
3
VFB
GND
P HS
A
6UD0
IUD7
22u
SYNC
5UD1
22u
2UD5
5
VIN
IUD3
7
SW
2UD4
INH
9
2
4
RES 1n0
2UD3
ENABLE-3V3-5V
SW
A
6
1
7UD0-1
ST1S10PH
10u
2UD2
10u
2UD1
+5V5-TUN
10u
*
IUD0
30R
0402 Jumper
2UD0
+12V
14
11
5UD3
+3V3
7U05-2
RES
4
3U07
100n
IU28
RES
33K
1%
12
1M0
3UD5
3UD4
VIA
10
5
15
13
IUD2
7UD1-2
ST1S10PH
BC847BS(COL)
10K
3
RES 2U28
2UE4
22u
22u
2UE3
+1V1
220u 16V
4
FUD2
3u6
3
VFB
GND
P HS
8
A
5UD2
2UE2
SYNC
IUD4
7
SW
VIN
1% 100K
5
INH
2UE1
2
9
ENABLE-3V3-5V
4n7
3UD3
A
SW
6
1
7UD1-1
ST1S10PH
10u
14
11
7UD2
LD1117DT25
3
IN
S1D
OUT
2
+2V5
2UE6
1
100n
2UE5
COM
22u 16V
IUD5
(*) FOR 5000 SERIES ONLY
(**) NOT FOR 5000 SERIES
7UD3
LD1117DT33
IN
OUT
2
+3V3
100n
COM
22u 16V
3
2UE8
6UD1
+5V
1
*
2UE7
10u
2UD9
10u
*
IUD1
30R
0402 Jumper
2UE0
* *
+12V
2UD8
B03E
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_026_110628.eps
110628
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 140
Temperature sensor & AmbiLight
B03F
Temperature sensor & AmbiLight
B03F
5UM1
IUM0
1UM0
+3V3
30R
FUM0
V-AMBI
T 1.0A 63V
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 65213
2011-05-10
3
2011-03-09
2
2010-12-23
19112_027_110628.eps
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 141
Fan control
Fan control
B03G
+12V
+12V
1K0
FAN-CTRL1
IUS3 3US5-1
8
1
8
IUT1
100n
7US1-1
LM339P
14
2US3
3
10K 7
10K
9
2
3US7
+12V
3US5-2
10K
3US2
1 3US4-1 8
+3V3
IUS6
10K
7US2
BC807-25W
12
+12V
IUS7
3
IUT2
7US1-2
LM339P
13
IUS4 3US5-4
5
4
10
FAN-CTRL2
10K
22R
BC807-25W
7US3
IUS8
12
3US6
IUS9
47R
11
3
+12V
3US3
10K
3US5-3
6
3US9
+3V3
10K
FAN-DRV
+3V3
3
10K
7US1-3
LM339P
2
10K
3US4-3
3
5
4
+12V
6
IUS5
3US4-4
5
+12V
4
12
TACH01
RES
+12V
3
7
2
10K
7
+12V
3US4-2
9US0
TACH02
7US1-4
LM339P
1
6
FUS0
12
B03G
TACHO
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_028_110628.eps
110628
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 142
Vdisp switch
Vdisp switch
B03H
1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES
RES
7UU0
SI4835DDY
6
RES 3UU0-4
+3V3-STANDBY
5
47K
2
4
RES
7UU2-1
PUMD12
1
7
6
FUU0
5
2
IUU2
1u0
3UU3-2
22n
+VDISP-INT
1
47K RES
RES 2UU1
47R
IUU1
RES 3UU0-1
8
1
47K
8
IUU3
7
47K RES
RES
7UU3
BC847BW
3
VDISP-SWITCH
1
IUU4 3UU3-3 IUU5 3UU3-4
4
5
6
3
47K RES
2
FUU1
3UU2
+3V3
47K RES
RES 100n
3
IUU0
5
47K
RES 3UU1
5
3UU3-1
6
2UU0
8
4
7
RES 2UU2
+12VD
RES
7UU2-2
PUMD12
8
RES
7UU1
SI3441BDV
RES 3UU0-2
7
2
B03H
+3V3
4K7 RES
LCD-PWR-ONn
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_029_110628.eps
110628
2011-Jul-15 back to
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 143
10-12 B04 313912365214
Analogue externals A
Analogue externals A
B04A
IE22
CDS4C12GTA
12V
1E31
2E88
1n0
CDS4C12GTA
12V
1E54
2E91
1n0
8
RES 6E03
FE23
3E07-4
1K0 5
RES
2
** 4E02
YPBPR1-PB
3E17
IE05
100p
**
FE74
+3V3
1E01-2
MSP-8033SH-02-NI-FE-RF-PBT-BRF
BLUE
3
4E04
RES
3E44
RES
2E15
150p
18R
2E80
150p
2E79
AV2-STATUS
4
3E75
1E12
BEC3
1u8
CDS4C12GTA
12V
5E73
RES 6E23
IE53
RES
FE73
EU 3E74 18R
AV1-B
1E02-2
MSP-8032SH-01-NI-FE-RF-PBT-BRF
WHITE
3
4K7
3E32
** 4E01
IE18
AV1-STATUS
4K7
1E02-1
MSP-8032SH-01-NI-FE-RF-PBT-BRF
RED
1
**
4
4K7
RES
100p
4
2E04
1K0
100p
2E06
1
AUDIO-IN1-L
FE71
3E07-1
AUDIO-IN1-R
6E09
B04A
IE48
AV1-BLK
YPBPR1-SYNCIN1
1E01-3
MSP-8033SH-02-NI-FE-RF-PBT-BRF
GREEN
5
EU 3E76 18R
** 4E05
1E01-1
MSP-8033SH-02-NI-FE-RF-PBT-BRF
RED
1
RES
4E03
RES
2
100p
2E12
1E19
18R
CDS4C12GTA
12V
FE81
RES 6E28
2E86
150p
2E85
1u8
**
EU 3E78
18R
BEC5
3E79
5E76
150p
IE55
CVBS-MON-OUT1
18p
YPBPR1-PR
AV1-R
4K7
3E73
100p
2E14
IE51
AV2-BLK
FE85
2E98
RES
6
FE80
1E18
18R
CDS4C12GTA
12V
1u8
+3V3
RES
RES 6E26
3E77
150p
5E74
2E84
150p
2E83
AV1-G
FE86
GND_A
3E07-2
2
1K0
7
3E07-3
3
1K0
6
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
4
2011-05-10
3
2011-03-09
2
2010-12-23
19112_030_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 144
Analogue externals B
B04B
Analogue externals B
B04B
SPDIF out
YPBPR
GND_A
GND_A
30R
AV2-CVBS
3E89
IE75
RES
6E46
IE73
RES
1E07
MTJ-032-68B-46-NI-FE
1
FE59
CDS4C12GTA
12V
SPDIF-OUT
RES
5E06
2
FE41
AV3-PB
18R
YPBPR1-PB
IE76
9E58
3E90
IE77
AV3-PR
18R
CDS4C12GTA
12V
FE42
RES
IE74
9E57
EU
RES 6E52
1E39
100p
2E68
1
** 4E22
IE15
27R
FE48
MTJ-032-21B-42 NI FE
2
1E04
3E88
9E04
CDS4C12GTA
12V
1E28
100p
RES
2E67
1
** 4E21
AP
EU
2
1E03
AV3-Y
YPBPR1-SYNCIN1
FE51
MTJ-032-21B-45 NI FE (PBT)
FE72
10p
RES 1E44
RES
3E87
18R
CDS4C12GTA
12V
RES 6E40
4E20
RES 6E51
**
1E43
100p
YELLOW
2E27
1
IE71
9E29
RES 2E22
1E08-1
*
MSP-8033SH-05-NI-FE-RF-PBT-BRF
EU
FE54
2
YPBPR1-PR
GND_A
Provision for
Dreamcatcher
YPBPR AUDIO
+3V3
MSP-8033SH-05-NI-FE-RF-PBT-BRF
6
FE49
GND_A
100p
2E72
3E96
RES 6E38
1E42
1n0
**
2E40
4
1E08-2
3
*
MSP-8033SH-05-NI-FE-RF-PBT-BRF
RES
WHITE
4E24
AV3-Y
AV1-CVBS
9E15
9E16
RES
RES
AV3-PR
RXD1-MIPS
9E19
9E12
RES
RES
AV3-PB
TXD1-MIPS
9E17
9E14
RES
RES
AUDIO-IN3-R
AV1-B
9E11
9E18
RES
RES
AUDIO-IN3-L
AV1-G
9E13
9E20
RES
RES
AV1-R
9E22
RES
AV1-STATUS
AUDIO-IN1-R
AV1-BLK
9E24
9E25
9E26
RES
RES
RES
AUDIO-IN1-L
9E28
RES
IE29
AUDIO-IN3-L
1K0
100p
GND_A
IE31
2E71
FE43
RES
RES
1E32
AUDIO-IN3-R
1K0
CDS4C12GTA
12V
RED
1E29
1n0
** 4E23
CDS4C12GTA
12V
FE50
5
RES 6E06
1E08-3
2E39
*
3E97
VGA ( OR DVI ) AUDIO
AUDIO-IN4-L
1K0
100p
CDS4C12GTA
12V
3E21
RES 6E19
V_NOM
1n0
1E37
2E36
FE02
IE09
2E35
1E09
MSJ-035-69A-B-RF-PBT-BRF
2
3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
31
DF50-30DP
FE01
AUDIO-IN4-R
100p
1K0
2E38
CDS4C12GTA
12V
RES 6E20
V_NOM
1n0
1E38
2E37
IE10
3E20
FE03
1E10
3150-831-030-H1
2
VCC
FE44
SPDIF-OPT
CDS4C12GTA
12V
RES 6E53
V_NOM
100p
1E80
100n
3
RES 2E77
GND
MT
7 6 5 4
1
2E73
VIN
1R0
3E9C
+3V3
* SOC Cinch V 3P 1L3 YEWHRDY at 1E08 for Brazil
** Provision for ESD
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_031_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 145
Ethernet & Service
3E53-2
IE49
RXD1-MIPS
IE07
3E53-3
IE50
47R
6E43
+3V3-ET-ANA
100n
10u
2E63
100n
2E66
30R
6E44
+3V3
2E62
4
3
BZX384-C5V1
5E08
6
1
2
47R
3E53-1
47R
3E53-4
FE56
8
5
MSJ-035-69A-B-RF-PBT-BRF
FE58
PROVISION FOR iTV
IE38
IE32
10u
2E48
2E49
100n
ETH-TXD(3)
ETH-TXER
12
ETH-RXDV
IE63
+3V3
10K
3E34
10K
3E72
3E68
RES
3E35
RES
14
2
RXD-UP
1
1
ETH-REGOFF
10K
X1
+3V3
ETH-INTSEL
10K
+3V3
9E42
ETH-CRS
32
RBIAS
IE39
MDC
MDIO
3
RXD1-MIPS
1
1
X1
VSS
13
RES
7E11-2
74HC4066PW
4
RES
7E12
PDTC144EU
RES
7E13
PDTC144EU
AV2-BLK
5
33
+3V3
RES
7E11-1
74HC4066PW
1
10K
10K
RES
2
CRS
ETH-RXCLK
RES
3E9E
3E65
3
REGOFF
1
LED
2
INTSEL
+3V3
14
10K
RES
10K
ETH-RXER
3E64
IE64
7
BAS316
ETH-TXCLK
RES
6E48
20
provision for iTV
100n
ETH-TXP
ETH-TXN
13
RXER
RXD4
0
PHYAD
1
RXCLK
0
1
2 TXD
3
4
INT
TXER
29
28
26
RXDV
TXEN
17
16
ETH-MDC
ETH-MDIO
P
N
ETH-RXP
ETH-RXN
RES
3E9D
22
23
24
25
18
TX
31
30
7
21
4
7
ETH-TXEN
P
N
14
+3V3
ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
RX
TXCLK
COL
CRS_DV
MODE2
1
2
3
5
502382-0370
RES
2E69
0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>
15
10K
10K
IO
RST
10K
RES 3E71
RES 3E80
1A 2A
VDD
3E40
19
+3V3
12K1
1%
CLKIN
1
XTAL
2
10p
1
27
CR
RES 2E70
1K5
6
10p
2E54
10p
2E55
RES
RES
RES
RES
7E10-1
LAN8710A-EZK
11
10
9
8
3E51
4n7
100n
2E53
2E52
TXD
RXD
ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)
3E70
RES
RES
1E71
25M
5
4
ETH-COL
IE06
IE33
1M0
1E70
NX3225GA
3E33
3E66
3E67
3E81
3E82
10K
10K
10K
10K
10K
3E30
3E69
RES
10K
B04C
+3V3
+3V3-ET-ANA
IE26
UART
SERVICE
CONNECTOR
47R
+3V3
RESET-ETHERNETn
1E06
2
3
1
FE57
1E85
7
1E86
TXD1-MIPS
BZX384-C5V1
Ethernet & Service
B04C
34
35
36
14
7E10-2
LAN8710A-EZK
VIA
40
41
42
VIA
9
TXD-UP
1
1
X1
6
14
37
38
39
7
VIA
RES
7E11-3
74HC4066PW
8
10
TXD1-MIPS
1
1
12
7
X1
RES
7E11-4
74HC4066PW
11
+3V3-ET-ANA
+3V3-ET-ANA
22R
22R
3E98
3E26
3E99
49R9
1%
3E95
49R9
1%
3E25
49R9
1%
3E22
49R9
1%
CONFIGURATION RESISTOR SETTINGS
Resistor
POP
EMPTY
ETHERNET CONNECTOR
ETH-TXP
1E87
3 ACM2012 2
FE27
1N00
FE60
1
ETH-RXP
FE29
1E88
3 ACM2012 2
ETH-RXN
FE31
4
FE30
FE61
22n
9 11
10 12
2E60
5
CDA5C16GTH
16V
6E47-4
4
CDA5C16GTH
16V
RES
6
6E47-3
3
7
2
CDA5C16GTH
16V
RES
6E47-1
15p
1
RES
RES
2E59
5E04
RES 27n
2E09
RES 15p
0 ohm
RES
15p
3E39
RES
2E58
5E03
RES 27n
2E08
RES 15p
0 ohm
RES
15p
3E29
2E57
RES
5E02
RES 27n
2E07
RES 15p
0 ohm
RES
15p
3E28
2E56
RES
5E01
RES 27n
2E05
0 ohm
RES
3E27
RES 15p
8
1
6E47-2
4
FE28
CDA5C16GTH
16V
RES
ETH-TXN
FE34
1
2
3
4
5
6
7
8
3E64 (RES)
PHYADD(0) = 1
PHYADD(0) = 0
3E65 (RES)
PHYADD(1) = 1
PHYADD(1) = 0
3E66 (RES)
PHYADD(2) = 1
PHYADD(2) = 0
3E67 (RES)
RMII mode selected
MII mode selected
5450-323-183-H3
3E68 (RES)
Internal 1.2V reg. disabled
Internal 1.2V reg. enabled
3E69 (RES)
MODE(0) = 0
MODE(0) = 1
3E70 (RES)
MODE(1) = 0
MODE(1) = 1
3E71 (RES)
MODE(2) = 0
MODE(2) = 1
FE32
3E72
ETH-INTSEL
ETH-REGOFF
FE33
INTERRUPT FUNCTION
INTERRUPT FUNCTION
DISABLED ON
ENABLED ON
nINT/TXER/TXD4 SIGNAL
nINT/TXER/TXD4 SIGNAL
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_032_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 146
HDMI
HDMI
B04D
ARX2+
10K
1u0
10u
100n
2ECV
FEC0
2EC0
220u 16V
RES 2EC1
1P04
3ECH
ARX1ARX0+
ARXCARXC+
65
66
BRX2+
ARX0ARX0+
67
68
BRX2BRX1+
ARX1ARX1+
69
70
BRX1BRX0+
ARX2ARX2+
71
72
AIN-5V
HDMI CONNECTOR 2
BIN-5V
BRX-HOTPLUG
47K
3ECM-3
6
10R
7
100K
1u0
BRX-DDC-SDA
BRX-DDC-SCL
IE43
2ECN
35
36
33
34
CEC_D
N
R0X0
P
FECC
FECD
BRX-DDC-SCL
BRX-DDC-SDA
FECE
FECF
BIN-5V
47K
BRX-HOTPLUG
1
20
22
3ECA-1
8
BRX-DDC-SCL
BRX-DDC-SDA
BIN-5V
HDMI CONNECTOR 1
2
CIN-5V
CRX2+
3ECM-2
7
3
3ECN-3
10R
CRX-DDC-SDA
CRX-DDC-SCL
1u0
PCEC-HDMI
4
47K
3E23
100R
IEC4
3ECM-1
8
10R
1u0
DRX-DDC-SDA
DRX-DDC-SCL
5
6
BRX2BRX2+
7
8
IE44
41
42
39
40
CRXCCRXC+
11
12
CRX0CRX0+
13
14
CRX1CRX1+
15
16
CRX2CRX2+
17
18
5
100K
30R
ARC-eHDMI+
2ECC
IE45
2ECQ
5EC2
eHDMI+
CIN-5V
7EC0
BC847BW
3ECD
+3V3-STANDBY
22K
RES
RES
7E02
BC847BW
1
DIN-5V
4
3ECN-4
10p
20
22
47K
CRX-HOTPLUG
3ECA-3
CIN-5V
3
FECM
FECN
BRX1BRX1+
DRX-HOTPLUG
CRX-DDC-SCL
CRX-DDC-SDA
6
FECK
FECL
3ECA-4
FECA
5
CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA
FECJ
3
4
2ECP
CIN-5V
CRX0CRXC+
BRX0BRX0+
6
100K
CRX2CRX1+
CRX1CRX0+
1
2
CRX-HOTPLUG
1P02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23
BRXCBRXC+
45
46
43
44
DRXCDRXC+
19
20
DRX0DRX0+
21
22
DRX1DRX1+
23
24
DRX2DRX2+
25
26
IEC6
9EC0
CEC-HDMI
IEC5
100n
49
6
10K
8
DSCL4
DSDA4
N
R0XC
P
2EC3
38
37
9
27
64
R4PWR5V
48
47
VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI
9EC2
RES
51
CEC-HDMI
N
R0X1
P
N
R0X2
P
(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1
TX2
N
P
TX1
N
P
TX0
N
P
TXC
N
P
7
3ECA-2
BRXCPCEC-HDMI
3
BIN-5V
2
BRX0BRXC+
2
3ECN-2
DSDA0
DSCL0
+5V-EDID
3
29
30
(CBUS) HPD0
R0PWR5V
N
R1XC
P
N
R1X0
P
57
56
HDMIA-RX2HDMIA-RX2+
59
58
HDMIA-RX1HDMIA-RX1+
61
60
HDMIA-RX0HDMIA-RX0+
63
62
HDMIA-RXCHDMIA-RXC+
3ECJ RES
N
R1X1
P
TPWR_CI2CA
N
R1X2
P
CEC_A
(CBUS) HPD2
R2PWR5V
INT
55
50
52
4K7
IE12
FECR
RES
3ECK
MICOM-VCC33
4K7
9EC3
RES
FECY
PCEC-HDMI
3ECL RES
+3V3
4K7
DSDA2
DSCL2
N
R2XC
P
CSCL
CSDA
N
R2X0
P
RSVDL
N
R2X1
P
54
53
10
28
N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA
N
R3X0
P
N
R3X1
P
N
R3X2
P
3EC3
3EC5
100R
100R
SCL-SSB
SDA-SSB
10p
2ECM
31
32
10K
3ECP-3
1u0
IE42
1
10R
ARX-DDC-SDA
ARX-DDC-SCL
8
100K
30R
10p
RES 2ECY
1
3ECN-1
RES 2ECX
5
SBVCC33
AIN-5V
3ECM-4
3ECP-1
8
4
MICOM_VCC33
1
47K
ARX-HOTPLUG
3EC1-1
ARX-HOTPLUG
10u
RES 2ECW
100n
100n
2EC8
VCC33
AIN-5V
20
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23
100n
2EC7
2EC6
6
47K
3EC1-3
3
7EC1
SII9187B
ARX-DDC-SCL
ARX-DDC-SDA
FEC4
FEC5
+3V3
+3V3-HDMI
ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA
RES
5EC3
FEC7
AIN-5V
ARX0ARXC+
FEC1
FEC2
SII9187B = 0xB2
FECB
ARX2ARX1+
1P03
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
73
EPAD
3ECE
22K
IEC7
FECW
+3V3-STANDBY
6EC1
+5V
7EC1
3ECN
3ECF
NON-INSTAPORT
9187B
4X 100K
100K
BLOCKBUSTER
INSTAPORT
9287B
4X 100K
100K
SUNDANCE
+5V-VGA
BAT54
IE11
3ECG
3ECF
4R7
FECP
30R
MICOM-VCC33
2EC2
5EC0
+3V3
HDMI CONNECTOR 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23
B04D
I2C Address
FEC3
FECZ
100K
DDCA-SDA
IE65
2
3ECU-2
7
+3V3
10K
2ECU
DDCA-SCL
IE66
4 3ECU-4 5
10K
1u0
4
SPB SSB TV550
2K11 4DDR BR SD
+5V-EDID
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_033_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 147
Headphone
Headphone
B04E
+3V3-STANDBY
5
4
PUMD12
7EE0-2
A-PLOP
3
6
A-STBY
FEE0
RESET-AUDIO
2
7EE0-1
PUMD12
1
2EE0
22K
3EE1-3
5
22K
3EE1-2
3EE1-4
2
4
6
8
22K
3
47p
3EE1-1
7
1
22K
2EE5
7EE1
TPA6111A2DGN
100n
2EE1
47p +3V3
8
3
IEE2
ADAC(4)
2EE3
1u0
IEE1
2EE4
1u0
8
3EE0-1
10K
Φ
IEE3
2
1
5
3EE0-4
6
4
10K
IEE4
5
2EE2
3
AMPLIFIER
2EE6
1
IEE7
4
33R
3EE2-4
6
FE36
5
VO
SHUTDOWN
BYPASS
2
VIA
GND GND_HS
2EE7
7
IEE8
2
4V 100u
10
11
AMP1
33R
4V 100u
2
3EE2-3
1
3EE2-2
33R
3EE2-1
FE35
7
AMP2
8
33R
3 3EE0-3 6
10K
22K
A-PLOP
1
IN-
4
1u0
IEE6
IEE5
1
VDD
9
IEE0
ADAC(3)
RES
3EE3
B04E
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
19112_034_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 148
10-13 B05 313912365214
DDR
DDR2-CLK_P
DDR2-CLK_N
3B28
DDR2-CLK_P
240R
DDR2-CLK_N
DDR2-BA2
DDR2-ODT
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2
F9
E8
F8
F2
G8
F7
G7
F3
B3
RES
240R
3B01
3B23
NU|RDQS
2
6 3B02-3
33R 3
8 3B02-1
33R 2
3B02-2
5
3B02-4
33R
4
8
33R
C8
3
C2
D7
1
D3
D1
D93B00-4 4
B1
B9 3B00-11
B7
A8
3B00-2
7
33R
6 3B00-3
33R
7
33R
5
33R
2p2
DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23
3B12
33R
3B13
2B44
RES
0
1 BA
2
DDR2-DQS2_P
DDR2-DQS2_N
33R
A2
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
G2
G3
G1
DDR2-BA0
DDR2-BA1
DDR2-BA2
DDR2-ODT
ODT
3B03
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
NC
L3
L7
DDR2-A14
VSSQ
VSSDL
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3
RES
240R
F9
E8
F8
F2
G8
F7
G7
F3
B3
3B24
33R
2B17
100n
2B37
100p
VDD
VDDL
VDDQ
E2
A9
C1
C3
C7
C9
E1
A1
E9
L1
H9
100n
100n
2B16
100n
2B15
100n
2B14
100n
2B13
100n
2B12
100n
2B11
100n
2B10
E2
A9
C1
C3
C7
C9
E1
DQS
A3
E3
J1
K9
33R
2B41
2B36
100p
2B08
100n
G2
G3
G1
DDR2-BA0
DDR2-BA1
DQ
0
1
2
3
4
5
6
7
VREF
Φ
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
SDRAM
DQ
0
1
2
3
4
5
6
7
DQS
C8
3B05-3
C2
D7
3B04-3
D3
D1
D93B04-4
B1
B93B04-1
3
3
4
1
B7
A8
2B45
0
1 BA
2
NU|RDQS
3B04-2
2
7
6
33R
6 33R
7 3B05-2
33R
33R 2
1
8 3B05-1
33R
5
5 3B05-4
33R
4
8
33R
33R
3B15
RES
2p2
3B14
33R
DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31
DDR2-DQS3_P
DDR2-DQS3_N
33R
A2
ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
+1V8
NC
L3
L7
DDR2-A14
VSSQ
VSSDL
A7
B2
B8
D2
D8
3B27
240R
Φ
SDRAM
B05A
DDR2-VREF-DDR
E7
DDR2-CLK_N
7B03
EDE1108AGBG-1J-F
VREF
VDDQ
A3
E3
J1
K9
DDR2-CLK_P
240R
VDDL
A7
B2
B8
D2
D8
3B22
VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
E7
AT T-POINT
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A1
E9
L1
H9
7B02
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
+1V8
DDR2-VREF-DDR
100n
100n
2B07
100n
2B06
100n
2B05
100n
2B04
100n
2B03
100n
2B02
100n
2B01
47u
2B00
2B40
+1V8
47u
2B09
DDR
B05A
+1V8
DDR2-VREF-DDR
3B25
33R
FB00
1X20
HOOK1
1X21
HOOK1
1X22
HOOK1
1X23
HOOK1
DQS
C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1
B7
A8
2B46
0
1 BA
2
NU|RDQS
2
5
33R
7
33R
5
33R
8
33R
3B17
RES
2p2
3
1
3
3B07-2
7
33R
6 3B07-3
33R
8 3B08-1
33R
6 3B08-3
33R
3B16
33R
DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7
DDR2-DQS0_P
DDR2-DQS0_N
33R
A2
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
G2
G3
G1
DDR2-BA0
DDR2-BA1
DDR2-BA2
DDR2-ODT
ODT
3B09
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
NC
VSSDL
L3
L7
DDR2-A14
VSSQ
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1
RES
240R
3B26
33R
F9
E8
F8
F2
G8
F7
G7
F3
B3
2B35
100n
2B39
100p
VDD
VDDL
VDDQ
E2
A9
C1
C3
C7
C9
E1
A1
E9
L1
H9
100n
100n
2B34
100n
2B33
100n
2B32
100n
2B31
100n
2B30
100n
2B29
100n
2B28
47u
2B27
2B43
2B26
100n
2B38
100p
E2
DQ
0
1
2
3
4
5
6
7
180R 1%
3B21
E1
SDRAM
A3
E3
J1
K9
DDR2-VREF-DDR
Φ
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
VREF
Φ
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13
SDRAM
DQ
0
1
2
3
4
5
6
7
DQS
C8
C2
3B11-3 3
D7
3B10-3 33R 3
D3
D1
D93B10-4 4
B1
B9 3B10-1 1
B7
A8
2B47
0
1 BA
2
NU|RDQS
6
6 33R
2 3B10-2 7
33R
2
1
5 3B11-1
33R
4
8
33R
3B19
RES
2p2
7 3B11-2
8 33R
33R
5 3B11-4
33R
3B18
33R
DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15
DDR2-DQS1_P
DDR2-DQS1_N
33R
A2
ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS
NC
VSSDL
L3
L7
DDR2-A14
VSSQ
A7
B2
B8
D2
D8
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0
F9
E8
F8
F2
G8
F7
G7
F3
B3
RES
240R
3B06
7B01
EDE1108AGBG-1J-F
VREF
E7
3B20
180R 1%
DDR2-ODT
VDDQ
A3
E3
J1
K9
DDR2-BA2
+1V8
VDDL
A7
B2
B8
D2
D8
DDR2-BA0
DDR2-BA1
G2
G3
G1
VDD
E7
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A1
E9
L1
H9
7B00
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
A9
C1
C3
C7
C9
100n
100n
2B25
100n
2B24
100n
2B23
100n
2B22
100n
2B21
100n
2B20
100n
2B19
47u
2B18
2B42
DDR2-VREF-DDR
1X24
HOOK1
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
4
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 149
10-14 B06 313912365214
Display interfacing-Vdisp
Display interfacing-Vdisp
B06A
1G03
T 3.0A 32V
5G01
FG0H
1G00
+VDISP-INT
100n
T 3.0A 32V
RES
2G43
+VDISP
30R
RES
5G02
22u
RES
30R
RES
2G44
B06A
RES
3G28
2K2
IG11
RES
6G00
LTST-C190KGKT
For Development use only
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
4
2011-05-10
3
2011-03-09
2
2010-12-23
19112_036_110628.eps
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 150
Video out - LVDS
Video out - LVDS
B06B
47p
47p
47p
2G27
2G24
2G25
47p
2G7A
2G26
47p
47p
2G78
2G79
47p
47p
2G76
47p
47p
10K
RES 3G35
2G75
10K
9G0K-4
9G0K-3
9G0K-2
9G0K-1
5
6
7
8
RES
2G77
10K
RES 3G34
+VDISP
RES 3G33
+3V3
FI-RE51S-HF
60 61
58 59
56 57
54 55
52 53
4
3
2
1
100n
2G93
100n
2G94
100n
FG2J
2G95
100n
FG30
FG31
FG32
FG33
2G96
2G99
2G97
2G98
PX3APX3A+
PX3BPX3B+
PX3CPX3C+
PX3CLKPX3CLK+
47p
47p
47p
47p
FG11
FG1J
PX3DPX3D+
PX3EPX3E+
PX4APX4A+
PX4BPX4B+
PX4CPX4C+
FG12
FG13
FG14
PX4CLKPX4CLK+
FG18
FG15
FG16
FG17
FG19
FG1A
FG1B
FG1Q
FG1P
CTRL-DISP
SDA-DISP
SCL-DISP
RES 3G32
3G2W
3G2Y
CTRL-DISP
RES 3G38
RES 3G37
BACKLIGHT-BOOST
3D-LR
CTRL-DISP
CTRL-DISP
3D-VS-DISP
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FG1C
FG1D
FG1E
FG1F
FG1G
FG1H
FG1K
FG1L
FG1M
FG1N
PX4DPX4D+
PX4EPX4E+
FI-RE41S-HF
51
50
48
49
46
47
44
45
42
43
RES 3G2Z
FG04 RES 3G30
RES 3G31
RES 3G36
100R
100R
100R
FG34
FG2H
FG2G
100R
100R
FG35
FG2R
100R
100R
100R
100R
FG2K
FG2L
FG2M
FG2E
FG2F
FG1Y
PX1APX1A+
PX1BPX1B+
PX1CPX1C+
FG21
PX1CLKPX1CLK+
FG22
FG23
PX1DPX1D+
PX1EPX1E+
FG24
FG25
FG26
FG27
FG1Z
FG20
10p
10p
2G28
2G29
PX2APX2A+
PX2BPX2B+
PX2CPX2C+
FG28
FG29
FG2A
FG2B
FG2C
FG2D
PX2CLKPX2CLK+
FG1R
FG1S
PX2DPX2D+
PX2EPX2E+
FG1T
FG1U
FG1W
FG1V
FG2P
+VDISP
100n
2G92
2G91
B06B
RES 9G0G
FG2N
1G50
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1G51
TO DISPLAY
TO DISPLAY
1X05
REF EMC HOLE
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 151
AmbiLight CPLD
AmbiLight CPLD
B06C
B06C
5GA0
FGA0
+3V3
VINT
5GA1
100n
100n
2GA2
2GA1
1u0
2GA0
30R
DEBUG ONLY
FGA1
+3V3
VIO
+3V3
100n
10K
RES
4
3
2
1
5
6
7
8
100R
100R
100R
100R
RES
RES
RES
RES
26
IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR
IGA2
IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28
IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38
IGA1
CPLED2
CPLED3
5
6
7
8
12
13
14
16
18
19
20
21
22
23
27
28
TCK
TDI
TDO
TMS
PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK
9GA1 RES
3GA1
4
3G10-4
2
3G10-2
3G12
4
3G11-4
RES
47R
5
33R
3
7 3G10-3
33R
3G13
1
10R
5 3G10-1
33R
IGA3
GCK2
+3V3
3
+3V3
AMBI-SPI-CS-EXTLAMPSn
6
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS
33R
8
33R
RES
7GA1-1
BC847BS(COL)
1
2
GTS1
+3V3
3
RES
7GA2-2
BC847BS(COL)
4
5
GTS2
GND
4
17
25
+3V3
RES
7GA1-2
BC847BS(COL)
4
5
GCK3
AMBI-PROG_B1
AMBI-BLANK_R1
6
33R
10p
11
9
24
10
3GA5-4
3GA5-3
3GA5-2
3GA5-1
SD51022
10p
2G19
29
30
31
32
37
38
IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18
10p
2G18
33R
3
33R
10p
10p
2G12
10p
2G11
10K
2G10
3G14
1
6
33R
3G11-3
8
3G11-1
IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42
10p
2G16
36
34
33
GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2
3G15
33R
GCK3
GTS1
GTS2
GSR
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R
10p
2G15
3GA3
VCCIO
10p
2G14
PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
2
3
39
40
41
42
VCCINT Φ
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3
2G13
43
44
1
15
35
7GA0
XC9572XL-10VQG44C0100
PXCLK54
GCK2
GCK3
VIO
1
2
3
4
5
6
+3V3
10p
RES
VINT
2GA6
3GA4
RES
1G37
10p
2G17
2GA5
1u0
2GA3
30R
+3V3
6
6 330R 3
RES
3GA6-3
5 330R 4
RES
3GA6-4
RES
3GA6-1
FGA3
+3V3
SD51022
BACKLIGHT-PWM
9GA0
LTST-C190KGKT
FGA5
FGA2
RES
6GA3
FGA4
LTST-C190KGKT
FGA6
RES
6GA2
1
2
3
4
5
6
LTST-C190KGKT
100R
100R
100R
100R
RES
6GA1
8
7
6
5
RES
6GA0
1
2
3
4
LTST-C190KGKT
2GA4
8
100n RES
RES 3GA2-1
RES 3GA2-2
RES 3GA2-3
RES 3GA2-4
8 330R 1
RES
1G36
1
2
3
4
5
6
7
RES
3GA6-2
DEBUG ONLY
RES
1G35
RES
7GA2-1
BC847BS(COL)
1
2
7 330R 2
GSR
BACKLIGHT-PWM_BL-VS
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
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3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 152
SPI buffer
SPI buffer
B06D
RES
+3V3
20
3EN1
3EN2
G3
PNX-SPI-CLK
PNX-SPI-SDO
RES
7GE0
74LVC245A
1
PNX-SPI-CSBn
IGE0
19
3
2
1
2
17
16
15
14
13
12
11
3GE0-3
47R
3
4
5
6
7
8
9
3GE1-3 6
3GE4
RES
3 RES
47R
3GE3
47R
6 RES
1
BL-SPI-CLK
3GE0-1
5
8 RES
47R
4 3GE1-4
47R RES
BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI
RES
47R
10
AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI
18
RES
7GE1
PDTC114EU
10K
100n
RES
3GE2
+3V3
RES
2GE0
B06D
PNX-SPI-CLK
8
RES
9GE0-1
1
BL-SPI-CLK
PNX-SPI-SDO
7
RES
9GE0-2
2
BL-SPI-SDO
BL-SPI-SDI
RES 9GE1
PNX-SPI-CS-BLn
RES 9GE2
RES
5 9GE0-4
IGE1
PNX-SPI-SDI
*
**
4
BL-SPI-CSn
Buffer
*
**
Direct
4
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 153
10-15 B09 313912365214
Connectors comp
Connectors comp
B09A
FC67
+3V3
30R
1M59
FC78
3C70
100R
FC79
100n
2C70
FC81
GND_AL
*
FC83
1C86
+24V
FC82
AMBI-POWER
100n
RES
2C95
FC84
100n
* 1C87
2C94
T 2.0A 63V
+12V_AL
100p
IC73
100R
2C78
IC74
3C77
100p
LED-2
100R
LED-1
FC91
FC92
3C78
100p
100R
2C80
FC95
KEYBOARD
FC93
FC94
+5V
3C79
100p
FH34SRJ-26S-0.5SH(50)
T 2.0A 63V
FC90
100p
28
1
2
3
4
5
6
7
8
FC89
2C79
IC75
1M19
FC88
+3V3-STANDBY
10R
2C96
TO
LED PANEL
100n
FC76
RC
2C81
FC77
47n RES
6C02
AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP
2C77
3C76
2C93
2C82
100n
RES
RES
V-AMBI
100p
100R
6C05
FC75
3C75
LIGHT-SENSOR
RES
BZX384-C5V6
FC74
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
2C76
FC87
BZX384-C5V6
FC73
AMBI-PWM-CLK_B2
6C03 RES
FC72
V-AMBI
BZX384-C5V6
FC71
AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
3C74
FC70
AMBI-SPI-CLK-OUT
100K
RES
5C55
**
B09A
GND_AL GND_AL
RES 3C96
+T
ITEMS
BLOCKBUSTER
EMMY
SUNDANCE
/ INFINITY
1C86
N
Y
N
1C87
N
N
Y
1
2
3
4
SDA-SET
FC64
* RES 3C92
RES
1M71
FC96
FC97
FC98
1
2
3
4
2041145-4
TEMPERATURE
SENSOR
100R
* RES 3C93
FH52-11S-0.5SH
10K
RES 5C54
RES 5C53
+12V
30R
T 1.0A 63V
RES
1C85
30R
IC78
1u0
FC99
+3V3
1u0
100R
RES 3C83
FC66
47R
RES
**
FC86
FC65
1u0
2C91
RES 3C82
RES
0R3
2C90
FC63
3C95
+T
47R
**
100R
RES3C81 100R
+3V3
FAN-DRV
8
7
6
5
10p
FC85
3C94
10p
2C87 RES
RES 3C80
9C00
RES
9C01
RES
2C86 RES
FC62
100R
FAN-CTRL2
*
* RES 3C91
100R
iTV
100p
SDA-BL
* RES 3C90
10K
RES 2C85
TACH02
+3V3
FC61
100p
RES 2C84
SCL-BL
9C02-1
9C02-2
9C02-3
9C02-4
1M20
1
2
3
4
5
6
7
8
9
10
11
12
3C97
RES 2C83
TACH01
0R3
+5V
SCL-SET
FAN-CTRL1
**
*
+3V3-STANDBY
Option table for Ambilight
**
Option table for Leading Edge
Sundance / Infinity
Items
BlockBuster / Emmy
1M19
Yes
No
1M20
No
Yes
RESERVED
SPB SSB TV550
2K11 4DDR BR SD
3139 123 6521
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2011-05-10
3
2011-03-09
2
2010-12-23
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Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 154
10-16 313912365214 SSB Layout
Overview top side
3UB1
2G98
2B46
3B07
5UD2
2UD8
2UD7
5UD1
3S1B
9F27
9F28
3S1L
3UD1
2S4D
3S3N
3S2A
3B13
3S3R
3S3T
3UD0
2UD1
3B00
3S1C
2UD2
3S3L
3B05
3S6K
5UD0
IF62
3S3F
3B15
DS50
3S54
2S4G
3S50
3S3W
2S7N
2S87
3S4R
3S59
2S7L
2S7U
2S8G
9S18
2S78
3S84
3S83
6F72
1FL5
3F78
7F70
3FLE
IF89
2FL6
2FL7
1P08
5F70
7FL5
2F9D
3F34
9FLE
9E15
9FLF
2FDD
3FDG
2FDC
1FD2
1FD3
6FD3
1T01
3FL2
3F65
2F88
9F71
3F64
5F72
2F86
3F75
3E20
2E37
1E38
6FC7
2F97
2E67
3ECF
6FC5
6E53
2E73
3E9C
1P02
3FC2
1FC6
1FC3 1FC4 1FC2
6FC2
6FC1
3FC5
3FC6
2FC6
2FC2
9FC4
2FC1
9FC5
3FC7
2FC4
2FC3
9FC6
2FC5
1E80
9FC3
2FC7
6FC6
6FC8
2FC8
1FC1
1P03
2ECC
1FC5
1P04
5EC2
1P05
6FC3
6FC4
3FC3
2E77
3FC4
2ECP
2ECM
3ECM
1E10
1N00
1E07
3U59
3U74
3U53
9U41
3U41
9U42
3U75
7EC1
2EC1
2F60
IEE3
9EC3
3U69
1F52
3F623F63
2ECN
2F81
7EE1
2EE1
1329
3ECN IE42
3FC1
3E89
9E57
9E17
3ECP
3EC5
IEE6
2EE2
2EE5
IEE5
3EE0
4E24
4E21
6E51
3EE2
2EE4
3EE3
6E46
2EE0
2EE7
IEE4
3EC3
1E44
3U70
3U68
7U43
2EE3
3EE1
2E22
3C95
2C81
4E20
2EE6
3C94
7U42
6EC1
1328
2E05
2C90
2C86
2C87
IE11
1P07
2ECU
5E06
3C97
2C91
1E03 1E04
3E27
6E47
IC74
3C79
6C05
9C02
1E43
2F9A
6FD2
5E01
1E87
1E88
2E62
2E60
3E26
6C03
2C82
5E02
3E28
3C77
5E08
3C96
2C78
IC75
3C78
3E98
2C80
2E63
2E56
3FL4
1F51
2F99
2F98
2E57
2C93
1E28
3E25 3E22
7EE0
2E66
2E07
3C76
3E40
3C74
6C02
2C77
1E37
1E08
3E72
3C75
IE10
6E20
2C76
1E42
1E29
1E09
3E21
3E68
3ECG
3E34
3E35
1E39
IE07
2G77
2E35
6E19
2E54
2G75
2E38
2E36
2E27
IE09
4E23
4E22
6E38
3E88
9E29
6E40
2E40
3E96
2E71
9E13
2E55
2E72
9E11
7E10
3E30
3E33
2E39
1E70
3G38
2G76
6E06
2E52
3E51
2F9B
1E32
3E97
2G24
3E87
9E04
2E53
4E05
4E04
2G79
4E01
2F93
3E65
3E66
3E70
3E67
3E69
2E49
2E48
3E64
9E42
3E80
3E71
2F9C
9FLK
9FLG
5F73
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4
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2011-05-10
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CXXX
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FECG
4
SSB Layout Bottom
2011-05-10
3139 123 6521
19112_042_110628.eps
110628
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 156
10-17 E 27221719026x IR/LED/Key Board
Leading Edge Module
Leading Edge Module
+3.3V
+3.3V
A
VDD
L1
BZ1
B
E
100uH
2
C6
104
1
R2
10K
VPP
C1
4.7uF/16V
BUZZER
BUZZER
Q1
R9
8
1K
VDDHI JP1
2SC8050
R1
ANALOG_VOUT
C2
105
ZD1
1K
C3
105
10
9
BUZZER
11
12
PWM
SCL
13
14
VPP/MCLR/RE3
SEG12/Vcap(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
SEG15/COM3/VREF+/C1IN+/AN3/RA3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5
VSS
SEG3/P1A/CCP1/RC2
SEG6/SCL/SCK/RC3
+5V
ANALOG_VOUT
LED1
+3.3V
LED2
IR
CPS3
100R
CPS2
100R
CPS1
100R
CPS0
18
17
16
15
CH+
CH-
1
HOME
1
AL
1
R8
19
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
100R
R7
C5
104
VSS
1
1
CPS4
R6
SEG1/VCAP(2)/CLKOUT/OSC2/RA6
SEG2/CLKIN/OSC1/RA7
P2B(1)/T1CKI/T1OSO/RC0
P2A(1)/CCP2(1)/T1OSI/RC1
100R
R5
VDD
20
VDD
CPS5
R4
26
25
24
23
22
21
RB5/AN13/CPS5/T1G
RB4/AN11/CPS4
RB3/AN9/CPS3/CCP2(1)
RB2/AN8/CPS2
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
1
100R
VOL+
1
VOL-
SDA
J2
CONNECTOR
8
7
6
5
4
3
2
1
28 ICSPDAT
27 ICSPCLK
RB7/ICSPDAT
RB6/ICSPCLK
5.6V
J1
Proximity
R3
1
2
3
4
5
6
7
C4
104
R11
100R
PIC16LF1933
U1
JP2
MCU
CAP TOUCHSENCE
E
LIGHT
2.0- 8pin
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
SCL
+5V
IR
IR
+3.3V
IR
ANALOG_VOUT
+3.3V
TVS1
RES
LED2
LED1
LIGHT
3
R18
5.6V
1
VDD
4
C10
4.7uF/6.3V
1
OUT
2
100R
ZD4
Proximity Sensor
U2
R17 10Ω
2
GND
1
CX
ANTENNA
OUT
5
VSSVDDHI
Proximity3
GND
R27
6
CX
2K
VDDHI
C8
1u
4
VREG
IQS127D
C9
104
C7
1u
TSOP75236
HEADER13
+5V
+3.3V
R10
4.7kΩ / 100Ω
+5V
TEMT6200FX01
D1
G1
WHITE
5
VSS
470Ω
2
U3A
1
R26
LIGHT
100R
LM358
R20
R16
22kΩ
R19
47kΩ
ZD3
5.6V
3
4
1
B
R22
LM358
Q3*
BC847
2
B
E
10kΩ
3
R14
C
3
LED2
C
Q2
BC847
E
B
6
1
R13
10kΩ
C
1
10kΩ
2
E
R12
3
LED1
U3B
7
RED
R21
R23
R24
104
ZD5
R25
100kΩ
C11 104
10kΩ
C12
18kΩ
D2
8
RED LED
Q3
BC857
2
+5V
LIGHT Sensor
15kΩ
WHITE LED
R15
47Ω
3.3V
100kΩ
C13 104
Leading Edge Module
8
2010-07-15
9
2010-07-15
2722 171 9026
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110217
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 157
10-18 E 27221719027x IR/LED/Key Board
Leading Edge Module
Leading Edge Module
E
U1
R16
CPS6
+3.3V
VDD
L1
100uH
R2
103
C1
C4
PIC16F1827
IN0 19
IN6 20
IN1 1
IN2 2
IN3 3
MCLR 4
17
18
3.9kΩ
10uF
5
6
104
RA0/AN0/CPS0/C12IN0RB0/SRI/T1G/CCP1(1)/P1A(1)/INT/FLT0
RA1/AN1/CPS1/C12IN1RB1/AN11/CP S11/RX(1)/DT(1)/SDA1/SDI1
RA2/AN2/VREF-/DACOUT/CPS2/C12IN2-/C12IN+
RB2/AN10/CP S10/MDMIN/TX(1)/CK(1)/RX(1)/DT(1)/SDO(1)
RA3/AN3/CPS3/C12IN3-/C1IN+/Vref+/C1OUT/CCP3(2)/SRQ
RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1)/Vcap
RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ
RB4/AN8/CPS8/SCL1/SCK1/MDCIN2
RA5/MCLR/VPP/SS1
RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SS1(1)
RA6/OSC2/CLKOUT/CLKR/P1D(1)/SDO1(1)
RB6/AN5/CPS5/T1OSI/T1CKI/PGC/P1C(1)
RA7/OSC1/CLKIN/P1C(1)
RB7/AN6/CPS6/T1OSO/PGD/P1D(1)/MDCIN1
VSS
VSS
VDD
VDD
7
8
9
10
11
12
13
14
PWM1 R1
SDA
1K
IN4
IN5
PWM2-SCL R27
BUZZER 1K
ICSPCLK
ICSPDAT
16
15
VDD
KEYBOARD
C2
105
C3
105
ZD2
5.6V
VDD
C5
104
CAP
touchsence
J1
NOT USED
TV
CONNECTOR
J7
1
2
3
4
5
6
7
8
2.0-8pin
VDD
IR
IR
LED2
L2
R11 100R
IN5 R3
100uH
LIGHT
IR
3
LED1
KEYBOARD
R18 100R
+5V
ZD4
5.6V
ESD
4
C10
10uF/6.3V
10uF/6.3V
OUT
2
+3.3V
1
C7
105
C8
U2
R17 10Ω
+3.3V
VDD
BUZZER
GND
BUZZER R9
BZ1
C6
104
test VDD
BUZZER
T1
BC847
T3
R15
47Ω/15Ω
+5V
J6
CPS0
G1
5
7
C
BC857
2
R20
BC847
R28
R21
100kΩ
C12
R23
R24
104
LIGHT
R26
100R
4
E
R19
22kΩ
B
B
ZD3
5.6V
1
470Ω
LM358
47kΩ
C
E
B
E
10kΩ
B
U3A
3
LM358
Q4
C
LED2 R14
R22
18kΩ
E
C
6
1
Q2
BC847
U3B
8
LIGHT Sensor
TEMT6200
D1
RED
1
+5V
15kΩ
Red LED
D2
C
1
3.9K
3.9K
R10
4.7kΩ / 100Ω
E
CPS1
IN0 R8
Q3
R13
10kΩ
1
J5
IN1 R7
+5V
B
CPS2
3.9K
+3.3V
2
1
J4
IN2 R6
ICSPCLK
MCLR
10kΩ
CPS3
3.9K
T5
LED1 R12
1
J3
IN3 R5
T2
T4
WHITE
CPS4
3.9K
ICSPDAT
White LED
1
J2
IN4 R4
Q1
1K
GND
CPS5
3.9K
TSOP75236
3
E
ZD1
3.3V
R25
100kΩ
10kΩ
C11 104
C13 104
8
Leading Edge Module
2010-08-23
2722 171 9027
19101_057_110505.eps
110624
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 158
10-19 E 27221719028x IR/LED/Key Board
Leading Edge Module
E
Leading Edge Module
E
3
Leading Edge Module
2010-08-24
2722 171 9028
19101_058_110505.eps
110505
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 159
10-20 E 27221719029x IR/LED/Key Board
Leading Edge Module
Leading Edge Module
E
U1
R16
CPS6
+3.3V
VDD
L1
100uH
C1
C4
R2
103
10uF
R29
1K
104
5
6
KEY2 SCL
C16
ZD5
5.6V
PIC16F1827
IN0 19
IN6 20
IN1 1
IN2 2
IN3 3
MCLR 4
17
18
3.9kΩ
RA0/AN0/CPS0/C12IN0RB0/SRI/T1G/CCP1(1)/P1A(1)/INT/FLT0
RA1/AN1/CPS1/C12IN1RB1/AN11/CP S11/RX(1)/DT(1)/SDA1/SDI1
RA2/AN2/VREF-/DACOUT/CPS2/C12IN2-/C12IN+
RB2/AN10/CP S10/MDMIN/TX(1)/CK(1)/RX(1)/DT(1)/SDO(1)
RA3/AN3/CPS3/C12IN3-/C1IN+/Vref+/C1OUT/CCP3(2)/SRQ
RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1)/Vcap
RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ
RB4/AN8/CPS8/SCL1/SCK1/MDCIN2
RA5/MCLR/VPP/SS1
RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SS1(1)
RA6/OSC2/CLKOUT/CLKR/P1D(1)/SDO1(1)
RB6/AN5/CPS5/T1OSI/T1CKI/PGC/P1C(1)
RA7/OSC1/CLKIN/P1C(1)
RB7/AN6/CPS6/T1OSO/PGD/P1D(1)/MDCIN1
VSS
VSS
VDD
VDD
TV
CONNECTOR
JP1
VDD
C2
105
R30
1K
KEY2 SCL
C14
101
+5V
L2
C7
105
C8
IR
IN5 R3
3
ZD4
5.6V
test VDD
BUZZER
T1
T3
GND
GND
T5
+3.3V
5
7
6
E
1
470Ω
2
R20
R21
100kΩ
C12
R23
R24
104
LIGHT
R26
100R
4
BC847
R28
R19
22kΩ
C
ZD3
5.6V
B
E
B
BC857
U3A
3
LM358
47kΩ
C
E
B
E
10kΩ
B
Q4
C
C
LED2 R14
R22
LM358
1
R13
10kΩ
E
10kΩ
Q2
BC847
U3B
18kΩ
D2
G1
8
LIGHT Sensor
TEMT6200
D1
RED
1
+5V
15kΩ
Red LED
+5V
C
R10
4.7kΩ / 100Ω
B
CPS0
3.9K
R15
47Ω/15Ω
1
J6
IN0 R8
Q3
2
CPS1
3.9K
MCLR
1
J5
IN1 R7
+5V
LED1 R12
CPS2
3.9K
ICSPDAT
1
J4
IN2 R6
T4
TSOP75236
HEADER13
CPS3
3.9K
BC847
1
J3
IN3 R5
T2
1
J2
CPS4
3.9K
ICSPCLK
1
CPS5
IN4 R4
Q1
1K
VDD
4
C10
10uF/6.3V
C6
104
BUZZER R9
OUT
2
+3.3V
ESD
WHITE
ZD2
5.6V
3.9K
BZ1
BUZZER
U2
R17 10Ω
IR
R18 100R
White LED
105
CAP
touchsence
J1
R11 100R
10uF/6.3V
C15
101
LED2
LED1
LIGHT
C3
VDD
100uH
SDA
IR
KEYBOARD
16
15
KEYBOARD
105
VDD
+3.3V
PWM1 R1
SDA
1K
IN4
IN5
PWM2-SCL R27
BUZZER 1K
ICSPCLK
ICSPDAT
C5
104
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
7
8
9
10
11
12
13
14
C17
105
3
E
ZD1
3.3V
R25
100kΩ
10kΩ
C11 104
C13 104
7
Leading Edge Module
2010-08-27
2722 171 9029
19101_059_110505.eps
110505
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 160
10-21 AL1 820400091394
LiteOn 5 LED RGB Master 24V
AL1A
LiteOn 5 LED RGB Master 24V
AL1A
1M83
FB01
+24V
+3V3
CLK-BUFFER
2B11
FB28
1 3B01-1 8
PWM-CLOCK
PWM-CLOCK-BUF
100n
100p
2
BLANK
PWM-CLOCK-BUF
PROG
BLANK
150R
SPI-DATA-RETURN
SPI-DATA-IN
FB15
FB16
4
3B00-4
SPI-CLOCK-BUF
3
LATCH
5
150R
3B00-3
22
25
32
+3V3
6
150R
SPI-CLOCK
28 27
100p
FB13
FB29
7
2B07
3B01-2
2B04
+3V3
2
SPI-CLOCK
PWM-CLOCK
31
24
26
3
1
2
23
3B18
FB35
100p
LATCH
SPI-CSn
100p
FB10
FB11
FB12
1K3
1 3B00-1 8
150R
PROG
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-IN
100p
+3V3
VCC
7
150R
2B06
FB07
FB06
FB05
27
7B26-1
TLC5946RHB
3B00-2
100p
2B05
2B00
150R
2B01
12
13
28
29
XERR
XHALF
XLAT
NC
GND
3B31
+3V3
1K43
42
41
40
SPI-CLOCK-BUF
100n
2B20
37
38
39
EEPROM
SPI-DATA-IN-BUF
8
7B07
M95010-WDW6
5
5
6
2
1
+3V3
Q
S
HOLD
3
7002
LTW-008RGB2
7000
LTW-008RGB2
7001
LTW-008RGB2
2
C
1
4
Φ
D
7003
LTW-008RGB2
7004
LTW-008RGB2
VCC
+3V3
7B06
74LVC1G32GW
7
+3V3
BLUE
5
BLUE
6
5
BLUE
6
5
BLUE
6
5
BLUE
6
5
BLUE
6
GREEN
1
GREEN
2
1
GREEN
2
1
GREEN
2
1
GREEN
2
1
GREEN
2
RED
3
RED
4
3
RED
4
3
RED
4
3
RED
4
3
RED
4
+24V
W
3
DATA-SWITCH
PWM-G4
PWM-R4
PWM-B4
PWM-G3
PWM-R3
PWM-B3
DATA-SWITCH
7B26-2
TLC5946RHB
VIA
34
35
VIA VIA
36
VIA
+3V3
SPI-CSn
PWM-R1
PWM-G1
PWM-B1
PWM-B2
PWM-R2
PWM-G2
GND_HS
30
FH34SRJ-26S-0.5SH(50)
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
OUT
8
9
10
11
12
13
14
15
BLANK
GSCLK
IREF
MODE
SCLK
SIN
SOUT
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
100n
2B03
4
GND
SPI-DATA-RETURN
10K
2 3B51-2 7
1
1
RES
9B01-4
10K
7 3B13-2 2
2
RES
FB50
PWM-B3
9B50-2
7
PWM-B3_C
FB61
PWM-G3_C
FB62
PWM-R3_C
1
8
4
10K
RES
9B50-1
1
GREEN-R
2
RED-R
10K
5
7B51
BC847BW 3
BLUE-R
4 3B51-4 5
7B23-2
BC847BS(COL)
3
10K
1 3B07-1 8
+24V
10K
5 3B50-4 4
FB30
6 3B13-3 3
FB60
2
+24V
PWM-B1
FB51
PWM-G3
RES
9B01-3
+24V
FB41
FB04
FB20
3
2
RES
9B01-2
10K
4
10K
FB40
RES
9B50-3
6
B012
1 3B51-1 8
B011
1
8 3B13-1 1
7B50-2
BC847BS(COL)
3
5
B010
7B25
BC847BW 3
10K
4 3B07-4 5
+24V
10K
7 3B50-2 2
FB31
PWM-R1
PWM-G1
7B50-1
BC847BS(COL)
6
2
7B23-1
BC847BS(COL)
6
10K
3 3B07-3 6
+24V
10K
6 3B50-3 3
+24V
PWM-R3
FB52
FB32
AL 2K11 LiteOn
5 LED RGB 24V Master
8204 000 9139
4
2010-11-15
3
2010-11-04
2
2010-09-23
1
2010-07-12
19111_002_110517.eps
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2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 161
10-22 AL1 820400091574
LiteOn 5 LED 12V 50%
AL1A
LiteOn 5 LED 12V 50%
AL1A
+3V3
2B11
100n
1M83
3
3B00-3
LATCH
2 3B00-2 7
6
150R
22
25
32
3B21
33R
+3V3
FB20
3B18
FB35
XERR
XHALF
XLAT
12
13
28
29
1p0
2B07
1p0
100p
2B04
2B06
150R
BLANK
GSCLK
IREF
MODE
SCLK
SIN
SOUT
NC
GND
FB12
PWM-CLOCK
FB16
SPI-CLOCK
FB15
3B31
+3V3
1K43
42
41
40
37
38
39
SPI-DATA-RETURN
SPI-DATA-IN
+3V3
PWM-G4
PWM-R4
PWM-B4
PWM-G3
PWM-R3
PWM-B3
DATA-SWITCH
7B26-2
TLC5946RHB
34
VIA
35
VIA VIA
36
VIA
+3V3
FB13
PWM-R1
PWM-G1
PWM-B1
PWM-B2
PWM-R2
PWM-G2
GND_HS
30
LATCH
SPI-CSn
FB11
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
OUT
8
9
10
11
12
13
14
15
33
FB10
1K3
31
24
26
3
1
2
23
1u0
PROG
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-IN
SPI-DATA-OUT
PROG
BLANK
FB06
+3V3
8
150R
4 3B00-4 5
150R
TEMP-SENSOR
FB07
VCC
3B00-1
100p
2B05
FB04
FB05
1
BLANK
PWM-CLOCK-BUF
+12V
2B12
FB01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
7B26-1
TLC5946RHB
28 27
FH34SRJ-26S-0.5SH(50)
+3V3
+3V3
1
4
W
3
2
1K5 1%
+3V3
5
3B40
3B39
FB41
100n
HOLD
7
9B10
7B30
150R
3B41
S
PWM-CLOCK-BUF
+3V3
1K5 1%
6
1
33R
C
FB28
1K5 1%
1 3B30-1 8
2B09
3
3
+3V3
PWM-CLOCK
2 3B01-2 7
33p
1
4
2
2B02
DATA-SWITCH
2
Q
100K RES
2
1
Φ
33p
SPI-CSn
6
5
7B06
74LVC1G32GW
D
VCC
2B00
5
7B20-1
74LVC2G17
8
7B07
M95010-WDW6
+3V3
100n
3B34
+3V3
+3V3
5
SPI-CLOCK-BUF
100n
2B17
SPI-DATA-IN-BUF
2B08
TEMP SENSOR
CLK-BUFFER
100n
2B20
EEPROM
LMV331IDCK
6B10
TEMP-SENSOR
BAT54 COL
FB40
3B01-4
5
3
4
3
33R
3B30-3
6
FB29
2B10
3B05
2
7002
LTW-008RGB2-PH1
7001
LTW-008RGB2-PH1
22R
PWM-B1
5
BLUE
6
cb01
5
BLUE
6
5
BLUE
PWM-G1
1
GREEN
2
9B01
1
GREEN
2
1
GREEN
2
PWM-R1
3
RED
4
3
RED
4
3
RED
4
+12V
2B03
3 3B03-3 6
6
220R
2 3B03-2 7
100n
33p
2B01
3B35
7000
LTW-008RGB2-PH1
SPI-CLOCK-BUF
150R
100n
4
2B13
SPI-CLOCK
33R
33p
3B22
SPI-DATA-RETURN
10K
5
3B11
7B20-2
74LVC2G17
+3V3
-T 10K
4
RES
GND
220R
FB30
FB31
FB32
FB50
FB51
FB52
FB60
FB61
FB62
B010
B011
B012
AL 2K11 LiteOn
5 LED 12V 50%
8204 000 9157
3
2010-12-02
2
2010-10-05
1
2010-07-15
19050_008_110418.eps
110418
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 162
LiteOn 5 LED 12V 50%
AL1B
LiteOn 5 LED 12V 50%
AL1B
7100
LTW-008RGB2-PH1
7101
LTW-008RGB2-PH1
PWM-B2
5
BLUE
6
5
BLUE
6
PWM-B2-R
PWM-G2
1
GREEN
2
1
GREEN
2
PWM-G2-R
PWM-R2
3
RED
4
3
RED
4
PWM-R2-R
AL 2K11 LiteOn
5 LED 12V 50%
8204 000 9157
4
2011-01-21
3
2010-12-02
2
2010-10-05
1
2010-07-15
19050_009_110418.eps
110418
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 163
10-23 AL3 820400091353
LiteOn 1 LED RGB Master 24V
AL3A
LiteOn 1 LED RGB Master 24V
AL3A
7005
LTW-008RGB2
1 3C01-1 8
BLUE
220R
2 3C01-2 7
3C02
220R
13R
1 3C03-1 8
5
BLUE
6
1
GREEN
2
3
RED
4
GREEN
RED
1K0
BLUE-R
2 3C03-2 7
GREEN-R
3
1K0
3C03-3
6
1K0
4 3C03-4 5
RED-R
1K0
1M85
FH34SRJ-18S-0.5SH(50)
PWM-G3_C
PWM-R3_C
PWM-B3_C
+24V
B013
FC12
19 20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AL 2K11 LiteOn
1 LED 24V
8204 000 9135
3
2010-11-22
2
2010-09-29
1
2010-07-12
19111_003_110517.eps
110517
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 164
10-24 AL3 820400091373
LiteOn 4 LED RGB Master 24V
AL3A
LiteOn 4 LED RGB Master 24V
AL3A
+24V
2K0
3C21-2
2K0
FC50
PWM-R4-C
1M85
1 3C03-1 8
2K0
470R
3K0
4 3C01-4 5
3 3C02-3 6
2 3C03-2 7
2K0
470R
3C02-4
GREEN-R
3
3K0
3C03-3
6
4 3C03-4 5
RED-R
10K
PWM-R3_C
PWM-B3_C
+24V
3K0
470R
PWM-B4-C
PWM-G3_C
FC16
PWM-R4
RED
7C06
BC847BW 3
FC51
PWM-G4-C
+24V
1
3K0
2 3C04-2 7
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FH34SRJ-18S-0.5SH(50)
FC17
PWM-G4
3K0
10K
1 3C04-1 8
2
8 3C16-1 1
3K0
19
470R
2 3C02-2 7
PWM-G4-C
PWM-R4-C
RES
9C00-1
2K0
3 3C01-3 6
GREEN
10K
1 3C02-1 8
1
8 3C15-1 1
2K0
2 3C01-2 7
7 3C16-2 2
BLUE
RES
9C00-2
2
1 3C01-1 8
BLUE-R
7C05-1
BC847BS(COL)
6
10K
7 3C15-2 2
3C21-1
3 3C04-3 6
+24V
3K0
3K0
7C05-2
BC847BS(COL)
3
10K
6 3C15-3 3
4 3C04-4 5
FC52
PWM-B4-C
RES
10K
4
9C00-4
6 3C16-3 3
5
FC18
PWM-B4
+24V
7
4K3
2
10K
4K3
4 3C07-4 5
RES
9C01-4
4K3
1 3C08-1 8
1 3C17-1 8
1K0
2 3C08-2 7
4K3
1K0
3K6
2 3C17-2 7
3 3C08-3 6
2 3C09-2 7
FC10
PWM-B2
+24V
8
10K
7C02
BC847BW 3
RES
9C01-2
2
10K
7103
LTW-008RGB2
BLUE
6
5
BLUE
6
4K3
1K0
3K6
5
BLUE
6
5
BLUE
6
GREEN
2
1
GREEN
2
3 3C17-3 6
4 3C08-4 5
3 3C09-3 6
1
GREEN
2
1
GREEN
2
3
RED
4
3
RED
4
4K3
3C17-4
1K0
3K6
3C09-4
3
RED
4
3
RED
4
4
5
4
4K3
3C10-1
+24V
5
3K6
1
8
3K6
FC11
PWM-G2
7102
LTW-008RGB2
1
1
3C06-1
8
1
1 3C09-1 8
5
1
3C05-1
7101
LTW-008RGB2
7100
LTW-008RGB2
100n
7
3 3C07-3 6
1
2
3C06-2
4K3
3C07-2
2C01
10K
2
2
3C05-2
7
1 3C07-1 8
7C01-1
BC847BS(COL)
6
2 3C10-2 7
+24V
3K6
10K
7C01-2
BC847BS(COL)
3
4 3C10-4 5
4
3C05-4
5
3K6
3 3C10-3 6
5
10K
4
3C06-4
4
RES
9C01-1
3K6
5
PWM-R2
FC12
B013
B014
FC20
AL 2K11 LiteOn
4 LED 24V Master
8204 000 9137
3
2010-11-15
2
2010-11-04
1
2010-09-28
19111_004_110517.eps
110517
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 165
10-25 AL3 820400091413
LiteOn 7 LED RGB Master 24V
LiteOn 7 LED RGB Master 24V
AL3A
+24V
7C05-1
BC847BS(COL)
6
10K
7 3C15-2 2
AL3A
FC50
PWM-R4-C
2
1M85
6
7005
LTW-008RGB2
2
RED
4
GREEN
RES
9C00-3
3
7C06
BC847BW 3
FC51
PWM-G4-C
+24V
1
4
GREEN
3
8 3C16-1 1
RED
RED-R
3C03-1
19
FC17
PWM-G4
1K0
20
FH34SRJ-18S-0.5SH(50)
5
1K0
3C03-2
RES
1
9C00-4
6
10K
BLUE
2
13R
PWM-B4-C
PWM-G3_C
PWM-R3_C
PWM-B3_C
10K
GREEN-R
5
8 3C15-1 1
BLUE
3C02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PWM-G4-C
PWM-R4-C
+24V
220R
BLUE-R
FC16
PWM-R4
220R
3C01-4
10K
7 3C16-2 2
3C01-3
1
3C03-3
6 3C15-3 3
1K0
10K
+24V
1K0
3C03-4
7C05-2
BC847BS(COL)
3
FC52
PWM-B4-C
RES
9C00-1 8
4
1
10K
6 3C16-3 3
5
FC18
PWM-B4
+24V
10K
2 3C05-2 7
1 3C07-1 8
220R
7C01-1
BC847BS(COL)
6
1
RES
9C01-2
10K
2 3C06-2 7
2
4 3C07-4 5
2
7
220R
FC10
PWM-B2
1 3C09-1 8
+24V
7101
LTW-008RGB2
7100
LTW-008RGB2
7104
LTW-008RGB2
7103
LTW-008RGB2
7102
LTW-008RGB2
1K0
7105
LTW-008RGB2
5
BLUE
6
GREEN
2
1
GREEN
2
RED
4
3
RED
4
RES
9C01-1
BLUE
3 3C09-3 6
1
GREEN
13R
1K0
3C09-4
3
RED
1K0
8
1
3
+24V
5
3C12
4
5
BLUE
6
2
1
GREEN
4
3
RED
6
5
BLUE
2
1
4
3
6
5
BLUE
GREEN
2
1
GREEN
2
RED
4
3
RED
4
6
5
1K0
100n
6
1
10K
2
1
1 3C06-1 8
BLUE
2C01
5
7C02
BC847BW 3
10K
1 3C05-1 8
2 3C09-2 7
FC11
PWM-G2
7C01-2
BC847BS(COL)
3
PWM-R2
5
4
B013
B014
B015
B016
FC20
FC21
4
10K
4 3C06-4 5
5
RES
9C01-4
10K
4 3C05-4 5
+24V
FC12
AL 2K11 LiteOn
7 LED 24V Master
8204 000 9141
3
2010-11-22
2
2010-09-23
1
2010-07-02
19111_005_110517.eps
110517
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 166
10-26 AL3 820400091583
LiteOn 4 LED 12V 50%
AL3A
LiteOn 4 LED 12V 50%
AL3A
1M84
SPI-CLOCK
PWM-B4
SPI-DATA-OUT
SPI-DATA-RETURN
PWM-G4
+3V3
PWM-CLOCK
PWM-R4
SPI-CSn
LATCH
+3V3
BLANK
PROG
TEMP-SENSOR
+12V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FH34SRJ-26S-0.5SH(50)
B013
B014
FC10
FC20
FC11
FC50
FC12
FC51
FC52
AL 2K11 LiteOn
4 LED 12V 50%
8204 000 9158
3
2010-12-02
2
2010-10-05
1
2010-07-15
19050_010_110418.eps
110418
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 167
LiteOn 4 LED 12V 50%
AL3B
LiteOn 4 LED 12V 50%
AL3B
7201
LTW-008RGB2-PH1
3C11
7200
LTW-008RGB2-PH1
7202
LTW-008RGB2-PH1
22R
6
6
cc10
5
BLUE
6
5
BLUE
GREEN
2
9C10
1
GREEN
2
1
GREEN
2
PWM-R3
3
RED
4
3
RED
4
3
RED
4
1 3C13-1 8
+12V
2C10
220R
2 3C13-2 7
100n
BLUE
1
100n
5
2C11
PWM-B3
PWM-G3
220R
AL 2K11 LiteOn
4 LED 12V 50%
8204 000 9158
3
2010-12-02
2
2010-10-05
1
2010-07-15
19050_011_110418.eps
110418
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 168
LiteOn 4 LED 12V 50%
LiteOn 4 LED 12V 50%
AL3C
3C31
7102
LTW-008RGB2-PH1
PWM-B2-R
cc30
5
BLUE
PWM-G2-R
9C30
1
GREEN
2
3
RED
4
220R
2 3C33-2 7
+12V
100n
1 3C33-1 8
2C31
PWM-R2-R
6
100n
22R
2C30
AL3C
220R
AL 2K11 LiteOn
4 LED 12V 50%
8204 000 9158
3
2010-12-02
2
2010-10-05
1
2010-07-15
19050_012_110418.eps
110418
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 169
10-27 AL3 820400091592
LiteOn 7 LED 12V 50%
LiteOn 7 LED 12V 50%
AL3A
7301
LTW-008RGB2-PH1
3C03
BLUE
6
PWM-G4
1
GREEN
2
PWM-R4
3
RED
4
22R
9C04
cc04
1
3C01-1
5
BLUE
6
5
BLUE
6
1
GREEN
2
1
GREEN
2
3
RED
4
3
RED
4
+12V
100n
5
1M84
SPI-CLOCK
100n
PWM-B4
7302
LTW-008RGB2-PH1
2C02
7300
LTW-008RGB2-PH1
2C01
AL3A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SPI-DATA-OUT
SPI-DATA-RETURN
+3V3
PWM-CLOCK
SPI-CSn
LATCH
8
+3V3
220R
BLANK
PROG
2 3C01-2 7
220R
TEMP-SENSOR
+12V
27
28
FH34SRJ-26S-0.5SH(50)
B013
B014
B015
B016
FC10
FC20
FC11
FC21
FC12
AL 2K11 LiteOn
7 LED 12V 50%
2
2010-12-02
1
2010-10-07
8204 000 9159
19101_054_110505.eps
110505
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 170
LiteOn 7 LED 12V 50%
AL3B
LiteOn 7 LED 12V 50%
AL3B
7200
LTW-008RGB2-PH1
PWM-B3
5
BLUE
7201
LTW-008RGB2-PH1
3C14
6
22R
7202
LTW-008RGB2-PH1
5
BLUE
6
5
BLUE
6
1
GREEN
2
1
GREEN
2
3
RED
4
3
RED
4
9C12
PWM-G3
1
GREEN
2
PWM-R3
3
RED
4
+12V
100n
2C10
220R
4 3C13-4 5
100n
2C04
cc12
3 3C13-3 6
220R
AL 2K11 LiteOn
7 LED 12V 50%
2
2010-12-02
1
2010-10-07
8204 000 9159
19101_055_110505.eps
110505
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 171
LiteOn 7 LED 12V 50%
LiteOn 7 LED 12V 50%
AL3C
7102
LTW-008RGB2-PH1
9C32
cc32
PWM-G2-R
PWM-R2-R
3 3C33-3 6
BLUE
6
1
GREEN
2
3
RED
4
+12V
2C30
220R
5
4 3C33-4 5
100n
22R
PWM-B2-R
2C05
3C15
100n
AL3C
220R
FC17
FC50
FC18
FC51
FC16
FC52
AL 2K11 LiteOn
7 LED 12V 50%
2
2010-12-02
1
2010-10-07
8204 000 9159
19101_056_110505.eps
110505
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 172
10-28 AL 310431364803 AmbiLight Layout
9 LED 50% 12 V LiteOn
FB04
FB13
FB61
FB11
FC12
FC11
7201
FC51
FC50
3C13
FC16
FC17
7202
FC20
1M84
2C31
7200
2C10
7102
B014
FB50
FC52
3C33
FB52
cc10
9C10
cc30
9C30
FB62
FB51
FB30
FB31
3C11
FB20
3C31
7101
FB32
3B21
FC18
FB35
FC10
7B26
FB60
7100
3B18
2B11
2C11
2B06
2B07
2B04
2B05
B013
FB29
2C30
7B06
3B22
B012
FB28
B011
2B102B02
2B13
7B07
FB05
7002
3B31
2B20
FB10
2B03
2B12
2B17
7B20
2B01
3B00
FB16
FB15
FB01
3B01
3B11
2B08
2B00
FB12
7B30
3B30
FB07
FB06
2B09
3B34
Cb01
9B01
7001
1M83
3B05
FB41
FB40
3B03
3B39
7000
3B35
B010
Layout Top
Layout Bottom
AL 2K11 LITEON
9 LED 50%
3
2010-12-02
2
2010-10-05
3104 313 6480
19050_069_110506.eps
110506
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 173
10-29 AL 310431364812 AmbiLight Layout
12 LED 50% 12 V LiteOn
Layout Bottom
FB61
FB11
FC12
FC10
FC11
7200
7201
FC18
FC51
FC50
FC16
FC17
FC52
3C13
7202
FC20
7300
FC21
7301
3C01
1M84
7302
2C02
3C33
3C03
7102
FB62
2C01
FB13
B016
FB04
9C04
Cc04
FB60
FB51
FB50
9C12
cc12
FB30
FB31
B015
FB20
3C14
7101
FB32
3B21
9C32
cc32
FB35
2C05
7B26
2C30
7100
3B18
2B11
3C15
2B06
2B07
2B04
2B05
2C04
FB29
FB52
7B06
FB01
3B22
2C10
FB28
B014
2B01
2B102B02
2B13
7B07
FB05
7002
3B31
2B20
FB10
2B03
2B00
2B12
2B17
7B20
B013
FB15
B012
FB16
B011
2B08
3B00
2B09
3B11
3B01
FB06
7B30
3B30
FB07
FB12
3B34
Cb01
9B01
7001
1M83
3B05
FB41
FB40
3B03
Layout Top
3B39
7000
3B35
B010
Layout Top
Layout Bottom
AL 2K11 LITEON
12 LED 50%
2
2010-12-02
1
2010-10-05
3104 313 6481
19050_070_110506.eps
110506
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 174
10-30 AL 310431364833 AmbiLight Layout
FB31
FB62
9B50
FB50
FB04
FB13
FB61
FB11
1M85
3C02
3C03
FB52
7005
3C01
FB60
3B51
3B50
7B50
FB51
7B51
B013
FB20
9B01
7B26
7B23
7004
FB32
7B25
FB30
3B18
2B07
2B06
FB29
3B07
B012
FB28
2B11
2B05
FB05
7003
FB35
3B13
3B31
FB15
B011
1M83
7B07
2B01
2B20
7002
2B04
FB10
FB01
FB06
2B00
FB07
FB12
3B01
3B00
7001
7B06
FB41
FB40
FB16
2B03
7000
B010
6 LED 24V LiteOn ECO RGB Master
FC12
3
AL 2K11 ECO RGB M
6LED 24V LITEON
2011-05-17
3104 313 6483
19110_057_110517.eps
110517
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 175
10-31 AL 310431364853 AmbiLight Layout
FB61
FB11
FC12
7101
3C08
3C09
FC50
7C05
FC16
3C10
FC17
3C07 3C17
FC51
7C06
7102
FC52
FC10
FC11
3C15
3C01 3C21
B014
FB13
9C00
FB04
7C02
3B51
3B50
FB50
3C16
9B50
3C03 3C04
9C01
FB52
FC18
7100
3C02
FB51
7B50
FB62
7B51
3C05
FB31
FB60
3C06
FB20
FB30
B013
7004
FB32
7B25
7B23
9B01
3B18
2B11
2B07
2B06 2B05
3B07
FB35
7C01
FB28
FB29
7003
7B26
3B13
FB05
7002
FB01
B012
FB16
7B07
B011
1M83
3B31
FB15
2B04
FB10
2B00
FB06
2B20
2B01
FB07
FB12
3B01
7001
3B00
FB41
FB40
7B06
2B03
7000
B010
9 LED 24V LiteOn ECO RGB Master
7103
FC20
1M85
2C01
3
AL 2K11 ECO RGB M
9LED 24V LITEON
2011-05-17
3104 313 6485
19110_059_110517.eps
110517
2011-Jul-15 back to
div. table
Circuit Diagrams and PWB Layouts
Q552.2L LA
10.
EN 176
10-32 AL 310431364873 AmbiLight Layout
3C12
7100
FC18
7C05
FC16
3C09
7101
3C07
FC17
FC52
FC51
7C06
7102
FC20
7103
7104
1M85
B016
FC11
FC21
FC10
FC50
9C01
B015
3C03
FC12
B014
FB11
3C15
3C01
FB61
9C00
FB13
3C16
FB04
B013
FB50
7C02
7B51
FB52
9B50
7005
FB62
3C02
FB60
3B51
3B50
9B01
FB30
FB31
3C05
FB20
3C06
7004
FB32
7B25
7B23
FB51
3B07
FB35
7B50
7003
7B26
7C01
FB29
3B18
2B11
7002
FB01
B012
FB28
3B13
FB05
2B07
7B07
2B06 2B05
2B04
FB10
B011
FB15
2B00
FB06
2B20
3B31
FB16
3B01
FB07
FB12
1M83
2B01
7001
3B00
FB41
FB40
7B06
2B03
7000
B010
12 LED 24V LiteOn ECO RGB Master
7105
2C01
3
AL 2K11 ECO RGB M
12LED 24V LITEON
2011-05-17
3104 313 6487
19110_061_110517.eps
110517
2011-Jul-15 back to
div. table
Styling Sheets
Q552.2L LA
11.
EN 177
11. Styling Sheets
11-1 Blockbuster/Emmy 32"
BLOCKBUSTER / EMMY 32"
1150
5213
5216
0011
1005
5216
0260
Pos No.
0029
8308
1004
1108
0004
0004
0011
0029
0260
1004
1005
1085
1108
1150
1161
1162
5213
5216
8191
8308
8G50
8G51
Description
Front Cabinet
Back Cover
Hard Switch bracket
Stand
Display panel
Power Supply Unit
Remote Control
Keyboard + IR assy
Board SSB
AmbiLight
AmbiLight
Loudspeaker box
Tweeter
Mainscord 1.8m
Main (power) switch
Cable LVDS FFC
Cable LVDS FFC
Remarks
Not displayed
Not displayed
Not displayed
Not displayed
Not displayed
Not displayed
19110_049_110420.eps
110420
2011-Jul-15 back to
div. table
Styling Sheets
Q552.2L LA
11.
EN 178
11-2 Blockbuster/Emmy 40" - 46"
BLOCKBUSTER / EMMY 40"- 46"
1150
1005
5216
0011
5213
0260
5216
0040
1004
1108
0004
8308
POS. NO.
0004
0011
0040
0260
1004
1005
1085
1108
1150
1161
1162
5213
5216
8191
8308
8G50
8G51
DESCRIPTION.
Front Cabinet
Back Cover
Hard Switch bracket
Stand
Display panel
Power Supply Unit
Remote Control
Keyboard + IR assy
Board SSB
AmbiLight
AmbiLight
Loudspeaker box
Tweeter
Mainscord 1.8m
Main (power) switch with cable
Cable LVDS FFC
Cable LVDS FFC
REMARKS
Not Displayed
Not Displayed
Not Displayed
Not Displayed
Not Displayed
Not Displayed
19110_050_110420.eps
110420
2011-Jul-15 back to
div. table
Styling Sheets
Q552.2L LA
11.
EN 179
11-3 Sundance 42" - 47"
SUNDANCE 42" - 47"
1150
1005
0050
0051
1163
0035
5217
0011
0050
5213
0051
0050
0257
0258
1163
Pos No.
8308
0029
1004
0004
1108
5216
0004
0011
0029
0035
0050
0051
0257
0258
0270
1004
1005
1027
1085
1108
1150
1163
5213
5216
5217
8191
8308
8G50
8G51
Description
Front Cabinet
Back Cover
Main Switch Bracket
Swivel bracket
Ambilight Clip
Ambilight Clip
Stand neck
Stand base
3D glasses
Display panel
Power Supply Unit
Temperature sensor board
Remote control
Keyboard assy (touch control)
Board SSB
Ambilight module
Loudspeaker box
Tweeter
Tweeter
Mainscord
Main Switch with cable
LVDS (FFC) Cable
LVDS (FFC) Cable
Remarks
42”
47”
Not displayed
Not displayed
Not displayed
Not displayed
Not displayed
19110_064_110711.eps
110711
2011-Jul-15 back to
div. table
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