Renesas | H8S/2668 Series | Limitation on Using the H8S/2678, 2678R, 2668, 2368, and 2378

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date: 2002/07/15
HITACHI SEMICONDUCTOR TECHNICAL UPDATE
Classification
of Production
No
Development environment
Limitation on Using the H8S/2678,
2678R, 2668, 2368, and 2378
E6000 Emulator
THEME
Classification
of
Information
1.
2.
3.
TN-EML-093A/E
Spec change
Supplement of Documents
Limitation of Use
HS2678REPI61H
See
below.
4.
5.
1
Change of Mask
Change of
Production Line
Effective Date
Lot No.
PRODUCT
NAME
Rev.
Reference
Documents
H8S Series E6000 Emulator
ADE-702-194B
Permanent
In the H8S/2678, 2678R, 2668, 2368, and 2378 series E6000 emulator HS2678REPI61H, there are following limitations.
These limitations apply to emulation of the H8S/2368 and H8S/2378 series microcomputer, and not to emulation of the
H8S/2678, H8S/2678R, and H8S/2668 series microcomputer.
If you need to modify the emulator, contact Hitachi’s sales agency.
1. Target Product Revisions (For details, refer to the following pages.)
No.
(1)
(2)
(3)
Limitation
IIC bus interface 1
Port 9
IIC bus interface 2
Emulator Revision
A
A
A and B
Microcomputer
H8S/2378, 2368 series
H8S/2378 series
H8S/2378, 2368 series
The product revision is written on the label on the back of the emulator station.
MODEL HS2678REPI61H
SERIAL No. XXXXA
DC 5V 5.0A
HITACHI MADE IN JAPAN
1/1
Revision A
2. Limitations
2-1 IIC Bus Interface 1
(1) Limitation on issuing the halt condition
When there is a slave device that inserts a wait by driving SCL at the low level, issue the halt condition after the
slave device has released SCL. The halt condition is not correctly issued during the low period of SCL.
9th clock
Slave device is
driven at low
Slave device
releases SCL
SCL
SDA
Issue the halt condition
Figure 2-1 Timing for Issuing the Halt Condition
(2) Limitation on automatically switching the slave transmit mode
In slave transmit mode, set the ACKE bit (to test and select the acknowledge bit) to 1 after the falling edge of
the ninth clock where the slave address has been matched.
Slave transmission
Slave reception
9th clock
SCL
SDA
Bit 7
TDRE
ACKE
Set 1 to ACKE
Figure 2-2 Timing for Setting ACKE
Bit 6
(3) Initial value of the ACKBR bit
Device specification
Emulator specification
Initial Value of the ACKBR Bit in
ICIER
0
1
Notes
This bit is read-only.
(4) Clear condition of the IIC bus status register (ICSR)
The clear conditions for the TDRE, TEND, and RDRF flags differ.
Device specification
Bit
Bit Name
7
TDRE: transmit data register empty
6
TEND: transmit end
5
RDRF: receive data register full
Emulator specification
Bit
Bit Name
7
TDRE: transmit data register empty
6
TEND: transmit end
5
RDRF: receive data register full
Clear Condition
• When 1 is read and 0 is written
• When the data is written in ICDRT
• When 1 is read and 0 is written
• When the data is written in ICDRR
Clear Condition
When 1 is read and 0 is written
2-2 PORT9 Register (H’FF58)
Device specification
Emulator specification
Reads the PORT9 register.
Reads the pin state.
Reads the undefined value.
2-3 IIC Bus Interface 2
When a program is created by using the flowchart described in the H8S/2378 hardware manual, in the master transmit
mode of the IIC bus format, the previous value of the MSB for the transmit data will be retained (see figure 2-3).
To prevent such state, as shown in figure 2-4, transmission must be performed in each byte. Before the transmit data
is written in ICDRT, test SCLO in ICCR2 and check that SCL outputs low level.
Write 1 to BBSY
and 0 to SCP
Write transmit data
in ICDRT
Write transmit data
in ICDRT
SCL
1
2
SDA
Bit 7
Bit 6
8
Bit 0
9
ACK
1
2
Bit 7
Bit 6
TDRE
The previous value of the MSB
(bit 7) will be retained.
Figure 2-3 Timing when Retaining the Previous Value of MSB in the Transmit Data
Start
[1] Test the status of the SCL and SDA lines.
Initialize
[2] Set master transmit mode.
Read BBSY in ICCR2
No
[3] Issue the start condition.
[1]
BBSY=0?
Yes
Set MST and TRS in
ICCR1 to 1
[2]
Write 1 to BBSY
and 0 to SCP
[3]
[4] Wait for the SCL=0 output.
[5] Set the first byte (slave address + R/W) of
transmit data.
[6] Wait for 1 byte to be transmitted.
[7] Clear the TEND flag.
Read SCLO in ICCR2
No
[8] Test the acknowledge transferred from the
specified slave device.
[4]
SCLO=0?
[9] Wait for the SCL=0 output.
Yes
Write transmit data
in ICDRT
[5]
[10] Set the second and subsequent bytes of transmit
data.
Read TEND in ICSR
No
[11] Wait for the completion of transmission.
[6]
TEND= 1?
Yes
Clear TEND in ICSR
[12] Clear the TEND flag.
[13] Test the acknowledge.
[7]
[14] Test the last byte.
Read ACKBR in ICIER
No
ACKBR=0?
[8]
[15] Clear the STOP flag.
[16] Issue the stop condition.
Yes
Transmit
mode?
Yes
No
Mater receive mode
[18] Set slave receive mode.
Read SCLO in ICCR2
No
[17] Wait for the creation of stop condition.
[19] Clear the TDRE flag.
[9]
SCLO=0?
Yes
Write transmit data
in ICDRT
[10]
A
Read TEND in ICSR
No
Clear STOP in ICSR
[11]
TEND=1 ?
Yes
Clear TEND in ICSR
[12]
Read ACKBR in ICIER
ACKBR=0?
No
[13]
Last byte?
Yes
A
[17]
STOP=1?
Yes
Set MST and TRS
in ICCR1 to 0
[14]
[16]
Read STOP in ICSR
No
Yes
No
Write 0 to BBSY
and SCP
[15]
Clear TDRE in ICSR
End
Figure 2-4 Sample Flowchart for Master Transmit Mode
[18]
[19]
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