st7565r

st7565r

ST

Sitronix

ST7565R

65 x 132 Dot Matrix LCD Controller/Driver

F e a t t u r r e s

l Directly display RAM data through Display Data RAM. l RAM capacity : 65 x 132 = 8580 bits l Display duty selectable by select pin

1/65 duty : 65 common x 132 segment

1/49 duty : 49 common x 132 segment

1/33 duty : 33 common x 132 segment

1/55 duty : 55 common x 132 segment

1/53 duty : 53 common x 132 segment l High-speed 8-bit MPU interface:

ST7565R can be connected directly to both the 80x86 series MPUs and the 6800 series MPUs.

Serial interface (SPI-4) is also supported. l Abundant command functions

Display data Read/Write, display ON/OFF, Normal/

Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction selects, power saver, static indicator, common output status select, V

0

voltage regulation internal resistor ratio set. l Static drive circuit equipped internally for indicators.

(1 system, with variable flashing speed.) l Embedded analog power supply circuits for Liquid

Crystal driving: Booster, Regulator and Follower. l Embedded Booster circuit:

2X,3X,4X,5X and 6X boost ratios are supported.

Independent input (V

DD2

) for boost reference voltage. l High-accuracy Regulator circuit:

Build-in Electronic volume function for the contrast control. Thermal gradient = –0.05%/°C. l Embedded voltage Follower circuit for LCD driving. l Embedded R-C oscillator circuit.

The external clock is also supported. l Extremely low power consumption: 60uA, bare dice

(using the internal power). Settings:

V

DD

– V

SS

= V

DD2

– V

SS

=3.0 V, Booster Ratio=4,

V

0

– V

SS

= 11.0 V. Display OFF and the normal mode is selected. l

Logic power supply : V

DD

– V

DD2

– V

SS

= 2.4V to 3.3V

SS

= 1.8V to 3.3 V

Analog Power (Boost reference voltage):

V

Booster maximum voltage limited

V

OUT

= 13.5V

Liquid crystal drive power supply:

V

0

– V

SS

= 3.0V to 12.0 V l Wide range of operating temperatures: –30 to 85°C l Package type: COG only. l The chip is not designed to resist the light or to resist the radiation.

G e n e r r a l l

D e s c r r i i p t t i i o n

The ST7565R is a single-chip dot matrix LCD driver that can be connected directly to a microprocessor bus. 8-bit parallel or 4-line SPI display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7565R contain

65x132 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom.

The ST7565R chips contain 65 common output circuits and

132 segment output circuits, so that a single chip can drive a

PART NO.

65x132 dot display (capable of displaying 8 columns x4 rows of a 16x16 dot kanji font).

Moreover, the capacity of the display can be extended through the use of master/slave structures between chips.

The chips are able to minimize power consumption because no external operating clock is necessary for the display data

RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, resistors for LCD driver power voltage adjustment and a display clock CR oscillator circuit, the ST7565R can be used to create the lowest power display system with the fewest components for high-performance portable devices.

V

RS

temperature gradient V

RS range

ST7565R -0.05%/°C

2.1V ±0.03V

Ver 1.5 1/72 2006/03/10

ST7565R

S T 7 5 6 5 R P a d A r r r r a n g e m e n t t

(

( C

O

G

)

)

Chip Size:

Bump Pitch:

Bump Size:

5900μm x 1000μm

34μm(Min.)

PAD No. 001〜067

PAD No. 068〜073

PAD No. 074〜084

PAD No. 085〜282

Bump Height: 15μm

Chip Thickness: 480μm

42μm x 54μm

56μm x 54μm

42μm x 54μm

17μm x 118μm

Ver 1.5 2/72 2006/03/10

ST7565R

P a d C e n t t e r r C o o r r d i i n a t t e s

(

( 1 /

/

6 5

D u t t y

)

)

PAD No. PIN Name

32

33

34

35

36

28

29

30

31

23

24

25

26

27

19

20

21

22

41

42

43

44

37

38

39

40

45

46

47

48

5

6

7

8

9

1

2

3

4

FRS

FR

CL

DOF

VSS

CS1B

CS2

VDD

RST

14

15

16

17

18

10

11

A0

VSS

12 /WR(R/W)

13 /RD(E)

VDD

D0

D1

D2

D3

CAP3P

CAP1N

CAP1N

CAP1P

CAP1P

CAP2P

CAP2P

CAP2N

CAP2N

CAP4P

CAP4P

VSS

VSS

VSS

VOUT

VOUT

CAP5P

CAP5P

CAP1N

CAP1N

CAP3P

D4

D5

D6

D7

VDD

VDD2

VDD2

VSS

VSS

X

955

895

821

761

701

641

581

521

461

1495

1435

1375

1315

1255

1195

1135

1075

1015

401

341

281

221

161

101

41

-19

-79

-139

-199

-273

2035

1975

1915

1855

1795

1735

1675

1615

1555

2575

2515

2455

2395

2335

2275

2215

2155

2095

Y

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

PAD No. PIN Name

80

81

82

83

84

76

77

78

79

71

72

73

74

75

67

68

69

70

89

90

91

92

85

86

87

88

93

94

95

96

62

63

64

65

66

58

59

60

61

53

54

55

56

57

49

50

51

52

X Y

CLS

C86

PSB

HPMB

IRS

SEL1

SEL2

SEL3

VSS

VDD2

TEST[0]

TEST[1]

TEST[2]

TEST[3]

TEST[4]

TEST[5]

VDD

MS

V2

V2

V1

V1

V

0

V

0

VR

VR

VDD

VSS

VRS

VRS

VDD2

VDD

V4

V4

V3

V3

-333

-408

-468

-542

-602

-676

-736

-796

-856

-916

-976

392

392

-1036 392

-1096 392

-1156 392

-1216 392

-1276 392

-1336 392

-1410 392

-1470

-1537

-1611

-1685

-1759

-1833

-1907

-1974

-2034

-2574

COM[31] -2810 373

COM[30] -2810 339

COM[29] -2810 305

COM[28] -2810 271

COM[27] -2810 237

COM[26] -2810 203

COM[25] -2810 169

COM[24] -2810 135

COM[23] -2810 101

COM[22] -2810 67

COM[21] -2810

COM[20] -2810

33

-1

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

-2094 392

-2154 392

-2214 392

-2274 392

-2334 392

-2394 392

-2454 392

-2514 392

392

Units: μm

Ver 1.5 3/72 2006/03/10

ST7565R

119

120

121

122

123

124

125

126

127

110

111

112

113

114

115

116

117

118

PAD No. PIN Name

97 COM[19]

X

-2810

98

99

COM[18]

COM[17]

-2810

-2810

Y

-35

-69

-103

100 COM[16] -2810 -137

101 COM[15] -2810 -171

102 COM[14] -2810 -205

103 COM[13] -2810 -239

104 COM[12] -2810 -273

105 COM[11] -2810 -307

106 COM[10] -2810 -341

107

108

109

COM[9]

COM[8]

COM[7]

-2810

-2573

-2539

-375

-360

-360

COM[6]

COM[5]

COM[4]

COM[3]

COM[2]

COM[1]

COM[0]

COMS2

SEG[0]

SEG[1]

SEG[2]

SEG[3]

SEG[4]

SEG[5]

SEG[6]

SEG[7]

SEG[8]

SEG[9]

-2505

-2471

-2437

-2403

-2369

-2335

-2301

-2267

-2227

-2057

-360

-360

-360

-360

-360

-360

-360

-360

-360

-2193 -360

-2159 -360

-2125 -360

-2091 -360

-360

-2023 -360

-1989 -360

-1955 -360

-1921 -360

128 SEG[10] -1887 -360

129 SEG[11] -1853 -360

130 SEG[12] -1819 -360

131 SEG[13] -1785 -360

132 SEG[14] -1751 -360

133 SEG[15] -1717 -360

134 SEG[16] -1683 -360

135 SEG[17] -1649 -360

136 SEG[18] -1615 -360

137 SEG[19] -1581 -360

138 SEG[20] -1547 -360

139 SEG[21] -1513 -360

140 SEG[22] -1479 -360

141 SEG[23] -1445 -360

142 SEG[24] -1411 -360

143 SEG[25] -1377 -360

144 SEG[26] -1343 -360

145 SEG[27] -1309 -360

146 SEG[28] -1275 -360

147 SEG[29] -1241 -360

148 SEG[30] -1207 -360

Ver 1.5 4/72

PAD No. PIN Name X Y

149 SEG[31] -1173 -360

150 SEG[32] -1139 -360

151 SEG[33] -1105 -360

152 SEG[34] -1071 -360

153 SEG[35] -1037 -360

154 SEG[36] -1003 -360

155 SEG[37]

156 SEG[38]

-969

-935

-360

-360

157 SEG[39]

158 SEG[40]

159 SEG[41]

160 SEG[42]

161 SEG[43]

-901

-867

-833

-799

-765

-360

-360

-360

-360

-360

162 SEG[44]

163 SEG[45]

164 SEG[46]

165 SEG[47]

166 SEG[48]

167 SEG[49]

168 SEG[50]

169 SEG[51]

170 SEG[52]

171 SEG[53]

172 SEG[54]

173 SEG[55]

174 SEG[56]

175 SEG[57]

176 SEG[58]

177 SEG[59]

178 SEG[60]

179 SEG[61]

-425

-391

-357

-323

-289

-255

-221

-187

-153

-731

-697

-663

-629

-595

-561

-527

-493

-459

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

180 SEG[62]

181 SEG[63]

182 SEG[64]

183 SEG[65]

184 SEG[66]

185 SEG[67]

186 SEG[68]

187 SEG[69]

188 SEG[70]

189 SEG[71]

190 SEG[72]

191 SEG[73]

192 SEG[74]

193 SEG[75]

194 SEG[76]

195 SEG[77]

196 SEG[78]

197 SEG[79]

198 SEG[80]

199 SEG[81]

200 SEG[82]

187

221

255

289

323

357

391

425

459

-119

-85

-51

-17

17

51

85

119

153

493

527

561

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

2006/03/10

ST7565R

PAD No. PIN Name

201 SEG[83]

202 SEG[84]

203 SEG[85]

204 SEG[86]

205 SEG[87]

206 SEG[88]

207 SEG[89]

208 SEG[90]

209 SEG[91]

X

595

629

663

697

731

765

799

833

867

210 SEG[92]

211 SEG[93]

212 SEG[94]

213 SEG[95]

901

935

-360

-360

969 -360

1003 -360

214 SEG[96]

215 SEG[97]

216 SEG[98]

217 SEG[99]

1037

1071

1105

1139

-360

-360

-360

-360

218 SEG[100] 1173 -360

219 SEG[101] 1207 -360

220 SEG[102] 1241 -360

221 SEG[103] 1275 -360

222 SEG[104] 1309 -360

223 SEG[105] 1343 -360

224 SEG[106] 1377 -360

225 SEG[107] 1411 -360

226 SEG[108] 1445 -360

227 SEG[109] 1479 -360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

228 SEG[110] 1513 -360

229 SEG[111] 1547 -360

230 SEG[112] 1581 -360

231 SEG[113] 1615 -360

232 SEG[114] 1649 -360

233 SEG[115] 1683 -360

234 SEG[116] 1717 -360

235 SEG[117] 1751 -360

236 SEG[118] 1785 -360

237 SEG[119] 1819 -360

238 SEG[120] 1853 -360

239 SEG[121] 1887 -360

240 SEG[122] 1921 -360

241 SEG[123] 1955 -360

242 SEG[124] 1989 -360

243 SEG[125] 2023 -360

244 SEG[126] 2057 -360

245 SEG[127] 2091 -360

PAD No. PIN Name X Y

246 SEG[128] 2125 -360

247 SEG[129] 2159 -360

248 SEG[130] 2193 -360

249 SEG[131] 2227 -360

250 COM[32] 2267 -360

251 COM[33] 2301 -360

252 COM[34] 2335 -360

253 COM[35] 2369 -360

254 COM[36] 2403 -360

255 COM[37] 2437 -360

256 COM[38] 2471 -360

257 COM[39] 2505 -360

258 COM[40] 2539 -360

259 COM[41] 2573 -360

260 COM[42] 2810 -375

261 COM[43] 2810 -341

262 COM[44] 2810 -307

263 COM[45] 2810 -273

264 COM[46] 2810 -239

265 COM[47] 2810 -205

266 COM[48] 2810 -171

267 COM[49] 2810 -137

268 COM[50] 2810 -103

269 COM[51] 2810 -69

270 COM[52] 2810

271 COM[53] 2810

272 COM[54] 2810

-35

-1

33

273 COM[55] 2810

274 COM[56] 2810

275 COM[57] 2810

276 COM[58] 2810

277 COM[59] 2810

278 COM[60] 2810

279 COM[61] 2810

280 COM[62] 2810

281 COM[63] 2810

282 COMS1 2810

67

101

135

169

203

237

271

305

339

373

Ver 1.5 5/72 2006/03/10

ST7565R

46

47

48

49

42

43

44

45

38

39

40

41

33

34

35

36

37

29

30

31

32

24

25

26

27

28

19

20

21

22

23

15

16

17

18

PAD No. PIN Name

1 FRS

2

3

FR

CL

4

5

DOF

VSS

X

2575

2515

2455

2395

2335

6

7

8

9

CS1B

CS2

VDD

RST

2275

2215

2155

2095

10

11

A0

VSS

2035

1975

12 /WR(R/W) 1915

13 /RD(E) 1855

14 VDD 1795

D0

D1

D2

D3

D4

D5

D6

D7

VDD

VDD2

VDD2

VSS

VSS

VSS

VSS

VOUT

VOUT

CAP5P

1195

1135

1075

1015

955

895

821

761

701

1735

1675

1615

1555

1495

1435

1375

1315

1255

CAP5P

CAP1N

CAP1N

CAP3P

CAP3P

CAP1N

CAP1N

CAP1P

CAP1P

CAP2P

CAP2P

CAP2N

CAP2N

CAP4P

CAP4P

VSS

VSS

101

41

-19

-79

-139

-199

-273

-333

641

581

521

461

401

341

281

221

161

Ver 1.5

P a d C e n t t e r r C o o r r d i i n a t t e s

(

( 1 /

/

4 9

D u t t y

)

)

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

U n i t s : :

6/72

95

96

97

98

91

92

93

94

87

88

89

90

82

83

84

85

86

78

79

80

81

73

74

75

76

77

68

69

70

71

72

64

65

66

67

PAD No. PIN Name

50 VRS

51

52

VRS

VDD2

53

54

VDD

V4

59

60

61

62

63

55

56

57

58

V2

V1

V1

V

0

V

0

V4

V3

V3

V2

VR

VR

VDD

VDD2

TEST[0]

TEST[1]

TEST[2]

TEST[3]

TEST[4]

X

-408

-468

-542

-602

-676

-736

-796

-856

-916

Y

392

392

392

392

392

392

392

392

392

-976 392

-1036 392

-1096 392

-1156 392

-1216 392

TEST[5]

VDD

MS

CLS

C86

PSB

HPMB

IRS

SEL1

-1276 392

-1336 392

-1410 392

-1470 392

-1537 392

-1611 392

-1685 392

-1759 392

-1833 392

-1907

-1974

-2034

-2094

-2154

392

392

392

392

392

-2214 392

-2274 392

-2334 392

-2394 392

SEL2

SEL3

-2454 392

-2514 392

VSS -2574 392

Reserve -2810 373

Reserve -2810 339

Reserve -2810 305

Reserve -2810 271

Reserve -2810 237

Reserve -2810 203

Reserve -2810 169

Reserve -2810 135

COM[23] -2810 101

COM[22] -2810 67

COM[21] -2810

COM[20] -2810

COM[19] -2810

COM[18] -2810

33

-1

-35

-69

μ m

2006/03/10

ST7565R

PAD No. PIN Name

99 COM[17]

X

-2810

Y

-103

100 COM[16] -2810 -137

101 COM[15] -2810 -171

102 COM[14] -2810 -205

103 COM[13] -2810 -239

104 COM[12] -2810 -273

105 COM[11] -2810 -307

106 COM[10] -2810 -341

107

108

109

110

111

COM[9]

COM[8]

COM[7]

COM[6]

COM[5]

-2810

-2573

-2539

-2505

-2471

-375

-360

-360

-360

-360

112

113

114

115

116

117

118

119

120

COM[4]

COM[3]

COM[2]

COM[1]

COM[0]

COMS2

SEG[0]

SEG[1]

SEG[2]

-2437 -360

-2403 -360

-2369 -360

-2335 -360

-2301 -360

-2267 -360

-2227 -360

-2193 -360

-2159 -360

121

122

123

124

125

SEG[3]

SEG[4]

SEG[5]

SEG[6]

SEG[7]

-2125 -360

-2091 -360

-2057 -360

-2023 -360

-1989 -360

126

127

SEG[8]

SEG[9]

-1955 -360

-1921 -360

128 SEG[10] -1887 -360

129 SEG[11] -1853 -360

130 SEG[12] -1819 -360

131 SEG[13] -1785 -360

132 SEG[14] -1751 -360

133 SEG[15] -1717 -360

134 SEG[16] -1683 -360

135 SEG[17] -1649 -360

136 SEG[18] -1615 -360

137 SEG[19] -1581 -360

138 SEG[20] -1547 -360

139 SEG[21] -1513 -360

140 SEG[22] -1479 -360

141 SEG[23] -1445 -360

142 SEG[24] -1411 -360

143 SEG[25] -1377 -360

144 SEG[26] -1343 -360

145 SEG[27] -1309 -360

146 SEG[28] -1275 -360

147 SEG[29] -1241 -360

148 SEG[30] -1207 -360

149 SEG[31] -1173 -360

150 SEG[32] -1139 -360

Ver 1.5 7/72

PAD No. PIN Name X Y

151 SEG[33] -1105 -360

152 SEG[34] -1071 -360

153 SEG[35] -1037 -360

154 SEG[36] -1003 -360

155 SEG[37]

156 SEG[38]

157 SEG[39]

158 SEG[40]

159 SEG[41]

160 SEG[42]

161 SEG[43]

162 SEG[44]

163 SEG[45]

-969

-935

-901

-867

-833

-799

-765

-731

-697

-360

-360

-360

-360

-360

-360

-360

-360

-360

164 SEG[46]

165 SEG[47]

166 SEG[48]

167 SEG[49]

168 SEG[50]

169 SEG[51]

170 SEG[52]

171 SEG[53]

172 SEG[54]

173 SEG[55]

174 SEG[56]

175 SEG[57]

176 SEG[58]

177 SEG[59]

178 SEG[60]

179 SEG[61]

180 SEG[62]

181 SEG[63]

-357

-323

-289

-255

-221

-187

-153

-119

-85

-663

-629

-595

-561

-527

-493

-459

-425

-391

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

182 SEG[64]

183 SEG[65]

184 SEG[66]

185 SEG[67]

186 SEG[68]

187 SEG[69]

188 SEG[70]

189 SEG[71]

190 SEG[72]

191 SEG[73]

192 SEG[74]

193 SEG[75]

194 SEG[76]

195 SEG[77]

196 SEG[78]

197 SEG[79]

198 SEG[80]

199 SEG[81]

200 SEG[82]

201 SEG[83]

202 SEG[84]

255

289

323

357

391

425

459

493

527

-51

-17

17

51

85

119

153

187

221

561

595

629

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

2006/03/10

ST7565R

238

239

240

241

242

243

230

231

232

233

234

235

236

237

244

245

221

222

223

224

225

226

227

228

229

212

213

214

215

216

217

218

219

220

PAD No. PIN Name

203

204

205

206

207

208

209

210

211

SEG[85]

SEG[86]

SEG[87]

SEG[88]

SEG[89]

SEG[90]

SEG[91]

SEG[92]

SEG[93]

SEG[94]

SEG[95]

SEG[96]

SEG[97]

SEG[98]

SEG[99]

SEG[100]

SEG[101]

SEG[102]

SEG[103]

SEG[104]

SEG[105]

SEG[106]

SEG[107]

SEG[108]

SEG[109]

SEG[110]

SEG[111]

SEG[112]

SEG[113]

SEG[114]

SEG[115]

SEG[116]

SEG[117]

SEG[118]

SEG[119]

SEG[120]

SEG[121]

SEG[122]

SEG[123]

SEG[124]

SEG[125]

SEG[126]

SEG[127]

1275

1309

1343

1377

1411

1445

1479

1513

1547

969

1003

1037

1071

1105

1139

1173

1207

1241

X

663

697

731

765

799

833

867

901

935

1581

1615

1649

1683

1717

1751

1785

1819

1853

1887

1921

1955

1989

2023

2057

2091

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

273

274

275

276

277

278

279

280

281

282

264

265

266

267

268

269

270

271

272

PAD No. PIN Name

255

256

257

258

259

260

261

262

263

246 SEG[128]

247 SEG[129]

248 SEG[130]

249 SEG[131]

250

251

252

253

254

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

COM[24]

COM[25]

COM[26]

COM[27]

COM[28]

COM[29]

COM[30]

COM[31]

COM[32]

COM[33]

COM[34]

COM[35]

COM[36]

COM[37]

COM[38]

COM[39]

COM[40]

COM[41]

COM[42]

COM[43]

COM[44]

COM[45]

COM[46]

COM[47]

COMS1

2810

2810

2810

2810

2810

2810

2810

2810

2810

2437

2471

2505

2539

2573

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

X

2125

2159

2193

2227

2267

2301

2335

2369

2403

-239

-205

-171

-137

-103

-69

-35

-1

33

-360

-360

-360

-360

-360

-375

-341

-307

-273

67

101

135

169

203

237

271

305

339

373

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

Ver 1.5 8/72 2006/03/10

ST7565R

46

47

48

49

42

43

44

45

38

39

40

41

33

34

35

36

37

29

30

31

32

24

25

26

27

28

19

20

21

22

23

15

16

17

18

PAD No. PIN Name

1 FRS

2

3

FR

CL

4

5

DOF

VSS

10

11

12

13

14

6

7

8

9

CS1B

CS2

VDD

RST

A0

VSS

/RD(E)

VDD

/WR(R/W)

VDD2

VDD2

VSS

VSS

VSS

VSS

VOUT

VOUT

CAP5P

D0

D1

D2

D3

D4

D5

D6

D7

VDD

CAP5P

CAP1N

CAP1N

CAP3P

CAP3P

CAP1N

CAP1N

CAP1P

CAP1P

CAP2P

CAP2P

CAP2N

CAP2N

CAP4P

CAP4P

VSS

VSS

Ver 1.5

P a d C e n t t e r r C o o r r d i i n a t t e s

(

( 1 /

/

3 3

D u t t y

)

)

1195

1135

1075

1015

955

895

821

761

701

1735

1675

1615

1555

1495

1435

1375

1315

1255

X

2575

2515

2455

2395

2335

2275

2215

2155

2095

2035

1975

1915

1855

1795

101

41

-19

-79

-139

-199

-273

-333

641

581

521

461

401

341

281

221

161

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

9/72

68

69

70

71

72

64

65

66

67

PAD No. PIN Name

50 VRS

51

52

VRS

VDD2

53

54

VDD

V4

59

60

61

62

63

55

56

57

58

V2

V1

V1

V

0

V

0

V4

V3

V3

V2

VR

VR

VDD

VDD2

TEST[0]

TEST[1]

TEST[2]

TEST[3]

TEST[4]

87

88

89

90

82

83

84

85

86

78

79

80

81

73

74

75

76

77

TEST[5]

VDD

MS

CLS

C86

PSB

HPMB

IRS

SEL1

SEL2

SEL3

VSS

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

91

92

93

94

Reserve

Reserve

Reserve

Reserve

-2810

-2810

-2810

-2810

95 RESERVED -2810

96 RESERVED -2810

97 RESERVED -2810

98 RESERVED -2810

-2454

-2514

-2574

-2810

-2810

-2810

-2810

-2810

-2810

-1907

-1974

-2034

-2094

-2154

-2214

-2274

-2334

-2394

-1276

-1336

-1410

-1470

-1537

-1611

-1685

-1759

-1833

X

-408

-468

-542

-602

-676

-736

-796

-856

-916

-976

-1036

-1096

-1156

-1216

U n i i t t s : μ m

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

169

135

101

67

33

-1

-35

-69

392

392

392

373

339

305

271

237

203

2006/03/10

ST7565R

139

140

141

142

143

144

145

146

147

130

131

132

133

134

135

136

137

138

148

149

150

121

122

123

124

125

126

127

128

129

112

113

114

115

116

117

118

119

120

PAD No. PIN Name X

99 RESERVED -2810

100 RESERVED -2810

101 COM[15] -2810

102 COM[14] -2810

103

104

105

106

107

108

109

110

111

COM[13]

COM[12]

COM[11]

COM[10]

COM[9]

COM[8]

COM[7]

COM[6]

COM[5]

-2810

-2810

-2810

-2810

-2810

-2573

-2539

-2505

-2471

COM[4]

COM[3]

COM[2]

COM[1]

COM[0]

COMS2

SEG[0]

SEG[1]

SEG[2]

SEG[3]

SEG[4]

SEG[5]

SEG[6]

SEG[7]

SEG[8]

SEG[9]

SEG[10]

SEG[11]

-2125

-2091

-2057

-2023

-1989

-1955

-1921

-1887

-1853

-2437

-2403

-2369

-2335

-2301

-2267

-2227

-2193

-2159

SEG[12]

SEG[13]

SEG[14]

SEG[15]

SEG[16]

SEG[17]

SEG[18]

SEG[19]

SEG[20]

SEG[21]

SEG[22]

SEG[23]

SEG[24]

SEG[25]

SEG[26]

SEG[27]

SEG[28]

SEG[29]

SEG[30]

SEG[31]

SEG[32]

-1513

-1479

-1445

-1411

-1377

-1343

-1309

-1275

-1241

-1819

-1785

-1751

-1717

-1683

-1649

-1615

-1581

-1547

-1207

-1173

-1139

Ver 1.5

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-103

-137

-171

-205

-239

-273

-307

-341

-375

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

191

192

193

194

195

196

197

198

199

182

183

184

185

186

187

188

189

190

200

201

202

173

174

175

176

177

178

179

180

181

164

165

166

167

168

169

170

171

172

PAD No. PIN Name

151 SEG[33]

152

153

154

SEG[34]

SEG[35]

SEG[36]

155

156

157

158

159

160

161

162

163

SEG[37]

SEG[38]

SEG[39]

SEG[40]

SEG[41]

SEG[42]

SEG[43]

SEG[44]

SEG[45]

SEG[46]

SEG[47]

SEG[48]

SEG[49]

SEG[50]

SEG[51]

SEG[52]

SEG[53]

SEG[54]

SEG[55]

SEG[56]

SEG[57]

SEG[58]

SEG[59]

SEG[60]

SEG[61]

SEG[62]

SEG[63]

SEG[64]

SEG[65]

SEG[66]

SEG[67]

SEG[68]

SEG[69]

SEG[70]

SEG[71]

SEG[72]

SEG[73]

SEG[74]

SEG[75]

SEG[76]

SEG[77]

SEG[78]

SEG[79]

SEG[80]

SEG[81]

SEG[82]

SEG[83]

SEG[84]

10/72

-357

-323

-289

-255

-221

-187

-153

-119

-85

-663

-629

-595

-561

-527

-493

-459

-425

-391

X

-1105

-1071

-1037

-1003

-969

-935

-901

-867

-833

-799

-765

-731

-697

255

289

323

357

391

425

459

493

527

-51

-17

17

51

85

119

153

187

221

561

595

629

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

2006/03/10

ST7565R

238

239

240

241

242

243

230

231

232

233

234

235

236

237

244

245

221

222

223

224

225

226

227

228

229

212

213

214

215

216

217

218

219

220

PAD No. PIN Name

203

204

205

206

207

208

209

210

211

SEG[85]

SEG[86]

SEG[87]

SEG[88]

SEG[89]

SEG[90]

SEG[91]

SEG[92]

SEG[93]

SEG[94]

SEG[95]

SEG[96]

SEG[97]

SEG[98]

SEG[99]

SEG[100]

SEG[101]

SEG[102]

SEG[103]

SEG[104]

SEG[105]

SEG[106]

SEG[107]

SEG[108]

SEG[109]

SEG[110]

SEG[111]

SEG[112]

SEG[113]

SEG[114]

SEG[115]

SEG[116]

SEG[117]

SEG[118]

SEG[119]

SEG[120]

SEG[121]

SEG[122]

SEG[123]

SEG[124]

SEG[125]

SEG[126]

SEG[127]

1275

1309

1343

1377

1411

1445

1479

1513

1547

969

1003

1037

1071

1105

1139

1173

1207

1241

X

663

697

731

765

799

833

867

901

935

1581

1615

1649

1683

1717

1751

1785

1819

1853

1887

1921

1955

1989

2023

2057

2091

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

273

274

275

276

277

278

279

280

281

282

264

265

266

267

268

269

270

271

272

PAD No. PIN Name

255

256

257

258

259

260

261

262

263

246 SEG[128]

247 SEG[129]

248 SEG[130]

249 SEG[131]

250

251

252

253

254

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

COM[16]

COM[17]

COM[18]

COM[19]

COM[20]

COM[21]

COM[22]

COM[23]

COM[24]

COM[25]

COM[26]

COM[27]

COM[28]

COM[29]

COM[30]

COM[31]

COMS1

2810

2810

2810

2810

2810

2810

2810

2810

2810

2437

2471

2505

2539

2573

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

X

2125

2159

2193

2227

2267

2301

2335

2369

2403

-239

-205

-171

-137

-103

-69

-35

-1

33

-360

-360

-360

-360

-360

-375

-341

-307

-273

67

101

135

169

203

237

271

305

339

373

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

Ver 1.5 11/72 2006/03/10

ST7565R

46

47

48

49

42

43

44

45

38

39

40

41

33

34

35

36

37

29

30

31

32

24

25

26

27

28

19

20

21

22

23

15

16

17

18

PAD No. PIN Name

1 FRS

2

3

FR

CL

4

5

DOF

VSS

10

11

12

13

14

6

7

8

9

CS1B

CS2

VDD

RST

A0

VSS

/RD(E)

VDD

/WR(R/W)

VDD2

VDD2

VSS

VSS

VSS

VSS

VOUT

VOUT

CAP5P

D0

D1

D2

D3

D4

D5

D6

D7

VDD

CAP5P

CAP1N

CAP1N

CAP3P

CAP3P

CAP1N

CAP1N

CAP1P

CAP1P

CAP2P

CAP2P

CAP2N

CAP2N

CAP4P

CAP4P

VSS

VSS

Ver 1.5

P a d C e n t t e r r C o o r r d i i n a t t e s

(

( 1 /

/

5 5

D u t t y

)

)

1195

1135

1075

1015

955

895

821

761

701

1735

1675

1615

1555

1495

1435

1375

1315

1255

X

2575

2515

2455

2395

2335

2275

2215

2155

2095

2035

1975

1915

1855

1795

101

41

-19

-79

-139

-199

-273

-333

641

581

521

461

401

341

281

221

161

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

87

88

89

90

82

83

84

85

86

78

79

80

81

73

74

75

76

77

95

96

97

98

91

92

93

94

68

69

70

71

72

64

65

66

67

PAD No. PIN Name

50 VRS

51

52

VRS

VDD2

53

54

VDD

V4

59

60

61

62

63

55

56

57

58

V2

V1

V1

V

0

V

0

V4

V3

V3

V2

VR

VR

VDD

VDD2

TEST[0]

TEST[1]

TEST[2]

TEST[3]

TEST[4]

COM[25]

COM[24]

COM[23]

COM[22]

COM[21]

COM[20]

COM[19]

COM[18]

TEST[5]

VDD

MS

CLS

C86

PSB

HPMB

IRS

SEL1

SEL2

SEL3

VSS

Reserve

Reserve

Reserve

Reserve

Reserve

COM[26]

12/72

U n i t s : : μ m

-1907

-1974

-2034

-2094

-2154

-2214

-2274

-2334

-2394

-1276

-1336

-1410

-1470

-1537

-1611

-1685

-1759

-1833

X

-408

-468

-542

-602

-676

-736

-796

-856

-916

-976

-1036

-1096

-1156

-1216

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2454

-2514

-2574

-2810

-2810

-2810

-2810

-2810

-2810

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

169

135

101

67

33

-1

-35

-69

392

392

392

373

339

305

271

237

203

2006/03/10

ST7565R

139

140

141

142

143

144

145

146

147

130

131

132

133

134

135

136

137

138

148

149

150

121

122

123

124

125

126

127

128

129

112

113

114

115

116

117

118

119

120

PAD No. PIN Name

99 COM[17]

100

101

102

COM[16]

COM[15]

COM[14]

103

104

105

106

107

108

109

110

111

COM[13]

COM[12]

COM[11]

COM[10]

COM[9]

COM[8]

COM[7]

COM[6]

COM[5]

COM[4]

COM[3]

COM[2]

COM[1]

COM[0]

COMS2

SEG[0]

SEG[1]

SEG[2]

SEG[3]

SEG[4]

SEG[5]

SEG[6]

SEG[7]

SEG[8]

SEG[9]

SEG[10]

SEG[11]

SEG[12]

SEG[13]

SEG[14]

SEG[15]

SEG[16]

SEG[17]

SEG[18]

SEG[19]

SEG[20]

SEG[21]

SEG[22]

SEG[23]

SEG[24]

SEG[25]

SEG[26]

SEG[27]

SEG[28]

SEG[29]

SEG[30]

SEG[31]

SEG[32]

Ver 1.5

-2125

-2091

-2057

-2023

-1989

-1955

-1921

-1887

-1853

-2437

-2403

-2369

-2335

-2301

-2267

-2227

-2193

-2159

X

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2573

-2539

-2505

-2471

-1513

-1479

-1445

-1411

-1377

-1343

-1309

-1275

-1241

-1819

-1785

-1751

-1717

-1683

-1649

-1615

-1581

-1547

-1207

-1173

-1139

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-103

-137

-171

-205

-239

-273

-307

-341

-375

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

191

192

193

194

195

196

197

198

199

182

183

184

185

186

187

188

189

190

200

201

202

173

174

175

176

177

178

179

180

181

164

165

166

167

168

169

170

171

172

PAD No. PIN Name

151 SEG[33]

152

153

154

SEG[34]

SEG[35]

SEG[36]

155

156

157

158

159

160

161

162

163

SEG[37]

SEG[38]

SEG[39]

SEG[40]

SEG[41]

SEG[42]

SEG[43]

SEG[44]

SEG[45]

SEG[46]

SEG[47]

SEG[48]

SEG[49]

SEG[50]

SEG[51]

SEG[52]

SEG[53]

SEG[54]

SEG[55]

SEG[56]

SEG[57]

SEG[58]

SEG[59]

SEG[60]

SEG[61]

SEG[62]

SEG[63]

SEG[64]

SEG[65]

SEG[66]

SEG[67]

SEG[68]

SEG[69]

SEG[70]

SEG[71]

SEG[72]

SEG[73]

SEG[74]

SEG[75]

SEG[76]

SEG[77]

SEG[78]

SEG[79]

SEG[80]

SEG[81]

SEG[82]

SEG[83]

SEG[84]

13/72

-357

-323

-289

-255

-221

-187

-153

-119

-85

-663

-629

-595

-561

-527

-493

-459

-425

-391

X

-1105

-1071

-1037

-1003

-969

-935

-901

-867

-833

-799

-765

-731

-697

255

289

323

357

391

425

459

493

527

-51

-17

17

51

85

119

153

187

221

561

595

629

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

2006/03/10

ST7565R

238

239

240

241

242

243

230

231

232

233

234

235

236

237

244

245

221

222

223

224

225

226

227

228

229

212

213

214

215

216

217

218

219

220

PAD No. PIN Name

203

204

205

206

207

208

209

210

211

SEG[85]

SEG[86]

SEG[87]

SEG[88]

SEG[89]

SEG[90]

SEG[91]

SEG[92]

SEG[93]

SEG[94]

SEG[95]

SEG[96]

SEG[97]

SEG[98]

SEG[99]

SEG[100]

SEG[101]

SEG[102]

SEG[103]

SEG[104]

SEG[105]

SEG[106]

SEG[107]

SEG[108]

SEG[109]

SEG[110]

SEG[111]

SEG[112]

SEG[113]

SEG[114]

SEG[115]

SEG[116]

SEG[117]

SEG[118]

SEG[119]

SEG[120]

SEG[121]

SEG[122]

SEG[123]

SEG[124]

SEG[125]

SEG[126]

SEG[127]

1275

1309

1343

1377

1411

1445

1479

1513

1547

969

1003

1037

1071

1105

1139

1173

1207

1241

X

663

697

731

765

799

833

867

901

935

1581

1615

1649

1683

1717

1751

1785

1819

1853

1887

1921

1955

1989

2023

2057

2091

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

273

274

275

276

277

278

279

280

281

282

264

265

266

267

268

269

270

271

272

PAD No. PIN Name

255

256

257

258

259

260

261

262

263

246 SEG[128]

247 SEG[129]

248 SEG[130]

249 SEG[131]

250

251

252

253

254

Reserve

Reserve

Reserve

Reserve

Reserve

COM[27]

COM[28]

COM[29]

COM[30]

COM[31]

COM[32]

COM[33]

COM[34]

COM[35]

COM[36]

COM[37]

COM[38]

COM[39]

COM[40]

COM[41]

COM[42]

COM[43]

COM[44]

COM[45]

COM[46]

COM[47]

COM[48]

COM[49]

COM[50]

COM[51]

COM[52]

COM[53]

COMS1

2810

2810

2810

2810

2810

2810

2810

2810

2810

2437

2471

2505

2539

2573

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

2810

X

2125

2159

2193

2227

2267

2301

2335

2369

2403

-239

-205

-171

-137

-103

-69

-35

-1

33

-360

-360

-360

-360

-360

-375

-341

-307

-273

67

101

135

169

203

237

271

305

339

373

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

Ver 1.5 14/72 2006/03/10

ST7565R

46

47

48

49

42

43

44

45

38

39

40

41

33

34

35

36

37

29

30

31

32

24

25

26

27

28

19

20

21

22

23

15

16

17

18

PAD No. PIN Name

1 FRS

2

3

FR

CL

4

5

DOF

VSS

10

11

12

13

14

6

7

8

9

CS1B

CS2

VDD

RST

A0

VSS

/RD(E)

VDD

/WR(R/W)

VDD2

VDD2

VSS

VSS

VSS

VSS

VOUT

VOUT

CAP5P

D0

D1

D2

D3

D4

D5

D6

D7

VDD

CAP5P

CAP1N

CAP1N

CAP3P

CAP3P

CAP1N

CAP1N

CAP1P

CAP1P

CAP2P

CAP2P

CAP2N

CAP2N

CAP4P

CAP4P

VSS

VSS

Ver 1.5

P a d C e n t t e r r C o o r r d i i n a t t e s

(

( 1 /

/

5 3

D u t t y

)

)

1195

1135

1075

1015

955

895

821

761

701

1735

1675

1615

1555

1495

1435

1375

1315

1255

X

2575

2515

2455

2395

2335

2275

2215

2155

2095

2035

1975

1915

1855

1795

101

41

-19

-79

-139

-199

-273

-333

641

581

521

461

401

341

281

221

161

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

87

88

89

90

82

83

84

85

86

78

79

80

81

73

74

75

76

77

95

96

97

98

91

92

93

94

68

69

70

71

72

64

65

66

67

PAD No. PIN Name

50 VRS

51

52

VRS

VDD2

53

54

VDD

V4

59

60

61

62

63

55

56

57

58

V2

V1

V1

V

0

V

0

V4

V3

V3

V2

VR

VR

VDD

VDD2

TEST[0]

TEST[1]

TEST[2]

TEST[3]

TEST[4]

COM[25]

COM[24]

COM[23]

COM[22]

COM[21]

COM[20]

COM[19]

COM[18]

TEST[5]

VDD

MS

CLS

C86

PSB

HPMB

IRS

SEL1

SEL2

SEL3

VSS

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

15/72

U n i t s : μ m

-1907

-1974

-2034

-2094

-2154

-2214

-2274

-2334

-2394

-1276

-1336

-1410

-1470

-1537

-1611

-1685

-1759

-1833

X

-408

-468

-542

-602

-676

-736

-796

-856

-916

-976

-1036

-1096

-1156

-1216

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2454

-2514

-2574

-2810

-2810

-2810

-2810

-2810

-2810

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

392

Y

392

392

392

392

392

169

135

101

67

33

-1

-35

-69

392

392

392

373

339

305

271

237

203

2006/03/10

ST7565R

139

140

141

142

143

144

145

146

147

130

131

132

133

134

135

136

137

138

148

149

150

121

122

123

124

125

126

127

128

129

112

113

114

115

116

117

118

119

120

PAD No. PIN Name

99 COM[17]

100

101

102

COM[16]

COM[15]

COM[14]

103

104

105

106

107

108

109

110

111

COM[13]

COM[12]

COM[11]

COM[10]

COM[9]

COM[8]

COM[7]

COM[6]

COM[5]

COM[4]

COM[3]

COM[2]

COM[1]

COM[0]

COMS2

SEG[0]

SEG[1]

SEG[2]

SEG[3]

SEG[4]

SEG[5]

SEG[6]

SEG[7]

SEG[8]

SEG[9]

SEG[10]

SEG[11]

SEG[12]

SEG[13]

SEG[14]

SEG[15]

SEG[16]

SEG[17]

SEG[18]

SEG[19]

SEG[20]

SEG[21]

SEG[22]

SEG[23]

SEG[24]

SEG[25]

SEG[26]

SEG[27]

SEG[28]

SEG[29]

SEG[30]

SEG[31]

SEG[32]

Ver 1.5

-2125

-2091

-2057

-2023

-1989

-1955

-1921

-1887

-1853

-2437

-2403

-2369

-2335

-2301

-2267

-2227

-2193

-2159

X

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2810

-2573

-2539

-2505

-2471

-1513

-1479

-1445

-1411

-1377

-1343

-1309

-1275

-1241

-1819

-1785

-1751

-1717

-1683

-1649

-1615

-1581

-1547

-1207

-1173

-1139

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-103

-137

-171

-205

-239

-273

-307

-341

-375

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

191

192

193

194

195

196

197

198

199

182

183

184

185

186

187

188

189

190

200

201

202

173

174

175

176

177

178

179

180

181

164

165

166

167

168

169

170

171

172

PAD No. PIN Name

151 SEG[33]

152

153

154

SEG[34]

SEG[35]

SEG[36]

155

156

157

158

159

160

161

162

163

SEG[37]

SEG[38]

SEG[39]

SEG[40]

SEG[41]

SEG[42]

SEG[43]

SEG[44]

SEG[45]

SEG[46]

SEG[47]

SEG[48]

SEG[49]

SEG[50]

SEG[51]

SEG[52]

SEG[53]

SEG[54]

SEG[55]

SEG[56]

SEG[57]

SEG[58]

SEG[59]

SEG[60]

SEG[61]

SEG[62]

SEG[63]

SEG[64]

SEG[65]

SEG[66]

SEG[67]

SEG[68]

SEG[69]

SEG[70]

SEG[71]

SEG[72]

SEG[73]

SEG[74]

SEG[75]

SEG[76]

SEG[77]

SEG[78]

SEG[79]

SEG[80]

SEG[81]

SEG[82]

SEG[83]

SEG[84]

16/72

-357

-323

-289

-255

-221

-187

-153

-119

-85

-663

-629

-595

-561

-527

-493

-459

-425

-391

X

-1105

-1071

-1037

-1003

-969

-935

-901

-867

-833

-799

-765

-731

-697

255

289

323

357

391

425

459

493

-207

-51

-17

17

51

85

119

153

187

221

-149

-91

-33

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

Y

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-360

-374

-374

-374

-374

2006/03/10

ST7565R

238

239

240

241

242

243

230

231

232

233

234

235

236

237

244

245

221

222

223

224

225

226

227

228

229

212

213

214

215

216

217

218

219

220

PAD No. PIN Name

203

204

205

206

207

208

209

210

211

SEG[85]

SEG[86]

SEG[87]

SEG[88]

SEG[89]

SEG[90]

SEG[91]

SEG[92]

SEG[93]

SEG[94]

SEG[95]

SEG[96]

SEG[97]

SEG[98]

SEG[99]

SEG[100]

SEG[101]

SEG[102]

SEG[103]

SEG[104]

SEG[105]

SEG[106]

SEG[107]

SEG[108]

SEG[109]

SEG[110]

SEG[111]

SEG[112]

SEG[113]

SEG[114]

SEG[115]

SEG[116]

SEG[117]

SEG[118]

SEG[119]

SEG[120]

SEG[121]

SEG[122]

SEG[123]

SEG[124]

SEG[125]

SEG[126]

SEG[127]

1069

1127

1185

1243

1301

1359

1417

1475

1533

547

605

663

721

779

837

895

953

1011

X

25

83

141

199

257

315

373

431

489

1591

1649

1707

1765

1823

1881

1939

1997

2055

2113

2171

2229

2287

2345

2403

2461

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

Y

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

273

274

275

276

277

278

279

280

281

282

264

265

266

267

268

269

270

271

272

PAD No. PIN Name

255

256

257

258

259

260

261

262

263

246 SEG[128]

247 SEG[129]

248 SEG[130]

249 SEG[131]

250

251

252

253

254

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

COM[26]

COM[27]

COM[28]

COM[29]

COM[30]

COM[31]

COM[32]

COM[33]

COM[34]

COM[35]

COM[36]

COM[37]

COM[38]

COM[39]

COM[40]

COM[41]

COM[42]

COM[43]

COM[44]

COM[45]

COM[46]

COM[47]

COM[48]

COM[49]

COM[50]

COM[51]

COMS1

3563

3621

3679

3737

3795

3853

3911

3969

4027

3041

3099

3157

3215

3273

3331

3389

3447

3505

4085

4143

4201

4259

4542

4542

4542

4542

4542

4542

X

2519

2577

2635

2693

2751

2809

2867

2925

2983

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-345

-287

-229

-171

-113

-55

Y

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

-374

Ver 1.5 17/72 2006/03/10

ST7565R

B l l o c k D i i a g r r a m

VDD

V0

V1

V2

V3

V4

VSS

HPM

Voltage follower circuit

V0

VR

VRS

IRS

VOUT

CAP1N

CAP1P

CAP2N

CAP2P

CAP3N

CAP4P

CAP5P

VDD2

VSS

Voltage

Regulator circuit

Voltage booster circuit

Power Supply

Circuit

Status

132 SEGMENT

DRIVERS

64 COMMON

DRI VERS

Display data latch circuit

COM output control circuit

FRS

M/S

CL

DOF

FR

DISPLAY DATA RAM

65 X 132 = 8580 Bits

Column address circuit

CLS

Command decoder

Bus holder

MPU INTERFACE ( Parallel and Serial )

Ver 1.5 18/72 2006/03/10

ST7565R

P i i n D e s c r r i i p t t i i o n s

Power Supply Pins

Pin Name I/O

VDD

VDD2

VSS

VRS

Function

Power

Supply

Power

Supply

Power supply

Power supply

Power

Supply

Ground

Power

Supply

This is the internal-output VREG power supply for the LCD power supply voltage regulator.

V

0

, V1,

V2, V3,

V4,Vss

Power

Supply

This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on Vss, and must maintain the relative magnitudes shown below.

V

0

≧V1 ≧V2 ≧V3 ≧V4 ≧Vss

When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command.

1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY

V1

V2

V3

V4

8/9*V

0

,6/7*V

0

7/9*V

0

,5/7*V

0

2/9*V

0

1/9*V

0

,2/7*V

0

,1/7*V

0

7/8*V

0

,5/6*V

0

6/8*V

0

,4/6*V

0

2/8*V

0

1/8*V

0

,2/6*V

0

,1/6*V

0

5/6*V

0

,4/5*V

0

4/6*V

0

,3/5*V

0

2/6*V

0

1/6*V

0

,2/5*V

0

,1/5*V

0

7/8*V

0

,5/6*V

0

6/8*V

0

,4/6*V

0

2/8*V

0

1/8*V

0

,2/6*V

0

,1/6*V

0

7/8*V

0

,5/6*V

0

6/8*V

0

,4/6*V

0

2/8*V

0

1/8*V

0

,2/6*V

0

,1/6*V

0

LCD Power Supply Pins

No. of Pins

13

10

2

2

10

Pin Name I/O

CAP1P

CAP1N

CAP2P

CAP2N

CAP3P

CAP4P

CAP5P

VOUT

VR

O

O

O

O

O

O

O

O

I

Function

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and VSS or VDD terminal.

Output voltage regulator terminal. Provides the voltage between VSS and V

0

through a resistive voltage divider.

IRS = “L” : the V

0

voltage regulator internal resistors are not used.

IRS = “H” : the V

0

voltage regulator internal resistors are used.

No. of Pins

4

2

2

2

2

2

2

2

2

Ver 1.5 19/72 2006/03/10

ST7565R

System Bus Connection Pins

Pin Name I/O

D5 to D0

D6 (SCL)

D7 (SI)

A0

/RES

CS1B

CS2

/RD

(E)

/WR

(R/W)

C86

P/S

I/O

I

I

I

I

I

I

I

Function

This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus.

When the serial interface (SPI-4) is selected (P/S = “L”) :

D7 : serial data input (SI) ; D6 : the serial clock input (SCL).

D0 to D5 should be connected to VDD or floating.

When the chip select is not active, D0 to D7 are set to high impedance.

This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or command.

A0 = “H”: Indicates that D0 to D7 are display data.

A0 = “L”: Indicates that D0 to D7 are control data.

When /RES is set to “L”, the register settings are initialized (cleared).

The reset operation is performed by the /RES signal level.

This is the chip select signal. When CS1B = “L” and CS2 = “H”, then the chip select becomes active, and data/command I/O is enabled.

• When connected to 8080 series MPU, this pin is treated as the “/RD” signal of the 8080

MPU and is LOW-active.

The data bus is in an output status when this signal is “L”.

• When connected to 6800 series MPU, this pin is treated as the “E” signal of the 6800

MPU and is HIGH-active.

This is the enable clock input terminal of the 6800 Series MPU.

• When connected to 8080 series MPU, this pin is treated as the “/WR” signal of the 8080

MPU and is LOW-active.

The signals on the data bus are latched at the rising edge of the /WR signal.

• When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800

MPU and decides the access type :

When R/W = “H”: Read.

When R/W = “L”: Write.

This is the MPU interface selection pin.

C86 = “H”: 6800 Series MPU interface.

C86 = “L”: 8080 Series MPU interface.

This pin configures the interface to be parallel mode or serial mode.

P/S = “H”: Parallel data input/output.

P/S = “L”: Serial data input.

The following applies depending on the P/S status:

P/S Data/Command Data Read/Write 4-line SPI Clock

No. of Pins

8

1

1

2

1

1

1

“H” A0 D0 to D7 /RD, /WR X

1

“L” A0 SI (D7) Write only

When P/S = “L”, D0 to D5 must be fixed to “H”.

/RD (E) and /WR (R/W) are fixed to either “H” or “L”.

The serial access mode does NOT support read operation.

SCL (D6)

Ver 1.5 20/72 2006/03/10

ST7565R

Pin Name I/O

CLS

M/S

CL

FR

/DOF

FRS

IRS

/HPM

SEL3

SEL2

SEL1

TEST0 ~ 5

Function

I

I

Selection pin to enable or disable the internal display clock oscillator circuit.

CLS = “H” : use internal oscillator circuit .

CLS = “L” : use external clock input (internal oscillator is disabled).

When CLS = “L”, input the external display clock through the CL terminal.

This terminal selects the master/slave operation for the ST7565R Series chips.

Master operation outputs the timing signals that are required for the LCD display, while slave operation input the timing signals required for the liquid crystal display.

That synchronized the liquid crystal display system between Master and Slave.

M/S = “H” Master operation

M/S = “L” Slave operation

M/S CLS

Oscillator

Circuit

Power

Supply

Circuit

CL FR FRS DOF

“H”

“L”

“H”

“L”

“H”

“L”

Enabled

Disabled

Disabled

Disabled

Enabled

Enabled

Disabled

Disabled

Output

Input

Input

Input

Output

Output

Input

Input

Output

Output

Output

Output

Output

Output

Input

Input

I/O

This is the display clock input terminal

The following is true depending on the M/S and CLS status.

M/S CLS CL

“H”

“L”

“H”

“L”

“H”

“L”

Output

Input

Input

Input

O This is the liquid crystal alternating current signal terminal.

O This is the LCD blanking control terminal.

O

I

I

I

I

This is the output terminal for the static drive.

This terminal is only enabled when the static indicator display is ON and is used in conjunction with the FR terminal.

This terminal selects the resistors for the V

0

voltage level adjustment.

IRS = “H”: Use the internal resistors

IRS = “L”: Do not use the internal resistors. The V

0

voltage level is regulated by an external resistive voltage divider attached to the VR terminal

This is the power control terminal for the power supply circuit for liquid crystal drive.

/HPM = “H”: Normal mode

/HPM = “L”: High power mode (suggested)

These pins are DUTY selection.

SEL 3, 2, 1 DUTY BIAS

0, 0, 0 1/65 1/9 or 1/7

0, 0, 1

0, 1, 0

1/49

1/33

1/8 or 1/6

1/6 or 1/5

0, 1, 1

1, 0, 0

1/55

1/53

1, X, X -----

These are terminals for IC testing.

They are set to open.

1/8 or 1/6

1/8 or 1/6

-----

No. of Pins

1

1

1

1

1

1

1

1

3

6

Ver 1.5 21/72 2006/03/10

ST7565R

LCD Driver Pins

Pin Name I/O Function No. of Pins

SEG0 to

SEG131

O

These are the LCD segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from V

SS

, V3, V2, and V

0

.

Output Voltage

RAM DATA FR

Normal Display Reverse Display

H

H

L

L

Power save

H

L

H

L

V

0

V

SS

V

2

V

3

V

SS

V

V

V

V

2

3

0 ss

132

COM0 to

COMn

O

Through a combination of the contents of the scan data and with the FR signal, a single level is selected from V

SS

, V

4

, V

1

, and V

0

.

Scan Data FR Output Voltage

H H V

SS

H

L

L

L

H

L

V

V

V

0

1

4

67

Power save V

SS

COMS O

These are the COM output terminals for the indicator. Both terminals output the same signal.

Leave these open if they are not used.

ST7565R I/O PIN ITO Resister Limitation

PIN Name

2

ITO Resister

CL, FR, /DOF, FRS, C86, PSB, MS, HPMB, SEL1…SEL3, CLS, IRS

TEST0 ~ 5, VRS

VDD, VDD2, VSS, VOUT, VR

V

0

, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP4P, CAP5P

CS1B, CS2, /RD, /WR, A0, D0 …D7,

RST

No Limitation

Floating

<200Ω

<300Ω

<1KΩ

<10KΩ

Ver 1.5 22/72 2006/03/10

ST7565R

D e s c r r i i p t t i i o n O f f F u n c t t i i o n s

T h e M P U I

I n t t e r r f f a c e

Selecting the Interface Type

With the ST7565R chips, data transfers are done through an

8-bit parallel data bus (D7 to D0) or through a 4-line SPI data input (SI). Through selecting the P/ S terminal polarity to the “H” or “L” it is possible to select either parallel data input or 4-line SPI data input as shown in Table 1.

Table 1

P/S /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0

H: Parallel Input /CS1

L: 4-line SPI Input /CS1

“—” indicates fixed to “H”

The Parallel Interface

CS2

CS2

A0

A0

/RD

/WR

C86

D7

SI

D6

SCL

D5~D0

(HZ)

When the parallel interface has been selected (P/S =“H”), then it is possible to connect directly to either an

8080-system MPU or a 6800 Series MPU (shown in Table 2) by selecting the C86 terminal to either “H” or to “L”.

Table 2

C86 (P/S=H) /CS1 CS2 A0 E(/RD) R/W(/WR) D7~D0

H: 6800 Series /CS1 CS2

L: 8080 Series /CS1 CS2

Moreover, data bus signals are recognized by a combination of A0, /RD (E), /WR (R/W) signals, as shown in Table 3.

Table 3

Shared 6800 Series 8080 Series

A0

A0

A0 R/W /RD /WR

0

0

1

1

1

0

1

0

0

1

0

1

1

0

1

0

E

/RD

R/W

/WR

Function

D7~D0

D7~D0

Reads the display data

Writes the display data

Status read

Write control data (command)

Ver 1.5 23/72 2006/03/10

ST7565R

The 4-line SPI Interface

When the 4-line SPI interface has been selected (P/S = “L”) then when the chip is in active state (/CS1 = “L” and CS2 =

“H”) the 4-line SPI data input (SI) and the 4-line SPI clock input (SCL) can be received. The 4-line SPI data is read from the 4-line SPI data input pin in the rising edge of the 4-line

SPI clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the

CS1 eighth 4-line SPI clock for the processing. The A0 input is used to determine whether or the 4-line SPI data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the 4-line SPI clock after the chip becomes active. Figure 1 is a 4-line SPI interface signal chart.

CS2

SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

SCL

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A0

Figure 1

* When the chip is not active, the shift registers and the counter are reset to their initial states.

* Reading is not possible while in 4-line SPI interface mode.

* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment.

The Chip Select

The ST7565R have two chip select terminals: /CS1 and

CS2. The MPU interface or the 4-line SPI interface is enabled only when /CS1 = “L” and CS2 = “H”.

When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, /RD, and /WR inputs are inactive. When the 4-line SPI interface is selected, the shift register and the counter are reset.

The Accessing the Display Data RAM and the Internal Registers

Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (t accessing the ST7565R. Wait time may not be considered.

And, in the ST7565R, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus.

CYC

) requirement alone in

For example, when the MPU writes data to the display data

RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM,

The Busy Flag

When the busy flag is “1” it indicates that the ST7565R is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time

( the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle.

There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy r e a d i s r e q u i r e d w h e n e v e r t h e a d d r e s s s e t u p or write cycle operation is conducted.

This relationship is shown in Figure 2. t

CYC

) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in

MPU processing capabilities possible.

Ver 1.5 24/72 2006/03/10

ST7565R

WR

DATA

BUS

Holder

Write

Signal

N

N

Writing

N+1

N+1

N+2

N+2

N+3

N+3

Reading

WR

RD

DATA

Address

Preset

Read

Signal

Column

Address

Bus Holder

N N n n+1

Address

Set #n

Preset N

N

Dummy

Read

Figure 2

Increment N+1 n n+1

N+2 n+2

Data Read

#n

Data Read

#n+1

Ver 1.5 25/72 2006/03/10

ST7565R

Display Data RAM

The display data RAM stores the dot data for the LCD. It has a 65 (8 page x 8 bit +1) x 132 bit structure.

As is shown in Figure 3, the D7 to D0 display data from the

MPU corresponds to the LCD display common direction; there are few constraints at the time of display data transfer when multiple ST7565R are used, thus and display structures can be created easily and with a high degree of

D0 0 1 1 1 0 freedom.

Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering).

COM0

D1 1 0 0 0 0 COM1

D2 0 0 0 0

D3 0 1 1 1

D4 1 0 0 0

-

0

0

0

COM2

COM3

COM4

-

Display data RAM Liquid crystal display

Figure 3

The Page Address Circuit

Page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access.

Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special

RAM for icons, and only display data D0 is used.

(see Figure 4)

The Column Addresses

The display data RAM column address is specified by the

Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementing of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H,

SEG Output

ADC

(D0) “0”

(D0) “1” it is necessary to respective both the page address and the column address.

Furthermore, as is shown in Table 4, the ADC command

(segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. As is shown in Figure 4,

Table 4

SEG0

SEG 131

0 (H)

®

Column Address

®

83 (H)

83 (H)

¬

Column Address

¬

0 (H)

The Line Address Circuit

The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for ST7565R, the detail is shown page.11 The display area is a 65 line area for the ST7565R.

If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.

Ver 1.5 26/72 2006/03/10

ST7565R

Page Address

Data

D3 D2 D1 D0

0

0

0

0

0

0

0

0

1

0

1

0

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

0

0

0

1

1

0

1

0

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

0 1 0 1

D4

D5

D6

D7

D0

D1

0 1 1 0

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

0 1 1 1

D4

D5

D6

D7

1 0 0 0 D0

Ver 1.5

Page 0

Page 1

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Page 8

Line

Address

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

3CH

3DH

3EH

3FH

12H

13H

14H

15H

16H

17H

18H

19H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

00H

01H

02H

03H

04H

05H

06H

07H

When the common output is normal

COM

Output

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM60

COM61

COM62

COM63

COMS

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

Regardless of the display start line address,

1/65duty => 64th line,

1/49duty =>48th line.

1/33duty =>32th line,

1/55duty =>54th line,

1/53duty =>52th line.

Figure 4

27/72 2006/03/10

ST7565R

The Display Data Latch Circuit

The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM.

Because the display normal/reverse status, display ON/OFF

The Oscillator Circuit

This is a CR-type oscillator that produces the display clock.

The oscillator circuit is only enabled when M/S= “H” and

CLS = “H”.

Display Timing Generator Circuit

The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal.

Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data

RAM by the MPU. Consequently, even if the display data

Two-frame alternating current drive waveform

64 65 1 2 3 4 5 6 status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself.

When CLS = “L” the oscillation stops, and the external clock is input through the CL terminal.

RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display.

Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit.

60 61 62 63 64 65 1 2 3 4 5 6

CL

FR

V0

V1

COM0

V4

V

SS

V

0

V

1

COM1

V

4

V ss

RAM

Data

SEGn

V

0

V

2

V

3

V

SS

Figure 5

Ver 1.5 28/72 2006/03/10

ST7565R

The Common Output Status Select Circuit

In the ST7565R chips, the COM output scan direction can be selected by the common output status select command.

Table 6

COM Scan Direction

Status

(See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized.

1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY

Normal

Reverse

COM0

®

COM63

COM63

®

COM0

COM0

®

COM47

COM47

®

COM0

COM0

®

COM31

COM31

®

COM0

COM0

®

COM53

COM53

®

COM0

COM0

®

COM51

COM51

®

COM0

Duty

COM dir

Common output pins

1/65

0

1

COM[0:15] COM[16:23] COM[24:26] COM[27:36] COM[37:39] COM[40:47] COM[48:63] COMS

COM[0:63] COMS

COM[63:0] COMS

1/49

1/33

1/55

1/53

0

1

COM[0:23]

COM[47:24]

0 COM[0:15]

1 COM[31:16]

0

1

COM[0:26]

COM[53:27]

0

1

COM[0:25]

COM[51:26]

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

COM[24:47]

COM[23:0]

COM[27:53]

COM[26:0]

COM[25:0]

COM[26:51]

COMS

COMS

COM[16:31] COMS

COM[15:0] COMS

COMS

COMS

COMS

COMS

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COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM1

COM2

COM3

COM4

COM5

COM6

COM7

ST7565R

The LCD Driver Circuits

These are a 187-channel that generates four voltage levels for driving the LCD . The combination of the display data, the

COM scan signal, and the FR signal produces the liquid

M

COM0

COM0

COM1

COM2

SEG0

SEG1

SEG 0 1 2 3 4

COM0 to

SEG0

COM0 to

SEG1 crystal drive voltage output.

Figure 6 shows examples of the SEG and COM output wave form.

V0

V1

V2

V3

V4

V

SS

-V4

-V3

-V2

-V1

-V0

V0

V1

V2

V3

V4

V

SS

V0

V1

V2

V3

V4

V

SS

V0

V1

V2

V3

V4

V

SS

-V4

-V3

-V2

-V1

-V0

V0

V1

V2

V3

V4

V

SS

V

DD

V

SS

V0

V1

V2

V3

V4

V

SS

V0

V1

V2

V3

V4

V

SS

Figure 6

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ST7565R

The Power Supply Circuits

The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the LCD drivers. They are Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the

Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations.

bit function

Table 7

D2

D1

D0

Booster circuit control bit

Voltage regulator circuit control bit (V/R circuit)

Voltage follower circuit control bit (V/F circuit)

Status

“1” “0”

ON OFF

ON OFF

ON OFF

Use Settings

The Control Details of Each Bit of the Power Control Set Command

Table 8

D2 D1

D0 booster

Voltage regulator

Voltage follower

1 1 1 ON ON ON

External voltage input

Step-up voltage

V

DD2

Used Only the internal power supply is used

Only the voltage regulator circuit and the voltage follower circuit are used

Only the V/F circuit is used

0

0

1

0

1

1

OFF

OFF

ON

OFF

ON

ON

V

OUT

, V

DD2

Open

V

0

, V

DD2

Open

Only the external power supply is used 0 0 0 OFF OFF OFF V

0 to V

4

Open

Reference Combinations

* The “step-up system terminals” refer CAP1N, CAP1P, CAP2N, CAP2P, and CAP3N.

* While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use.

The Step-up Voltage Circuits

Using the step-up voltage circuits equipped within the

ST7565R chips it is possible to product a 2X,3X,4X,5X or 6X step-up of the V

SS

– V

DD2 voltage levels.

6X step-up: Connect capacitor C1 between CAP1N and

CAP1P, between CAP2N and CAP2P, between

CAP1N and CAP3P, between CAP2N and

CAP4P,between CAP1N and CAP5P, and between V

DD2 and

VOUT

, to produce a voltage level in the positive direction at the

VOUT terminal that is 6 times the voltage level between V

SS and V

DD

2.

5X step-up: Connect capacitor C1 between CAP1N and

CAP1P, between CAP2N and CAP2P, between

CAP1N and CAP3P, between CAP2N and

CAP4P,and between V

DD2 and

VOU

T, to produce a voltage level in the positive direction at the

VOUT terminal that is 5 times the voltage level between V

SS and V

DD

2.

4X step-up: Connect capacitor C1 between CAP1N and

CAP1P, between CAP2N and CAP2P, between

CAP1N and CAP3P, and between V

DD2 and

VOU

T, to produce a voltage level in the positive direction at the

VOUT terminal that is 4 times the voltage level between V

SS and V

DD

2.

3X step-up: Connect capacitor C1 between CAP1N and

CAP1P, between CAP2N and CAP2P and between

V

DD2 and V

OUT

, and short between CAP3P and

VOUT to produce voltages level in the positive direction

at the

VOUT terminal that is 3 times the voltage difference between V

SS and V

DD

2.

2X step-up: Connect capacitor C1 between CAP1N and

CAP1P, and between V

DD2 and V

OUT

, leave

CAP2N open, and short between CAP2P,

CAP3P and

VOUT to produce a voltage in the positive direction at the

VOUT terminal that Is twice the voltage between

VSS and V

DD

2.

The step-up voltage relationships are shown in Figure 7.

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ST7565R

C1

C1

V

DD2

or V

SS

V

OUT

CAP3P

CAP1N

CAP1P

CAP2P

OPEN CAP2N

OPEN

OPEN

CAP4P

CAP5P

2x voltage booster circuit

V

OUT

<=2xV

DD2

Do NOT over voltage limitation

V

DD2

V

SS

2x boost voltage relationship

C1

V

DD2

or V

SS

V

OUT

CAP3P

CAP1N

C1

CAP1P

CAP2P

C1

CAP2N

OPEN

OPEN

CAP4P

CAP5P

3x voltage booster circuit

V

OUT

<=3xV

DD2

Do NOT over voltage limitation

V

DD2

V

SS

3x boost voltage relationship

C1

V

DD2

or V

SS

V

OUT

CAP3P

C1

C1

CAP1N

CAP1P

CAP2P

C1

CAP2N

OPEN

OPEN

CAP4P

CAP5P

4x voltage booster circuit

V

OUT

<=4xV

DD2

Do NOT over voltage limitation

V

DD2

V

SS

4x boost voltage relationship

V

DD2

or V

SS

V

DD2

or V

SS

C1 C1

V

OUT

CAP3P

V

OUT

CAP3P

C1 C1

CAP1N CAP1N

C1 C1

CAP1P

CAP2P

CAP1P

CAP2P

C1 C1

CAP2N CAP2N

C1 C1

OPEN

CAP4P

CAP5P

C1

CAP4P

CAP5P

5x voltage booster circuit 6x voltage booster circuit

V

OUT

<=5xV

DD2

Do NOT over voltage limitation

V

OUT

<=6xV

DD2

Do NOT over voltage limitation

V

DD2

V

SS

V

DD2

V

SS

5x boost voltage relationship 6x boost voltage relationship

Figure 7

* The V

DD2 voltage range must be set so that the V

OUT terminal voltage does not exceed the absolute maximum rated value.

* The maximum voltage of the booster capacitor terminals are :

V

MAX

: CAP5P > CAP4P > CAP3P > CAP2P > CAP1P > CAP2N = CAP1N.

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ST7565R

The Voltage Regulator Circuit

The step-up voltage generated at

VOUT outputs the LCD driver voltage V

0 through the voltage regulator circuit.

Because the ST7565R chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V

0 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components.

(

VREG thermal gradients approximate -0.05%/°C)

(A) When the V

0

Voltage Regulator Internal Resistors Are Used

Through the use of the V

0 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V

0 can be controlled by commands alone

(without adding any external resistors), making it possible to

V

0

=

(

1 +

Rb

Ra

)

V

EV

adjust the liquid crystal display brightness. The V

0 voltage can be calculated using equation A-1 over the range where

| V

0

| < | V

OUT

|.

=

(

1 +

Rb

Ra

) (

1 -

α

162

)

V

REG

[

V

EV

=

(

1 -

α

162

)

V

REG

]

V

SS

V

EV

(constant voltage supply+electronic volume)

Internal Ra

V

0

Internal Rb

Figure 8

V

REG

is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9.

Table 9

Part no.

Equipment Type Thermal Gradient V

REG

ST7565R Internal Power Supply –0.05 %/°C 2.1V

α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume registers. Table 10 shows the value for α depending on the electronic volume register settings.

Rb/Ra is the V

0

voltage regulator internal resistor ratio, and can be set to 8 different levels through the V

0

voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V

0

voltage regulator internal resistor ratio register.

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ST7565R

D5 D4 D3

Table 10

D2 D1

D0 α

1

1

1

0

0

0

1

1

1

0

0

0

1

1

1

0

0

0

:

1

1

1

0

0

0

:

0

0

1

0

1

1

0

1

0

1

0

1

:

2

1

0

63

62

61

:

V

0

voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value)

Table 11

Register ST7565R

D2 D1 D0 (1) –0.05 %/°C

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Figures 9, 10 show V

0

voltage measured by values of the internal resistance ratio resistor for V

0

voltage adjustment and electric volume resister for each temperature grade model.

V0

UNIT:V

Ta = 25 °C and booster off ,regulator,follower on

VDD=3V

8

7

6

5

4

15

14

13

12

11

10

9

111

110

101

100

011

010

001

000

V0 voltage regulator internal resistor ratio set D2,D1,D0

3

2

1

0

00H 1FH 3FH

Electronic volume registered

D5 ~ D0

Figure 9 : (1) For ST7565R the Thermal Gradient = -0.05%/°C

The V

0

voltage as a function of the V

0

voltage regulator internal resistor ratio register and the electronic volume register.

Setup example: When selecting Ta = 25°C and V

0

= 7V for an ST7565R on which Temperature gradient = –0.05%/°C.

Using Figure 9 and the equation A-1, the following setup is enabled.

At this time, the variable range and the notch width of the V

0

voltage is, as shown Table 13, as dependent on the electronic volume.

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ST7565R

Contents

For V

0

voltage regulator

Electronic Volume

D5

1

Table 12

D4

0

Register

D3

D2

0

0 1

D1

1

0

D0

0

1

V

0

Variable Range

Notch width

Min

5.1 (63 levels)

Table 13

Typ

7.0 (central value)

51

Max

8.4 (0 level)

Units

[V]

[mV]

(B) When an External Resistance is Used (The V

0

Voltage Regulator Internal Resistors Are Not Used) (1)

The liquid crystal power supply voltage V without using the V

0

V

0

=

(

1 +

Rb'

Ra'

)

V

EV

0 can also be set

voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between V

DD and V

R

, and between V

R and V

0

, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V through commands.

0

In the range where | V

0

| < | V

OUT

|, the V

0 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’.

=

(

1 +

Rb'

Ra'

) (

1 -

α

162

)

V

REG

[

V

EV

=

(

1 -

α

162

)

V

REG

]

External resistor Ra'

V

SS

V

EV

(fixed voltage power supply+electronic volume)

V

0

External resistor Rb'

Figure 11

Setup example: When selecting Ta = 25°C and V

0

= 7 V for

ST7565R the temperature gradient = –0.05%/°C.

When the central value of the electron volume register is

Moreover, when the value of the current running through

Ra’ and Rb’ is set to 5 uA,

(Equation B-3)

(D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and

Ra’ + Rb’ = 1.4MΩ

Consequently, by equations B-2 and B-3,

V

REG

= 2.1V so, according to equation B-1,

V

0

=

(

1 +

Rb'

Ra'

) (

1 -

α

162

)

V

REG

Rb'

Ra'

= 3.12

Ra' = 340kΩ

7V =

(

1 +

Rb'

Ra'

) (

1 -

31

162

)

(2.1)

Rb' = 1060kΩ

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ST7565R

At this time, the V0 voltage variable range and notch width, based on the electron volume function, is as given in Table 14.

Table 14

V

0

Variable Range

Notch width

Min

5.3 (63 levels)

Typ

7.0 (central value)

52

Max

8.6 (0 level)

Units

[V]

[mV]

(C) When External Resistors are Used (The V

0

Voltage Regulator Internal Resistors Are Not Used) (2)

When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V

0

. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V

0 by commands to adjust the liquid

V

0

=

(

1 +

R3+R2-ΔR2

R1+ΔR2

)

V

EV

crystal display brightness.

In the range where | V

0

| < | V

OUT

| the V calculated by equation C-1 below based on the R

1 and R

2

(variable resistor) and R

3 settings, where R

2 can be subjected to fine adjustments (Δ R

2

).

0 voltage can be

=

(

1 +

R3+R2-ΔR2

R1+ΔR2

) (

1 -

α

162

)

V

REG

[

V

EV

=

(

1 -

α

162

)

V

REG

]

Ra'

Rb'

External resistor R1

External resistor R2

External resistor R3

Δ

R

2

V

R

V

SS

V

EV

(fixed voltage power supply+electronic volume)

V

0

Figure 12

Setup example: When selecting Ta = 25°C and V

0

= 5 to 9 V

(using R2) for an ST7565R the temperature gradient

= –0.05%/°C.

When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α =

31 and V

REG

= 2.1 V so, according to equation C-1, when Δ

R1 = 264kΩ

R2 = 211kΩ

R

2

= 0 Ω, in order to make V

0

= 9 V,

9V =

(

1 +

R3+R2

R1

) (

1 -

31

162

)

(2.1)

When ΔR

2

= R

2

, in order to make V = –5 V,

R

1

+ R

2

+ R

3

= 1.4MΩ (Equation C-4)

With this, according to equation C-2, C-3 and C-4,

R3 = 925kΩ

The V

0

voltage variable range and notch width based on the electron volume function is as shown in Table 15.

5V =

(

1 +

R3

R1+R2

) (

1 -

31

162

)

(2.1)

When the current flowing V

DD

and V

0

is set to 5 uA,

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ST7565R

V

0

Min

Table 15

Typ Max

Units

Variable Range

Notch width

5.3 (63 levels) 7.0 (central value)

53

8.7 (0 level) [V]

[mV]

* When the V

0 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands.

Moreover, it is necessary to provide a voltage from V

OUT when the Booster circuit is OFF.

* The V

R terminal is enabled only when the V

When the V

0 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the V

R terminal is left open.

* Because the input impedance of the

VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise.

0 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”).

The LCD Voltage Generator Circuit

The V

0 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V

1

, V

2

, V

3

, and V

4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V

1

, V

2

, V

3 and V

4 to the liquid crystal drive circuit.

High Power Mode

The power supply circuit equipped in the ST7565R chips has very low power consumption (normal mode: HPM = “H”).

However, for LCD panels with large loads (size), this low-power power supply may cause display quality to degrade. When this occurs, set the HPM terminal to “L”

(high power mode) can improve the display quality.

The Internal Power Supply Shutdown Command Sequence

SITRONIX recommends that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally.

The sequence shown in Figure 13 is recommended for shutting down the internal power supply, first placing the internal power supply in power saver mode and then turning

Sequence

Step1

Step2

End

Details

(Command, status)

Display OFF

Display all points ON

Internal power supply OFF the internal power supply OFF. The power consumption can be reduced by this sequence. Please refer to the “Power

Save” section for the detailed power saving information.

Command address

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 0 1 1 1 0

1 0 1 0 0 1 0 1

Power saver commands

(compound)

Figure 13

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ST7565R

Reference Circuit Examples

1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit

(1) When the voltage regulator internal resistor is used.

(Example where V

DD

2 = V

DD

, with 4x step-up)

(2) When the voltage regulator internal resistor is not used.

(Example where V

DD

2 = V

DD

, with 4x step-up)

V

DD

V

SS

V

DD

IRS M/S IRS M/S

V

DD or VSS

C1

C1

C1

C1

C2

C2

C2

C2

C2

V0

V1

V2

V3

V4

V

DD2 or

VSS

V

OUT

CAP3P

CAP1N

CAP1P

CAP2N

CAP2P

V

5

V

R

CAP4P

CAP5P

V

DD or

VSS

R2

R1

C1

C1

C1

C1

R3

C2

C2

C2

C2

C2

V

DD2 or

VSS

V

OUT

CAP3P

CAP1N

CAP1P

CAP2N

CAP2P

V0

V

R

V

SS

V0

V1

V2

V3

V4

CAP4P

CAP5P

VDD2 or V

SS VDD2 or V

SS

2. When the voltage regulator circuit and V/F circuit alone are used

(1) W hen the V

0

voltage regulator internal resistor is not used.

(2) W hen the V is used.

0

voltage regulator internal resistor

V

SS

V

DD

V

DD

M/S M/S

V

DD

External power supply

R2

R1

VDD or V

SS

C2

C2

C2

C2

C2

R3

V

SS

V

0

V1

V2

V3

V4

V

DD2

V

OUT

CAP3P

CAP1N

CAP1P

CAP2N

CAP2P

V

0

V

R

IRS

CAP4P

CAP5P

V

DD

External power supply

VDD or V

SS

C2

C2

C2

C2

C2

V

0

V1

V2

V3

V4

V

DD2

V

OUT

CAP3P

CAP1N

CAP1P

CAP2N

CAP2P

V

0

V

R

IRS

CAP4P

CAP5P

Ver 1.5 38/72 2006/03/10

ST7565R

(3) When the V/F circuit alone is used

V

DD

IRS M/S

(4) When the built-in power is not used

V

DD

V

SS

IRS M/S

V

SS

External power supply

V

SS

V

OUT

CAP3P

CAP1N

CAP1P

CAP2N

CAP2P

V

0

V

R

CAP4P

CAP5P

V

SS

V

SS

V

OUT

CAP3P

CAP1N

CAP1P

CAP2N

CAP2P

V

0

V

R

CAP4P

CAP5P

C2

V

0

V

0

C2

V1

V1

C2

V2

External power supply

V2

C2

V3

V3

C2

V4

VDD or V

SS

V4

VDD or V

SS

VDD or

V

SS

Item

C1

C2

Set value

1.0 to 4.7

0.1 to 4.7 units uF uF

C1 and C2 are determined by the size of the LCD being driven

* 1. Because the VR terminal input impedance is high, use short leads and shielded lines.

* 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage.

Example of the Process by which to Determine the Settings:

• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.

• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V

0

to V

4

). Note that all C2 capacitors must have the same capacitance value.

• Next turn all the power supplies ON and determine C1.

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ST7565R

The Reset Circuit

When the /RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows:

1. Display OFF

2. Normal display

3. ADC select: Normal (ADC command D0 = “L”)

4. Power control register: (D2, D1, D0) = (0, 0, 0)

5. 4-line SPI interface internal register data clear

6. LCD power supply bias rate:

1/65 DUTY = 1/9 bias

1/49,1/55,1/53 DUTY = 1/8 bias

1/33 DUTY = 1/6 bias

7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”)

8. Power saving clear

9. V

0

voltage regulator internal resistors Ra and Rb separation

10. Output conditions of SEG and COM terminals

SEG=VSS, COM=VSS

11. Read modify write OFF

12. Static indicator OFF Static indicator register : (D1, D2) =

(0, 0)

13. Display start line set to first line

14. Column address set to Address 0

15. Page address set to Page 0

16. Common output status normal

17. V

0

voltage regulator internal resistor ratio set mode clear

18. Electronic volume register set mode clear Electronic volume register :

( D 5 , D 4 , D 3 , D 2 , D 1 , D 0 ) = ( 1 , 0 . 0 , 0 , 0 , 0 )

19. Test mode clear

On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed.

When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the /RES terminal. After the initialization, each input terminal should be controlled normally.

Moreover, when the control signal from the MPU is in the high impedance, an over current may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state.

If the internal liquid crystal power supply circuit is not used on ST7565R,it is necessary that /RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V

0

when /RES is “L,” and the external power supply short-circuits to V ss

when /RES is “L.”

While /RES is “L,” the oscillator and the display timing generator stop, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The

V

SS

level is output from the SEG and COM output terminals.

This means that an internal resistor is connected between

V

SS

and V

0

.

When the internal liquid crystal power supply circuit is not used on other models of ST7565R series, it is necessary that /RES is “L” when the external liquid crystal power supply i turned on. s

While /RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected.

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C o m m a n d s

The ST7565R identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required.

In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example.

When the 4-line SPI interface is selected, the data is input in sequence starting with D7.

<Explanation of Commands>

Display ON/OFF

This command turns the display ON and OFF.

A0

0

E

/RD

1

R/W

/WR

0

D7 D6

1 0

D5

1

D4

0

D3

1

D2

1

D1

1

D0

1

0

Setting

Display ON

Display OFF

When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details.

Display Start Line Set

This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”.

A0

0

E

/RD

1

R/W

/WR

0

D7 D6

0 1

D5

0

0

0

1

1

D4

¯

1

1

0

0

0

D3

0

0

0

1

1

D2

0

0

0

1

1

D1

0

0

1

1

1

D0

0

1

0

0

1

Line address

0

1

2

¯

62

63

Page Address Set

This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM

(see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM.

Changing the page address does not accompany a change in the status display.

A0

0

E

/RD

1

R/W

/WR

0

D7 D6

1 0

D5

1

D4

1

D3

¯

0

1

0

0

0

D2

0

0

0

1

0

D1

0

0

1

1

0

D0

0

1

0

1

0

Page address

0

1

2

¯

7

8

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Column Address Set

This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details.

High bits

®

Low bits

®

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0

Column

address

0

0 A3 A2 A1 A0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

1

2

¯ ¯

1 0 0 0 0 0 1 0 130

1 0 0 0 0 0 1 1 131

Status Read

A0

0

E

/RD

0

R/W

/WR

1

D7 D6 D5 D4 D3

BUSY ADC ON/OFF RESET 0

D2

0

D1

0

D0

0

BUSY

ADC

ON/OFF

RESET

BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process.

BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check for

BUSY conditions.

This shows the relationship between the column address and the segment driver.

0: Normal (column address n

«

SEG n)

1: Reverse (column address 131-n

«

SEG n)

(The ADC command switches the polarity.)

ON/OFF: indicates the display ON/OFF state.

0: Display ON

1: Display OFF

(This display ON/OFF command switches the polarity.)

This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset command.

0: Operating state

1: Reset in progress

Display Data Write

This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

1 1 0 Write data

Display Data Read

This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the 4-line SPI interface is used, reading of the display data becomes unavailable.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

1 0 1 Read data

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ADC Select (Segment Driver Direction Select)

This command can reverse the correspondence between the display RAM data column address and the segment driver output.

Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0 Setting

0 1 0

1 0 1 0 0 0 0 0

1

Normal

Reverse

Display Normal/Reverse

This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0 Setting

0 1 0 1 0 1 0 0 1 1 0

1

RAM Data “H”

LCD ON voltage (normal)

RAM Data “L”

LCD ON voltage (reverse)

Display All Points ON/OFF

This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0 Setting

0 1 0

1 0 1 0 0 1 0 0

1

Normal display mode

Display all points ON

When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode.

For details, see the Power Save section.

LCD Bias Set

This command selects the voltage bias ratio required for the liquid crystal display.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1 D0

Select Status

1/65duty 1/49duty 1/33duty 1/55duty 1/53duty

0 1 0

1 0 1 0 0 0 1 0

1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias

1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias

Read-Modify-Write

This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the Read-Modify-Write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

0 1 0 1 1 1 0 0 0 0 0

* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.

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Read-Modify-Write

Page Address Set

Column Address Set

Read-Modify-Write Cycle

Dummy Read

Data Read

Modify Data

Data Write (at same Address)

No

Column address

Finished?

Yes

Done

Figure 24 Command Sequence For read modify write

N

N+1

N+2 N+3 N+m

N

Return

Read-modify-write mode set

End

Figure 25

End

This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

0 1 0 1 1 1 0 1 1 1 0

Reset

This command initializes the display start line, the column address, the page address, the common output mode, the V

0 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details.

The reset operation is performed after the reset command is entered.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

0 1 0 1 1 1 0 0 0 1 0

The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset command must not be used instead.

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Common Output Mode Select

This command can select the scan direction of the COM output terminal. For details, see the function explanation in

“Common Output Mode Select Circuit.”

E R/W

D7 D6 D5 D4 D3 D2 D1 D0

A0 /RD /WR

1/65duty

Selected Mode

1/49duty 1/33duty 1/55duty 1/53duty

0 1 0

1 1 0 0 0 * * *

1

Normal

Reverse

* Disabled bit

COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51

COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0

Power Controller Set

This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0 Selected Mode

0 0 1 0 1 0

1

Booster circuit: OFF

Booster circuit: ON

0 1 0

0

1

Voltage regulator circuit: OFF

Voltage regulator circuit: ON

0

1

Voltage follower circuit: OFF

Voltage follower circuit: ON

V

0

Voltage Regulator Internal Resistor Ratio Set

This command sets the V

0

voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage

Regulator circuit " and table 11 .

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0 Rb/Ra Ratio

0 1 0

0 0 1 0

¯

0 0

0

0

1

1

0

0

1

1

1

0

1

0

1

1

Small

¯

Large

The Electronic Volume (Double Byte Command)

This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V

0 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other.

The Electronic Volume Mode Set

When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

0 1 0 1 0 0 0 0 0 0 1

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Electronic Volume Register Set

By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V

0

assumes one of the 64 voltage levels.

When this command is input, the electronic volume mode is released after the electronic volume register has been set.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2

*

*

*

*

*

*

0

0

0

0

0

0

0

0

0

0

0

0

0 1 0

*

*

*

*

1

1

1

1

1

1

1

1

* Inactive bit (set “0”)

When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)

D1

0

1

1

¯

1

1

D0

1

0

1

0

1

| V

0

Small

¯

|

Large

The Electronic Volume Register Set Sequence

Figure 26

Static Indicator (Double Byte Command)

This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands.

This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes.

The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.)

Static Indicator ON/OFF

When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used.

Thi s m o d e i s c le a re d when data is set in the register by the static indicator register set command.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0 Static Indicator

0 1 0

1 0 1 0 1 1 0 0

1

OFF

ON

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Static Indicator Register Set

This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Indicator Display State

0 1 0

* * * * * * 0 0

0

1

1

1

0

1

OFF

ON (blinking at approximately one second intervals)

ON (blinking at approximately 0.5 second intervals)

ON (constantly on)

* Disabled bit (set “0”)

Static Indicator Register Set Sequence

Figure 27

Power Save (Compound Command)

When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption.

The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered.

In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM.

Refer to figure 28 for power save off sequence.

Normal Mode Normal Mode

Static Indicator OFF (2bytes)

Display OFF

Display all points ON

Sleep Mode

Static Indicator ON & Set (2bytes)

Display OFF

Display all points ON

Standby Mode

Power save OFF

Display all points OFF

Static Indicator ON & Set (2bytes)

Power save OFF

Display all points OFF

Normal Mode

(Exit Sleep Mode)

Figure 28

Normal Mode

(Exit Standby Mode)

Sleep Mode

This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows:

1. The oscillator circuit and the LCD power supply circuit are halted.

2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a V

SS

level.

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Standby Mode

The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode.

1 The LCD power supply circuits are halted. The oscillator circuit continues to operate.

2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a V

SS

level.

The static drive system does not operate.

When a reset command is performed while in standby mode, the system enters sleep mode.

* When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The ST7565R series chips have a liquid crystal display blanking control terminal /DOF. This terminal enters an “L” state when the power saver mode is launched.

Using the output of /DOF, it is possible to stop the function of an external power supply circuit.

* When the master is turned on, the oscillator circuit is operable immediately after the powering on.

The Booster Ratio (Double Byte Command)

This command makes it possible to select step-up ratio. It is used when the power control set have turn on the internal booster circuit. This command is a two byte command used as a pair with the booster ratio select mode set command and the booster ratio register set command, and both commands must be issued one after the other.

Booster Ratio Select Mode Set

When this command is input, the Booster ratio register set command becomes enabled. Once the booster ratio select mode has been set, no other command except for the booster ratio register command can be used. Once the booster ratio register set command has been used to set data into the register, then the booster ratio select mode is released.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

0 1 0 1 1 1 1 1 0 0 0

Booset Ratio Register Set

By using this command to set two bits of data to the booster ratio register, it can be select what kind of the booster ratio can be used.

When this command is input, the booster ratio select mode is released after the booster ratio register has been set.

A0

0

E

/RD

1

R/W

/WR

0

D7 D6

*

*

*

*

*

*

D5

*

*

*

D4

*

*

*

D3

*

*

*

D2

*

*

*

D1

0

0

1

D0

0

1

1

* Inactive bit (set “0”)

When the booster ratio select function is not used, set this to (0, 0) 2x,3x,4x step-up mode

Booster ratio select

2x,3x,4x

5x

6x

The booster ratio Register Set Sequence

Booster Ratio Set

Booster Ratio Select Mode

Set

Booster Ratio Register Set

No

Set Complete?

Yes

Done

Figure 29

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NOP

Non-Operation Command

A0

E

/RD

R/W

/WR

0 1 0

D7 D6

1 1

D5

1

D4

0

D3

0

D2

0

D1

1

D0

1

Test

This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the /RES input by the reset command or by using an NOP.

A0

E

/RD

R/W

/WR

D7 D6 D5 D4 D3 D2 D1

D0

0 1 0 1 1 1 1 1 1 * *

* Inactive bit

Note: The ST7565R maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the ST7565R . Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise.

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Table 16: Table of ST7565R Commands

Command Code

(Note) *: ignored data

Command

(1) Display ON/OFF

(2) Display start line set

(3) Page address set

A0 /RD

/WR D7 D6 D5 D4 D3 D2 D1 D0

0 1 0

0

0

1

1

0

0

1 0 1 0 1 1 1 0

1

0

1

1

0 1

Display start address

1

Function

LCD display ON/OFF

0: OFF, 1: ON

Sets the display RAM display start line address

Page address Sets the display RAM page address

(4) Column address set upper bit

Column address set lower bit

(5) Status read

0 1 0

0 0 1

0 0 0 1

0 0 0 0

Status

Most significant column address

Least significant column address

Sets the most significant 4 bits of the display

RAM column address.

Sets the least significant 4 bits of the display

RAM column address.

0 0 0 0 Reads the status data

(6) Display data write 1 1 0 Write data Writes to the display RAM

(7) Display data read 1 0 1 Read data Reads from the display RAM

(8) ADC select

(9) Display normal/ reverse

(10) Display all points

ON/OFF

(13) End

(11) LCD bias set

(12) Read-modify-write

0

0

0

0

0

1

1

1

1

1

0

0

0

0

0

1

1 0 1 0 0 1 1 0

1

1 0 1 0 0 0 1 0

1

0

0

1

1

1

1

0

0

0

0

0

0

0

1

0

0

0

0

0

1

1

0

1

1

0

Sets the display RAM address SEG output correspondence

0: normal, 1: reverse

Sets the LCD display normal/ reverse

0: normal, 1: reverse

Display all points

0: normal display

1: all points ON

Sets the LCD drive voltage bias ratio

0: 1/9 bias, 1: 1/7 bias (ST7565R)

Column address increment

At write: +1

At read: 0

0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write

(14) Reset

(15) Common output mode select

(16) Power control set

0 1 0 1 1 1 0 0 0 1 0 Internal reset

0 1 0

1 1 0 0 0

1

* * *

Select COM output scan direction

0: normal direction

1: reverse direction

0 1 0 0 0 1 0 1

Operating mode

Select internal power supply operating mode

(17) V

0

voltage regulator internal resistor ratio set

(18) Electronic volume mode set

Electronic volume register set

(19) Static indicator

ON/OFF

Static indicator register set

(20) Booster ratio set

(21) Power save

(22) NOP

0 1 0 0 0 1 0 0 Resistor ratio Select internal resistor ratio(Rb/Ra) mode

0 1 0

1 0 0 0 0 0 0 1

0 0 Electronic volume value

Set the V

0

output voltage electronic volume register

0

0

0

1

1

1

0

0

0

1 0 1 0 1 1 0 0

1

0 0 0 0 0 0 0 Mode

0: OFF, 1: ON

Set the flashing mode

1

0

1

0

1

0

1

0

1

0

0

0

0 0 step-up value select booster ratio

00: 2x,3x,4x

01: 5x

11: 6x

Display OFF and display all points ON compound command

0 1 0 1 1 1 0 0 0 1 1 Command for non-operation

(23) Test 0 1 0 1 1 1 1 * * * *

Command for IC test. Do not use this command

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C o m m a n d D e s c r r i i p t t i i o n

Instruction Setup: Reference

(1) Initialization

Note: With this IC, when the power is applied, LCD driving non-selective potentials V

2

and V

3

(SEG pin) and V

1 and V

4

(COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V

0

~ V

4

) and the V

SS

pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power.

1. When the built-in power is being used immediately after turning on the power:

* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.

Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit

*2: Command description; LCD bias setting

*3: Command description; ADC selection

*4: Command description; Common output state selection

*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V

0

voltage

*6: Description of functions; Power circuit & Command description; Electronic volume control

*7: Description of functions; Power circuit & Command description; Power control setting

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2. When the built-in power is not being used immediately after turning on the power:

* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.

Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit

*2: Command description; LCD bias setting

*3: Command description; ADC selection

*4: Command description; Common output state selection

*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V

0 voltage

*6: Description of functions; Power circuit & Command description; Electronic volume control

*7: Description of functions; Power circuit & Command description; Power control setting

*8: The power saver ON state can either be in sleep state or stand-by state.

Command description; Power saver START (multiple commands)

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(2) Data Display

Write Display Data (After Initialized)

Function setup by command

(user setting)

(2) Display Start Line Set ...*9

(3) Page Address Set ...*10

(4) Column Address Set ...*11

Data setup by Data Write

(6) Display Data Write ...*12

Function setup by command

(user setting)

(1) Display ON/OFF ...*13

End of Write Display Data

Notes: Reference items

*9: Command Description; Display start line set

*10: Command Description; Page address set

*11: Command Description; Column address set

*12: Command Description; Display data write

*13: Command Description; Display ON/OFF

Avoid displaying all the data at the data display start (when the display is ON) in white.

(3) Power OFF *14

Notes: Reference items

*14: The logic circuit of this IC’s power supply V

DD

- V

SS

controls the driver of the LCD power supply V

SS

–V

0 power supply V

DD

- V

SS

is cut off when the LCD power supply V

SS

–V

0

. So, if the

has still any residual voltage, the driver

(COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures:

• After turning off the internal power supply, make sure that the potential V

0

~ V

4

has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (V

DD

- V

SS

). 6. Description of Function, 6.7

Power Circuit

*15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power supply V

DD

- V

SS

is turned off. 7. Command Description (20) Power Save

*16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply

V

DD

- V

SS

is turned off. 7. Command Description (20) Power Save

Ver 1.5 53/72 2006/03/10

ST7565R

Refresh

It is recommended to turn on the refresh sequence regularly at a specified interval.

Precautions on Turning off the power

<Turning the power (V

DD

- V

SS

) off>

1) Power Save (The LCD powers (V

0

- V

SS

) are off.) → Reset input → Power (V

DD

- V

SS

) OFF

• Observe t

L

> t

H

.

• When t

L

< t

H

, an irregular display may occur.

Set t

L

on the MPU according to the software. t

H

is determined according to the external capacity C2 (smoothing capacity of

V

0

~ V

4

) and the driver’s discharging capacity.

Reset

Power Off

Power save t

L

V

DD

1.8V

RES

SEG

V

SS

Since the power (V

DD

-V

SS

) is cut off, the output comes not to be fixed.

COM

V

OUT

V0

V1

V2

V3

V4

V

SS t

H

Above Vth of the LCD Panel.

Under Vth of the LCD Panel.

Depends on the LCD Module characteristic (around 0.2~1V).

Ver 1.5 54/72 2006/03/10

ST7565R

<Turning the power (V

DD

- V

SS

) off : When command control is not possible.>

2) Reset (The LCD powers (V

DD

- V

SS

) are off.) → Power (V

DD

- V

SS

) OFF

• Observe t

L

> t

H

.

• When t

L

< t

H

, an irregular display may occur.

For t

L

, make the power (V

DD

- V

SS

) falling characteristics longer or consider any other method. t

H

is determined according to the external capacity C2 (smoothing capacity of V

0

to V

4

) and the driver’s discharging capacity.

Reset

Power Off t

L

V

DD

1.8V

RES

Since the power (V

DD

-V

SS

) is cut off,the output comes not be fixed.

SEG

V

SS

COM

V

SS

V

OUT

V0

V1

V2

V3

V4

Above Vth of the LCD Panel.

Under Vth of the LCD Panel.

Depends on the LCD Module characteristic (around 0.2~1V).

t

H

<Reference Data>

V

0

voltage falling (discharge) time ( t

H

) after the process of operation → power save → reset.

V

0

voltage falling (discharge) time ( t

H

) after the process of operation → reset.

100

V

DD

-V

SS

(V)

50

1.8

2.4

3.0

4.0

5.0

0

Ver 1.5

0.5

C2 : V

0

to V

4

capacity (uF)

Figure 31

55/72

1.0

2006/03/10

ST7565R

A b s o l l u t t e M a x i i m u m R a t t i i n g s

Unless otherwise noted, V ss

= 0V

Parameter

Power Supply Voltage

Power supply voltage (V

DD standard)

Power supply voltage (V

DD standard)

Power supply voltage (V

DD standard)

Operating temperature

Storage temperature Bare chip

Table 17

Symbol

V

DD

V

DD2

V

0

, V

OUT

V

1

, V

2

, V

3

, V

4

T

OPR

T

STR

Conditions

-0.3 ~ 3.6

-0.3 ~ 3.6

-0.3 ~ 13.5

-0.3 to V

0

–30 to +85

–65 to +150

Unit

V

V

V

V

°C

°C

V

0

V

1

to V

4

V

DD

V

DD

V

SS

V

SS

V

SS

System (MPU) side ST7565R chip side

Figure 30

Notes and Cautions

1. The V

DD2

, V

0 to V

4

and V

OUT

are relative to the V

SS

= 0V reference.

2. Insure that the voltage levels of V

1

, V

2

, V

3

, and V

4

are always such that V

OUT

≧ V

0

≧ V

1

≧ V

2

≧ V

3

≧ V

4

.

3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.

Ver 1.5 56/72 2006/03/10

ST7565R

D C C h a r r a c t t e r r i i s t t i i c s

Unless otherwise specified, V

SS

= 0 V, V

DD

= 3.0 V, Ta = –30 to 85°C

Table 18

Item Symbol Condition

Operating Voltage (1) V

DD

Min.

1.8

Rating

Typ.

Max.

3.3

Units

Applicable

Pin

V V

DD

*1

Operating Voltage (2) V

DD2

(Relative to V

SS

) 2.4 — 3.3 V V

DD

High-level Input Voltage

Low-level Input Voltage

High-level Output Voltage

V

IHC

V

ILC

V

OHC

I

OH

= –0.5 mA

Low-level Output Voltage

Input leakage current

V

OLC

I

OL

= 0.5 mA

I

LI

V

IN

= V

DD

or V

SS

Output leakage current

Liquid Crystal Driver ON

Resistance

I

LO

V

IN

= V

DD

or V

SS

R

ON

Ta = 25°C

(Relative to V

SS

)

V

0

= 13.0 V

V

0

= 8.0 V

Static Consumption Current I

SSQ

Output Leakage Current I

0Q

V

0

= 13.0 V

(Relative To V

SS

)

Input Terminal Capacitance

Oscillator

Frequency

Internal

Oscillator

External

Input

Internal

Oscillator

External

Input f

C f f

IN

CL

OSC

CL f

OSC

Ta = 25°C, f = 1 MHz

1/65 duty

1/33 duty

Ta = 25°C

1/49 duty

1/53 duty

1/55 duty

Ta = 25°C

Item Symbol

Table 19

Condition

Input voltage

Supply Step-up output voltage Circuit

Voltage regulator

Circuit Operating

Voltage

Voltage Follower

Circuit Operating

Voltage

V

DD2

V

OUT

(Relative To V

SS

)

V

OUT

(Relative To V

SS

)

V

0

(Relative To V

(Relative To V

SS

SS

)

)

Base Voltage VRS

Ta = 25°C, (Relative To V

–0.05%/°C

SS

)

0.8 x V

DD

V

SS

V

DD

0.2 x V

DD

V

V

0.8 x V

DD

— V

DD

V

V

SS

–1.0

–3.0

— 0.2 x V

DD

V

2.0

3.2

0.01

1.0

3.0

3.5

5.4

2

μA

μA

μA

*3

*3

*4

*6

SEGn

COMn *7

V

DD

*4

*5

, V

DD2

17

17

25

25

Min.

2.4

6.0

4.0

2.07

0.01

5.0

20

20

30

30

Rating

Typ.

2.10

10

8.0

24

24

35

35

Max.

3.3

13.5

13.5

13.5

2.13

μA pF kHz kHz kHz kHz

V

0

*8

CL

*8

CL

Units

Applicable

Pin

V

V

V

V

V

V

V

DD

V

V

OUT

OUT

0

*10

* 9

Ver 1.5 57/72 2006/03/10

ST7565R

• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used .

Table 20

Test pattern Symbol Condition

Min.

Rating

Typ. Max.

Units Notes

Display Pattern

OFF

I

DD

V

DD

= 3.0 V,

V

0

– V

SS

= 11.0 V

— 16 27 μA

*11

Display Pattern

Checker

I

DD

V

0

V

DD

– V

= 3.0 V,

SS

= 11.0 V

— 19 32

• Dynamic Consumption Current : During Display, with the Internal Power Supply ON

Table 21

Test pattern Symbol Condition

Min.

Rating

Typ.

Normal Mode — 90

Display

Pattern OFF

I

DD

V

DD

= 3.0 V,

Quad step-up voltage.

V

0

– V

SS

= 11.0 V High-Power Mode — 128

μA

Max.

130

193

μA

*11

Units Notes

*12

Display

Pattern

Checker

I

DD

V

DD

= 3.0 V,

Quad step-up voltage.

V

0

– V

SS

= 11.0 V

Normal Mode — 100 147

μA

*12

High-Power Mode — 135 205

• Consumption Current at Time of Power Saver Mode : VDD = 3.0 V

Table 22

Item

Sleep mode

Symbol

I

DD

Condition

Ta = 25°C

Min.

Rating

Typ.

0.1

Max.

4

Units

μA

Notes

Standby Mode I

DD

Ta = 25°C — 5 10

• The Relationship Between Oscillator Frequency f

OSC

, Display Clock Frequency f

CL

and the Liquid Crystal Frame Rate

Frequency f

FR

Table 23

Item f

CL f

FR

1/65 DUTY

1/49 DUTY

1/33 DUTY

1/55 DUTY

Used internal oscillator circuit

Used external display clock

Used internal oscillator circuit

Used external display clock

Used internal oscillator circuit

Used external display clock

Used internal oscillator circuit f

OSC

/ 4

External input (f

CL

) f

OSC

/ 4

External input (f

CL

) f

OSC

/ 8

External input (f

CL

) f

OSC

/ 4

External input (f

CL

)

Used external display clock

Used internal oscillator circuit f

OSC

/ 4

1/53 DUTY

Used external display clock External input (f

CL

)

(f

FR

is the liquid crystal alternating current period, and not the FR signal period.) f

OSC

/ (4*65) f

CL

/ 260 f

OSC

/ (4*49) f

CL

/ 196 f

OSC

/ (8*33) f

CL

/ 264 f

OSC

/ (4*55) f

CL

/ 220 f

OSC

/ (4*53) f

CL

/ 212

Ver 1.5 58/72 2006/03/10

ST7565R

References for items market with *

*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed.

*2 The operating voltage range for the V

SS

system and the V

0

system is. This applies when the external power supply is

being used.

*3 The A0, D0 to D5, D6 (SCL), D7 (SI), /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S, C86, P/S, /DOF, /RES, IRS, and

/HPM terminals.

*4 The D0 to D7, FR, FRS, /DOF, and CL terminals.

*5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S, /RES, IRS, and /HPM terminals.

*6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state.

*7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V

1

, V

2

, V

3

, and V

4

). These are specified for the operating voltage (3) range.

R

ON

= 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)

*8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency.

*9 The V

0

voltage regulator circuit regulates within the operating voltage range of the voltage follower.

*10 This is the internal voltage reference supply for the V approximately –0.05%/°C.

0

voltage regulator circuit. In the ST7565R, the temperature range

*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.

The ST7565R is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity.

Applicable only when there is no access from the MPU.

*12 It is the value on a ST7565R having the V

REG

temperature gradient is –0.05%/°C when the V

0

voltage regulator internal resistor is used.

Ver 1.5 59/72 2006/03/10

ST7565R

T i i m i i n g C h a r r a c t t e r r i i s t t i i c s

System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)

A0 t

AW8

CS1

(CS2="1") t

CYC8 t

CCLR

,t

CCLW

WR,RD t

AH8 t

CCHR

,t

CCHW t

DS8 t

DH8

D0 to D7

(Write) t

ACC8

D0 to D7

(Read)

Item

Address hold time

Address setup time

System cycle time

Enable L pulse width (WRITE)

Enable H pulse width (WRITE)

Enable L pulse width (READ)

Enable H pulse width (READ)

WRITE Data setup time

WRITE Address hold time

READ access time

READ Output disable time

Figure 37

Table 24

Signal

Symbol

A0

WR

RD t

AH8 t

AW8 t

CYC8 t

CCLW t

CCHW t

CCLR t

CCHR t

DS8 t

DH8

D0 to D7 t

ACC8 t

OH8

Condition

C

L

= 100 pF

C

L

= 100 pF t

OH8

(V

DD

= 3.3V, Ta = –30 to 85°C)

Rating

Min. Max.

Units

0 —

0

240

80

80

140

80

— Ns

40

0

5

70

50

Ver 1.5 60/72 2006/03/10

ST7565R

Item

Address hold time

Address setup time

System cycle time

Enable L pulse width (WRITE)

Enable H pulse width (WRITE)

Enable L pulse width (READ)

Enable H pulse width (READ)

Signal

A0

WR

RD

Table 25

Symbol t

AH8 t

AW8 t

CYC8 t

CCLW t

CCHW t

CCLR t

CCHR

Condition

(V

DD

= 2.7V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

0 —

0

400

220

180

220

180

— ns

WRITE Data setup time

WRITE Address hold time

READ access time

READ Output disable time t

DS8 t

DH8

D0 to D7 t

ACC8 t

OH8

C

L

= 100 pF

C

L

= 100 pF

40

0

10

140

100

Table 26

Item

Signal

Symbol Condition

(V

DD

= 1.8V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

0 — Address hold time

Address setup time

A0 t

AH8 t

AW8

0 —

System cycle time

Enable L pulse width (WRITE)

Enable H pulse width (WRITE)

Enable L pulse width (READ)

Enable H pulse width (READ)

WR

RD t

CYC8 t

CCLW t

CCHW t

CCLR t

CCHR

640

360

280

360

— ns

280

WRITE Data setup time t

DS8

80 —

WRITE Address hold time t

DH8

0 —

D0 to D7

READ access time t

ACC8

C

L

= 100 pF — 240

READ Output disable time t

OH8

C

L

= 100 pF 10 200

*1 The input signal rise time and fall time (

( t r

, t f

) is specified at 15 ns or less. When the system cycle time is extremely fast, t r

+ t f

) ≦ ( t

CYC8

– t

CCLW

– t

CCHW

) for ( t r

+ t f

) ≦ ( t

CYC8

– t

CCLR

– t

CCHR

) are specified.

*2 All timing is specified using 20% and 80% of V

DD

as the reference.

*3 t

CCLW

and t

CCLR

are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.

Ver 1.5 61/72 2006/03/10

ST7565R

System Bus Read/Write Characteristics 2 (For the 6800 Series MPU)

A0

R/W t

AW6

CS1

(CS2="1") t

CYC6 tew

LR

,tew

LW

E t

AH6 tew

HR

,tew

HW t

DS6 t

DH6

D0 to D7

(Write) t

ACC6

D0 to D7

(Read)

Item

Address hold time

Address setup time

System cycle time

Enable L pulse width (WRITE)

Enable H pulse width (WRITE)

Enable L pulse width (READ)

Enable H pulse width (READ)

WRITE Data setup time

WRITE Address hold time

READ access time

READ Output disable time

Figure 38

Table 27

Signal

Symbol

A0

WR t

AH6 t

AW6 t

CYC6 t

EWLW t

EWHW

RD t

EWLR t

EWHR t

DS6 t

DH6

D0 to D7 t

ACC6 t

OH6

Condition

C

L

= 100 pF

C

L

= 100 pF t

OH6

(V

DD

= 3.3V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

0 —

0 —

240

80

80

80

140

40

0

5

70

50 ns

Ver 1.5 62/72 2006/03/10

ST7565R

Item

Address hold time

Address setup time

System cycle time

Enable L pulse width (WRITE)

Enable H pulse width (WRITE)

Enable L pulse width (READ)

Enable H pulse width (READ)

Signal

A0

WR

RD

Table 28

Symbol t

AH6 t

AW6 t

CYC6 t

EWLW t

EWHW t

EWLR t

EWHR

Condition

(V

DD

= 2.7V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

0 —

0

400

220

180

220

180

— ns

WRITE Data setup time

WRITE Address hold time

READ access time

READ Output disable time t

DS6 t

DH6

D0 to D7 t

ACC6 t

OH6

C

L

= 100 pF

C

L

= 100 pF

40

0

10

140

100

Table 29

Item

Signal

Symbol Condition

(V

DD

= 1.8V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

0 — Address hold time

Address setup time

A0 t

AH6 t

AW6

0 —

System cycle time

Enable L pulse width (WRITE)

Enable H pulse width (WRITE)

Enable L pulse width (READ)

Enable H pulse width (READ)

WR

RD t

CYC6 t

EWLW t

EWHW t

EWLR t

EWHR

640

360

280

360

— ns

280 —

WRITE Data setup time t

DS6

80 —

WRITE Address hold time t

DH6

0 —

D0 to D7

READ access time t

ACC6

C

L

= 100 pF — 240

READ Output disable time t

OH6

C

L

= 100 pF 10 200

*1 The input signal rise time and fall time (

( t r

, t f

) is specified at 15 ns or less. When the system cycle time is extremely fast, t r

+ t f

) ≦ ( t

CYC6

– t

EWLW

– t

EWHW

) for ( t r

+ t f

) ≦ ( t

CYC6

– t

EWLR

– t

EWHR

) are specified.

*2 All timing is specified using 20% and 80% of V

DD

as the reference.

*3 t

EWLW

and t

EWLR

are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.

Ver 1.5 63/72 2006/03/10

ST7565R

The 4-line SPI Interface

CS1

(CS2="1")

A0

SCL

SI

Item

4-line SPI Clock Period

SCL “H” pulse width

SCL “L” pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS-SCL time

CS-SCL time

Item

4-line SPI Clock Period

SCL “H” pulse width

SCL “L” pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS-SCL time

CS-SCL time

Ver 1.5 t f t

CCSS t

CSH t

SAS t

SAH t

SCYC t

SLW t

SHW t r t

SDS t

SDH

Figure 39

Table 30

Signal

SCL

A0

SI

CS

Symbol

T scyc

T shw

T

SLW

T

SAS

T sah

T sds

T

SDH

T css

T csh

Table 31

Signal

SCL

A0

SI

CS

Symbol

T scyc

T

SHW

T

SLW

T

SAS

T

SAH

T

SDS

T

SDH

T

CSS

T

CSH

Condition

(V

DD

= 3.3V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

50 —

25

25

20

10

20

10

20

40

— ns

Condition

(V

DD

= 2.7V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

100 —

50

50

30

20

30

20

30

60

— ns

64/72 2006/03/10

ST7565R

Table 32

Item

Signal

Symbol

4-line SPI Clock Period

SCL “H” pulse width SCL

T

SCYC

T

SHW

SCL “L” pulse width

Address setup time

T

SLW

T

SAS

Data setup time

A0

Address hold time

SI

T

SAH

T

SDS

T

SDH

Data hold time

CS-SCL time

T

CSS

CS

CS-SCL time

T

CSH

*1 The input signal rise and fall time ( t r, t f) are specified at 15 ns or less.

*2 All timing is specified using 20% and 80% of V

DD

as the standard.

Reset Timing

Condition t

RW

RES

(V

DD

= 1.8V,Ta = –30 to 85°C)

Rating

Min. Max.

Units

200 —

80

80

60

30

60

— ns

30

40

100

Internal status

During reset

Figure 41

Table 36

Item

Reset time

Reset “L” pulse width

Signal

Symbol

/RES t

R t

RW

Condition

Table 37

Item

Reset time

Reset “L” pulse width

Signal

Symbol

/RES t t

R

RW

Condition

Table 38

Item

Signal

Symbol Condition

Reset time t

R

Reset “L” pulse width /RES t

RW

*1 All timing is specified with 20% and 80% of V

DD

as the standard. t

R

Reset complete

Min.

(V

DD

= 3.3V,Ta = –30 to 85°C)

Rating

Typ. Max.

Units

1.0

1.0

— us us

Min.

(V

DD

= 2.7V,Ta = –30 to 85°C)

Rating

Typ. Max.

Units

— — 2.0 us

2.0 — — us

Min.

(V

DD

= 1.8V,Ta = –30 to 85°C)

Rating

Typ. Max.

Units

— — 3.0 us

3.0 — — us

Ver 1.5 65/72 2006/03/10

ST7565R

T h e M P U I

I n t t e r r f f a c e

(

(

R e f f e r r e n c e

E x a m p l l e s

)

)

The ST7565R Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the 4-line SPI interface it is possible to operate the ST7565R series chips with fewer signal lines.

The display area can be enlarged by using multiple ST7565R Series chips. When this is done, the chip select signal can be used to select the individual ICs to access.

(1) 8080 Series MPUs

V

DD

V

CC

A0

A1 to A7

IORQ

GND

DO to D7

RD

WR

RES

Decoder

A0

CS1

CS2

V

DD

C86

DO to D7

RD

WR

RES

V

SS

P/S

RESET

(2) 6800 Series MPUs

Figure 42-1

V

SS

V

DD

V

CC

A0

A1 to A15

VMA

GND

DO to D7

E

R/W

RES

Decoder

A0

CS1

CS2

V

DD

C86

DO to D7

E

R/W

RES

V

SS

P/S

RESET

V

SS

Figure 42-2

(3) Using the 4-line SPI Interface

V

DD or V

SS

V

CC

A0

A1 to A7 Decoder

A0

CS1

CS2

V

DD

C86

GND

Port 1

Port 2

RES

SI

SCL

RES

V

SS

P/S

RESET

V

SS

Figure 42-3

Ver 1.5 66/72 2006/03/10

ST7565R

C o n n e c t t i i o n s B e t t w e e n L C D D r r i i v e r r s

(

( R e f f e r r e n c e E x a m p l l e

)

)

The liquid crystal display area can be enlarged with ease through the use of multiple ST7565R Series chips. Use the same equipment type.

(1) Single-chip Structure

Ver 1.5

Figure 43-1

67/72 2006/03/10

ST7565R

(2) Double-chip Structure

Ver 1.5

Figure 43-2

68/72 2006/03/10

ST7565R

A p p l l i i c a t t i i o n N o t t e s

(1) 4-line interface

, 4x booster, 65 duty, internal resistor, high power mode, internal oscillator, master mode

Ver 1.5 69/72 2006/03/10

ST7565R

(2) 80 interface

, 5x booster, 49 duty, internal resistor, high power mode, internal oscillator, master mode

Ver 1.5 70/72 2006/03/10

ST7565R

(3) 68 interface

, 6x booster, 55 duty, internal resistor, high power mode, internal oscillator, master mode

Ver 1.5 71/72 2006/03/10

ST7565R

C h a n g e N o t t e s

:

:

2005/03/24 Ver 0.1

l

Preliminary

2005/05/20 Ver 0.2

l Bump Height

2005/08/10 Ver 0.3 l Shipping Forms l Pad Arrangement, Bump Height, Bump Pitch, Bump Height l Pad Names- remove ”:P”, “:g”, rename FUSE, VSSF as TEST l Connections Between LCD Drivers

2005/09/29 Ver 0.4 l Application Notes l Unused Data Pin In 4-Line SPI Fixed To ‘H’ l ITO Resister Limitation l Modify the Absolute Maximum Ratings. l Modify the operating range of VDD, VDD2, VOUT and

V

0

. l

Modify the description of features. l Modify the Operating Temperature. l Modify the Ta value of DC Characteristics and Reset Timing. l Remove redundant features on Page 2.

2005/10/20 Ver 1.0 l Remove Preliminary l Modify the Pad Arrangement(COG) on Page 2. l Modify the I/O PIN ITO Resister Limitation on Page 22.

2005/10/21 Ver 1.1 l Modify the Operating Temperature

2005/11/07 Ver 1.2 l Unused Data Pin In 4-Line C86 Fixed To ‘H’ l Unused Data Pin In 4-Line /RD Fixed To ‘H’ l Unused Data Pin In 4-Line /WR Fixed To ‘H’

2005/11/25 Ver 1.3 l Modify the flow chart on Page 46, 47 and 49.

2006/02/13 Ver 1.4 l Modify the description of DC characteristics. l

Modify function description. l Redraw figures. l Redraw the PAD DIAGRAM. l Highlight the HPM (High Power Mode) description. l Put emphasis on the power OFF procedure (Page 54-55).

2006/03/10 Ver 1.5 l Fix Ver. 1.4: Booster Circuit mistake (Booster X6, Page 32).

Ver 1.5 72/72 2006/03/10

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