Renesas PCA4738L-64A Technical information

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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
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Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3886 group is the 8-bit microcomputer based on the 740 family core technology.
The 3886 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, D-A converters, system data bus interface function,
watchdog timer, and comparator circuit.
The multi-master I2C bus interface can be added by option.
FEATURES
<Microcomputer mode>
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.4 µs
(at 10 MHz oscillation frequency)
●Memory size
ROM ................................................................. 32K to 60K bytes
RAM ............................................................... 1024 to 2048 bytes
●Programmable input/output ports ............................................ 72
●Software pull-up resistors ................................................. Built-in
●Interrupts ................................................. 21 sources, 16 vectors
(Included key input interrupt)
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●PWM output circuit ....................................................... 14-bit ✕ 2
●Bus interface .................................................................... 2 bytes
●I2C bus interface (option) ............................................. 1 channel
●A-D converter ............................................... 10-bit ✕ 8 channels
●D-A converter ................................................. 8-bit ✕ 2 channels
●Comparator circuit ...................................................... 8 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 10 MHz oscillation frequency)
In middle-speed mode ........................................... 2.7 to 5.5 V(*)
(at 10 MHz oscillation frequency)
In low-speed mode ............................................... 2.7 to 5.5 V (*)
(at 32 kHz oscillation frequency)
(*: 4.0 to 5.5 V for Flash memory version)
●Power dissipation
In high-speed mode .......................................................... 40 mW
(at 10 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Memory expansion possible (only for M38867M8A/E8A)
●Operating temperature range .................................... –20 to 85°C
<Flash memory mode>
●Supply voltage ................................................. VCC = 5 V ± 10 %
●Program/Erase voltage ............................... VPP = 11.7 to 12.6 V
●Programming method ...................... Programming in unit of byte
●Erasing method
Batch erasing ........................................ Parallel/Serial I/O mode
Block erasing .................................... CPU reprogramming mode
●Program/Erase control by software command
●Number of times for programming/erasing ............................ 100
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
1. The flash memory version cannot be used for application embedded in the MCU card.
2. Power source voltage Vcc of the flash memory version is 4.0
to 5.5 V.
APPLICATION
Household product, consumer electronics, communications, note
book PC, etc.
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
45
44
43
42
41
47
46
49
48
50
53
52
51
55
54
58
57
56
60
59
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/P3REF/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
PIN CONFIGURATION (TOP VIEW)
40
39
38
37
36
35
34
33
32
31
30
29
28
61
62
63
64
65
66
67
68
69
70
71
M38867M8A-XXXHP
M38867E8AHP
72
73
74
75
27
26
25
76
77
78
24
23
22
21
20
19
17
18
15
16
14
11
12
13
8
9
10
7
6
4
5
2
3
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
1
79
80
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
VPP
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
: PROM version
Note: The pin number and the position of the
function pin may change by the kind of
package.
Package type : 80P6Q-A
Fig. 1 M38867M8A-XXXHP, M38867E8AHP pin configuration
69
70
71
72
73
74
75
8
9
10
11
12
13
14
15
16
17
6
7
44
43
42
41
34
33
32
31
30
29
28
27
26
25
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
VPP
CNVSS
P42/INT0/OBF00
P62/AN2
P61/AN1
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
P44/RXD
P43/INT1/OBF01
4
5
76
77
78
79
80
40
39
38
37
36
35
18
19
20
21
22
23
24
M38867E8AFS
47
46
45
53
52
51
50
49
48
57
56
55
54
65
66
67
68
1
2
3
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
60
59
58
64
63
62
61
P30/PWM00
P31/PWM10
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/P3REF/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
PIN CONFIGURATION (TOP VIEW)
Package type : 80D0
Fig. 2 M38867E8AFS pin configuration
2
Note: The pin number and the position of
the function pin may change by the
kind of package.
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
41
44
43
42
46
45
50
49
48
47
40
39
38
37
36
35
34
33
61
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
VPP
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
20
19
18
17
16
15
14
13
12
11
9
10
6
7
8
3
32
31
30
29
28
27
26
25
24
23
22
21
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
4
5
M38869MFA-XXXGP/HP
M38869FFAGP/HP
2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
57
56
55
54
53
52
51
60
59
58
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6S-A/80P6Q-A
: Flash memory version
Note: The pin number and the position of the
function pin may change by the kind of
package.
Fig. 3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration
3
4
Fig. 4 Functional block diagram
XCIN
XCOUT
Sub-clock Sub-clock
input
output
2
P7(8)
2 3 4 5 6 7 8 9
I/O port P7
63 64 65 66 67 68 69 70
I/O port P8
AVSS
VREF
I/O port P5
I/O port P6
P5(8)
D-A
converter
1(8)
PC H
10 11 12 13 14 15 16 17
P6(8)
D-A
converter 2
(8)
ROM
30
VSS
74 75 76 77 78 79 80 1
A-D
converter
(10)
RAM
72 73
INT21,
INT31,
INT41
SI/O2(8)
P8(8)
D Q7
to
D Q0
Bus interface
S CL S DA
I C
Reset
Clock generating circuit
29
Main-clock
output
XOUT
Watchdog
timer
28
Main-clock
input
XIN
PS
INT20,
INT30,
INT40
INT0,
INT1
I/O port P4
18 19 20 21 22 23 26 27
P4(8)
PC L
S
Y
X
A
SI/O1(8)
C P U
71
VCC
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6Q-A, 80P6S-A)
XCOUT
XCIN
P3(8)
CNTR1
I/O port P3
I/O port P2
I/O port P1
39 40 41 42 43 44 45 46
P1(8)
P0(8)
I/O port P0
47 48 49 50 51 52 53 54
PWM10,
PWM11
PWM00,
PWM01
31 32 33 34 35 36 37 38
P2(8)
PWM1(14)
Timer Y( 8 )
Timer X( 8 )
Timer 2( 8 )
Timer 1( 8 )
PWM0(14)
Prescaler Y(8)
Prescaler X(8)
Prescaler 12(8)
Key-on
wake-up
CNTR0
24
CNVSS
55 56 57 58 59 60 61 62
Comparator
25
RESET
Reset input
P3REF
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
VCC, VSS
Functions
Name
Power source
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
CNVSS
CNVSS input
•If this pin is connected to Vcc, the internal ROM is inhibited and an external memory is accessed.
•In the flash memory version, connected to VSS.
•In the EPROM version or the flash memory version, this pin functions as the VPP power source input pin.
VREF
Reference voltage
AVSS
Analog power source
RESET
Reset input
XIN
Clock input
XOUT
Clock output
P00/P3REF
I/O port P0
P01–P07
•Reference voltage input pin for A-D and D-A converters.
•Analog power source input pin for A-D and D-A converters.
•Connect to VSS.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•Comparator reference power source
•I/O direction register allows each pin to be individually input pin
programmed as either input or output.
•When the external memory is used, these pins are used as the address bus.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
P10–P17
I/O port P1
•When the external memory is used, these pins are used as the address bus.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
P20–P27
I/O port P2
•When the external memory is used, these pins are used as the data bus.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P24 to P27 (4 bits) are enabled to output large current for LED drive (only in single-chip mode).
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
P30/PWM00
P31/PWM10
•When the external memory is used, these pins are
used as the control bus.
I/O port P3
•CMOS compatible input level.
•CMOS 3-state output structure.
P32–P37
•Key-on wake-up input pin
•Comparator input pin
•PWM output pin
•Key-on wake-up input pin
•Comparator input pin
•These pins function as key-on wake-up and comparator input.
•These pins are enabled to control pull-up.
5
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
Functions
Name
•8-bit I/O port with the same function as port P0.
Function except a port function
•Sub-clock generating circuit I/O
pins
P40/XCOUT
P41/XCIN
<Input level>
(Connect a resonator.)
P42/INT0
/OBF00
P43/INT1
/OBF01
P40, P41 : CMOS input level
P42–P46 : CMOS compatible input level or TTL input level
P47 : CMOS compatible input level or TTL input
level in the bus interface function
•Interrupt input pins
I/O port P4
•Bus interface function pins
<Output structure>
P40, P41, P47 : CMOS 3-state output structure
P42–P46 : CMOS 3-state output structure or Nchannel open-drain output structure
P44/RxD
P45/TxD
•Serial I/O1 function pins
P46/SCLK1
/OBF10
P47/SRDY1
/S1
•Regardless of input or output port, P4 2 to P46 can
be input every pin level.
•When P4 2 and P43 are used as output port, the
function which makes P4 2 and P4 3 clear to “0”
when the host CPU reads the output data bus
buffer 0 can be added.
•Serial I/O1 function pins
P50/A0
•8-bit I/O port with the same function as port P0.
•Bus interface function pins
P51/INT20
/S0
P52/INT30
/R
P53/INT40
/W
•CMOS compatible input level.
•CMOS 3-state output structure.
•P50 to P53 can be switched between CMOS compatible input level or TTL input level in the bus
interface function.
•Timer X, timer Y function pins
P56/DA1
/PWM01
P57/DA2
/PWM11
•D-A converter output pin
•PWM output pin
I/O port P6
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•A-D converter output pin
•CMOS 3-state output structure.
•8-bit I/O port with the same function as port P0.
P70/SIN2
P71/SOUT2
P72/SCLK2
P73/SRDY2
/INT21
P74/INT31
P75/INT41
•Interrupt input pins
•Bus interface function pins
I/O port P5
P54/CNTR0
P55/CNTR1
P60/AN0–
P67/AN7
•Bus interface function pins
I/O port P7
P70–P75 : CMOS compatible input level or TTL input level
•Serial I/O2 function pin
P76, P77 : CMOS compatible input level or
SMBUS input level in the I2C-BUS interface function, N-channel open-drain
output structure
•Serial I/O2 function pin
•Regardless of input or output port, P7 0 to P75 can
be input every pin level.
P76/SDA
P77/SCL
•Interrupt input pin
•Interrupt input pin
•I2C-BUS interface function pin
•8-bit I/O port with the same function as port P0.
P80/DQ0–
P87/DQ7
•CMOS compatible input level.
I/O port P8
•CMOS 3-state output structure.
•CMOS compatible input level or TTL input level in
the bus interface function.
6
•Bus interface function pin
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product name
M3886
7
M
8 A-
XXX
HP
Package type
HP : 80P6Q-A
GP : 80P6S-A
FS : 80D0
ROM number
Omitted in the one time PROM version shipped in blank,
the EPROM version and the flash memory version.
A– : High-speed version
– is omitted in the One Time PROM version shipped in blank,
the EPROM version and the flash memory version.
ROM/PROM size
1 : 4096 bytes
9: 36864 bytes
2 : 8192 bytes
A : 40960 bytes
B : 45056 bytes
3 : 12288 bytes
C: 49152 bytes
4 : 16384 bytes
D: 53248 bytes
5 : 20480 bytes
E : 57344 bytes
6 : 24576 bytes
F : 61440 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved
areas ; they cannot be used.
However, they can be programmed or erased in the EPROM
version and the flash memory version, so that the users can
use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 5 Part numbering
7
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 3886 group as follows.
80P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP
80P6S-A ................................... 0.65mm pitch plastic molded QFP
80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, EPROM and flash
memory version.
The pin number and the position of the function pin may change
by the kind of package.
Memory Size
ROM size ........................................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion
ROM size (bytes)
ROM
external
: Mass production
60K
M38869FFA/MFA
48K
M38869MCA
32K
M38869M8A
M38867E8A/M8A
28K
24K
20K
16K
12K
8K
384
512
640
768
896
1024
1152
1280
1408
1536
2048
3072
4032
RAM size (bytes)
Fig. 6 Memory expansion plan
Currently products are listed below.
As of Jan. 2000
Table 3 Support products
Product name
M38867M8A-XXXHP
M38867E8A-XXXHP
M38867E8AHP
M38867E8AFS
M38869M8A-XXXHP
M38869M8A-XXXGP
M38869MCA-XXXHP
M38869MCA-XXXGP
M38869MFA-XXXHP
M38869MFA-XXXGP
M38869FFAHP
M38869FFAGP
8
(P) ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
Package
1024
80P6Q-A
2048
80D0
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
32768 (32638)
49152 (19022)
61440 (61310)
Remarks
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
Flash memory version
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3886 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
processor mode bits specifying the chip operation mode, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode (Note)
1 0 : Microprocessor mode (Note)
1 1 : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Note: This mode is not available for M38869M8A/MCA/MFA and the flash memory version.
Fig. 7 Structure of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
RAM
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
ROM
Access to this area with only 2 bytes is possible in the special
page addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. Program/Erase of the reserved ROM area is possible in the EPROM
version and the flash memory version
RAM area
RAM size
(bytes)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
000016
SFR area
Zero page
004016
RAM
010016
XXXX16
Not used
0FFE16
SFR area (Note 1)
0FFF16
YYYY16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
Fig. 8 Memory map diagram
10
Reserved ROM area
(Note 2) (128 bytes)
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
FFFF16
Special page
Reserved ROM area
(Note 2)
Notes 1: This area is SFR in M38869FFA.
This area is Reserved in M38869MFA/MCA/M8A.
This area is not used in M38867M8A/E8A.
2: This area is usable in EPROM version and flash memory version.
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Data bas buffer register 0 (DBB0)
000916
Port P4 direction register (P4D)
002916
Data bas buffer status register 0 (DBBSTS0)
000A16
Port P5 (P5)
002A16
Data bas buffer control register (DBBCON)
000B16
Port P5 direction register (P5D)
002B16
Data bas buffer register 1 (DBB1)
000C16
Port P6 (P6)
002C16
Data bas buffer status register 1 (DBBSTS1)
000D16
Port P6 direction register (P6D)
002D16
Comparator data register (CMPD)
000E16
Port P7 (P7)
002E16
Port control register 1 (PCTL1)
000F16
Port P7 direction register (P7D)
002F16
Port control register 2 (PCTL2)
001016
Port P8 (P8)/Port P4 input register (P4I)
003016
PWM0H register (PWM0H)
001116
Port P8 direction register (P8D)/Port P7 input register (P7I)
003116
PWM0L register (PWM0L)
001216
I2C data shift register (S0)
003216
PWM1H register (PWM1H)
001316
I2C address register (S0D)
003316
PWM1L register (PWM1L)
001416
I2C status register (S1)
003416
AD/DA control register (ADCON)
001516
I2C control register (S1D)
003516
A-D conversion register 1 (AD1)
001616
I2C clock control register (S2)
003616
D-A1 conversion register (DA1)
001716
I2C start/stop condition control register (S2D)
003716
D-A2 conversion register (DA2)
001816
Transmit/Receive buffer register (TB/RB)
003816
A-D conversion register 2 (AD2)
001916
Serial I/O1 status register (SIO1STS)
003916
Interrupt source selection register (INTSEL)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2 (IREQ2)
001E16
Watchdog timer control register (WDTCON)
003E16
Interrupt control register 1 (ICON1)
001F16
Serial I/O2 register (SIO2)
003F16
Interrupt control register 2 (ICON2)
0FFE16
Flash memory control register (FCON)
(Note)
0FFF16
Flash command register (FCMD)
(Note)
Note: Flash memory version only
Fig. 9 Memory map of special function register (SFR)
11
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
When the P8 function select bit of the port control register 2 (address 002F16) is set to “1”, read from address 0010 16 becomes
the port P4 input register, and read from address 001116 becomes
the port P7 input register.
As the particular function, value of P42 to P46 pins and P70 to P75
pins can be read regardless of setting direction registers, by reading the port P4 input register (address 001016) or the port P7 input
register (address 001116) respectively.
Table 4 I/O port function (1)
Pin
Name
Input/Output
P00/P3REF
CMOS compatible
input level
CMOS 3-state output
or N-channel opendrain output
Port P0
P01–P07
P10–P17
Port P1
P20–P27
Port P2
I/O Structure
P30/PWM00
P31/PWM10
CMOS compatible
input level
CMOS 3-state output
Port P3
Non-Port Function
Address low-order byte
output
Analog comparator
power source input pin
Address low-order byte
output
Address high-order
byte output
Data bus I/O
Control signal I/O
PWM output
Key-on wake up input
Comparator input
Related SFRs
Ref.No.
CPU mode register
Port control register 1
Serial I/O2 control
register
(1)
CPU mode register
Port control register 1
(2)
CPU mode register
(3)
CPU mode register
Port control register 1
AD/DA control register
(4)
(5)
P32–P37
Control signal I/O
Key-on wake up input
Comparator input
CPU mode register
Port control register 1
(6)
P40/XCOUT
P41/XCIN
Sub-clock generating
circuit
CPU mode register
(7)
(8)
External interrupt input
Bus interface function
I/O
Interrupt edge selection
register
Port control register 2
(9)
(10)
Serial I/O1 function input
Serial I/O1 control
register
Port control register 2
(11)
P42/INT0/
OBF00
P43/INT1/
OBF01
Input/output,
individual bits
CMOS compatible
input level or TTL
input level
CMOS 3-state output
or N-channel opendrain output
P44/RXD
P45/TXD
Port P4
Serial I/O1 function I/O
Bus interface function
output
P46/SCLK1
/OBF10
P47/SRDY1
/S1
12
Serial I/O1 function output
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
Serial I/O1 function output
Bus interface function
input
Serial I/O1 control
register
UART control register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
(12)
(13)
(14)
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 I/O port function (2)
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRs
Ref.No.
Bus interface function
input
Data bus buffer control
register
(15)
External interrupt input
Bus interface function
input
Interrupt edge selection
register
Data bus buffer control
register
(16)
Timer X, timer Y function I/O
Timer XY mode register
(17)
D-A converter output
PWM output
AD/DA control register
UART control register
(18)
(19)
A-D converter input
AD/DA control register
(20)
Serial I/O2 function I/O
Serial I/O2 control
register
Port control register 2
(21)
(22)
(23)
Serial I/O2 function output
Bus interface function
input
Serial I/O2 control
register
Port control register 2
(24)
External interrupt input
Interrupt edge selection
register
Port control register 2
(25)
P76/SDA
P77/SCL
CMOS compatible
input level
N-channel open-drain
output
(when selecting I2CBUS interface
function)
CMOS compatible
input level or SMBUS
input level
I2C-BUS interface function I/O
I2C control register
(26)
(27)
P80/DQ0–
P87/DQ7
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
Bus interface function
I/O
Data bus buffer control
register
(28)
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
P50/A0
P51/INT20
/S0
P52/INT30
/R
P53/INT40
/W
Port P5
P54/CNTR0
P55/CNTR1
P56/DA1/
PWM01
P57/DA2/
PWM11
P60/AN0–
P67/AN7
CMOS compatible
input level
CMOS 3-state output
Port P6
P70/SIN2
P71/SOUT2
P72/SCLK2
Input/output,
individual bits
P73/SRDY2/
INT21
P74/INT31
P75/INT41
CMOS compatible
input level or TTL
input level
N-channel open-drain
output
Port P7
Port P8
Notes1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer
to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
13
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P00
(2) Ports P01–P07,P1
P00–P03 output
structure selection bit
P00–P03,
P04–P07,
P10–P13,
P14–P17 output structure
selection bits
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Comparator reference power source input
Comparator reference input
pin select bit
(3) Port P2
(4) Port P30
Direction
register
Data bus
P30–P33 pull-up control bit
PWM0 output pin selection bit
PWM0 enable bit
Direction
register
Port latch
Data bus
Port latch
PWM00 output
(5) Port P31
P30–P33 pull-up control bit
Comparator
input
Key-on wake-up
(6) Ports P32–P37
PWM1 output pin selection bit
PWM1 enable bit
P30–P33,
P34–P37 pull-up control bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
PWM10 output
Port latch
Comparator
input
Key-on wake-up
Comparator
input
Key-on wake-up
(7) Port P40
(8) Port P41
Port XC switch bit
Port XC switch bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Oscillator
Port P41
Port XC switch bit
Fig. 10 Port block diagram (1)
14
Sub-clock generating circuit input
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P42
(10) Port P43
P4 output structure selection bit
P4 output structure selection bit
OBF00 output enable bit
OBF01 output enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
✻1
✻1
✻2
✻2
OBF01 output
OBF00 output
INT1 interrupt input
INT0 interrupt input
(11) Port P44
(12) Port P45
P4 output structure selection bit
Serial I/O1 enable bit
Receive enable bit
P45/TXD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
✻1
✻1
✻2
✻2
Serial I/O1 output
Serial I/O1 input
(13) Port P46
(14) Port P47
Serial I/O1
P4 output structure selection bit
synchronous clock selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
SRDY1 output enable bit
Data bus buffer function
selection bit
Direction
register
Serial I/O1 mode selection bit
Serial I/O1 enable bit
OBF10 output enable bit
Direction
register
Data bus
Port latch
Data bus
Port latch
✻1
✻3
Serial I/O1 ready output
✻2
S1 input
Data bus buffer function
selection bit
Serial I/O1 clock output
OBF10 output
Serial I/O1 external clock input
(15) Port P50
(16) Ports P51,P52,P53
Data bus buffer enable bit
Data bus buffer enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
✻3
A0 input
Data bus buffer
enable bit
INT20, INT30, INT40 interrupt input
✻3
S0,R,W input
Data bus buffer
enable bit
✻1. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F16).
✻2. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F16).
The port P8 and port P4 input register can be switched by the P8 function selection bit of the port control register 2 (address 002F16).
✻3. The input level can be switched between CMOS compatible input level and TTL level by the input level selection bit of the data bus buffer
control register (address 002A16).
Fig. 11 Port block diagram (2)
15
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Ports P54,P55
(18) Port P56
Direction
register
Data bus
PWM0 output pin selection bit
PWM0 enable bit
Direction
register
Port latch
Data bus
Port latch
Pulse output mode
Timer output
CNTR0,CNTR1 interrupt input
(19) Port P57
PWM01 output
D-A converter output
D-A1 output enable bit
(20) Port P6
PWM1 output pin selection bit
PWM1 enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
A-D converter input
Analog input pin selection bit
PWM11 output
D-A converter output
D-A2 output enable bit
(21) Port P70
(22) Port P71
Serial IO/2 transmit completion signal
Serial I/O2 port selection bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
✻4
✻5
✻4
Serial I/O2 input
✻5
Serial I/O2 output
(23) Port P72
(24) Port P73
Serial I/O2 synchronization
clock selection bit
Serial I/O2 port selection bit
Direction
register
SRDY2 output enable bit
Direction
register
Data bus
Data bus
Port latch
Port latch
✻4
✻4
✻5
✻5
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2
external clock input
INT21 interrupt input
✻4. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (address 002F16).
✻5. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (address 002F16).
The port P8 direction register and port P7 input register can be switched by the P8 function selection bit of the port control register 2
(address 002F16).
Fig. 12 Port block diagram (3)
16
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(25) Ports P74,P75
(26) Port P76
I2C-BUS interface
enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
✻4
✻5
INT31,INT41 interrupt input
SDA output
SDA input
(27) Port P77
(28) Port P8
S0
S1
R
Data bus buffer enable bit
Direction
register
I2C-BUS interface
enable bit
Direction
register
Data bus
✻6
Data bus
Port latch
Port latch
Output buffer 0
SCL output
SCL input
✻6
Status register 0
Output buffer 1
Status register 1
✻3
Input buffer 0
✻3
Input buffer 1
✻6. The input level can be switched between CMOS compatible input level and SMBUS level by the I2C-BUS interface pin input
selection bit of the I2C control register (address 001516).
Fig. 13 Port block diagram (4)
17
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Port control register 1
(PCTL1: address 002E16)
P00–P03 output structure selection bit
0: CMOS
1: N-channel open-drain
P04–P07 output structure selection bit
0: CMOS
1: N-channel open-drain
P10–P13 output structure selection bit
0: CMOS
1: N-channel open-drain
P14–P17 output structure selection bit
0: CMOS
1: N-channel open-drain
P30–P33 pull-up control bit
0: No pull-up
1: Pull-up
P34–P37 pull-up control bit
0: No pull-up
1: Pull-up
PWM0 enable bit
0: PWM0 output disabled
1: PWM0 output enabled
PWM1 enable bit
0: PWM1 output disabled
1: PWM1 output enabled
b7
b0
Port control register 2
(PCTL2: address 002F16)
P4 input level selection bit (P42–P46)
0: CMOS level input
1: TTL level input
P7 input level selection bit (P70–P75)
0: CMOS level input
1: TTL level input
P4 output structure selection bit (P42, P43, P44, P46)
0: CMOS
1: N-channel open-drain
P8 function selection bit
0: Port P8/Port P8 direction register
1: Port P4 input register/Port P7 input register
INT2, INT3, INT4 interrupt switch bit
0: INT20, INT30, INT40 interrupt
1: INT21, INT31, INT41 interrupt
Timer Y count source selection bit
0: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
1: f(XCIN)
Oscillation stabilizing time set after STP instruction released bit
0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12
1: No automatic set
Port output P42/P43 clear function selection bit
0: Only software clear
1: Software clear and output data bus buffer 0 reading
(system bus side)
Fig. 14 Structure of port I/O related register
18
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt Source Selection
Interrupts occur by 16 sources among 21 sources: nine external,
eleven internal, and one software.
Any of the following interrupt sources can be selected by the interrupt source selection register (address 003916).
1. INT0 or Input buffer full
2. INT1 or Output buffer empty
3. Serial I/O1 transmission or SCLSDA
4. CNTR0 or SCLSDA
5. Serial I/O2 or I2C
6. INT2 or I2C
7. CNTR1 or Key-on wake-up
8. A-D conversion or Key-on wake-up
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
External Interrupt Pin Selection
The occurrence sources of the external interrupt INT2, INT3, and
INT4 can be selected from either input from INT20, INT30, INT40
pin, or input from INT21, INT31, INT41 pin by the INT2, INT3, INT4
interrupt switch bit (bit 4 of address 002F16).
■ Notes
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
When setting of the following register or bit is changed, the interrupt request bit may be set to “1.”
• Interrupt edge selection register (address 003A16)
• Interrupt source selection register (address 003916)
• INT2, INT3, INT4 interrupt switch bit of Port control register 2 (bit
4 of address 002F16)
Accept the interrupt after clearing the interrupt request bit to “0”
after interrupt is disabled and the above register or bit is set.
19
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
INT0
2
FFFB16
FFFA16
Interrupt Request
Generating Conditions
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Input buffer full
(IBF)
At input data bus buffer writing
INT1
At detection of either rising or
falling edge of INT1 input
Output buffer
empty (OBE)
Serial I/O1
reception
Serial I/O1
transmission
3
FFF916
FFF816
4
FFF716
FFF616
5
FFF516
FFF416
SCL, SDA
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
CNTR0
10
FFEB16
FFEA16
11
FFE916
FFE816
SCL, SDA
CNTR1
Key-on wake-up
Serial I/O2
12
FFE716
FFE616
13
FFE516
FFE416
I 2C
INT2
I 2C
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmission buffer is empty
At detection of either rising or
falling edge of SCL or SDA
At timer X underflow
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of SCL or SDA
At detection of either rising or
falling edge of CNTR1 input
At falling of port P3 (at input) input logical level AND
At completion of serial I/O2 data
transfer
At completion of data transfer
At detection of either rising or
falling edge of INT2 input
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
At completion of data transfer
14
FFE316
FFE216
At detection of either rising or
falling edge of INT3 input
INT4
15
FFE116
FFE016
At detection of either rising or
falling edge of INT4 input
16
FFDF16
FFDE16
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
At completion of A-D conversion
A-D converter
Key-on wake-up
17
FFDD16
FFDC16
At falling of port P3 (at input) input logical level AND
External interrupt (falling valid)
At BRK instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
20
External interrupt
(active edge selectable)
At output data bus buffer reading
INT3
BRK instruction
Remarks
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 15 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
Not used (returns “0” when read)
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
Not used (returns “0” when read)
b7
0 : Falling edge active
1 : Rising edge active
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
INT0/input buffer full interrupt request
bit
INT1/output buffer empty interrupt
request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit/SCL, SDA interrupt
request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
INT0/input buffer full interrupt enable bit
INT1/output buffer empty interrupt
enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit/SCL, SDA interrupt
enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
b0 Interrupt request register 2
(IREQ2 : address 003D16)
CNTR0/SCL, SDA interrupt request bit
CNTR1/key-on wake-up interrupt
request bit
Serial I/O2/I2C interrupt request bit
INT2/I2C interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
AD converter/key-on wake-up interrupt
request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
CNTR0/SCL, SDA interrupt enable bit
CNTR1/key-on wake-up interrupt
enable bit
Serial I/O2/I2C interrupt enable bit
INT2/I2C interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
AD converter/key-on wake-up interrupt
enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers (1)
21
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt source selection register
(INTSEL: address 003916)
INT0/input buffer full interrupt source selection bit
0 : INT0 interrupt
1 : Input buffer full interrupt
INT1/output buffer empty interrupt source selection bit
0 : INT1 interrupt
1 : Output buffer empty interrupt
Serial I/O1 transmit/SCL,SDA interrupt source selection bit
0 : Serial I/O1 transmit interrupt
1 : SCL,SDA interrupt
CNTR0/SCL,SDA interrupt source selection bit
0 : CNTR0 interrupt
1 : SCL,SDA interrupt
(Do not write “1” to these bits simultaneously.)
Serial I/O2/I2C interrupt source selection bit
0 : Serial I/O2 interrupt
1 : I2C interrupt
INT2/I2C interrupt source selection bit
0 : INT2 interrupt
1 : I2C interrupt
(Do not write “1” to these bits simultaneously.)
CNTR1/key-on wake-up interrupt source selection bit
0 : CNTR1 interrupt
1 : Key-on wake-up interrupt
(Do not write “1” to these bits simultaneously.)
AD converter/key-on wake-up interrupt source selection bit
0 : A-D converter interrupt
1 : Key-on wake-up interrupt
Fig. 17 Structure of interrupt-related registers (2)
22
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake Up)
A Key input interrupt request is generated by applying “L” level to
any pin of port P3 that have been set to input mode. In other
words, it is generated when AND of input level goes from “1” to
“0”. An example of using a key input interrupt is shown in Figure
18, where an interrupt request is generated by pressing one of the
keys consisted as an active-low key matrix which inputs to ports
P30–P33.
Port PXx
“L” level output
Port control register 1
Bit 5 = “1”
✻
✻✻
Port P37
direction register = “1”
Port P37
latch
Key input interrupt request
P37 output
Port P36
direction register = “1”
✻
✻✻
Port P36
latch
✻
✻✻
Port P35
latch
P36 output
Port P35
direction register = “1”
P35 output
✻
Port P34
direction register = “1”
✻✻
Port P34
latch
P34 output
✻
P33 input
Port control register 1
Bit 4 = “1”
✻✻
Port P33
latch
Port P3
Input reading circuit
Comparator circuit
Port P32
direction register = “0”
✻
✻✻
✻
✻✻
✻
✻✻
P32 input
Port P32
latch
Port P31
direction register = “0”
P31 input
P30 input
Port P33
direction register = “0”
Port P31
latch
Port P30
direction register = “0”
Port P30
latch
✻ P-channel transistor for pull-up
✻✻ CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P3 block diagram
23
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
Timer 1 and Timer 2
The 3886 group has four timers: timer X, timer Y, timer 1, and
timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts f(XIN)/16.
(2) Pulse Output Mode
b7
b0
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 19 Structure of timer XY mode register
24
Timer X (or timer Y) counts f(X IN)/16. Whenever the contents of
the timer reach “00 16 ”, the signal output from the CNTR 0 (or
CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P54 ( or port P55) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR 0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts f(XIN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the
CNTR 0 (or CNTR 1 ) active edge selection bit is “1”, the timer
counts while the CNTR0 (or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer overflows.
The count source for timer Y in the timer mode or the pulse output
mode can be selected from either f(XIN)/16 or f(XCIN) by the timer
Y count source selection bit of the port control register 2 (bit 5 of
address 002F16).
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Divider
Oscillator
f(XIN)
Prescaler X latch (8)
1/16
Pulse width
measurement
mode
(f(XCIN) in low-speed mode)
Timer mode
Pulse output mode
Prescaler X (8)
CNTR0 active
edge selection
bit “0”
P54/CNTR0
“1 ”
Event
counter
mode
Timer X (8)
To timer X interrupt
request bit
Timer X count stop bit
To CNTR0 interrupt
request bit
CNTR0 active
edge selection “1”
bit
“0 ”
Q
Toggle flip-flop T
Q
R
Timer X latch write pulse
Pulse output mode
Port P54
latch
Port P54
direction register
Timer X latch (8)
Pulse output mode
Data bus
Oscillator
Divider
f(XIN)
Timer Y count source
selection bit
“0 ”
1/16
(f(XCIN) in low-speed mode)
Prescaler Y latch (8)
Oscillator
“1 ”
f(XCIN)
Prescaler Y (8)
CNTR1 active
edge selection
bit “0”
P55/CNTR1
“1 ”
Event
counter
mode
Port P55
direction register
Timer Y (8)
To timer Y interrupt
request bit
Timer Y count stop bit
To CNTR1 interrupt
request bit
CNTR1 active
edge selection “1”
bit
Q
Toggle flip-flop T
Q
Port P55
latch
Timer Y latch (8)
Pulse width
measureTimer mode
ment mode Pulse output mode
“0 ”
R
Timer Y latch write pulse
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
Oscillator
f(XIN)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
Divider
1/16
Prescaler 12 (8)
To timer 2 interrupt
request bit
(f(XCIN) in low-speed mode)
To timer 1 interrupt
request bit
Fig. 20 Block diagram of timer X, timer Y, timer 1, and timer 2
25
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Clock Synchronous Serial I/O Mode
SERIAL I/O
Serial I/O1
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O1 control register
Address 001816
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P44/RXD
Shift clock
Address 001A16
Receive buffer full flag (RBF)
Clock control circuit
P46/SCLK1/OBF10
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
BRG count source selection bit
f(XIN)
(f(XCIN) in low-speed mode)
1/4
P47/SRDY1/S1
F/F
Clock control circuit
Falling-edge detector
Shift clock
P45/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Data bus
Fig. 21 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 22 Operation of clock synchronous serial I/O1 function
26
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer register
OE
Character length selection bit
P44/RXD
ST detector
7 bits
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
P46/SCLK1/OBF10
BRG count source selection bit Frequency division ratio 1/(n+1)
f(XIN)
Baud rate generator
(f(XCIN) in low-speed mode)
Address 001C16
1/4
ST/SP/PA generator
1/16
Transmit shift register
P45/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 23 Block diagram of UART serial I/O1
27
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
SP
D1
✽
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
Receive buffer read
signal
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 24 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIO1CON)]
001A16
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The serial I/O1 control register consists of eight control bits for the
serial I/O function.
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD pin.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
28
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 status register
(SIO1STS : address 001916)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001B16)
b7
b0
Serial I/O1 control register
(SIO1CON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P47 pin operates as ordinary I/O pin
1: P47 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O disabled
(pins P44 to P47 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P44 to P47 operate as serial I/O pins)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 25 Structure of serial I/O1 control registers
29
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
b7
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
[Serial I/O2 Control Register (SIO2CON)]
001D16
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Comparator reference input selection bit
0: P00/P3REF input
1: Reference input fixed
Fig. 26 Structure of serial I/O2 control register
1/8
XCIN
Internal synchronous
clock selection bits
1/16
“10”
Divider
Main clock divide ratio
selection bits (Note)
“00”
“01”
XIN
1/32
Data bus
1/64
1/128
1/256
P73 latch
P73/SRDY2
/INT21
Serial I/O2 synchronous
clock selection bit “1”
SRDY2
“1 ”
SRDY2 output enable bit
Synchronization
circuit
SCLK2
“0 ”
“0 ”
External clock
P72 latch
“0 ”
P72/SCLK2
“1 ”
Serial I/O2 port selection bit
Serial I/O counter 2 (3)
P71 latch
“0 ”
P71/SOUT2
“1 ”
Serial I/O2 port selection bit
P70/SIN2
Serial I/O2 register (8)
Note: These are assigned to bits 7 and 6 of the CPU mode register (address 003B16).
These bits select any of the high-speed mode, the middle-speed mode, and the low-speed mode.
Fig. 27 Block diagram of serial I/O2 function
30
Serial I/O2
interrupt request
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig. 28 Timing of serial I/O2 function
31
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
OUTPUT CIRCUIT
The following explanation assumes f(XIN) = 8 MHz.
The 3886 group has two PWM output circuits, PWM0 and PWM1,
with 14-bit resolution respectively. These can operate independently. When the oscillation frequency X IN is 10 MHz, the
minimum resolution bit width is 200 ns and the cycle period is
3276.8 µs. The PWM timing generator supplies a PWM control
signal based on a signal that is the frequency of the XIN clock.
Data Bus
Set to “1”
at write
PWM0L register (address 003116)
bit 7
bit 5
bit 0
bit 0
bit 7
PWM0H register
(address 003016)
PWM0 latch (14 bits)
MSB
LSB
14
P30 latch
P30/PWM00
PWM0
14-bit PWM0 circuit
PWM0 enable bit
f(XIN)
(8MHz)
1/2
(4MHz)
PWM0
timing
generator
PWM0 output selection bit
PWM0 enable bit
(64 µs period)
(4096 µs period)
P30 direction register
P56 latch
P56/DA1/PWM01
PWM0 enable bit
PWM0 output selection bit
PWM0 enable bit
P56 direction register
Fig. 29 PWM block diagram (PWM0)
32
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Setup (PWM0)
mum resolution (250 ns).
“H” or “L” of the bit in the ADD part shown in Figure 30 is added to
this “H” duration by the contents of the low-order 6-bit data according to the rule in Table 7.
That is, only in the sub-period tm shown by Table 7 in the PWM
cycle period T = 64t, its “H” duration is lengthened to the minimum
resolution τ added to the length of other periods.
The PWM0 output pin also functions as port P3 0 or P5 6. The
PWM0 output pin is selected from either P3 0 /PWM 00 or
P5 6 /PWM 01 by bit 4 of the AD/DA control register (address
003416).
The PWM0 output becomes enabled state by setting bit 6 of the
port control register 1 (address 002E16). The high-order eight bits
of output data are set in the PWM0H register (address 0030 16)
and the low-order six bits are set in the PWM0L register (address
003116).
PWM1 is set as the same way.
For example, if the high-order eight bits of the 14-bit data are 0316
and the low-order six bits are 0516, the length of the “H”-level output in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its length is 3
τ in all other sub-periods.
Time at the “H” level of each sub-period almost becomes equal,
because the time becomes length set in the high-order 8 bits or
becomes the value plus τ, and this sub-period t (= 64 µs, approximate 15.6 kHz) becomes cycle period approximately.
PWM Operation
The 14-bit PWM data is divided into the low-order six bits and the
high-order eight bits in the PWM latch.
The high-order eight bits of data determine how long an “H”-level
signal is output during each sub-period. There are 64 sub-periods
in each period, and each sub-period is 256 ✕ τ (64 µs) long. The
signal is “H” for a length equal to N times τ, where τ is the mini-
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch
at each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch at each sub-period
(every 64 µs). The signal which is output to the PWM output pin is
corresponding to the contents of this latch. When the PWML register is read, the latch contents are read. However, bit 7 of the
PWML register indicates whether the transfer to the PWM latch is
completed; the transfer is completed when bit 7 is “0” and it is not
done when bit 7 is “1.”
Table 7 Relationship between low-order 6 bits of data and
period set by the ADD bit
Low-order 6 bits of data (PWML)
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
Sub-periods tm Lengthened (m=0 to 63)
LSB
0
1
0
0
0
0
0
None
m=32
m=16, 48
m=8, 24, 40, 56
m=4, 12, 20, 28, 36, 44, 52, 60
m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63
4096 µs
64 µs
64 µs
64 µs
64 µs
m=0
m=7
m=8
m=9
15.75 µs
15.75 µs
15.75 µs
16.0 µs
Pulse width modulation register H :
00111111
Pulse width modulation register L :
000101
Sub-periods where “H” pulse width is 16.0 µs :
Sub-periods where “H” pulse width is 15.75 µs :
15.75 µs
64 µs
m=63
15.75 µs
15.75 µs
m = 8, 24, 32, 40, 56
m = all other values
Fig. 30 PWM timing
33
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data 6A16 stored at address 003016
PWM0H
register
5916
Data 7B16 stored at address 003016
6A16
7B16
Data 2416 stored at address 003116
PWM0L
register
1316
Bit 7 cleared after transfer
A416
Data 3516 stored at address 003116
2416
3516
Transfer from register to latch
PWM0 latch
(14bits)
165316
1A9316
Transfer from register to latch
B516
1AA416
1AA416
1EE416
1EF516
When bit 7 of PWM0L is 0, transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
Example 1
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
5
2
5
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
PWM0 output
1
low-order
6-bit output:
H
L
6A16, 2416
Example 2
5
5
5
5
6B16 ·············· 36 times
(107)
6A
6A 6A
6A
6B
6A
5
5
5
6A16 ············· 28 times
(106)
6B
6A
6B
6A
6A
6A
5
5
5
5
5
106 ✕ 64 + 36
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
PWM0 output
low-order
6-bit output:
H
L
6A16, 1816
4
6B16
3
··············
4
4
3
4
6A16 ······· 40 times
24 times
4
3
4
106 ✕ 64 + 24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum resolution bit width τ = 0.25 µs
PWM output
2
6B
6A
69
68
67
·······
02
01
FF
FE
FD
FC
·······
97
96
ADD
8-bit
counter
02
01
00
69
68
67
·······
02
01
FF
FE
FD
FC
·······
97
96
ADD
The ADD
portions with
additional τ are
determined by
PWML.
Fig. 31 14-bit PWM timing (PWM0)
34
6A
95
H duration length specified by PWM0H
256 τ (64 µs), fixed
·······
02
01
00
95
·······
6A
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUS INTERFACE
The 3886 group has a 2-byte bus interface function which is almost functionally equal to MELPS8-41 series and the control
signal from the host CPU side can operate it (slave mode).
It is possible to connect the 3886 group with the RD and WR
separated CPU bus directly. Figure 34 shows the block diagram of
the bus interface function.
The data bus buffer function I/O pins (P4 2, P43, P46 , P47, P5 0–
P53, P8) also function as the normal digital port I/O pins. When bit
0 (data bus buffer enable bit) of the data bus buffer control register (address 002A16) is “0,” these pins become the normal digital
port I/O pins. When it is “1,” these bits become the data bus buffer
function I/O pins.
Input buffer
full flag 0 IBF0
Rising edge
detection circuit
The selection of either the single data bus buffer mode, which
uses 1 byte: data bus buffer 0 only, or the double data bus buffer
mode, which uses 2 bytes: data bus buffer 0 and data bus buffer
1, is performed by bit 1 (data bus buffer function selection bit) of
the data bus buffer control register (address 002A16). Port P47 becomes S1 input in the double data bus buffer mode. When data is
written from the host CPU side, an input buffer full interrupt occurs. When data is read from the host CPU, an output buffer
empty interrupt occurs. This microcomputer shares two input
buffer full interrupt requests and two output buffer empty interrupt
requests as shown in Figure 32, respectively.
One-shot pulse
generating circuit
Input buffer full interrupt
request signal IBF
Input buffer
full flag 1 IBF1
Output buffer
full flag 0
OBF0
Rising edge
detection circuit
OBE0
Output buffer
full flag 1
OBF1
OBE1
One-shot pulse
generating circuit
Rising edge
detection circuit
One-shot pulse
generating circuit
Rising edge
detection circuit
One-shot pulse
generating circuit
Output buffer empty interrupt
request signal OBE
IBF0
IBF1
IBF
Interrupt request is set at this rising edge
OBF0
(OBE0)
OBF1
(OBE1)
OBE
Interrupt request is set at this rising edge
Fig. 32 Interrupt request circuit of data bus buffer
35
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Data bus buffer control register
(DBBCON : address 002A16)
Data bus buffer enable bit
0 : P50–P53, P8 I/O port
1 : Data bus buffer enabled
Data bus buffer function selection bit
0 : Single data bus buffer mode (P47 functions as I/O port.)
1 : Double data bus buffer mode (P47 functions S1 input.)
OBF0 output selection bit
0 : OBF00 valid
1 : OBF01 valid
OBF00 output enable bit
0 : P42 functions as port I/O pin.
1 : P42 functions as OBF00 output pin.
OBF01 output enable bit
0 : P43 functions as port I/O pin.
1 : P43 functions as OBF01 output pin.
OBF10 output enable bit
0 : P46 functions as port I/O pin.
1 : P46 functions as OBF10 output pin.
Input level selection bit
0 : CMOS level input
1 : TTL level input
Reserved
Do not write “1” to this bit.
b7
b0
Data bus buffer status register 0
(DBBSTS0 : address 002916)
Output buffer full flag 0 (OBF0)
0 : Buffer empty
1 : Buffer full
Input buffer full flag 0 (IBF0)
0 : Buffer empty
1 : Buffer full
User definable flag (U02)
This flag can be defined by user freely.
A00 flag (A00)
This flag indicates the condition of A00 status
when the IBF0 flag is set.
User definable flag (U04–U07)
This flag can be defined by user freely.
b7
b0
Data bus buffer status register 1
(DBBSTS1 : address 002C16)
Output buffer full flag 1 (OBF1)
0 : Buffer empty
1 : Buffer full
Input buffer full flag 1 (IBF1)
0 : Buffer empty
1 : Buffer full
User definable flag (U12)
This flag can be defined by user freely.
A01 flag (A01)
This flag indicates the condition of A01 status
when the IBF1 flag is set.
User definable flag (U14–U17)
This flag can be defined by user freely.
Fig. 33 Structure of bus interface related register
36
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(Address 002A16)
b7
b6
b5
b4
b3
b2
b1
b0
P42/INT0/OBF00
P43/INT1/OBF01
P50/A0
P51/INT20/S0
P52/INT30/R
P53/INT40/W
(Address 002916)
U07
P80/DQ0
U06
U05
U04
A00
U02 IBF0 OBF0
Output data bus buffer 0
(Address 002816)
P82/DQ2
WR
DBBSTS0
P84/DQ4
System bus
Input data bus buffer 0
P83/DQ3
Internal data bus
P81/DQ1
(Address 002816)
RD
D B B0
RD
D B B1
Input data bus buffer 1
P85/DQ5
DBBSTS1
WR
(Address 002B16)
P86/DQ6
P87/DQ7
Output data bus buffer 1
(Address 002B16)
U17
U16
U15
U14
A01
U12
IBF1 OBF1
(Address 002C16)
P47/SRDY1/S1
P46/SCLK1/OBF10
Fig. 34 Bus interface device block diagram
37
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Data Bus Buffer Status Register 0, 1
(DBBSTS0, DBBSTS1)] 002916, 002C16
The data bus buffer status register 0, 1 consist of eight bits.
Bits 0, 1, and 3 are read-only bits and indicate the condition of the
data bus buffer. Bits 2, 4, 5, 6, and 7 are user definable flags
which can be set by program, and can be read/written. This register can be read from the host CPU when the A0 pin is set to “H”
only.
•Bit 0: Output buffer full flag OBF0, OBF1
When writing data to the output data bus buffer, these flags are
set to “1”. When reading the output data bus buffer from the host
CPU, these flags are cleared to “0”.
•Bit 1: Input buffer full flag IBF0, IBF1
When writing data from the host CPU to the input data bus
buffer, these flags are set to “1”. When reading the input data
bus buffer from the slave CPU side, these flags are cleared to
“0”.
•Bit 3: A0 flag A00, A01
When writing data from the host CPU to the input data bus
buffer, the level of the A0 pin is latched.
[Input Data Bus Buffer Register 0, 1 (DBBIN0,
DBBIN1)] 002816, 002B16
Data on the data bus is latched to DBBIN by writing request from
the host CPU. Data of DBBIN can be read from the data bus
buffer registers (address 002816 or 002B16) on SFR.
[Output Data Bus Buffer Register 0, 1
(DBBOUT0, DBBOUT1)] 002816, 002B16
When writing data to the data bus buffer registers (address 002816
or 002B16) on SFR, data is set to DBBOUT. Data of DBBOUT is
output from the host CPU to the data bus by performing the reading request when the A0 pin is set to “L”.
38
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Function description of control I/O pins at bus interface function selected
Pin
Name
OBF00
output
enable bit
OBF01
output
enable bit
OBF10
output
enable bit
Input
/Output
P47/SRDY1
/S1
S1
–
–
–
Input
P50/A0
A0
–
–
–
Input
P51/INT20
/S0
S0
–
–
–
Input
R
–
–
–
Input
W
–
–
–
Output
OBF00
1
0
0
Output
OBF01
0
1
0
Output
OBF10
0
0
1
Output
P52/INT30
/R
P53/INT40
/W
P42/INT0
/OBF00
P43/INT1
/OBF01
P46/SCLK1
/OBF10
Functions
Chip select input
This is used for selecting the data bus buffer and is
selected at “L” level.
Address input
This is used for selecting DBBSTS and DBBOUT
when the host CPU is read.
This is used for distinguishing command from data
when writing to the host CPU.
Chip select input
This is used for selecting the data bus buffer and is
selected at “L” level.
This is a timing signal for reading data from the
data bus buffer to the host CPU.
This is a timing signal for writing data to the data
bus buffer by the host CPU.
Status output signal
OBF00 signal is output.
Status output signal
OBF01 signal is output.
Status output signal
OBF10 signal is output.
39
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MULTI-MASTER I2C-BUS INTERFACE
Table 9 Multi-master I2C-BUS interface functions
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial
communications.
Figure 35 shows a block diagram of the multi-master I2C-BUS interface and Table 9 lists the multi-master I 2 C-BUS interface
functions.
This multi-master I2C-BUS interface consists of the I 2C address
register, the I 2C data shift register, the I2C clock control register,
the I2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I 2 C-BUS interface, set 1 MHz or
more to φ.
b7
Interrupt
generating
circuit
Interrupt request signal
(SCL SDAIRQ)
Item
Format
Communication mode
SCL clock frequency
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
20.2 kHz to 312.5 kHz (at φ = 5 MHz)
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
I2C address register
b0
Interrupt
generating
circuit
SA D6 SA D5 SA D4 SA D3 SA D2 SA D1 SA D0 RBW
S0D
Interrupt request signal
(I2CIRQ)
Address comparator
Serial data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
S2D
STSP
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
SEL
AL
circuit
S1
I2C status register
I2C start/stop condition
control register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
ACK
b0
ACK F AST CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
I2C clock control register
S1D
b0
b7
TISS
CLK
STP
10 BIT
S AD AL S
ES0 BC2 BC1 BC0
S2
I2C clock control register
Clock division
S top sele ction
System clock (φ)
Bit counter
Fig. 35 Block diagram of multi-master I2C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
40
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[I2C Data Shift Register (S0)] 001216
The I2C data shift register (S0 : address 001216) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 cycles of φ are required from
the rising of the SCL clock until input to this register.
The I2C data shift register is in a write enable status only when the
I2 C-BUS interface enable bit (ES0 bit : bit 3 of address 15 16) of
the I2C control register is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and
the MST bit of the I2C status register (address 001416) are “1,” the
SCL is output by a write instruction to the I 2C data shift register.
Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value.
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
I2C address register
(S0D: address 001316)
Read/write bit
Slave address
Fig. 36 Structure of I2C address register
[I2C Address Register (S0D)] 001316
The I2C address register (address 001316) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be
received immediately after the START condition is detected.
•Bit 0: Read/write bit (RBW)
This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RBW) of the I 2C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
41
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[I2C Clock Control Register (S2)] 001616
I2 C
Note: Do not write data into the
clock control register during transfer. If
data is written during transfer, the I 2C clock generator is reset, so
that data cannot be transferred normally.
42
b0
A CK F AST
B IT MODE CCR4 CCR3 CCR2 CCR1 CCR0
I2C clock control register
(S2 : address 001616)
SCL frequency control
bits
Refer to Table 10.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock
mode
ACK bit
0 : ACK is returned.
1 : ACK is not
returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Fig. 37 Structure of I2C clock control register
Table 10 Set values of I 2C clock control register and S CL
frequency
Setting value of
CCR4–CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
SCL frequency
(at φ = 4 MHz, unit : kHz) (Note 1)
Standard clock High-speed clock
mode
mode
0
0
0
Setting disabled
Setting disabled
0
0
0
1
Setting disabled
Setting disabled
0
0
0
1
0
Setting disabled
Setting disabled
0
0
0
1
1
– (Note 2)
333
0
0
1
0
0
– (Note 2)
250
0
0
1
0
1
100
400 (Note 3)
0
0
1
1
0
83.3
166
1000/CCR value
(Note 3)
…
0
0
…
0
…
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at the
occurrence of an ACK clock (makes S DA “H”) and receives the
ACK bit generated by the data receiving device.
A CK
…
✽ACK clock: Clock for acknowledgment
b7
…
The I2C clock control register (address 001616) is used to set ACK
control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 10.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the S CL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(XIN) and high-speed mode (2 division main clock).
•Bit 6: ACK bit (ACK BIT)
This bit sets the S DA status when an ACK clock✽ is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit is
set to “1,” the ACK non-return mode is selected. The SDA is held in
the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned).
500/CCR value
(Note 3)
1
1
1
0
1
17.2
34.5
1
1
1
1
0
16.6
33.3
1
1
1
1
1
16.1
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 cycles of φ in the standard clock mode, and fluctuates from –2 to +2 cycles of φ in the high-speed clock mode. In
the case of negative fluctuation, the frequency does not increase
because “L” duration is extended instead of “H” duration reduction.
These are value when S CL clock synchronization by the synchronous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[I2C Control Register (S1D)] 001516
The I2C control register (address 001516) controls data communication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I2C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
bit (bit 7 of address 0016 16)) have been transferred, and BC0 to
BC2 are returned to “0002”.
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
•Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C
status register at address 001416 ).
• Writing data to the I2C data shift register (address 001216) is dis
abled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “(5) I 2C Status Register,” bit 1) is received, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I2C address register (address 0013 16) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I 2C address register are compared with address
data.
•Bit 6: System clock stop selection bit (CLKSTP)
When executing the WIT or STP instruction, this bit selects the
condition of system clock provided to the multi-master I2C-BUS interface. When this bit is set to “0,” system clock and operation of
the multi-master I2C-BUS interface stop by executing the WIT or
STP instruction.
When this bit is set to “1,” system clock and operation of the multimaster I 2 C-BUS interface do not stop even when the WIT
instruction is executed.
When the system clock stop selection bit is “1,” do not execute the
STP instruction.
•Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the multimaster I2C-BUS interface.
b7
b0
10 B IT
TISS CLK SAD ALS ES0 BC2 BC1 BC0
STP
I2C control register
(S1D : address 001516)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
I2C-BUS interface
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit
addressing format
System clock stop
selection bit
0 : System clock stop
when executing WIT
or STP instruction
1 : Not system clock
stop when executing
WIT instruction
(Do not use the STP
instruction.)
I2C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
Fig. 38 Structure of I2C control register
43
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[I2C Status Register (S1)] 001416
The I2C status register (address 001416) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I2C data shift register
(address 001216).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0,” this bit is set to “1” when a general call ✽
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
✽General call: The master transmits the general call address “0016 ” to all
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
➀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 001316).
• A general call is received.
➁ In the slave reception mode, when the 10-bit addressing format
is selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2C address register (8 bits consisting of slave address and RBW bit), the first
bytes agree.
➂ This bit is set to “0” by executing a write instruction to the I2C
data shift register (address 001216) when ES0 is set to “1” or
reset.
•Bit 3: Arbitration lost✽ detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and address data transmitted by another master device.
✽Arbitration lost :The status in which communication as a master is disabled.
44
•Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the S CL is kept in the “0” state and
clock generation is disabled. Figure 40 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I2 C data shift register (address 001216). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated except for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I2C start/stop condition
control register (address 001716). When the ES0 bit (bit 3) of the
I2C control register (address 0015 16) is “0” or reset, the BB flag is
set to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Generating Method” described later.
MITSUBISHI MICROCOMPUTERS
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•Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated on
the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communication are generated on the SCL.
This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbitration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note).
• At reset
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
b7
b0
MST TRX BB PIN AL AAS AD0 LRB
I2C status register
(S1 : address 001416)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
I2C-BUS interface interrupt
request bit
0 : Interrupt request issued
1 : No interrupt request
issued
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
Note: These bit and flags can be read out but cannot
be written.
Write “0” to these bits at writing.
Fig. 39 Structure of I2C status register
SC L
PIN
I2CIRQ
Fig. 40 Interrupt request signal generating timing
45
MITSUBISHI MICROCOMPUTERS
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START Condition Generating Method
START/STOP Condition Detecting Operation
When writing “1” to the MST, TRX, and BB bits of the I 2C status
register (address 0014 16) at the same time after writing the slave
address to the I 2C data shift register (address 001216) with the
condition in which the ES0 bit of the I2C control register (address
001516) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 41, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
The START/STOP condition detection operations are shown in
Figures 43, 44, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: S CL release time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I2CIRQ” occurs to the CPU.
I2C status register
write signal
SC L
Setup
time
SD A
SCL release time
Hold time
SCL
Fig. 41 START condition generating timing diagram
Setup
time
Hold
time
START/STOP condition
generating selection bit
Standard
clock mode
High-speed
clock mode
“0”
“1”
“0”
“1”
5.0 µs (20 cycles)
13.0 µs (52 cycles)
5.0 µs (20 cycles)
13.0 µs (52 cycles)
2.5 µs (10 cycles)
6.5 µs (26 cycles)
2.5 µs (10 cycles)
6.5 µs (26 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 001516) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2C status register (address 001416) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 42, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
SC L
SDA
Setup
time
Hold time
Table 12 STOP condition generating timing table
Setup
time
Hold
time
START/STOP condition
generating selection bit
“0”
“1”
“0”
“1”
Standard
clock mode
5.5 µs (22 cycles)
13.5 µs (54 cycles)
5.5 µs (22 cycles)
13.5 µs (54 cycles)
High-speed
clock mode
3.0 µs (12 cycles)
7.0 µs (28 cycles)
3.0 µs (12 cycles)
7.0 µs (28 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
46
SCL release time
SC L
SDA
BB flag
Setup
time
Hold time
BB flag
reset
time
Fig. 44 STOP condition detecting timing diagram
Table 13 START condition/STOP condition detecting conditions
Standard clock mode
SCL release time
SSC value + 1 cycle (6.25 µs)
Setup time
SSC value + 1 cycle < 4.0 µs (3.25 µs)
2
SSC value
cycle < 4.0 µs (3.0 µs)
2
Hold time
SSC value –1 + 2 cycles (3.375 µs)
2
High-speed clock mode
4 cycles (1.0 µs)
2 cycles (1.0 µs)
2 cycles (0.5 µs)
3.5 cycles (0.875 µs)
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
Fig. 42 STOP condition generating timing diagram
Item
Fig. 43 START condition detecting timing diagram
BB flag set/
reset time
I2C status register
write signal
Hold time
BB flag
reset
time
BB flag
Table 11 START condition generating timing table
Item
SDA
Setup
time
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[I2C START/STOP Condition Control Register
(S2D)] 001716
The I2C START/STOP condition control register (address 001716)
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 13.
Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or SDA
pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL /S DA interrupt pin selection bit, or the I2 C-BUS
interface enable bit ES0, the S CL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
S DA interrupt pin selection bit, or the I 2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
➁ 10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I2 C control register (address 0015 16) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I2C address register (address 001316). At the time of this
comparison, an address comparison between the RBW bit of
the I 2C address register (address 0013 16) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RBW bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (address 001416) is set to
“1.” After the second-byte address data is stored into the I2C
data shift register (address 001216), perform an address comparison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RBW bit of the I2C address register
(address 001316) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of
the I2C address register (address 001316). For the data transmission format when the 10-bit addressing format is selected,
refer to Figure 46, (3) and (4).
•Bit 7: START/STOP condition generating selection bit
(STSPSEL)
Setup/Hold time when the START/STOP condition is generated
can be selected.
Cycle number of system clock becomes standard for setup/hold
time. Additionally, setup/hold time is different between the START
condition and the STP condition. (Refer to Tables 11 and 12.) Set
“1” to this bit when the system clock frequency is 4 MHz or more.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
➀ 7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I2C control register (address 001516) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2C address register
(address 001316). At the time of this comparison, address comparison of the RBW bit of the I2 C address register (address
0013 16 ) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 46,
(1) and (2).
47
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b7
b0
STS P
SE L
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C START/STOP condition
control register
(S2D : address 001716)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
START/STOP condition generating
selection bit
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
Fig. 45 Structure of I2C START/STOP condition control register
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
Main clock
divide ratio
System
clock φ
(MHz)
START/STOP
condition
control register
SCL release time
(µs)
Setup time
(µs)
Hold time
(µs)
10
2
5
8
2
4
8
8
1
4
2
2
2
2
1
XXX11110
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.2 µs (31 cycles)
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.2 µs (16 cycles)
3.5 µs (14 cycles)
3.25 µs (13 cycles)
3.0 µs (3 cycles)
3.5 µs (7 cycles)
3.0 µs (6 cycles)
3.0 µs (3 cycles)
3.0 µs (15 cycles)
3.25 µs (13 cycles)
3.0 µs (12 cycles)
2.0 µs (2 cycles)
3.0 µs (6 cycles)
2.5 µs (5 cycles)
2.0 µs (2 cycles)
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
S
Slave address R/W
A
Data
A
Data
A/A
P
A
P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd bytes
A
Data
A
Data
A/A
P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd bytes
A
Sr
Slave address
R/W
1st 7 bits
“1”
7 bits
“0”
8 bits
7 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 46 Address data communication format
48
A
Data
1 to 8 bits
A
Data
1 to 8 bits
A
P
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the S CL frequency of 100 kHz and in the ACK return mode is
shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 001316) and “0” into the RBW bit.
➁ Set the ACK return mode and S CL = 100 kHz by setting “8516” in
the I2C clock control register (address 001616).
➂ Set “00 16” in the I2C status register (address 0014 16) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2C
control register (address 001516).
➄ Confirm the bus free condition by the BB flag of the I 2C status
register (address 001416).
➅ Set the address data of the destination of transmission in the
high-order 7 bits of the I2C data shift register (address 001216)
and set “0” in the least significant bit.
➆ Set “F016” in the I2C status register (address 001416) to generate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
➇ Set transmit data in the I2C data shift register (address 001216).
At this time, an SCL and an ACK clock automatically occur.
➈ When transmitting control data of more than 1 byte, repeat step
➇.
➉ Set “D016” in the I2C status register (address 001416) to generate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Example of Slave Reception
■Precautions when using multi-master I2CBUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I2C-BUS interface are described below.
• I2C data shift register (S0: address 001216)
When executing the read-modify-write instruction for this register during transfer, data may become a value not intended.
• I2C address register (S0D: address 001316)
When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RBW) at the above timing.
• I2C status register (S1: address 001416)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
• I2C control register (S1D: address 001516)
When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
• I2C clock control register (S2: address 001616)
The read-modify-write instruction can be executed for this register.
• I 2 C START/STOP condition control register (S2D: address
001716)
The read-modify-write instruction can be executed for this register.
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 001316) and “0” in the RBW bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
in the I2C clock control register (address 001616).
➂ Set “00 16” in the I2C status register (address 0014 16) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2C
control register (address 001516).
➄ When a START condition is received, an address comparison is
performed.
➅ •When all transmitted addresses are “0” (general call):
AD0 of the I 2C status register (address 0014 16) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set
in ➀:
ASS of the I2C status register (address 001416) is set to “1”
and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register (address 001416) are set to “0” and no interrupt
request signal occurs.
➆ Set dummy data in the I2C data shift register (address 001216).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
49
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5.
.....
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
.....
LDA —
SEI
BBS 5, S1, BUSBUSY
cess)
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch pro-
.....
2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag
confirming and branch process.
3. Use “STA $12, STX $12” or “STY $12” of the zero page addressing instruction for writing the slave address value to the
I2C data shift register.
4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure
example.
5. Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(3) RESTART condition generating procedure
This cannot be applied when the external memory is used and the
bus cycle is extended by ONW function.
1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is “0.”
.....
.....
LDM #$00, S1
LDA —
SEI
STA S0
LDM #$F0, S1
CLI
(Select slave receive mode)
(Taking out of slave address value)
(Interrupt disabled)
(Writing of slave address value)
(Trigger of RESTART condition generating)
(Interrupt enabled)
2. Select the slave receive mode when the PIN bit is “0.” Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified for the
writing to the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
the I2C data shift register.
4. Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
50
(4) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is
released and the S DA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” It is because
it may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
(6) STOP condition input at 7th clock pulse
In the slave mode, the STOP condition is input at the 7th clock
pulse while receiving a slave address or data. As the clock pulse
is continuously input, the SDA line may be held at LOW even if
flag BB is set to “0” (only for M38867M8A and M38867E8).
Countermeasure:
Write dummy data to the I2C shift register or reset the ES0 bit in
the S1D register (ES0 = “L” → ES0 = “H”) during a stop condition
interrupt routine with flag PIN = “1”.
Note: Do not use the read-modify-write instruction at this time.
Furthermore, when the ES0 bit is set to “0”, it becomes a
general-purpose port; so that the port must be set to input
mode or “H”.
(7) ES0 bit switch
In standard clock mode when SSC = “000102” or in high-speed
clock mode, flag BB may switch to “1” if ES0 bit is set to “1” when
SDA is “L”.
Countermeasure:
Set ES0 to “1” when SDA is “H”.
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
[A-D Conversion Register 1,2 (AD1, AD2)]
003516, 003816
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode selection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
10-bit reading or 8-bit reading can be performed by selecting the
reading procedure of the A-D conversion register 1, 2 after A-D
conversion is completed (in Figure 48).
The A-D conversion register 1 performs the 8-bit reading inclined
to MSB after reset, the A-D conversion is started, or reading of the
A-D converter register 1 is generated; and the register becomes
the 8-bit reading inclined to LSB after the A-D converter register 2
is generated.
Channel Selector
The channel selector selects one of ports P60/AN 0 to P6 7/AN 7,
and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit
and the A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
b7
b0
AD/DA control register
(ADCON : address 003416)
Analog input pin selection bits
b2 b1 b0
0
0
0
0
1
1
1
1
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
0: P60/AN0
1: P61/AN1
0: P62/AN2
1: P63/AN3
0: P64/AN4
1: P65/AN5
0: P66/AN6
1: P67/AN7
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
PWM0 output pin selection bit
0: P56/PWM01
1: P30/PWM00
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024, and outputs the divided voltages in the
10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
Vref in each mode, dividing the V REF (see below), with the input
voltage.
• 10-bit A-D mode (10-bit reading)
VREF
Vref = 1024 ✕ n (n = 0–1023)
• 10-bit A-D mode (8-bit reading)
VREF
Vref = 256 ✕ n (n = 0–255)
• 8-bit A-D mode
VREF
Vref = 256 ✕ (n–0.5) (n = 1–255)
=0
(n = 0)
0
0
1
1
0
0
1
1
PWM1 output pin selection bit
0: P57/PWM11
1: P31/PWM10
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
Fig. 47 Structure of AD/DA control register
10-bit reading
(Read address 003816 before 003516)
b7
(Address 003816)
0
b0
b9 b8
b7
(Address 003516)
b0
b7 b6 b5 b4 b3 b2 b1 b0
Note: Bits 2 to 6 of address 003816 becomes “0”at reading.
8-bit reading (Read only address 003516)
b7
(Address 003516)
b0
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 48 Structure of 10-bit A-D mode reading
51
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
AD/DA control register
(Address 003416)
b7
b0
3
A-D control circuit
Channel selector
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Comparator
A-D conversion register 2 (Address 003816)
A-D conversion register 1 (Address 003516)
10
Resistor ladder
VREF AVSS
Fig. 49 Block diagram of A-D converter
52
A-D interrupt request
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The 3886 group has two internal D-A converters (DA 1 and DA2)
with 8-bit resolution.
The D-A converter is performed by setting the value in each D-A
conversion register. The result of D-A conversion is output from
the DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P56/DA1/PWM01 or P57/DA2/PWM11) must be set to
“0” (input status).
The output analog voltage V is determined by the value n (decimal
notation) in the D-A conversion register as follows:
Data bus
D-A1 conversion register (8)
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
R-2R resistor ladder
DA1 output enable bit
P56/DA1/PWM01
D-A2 conversion register (8)
At reset, the D-A conversion registers are cleared to “00 16”, the
DA output enable bits are cleared to “0”, and the P56/DA1/PWM01
and P57/DA2/PWM11 pins become high impedance.
The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load.
Set VCC to 4.0 V or more when using the D-A converter.
R-2R resistor ladder
DA2 output enable bit
P57/DA2/PWM11
Fig. 50 Block diagram of D-A converter
“0” DA1 output enable bit
R
R
R
R
R
R
R
2R
P56/DA1/PWM01
“1”
2R
2R
MSB
D-A1 conversion register
“0”
2R
2R
2R
2R
2R
2R
LSB
“1”
AVSS
VREF
Fig. 51 Equivalent connection circuit of D-A converter (DA1)
53
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
performed by the writing operation to the comparator data register
(address 002D16). After 14 cycles of the internal system clock φ
(the time required for the comparison), the comparison result is
stored in the comparator register (address 002D16).
If the analog input voltage is greater than the internal reference
voltage, each bit of this register is “1”; if it is less than the internal
reference voltage, each bit of this register is “0”. To perform another comparison, the voltage comparison must be performed
again by writing to the comparator data register (address 002D16).
Read the result when 14 cycles of φ or more have passed after the
comparator operation starts. The ladder resistor is turned on during 14 cycles of φ , which is required for the comparison, and the
reference voltage is generated. An unnecessary current is not
consumed because the ladder resistor is turned off while the comparator operation is not performed. Since the comparator consists
of capacitor coupling, the electric charge is lost if the clock frequency is low.
Keep that the clock frequency is 1 MHz or more during the comparator operation. Do not execute the STP, WIT, or port P3 I/O
instruction.
COMPARATOR CIRCUIT
Comparator Configuration
The comparator circuit consists of resistors, comparators, a comparator control circuit, the comparator reference input selection bit
(bit 7 of address 001D 16 ), a comparator data register (address
002D16), the comparator reference power source input pin (P0 0/
P3REF) and analog signal input pins (P30–P37). The analog input
pin (P30–P37) also functions as an ordinary digital port.
Comparator Operation
To activate the comparator, first set port P3 to input mode by setting the corresponding direction register (address 000716) to “0” to
use port P3 as an analog voltage input pin. The internal fixed analog voltage (VCC ✕ 29/32) can be generated by setting “1” to the
comparator reference input selection bit (bit 7) of the serial I/O2
control register (address 001D16). (The internal fixed analog voltage becomes about 4.5 V at VCC = 5.0 V.) When setting “0” to the
comparator reference input selection bit, the P00/P3REF pin becomes the comparator reference power source input pin and it is
possible to input the comparator reference power source optionally from the external. The voltage comparison is immediately
Data bus
8
8
P3 (8)
Comparator data register
(address 002D16)
b0
P37
Comparator
P36
Comparator
“0”
P30
Comparator
P00/P3REF
Fig. 52 Comparator circuit
54
Comparator reference input selection
bit (bit 7) of serial I/O2 control
register(address 001D16)
“1”
Comparator
Comparator connecting control circuit Ladder resistor
signal
connecting signal VSS
VCC
VCC✕29/32
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 001E16) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to f(XIN)=131.072 ms
at 8 MHz frequency and f(XCIN)=32.768 s at 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to f(XIN)= 512 µs at 8 MHz frequency and f(XCIN)=128 ms at
32 kHz frequency. This bit is cleared to “0” after resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 001E16) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
001E16) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 001E 16 ) may be
started before an underflow. When the watchdog timer control register (address 001E16) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 001E16) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
001E16), each watchdog timer H and L is set to “FF16.”
XCIN
“10”
Main clock division
ratio selection bits
(Note)
XIN
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“FF16” is set when
watchdog timer
control register is
written to.
“0”
Watchdog timer L (8)
1/16
“1”
“00”
“01”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 53 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 001E16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 54 Structure of Watchdog timer control register
55
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L"
level for 2 µs or more. Then the RESET pin is returned to an "H"
level (the power source voltage should be between 2.7 V and 5.5
V (4.0 V to 5.5 V for flash memory version), and the oscillation
should be stable), reset is released. After the reset is completed,
the program starts from the address contained in address FFFD16
(high-order byte) and address FFFC16 (low-order byte). Make sure
that the reset input voltage is less than 0.54 V for VCC of 2.7 V. For
flash memory version, make sure that the reset input voltage is
less than 0.8 V for Vcc of 4.0 V.
Poweron
RESET
Power source
voltage
0V
VCC
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
(Vcc = 4.0 V for flash memory version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 55 Reset circuit example
XIN
φ
RESET
Internal
reset
?
?
Address
?
?
FFFC
F FFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 56 Reset sequence
56
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
(1)
Port P0 (P0)
000016
0016
(33) Prescaler 12 (PRE12)
002016
FF16
(2)
Port P0 direction register (P0D)
000116
0016
(34) Timer 1 (T1)
002116
0116
(3)
Port P1 (P1)
000216
0016
(35) Timer 2 (T2)
002216
FF16
(4)
Port P1 direction register (P1D)
000316
0016
(36) Timer XY mode register (TM)
002316
0016
(5)
Port P2 (P2)
000416
0016
(37) Prescaler X (PREX)
002416
FF16
(6)
Port P2 direction register (P2D)
000516
0016
(38) Timer X (TX)
002516
FF16
(7)
Port P3 (P3)
000616
0016
(39) Prescaler Y (PREY)
002616
FF16
(8)
Port P3 direction register (P3D)
000716
0016
(40) Timer Y (TY)
002716
FF16
(9)
Port P4 (P4)
000816
0016
(41) Data bus buffer register 0 (DBB0) 002816 X X X X X X X X
(10) Port P4 direction register (P4D)
000916
0016
(42) Data bus buffer status register 0 (DBBSTS0)
002916
0016
(11) Port P5 (P5)
000A16
0016
(43) Data bus buffer control register (DBBCON)
002A16
0016
(12) Port P5 direction register (P5D)
000B16
0016
(44) Data bus buffer register 1 (DBB1) 002B16 X X X X X X X X
(13) Port P6 (P6)
000C16
0016
(45) Data bus buffer status register 1 (DBBSTS1)
002C16
(14) Port P6 direction register (P6D)
000D16
0016
(46) Comparator data register (CMPD)
002D16 X X X X X X X X
(15) Port P7 (P7)
000E16
0016
(47) Port control register 1 (PCTL1)
002E16
0016
(16) Port P7 direction register (P7D)
000F16
0016
(48) Port control register 2 (PCTL2)
002F16
0016
(17) Port P8 (P8)
001016
0016
(49) PWM0H register (PWM0H)
003016 X X X X X X X X
(18) Port P8 direction register (P8D)
001116
0016
(50) PWM0L register (PWM0L)
003116 X 0 X X X X X X
(19) I2C data shift register (S0)
001216 X X X X X X X X
(51) PWM1H register (PWM1H)
003216 X X X X X X X X
(20) I2C address register (S0D)
001316
(52) PWM1L register (PWM1L)
003316 X 0 X X X X X X
(21) I2C status register (S1)
001416 0 0 0 1 0 0 0 X
(53) AD/DA control register (ADCON)
003416 0 0 0 0 1 0 0 0
(22) I2C control register (S1D)
001516
0016
(54) A-D conversion register 1 (AD1)
003516 X X X X X X X X
(23) I2C clock control register (S2)
001616
0016
(55) D-A1 conversion register (DA1)
003616
0016
(24) I2C start/stop condition control register (S2D)
001716 0 0 0 1 1 0 1 0
(56) D -A 2 conversion register (DA2)
003716
0016
(25) Transmit/Receive buffer register (TB/RB)
001816 X X X X X X X X
(57) A -D conversion register 2 (AD2)
003816 0 0 0 0 0 0 X X
(26) Serial I/O1 status register (SIO1STS)
001916 1 0 0 0 0 0 0 0
(58) Interrupt source selection register (INTSEL)
003916
0016
(27) Serial I/O1 control register (SIO1CON)
001A16
(59) Interrupt edge selection register (INTEDGE)
003A16
0016
(28) UART control register (UARTCON)
001B16 1 1 1 0 0 0 0 0
(60) CPU mode register (CPUM)
003B16 0 1 0 0 1 0
(29) Baud rate generator (BRG)
001C16 X X X X X X X X
(61) Interrupt request register 1 (IREQ1)
003C16
0016
(30) Serial I/O2 control register (SIO2CON)
001D16
(62) Interrupt request register 2 (IREQ2)
003D16
0016
(31) Watchdog timer control register (WDTCON)
001E16 0 0 1 1 1 1 1 1
(63) Interrupt control register 1 (ICON1)
003E16
0016
(32) Serial I/O2 register (SIO2)
001F16 X X X X X X X X
(64) Interrupt control register 2 (ICON2)
003F16
0016
(65) Flash memory control register (FCON) 0FFE16
0016
(66) Flash command register (FCMD)
0FFF16
0016
(67) Processor status register
(PS)
(68) Program counter
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
0016
0016
0016
Note : ✻ The initial values depend on level of the CNVSS pin.
X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
0016
✻
0
X X X X X1 X X
Fig. 57 Internal status at reset
57
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3886 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
Frequency Control
(1) Middle-speed mode
XCIN
The internal clock φ is the frequency of X IN divided by 8. After reset, this mode is selected.
XCOUT
Rf
(2) High-speed mode
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
XIN
XOUT
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
Fig. 58 Ceramic resonator circuit
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN).
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
Either X IN or X CIN divided by 16 is input to the prescaler 12 as
count source, and the output of the prescaler 12 is connected to
timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before
executing the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU (remains at “H”) until timer 1 underflows. The internal clock φ
is supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
58
XCIN
XCOUT
Open
Open
External oscillation
circuit
External oscillation
circuit
VCC
VSS
VCC
VSS
Fig. 59 External clock input circuit
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note)
Low-speed mode
1/2
1/4
Prescaler 12
1/2
High-speed or
middle-speed
mode
Timer 1
Reset or
0116 STP instruction
FF16
Main clock division ratio
selection bits (Note)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
Fig. 60 System clock generating circuit block diagram (Single-chip mode)
59
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
C
“0 M4
CM ”←
“1 6 →“
1”
”←
→
“0
”
”
“0
→
CM ”←
0”
“1 M6 →“
C ”←
“1
4
C M6
“1”←→“0”
C
“0 M7
CM ”←→
“1 6
“1
”←
”
→
“0
”
CM4
“1”←→“0”
CM4
“1”←→“0”
CM7=0
CM6=1
CM5=0(10 MHz oscillating)
CM4=0(32 kHz stopped)
Middle-speed mode
(f(φ)=1.25 MHz)
CM7=0
CM6=1
CM5=0(10 MHz oscillating)
CM4=1(32 kHz oscillating)
High-speed mode
(f(φ)=5 MHz)
CM7=0
CM6=0
CM5=0(10 MHz oscillating)
CM4=0(32 kHz stopped)
C M6
“1”←→“0”
High-speed mode
(f(φ)=5 MHz)
CM7=0
CM6=0
CM5=0(10 MHz oscillating)
CM4=1(32 kHz oscillating)
CM7
“1”←→“0”
Middle-speed mode
(f(φ)=1.25 MHz)
Low-speed mode
(f(φ)=16 kHz)
CM5
“1”←→“0”
CM7=1
CM6=0
CM5=0(10 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
(f(φ)=16 kHz)
CM7=1
CM6=0
CM5=1(10 MHz stopped)
CM4=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 ( High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 10 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 61 State transitions of system clock
60
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
Single-chip mode, memory expansion mode, and microprocessor
mode in the M38867M8A/E8A can be selected by changing the
contents of the processor mode bits (CM0 and CM1 : b1 and b0 of
address 003B16). In memory expansion mode and microprocessor
mode, memory can be expanded externally through ports P0 to
P3. In these modes, ports P0 to P3 lose their I/O port functions
and become bus pins.
000816
Port P3
Function
Outputs low-order 8 bits of address.
Outputs high-order 8 bits of address.
Operates as I/O pins for data D7 to D0
(including instruction code).
P30 and P31 function only as output pins
(except that the port latch cannot be read).
P32 is the ONW input pin.
P33 is the RESETOUT output pin. (Note)
P34 is the φ output pin.
P35 is the SYNC output pin.
P36 is the WR output pin, and P37 is the RD output pin.
Note : If CNV SS is connected to VSS, the microcomputer goes to singlechip mode after a reset, so that this pin cannot be used as the
RESETOUT output pin.
(1) Single-chip mode
000816
SFR area
SFR area
004016
004016
Internal RAM
reserved area
Table 15 Port functions in memory expansion mode and
microprocessor mode
Port Name
Port P0
Port P1
Port P2
000016
000016
XXXX16*
Internal RAM
reserved area
XXXX16*
YYYY16*
Internal ROM
FFFF16
FFFF16
Memory expansion mode
Microprocessor mode
The shaded area are external memory area.
*: XXXX16 indicates the last address of internal RAM.
YYYY16 indicates the first address of internal ROM.
Fig. 62 Memory maps in various processor modes
Select this mode by resetting the microcomputer with CNVSS connected to VSS.
(2) Memory expansion mode
Select this mode by setting the processor mode bits (b1, b0) to
“01” in software with CNVSS connected to VSS. This mode enables
external memory expansion while maintaining the validity of the internal ROM.
However, do not set this mode in the M38869M8A/MCA/MFA and
the flash memory version.
(3) Microprocessor mode
Select this mode by resetting the microcomputer with CNVSS connected to V CC, or by setting the processor mode bits to “10” in
software with CNVSS connected to VSS. In microprocessor mode,
the internal ROM is no longer valid and external memory must be
used.
Do not set this mode in the M38869M8A/MCA/MFA and the flash
memory version.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits (CM1, CM0)
b1 b0
0
0
1
1
0: Single-chip mode
1: Memory expansion mode (Note)
0: Microprocessor mode (Note)
1: Not available
Stack page selection bit
0: 0 page
1: 1 page
Note: This is not available for the products except
M38867M8A/E8A.
Fig. 63 Structure of CPU mode register
61
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUS CONTROL AT MEMORY EXPANSION
The M38867M8A/E8A have a built-in ONW function to facilitate
access to an external (expanded) memory and I/O devices in
memory expansion mode or microprocessor mode.
If an “L” level signal is input to the P32/ONW pin when the CPU is
in a read or write state, the corresponding read or write cycle is
extended by one cycle of φ. During this extended term, the RD
and WR signals remain at “L.” This extension function is valid only
for writing to and reading from addresses 0000 16 to 000716 and
044016 to FFFF16, and only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
φ
AD15—AD0
RD
WR
ONW
*
*
*
* Term where ONW input signal is received.
During this term, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16,
because the ONW signal is not received.
Fig. 64 ONW function timing
62
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
EPROM MODE
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. The One Time PROM version and the built-in EPROM
version have the function of the M5M27C101 corresponding for
writing to the built-in PROM. Set the address of PROM programmer in the user ROM area.
Table 16 Programming adapter
Package
Name of Programming Adapter
80P6Q-A
PCA4738H-80A
80D0
PCA4738L-80A
Table 17 PROM programmer setup
PROM programmer setup
Product name
Corresponding
device
M38867E8AHP M5M27C101K
byte
program
M38867E8AFS
Writing
area
0808016
|
0FFFD16
ROM area of
microcomputer
808016
|
FFFD16
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 65 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 65 Programming and testing of One Time PROM version
63
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLASH MEMORY MODE
Functional Outline (parallel input/output mode)
The M38869FFAHP/GP has the flash memory mode in addition to
the normal operation mode (microcomputer mode). The user can
use this mode to perform read, program, and erase operations for
the internal flash memory.
The M38869FFAHP/GP has three modes the user can choose:
the parallel input/output and serial input/output mode, where the
flash memory is handled by using the external programmer, and
the CPU reprogramming mode, where the flash memory is
handled by the central processing unit (CPU). The following explains these modes.
In the parallel input/output mode, the M38869FFAHP/GP allow the
user to choose an operation mode between the read-only mode
and the read/write mode (software command control mode) depending on the voltage applied to the V PP pin. When VPP = VPPL,
the read-only mode is selected, and the user can choose one of
three states (e.g., read, output disable, or standby) depending on
___ ___
___
inputs to the CE, OE, and WE pins. When VPP = VPPH, the read/
write mode is selected, and the user can choose one of four states
(e.g., read, output disable, standby, or write) depending on inputs
__ __
___
to the CE, OE, and WE pins. Table 19 shows assignment states of
control input and each state.
(1) Flash memory mode 1 (parallel I/O mode)
● Read
__
The microcomputer enters the read state by driving the CE, and
__
___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0–A16).
are output to the data input/output pins (D0–D7).
The parallel I/O mode can be selected by connecting wires as
shown in Figures 65 and supplying power to the V CC and V PP
pins. In this mode, the M38869FFAHP/GP operates as an equivalent of MITSUBISHI’s CMOS flash memory M5M28F101.
However, because the M38869FFAHP/GP’s internal memory has
a capacity of 60 Kbytes, programming is available for addresses
01000 16 to 0FFFF16, and make sure that the data in addresses
0000016 to 00FFF16 and addresses 1000016 to 1FFFF16 are FF16.
Note also that the M38869FFAHP/GP does not contain a facility to
read out a device identification code by applying a high voltage to
address input (A9). Be careful not to erratically set program conditions when using a general-purpose PROM programmer.
Table 18 shows the pin assignments when operating in the parallel input/output mode.
Table 18
● Output disable
The microcomputer enters the output disable state by driving the
__
___
__
CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state.
● Standby
__
The microcomputer enters the standby state by driving the CE pin
high. the M38869FFAHP/GP is placed in a power-down state consuming only a minimal supply current. At this time, the data input/
output pins enter the floating state.
Pin assignments of M38869FFAHP/GP when
operating in the parallel input/output mode
VCC
VPP
VSS
Address input
Data I/O
__
CE
___
OE
___
WE
M38869FFAHP/GP
VCC
CNVSS
VSS
Ports P0, P1, P31
Port P2
P36
P37
P33
M5M28F101
VCC
VPP
VSS
A0–A16
D0–D7
__
CE
__
OE
___
WE
● Write
The microcomputer enters the write state by driving the VPP pin
___
__
high (V PP = VPPH) and then the WE pin low when the CE pin is
__
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this software command.
Table 19 Assignment sates of control input and each state
Pin
Mode
Read-only
Read/Write
State
Read
Output disable
Standby
Read
Output disable
Standby
Write
Note: × can be VIL or VIH.
64
__
__
___
CE
OE
WE
VPP
Data I/O
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
×
VIL
VIH
×
VIH
VIH
VIH
×
VIH
VIH
×
VIL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
Output
Floating
Floating
Output
Floating
Floating
Input
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Pin description (flash memory parallel I/O mode)
Pin
Name
VCC, VSS
CNVSS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
P30–P37
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Address input (A0–A7)
Address input (A8–A15)
Data I/O (D0–D7)
Control signal input
P40–P47
P50–P57
P60–P67
P70–P77
P80–P87
Input port P4
Input port P5
Input port P6
Input port P7
Input port P8
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 5 V ± 10 % in read-only mode, connect to 11.7 to 12.6 V in read/write mode.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Connect to VSS.
Port P0 functions as 8-bit address input (A0–A7).
Port P1 functions as 8-bit address input (A8–A15).
Function as 8-bit data’s I/O pins__
(D0__
–D7). ___
P37, P36 and P33 function as the OE, CE and WE input pins respectively. P31 functions as
the A16 input pin. Connect P30 and P32 to VSS. Input “H” or “L” to P34, P35, or keep
them open.
Connect P44, P46 to VSS. Input “H” or “L” to P40 - P43, P45, P47, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
65
MITSUBISHI MICROCOMPUTERS
3886 Group
A13
A12
A9
A11
A10
A8
A7
A6
A5
A4
A3
A2
A1
A0
CE
OE
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
WE
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
A16
Vcc
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
61
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
M38869FFAHP
M38869FFAGP
25
24
77
78
79
80
23
22
21
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
V ss
*
Vpp
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
* :Coninndeicctattoesththeeceflarasmh imc eomscoilrlay tpioinn.circuit.
Fig. 66
66
Pin connection of M38869FFAHP/GP when operating in parallel input/output mode
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Read-only Mode
shown in Figure 67, and the M38869FFAHP/GP will output the
contents of the user’s specified address from data I/O pin to the
external. In this mode, the user cannot perform any operation
other than read.
The microcomputer enters the read-only mode by applying VPPL
to the VPP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
VIH
Address
Valid address
VIL
tRC
VIH
CE
VIL
ta(CE)
VIH
OE
VIL
tWRR
tDF
VIH
WE
VIL
VOH
Data
ta(OE)
Floating
Dout
tCLZ
VOL
tDH
tOLZ
Floating
ta(AD)
Fig. 67 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPPH
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38869FFAHP/GP executes the specified operation.
Table 21 shows the software commands and the input/output information in the first and the second cycles. The input address is
___
latched internally at the falling edge of the WE input; software
commands and other input data are latched internally at the rising
___
edge of the WE input.
The following explains each software command. Refer to Figures 68
to 70 for details about the signal input/output timings.
Table 21 Software command (Parallel input/output mode)
Symbol
Read
Program
Program verify
Erase
Erase verify
Reset
Device identification
First cycle
Address input
×
×
×
×
Verify address
×
×
Data input
0016
4016
C016
2016
A016
FF16
9016
Second cycle
Address input
Data I/O
Read address
Read data (Output)
Program address
Program data (Input)
×
Verify data (Output)
×
2016 (Input)
×
Verify data (Output)
×
FF16 (Input)
ADI
DDI (Output)
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 0000116
DDI = Device identification data : manufacturer’s code 1C16, device code D016
X can be VIL or VIH.
67
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Read command
The microcomputer enters the read mode by inputting command
code “00 16” in the first cycle. The command code is latched into
___
the internal command latch at the rising edge of the WE input.
When the address of a memory location to be read is input in the
second cycle, with control signals input at the timing shown in
Figure 68, the M38869FFAHP/GP outputs the contents of the
specified address from the data I/O pins to the external.
The read mode is retained until any other command is latched into
the command latch. Consequently, once the M38869FFAHP/GP enters the read mode, the user can read out the successive memory
contents simply by changing the input address and executing the
second cycle only. Any command other than the read command
must be input beginning from its command code over again each
time the user execute it. The contents of the command latch immediately after power-on is 0016.
VIH
Address
Valid address
VIL
tRC
tWC
VIH
CE
VIL
tCH
ta(CE)
tCS
VIH
OE
VIL
tRRW
tWP
tWRR
tDF
VIH
WE
VIL
ta(OE)
tDS
VIH
Data
VIL
tDH
tVSC
VPPH
VPP
VPPL
Fig. 68 Timings during reading
68
tOLZ
0016
tCLZ
ta(AD)
Dout
tDH
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
The microcomputer enters the program mode by inputting command code “4016” in the first cycle. The command code is latched
___
into the internal command latch at the rising edge of the WE input.
When the address which indicates a program location and data is
input in the second cycle, the M38869FFAHP/GP internally
___
latches the address at the falling edge of the WE input and the
___
data at the rising edge of the WE input. The M38869FFAHP/GP
___
starts programming at the rising edge of the WE input in the second cycle and finishes programming within 10 µs as measured by
its internal timer. Programming is performed in units of bytes.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 71 for the programming flowchart.
● Program verify command
The microcomputer enters the program verify mode by inputting
command code “C016” in the first cycle. This command is used to
verify the programmed data after executing the program command. The command code is latched into the internal command
___
latch at the rising edge of the WE input. When control signals are
input in the second cycle at the timing shown in Figure 69, the
M38869FFAHP/GP outputs the programmed address’s contents to
the external. Since the address is internally latched when the program command is executed, there is no need to input it in the
second cycle.
Program verify
VIH
Program
address
Address
VIL
tAS
tWC
Program
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDP
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
4016
Data
VIL
DIN
tDH
C016
tDH
Dout
tDH
Verify data output
tVSC
VPPH
VPP
VPPL
Fig. 69 Input/output timings during programming (Verify data is output at the same timing as for read.)
69
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase command
The erase command is executed by inputting command code 2016
in the first cycle and command code 2016 again in the second
cycle. The command code is latched into the internal command
___
latch at the rising edges of the WE input in the first cycle and in
the second cycle, respectively. The erase operation is initiated at
___
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 71
for the erase flowchart.
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
A016 in the first cycle. The address is internally latched at the fall___
ing edge of the WE input, and the command code is internally
___
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 70, the
M38869FFAHP/GP outputs the contents of the specified address
to the external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
Erase verify
VIH
Address
Erase
VIL
Verify
address
tAS
tWC
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDE
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
2016
Data
2016
A016
VIL
tVSC
tDH
tDH
tDH
VPPH
VPP
VPPL
Fig. 70 Input/output timings during erasing (verify data is output at the same timing as for read.)
70
Dout
Verify data output
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Reset command
The reset command provides a means of stopping execution of
the erase or program command safely. If the user inputs command
code FF16 in the second cycle after inputting the erase or program
command in the first cycle and again input command code FF 16 in
the third cycle, the erase or program command is disabled (i.e.,
reset), and the M38869FFAHP/GP is placed in the read mode. If
the reset command is executed, the contents of the memory does
not change.
● Device identification code command
By inputting command code 90 16 in the first cycle, the user can
read out the device identification code. The command code is
latched into the internal command latch at the rising edge of the
___
WE input. At this time, the user can read out manufacture’s code
1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input
pins in the second cycle; the user can read out device code D016
(i. e., 1M-bit flash memory) by inputting 000116.
These command and data codes are input/output at the same timing as for read.
71
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Program
Erase
START
START
VCC = 5 V, VPP = VPPH
VCC = 5 V, VPP = VPPH
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
DURATION = 10 µs
X=X+1
WRITE PROGRAM-VERIFY
COMMAND
C016
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
DURATION = 9.5 ms
DURATION = 6 µs
YES
X=X+1
X = 25 ?
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
FAIL
YES
X = 1000 ?
NO
INC ADRS
A016
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
0016
VERIFY BYTE ?
FAIL
PASS
VPP = VPPL
NO
INC ADRS
DEVICE
PASSED
DEVICE
FAILED
LAST ADRS ?
YES
WRITE READ COMMAND
0016
VPP = VPPL
DEVICE
PASSED
Fig. 71 Programming/Erasing algorithm flow chart
72
DEVICE
FAILED
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
Limits
Typ.
Max.
1
__
ISB1
ISB2
VCC = 5.5 V, CE = VIH
V
CC = 5.5 V,
__
CE = VCC ± 0.2 V
__
VCC = 5.5 V, CE = VIL,
tRC = 150 ns, IOUT = 0 mA
VPP = VPPH
VPP = VPPH
0≤VPP≤VCC
VCC<VPP≤VCC + 1.0 V
VPP = VPPH
VPP = VPPH
VPP = VPPH
VCC supply current (at standby)
ICC1
VCC supply current (at read)
ICC2
ICC3
VCC supply current (at program)
VCC supply current (at erase)
IPP1
VPP supply current (at read)
IPP2
IPP3
VIL
VIH
VOL
VOH1
VOH2
VPPL
VPPH
VPP supply current (at program)
VPP supply current (at erase)
“L” input voltage
“H” input voltage
“L” output voltage
“H” output voltage
0
2.0
IOL = 2.1 mA
IOH = –400 µA
IOH = –100 µA
VPP supply voltage (read only)
VPP supply voltage (read/write)
2.4
VCC –0.4
VCC
11.7
12.0
Unit
mA
100
µA
15
mA
15
15
10
100
100
30
30
0.8
VCC
0.45
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
V
V
VCC + 1.0
12.6
AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Table 23 Read-only mode
Symbol
tRC
ta(AD)
ta(CE)
ta(OE)
tCLZ
tOLZ
tDF
tDH
tWRR
Parameter
Read cycle time
Address access time
__
CE access time
__
OE access time
__
Output enable time (after CE)
__
Output enable time (after OE)
__
Output floating time (after OE)
__ __
Output valid time (after CE, OE, address)
Write recovery time (before read)
Limits
Min.
250
Max.
250
250
100
0
0
35
0
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Table 24 Read/Write mode
Symbol
Parameter
tWC
tAS
tAH
tDS
tDH
tWRR
tRRW
tCS
tCH
tWP
Write cycle time
Address set up time
Address hold time
Data setup time
Data hold time
Write recovery time (before read)
Read recovery time (before write)
__
CE setup time
__
CE hold time
Write pulse width
tWPH
tDP
tDE
tVSC
Write pulse waiting time
Program time
Erase time
VPP setup time
Limits
Min.
150
0
60
50
10
6
0
20
0
60
20
10
9.5
1
Max.
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
Note: Read timing of Read/Write mode is same as Read-only mode.
73
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Flash memory mode 2 (serial I/O mode)
connecting wires as shown in Figures 72 and powering on the VCC
pin and then applying VPPH to the VPP pin.
In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and
error check.
Serial input/output is accomplished synchronously with the clock,
beginning from the LSB (LSB first).
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
OE
The M38869FFAHP/GP has a function to serially input/output the
software commands, addresses, and data required for operation
on the internal flash memory (e. g., read, program, and erase) using only a few pins. This is called the serial I/O (input/output)
mode. This mode can be selected by driving the SDA (serial data
__
input/output), SCLK (serial clock input ), and OE pins high after
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Vcc
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
40
39
38
37
36
61
62
63
64
65
35
34
33
32
66
67
68
69
70
71
72
73
74
M38869FFAHP
M38869FFAGP
31
30
29
28
27
26
25
24
23
75
76
77
78
79
80
22
21
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
Vss
*
Vpp
SDA
SCLK
BUSY
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
* :Coninnedcictatotetshtehecefrlaasmhicmoesmciollraytiopnin.circuit.
Fig. 72 Pin connection of M38869FFAHP/GP when operating in serial I/O mode
74
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 25 Pin description (flash memory serial I/O mode)
Pin
Name
VCC, VSS
CNVSS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
P30–P36
P37
P40–P43,
P45
P44
P46
P47
P50–P57
P60–P67
P70–P77
P80–P87
Input port P3
Control signal input
Input port P4
SDA I/O
SCLK input
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Output
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 11.7 to 12.6 V.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Input an arbitrary level between the range of VSS and VCC.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
__
OE input pin
Input “H” or “L” to P40 - P43, P45, or keep them open.
This pin is for serial data I/O.
This pin is for serial clock input.
This pin is for BUSY signal output.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
75
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Functional Outline (serial I/O mode)
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the
contents of the command. Table 26 shows the software commands used in the serial I/O mode. The following explains each
software command.
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Table 26 Software command (serial I/O mode)
Number of transfers First command
Command
code input
Read
0016
Program
4016
Program verify
C016
Erase
2016
Erase verify
A016
Error check
8016
Second
Third
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Verify address L (Input)
Error code (Output)
Fourth
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
__
● Read command
Input command code 0016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the M38869FFAHP/GP
reads out the contents of the specified address, and then latchs it
into the internal data latch. When the OE pin is released back high
and serial clock is input to the SCLK pin, the read data that has
been latched into the data latch is serially output from the SDA
pin.
tCH
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 0 0 0
Command code input (0016) Read address input (L)
A8
A15
Read address input (H)
tCR
D0
tWR
tRC
Read data output
OE
Read
BUSY “L”
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 73 Timings during reading
76
D7
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
Input command code 4016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the serial clock during program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 µs as measured by the internal timer, and the BUSY pin
is pulled low.
Note : A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the
verification. Refer to Figure 71 for the programming flowchart.
tCH
tCH
tCH
SCLK
tPC
A0
SDA
0 0 0 0 0 0 1 0
Command code input (4016)
A8
A7
D0
A15
Program address input (L) Program address input (H)
D7
Program data input
OE
tWP
Program
BUSY
Fig. 74 Timings during programming
● Program verify command
Input command code C016 in the first transfer. Proceed and drive
__
the OE pin low. When this is done, The M38869FFAHP/GP verifyreads the programmed address’s contents, and then latchs it into
__
the internal data latch. When the OE pin is released back high and
serial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
SCLK
D0
SDA
0 0 0 0 0 0 1 1
Command code input (C016)
D7
Verify data output
tCRPV
tWR
tRC
OE
Verify read
BUSY “L”
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 75 Timings during program verify
77
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase command
Input command code 2016 in the first transfer and command code
20 16 again in the second transfer. When this is done, the
M38869FFAHP/GP executes an erase command. Erase is initiated at the last rising edge of the serial clock. The BUSY pin is
driven high during the erase operation. Erase is completed within
9.5 ms as measured by the internal timer, and the BUSY pin is
pulled low. Note that data 0016 must be written to all memory loca-
tions before executing the erase command.
Note: A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification.
Refer to Figure 71 for the erase flowchart.
tCH
SCLK
tEC
SDA
0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0
Command code input (2016) Command code input (2016)
“H”
OE
twE
BUSY
Erase
Fig. 76 Timings at erasing
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. Input command code A016 in the first
transfer. Proceed and input the low-order 8 bits and the high-order
__
8 bits of the address and pull the OE pin low. When this is done,
the M38869FFAHP/GP reads out the contents of the specified ad__
dress, and then latchs it into the internal data latch. When the OE
pin is released back high and serial clock is input to the SCLK pin,
the verify data that has been latched into the data latch is serially
output from the SDA pin.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
tCH
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 1 0 1
Command code input (A016) Verify address input (L)
A8
A15
Verify address input (H)
tCREV
D0
tWR
tRC
D7
Verify data output
OE
Verify read
BUSY “L”
Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 77 Timings during erase verify
78
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Error check command
Input command code 80 16 in the first transfer, and the
M38869FFAHP/GP outputs error information from the SDA pin,
beginning at the next falling edge of the serial clock. If the LSB bit
of the 8-bit error information is 1, it indicates that a command error
has occurred. A command error means that some invalid commands other than commands shown in Table 26 has been input.
When a command error occurs, the serial communication circuit
sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the
serial communication circuit does not accept the subsequent serial
clock and data (even including an error check command). Therefore, if the user wants to execute an error check command,
temporarily drop the VPP pin input to the V PPL level to terminate
the serial input/output mode. Then, place the M38869FFAHP/GP
into the serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands.
The error flag alone is not cleared by this operation, so the user
can examine the serial communication circuit’s error conditions
before reset. This examination is done by the first execution of an
error check command after the reset. The error flag is cleared
when the user has executed the error check command. Because
the error flag is undefined immediately after power-on, always be
sure to execute the error check command.
tCH
SCLK
E0
SDA
OE
0 0 0 0 0 0 0 1
Command code input (8016)
? ? ? ? ? ? ?
Error flag output
“H”
BUSY “L”
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
Fig. 78 Timings at error checking
Note: The programming/erasing algorithm flow chart of the serial
I/O mode is the same as that of the parallel I/O mode. Refer to Figure 71.
79
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, unless otherwise noted)
ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. V IH, VIL, VOH, VOL, IIH, and
__
IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 27 AC Electrical characteristics
(Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, f(XIN) = 10 MHz, unless otherwise noted)
Symbol
tCH
tCR
tWR
tRC
tCRPV
tWP
tPC
tCREV
tWE
tEC
tc(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
td(C-Q)
th(C-Q)
th(C-E)
tsu(D-C)
th(C-D)
Limits
Min.
Max.
500(Note 1)
500(Note 1)
400(Note 2)
500(Note 1)
6
10
500(Note 1)
6
9.5
500(Note 1)
250
100
100
20
20
0
90
0
150(Note 3) 250(Note 4)
30
90
Parameter
Serial transmission interval
Read waiting time after transmission
Read pulse width
Transfer waiting time after read
Waiting time before program verify
Programming time
Transfer waiting time after programming
Waiting time before erase verify
Erase time
Transfer waiting time after erase
SCLK input cycle time
SCLK high-level pulse width
SCLK low-level pulse width
SCLK rise time
SCLK fall time
SDA output delay time
SDA output hold time
SDA output hold time (only the 8th bit)
SDA input set up time
SDA input hold time
Unit
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 1.
5000
× 106
f(XIN)
2: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 2.
Formula 1 :
4000
× 106
f(XIN)
3: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 3.
Formula 2 :
1500
× 106
f(XIN)
4: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 4
Formula 3 :
Formula 4 :
2500
f(XIN)
× 106
AC waveforms
tf(CK)
tw(CKL)
tc(CK)
tr(CK)
tw(CKH)
SCLK
th(C-Q)
td(C-Q)
th(C-E)
Test conditions for AC characteristics
SDA output
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
tsu(D-C)
SDA input
80
th(C-D)
• Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38869FFAHP/GP has the CPU reprogramming mode where
a built-in flash memory is handled by the central processing unit
(CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 79) and the flash command register (see Figure 80).
The CNVSS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
Functional Outline (CPU reprogramming mode)
Figure 79 shows the flash memory control register bit configuration. Figure 80 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to “1” and V PP H is
applied to the CNVss/V PP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
7
6
0
5
4
3
0
2
1
Whether these operations have been completed or not is judged
by checking this flag after each command of erase and the program is executed.
Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Only for the specified area, programming is enabled; for
the other areas, programming is disabled.
When CPU reprogramming mode is valid, the area where is not
specified by the erase/program area select bits cannot be read
out.
Transfer CPU reprogramming mode control program to internal
RAM before entering the CPU reprogramming mode, and then execute this program on internal RAM.
If an interrupt occurs while this program is being executed, the
flash memory area is accessed, but normally operation cannot be
performed because the flash memory area cannot be read out.
During CPU reprogramming mode control program execution, execute the processing such as interrupt disabled, etc.
Figure 81 shows the CPU mode register bit configuration in the
CPU reprogramming mode. Set bits 1 and 0 to “00” (single-chip
mode) in the CPU reprogramming mode.
0
Flash memory control regsiter
(FCON : address 0FFE16)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Fix this bit to “0.”
Erase/Program area select bits
0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes)
0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes)
1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes)
1 1 : Not available
Fix this bit to “0.”
Not used (returns "0" when read)
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 79 Flash memory control register bit configuration
81
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● CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is described below.
< Beginning procedure >
➀ Apply 0 V to the CNVss/VPP pin for reset release.
➁ After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program).
➂ Set “1" to the CPU reprogramming mode select bit.
➃ Apply VPPH to the CNVSS/VPP pin.
➄ Wait till CNVSS/VPP pin becomes 12 V.
➅ Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
➆ The operation of the flash memory is executed by software-command-writing to the flash command register .
Note: The following are necessary other than this:
•Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
•Initial setting for ports etc.
•Writing to the watchdog timer
< Release procedure >
➀ Apply 0V to the CNVSS/VPP pin.
➁ Wait till CNVSS/VPP pin becomes 0V.
➂ Set the CPU reprogramming mode select bit to “0.”
Each software command is explained as follows.
● Read command
When “00 16 " is written to the flash command register, the
M38869FFAHP/GP enters the read mode. The contents of the
corresponding address can be read by reading the flash memory
(For instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
b7
7
6
5
4
3
2
1
0
Flash command register
(FCMD : address 0FFF16)
Writing of software command
<Software command name>
<Command code>
• Read command
“0016”
• Program command
“4016”
• Program verify command
“C016”
• Erase command
“2016” + “2016”
• Erase verify command
“A016”
• Reset command
“FF16” + “FF16”
Note: The flash command register is write-only register.
Fig. 80 Flash command register bit configuration
82
b0
0
0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Not available
1 X : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Fig. 81 CPU mode register bit configuration in CPU rewriting
mode
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
When “40 16 ” is written to the flash command register, the
M38869FFAHP/GP enters the program mode.
Subsequently to this, if the instruction (for instance, STA
instruction) for writing byte data in the address to be programmed
is executed, the control circuit of the flash memory executes the
program. The erase/program busy flag of the flash memory control
register is set to “1” when the program starts, and becomes “0”
when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the
program by polling this bit.
The programmed area must be specified beforehand by the erase/
program area select bits.
During programming, watchdog timer stops with “FFFF16” set.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 82 for the flow chart of the programming.
● Program verify command
When “C0 16 ” is written to the flash command register, the
M38869FFAHP/GP enters the program verify mode. Subsequently
to this, if the instruction (for instance, LDA instruction) for reading
byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the
address actually is read.
CPU compares this read data with data which has been written by
the previous program command. In consequence of the comparison, if not agreeing, the operation of “program → program verify”
must be executed again.
● Erase verify command
When “A0 16 ” is written to the flash command register, the
M38869FFAHP/GP enters the erase verify mode. Subsequently to
this, if the instruction (for instance, LDA instruction) for reading
byte data from the address to be verified, the contents of the address is read.
CPU must erase and verify to all erased areas in a unit of address.
If the address of which data is not “FF16” (i.e., data is not erased)
is found, it is necessary to discontinue erasure verification there,
and execute the operation of “erase → erase verify” again.
Note: By executing the operation of “erase → erase verify” again
when the memory not erased is found. It is unnecessary to
write data “0016” before erasing in this case.
● Reset command
The reset command is a command to discontinue the program or
erase command on the way. When “FF16” is written to the command
register two times continuously after “4016” or “2016” is written to the
flash command register, the program, or erase command becomes
invalid (reset), and the M38869FFAHP/GP enters the reset mode.
The contents of the memory does not change even if the reset command is executed.
DC Electric Characteristics
Note: The characteristic concerning the flash memory part are the
same as the characteristic of the parallel I/O mode.
AC Electric Characteristics
Note: The characteristics are the same as the characteristic of the
microcomputer mode.
● Erase command
When writing “2016” twice continuously to the flash command register, the flash memory control circuit performs erase to the area
specified beforehand by the erase/program area select bits.
Erase/program busy flag of the flash memory control register becomes “1” when erase begins, and it becomes “0” when erase
completes. Accordingly, CPU can recognize the completion of
erase by polling this bit.
Data “0016” must be written to all areas to be erased by the program and the program verify commands before the erase
command is executed.
During erasing, watchdog timer stops with “FFFF16” set.
Note: The erasing operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 82 for
the erasing flowchart.
83
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Program
Erase
START
START
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
WAIT 1µs
NO
ERASE PROGRAM
BUSY FLAG = 0
YES
X=X+1
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
WAIT 1µs
WRITE PROGRAM-VERIFY
COMMAND
C016
NO
ERASE PROGRAM
BUSY FLAG = 0
DURATION = 6 µs
YES
X=X+1
X = 25 ?
YES
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
A016
FAIL
YES
X = 1000 ?
INC ADRS
NO
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
VERIFY BYTE ?
0016
FAIL
PASS
DEVICE
PASSED
DEVICE
FAILED
NO
INC ADRS
LAST ADRS ?
YES
WRITE READ COMMAND
DEVICE
PASSED
Fig. 82 Flowchart of program/erase operation at CPU reprogramming mode
84
0016
DEVICE
FAILED
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1.”
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. SOUT2 pin for serial I/O2 goes to high
impedance after transfer is completed.
When in serial I/O1 (clock-synchronous mode) or in serial I/O2, an
external clock is used as synchronous clock, write transmission
data to the transmit buffer register or serial I/O2 register, during
transfer clock is “H.”
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
D-A Converter
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of V CC ≥ 4.0 V
is recommended. When a D-A converter is not used, set all values
of D-Ai conversion registers (i=1, 2) to “0016.”
Multiplication and Division Instructions
Instruction Execution Time
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
The instruction execution time is obtained by multiplying the period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is half of the XIN period in highspeed mode.
When the ONW function is used in modes other than single-chip
mode, the period of the internal clock φ may be four times that of
the XIN.
Timers
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
85
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NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (V CC pin) and GND pin (V SS pin), between power
source pin (V CC pin) and analog power source input pin (AV SS
pin), and between program power source pin (CNVss/V PP) and
GND pin for flash memory version when on-board reprogramming
is executed. Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far
from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1
µF is recommended.
EPROM version/One Time PROM version/
Flash memory version
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVSS
pin and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNV SS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
Erasing of Flash memory version
Set addresses 0100016 to 0FFFF16 as memory area for erasing in
the parallel serial I/O mode and the serial I/O mode. If the memory
area for erasing is set to mistaken area, the product may be permanently damaged.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1.Mask ROM Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical copies)
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
1.ROM Programming Confirmation Form
2.Mark Specification Form
3.Data to be programmed to PROM, in EPROM form (three identical copies)
86
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 28 Absolute maximum ratings
Symbol
VCC
VCC
VI
VI
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltageS (Note 1)
Power source voltageS (Note 2)
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87, VREF
Input voltage P70–P77
Input voltage RESET, XIN
Input voltage CNVSS (Note 3)
Input voltage CNVSS (Note 4)
Input voltage
CNVSS (Note 5)
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87, XOUT
Output voltage P70–P77
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = 25 °C
Ratings
–0.3 to 7.0
–0.3 to 6.5
Unit
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 7
–0.3 to VCC +0.3
–0.3 to 13
V
V
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
500
–20 to 85
–40 to 125
V
mW
°C
°C
Notes 1: M38867M8A, M38867E8A
2: M38869M8A, M38869MCA, M38869MFA, M38869FFA
3: M38867M8A
4: M38869M8A, M38869MCA, M38869MFA
5: M38867E8A, M38869FFA
87
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Table 29 Recommended operating conditions
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
f(XIN) ≤ 4.1 MHz
f(XIN) = 10 MHz
VCC
Power source voltage (except flash memory version)
VCC
VSS
Power source voltage (flash memory version)
Power source voltage
VREF
Analog reference voltage
AVSS
VIA
Analog power source voltage
A-D converter input voltage AN0–AN7
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40, P41,
P47, P50–P57, P60–P67, P80–P87
“H” input voltage
P76, P77
“H” input voltage (when I2C-BUS input level is selected)
SDA, SCL
“H” input voltage (when SMBUS input level is selected)
SDA, SCL
“H” input voltage (when CMOS input level is selected)
P42–P46, DQ0–DQ7, W, R, S0, S1, A0
“H” input voltage (when CMOS input level is selected)
P70–P75
“H” input voltage (when TTL input level is selected)
P42–P46, DQ0–DQ7, W, R, S0, S1, A0 (Note)
“H” input voltage (when TTL input level is selected)
P70–P75 (Note)
“H” input voltage
RESET, XIN, XCIN, CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
“L” input voltage (when I2C-BUS input level is selected)
SDA, SCL
“L” input voltage (when SMBUS input level is selected)
SDA, SCL
“L” input voltage (when CMOS input level is selected)
P42–P46, P70–P75, DQ0–DQ7, W, R, S0, S1, A0
“L” input voltage (when TTL input level is selected)
P42–P46, P70–P75, DQ0–DQ7, W, R, S0, S1, A0 (Note)
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
when A-D converter is used
when D-A converter is used
Min.
2.7
4.0
4.0
Limits
Typ.
5.0
5.0
5.0
0
2.0
2.7
Max.
5.5
5.5
5.5
VCC
VCC
V
V
V
VCC
V
V
0.8VCC
VCC
V
0.8VCC
5.5
V
0.7VCC
5.5
V
1.4
5.5
V
0.8VCC
VCC
V
0.8VCC
5.5
V
2.0
VCC
V
2.0
5.5
V
0.8VCC
VCC
V
0
0.2VCC
V
0
0.3VCC
V
0
0.6
V
0
0.2VCC
V
0
0.8
V
V
V
0
“L” input voltage
RESET, CNVSS
0
0.2VCC
VIL
“L” input voltage
XIN, XCIN
0
0.16VCC
88
V
AVSS
VIL
Note : When VCC is 4.0 to 5.5 V.
Unit
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 30 Recommended operating conditions
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
ΣIOL(peak)
“L” total peak output current
P24–P27 (Note)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
ΣIOL(avg)
ΣIOL(avg)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note)
P40–P47, P50–P57, P60–P67 (Note)
P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 (Note)
In single-chip mode
In memory expansion mode
In microprocessor mode
Min.
Limits
Typ.
Max.
–80
–80
80
80
Unit
mA
mA
mA
mA
40
mA
80
–40
–40
40
40
mA
mA
mA
mA
mA
“L” total average output current
In memory expansion mode
P24–P27 (Note)
In microprocessor mode
40
mA
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note)
40
mA
P40–P47,P50–P57, P60–P67, P70–P77 (Note)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note)
P40–P47,P50–P57, P60–P67 (Note)
P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 (Note)
In single-chip mode
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
89
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Table 31 Recommended operating conditions
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOL(peak)
IOL(peak)
Parameter
“H” peak output current
“L” peak output current
“L” peak output current
P24–P27 (Note 1)
IOH(avg)
“H” average output current
IOL(avg)
“L” average output current
IOL(avg)
“L” peak output current
P24–P27 (Note 2)
f(XIN)
f(XCIN)
Min.
Limits
Typ.
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 1)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 1)
In single-chip mode
In memory expansion mode
In microprocessor mode
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
In single-chip mode
In memory expansion mode
In microprocessor mode
High-speed mode
4.0 V≤ VCC ≤ 5.5 V
High-speed mode
2.7 V≤ VCC ≤ 4.0 V
Main clock input oscillation
Middle-speed mode
frequency (Note 3)
4.0 V≤ VCC ≤ 5.5 V
Middle-speed mode
2.7 V≤ VCC ≤ 4.0 V (Note 5)
Middle-speed mode
2.7 V≤ VCC ≤ 4.0 V (Note 5)
Sub-clock input oscillation frequency (Notes 3, 4)
32.768
Max.
Unit
–10
mA
10
mA
20
mA
10
mA
–5
mA
5
mA
15
mA
5
mA
10
MHz
4.5 VCC–8
MHz
10
MHz
10
MHz
4.5 VCC–8
MHz
50
kHz
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
4: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
5: When using the timer X/Y, timer 1/2, serial I/O1, serial I/O2, A-D converter, comparator, and PWM, set the main clock input oscillation frequency to
the max. 4.5VCC–8 (MHz).
90
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 32 Electrical characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P80–P87 (Note)
“L” output voltage
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
Hysteresis
CNTR0, CNTR1, INT0, INT1
INT20–INT40, INT21–INT41
P30–P37
Hysteresis
RxD, SCLK1, SIN2, SCLK2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
“L” input current
RESET,CNVSS
“L” input current
XIN
“L” input current
P30–P37 (at Pull-up)
RAM hold voltage
Test conditions
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.6 mA
VCC = 2.7–5.5 V
Min.
Typ.
Unit
VCC–2.0
V
VCC–1.0
V
VI = VCC
VI = VCC
2.0
V
0.4
V
0.4
V
0.5
V
0.5
V
VI = VCC
(Pin floating. Pull-up
transistors “off”)
5.0
µA
5.0
µA
µA
–5.0
µA
–5.0
µA
µA
–120
µA
4
VI = VSS
(Pin floating. Pull-up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
VCC = 4.0–5.5 V
VI = VSS
VCC = 2.7–5.5 V
When clock stopped
Max.
–4
–20
–60
µA
–10
2.0
5.5
V
Note: P00–P03 are measured when the P00–P03 output structure selection bit of the port control register 1 (bit 0 of address 002E16) is “0”.
P04–P07 are measured when the P04–P07 output structure selection bit of the port control register 1 (bit 1 of address 002E16) is “0”.
P10–P13 are measured when the P10–P13 output structure selection bit of the port control register 1 (bit 2 of address 002E16) is “0”.
P14–P17 are measured when the P14–P17 output structure selection bit of the port control register 1 (bit 3 of address 002E16) is “0”.
P42, P43, P44, and P46 are measured when the P4 output structure selection bit of the port control register 2 (bit 2 of address 002F16) is “0”.
P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
91
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 33 Electrical characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Parameter
Power source current
Test conditions
High-speed mode
f(XIN) = 10 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 10 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 10 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 10 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 10 MHz
All oscillation stopped
(in STP state)
Output transistors “off”
92
Ta = 25 °C
Ta = 85 °C
Min.
Unit
Typ.
Max.
8.0
15
mA
6.8
13
mA
mA
1.6
60
200
µA
20
40
µA
20
55
µA
8.0
20.0
µA
4.0
7.0
mA
1.5
mA
800
µA
0.1
1.0
µA
10
µA
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 34 A-D converter characteristics (1)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is “0”)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
–
Resolution
bit
10
–
VCC = VREF = 5.0 V
Absolute accuracy (excluding quantization error)
LSB
±4
tCONV
Conversion time
2tc(XIN)
61
RLADDER
Ladder resistor
kΩ
12
35
100
at A-D converter operated VREF = 5.0 V
Reference power
µA
50
150
200
IVREF
source input current
VREF = 5.0 V
at A-D converter stopped
µA
5
II(AD)
A-D port input current
µA
5.0
Table 35 A-D converter characteristics (2)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is “1”)
Symbol
Parameter
–
–
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
at A-D converter operated
Reference power
source input current
at A-D converter stopped
tCONV
RLADDER
IVREF
II(AD)
Test conditions
Limits
Min.
Typ.
VCC = VREF = 5.0 V
VREF = 5.0 V
VREF = 5.0 V
12
50
35
150
A-D port input current
Max.
8
±2
50
100
200
5
5.0
Unit
bit
LSB
2tc(XIN)
kΩ
µA
µA
µA
Table 36 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)
Symbol
–
–
tsu
RO
IVREF
Parameter
Test conditions
Limits
Min.
Typ.
Resolution
VCC = 4.0–5.5 V
VCC = 2.7–4.0 V
Absolute accuracy
Setting time
Output resistor
Reference power source input current (Note 1)
1
2.5
Max.
8
1.0
2.5
3
4
3.2
Unit
Bits
%
%
µs
kΩ
mA
Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”.
Table 37 Comparator characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
Parameter
Absolute accuracy
TCONV
Conversion time
VIA
IIA
RLADDER
Analog input voltage
Analog input current
Ladder resistor
CMPREF
Test conditions
Limits
Min.
1LSB = VCC/16
at 10 MHz operating
at 8 MHz operating
at 4 MHz operating
0
20
40
Max.
1/2
2.8
3.5
7
VCC
5.0
50
29VCC
/32
Internal reference voltage
External reference input voltage
Typ.
VCC/32
Unit
LSB
µs
µs
µs
V
µA
kΩ
V
VCC
V
93
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 38 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
2
100
40
40
20
5
5
200
80
80
Typ.
Max.
Unit
µs
ns
ns
ns
µs
µs
µs
ns
ns
ns
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
Reset input “L” pulse width
Main clock input cycle time
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
tWH(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
80
ns
tWL(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
80
ns
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
800
370
370
220
100
1000
400
400
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
94
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 39 Timing requirements (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
2
1000/(4.5VCC–8)
400/(4.5VCC–8)
400/(4.5VCC–8)
20
5
5
500
230
230
Typ.
Max.
Unit
µs
ns
ns
ns
µs
µs
µs
ns
ns
ns
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
Reset input “L” pulse width
Main clock input cycle time
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
tWH(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
230
ns
tWL(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
230
ns
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
2000
950
950
400
200
2000
950
950
400
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
95
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 40 Timing requirements for system bus interface
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tsu (S-R)
tsu (S-W)
th (R-S)
th (W-S)
tsu (A-R)
tsu (A-W)
th (R-A)
th (W-A)
tw (R)
tw (W)
tsu (D-W)
th (W-D)
Parameter
S0, S1 setup time
S0, S1 setup time
S0, S1 hold time
S0, S1 hold time
A0 setup time
A0 setup time
A0 hold time
A0 hold time
Read pulse width
Write pulse width
Before write data input setup time
After write data input hold time
Limits
Min.
0
0
0
0
10
10
0
0
120
120
50
0
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 41 Timing requirements for system bus interface
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tsu (S-R)
tsu (S-W)
th (R-S)
th (W-S)
tsu (A-R)
tsu (A-W)
th (R-A)
th (W-A)
tw (R)
tw (W)
tsu (D-W)
th (W-D)
96
Parameter
S0, S1 setup time
S0, S1 setup time
S0, S1 hold time
S0, S1 hold time
A0 setup time
A0 setup time
A0 hold time
A0 hold time
Read pulse width
Write pulse width
Before write data input setup time
After write data input hold time
Limits
Min.
0
0
0
0
30
30
0
0
250
250
130
0
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 42 Switching characteristics 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Test
conditions
Limits
Min.
Typ.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Max.
140
Fig. 83
–30
30
30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
Fig. 84
0
10
10
Fig. 83
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Table 43 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Test
conditions
Fig. 83
Limits
Min.
Typ.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
Max.
350
–30
50
50
tC(SCLK2)/2–240
tC(SCLK2)/2–240
400
Fig. 84
0
Fig. 83
20
20
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
97
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 44 Switching characteristics for system bus interface
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ta(R-D)
tv(R-D)
tPLH(R-OBF)
Parameter
After read data output enable time
After read data output disable time
After read OBF00, OBF01, OBF10 output propagation time
Limits
Min.
Typ.
Max.
80
30
150
0
Unit
ns
ns
ns
Table 45 Switching characteristics for system bus interface
(VCC =2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ta(R-D)
tv(R-D)
tPLH(R-OBF)
98
Parameter
After read data output enable time
After read data output disable time
After read OBF00, OBF01, OBF10 output propagation time
Min.
0
Typ.
Max.
130
85
300
Unit
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 46 Timing requirements in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
Limits
Symbol
Parameter
tsu (ONW-φ)
th (φ-ONW)
tsu (DB-φ)
th (φ-DB)
tsu (ONW-RD), tsu (ONW-WR)
th (RD-ONW), th (WR-ONW)
tsu (DB-RD)
th (RD-DB)
Min.
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
–20
–20
50
0
–20
–20
50
0
Table 47 Switching characteristics in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
Symbol
Parameter
tC(φ)
tWH(φ)
tWL(φ)
td(φ-AH)
td(φ-AL)
tV(φ-AH)
tV(φ-AL)
td(φ-SYNC)
tV(φ-SYNC)
td(φ-DB)
tV(φ-DB)
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
tWL(RD), tWL(WR)
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
td(AH-RD), td(AH-WR)
td(AL-RD), td(AL-WR)
tV(RD-AH), tV(WR-AH)
tV(RD-AL), tV(WR-AL)
td(WR-DB)
tV(WR-DB)
td(RESET-RESETOUT)
tV(φ-RESETOUT)
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
Data bus delay time
Data bus valid time
RESETOUT output delay time
RESETOUT output valid time (Note)
Test
conditions
Limits
Min.
Typ.
Max.
2tC(XIN)
tC(XIN)–10
tC(XIN)–10
2
2
Fig. 83
16
20
5
5
16
5
15
35
40
30
10
tC(XIN)–10
3tC(XIN)–10
tC(XIN)–35
tC(XIN)–40
2
2
tC(XIN)–16
tC(XIN)–20
5
5
15
30
10
0
200
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The RESETOUT output goes “H” in synchronized with the rise of the φ clock that is anywhere between a few cycles and 10-several cycles after RESET
input goes “H”.
99
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1kΩ
Measurement output pin
Measurement output pin
100pF
100pF
CMOS output
Fig. 83 Circuit for measuring output switching characteristics (1)
100
N-channel open–drain output
Fig. 84 Circuit for measuring output switching characteristics (2)
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in single-chip mode
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
C N TR 0 , C N TR 1
0.2VCC
tWL(INT)
tWH(INT)
INT0,INT1
INT20,INT30,INT40
INT21,INT31,INT41
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(XCIN)
tWL(XCIN)
tWH(XCIN)
0.8VCC
XCIN
0.2VCC
tC(SCLK1), tC(SCLK2)
tr
tWL(SCLK1), tWL(SCLK2)
tf
SCLK1
SCLK2
tWH(SCLK1), tWH(SCLK2)
0.8VCC
0.2VCC
tsu(RxD-SCLK1),
tsu(SIN2-SCLK2)
th(SCLK1RxD),th(SCLK2SIN2)
RX D
SIN2
0.8VCC
0.2VCC
td(SCLK1-TXD),td(SCLK2-SOUT2)
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
TX D
SOUT2
Fig. 85 Timing diagram (1) (in single-chip mode)
101
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in memory expansion mode and microprocessor mode (1)
tC(φ)
tWL(φ)
tWH(φ)
φ
0.5VCC
tv(φ-AH)
td(φ-AH)
AD15–AD8
0.5VCC
td(φ-AL)
AD7–AD0
tv(φ-AL)
0.5VCC
tv(φ-SYNC)
td(φ-SYNC)
0.5VCC
SYNC
td(φ-WR)
RD,WR
tv(φ-WR)
0.5VCC
th(φ-ONW)
tSU(ONW-φ)
0.8VCC
0.2VCC
ONW
tSU(DB-φ)
0.8VCC
0.2VCC
DB0–DB7
(At CPU reading)
td(φ-DB)
DB0–DB7
(At CPU writing)
tv(φ-DB)
0.5VCC
Timing diagram in microprocessor mode
RESET
0.8VCC
0.2VCC
φ
0.5VCC
td(RESET- RESETOUT)
RESETOUT
0.5VCC
Fig. 86 Timing diagram (2) (in memory expansion mode and microprocessor mode)
102
th(φ-DB)
tv(φ- RESETOUT)
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in memory expansion mode and microprocessor mode (2)
tWL(RD)
tWL(WR)
RD,WR
0.5VCC
td(AH-RD)
td(AH-WR)
AD15–AD8
tv(RD-AH)
tv(WR-AH)
0.5VCC
td(AL-RD)
td(AL-WR)
AD7–AD0
tv(RD-AL)
tv(WR-AL)
0.5VCC
th(RD-ONW)
th(WR-ONW)
tsu(ONW-RD)
tsu(ONW-WR)
ONW
0.8VCC
0.2VCC
(At CPU reading)
RD
0.5VCC
tSU(DB-RD)
th(RD-DB)
0.8VCC
0.2VCC
DB0–DB7
(At CPU writing)
WR
0.5VCC
tv(WR-DB)
td(WR-DB)
DB0–DB7
0.5VCC
Fig. 87 Timing diagram (3) (in memory expansion mode and microprocessor mode)
103
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
System bus interface timing diagram
Read operation
tsu(A-R)
A0
th(R-A)
2.4 (0.8VCC)
0.45 (0.2VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
tsu(S-R)
S0,S1
th(R-S)
0.45 (0.2VCC)
0.45 (0.2VCC)
tw(R)
R
2.4 (0.8VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
0.45 (0.2VCC)
2.0 (0.8VCC)
0.8 (0.2VCC)
2.0 (0.8VCC)
0.8 (0.2VCC)
DQ0–DQ7
ta(R-D)
tv(R-D)
tPLH(R-OBF)
OBF00,OBF01,OBF10
0.8 (0.2VCC)
Write operation
tsu(A-W)
A0
th(W-A)
2.4 (0.8VCC)
0.45 (0.2VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
tsu(S-W)
S0,S1
th(W-S)
0.45 (0.2VCC)
0.45 (0.2VCC)
tw(W)
W
2.4 (0.8VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
0.45 (0.2VCC)
th(W-D)
DQ0–DQ7
2.4 (0.8VCC)
0.45 (0.2VCC)
tsu(D-W)
Outside of parenthesis : TTL I/O
Inside of parenthesis : CMOS I/O
Fig. 88 Timing diagram (4) (system bus interface)
104
2.4 (0.8VCC)
0.45 (0.2VCC)
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 48 Multi-master I2C-BUS bus line characteristics
Standard clock mode High-speed clock mode
Symbol
Parameter
Min.
Max.
Max.
Unit
tBUF
Bus free time
4.7
Min.
1.3
tHD;STA
Hold time for START condition
4.0
0.6
tLOW
Hold time for SCL clock = “0”
4.7
tR
Rising time of both SCL and SDA signals
tHD;DAT
Data hold time
tHIGH
Hold time for SCL clock = “1”
tF
Falling time of both SCL and SDA signals
tSU;DAT
Data setup time
250
100
ns
tSU;STA
Setup time for repeated START condition
4.7
0.6
µs
tSU;STO
Setup time for STOP condition
4.0
0.6
µs
µs
µs
µs
1.3
20+0.1Cb
300
ns
0
0
0.9
µs
4.0
0.6
1000
300
µs
20+0.1Cb
300
ns
Note: Cb = total capacitance of 1 bus line
SDA
tHD:STA
tBUF
tLOW
SCL
P
tR
tF
S
tHD:STA
Sr
tHD:DAT
tsu:STO
tHIGH
tsu:DAT
P
tsu:STA
S : START condition
Sr: RESTART condition
P : STOP condition
Fig. 89 Timing diagram of multi-master I2C-BUS
105
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
80P6Q-A
Plastic 80pin 12✕12mm body LQFP
EIAJ Package Code
LQFP80-P-1212-0.5
Weight(g)
Lead Material
Cu Alloy
MD
e
JEDEC Code
–
HD
80
ME
D
1
b2
61
60
l2
E
HE
Recommended Mount Pad
Symbol
41
20
21
40
A
F
L1
c
A2
e
b
A1
y
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
b2
I2
MD
ME
L
Detail F
80D0
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.1
0.2
0
1.4
–
–
0.13
0.18
0.28
0.105
0.125
0.175
11.9
12.0
12.1
11.9
12.0
12.1
0.5
–
–
13.8
14.0
14.2
13.8
14.0
14.2
0.3
0.5
0.7
1.0
–
–
0.1
–
–
0°
10°
–
0.225
–
–
1.0
–
–
12.4
–
–
12.4
–
–
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
21.0±0.2
Weight(g)
18.4±0.15
3.32MAX
0.8TYP
1.78TYP
0.6TYP
41
64
65
INDEX
106
0.5TYP
0.8TYP
12.0±0.15
1.2TYP
15.6±0.2
0.8TYP
40
25
80
24
1.2TYP
1
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6S-A
Plastic 80pin 14✕14mm body QFP
EIAJ Package Code
QFP80-P-1414-0.65
Weight(g)
1.11
Lead Material
Alloy 42
MD
e
JEDEC Code
HD
61
1
b2
80
ME
D
60
I2
Symbol
HE
E
Recommended Mount Pad
41
20
21
A
40
c
F
A2
L1
y
x
M
A1
b
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
13.8
14.0
14.2
0.65
–
–
16.5
16.8
17.1
16.5
16.8
17.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
0.1
–
–
0°
10°
–
0.35
–
–
–
–
1.3
14.6
–
–
–
–
14.6
107
REVISION DESCRIPTION LIST
Rev.
No.
3886 GROUP DATA SHEET
Revision Description
Rev.
date
1.0
First Edition
980216
2.0
The contents of flash memory version were added.
980716
2.1
All pages; “PRELIMINARY Notice: This is...” eliminated.
000114
Page 1; The second “In high-speed mode” of “Power dissipation” eliminated.
Page 1; “Memory expansion” is revised.
Page 1; Explanation of “<Flash memory mode>” is revised.
Page 1; Notes 2 is changed.
Page 1; Some words of “APPLICATION” are added.
Page 2; Figure 1 and Figure 2 are partly revised.
Page 3; Figure 3 is added.
Page 7; Figure 5 is partly revised.
Page 8; Figure 6 is partly revised.
Page 8; Some products are added into Table 3.
Page 9; Note into Figure 7 is revised.
Page 10; Note into Figure 8 is revised.
Page 11; Note into Figure 9 is added.
Page 41; Explanation of “I2C Data Shift Register” is partly revised.
Page 42; Explanation of “I2C Clock Control Regsiter” is partly revised.
Page 42; Note 1 into Table 10 is partly revised.
Page 50; (6) and (7) of “Precaution when using multi-master I2C BUS interface” are added.
Page 51; Figure 48 is partly revised.
Page 56; Explanation of “RESET CIRCUIT” is partly revised.
Page 56; Note into Figure 55 is revised.
Page 60; Figure 61 is partly revised.
Page 61; Explanation of “PROCESSOR MODE” is partly revised.
Page 61; Explanation into Figure 62 is eliminated partly.
Page 61; Note into Figure 63 is revised.
Page 66; Figure 66 is partly revised.
(1/2)
REVISION DESCRIPTION LIST
Rev.
Revision Description
No.
2.1
3886 GROUP DATA SHEET
Page 73; Minimum limits of VPPH into Table 22 is revised.
Page 74; Figure 72 is partly revised.
Page 81; Explanation of “Flash memory mode 3 (CPU reprogramming mode)” is added.
Page 81; Note into Figure 79 is eliminated partly.
Page 82; “CPU reprogramming mode operation procedure” is eliminated partly.
Page 82; Figure 81 is partly revised.
Page 86; Explanation of “Handling of Power Source Pins” is added.
Page 86; Explanation of “Erasing of Flash memory version” is added.
Page 87; Parameter into Table 28 is partly revised.
Page 88; Parameter into Table 29 is partly revised.
•Mask ROM confirmation forms are eliminated.
✽ Refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.
mesc.co.jp/indexe/htm). [38000 Series → Mask ROM Confirmation Forms]
•ROM programming confirmation form is eliminated.
✽ Refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.
mesc.co.jp/indexe/htm). [38000 Series → Mask ROM Confirmation Forms]
•Mark specification form is eliminated.
✽ Refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.
mesc.co.jp/indexe/htm). [38000 Series → Mask ROM Confirmation Forms → ROM
Ordering Method → Mark Specification Forms]
Page 107; Package outline for 80P6S-A is added.
(2/2)
Rev.
date
000114
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
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Notes regarding these materials
•
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© 2000 MITSUBISHI ELECTRIC CORP.
H-LF492-A KI-0001 Printed in Japan (ROD) II
New publication, effective Jan. 2000.
Specifications subject to change without notice.