CYRF7936
2.4-GHz CyFi™ Transceiver
Features
■
2.4-GHz direct sequence spread spectrum (DSSS) radio transceiver
■
Operating voltage from 1.8 V to 3.6 V
■
Operating temperature from 0 °C to 70 °C
■
Space saving 40-pin QFN 6 × 6 mm package
■
Operates in the unlicensed worldwide industrial, scientific, and
medical (ISM) band (2.400 GHz to 2.483 GHz)
Applications
■
21-mA operating current (transmit at –5 dBm)
■
Wireless sensor networks
■
Transmit power up to +4 dBm
■
Wireless actuator control
■
Receive sensitivity up to –97 dBm
■
Home automation
■
Sleep current less than 1 µA
■
White goods
■
DSSS data rates up to 250 kbps, Gaussian frequency-shift
keying (GFSK) data rate of 1 Mbps
■
Commercial building automation
■
Automatic meter readers
■
Low external component count
■
Precision agriculture
■
Auto transaction sequencer (ATS) - no MCU intervention
■
Remote controls
■
Framing, length, CRC16, and auto acknowledge (ACK)
■
Consumer electronics
■
Power management unit (PMU) for MCU
■
Personal health and fitness
■
Fast startup and fast channel changes
■
Toys
■
Separate 16 byte transmit and receive FIFOs
■
Dynamic data rate reception
■
Receive signal strength indication (RSSI)
■
Serial peripheral interface (SPI) control while in sleep mode
■
4-MHz SPI microcontroller interface
■
Battery voltage monitoring circuitry
■
Supports coin-cell operated applications
Applications Support
The CYRF7936 CyFi™ transceiver is a radio IC designed for low
power embedded wireless applications. It can be used only with
Cypress’s PSoC programmable system-on-chip. Combined with
the PSoC and a CyFi network protocol stack, CYRF7936 can be
used to implement a complete CyFi wireless system.
See www.cypress.com for development tools, reference
designs, and application notes.
Logic Block Diagram
VREG
L/D
VBAT
VCC
VDD
PMU
CyFi Radio Modem
VIO
IRQ
SS#
SCK
MISO
MOSI
PACTL
Data
Interface
and
Sequencer
GFSK
Modulator
DSSS
Baseband
& Framer
RFN
RFBIAS
GFSK
Demodulator
SPI
RSSI
Xtal Osc
RFP
Synthesizer
RST
XTAL XOUT
Cypress Semiconductor Corporation
Document Number: 001-48013 Rev *E
•
GND
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 21, 2010
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CYRF7936
Contents
Features .................................................................................. 1
Application Examples ........................................................... 9
Applications ........................................................................... 1
Absolute Maximum Ratings ............................................... 13
Applications Support ............................................................ 1
Operating Conditions .......................................................... 13
Logic Block Diagram ............................................................. 1
DC Characteristics .............................................................. 13
Contents ................................................................................. 2
AC Characteristics .............................................................. 14
Pinouts ................................................................................... 3
RF Characteristics ............................................................... 15
Functional Overview ............................................................. 4
Typical Operating Characteristics ..................................... 17
Data Transmission Modes ................................................ 4
Packet Framing ................................................................ 4
Packet Buffers .................................................................. 5
Auto Transaction Sequencer (ATS) ................................. 5
Data Rates ....................................................................... 5
Ordering Information ........................................................... 19
Functional Block Overview ................................................... 6
2.4-GHz CyFi Radio Modem ............................................ 6
Frequency Synthesizer ..................................................... 6
Baseband and Framer ...................................................... 6
Packet Buffers and Radio Configuration Registers .......... 6
SPI Interface ..................................................................... 6
Interrupts .......................................................................... 8
Clocks ............................................................................... 8
Power Management ......................................................... 8
Receiver Front End .......................................................... 8
Document Number: 001-48013 Rev *E
Ordering Code Definition ................................................ 19
Package Description ........................................................... 20
Document Conventions ...................................................... 21
Acronyms ....................................................................... 21
Units of Measure ............................................................ 21
Document History Page ...................................................... 22
Sales, Solutions, and Legal Information ........................... 22
Worldwide Sales and Design Support ............................ 22
Products ......................................................................... 22
PSoC Solutions .............................................................. 22
Page 2 of 22
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CYRF7936
Pinouts
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
NC 32
NC 31
VIO 33
RST 34
NC 36
VDD 35
L/D 37
VBAT0 38
NC 39
VREG 40
Corner
tabs
XTAL 1
30
PACTL / GPIO
NC
2
29
XOUT / GPIO
VCC
3
28
MISO / GPIO
NC
4
NC
5
VBAT1
6
VCC
7
24 SS
VBAT2
8
23 NC
NC
9
CYRF7936
CyFi Transciever
40 lead QFN
27
MOSI / SDAT
26
IRQ / GPIO
25 SCK
22 NC
* E- PAD Bottom Side
RFBIAS 10
21 NC
20 NC
19 RESV
18 NC
17 NC
16 VCC
15 NC
14 NC
13 RFN
12 GND
11 RFP
Table 1. Pin Description - CYRF7936 40-Pin QFN
Pin Number
1
Name
XTAL
Type
Default
I
I
Description
12-MHz crystal
2, 4, 5, 9, 14, 15, NC
17, 18, 20, 21, 22,
23, 31, 32, 36, 39
NC
Connect to GND
3, 7, 16
VCC
Pwr
VCC = 2.4 V to 3.6 V. Typically connected to VREG.
6, 8, 38
VBAT(0-2)
Pwr
VBAT = 1.8 V to 3.6 V. Main supply.
10
RFBIAS
O
O
RF I/O 1.8 V reference voltage
11
RFP
I/O
I
Differential RF signal to and from antenna
12
GND
GND
13
RFN
I/O
19
RESV
I
24
SS#
I
25
SCK
26
IRQ
27
MOSI
28
Ground
I
Differential RF signal to and from antenna
Must be connected to GND
I
SPI enable, active LOW assertion. Enables and frames transfers.
I
I
SPI clock
I/O
O
Interrupt output (configurable active HIGH or LOW), or GPIO
I/O
I
SPI data input pin master out slave in (MOSI) or serial data (SDAT)
MISO
I/O
Z
SPI data output pin - master in slave out (MISO), or GPIO (in SPI 3-pin mode).
Tristates when SPI 3PIN = 0 and SS# is deasserted.
29
XOUT
I/O
O
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tristates in sleep mode (configure as GPIO drive LOW).
30
PACTL
I/O
O
Control signal for external PA, T/R switch, or GPIO
33
VIO
Pwr
34
RST
I
35
VDD
Pwr
Document Number: 001-48013 Rev *E
I/O interface voltage, 1.8 V to 3.6 V
I
Device reset. Internal 10-kΩ pull-down resistor. Active HIGH, typically connect
through a 0.47-μF capacitor to VBAT. Must have RST = 1 event the first time power
is applied to the radio. Otherwise, the radio control register state is unknown.
Decoupling pin for 1.8 V logic regulator, connect through a 0.47-μF capacitor to
GND.
Page 3 of 22
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CYRF7936
Table 1. Pin Description - CYRF7936 40-Pin QFN (continued)
Pin Number
Name
Type
Default
Description
37
LVD
O
40
VREG
Pwr
PMU boosted output voltage feedback
E-pad
GND
GND
Must be soldered to ground
Corner tabs
NC
NC
PMU inductor or diode connection, when used. If not used, connect to GND.
Do not solder the tabs and keep other signal traces clear. All tabs are common to
the lead frame or paddle, which is grounded after the pad is grounded. While they
are visible to the user, they do not extend to the bottom.
Functional Overview
The CYRF7936 IC is designed to implement wireless device
links operating in the worldwide 2.4-GHz ISM frequency band. It
is intended for systems compliant with worldwide regulations
covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1
V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry
Canada), and TELEC ARIB_T66_March, 2003 (Japan).
The CYRF7936 contains a 2.4-GHz CyFi radio modem, which
features a 1-Mbps GFSK radio front-end, packet data buffering,
packet framer, DSSS baseband controller, and RSSI.
CYRF7936 features a SPI interface for data transfer and device
configuration.
The CyFi radio modem supports 98 discrete 1-MHz channels
(regulations may limit the use of some of these channels in
certain jurisdictions).
The baseband performs DSSS spreading and despreading,
start-of-packet (SOP), end-of-packet (EOP) detection, and
CRC16 generation and checking. The baseband may also be
configured to automatically transmit ACK handshake packets
whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
In addition, the CYRF7936 IC has a power management unit
(PMU), which allows direct connection of the device to any
battery voltage in the range 1.8 V to 3.6 V. The PMU conditions
the battery voltage to provide the supply voltages required by the
device, and may supply external devices.
Data Transmission Modes
The CyFi radio transceiver supports two different data
transmission modes:
■
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
■
In 8DR mode, DSSS is enabled and eight bits are encoded in
each derived code symbol transmitted.
Packet Framing
The CYRF7936 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SOP marker. The
SOP_CODE_ADR PN code used for the SOP is different from
that used for the “body” of the packet, and if necessary may be
a different length. SOP must be configured to be the same length
on both sides of the link.
Length
This is the first eight bits after the SOP symbol and is transmitted
at the payload data rate. An EOP condition is inferred after
reception of the number of bytes defined in the length field, plus
two bytes for the CRC16.
CRC16
The device may be configured to append a 16-bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed. The
received data CRC16 is checked against both the configured
and zero CRC16 seeds.
CRC16 detects the following errors:
■
Any one bit in error.
■
Any two bits in error (irrespective of how far apart, which
column, and so on).
■
Any odd number of bits in error (irrespective of the location).
■
An error burst as wide as the checksum itself.
Figure 2 shows an example packet with SOP, CRC16, and
lengths fields enabled and Figure 3 shows a standard ACK
packet.
Both 64 chip and 32 chip pseudo noise (PN) codes are supported
in 8DR mode. In general, lower data rates reduce packet error
rate in any given environment.
Document Number: 001-48013 Rev *E
Page 4 of 22
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CYRF7936
Figure 2. Example Packet Format
P re a m b le
n x 16us
P
2 n d F ra m in g
S y m b o l*
SOP 1
SOP 2
L e n g th
P a y lo a d D a ta
Packet
le n g th
1 B y te
P e rio d
1 s t F ra m in g
S y m b o l*
C R C 16
*N o te :3 2 o r 6 4 u s
Figure 3. Example ACK Packet Format
P r e a m b le
n x 16us
P
2 n d F r a m in g
S y m b o l*
SO P 1
SO P 2
1 s t F r a m in g
S y m b o l*
C RC 16
C R C fie ld fr o m
r e c e iv e d p a c k e t.
2 B y te p e r io d s
Packet Buffers
All data transmission and reception use the 16-byte packet
buffers: one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to
16 bytes of payload data in one burst SPI transaction. This is
then transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
Maximum packet length depends on the accuracy of the clock on
each end of the link. Packet lengths up to 40 bytes are supported
when the delta between the transmitter and receiver crystals is
60 ppm or better. Interrupts are provided to allow an MCU to use
the transmit and receive buffers as FIFOs. When transmitting a
packet longer than 16 bytes, the MCU can load 16 bytes initially,
and add further bytes to the transmit buffer as transmission of
data creates space in the buffer. Similarly, when receiving
packets longer than 16 bytes, the MCU must fetch received data
from the FIFO periodically during packet reception to prevent it
from overflowing.
Auto Transaction Sequencer (ATS)
The CYRF7936 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
■
Starts the crystal and synthesizer
■
Enters transmit mode
■
Transmits the packet in the transmit buffer
■
Transitions to receive mode and waits for an ACK packet
■
Transitions to the transaction end state when an ACK packet
is received or a timeout period expires
Document Number: 001-48013 Rev *E
*N o te :3 2 o r 6 4 u s
Similarly, when receiving in transaction mode, the device
automatically:
■
Waits in receive mode for a valid packet to be received
■
Transitions to transmit mode, transmits an ACK packet
■
Transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF7936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
■
1000 kbps (GFSK)
■
250 kbps (32 chip 8DR)
■
125 kbps (64 chip 8DR)
Page 5 of 22
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CYRF7936
Functional Block Overview
2.4-GHz CyFi Radio Modem
The CyFi radio modem is a dual conversion low IF architecture
optimized for power, range, and robustness. The CyFi radio
modem employs channel-matched filters to achieve high
performance in the presence of interference. An integrated
power amplifier (PA) provides up to +4 dBm transmit power, with
an output power control range of 34 dB in seven steps. The
supply current of the device is reduced as the RF output power
is reduced.
Table 2. Internal PA Output Power Step Table
PA Setting
7
6
5
4
3
2
1
0
Typical Output Power (dBm)
+4
0
–5
–13
–18
–24
–30
–35
Frequency Synthesizer
Prior to transmission or reception, the frequency synthesizer
must settle. The settling time varies depending on the channel;
25 fast channels are provided with a maximum settling time of
100 µs.
The ‘fast channels’ (less than 100 µs settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet.
Configuration registers allow configuration of DSSS PN codes,
data rate, operating mode, interrupt masks, interrupt status, and
so on.
SPI Interface
The CYRF7936 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF7936). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of slave select (SS#), serial clock (SCK), MOSI, MISO,
or SDAT.
Document Number: 001-48013 Rev *E
SPI communication is described as follows:
■
Command direction (bit 7) = ‘1’ enables SPI write transaction.
When it equals a ‘0’, it enables SPI read transactions.
■
Command increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically
increments at the end of each data byte in a burst access.
Otherwise the same address is accessed.
■
Six bits of address
■
Eight bits of data
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW SS# pin must be asserted to initiate an SPI transfer.
The application MCU can initiate SPI data transfers using a
multibyte transaction. The first byte is the Command/Address
byte and the following bytes are the data bytes as shown in
Table 3 through Figure 6 on page 7.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS# = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 4 and Figure 5 on page 7,
respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 6 and Figure 7 on page 7,
respectively.
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using the 3-pin mode, firmware must
ensure that the MOSI pin on the MCU is in a high-impedance
state except when MOSI is actively transmitting data.
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
The IRQ pin function may be optionally multiplexed to the MOSI
pin. When this option is enabled, the IRQ function is not available
while the SS# pin is LOW. When using this configuration,
firmware must ensure that the MOSI pin on the MCU is in a high
impedance state whenever the SS# pin is HIGH.
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VIO). This enables the device to interface
directly to MCUs operating at voltages below the CYRF7936 IC
supply voltage.
Page 6 of 22
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CYRF7936
Table 3. SPI Transaction Format
Parameter
Byte 1
Byte 1+N
Bit #
7
6
[5:0]
[7:0]
Bit Name
DIR
INC
Address
Data
Figure 4. SPI Single Read Sequence
SCK
SS
cmd
MOSI
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu
MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. SPI Incrementing Burst Read Sequence
SCK
SS
cmd
MOSI
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu1+N
data to mcu1
MISO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
Figure 6. SPI Single Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
Figure 7. SPI Incrementing Burst Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu1
A1
A0
D7
D6
D5
D4
D3
D2
data from mcu1+N
D1
D0
D7
D6
D5
D4
D3
D2
MISO
Document Number: 001-48013 Rev *E
Page 7 of 22
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CYRF7936
Interrupts
The device provides an interrupt (IRQ) output, which is
configurable to indicate the occurrence of different events. The
IRQ pin can be programmed to be either active HIGH or active
LOW; it can be a CMOS or open drain output.
The CYRF7936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled or disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is necessary
to read the relevant status register to determine which event
caused the IRQ pin to assert. Even when a given interrupt source
is disabled, the status of the condition that otherwise causes an
interrupt can be determined by reading the appropriate status
register. It is therefore possible to use devices without the IRQ
pin, by polling the status registers to wait for an event, rather than
using the IRQ pin.
Clocks
A 12-MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external
capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.
The requirements to directly connect the crystal to the XTAL pin
and GND are:
■
Nominal frequency: 12 MHz
■
Operating mode: Fundamental mode
■
Resonance mode: Parallel resonant
■
Frequency stability: ±30 ppm
■
Series resistance: <60 Ω
■
Load capacitance: 10 pF
■
Drive level: 100 µW
Power Management
The operating voltage of the device is 1.8 V to 3.6 V DC, which
is applied to the VBAT pin. The device can be shut down to a fully
static sleep mode by writing to the FRC END = 1 and
END STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing the packet transmission or
reception. When in sleep mode, the on-chip oscillator is stopped,
but the SPI interface remains functional. The device wakes from
sleep mode automatically when the device is commanded to
enter transmit or receive mode. When resuming from sleep
mode, there is a short delay while the oscillator restarts. The
device can be configured to assert the IRQ pin when the
oscillator has stabilized.
Document Number: 001-48013 Rev *E
The output voltage (VREG) of the PMU is configurable to several
minimum values between 2.4 V and 2.7 V. VREG may be used to
provide up to 15 mA (average load) to external devices. It is
possible to disable the PMU and provide an externally regulated
DC supply voltage to the device’s main supply in the range 2.4 V
to 3.6 V. The PMU also provides a regulated 1.8 V supply to the
logic.
The PMU is designed to provide high boost efficiency (74%–85%
depending on input voltage, output voltage, and load) when
using a Schottky diode and power inductor. This eliminates the
need for an external boost converter in many systems where
other components require a boosted voltage. However,
reasonable efficiencies (69%–82% depending on input voltage,
output voltage, and load) can be achieved when using low cost
components such as SOT23 diodes and 0805 inductors.
The current through the diode must stay within the linear
operating range of the diode. For some loads the SOT23 diode
is sufficient, but with higher loads it is not; a SS12 diode must be
used to stay within this linear range of operation. Along with the
diode, the inductor used must not saturate its core. In higher
loads, a lower resistance/higher saturation coil such as the
inductor from Sumida must be used.
The PMU also provides a configurable low battery detection
function, which can be read over the SPI interface. One of seven
thresholds between 1.8 V and 2.7 V can be selected. The
interrupt pin can be configured to assert when the voltage on the
VBAT pin falls below the configured threshold. LV IRQ is not a
latched event. Battery monitoring is disabled when the device is
in sleep mode.
Receiver Front End
The gain of the receiver can be controlled directly by writing to
the low-noise amplifier (LNA) bit and the attenation (ATT) bit of
the RX_CFG_ADR register. Clearing the LNA bit reduces the
receiver gain approximately 20 dB, allowing accurate reception
of very strong received signals (for example, when operating a
receiver very close to the transmitter). Approximately 30 dB of
receiver attenuation can be added by setting the ATT bit. This
limits data reception to devices at very short ranges. Enabling
LNA is recommended, unless receiving from a device using
external PA.
When the device is in receive mode, the RSSI_ADR register
returns the relative signal strength of the on-channel signal
power.
When receiving, the device automatically measures and stores
the relative strength of the signal being received as a five bit
value. An RSSI reading is taken automatically when the SOP is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI_ADR register. This
allows the background RF energy level on any given channel to
be easily measured when RSSI is read while no signal is being
received. A new reading can occur as fast as once every 12 µs.
Page 8 of 22
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CYRF7936
Application Examples
CYRF7936
Figure 8. Recommended Circuit for Systems where VBAT ≤ 2.4 V
Document Number: 001-48013 Rev *E
Page 9 of 22
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CYRF7936
Table 4. Recommended BoM for Systems where VBAT ≤ 2.4 V
Item Qty
1
1
CY Part Number
NA
Reference
ANT1
Description
Manufacturer
2.5 GHz H-STUB Wiggle Antenna for 32 NA
MIL PCB
Mfr Part Number
NA
2
1
730-10012
C1
CAP 15 PF 50V CERAMIC NPO 0402 Panasonic
ECJ-0EC1H150J
3
1
730-11955
C3
CAP 2.0 PF 50V CERAMIC NPO 0402 Kemet
C0402C209C5GACTU
4
1
730-11398
C4
CAP 1.5PF 50V CERAMIC NPO 0402
SMD
PANASONIC
ECJ-0EC1H1R5C
5
1
730R-13322
C5
CAP CER.47 uF 6.3V X5R 0402
Murata
GRM155R60J474KE1
9D
6
2
730-13037
C12,C7
CAP CERAMIC 10 uF 6.3V X5R 0805
Kemet
C0805C106K9PACTU
7
1
730-13400
C8
CAP 1 uF 6.3V CERAMIC X5R 0402
Panasonic
ECJ-0EB0J105M
8
6
730-13404
C9,C10,C11, CAP 0.047 uF 50V CERAMIC X5R 0402 AVX
C13,C15,C16
0402YD473KAT2A
9
1
730R-11952
C17
CAP.10UF 10V CERAMIC X5R 0402
Kemet
C0402C104K8PACTU
10
1
800-13317
D1
Diode Schottky 0.5A 40V SOT23
DIODES INC
BAT400D-7-F
11
1
420-11976
J1
CONN HEADER 12 PIN 2MM GOLD
Hirose Electric
Co. Ltd.
DF11-12DP-2DSA(01)
12
1
800-13401
L1
INDUCTOR 22NH 2% FIXED 0603
SMD
Panasonic - ECG ELJ-RE22NGF2
13
1
800-11651
L2
INDUCTOR 1.8NH +-.3NH FIXED 0402 Panasonic - ECG ELJ-RF1N8DF
SMD
14
1
800-10594
L3
COIL 10UH 1100MA CHOKE 0805
Newark
30K5421
15
1
630-11356
R1
RES 1.00 OHM 1/8W 1% 0805 SMD
Yageo
9C08052A1R00FKHFT
16
1
610-13402
R2
RES 47 OHM 1/16W 5% 0402 SMD
Panasonic - ECG ERJ-2GEJ470X
17
1
CYRF7936-40LFXC U1
IC, LP 2.4 GHz Radio SoC QFN-40
Cypress
Semiconductor
CYRF7936-40LFXC
18
1
800-13259
Crystal 12.00 MHZ HC49 SMD
eCERA
GF-1200008
19
1
PDCR-9515 REV01 PCB
Printed Circuit Board
Cypress
Semiconductor
PDCR-9515 REV01
20
1
920-11206
LABEL1
Serial Number
21
1
920-51500 REV01
LABEL2
PCA #
Y1
Document Number: 001-48013 Rev *E
121R-51500 REV01
Page 10 of 22
[+] Feedback
VBUS
DM
DP
GND
S1
S2
1
2
3
4
5
6
USB A RA PLUG
J1
R4
zero
VBUS
DM
DP
0805
5V
4.7 uFd
C13
R1
R2
24
24
0603
5V
5V
R9
R8
3
1
EN
VIN
U3
100
100
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
DM
DP
CY8C24794-24LFXI
25
18
25
17
22
16
28
15
21
20
U2
S1
2
1
D1
4
5
TPS79133
PYBASS
VOUT
KR
KG
2A
2B
0402
0.01 uFd
C15
4
3
SW1
LED Green Red
RD
GR
SW PUSHBUTTON
1A
1B
620
620
0805
VCC
2.2 uFd
C14
nLED2
nLED1
RED
= USB ACTIVITY
GREEN = RF ACTIVITY
Power Supply
5V
R10
R11
LP_nSS R6
LP_IRQ
1K
R5
SCK
MISO
1K
CLKOUT
R7
MOSI
1K
0402
0402
GND
0402
0402
0402
2
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
40
2
42
1
43
56
45
54
46
53
47
52
40
51
TP1
NO LOAD
R3
nLED2
nLED1
SW1
P0_1
RST
TP3
TP4
0402
VCC
0402
VCC
0402
2
4
5
9
14
15
17
18
37
26
24
25
27
28
34
C6
0.047 uFd
LP_IRQ
LP_nSS
SCK
MOSI
MISO
RST
C17
0.47 uFd
U1
CYRF7936
0402
C7
0.047 uFd
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
L/D
IRQ
SS
SCK
MOSI
MISO
RST
0402
C8
0.047 uFd
RFn
RFp
19
20
21
22
23
31
32
36
39
29
1
30
13
11
10
0402
C10
0.047 uFd
RESV
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
XOUT
XTAL
PACTL
0402
C9
0.047 uFd
C5
0402
0.47 uFd
RFbias
8
6
38
VBAT2
VBAT1
VBAT0
0402
1500 pFd
33
VIO
VCC
TP2
C11
0.047 uFd
CLKOUT TV1
PACTL
L2
L1
1.8 nH
IND0402
22 nH
IND0603
0402
12 MHz Crystal
Y1
2.0 pFd
C3
C1
15 pFd
0402
1.5 pFd
C4
ANT1
WIGGLE 32
1
2
C12
0402
VCC
22
49
VDD
VSS
VSS
19
50
40
VREG
GND1
3
7
16
VCC1
VCC2
VCC3
12
35
VDD
E-PAD
0402
0402
0603
Document Number: 001-48013 Rev *E
41
0402
5V
CYRF7936
Figure 9. Recommended Circuit for Systems where VBAT is 2.4 V to 3.6 V (PMU Disabled)
Page 11 of 22
[+] Feedback
0402
CYRF7936
Table 5. Recommended BoM for Systems where VBAT is 2.4V - 3.6V (PMU disabled)
Item Qty
CY Part Number
Reference
ANT1
Description
Manufacturer
Mfr Part Number
1
1
NA
2.5 GHz H-STUB Wiggle Antenna for 32MIL NA
PCB
NA
2
1
730-10012
3
1
730-11955
C1
CAP 15 PF 50V CERAMIC NPO 0402
Panasonic
ECJ-0EC1H150J
C3
CAP 2.0 PF 50V CERAMIC NPO 0402
Kemet
4
1
730-11398
C4
CAP 1.5 PF 50V CERAMIC NPO 0402 SMD PANASONIC
ECJ-0EC1H1R5C
CAP 0.47 uF 6.3V CERAMIC X5R 0402
C0402C209C5GACTU
5
1
730-13322
C5
Murata
GRM155R60J474KE19D
6
6
730-13404
C6,C7,C8,C CAP 0.047 uF 16V CERAMIC X5R 0402
9,C10, C11
AVX
0402YD473KAT2A
7
1
730-11953
C12
CAP 1500PF 50V CERAMIC X7R 0402
Kemet
C0402C152K5RACTU
8
1
730-13040
C13
CAP CERAMIC 4.7UF 6.3V XR5 0805
Kemet
C0805C475K9PACTU
9
1
730-12003
C14
CAP CER 2.2 uF 10V 10% X7R 0805
Murata
GRM21BR71A225KA01L
Electronics North
America
10
1
800-13333
D1
LED GREEN/RED BICOLOR 1210 SMD
LITEON
LTST-C155KGJRKT
11
1
420-13046
J1
CONN USB PLUG TYPE A PCB SMT
ACON
UAR72-4N5J10
12
1
800-13401
L1
INDUCTOR 22NH 2% FIXED 0603 SMD
Panasonic - ECG ELJ-RE22NGF2
13
1
800-11651
L2
INDUCTOR 1.8NH +-.3NH FIXED 0402
SMD
Panasonic - ECG ELJ-RF1N8DF
14
2
610-10037
R1, R2
RES 24 OHM 1/16W 5% 0603 SMD
Panasonic - ECG ERJ-3GEYJ240V
15
1
610-10343
R4
RES ZERO OHM 1/16W 0402 SMD
16
3
610-10016
R5, R6, R7 RES CHIP 1K OHM 1/16W 5% 0402 SMD
17
2
610-13472
R9,R8
RES CHIP 620 OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ621X
18
2
610-10684
R10, R11
RES CHIP 100 OHM 1/16W 5% 0402 SMD Phycomp USA Inc 9C1A04021000FLHF3
Panasonic - ECG ERJ-2GE0R00X
Panasonic - ECG ERJ-2GEJ102X
19
1
200-13471
S1
SWITCH LT 3.5MMX2.9MM 160GF SMD
Panasonic - ECG EVQ-P7J01K
20
1
CYRF7936-40LFC
U1
IC, 2.4 GHz CyFi Transceiver QFN-40
Cypress
Semiconductor
CYRF7936 Rev A5
21
1
CY8C24794-24LFXI U2
PSoC Mixed Signal Array
Cypress
Semiconductor
CY8C24794-24LFXI
22
1
800-13259
Y1
Crystal 12.00 MHZ HC49 SMD
eCERA
GF-1200008
23
1
LABEL1
Serial Number
XXXXXX
Document Number: 001-48013 Rev *E
Page 12 of 22
[+] Feedback
CYRF7936
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with power applied . –55 °C to +125 °C
Supply voltage on any power supply pin
relative to VSS ...............................................–0.3 V to +3.9 V
DC voltage to logic inputs[8] ................... –0.3 V to VIO +0.3 V
DC voltage applied to outputs
in high-Z state........................................ –0.3 V to VIO +0.3 V
Static discharge voltage (digital)[9] ............................ >2000 V
Static discharge voltage (RF)[9] ................................. 1100 V
Latch-up current ......................................+200 mA, –200 mA
Operating Conditions
VCC ...................................................................2.4 V to 3.6 V
VIO ....................................................................1.8 V to 3.6 V
VBAT ..................................................................1.8 V to 3.6 V
TA (ambient temperature under bias) ............. 0 °C to +70 °C
Ground voltage ................................................................. 0 V
FOSC (crystal frequency)....................... 12 MHz ±30 ppm b
DC Characteristics
(T = 25°C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000 MHz)
Min
Typ
Max
VBAT
Parameter
Battery voltage
0 °C to 70 °C
1.8
–
3.6
V
VREG[10]
PMU output voltage
2.4 V mode
2.4
2.43
–
V
VREG[10]
PMU output voltage
2.7 V mode
2.7
2.73
–
V
VIO
[11]
Description
Conditions
VIO voltage
Unit
1.8
–
3.6
V
2.4[12]
–
3.6
V
At IOH = –100.0 µA
VIO – 0.2
VIO
–
V
Output high voltage condition 2
At IOH = –2.0 mA
VIO – 0.4
VIO
–
V
At IOL = 2.0 mA
–
0
0.45
V
0.7VIO
–
VIO
V
VCC
VCC voltage
0 °C to 70 °C
VOH1
Output high voltage condition 1
VOH2
VOL
Output low voltage
VIH
Input high voltage
VIL
Input low voltage
0
–
0.3VIO
V
IIL
Input leakage current
0 < VIN < VIO
–1
0.26
+1
µA
Pin input capacitance
Except XTAL, RFN, RFP, RFBIAS
–
3.5
10
pF
CIN
(GFSK)[13]
Average TX ICC, 1 Mbps, slow channel
PA = 5, 2 way, 4 bytes/10 ms
–
0.87
–
mA
ICC (32-8DR)[13]
Average TX ICC, 250 kbps, fast channel
PA = 5, 2 way, 4 bytes/10 ms
–
1.2
–
mA
ISB[14]
Sleep mode ICC
–
0.8
10
µA
[14]
ICC
Sleep mode ICC
PMU enabled
–
31.4
–
µA
IDLE ICC
Radio off, XTAL Active
XOUT disabled
–
1.0
–
mA
ISB
Isynth
ICC during Synth Start
–
8.4
–
mA
TX ICC
ICC during Transmit
PA = 5 (–5 dBm)
–
20.8
–
mA
TX ICC
ICC during Transmit
PA = 6 (0 dBm)
–
26.2
–
mA
TX ICC
ICC during Transmit
PA = 7 (+4 dBm)
–
34.1
–
mA
RX ICC
ICC during Receive
LNA off, ATT on
–
18.4
–
mA
RX ICC
ICC during Receive
LNA on, ATT off
–
21.2
–
mA
Boost Eff
PMU boost converter efficiency
VBAT = 2.5 V, VREG = 2.73 V,
ILOAD = 20 mA
–
81
–
%
ILOAD_EXT[15]
Average PMU external load current
VBAT = 1.8 V, VREG = 2.73 V,
0–50 °C, RX mode
–
–
15
mA
ILOAD_EXT[15]
Average PMU external load current
VBAT = 1.8V, VREG = 2.73V, 50 °C–70 °C,
RX mode
–
–
10
mA
Notes
8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.
9. Human body model (HBM).
10. VREG depends on battery input voltage.
11. In sleep mode, the I/O interface voltage reference is VBAT.
12. In sleep mode, VCC min. can be as low as 1.8 V.
13. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK
handshake. Device is in sleep except during this transaction.
14. ISB is not guaranteed if any I/O pin is connected to voltages higher than VIO.
15. ILOAD_EXT is dependant on external components and this entry applies when the components connected to L/D are SS12 series diode and DH53100LC inductor from
Sumida.
Document Number: 001-48013 Rev *E
Page 13 of 22
[+] Feedback
CYRF7936
AC Characteristics
Table 6. SPI Interface[16, 17]
Parameter
Description
Min
Typ
Max
Unit
238.1
–
–
ns
SPI clock high time
100
–
–
ns
tSCK_LO
SPI clock low time
100
–
–
ns
tDAT_SU
SPI input data setup time
25
–
–
ns
tDAT_HLD
SPI input data hold time
10
–
–
ns
tDAT_VAL
SPI output data valid time
0
tDAT_VAL_TRI
SPI output data tristate (MOSI from slave select deassert)
tSS_SU
SPI slave select setup time before first positive edge of SCK[18]
tSS_HLD
SPI slave select hold time after last negative edge of SCK
10
–
–
ns
tSS_PW
SPI slave select minimum pulse width
20
–
–
ns
tSCK_SU
SPI slave select setup time
10
–
–
ns
tSCK_HLD
SPI SCK hold time
10
–
–
ns
tRESET
Minimum RST pin pulse width
10
–
–
ns
tSCK_CYC
SPI clock period
tSCK_HI
10
–
50
ns
–
20
ns
–
–
ns
Figure 10. SPI Timing
tSCK_CYC
tSCK_HI
SCK
tSCK_LO
tSCK_HLD
tSCK_SU
nSS
tSS_SU
tDAT_SU
tSS_HLD
tDAT_HLD
MOSI input
tDAT_VAL
tDAT_VAL_TRI
MISO
MOSI output
Notes
16. AC values are not guaranteed if voltage on any pin exceeding VIO.
17. CLOAD = 30 pF
18. SCK must start low at the time SS# goes LOW, otherwise the success of SPI transactions are not guaranteed.
Document Number: 001-48013 Rev *E
Page 14 of 22
[+] Feedback
CYRF7936
RF Characteristics
Table 7. Radio Parameters
Parameter Description
Conditions
RF frequency range
Refer Note 19
Receiver (T = 25 °C, VCC = 3.0 V, fOSC = 12.000000 MHz, BER < 1E-3)
Sensitivity 125 kbps 64-8DR
BER 1E-3
Sensitivity 250 kbps 32-8DR
BER 1E-3
Sensitivity
CER 1E-3
Sensitivity GFSK
BER 1E-3, ALL SLOW = 1
Min
Typ
Max
Unit
2.400
–
2.497
GHz
–97
–
dBm
–93
–
dBm
–87
–
dBm
–84
–
dBm
–80
LNA gain
–
22.8
–
dB
ATT gain
–
–31.7
–
dB
–15
–6
–
dBm
21
–
Count
1.9
–
dB/Count
9
–
dB
Maximum received signal
LNA On
RSSI value for PWRin –60 dBm
LNA On
RSSI slope
Interference Performance (CER 1E-3)
Co-channel Interference rejection
carrier-to-Interference (C/I)
C = –60 dBm
–
Adjacent (±1 MHz) channel selectivity C/I 1 MHz
C = –60 dBm
–
3
–
dB
Adjacent (±2 MHz) channel selectivity C/I 2 MHz
C = –60 dBm
–
–30
–
dB
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz
C = –67 dBm
–
–38
–
dB
Out-of-band blocking 30 MHz–12.75 MHz[20]
C = –67 dBm
–
–30
–
dBm
Intermodulation
C = –64 dBm, Δf = 5,10 MHz
–
–36
–
dBm
Receive Spurious Emission
800 MHz
100 kHz ResBW
–
–79
–
dBm
1.6 GHz
100 kHz ResBW
–
–71
–
dBm
3.2 GHz
100 kHz ResBW
–
–65
–
dBm
Maximum RF transmit power
PA = 7
+2
4
+6
dBm
Maximum RF transmit power
PA = 6
–2
0
+2
dBm
Maximum RF transmit power
PA = 5
–7
–5
–3
dBm
Maximum RF transmit power
PA = 0
–
–35
–
dBm
–
39
–
dB
RF power range control step size
Seven steps, monotonic
–
5.6
–
dB
Frequency deviation min
PN code pattern 10101010
–
270
–
kHz
Frequency deviation max
PN code pattern 11110000
–
323
–
kHz
Transmitter (T = 25°C, VCC = 3.0V)
RF power control range
Error vector magnitude (FSK error)
>0 dBm
Occupied bandwidth
–6 dBc, 100 kHz ResBW
–
10
–
%rms
500
876
–
kHz
In-band spurious second channel power (±2 MHz)
–
–38
–
dBm
In-band spurious third channel power (>3 MHz)
–
–44
–
dBm
Transmit Spurious Emission (PA = 7)
Notes
19. Subject to regulation.
20. Exceptions F/3 and 5C/3.
Document Number: 001-48013 Rev *E
Page 15 of 22
[+] Feedback
CYRF7936
Table 7. Radio Parameters (continued)
Parameter Description
Conditions
Min
Typ
Max
Unit
Nonharmonically related spurs (800 MHz)
–
–38
–
dBm
Nonharmonically related spurs (1.6 GHz)
–
–34
–
dBm
Nonharmonically related spurs (3.2 GHz)
–
–47
–
dBm
Harmonic spurs (second harmonic)
–
–43
–
dBm
Harmonic spurs (third harmonic)
–
–48
–
dBm
Fourth and greater harmonics
–
–59
–
dBm
–
0.7
1.3
ms
Power Management (Crystal PN# eCERA GF-1200008)
Crystal start to 10 ppm
Crystal start to IRQ
XSIRQ EN = 1
–
0.6
–
ms
Synth settle
Slow channels
–
–
270
µs
Synth settle
Medium channels
–
–
180
µs
Synth settle
Fast channels
–
–
100
µs
Link turnaround time
GFSK
–
–
30
µs
Link turnaround time
250 kbps
–
–
62
µs
Link turnaround time
125 kbps
–
–
94
µs
Link turnaround time
<125 kbps
–
–
31
µs
Maximum packet length
<60 ppm crystal-to-crystal
–
–
40
bytes
Document Number: 001-48013 Rev *E
Page 16 of 22
[+] Feedback
CYRF7936
Typical Operating Characteristics
The typical operating characteristics of CYRF7936 follow[21]
Transmit Power vs. Temperature
(Vcc = 2.7v)
Transmit Power vs. Channel
Transmit Power vs. Vcc
(PMU off)
6
6
-2
-4
PA5
-6
-8
-10
PA4
-12
2
20
PA6
0
-2
-4
PA5
-6
-8
-10
PA4
-12
-14
0
40
Output Power (dBm)
PA6
0
-14
2.4
60
2.6
2.8
3
3.2
3.4
PA4
0
20
40
LNA OFF
ATT ON
LNA OFF
80
Average RSSI vs. Vcc
(Rx signal = -70dBm)
20
19
18
RSSI Count
LNA ON
60
Channel
17
RSSI Count
RSSI Count
-8
-10
3.6
19
24
16
15
17
16
15
14
13
14
12
13
0
-120
11
10
2.4
12
-100
-80
-60
-40
0
-20
20
40
60
RSSI vs. Channel
(Rx signal = -70dBm)
12
10
8
6
4
2
0
40
60
-82
-84
-86
CER
-88
-90
8DR32
-92
-94
2.4
80
3.4
3.6
-82
-84
-86
CER
-88
-90
8DR32
-92
-94
2.6
2.8
Channel
3
3.2
3.4
3.6
0
20
Vcc
40
60
Temp (deg C)
Receiver Sensitivity vs Channel
(3.0v, Room Temp)
Receiver Sensitivity vs. Frequency Offset
-80
3.2
-80
Receiver Sensitivity (dBm)
Receiver Sensitivity (dBm)
14
3
Rx Sensitivity vs. Temperature
(1Mbps CER)
-80
16
20
2.8
Vcc
Rx Sensitivity vs. Vcc
(1Mbps CER)
18
0
2.6
Temp (deg C)
Input Power (dBm)
Carrier to Interferer
(Narrow band, LP modulation)
-81
Receiver Sensitivity (dBm)
-82
-84
GFSK
-86
-88
-90
-92
-94
8DR64
10.0
0.0
-85
CER
-87
-89
-50
0
50
100
150
Crystal Offset (ppm)
-20.0
-30.0
-50.0
8DR32
-60.0
-10
-95
-100
-10.0
-40.0
-91
-93
-96
20.0
GFSK
-83
C/I (dB)
RSSI Count
PA5
-6
-12
18
Receiver Sensitivity (dBm)
-4
Average RSSI vs. Temperature
(Rx signal = -70dBm)
32
-98
-150
PA6
0
-2
Vcc
Typical RSSI Count vs Input Power
8
2
-14
Temp (deg C)
16
PA7
4
PA7
4
Output Power (dBm)
2
Output Power (dBm)
6
PA7
4
0
10
20
30
40
50
60
70
80
-5
0
5
10
Channel Offset (MHz)
Channel
Note
21. With LNA on, ATT off, above –2dBm erroneous RSSI values may be read. Cross-checking RSSI with LNA off/on is recommended for accurate readings.
Document Number: 001-48013 Rev *E
Page 17 of 22
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CYRF7936
Typical Operating Characteristics (continued)
GFSK vs. BER
(SOP Threshold = 5, C38 slow)
BER vs. Data Threshold (32-8DR)
(SOP Threshold = 5, C38 slow)
10
100
0 Thru 7
10
1
1
0.1
%BER
0.01
0.01
0.001
0.001
0.0001
0.0001
0.00001
-100
-95
-90
-85
-80
-75
GFSK
0.00001
-100
-70
Input Power (dBm)
-80
-60
-40
-20
0
Input Power (dBm)
ICC RX
(LNA ON)
ICC RX
(LNA OFF)
ICC RX SYNTH
25
21
19.5
19
18.5
18
17.5
3.3V
3.0V
2.7V
2.4V
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
17
0
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70
5
10 15 20 25 30 35 40 45 50 55 60 65 70
5
16
15.5
15
14.5
OPERATING CURRENT (mA)
17.5
3.3V
3.0V
2.7V
2.4V
16.5
10 15 20 25 30 35 40 45 50 55 60 65 70
16.5
16
15.5
15
14.5
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70
ICC TX @ PA4
20.5
16
15.5
OPERATING CURRENT (mA)
19
16.5
3.3V
3.0V
2.7V
2.4V
18.5
18
17.5
17
16.5
16
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Document Number: 001-48013 Rev *E
3.3V
3.0V
2.7V
2.4V
20
19.5
19
18.5
18
17.5
17
15.5
15
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA3
18
17
5
TEMPERATURE (C)
ICC TX @ PA2
3.3V
3.0V
2.7V
2.4V
3.3V
3.0V
2.7V
2.4V
17
14
0
TEMPERATURE (C)
17.5
10 15 20 25 30 35 40 45 50 55 60 65 70
ICC TX @ PA1
14
0
5
TEMPERATURE (C)
17
3.3V
3.0V
2.7V
2.4V
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
0
ICC TX @ PA0
ICC TX SYNTH
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
3.3V
3.0V
2.7V
2.4V
TEMPERATURE (C)
TEMPERATURE (C)
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
3.3V
3.0V
2.7V
2.4V
20
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
24.5
20.5
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
OPERATING CURRENT (mA)
%BER
0.1
16.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Page 18 of 22
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CYRF7936
Typical Operating Characteristics (continued)
ICC TX @ PA5
23
29.5
22.5
22
OPERATING CURRENT (mA)
3.3V
3.0V
2.7V
2.4V
21.5
21
20.5
20
3.3V
3.0V
2.7V
2.4V
29
28.5
28
OPERATING CURRENT (mA)
23.5
OPERATING CURRENT (mA)
ICC TX @ PA7
ICC TX @ PA6
30
27.5
27
26.5
26
25.5
25
19.5
24.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
0
40.5
40
39.5
39
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
32.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
3.3V
3.0V
2.7V
2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
DC Test Load
OUTPUT
OUTPUT
5 pF
30 pF
INCLUDING
JIG AND
SCOPE
VCC
R1
OUTPUT
INCLUDING
JIG AND
Typical
SCOPE
Max
R2
ALL INPUT PULSES
Parameter
R1
R2
RTH
VTH
VCC
VCC
Unit
Ω
Ω
Ω
V
V
1071
937
500
1.4
3.00
90%
10%
GND
Rise time: 1 V/ns
90%
10%
Fall time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
VTH
OUTPUT
Equivalent to:
Ordering Information
Part Number
CYRF7936-40LTXC
Radio
Package Name
Transceiver
40-QFN
Package Type
40-QFN (Sawn type)
Operating Range
Commercial
Ordering Code Definition
CY RF 7936 40-LTX C
Temperature range: = Commercial
40-pin QFN package
X = Pb-free
Part Number
Marketing Code
Company ID: CY = Cypress
Document Number: 001-48013 Rev *E
Page 19 of 22
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CYRF7936
Package Description
The recommended dimension of the PCB pad size for the E-pad underneath the QFN is 3.5 mm × 3.5 mm (width × length).
Figure 12. 40-Pin Sawn QFN (6 × 6 × 0.90 mm)
001-44328 *D
Document Number: 001-48013 Rev *E
Page 20 of 22
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CYRF7936
Document Conventions
Acronyms
Units of Measure
Table 8. Acronyms Used in this Document
Table 9 lists the unit sof measures.
Acronym
Description
Table 9. Units of Measure
Symbol
Unit of Measure
ACK
Acknowledge (packet received, no errors)
ATS
Auto transaction sequencer
°C
degree Celsius
BER
Bit error rate
dB
decibels
BOM
Bill of materials
dBc
decibel relative to carrier
CMOS
Complementary metal oxide semiconductor
dBm
decibel-milliwatt
Hz
hertz
KB
1024 bytes
Kbit
1024 bits
kHz
kilohertz
kΩ
kilohm
CRC
Cyclic redundancy check
DSSS
Direct sequence spread spectrum
EOP
End-of-packet
FEC
Forward error correction
GFSK
Gaussian frequency-shift keying
MHz
megahertz
HBM
Human body model
MΩ
megaohm
ISM
Industrial, scientific, and medical
μA
microampere
IRQ
Interrupt request
μs
microsecond
LNA
Low-noise amplifier
μV
microvolts
MCU
Microcontroller unit
μVrms
microvolts root-mean-square
MISO
Master in slave out
μW
microwatts
MOSI
Master out slave in
mA
milliampere
PA
Power amplifier
ms
millisecond
PLL
Phase locked loop
mV
millivolts
PMU
Power management unit
nA
nanoampere
ns
nanosecond
nV
nanovolts
Ω
ohm
pp
peak-to-peak
ppm
parts per million
PN
Pseudo noise
QFN
Quad flat no-leads
RSSI
Received signal strength indication
RF
Radio frequency
Rx
Receive
ps
picosecond
SCK
Serial clock
sps
samples per second
SDAT
Serial data
V
volts
SOP
Start-of-packet
SPI
Serial peripheral interface
Tx
Transmit
Document Number: 001-48013 Rev *E
Page 21 of 22
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CYRF7936
Document History Page
Description Title: CYRF7936 2.4-GHz CyFi™ Transceiver
Document Number: 001-48013
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2557501
KKU/AESA
08/25/2008
New Data Sheet
*A
2615458
KKU/AESA
01/13/2009
Updated block diagram, changed SoP to SOP, changed EoP to EOP,
changed Frequency Initial Stability to Frequency Stability, change
section on Low Noise Amplifier.... to Receiver Front End and removed
AGC enable. Updated Register Map Summary.
*B
2672793
DPT/PYRS
03/12/2009
Updated packaging and ordering information.
*C
2902376
TGE
03/31/2010
Removed inactive parts from Ordering Information.
Updated Package Diagram.
*D
2927979
TGE/AESA
05/05/2010
Removed Register Descriptions section.
Added Contents
Updated links in Sales, Solutions, and Legal Information.
*E
3028381
TGE
09/13/2010
Updated Applications Support section
Added Acronyms and Units of Measure tables
Added Ordering Code Definition section
Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
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Interface
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cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
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cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
cypress.com/go/memory
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
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PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/image
cypress.com/go/psoc
© Cypress Semiconductor Corporation, 2008-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-48013 Rev *E
Revised September 21, 2010
Page 22 of 22
CyFi, WirelessUSB, PSoC, and enCoRe are trademarks of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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