Agilent Technologies | N5980A | Agilent J-BERT N4903B High-Performance Serial BERT

Agilent J-BERT N4903B
High-Performance Serial BERT
7 Gb/s and 12.5 Gb/s
Data Sheet Version 1.1 (Extended SSC and 14.2 Gb/s)
Complete jitter tolerance test
for embedded and
forwarded clock devices
•
•
•
•
Integrated
Calibrated
Automated
Compliant
Agilent Technologies N4900 Series
Agilent offers a wide range of serial bit error ratio test (BERT)
solutions for R&D and manufacturing. The J-BERT N4903B highperformance serial BERT is the flagship of Agilent’s N4900 serial
BERT series. It addresses the needs of R&D and validation teams
who characterize serial I/O ports or ASICs up to 14.2 Gb/s.
Integrated and calibrated jitter sources for jitter tolerance measurements also allow designers to characterize and prove compliance
of their receiver’s jitter tolerance.
Agilent’s N4900 serial BERT series offers key
benefits:
The B version of the J-BERT has been improved to address the test
needs during characterization and compliance test of emerging
forwarded clock and embedded clock devices in the most complete
and integrated way.
• Remote control via LAN, USB and GPIB interfaces, compatible
with existing command set Agilent 71612, 81630A Series, N4900
Series
• Excellent precision and sensitivity for accurate measurements
• Choice of feature set and frequency classes to tailor to test needs
and budget
• State-of-the-art user interfaces with color touch screen
• Small form factor saves rack or bench space
Table 1. Serial BERT applications and selection guide
Device under test
Typical requirements
Recommended Agilent BERT
For R&D and
characterization
For manufacturing
Optical transceivers, i.e.:
SONET, SDH, 10 GbE, XFP/XFI, SFP+, 16x FC
•
•
•
•
PRBS
Signal precision
Eye masks
Data rates > 10 Gb/s
N4903B
N4906B-012
or N2101B-300
High-speed serial computer buses, and backplanes, i.e.
QPI, HT, FB-DIMM, PCI Express, USB 3, SATA, SAS,
DisplayPort, CEI, Fibre Channel 4 G/8 G
•
•
•
•
Test pattern sequences
CDR
Differential inputs
Data rates < 7 Gb/s
N4903B1
N4906B-012
N4906B-101
N4906B-102
0.6 – 2.5 Gb/s transceiver, i.e. E-PON/ G-PON OLTs,
Gigabit Ethernet, Fibre Channel 1x/2x
• Fast bit synchronization
• Data rates < 3.5 Gb/s
N4906B Option 0031
N5980A
or N2101B-100
1. Or ParBERT 81250 for multi-lane testing
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J-BERT N4903B
The J-BERT N4903B high-performance serial BERT is the ideal
choice for characterization. It offers calibrated jitter tolerance
tests fully integrated in a high-performance BERT.
N4906B
The N4906B serial BERT offers an economic BERT solution for
manufacturing and telecom device testing.
N5980A
The N5980A manufacturing serial BERT up to 3.125 Gb/s data
rate enables transceiver test at up to one-sixth of the test cost
and the front panel size of comparable BERT solutions.
N2101B
The N2101B PXIT manufacturing BERT is a PXI module that has
been designed for testing optical transceivers up to 10.3125 Gb/s.
R&D
characterization
compliance test
J-BERT
7, 12.5, 14.2 Gb/s
N4903B
Manufacturing
volume ramp
test
Mfg BERT
3 Gb/s
N5980A
3 Gb/s
PXIT BERT
10.3125 GB/s
N2101B
7 Gb/s
Serial BERT
3 & 12.5 Gb/s
N4906B
10 Gb/s
12.5 Gb/s
Maximum data rate
Figure 1. J-BERT is the highest-performance BERT amongst Agilent‘s
offering of serial BERT solutions for R&D and manufacturing
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J-BERT N4903B High-Performance Serial BERT
Accurate characterization is achieved with clean signals from the
pattern generator, which features exceptionally low jitter and extremely
fast transition times. Built-in and calibrated jitter sources allow accurate jitter tolerance testing of receivers.
The J-BERT N4903B high-performance serial BERT provides the
most complete jitter tolerance test for embedded and forwarded
clock devices.
It is the ideal choice for R&D and validation teams characterizing
and stressing chips and transceiver modules that have serial I/O
ports up to 7 Gb/s, 12.5 Gb/s or even 14.2 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:
Test set-up is simplified significantly, because the J-BERT N4903B is
designed to match serial bus standards optimally. It offers: differential
I/Os, variable voltage levels on all signal outputs, built-in jitter and ISI,
pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic
patterns.
• PCI Express
• SATA/SAS
• DisplayPort
• USB SuperSpeed
• Fibre Channel
• QPI
• HyperTransport
Press the Jitter button to set all
jitter parameters you need
• Memory buses, such as fully buffered DIMM2
• Backplanes, such as CEI
• 10 GbE/ XAUI
• XFP/XFI, SFP+
Touch screen control of
all J-BERT parameters
Remote operation via LAN, GPIB, USB2
or GUI control via built-in web server
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J-BERT N4903B The Most Complete Jitter Tolerance Test Solution
Faster test execution is possible with J-BERT’s automated jitter
tolerance tests and fast total jitter measurements.
Key NEW Capabilities of J-BERT N4903B
• Supports testing of forwarded clock devices: halfrate clock with variable duty cycle, jitter on clock
and data, delay of jitter between clock and data
The J-BERT N4903B is a long-term investment which is configurable for today’s test and budget requirements but also allows
upgrades from the N4903A model, and later retrofit of all options
and full speed when test needs change.
• PCIe 2.0 compliant jitter injection: LF-RJ and HF-RJ,
dual-tone PJ, residual SSC, electrical idle
• Variable output levels on trigger and aux data
outputs
• 16x FC testing with extended data rate for the
pattern generator up to 14.2 Gb/s
• Arbitrary SSC profile and extended SSC range
to characterize SATA/SAS and USB3 receivers
under real-world condition
• Improved output signal performance
Press Auto Align to automatically adjust
the analyzer’s sampling point delay and
threshold to the center of the eye
• Wider
Wid PJ range up to 300 MHz
tunable CDR always included
• Built-in
Bui
sequencer with up to 60 blocks
• Pattern
Pat
path from N4903A
• Upgrade
Upg
Control output voltage of data, aux data,
clock, trigger/ref clock individually
Plug-in the interference channel to use the builtin switchable ISI traces and to inject near-end or
far-end sinusoidal interference
Recover the clock from incoming data with
the built-in CDR with tunable loop bandwidth
Figure 2. J-BERT N4903B The most complete jitter tolerance test
solution for testing embedded and forwarded clock devices
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Jitter Tolerance Tests
Calibrated and integrated jitter injection
• Periodic jitter, single and dual-tone (Option J10)
• Sinusoidal jitter (Option J10)
• Random jitter and spectrally distributed RJ (Option J10)
• Bounded uncorrelated jitter (Option J10)
• Intersymbol interference (ISI) (Option J20)
• Sinusoidal interference (Option J20)
• Spread spectrum clocking (SSC) and residual SSC (Option J11)
External jitter injection
Using an external source connected to delay control input.
Figure 3. Manual jitter composition. This allows a combination of jitter types
to be injected. Example shows a typical jitter setup for a PCIe 2.0 add-in
card test
User controls
Manual jitter composition
Option J10: PJ 1/2, SJ, RJ, sRJ, and BUJ
Option J20: ISI and sinusoidal interference
Option J11: SSC and residual SSC
This screen allows the user to set up combinations of jitter types
and jitter magnitudes easily. Therefore a calibrated ‘stressed
eye’ with more than 50% eye closure can be set up for receiver
testing. Additional jitter can be injected with the interference
channel. It adds ISI and differential/single mode sinusoidal
interference.
Automated jitter tolerance characterization (Option J10)
This test automatically sweeps over SJ frequency based on the
selected start/stop frequency, steps, accuracy, BER level, confidence level and DUT relax time. The green dots indicate where
the receiver tolerated the injected jitter. The red dots show where
the BER level was exceeded. By selecting a tested point, the jitter
setup condition is restored for further analysis. The compliance
curve can be shown on the result screen for immediate result
interpretation. This automated characterization capability saves
significant programming time.
Figure 4. Automated jitter tolerance characterization. The green circles
show where DUT works within the required BER-level
Automated jitter tolerance compliance (Option J12)
This test automatically verifies compliance against a receiver’s jitter
tolerance curve limits specified by a standard or by the user. Most of
the popular serial bus standards define jitter tolerance curves. This
option includes a library of jitter tolerance curves for: SATA, Fibre
Channel, FB-DIMM, 10 GbE/XAUI, CEI 6/11 G, and XFP/XFI. Pass/
fail is shown on a graphical result screen, which can be saved and
printed. A comprehensive compliance report, including the jitter
setup and total jitter results for each test point, can be generated and
saved as a html file for simple jitter tolerance test documentation.
Figure 5. Result screen of the automated jitter tolerance
compliance. A library of jitter tolerance curves is available
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User Interface and Measurement Suite
Quick eye diagram and masking
Eye contour
The quick eye diagram allows a one-shot check for a valid signal.
Due to the higher sampling depth of a BERT, the eye contour
lines visualize the measured eye at a deeper BER level for more
accurate results. Extrapolated eye contour lines display the eye
opening for even lower BER levels, such as 10-15, reducing the
measurement time significantly. The display shows numerical
results for 1- and 0- level, eye amplitude and width, total jitter
and more. Eye masks can be loaded from a library. Violations of
the captured eye mask are displayed. The result screen can be
printed and saved for documenting the test results (see Figure 6).
The eye opening is a key characteristic of a device. The BER is
displayed as a function of sampling delay and sampling threshold.
Different views are available: eye contour (see Figure 8), pseudo
colors and equal BER plots.
Figure 8. Eye contour with colors indicating BER level
BERT scan including RJ/DJ separation
This measurement shows the BER versus the sampling point
delay, which is displayed as a “bathtub” curve or as a histogram.
The measurement results are displayed in a table with setup and
hold time over phase margin, total jitter in rms or peak-to-peak,
and random and deterministic jitter. The measurement method is
equivalent to IEEE 802.3ae (see Figure 9).
Figure 6. Quick eye diagram with BER contour and masking
Spectral jitter decomposition
The spectral jitter decomposition measures the spectral decomposition of jitter components. When debugging designs, the jitter
decomposition simplifies identifying deterministic jitter sources
(see Figure 7).
Figure 9. BERT scan including RJ/DJ separation, total jitter
Figure 7. Spectral jitter decomposition for debugging jitter sources in a
design.
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User Interface
Bit recovery mode (Option A01)
This mode is useful for analyzing non-deterministic traffic. This is
helpful when you need to analyze real world traffic, for example in
a PCI Express link, where so-called ‘skip ordered sets’ are added
unpredictably to avoid FIFO overflow. This simplifies setup by
eliminating the need to setup expected data for the error detector.
Two analyzer sampling points are used to measure a relative BER,
which makes the following measurements possible with relative
BER:
• BERT scan including RJ/DJ separation
• Output levels and Q factor
Figure 10. Bit recovery mode for analyzing non-deterministic traffic
• Eye contour
• Fast eye mask
• Fast total jitter
• Spectral jitter decomposition
Automatic alignment
The J-BERT is able to align the voltage threshold and the delay
offset of the sampling point automatically, either simultaneously
or separately. It is possible to search for the 0/1 threshold
automatically on command, and to track the 0/1 threshold
continuously (see Figure 11).
Fast total jitter
Agilent implemented a new measurement technique for TJ (BER),
the fast total jitter measurement. This method provides fast and
feasible total jitter measurements, around 40 times faster than
a common BERT scan but with comparable confidence level.
Instead of comparing bits until the BER reaches a defined number
of bits or a defined number of errors, it only compares bits until it
can decide with a 95% confidence level whether the actual BER
is above or below the desired BER (see Figure 12).
Figure 11. Auto alignment (center) simplifies correct sampling
Web-based access to GUI
J-BERT can be operated conveniently from any remote web
location with the built-in web server. So even without programming knowledge, J-BERT can be operated and monitored from a
distance or off-site and in noisy or environmental test labs.
Figure 12. Fast total jitter measurement for quick and accurate total jitter
measurements
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Specifications-Pattern Generator
Pattern generator key characteristics:
• Available as 7 and 12.5 Gb/s pattern generator without
error detector (Options G07 and G13), extension to
14.2Gb/s (Option D14)
• Differential outputs with variable output levels for data,
aux data, clock and trigger
• Lowest intrinsic jitter – 800 fs rms
Figure 13. Generator connectors on front panel
• Transitions times < 20 ps
• Half-rate clock with variable duty cycle (Option 003)
• Pattern sequencer with up to 60 blocks and counted loops
• Calibrated and integrated jitter injection with SJ, two-tone
PJ, RJ/sRJ, BUJ, ISI, S.I. (Option J10, J20)
• SSC and residual SSC (Option J11)
• Automated jitter tolerance characterization sweep makes
use of SJ and PJ using 610 ps or 220 ps delay line
• High precision delay control input to inject jitter from an
external source
• Electrical idle state on data outputs
Figure 14. Pattern generator setup screen with graphical display of signal
levels and data-to-clock delay
Figure 15. Clean output signal; 10 Gb/s, 400 mV amplitude
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Specifications-Pattern Generator
Data output and auxiliary data output (DATA OUT, AUX DATA OUT)
Table 2. Output characteristics for J-BERT N4903B generator. All timing parameters are measured at ECL levels.
Range of operation 5
150 Mb/s to 14.2 Gb/s (Option D14, required in addition to C13 or G13)
150 Mb/s to 12.5 Gb/s (Option C13 or G13); can be programmed up to 13.5 Gb/s
150 Mb/s to 7 Gb/s (Option C07 or G07);
< 620 MHz only with external clock
Frequency accuracy
± 15 ppm typical
Format
NRZ, normal or inverted
Electrical idle
Output transitions from full swing signal to 0 V amplitude and vice versa at constant offset within 4 ns typ. Electrical
idle is controlled by the error add input connector
Amplitude/resolution
0.050 V to 1.800 V, 5 mV steps; addresses LVDS, CML, PECL, ECL (terminated to 1.3 V/0 V/-2 V), low voltage CMOS
Output voltage window
- 2.0 V to +3.0 V
Predefined levels
ECL (-2V), SCFL (0V), LVPECL (1.3V), LVDS (1.25V), and CML (0V)
Transition times
20% to 80%
10% to 90% 1
< 20 ps
< 25 ps
Intrinsic jitter 4
9 ps pp typical with internal clock
Clock/data delay range
± 0.75 ns in 100 fs steps
Auto-calibration possible to compensate for temperature drifts
External termination voltage 2
- 2 V to +3 V
Crossing point
Adjustable 20% to 80% typical to emulate duty cycle distortions
AUX data modes:
1. sub-rate clock mode: can be used to generate lower rate reference clocks with divider factor
n = 2, 3, 4, 5, ... 128 relative to data rate. This is the same function as the sub-rate clock output of N4903A.
2. tbd
Single error inject
Adds single errors on demand
Fixed error inject
Fixed error ratios of 1 error in 10n bits, n = 3, 4, 5, 6, 7, 8, 9
Interface
3
Connector
Differential or single-ended, DC coupled, 50 Ω
2.4 mm female
1. At 10 Gb/s and 7 Gb/s
2. For positive termination voltage or termination to GND, external termination voltage must be less than 3 V below VOH. For negative termination voltage, external termination
voltage must be less than 2 V below VOH. External termination voltage must be less than 3 V above VOL.
3. Unused outputs must be terminated with 50 Ω to GND.
4. At target BER 10 -9, with PRBS 2 31, 10 Gb/s
5. When Option D14 is enabled, and data rates are > 12.5 Gb/s: PJ1 + PJ2 range 0 to 2.0 UI, modulation frequency range 1 kHz to 100 MHz. RJ range 0 to 20 mUI rms
(0 to 280 mUI pp). For BUJ, SSC, SJ functionality is not guaranteed and might require manual calibration.
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Pattern Generator Specifications
Clock output (CLK OUT)
1/z
E xtern al clock
Clock can operate at full bit-rate or at half bit-rate (Option 003) to
support testing of forward clocked devices.
E xtern al clock
(P LL m ode)
Table 3. Clock output specifications
10 M H z ref clock
x/y
PLL
VCO
Clock
source
selection
Internal clock
Frequency range
150 MHz to 14.2 GHz (Option D14,
in addition to C13 or G13);
150 MHz to 12.5 GHz (Option C13 or G13);
can be programmed up to 13.5 GHz
150 MHz to 7 GHz (Option C07 or G07);
< 620 MHz only with external clock
Half-rate clocking
Only with Option 003: Available at bit rates
> 2.7 Gb/s; duty cycle on half-rate clock
adjustable 40% to 60%
Amplitude/resolution
0.050 V pp to 1.800 V pp, 5 mV steps
Output voltage window
-2.00 to +3.00 V
Transition times
20% to 80%
10% to 90% 1
< 20 ps
< 25 ps
z = 1,2,4,8,16,
resulting bit rate
must be > 150 Mb/s
C lock generator
Figure 16. N4903B supports multiple clock modes
10 MHz reference input (10 MHz REF IN)
This is used to lock the generator to an external 10 MHz reference
clock. The data rate can be selected within the same range as if
the internal clock would be used. The provided reference clock
must not be modulated. All internal jitter sources are available.
Table 4. Specifications for clock input and 10 MHz reference input
External termination
voltage
-2 V to +3 V
Jitter
800 fs rms typical with internal clock
SSB phase noise
< -75 dBc with internal clock source, 10 GHz
at 10 kHz offset, 1 Hz bandwidth
Interface 3
Differential or single-ended, DC coupled,
50 Ω output impedance
Connector
2.4 mm female
Amplitude
200 mV to 2 V
Interface
AC coupled, 50 Ω nominal
Connectors
Clock input
10 MHz reference input
SMA female, front panel
BNC, rear panel
Delay control input (DELAY CTRL IN)
1. At 10 Gb/s and 7 Gb/s
2. For positive termination voltage or termination to GND, external termination
voltage must be less than 3 V below VOH. For negative termination voltage,
external termination voltage must be less than 2 V below VOH. External
termination volt age must be less than 3 V above VOL.
3. Unused outputs must be terminated with 50 Ω to GND.
The external signal applied to delay control input varies the delay
between data output and clock output. This can be used to generate jittered signals to stress the device under test in addition to
the calibrated jitter injection from N4903B.
Clock input (CLK IN)
Table 5. Specifications for delay control input
There are two modes when using the clock input connector.
1. External clock mode: all output signals follow the external
clock and its modulation. The modulation of the external clock
must be within the same range given for SSC and SJ (see
Table 12). If the external clock is above 6.75 GHz, all internal
jitter sources can be used (for using 610 ps delay line, external
clock divider z = 4). Below 6.75 GHz, SJ and SSC are not available. However, the external clock can optionally be divided by
1, 2, 4, 8, or 16, provided that the resulting bit rate does not fall
below 150 Mb/s. Modulation using the 220 ps delay line is still
available (see Figure 22).
2. External PLL mode: it is used to lock the generator to an
external clock. The provided clock must not be modulated in
external PLL mode. All internal jitter sources are available. A
clock multiplication with x/y is possible, with x, y = 1,2,3, to
255. The resulting bit rate has to be within the range 150 Mb/s
to maximum bit rate.
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Range
-110 ps to +110 ps
Sensitivity
Typical
Linearity
±5% typical
Modulation bandwidth
1 GHz typical at 10.8 Gb/s
data rate
Levels
-275 mV to +275 mV
Interface
DC coupled, 50 Ω nominal
Connector
SMA female
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Specifications-Pattern Generator
Error add input (ERROR ADD)
Table 8. Specifications for trigger/reference clock output
The external error add input adds a single error to the data output
for each rising edge at the input. When electrical idle is selected
for the data and aux data outputs: a logical high state causes
the output to transition to electrical idle state. A logic low state
causes the outputs to return to normal operation.
Pulse width
Amplitude/ resolution
Output voltage window
Predefined levels
Transition times
Table 6. Specifications for error inject input
Levels
TTL compatible
Interface
DC coupled, 50 Ω nominal
Connector
SMA female
Interface1
Connector
Square wave
0.050 V to 1.800 V, 5 mV steps.
Addresses LVDS, CML, PECL, ECL
(terminated to 1.3V/0 V/-2 V), low
voltage CMOS
- 2.0 V to +3.0 V
ECL, PECL (3.3V), LVDS, CML
< 20 ps typical (20% to 80%)
< 25 ps typical (10% to 90%)
DC coupled, 50 Ω nominal,
Single ended or differential
2.4 mm female
1. Unused output must be terminated with 50 Ω to GND.
10 MHz reference output (10 MHZ REF OUT)
AUX input (AUX IN)
Table 7. Specifications for the 10 MHz reference output
Amplitude
1 V into 50 Ω typical
Interface
AC coupled,
50 Ω output impedance
Connector
BNC, rear panel
When the alternate pattern mode is activated, the memory is split
into two parts, and the user can define a pattern for each part.
Depending on the operating mode of the auxiliary input, the user
can switch the active pattern in real time by applying a pulse
(mode 1) or a logical state (mode 2) to the auxiliary input. If the
alternate pattern mode is not activated, the user can suppress the
data on the data output by applying a logical high to the auxiliary
input (mode 3).
Table 9. Specifications for auxilliary input
Trigger/reference clock outputs
(TRIGGER/ REF CLK OUT)
Levels
Interface
Connector
This output provides a trigger signal synchronous with the
pattern, for use with an oscilloscope or other test equipment.
Typically there is a delay of 32 ns between trigger and data output
for data rates > 620 Mb/s. The trigger output has two modes.
TTL compatible
DC coupled, 50 Ω nominal
SMA female
Auxillary clock output (AUX CLK OUT)
Pattern trigger mode: For PRBS patterns; the pulse is synchronized with a user specified trigger pattern. One pulse is generated
for every 4th PRBS pattern.
This output is intended as clock input for N4916B de-emphasis
signal converter.
Divided clock mode: Generates a square wave (clock) with the
frequency of the full-rate clock divided by 2, 4, 8, 10, 16, 20, 24,
25, 26, up to 32,792 . It is possible to enable/disable SJ, SSC or
residual SSC for this output to use it as a lower frequency
reference clock.
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Pattern Generator Specifications
Library of pre-defined patterns
Alternate pattern
Many popular compliance patterns are predefined, such as:
CJTPAT, CJPAT, DisplayPort, FDDI, Fibre Channel, K28.5, PCI
Express, SAS, SATA, SDH, SONET, USB3
This allows switching between two patterns of equal length that
have been programmed by the user, each of which can be up
to 16 Mbit. Switching is possible using a front panel key, over
GPIB or by applying the appropriate signal to the auxiliary input
port. Changeover occurs at the end of the pattern. The length
of the alternating patterns should be a multiple of 512 bits. Two
methods of controlling pattern changeover are available: one-shot
and alternate.
Patterns
PRBS: 2n-1 with n = 7, 10, 11, 15, 23, 31, and 2n with
n = 7, 10, 13, 15, 23, 31.
Zero substitution
User definable pattern: 32 Mbit, independent for pattern generator and error detector.
Zeros can be substituted for data to extend the longest run
of zeros in the patterns listed below. The longest run can be
extended to the pattern length-1. The bit following the substituted
zeros is set to 1.
Generator pattern sequencing
The generators pattern sequences can be started on command or
by a signal applied to the auxiliary input.
Variable mark density
Number of blocks and counted loops: up to 60; the block resolution of user definable pattern is 512 bits.
The ratio of ones to total bits in the predefined pattern library can
be set to ⅛, ¼, ½, ¾, or ⅞.
Loops: over 60 or fewer blocks, 1 loop level, loop counter and
infinite.
Figure 17. Pattern generator sequencer helps to set up complex training
sequences.
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Jitter Tolerance Test Specifications
The built-in jitter sources are designed to cover DisplayPort,
PCI Express, SATA, USB3, Fibre Channel, QPI, Hypertransport,
FB-DIMM, CEI 6 G/11 G, 10 GbE and XFP/XFI, SFP+ jitter tolerance test needs.
Jitter
amplitude
(UI)
Sine wave
Sine wave
triangular
square wave
For all data rates
Data rate x 220 ps
Periodic jitter (Option J10)
1.0*
For data rates ≥ 8.1 Gb/s
This injects sinusoidal, rectangular
or triangular jitter over a wide
frequency range.
0.001
* 220 ps max.
Table 10. Specifications for periodic jitter (PJ)
20
100
300
Modulation
frequency (MHz)
Figure 19. Periodic jitter maximum using the 220 ps delay line
Range1
0 to 220 ps pp at all data rates
0 to 610 ps pp at data rates
≤ 3.375 Gb/s
Modulation frequency
Sine
One- and two-tone possible
1 kHz to 300 MHz
Triangle/square
SSC – spread spectrum clocking (Option J11)
The built-in SSC clock modulation source is available only in
combination with Option J10. It either generates a frequency
modulated clock signal (SSC) or a phase modulated clock signal
(residual SSC) as used in some computer or storage standards
such as PCIe, USB and SATA to spread EMI. If residual SSC
is enabled, sinusoidal jitter is not available, however all other
jitter sources can be used. If SSC is enabled, sinusoidal jitter is
available in a limited range, however all other jitter sources can
be used without restrictions. SSC (% of max) + SJ (% of max) ≤
100%.
1 kHz to 20 MHz
Modulation frequency
accuracy
0.5% ± 25 MHz typical
Jitter amplitude accuracy
10% ± 1 ps typical
Impacted signals
610 ps delay line: only on data and aux
data outputs
220 ps delay line: user selectable for
data and aux data outputs, clock output
Jitter delay
0 to ±2.2 ns, 100 ps steps between
jitter on data and aux data output
versus jitter on clock output for all jitter
sources using the 220 ps delay line.
Table 11. Spread spectrum clocking (SSC) characteristics
SSC frequency deviation:
up-spread/down-spread
SSC frequency deviation:
center-spread
1. Available range depends on modulation frequency and data rate
(see Figures 18 and 19).
Jitter
amplitude
(UI)
Data
rate x
610 ps
Residual SSC phase modulation
Modulation frequency
Modulation waveform
Sine wave
Sine wave,
trinagular,
square wave
1.1*
0.5*
0.001
20
80
* 610 ps max.
250 300
Signals impacted
Modulation
frequency
(MHz)
0 to -0.5% (5,000 ppm),
2% typical accuracy
0 to 1.0% pp (10,000 ppm),
2 % typical accuracy. Can be
used also for down-spread
SSC, allowing more SJ range
0 to 100 ps
100 Hz to 100 kHz
Triangular or arbitrary.
Arbitrary files can be uploaded
as txt file. Values from -1.0 to
+1.0 for 1.0% center-spread
modulation, maximum of
16384 data points
Can be enabled for either data
and aux data output and/or
clock output and trigger/ref
clock out
Figure 18. Periodic jitter maximum for data rates ≤ 3.375 Gb/s using the
610 ps delay line
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Jitter Tolerance Test Specifications
Random jitter (Option J10)
Sinusoidal jitter (Option J10)
This injects random jitter with a high bandwidth and excellent crest factor.
This injects sinusoidal jitter in the lower
frequency range with multiple UIs.
It also allows injecting a spectrally distributed random jitter profile, as required for
PCIe 2.0 receiver test.
Table 12. Specifications for sinusoidal jitter (SJ)
Table 13. Specifications for random jitter (RJ)
Range1
2 UI at 5 MHz
1000 UI at 10 kHz
For frequencies between 10 kHz and
5 MHz the jitter amplitude
=
Range
• 0 to 15.7 ps rms (0 to 220 ps pp) at
data rates < 8.1 Gb/s
• 0 to 72 mUI (0 to 1UI pp) at data
rates ≥ 8.1 Gb/s
• 0 to 8 ps rms ( 0 to 112 ps pp) if
100 MHz low-pass filter is turned on
sRJ
If spectrally distributed random jitter
(sRJ) is used, the same limits apply to
the square root sum of LF-RJ and HFRJ components. See Figure 21.
10 MHz
UI
n x f (mod)
Modulation frequency
100 Hz to 5 MHz (For higher modulation
frequencies, see Table 10)
Modulation frequency
accuracy
0.5% typical
Jitter amplitude accuracy
2% ± 1 ps typical
Crest factor
14 (pp to rms ratio)
Impacted signals
User selectable for data and aux data
outputs, clock output and trigger/ref
clock output.
Bandwidth
50 kHz to 1 GHz
Filter
• 10 MHz high-pass
• 100 MHz low-pass
• 500 MHz low-pass
Can be turned on or off individually to
limit jitter bandwidth
Jitter amplitude accuracy
10% ± 0.2 ps typical
1. Available range depends on modulation frequency and data rate
(see Figure 20).
1000 UI
n
Jitter
amplitude
(UI)
100 Hz
2UI
n
10 kHz
5 MHz
R J jitter
amplitude
(ps rms/¥Hz)
Modulation
frequency
n
Max UI at
modulation
frequency
100 Hz to 10 kHz
Max UI at
modulation
frequency
5 MHz
6.75 Gb/s to 12.5 Gb/s
n=1
1000 UI
2 UI
3.375 Gb/s to 6.75 Gb/s
n=2
500 UI
1 UI
1.6875 Gb/s to 3.375 Gb/s
n=4
250 UI
0.5 UI
Data rate
R J-LF
R J-H F
10 kH z
1.5 M H z
100 MHz 1 GHz Modulation
frequency
Figure 21. Spectrally distributed RJ allows to inject low frequency and
high frequency RJ: this is required for compliant PCIe 2 receiver testing
843,75 Mb/s to 1.6875 Gb/s
n=8
125 UI
0.25 UI
620 Mb/s to 843.75 Mb/s
n = 16
62.5 UI
0.125 UI
Figure 20. Sinusoidal jitter maximum UI
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Jitter Tolerance Test Specifications
Bounded uncorrelated jitter (Option J10)
Table 15. BUJ accuracy applies for these BUJ calibration settings
BUJ
calibration
setting1
This injects a high probability jitter using a
PRBS generator and low-pass filters.
CEI 6G
Table 14. Specifications for bounded uncorrelated jitter (BUJ)
Data rate for
PRBS generator
PRBS
Filter
1.1 Gb/s
PRBS 29 - 1
100 MHz
11
CEI 11G
2 Gb/s
PRBS 2 -1
200 MHz
Gaussian
2 Gb/s
PRBS 231-1
100 MHz
1. Other settings are not calibrated and do not necessarily generate the desired
jitter histograms for all datarates of the PRBS generator.
Range
0 to 1.1 UI (not to exceed capabilitiy of
delay line used)
PRBS polynomials
2n-1; n = 7, 8, 9, 10, 11, 15, 23, 31
Data rate of PRBS generator
200 Mb/s to 3.2 Gb/s
Filters
50/100/200 MHz lowpass 3rd order
Jitter amplitude accuracy
10% ± 1 ps typical for settings shown
in Table 15.
2. When using the clock modulator in external clock mode, the external clock
must be > 6.75 GHz. When using the 610 ps delay line in external clock mode,
the external clock must be > 6.75 GHz and z = 4.
Total jitter
A combination of internally generated SJ/SSC/rSSC, PJ, RJ, BUJ
and external jitter (injected using external delay control input) is
possible.
The overall jitter composition does reduce the available jitter
budget of the respective jitter sources.
6.75 Gb/s ... 12.5 Gb/s
External
clock
C lock
sour ce
selection
Trigger/
ref clock
1/n
1/z
150 Mb/s ... 12.5 Gb/s
PLL
x/y
C lock
modulator 2
620 Mb/s ... 12.5 Gb/s
Inter nal clock
oscillator
1/1 or 1/2
D elay modulation
220 ps
rSSC
C lock
Aux clock
SSC
D elay modulation
610 ps 2
+
SJ
D elay modulation
220 ps
Aux data
PJ1
PJ 2
+
Clock & data
220 ps data & aux data on
BU J
M odulation signal
sR J
+
RJ
220 ps for w ar ded clock on
F unctional coupling
Jitter delay
+
External
delay
External
Figure 22. Overview of jitter injection capabilities
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ISI
S.I.
Jitter Tolerance Test Specifications
S21
Interference channel (Option J20)
The Option J20 is only available in addition to Option J10. It
includes the semi-rigid cable set to connect data outputs to P1
and P1 (N4915A-008).
Figure 24. Typical S21 parameter for ISI channel of 9 inch length
Figure 23. Interference channel connectors
Interference channel input and output (P1, P2)
Sinusoidal interference (Option J20)
User selectable board traces are switched into
the signal path to emulate a backplane.
This adds common mode, differential or
single-ended sinewave signal on top of the
data outputs, to test common mode rejection
of a receiver and to emulate vertical eye
closure. Sinusoidal interference is injected
before the signal passes through the ISI
board traces (“near end”) when using P1 as input. For “far end”
injection P2 has to be used as input.
Table 16. Specifications for inter symbol interference (ISI)
Trace length
3.5” (minimum), 9” (minimum with S.I.
enabled) 16”, 20”, 24”, 28”, 32”, 36”, 40”,
44” inches of board trace type Nelco 4000-6.
When using in combination with sinusoidal
interference, minimum trace length is 9 inches
Amplitude1
0 to 400 mV common mode, single
ended and differential (differential
amplitude 0 to 800 mV)
-5.5 V to +5.5 V
Frequency
10 MHz to 3.2 GHz in 100 kHz steps
2.4 mm, female
Level accuracy
± 10% ±10 mV typical
S21 parameter
See Figure 25
Range
See Table 17
Max input levels
Connectors
Table 18. Specifications for sinusoidal interference (SI)
1. The output signal amplitude is reduced by 3 dB when sinusoidal interference
is enabled.
Table 17. Typical ISI (measured in UI) for traces depending on data rate, pattern and trace length.
Data rate
1.25 Gb/s
ISI trace
PRBS
215-1
CJPAT
PRBS
27-1
PRBS
215-1
CJPAT
PRBS
27-1
PRBS
215-1
CJPAT
PRBS
27-1
PRBS
215-1
CJPAT
PRBS
27-1
PRBS
215-1
CJPAT
PRBS
27-1
PRBS
215-1
CJPAT
length
PRBS
27-1
2.5 Gb/s
3.125 Gb/s
5 Gb/s
6.25 Gb/s
11 Gb/s
3.5 inches
0.007
0.017
0.016
0.016
0.022
0.014
0.020
0.031
0.029
0.037
0.062
0.038
0.054
0.085
0.056
0.099
0.146
0.131
9 inches
0.026
0.034
0.037
0.039
0.066
0.039
0.057
0.080
0.079
0.104
0.157
0.092
0.147
0.216
0.138
0.329
0.504
0.405
16 inches
0.045
0.068
0.051
0.103
0.138
0.106
0.137
0.191
0.117
0.279
0.365
0.260
0.346
0.543
0.376
20 inches
0.058
0.088
0.062
0.152
0.184
0.123
0.181
0.276
0.167
0.366
0.529
0.349
0.580
24 inches
0.081
0.109
0.103
0.182
0.260
0.171
0.254
0.356
0.274
0.529
28 inches
0.098
0.141
0.147
0.241
0.334
0.238
0.319
0.483
0.373
32 inches
0.128
0.153
0.120
0.289
0.395
0.295
0.389
0.570
0.376
36 inches
0.156
0.188
0.168
0.375
0.493
0.390
0.507
40 inches
0.172
0.228
0.199
0.458
0.626
0.423
0.617
44 inches
0.199
0.262
0.247
0.571
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Error Detector Specifications
Error detector key characteristics:
• True differential inputs to match today’s ports
• Built-in CDR with tunable loop-bandwidth up to 12 MHz
• Auto-alignment of sampling point
• Bit recovery mode for unknown data traffic (Option AO1)
Figure 25. Front panel connectors for error detection
• Burst mode for testing recirculating loop
• BER result and measurement suite
Clock inputs (CLK IN)
• Quick eye diagram and mask with BER contours
The error detector requires an external clock signal to sample
data or it can recover the clock from the data signal using the
built-in clock data recovery (CDR).
Data inputs (DATA IN)
Table 20. Specification for the clock input
Table 19. Specifications for error detector
Frequency range
150 MHz to 12.5 GHz (Option
C13); 150 MHz to 7 GHz
(Option C07)
NRZ
Amplitude
100 mV to 1.2 V
Max. input amplitude
2.0 V
Sampling
Termination voltage 1
-2 V to +3 V or off
true differential mode
Positive or negative
clock edge
Sensitivity 2
< 50 mV pp
Interface
AC coupled, 50 Ω nominal
Intrinsic transition time 3
25 ps typical 20% to 80%, single ended
Connector
SMA female
Decision threshold range
-2 V to +3 V in 1 mV steps
Maximum levels
-2.2 V to +3.2 V
Range of operation
150 Mb/s to 12.5 Gb/s (Option C13)
150 Mb/s to 7 Gb/s (Option C07)
Format
Phase margin
4
Clock data recovery
1 UI – 12 ps typical
Clock-to-data
sampling delay
±0.75 ns in 100 fs steps
Interface
Single-ended: 50 Ω nominal,
differential: 100 Ω nominal
Connector
2.4 mm female
The error detector can recover the clock from the incoming data
stream with the built-in clock data recovery (CDR). The tunable
loop bandwidth comes with N4903A Options C07 and C13. The
recovered clock signal is available at the aux output.
Table 21. Specifications for the clock data recovery (Options C07, C13)
1. Clock/data sampling delay range selectable 2 V operating voltage window,
which is in the range between
-2.0 V to +3.0 V. The data signals, termination voltage and decision threshold
have to be within this voltage window.
2. At 10 Gb/s, BER 10-12, PRBS 231-1. For input levels < 100 mV manual threshold
value adjustments may be required.
3. At cable input, at ECL levels.
Input data rate
1 Gb/s to 12.5 Gb/s1 (Option C13)
1 Gb/s to 7 Gb/s (Option C07)
CDR clock output jitter
0.01 UI rms (RJ) typical 2
Interface
AC coupled, 50 Ω nominal
Connector
SMA female
4. Based on the internal clock.
1. With bit recovery mode (Option A01) enabled the max data rate is 11.5 Gb/s.
2. When measured with PRBS 223-1
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Error Detector Specifications
Table 22. Specifications for tunable loop bandwidth
Tunable loop bandwidth
Loop
bandwidth
(MHz)
12.0
500 kHz to 12 MHz for data rates
1.46 Gb/s to 12.5 Gb/s
100 kHz to 4 MHz for data rates
1 Gb/s to 1.46 Gb/s
Tunable loop bandwidth
7.5
Loop bandwidth accuracy 10% typical (at transition density 50%)
Transition density
compensation
25% to 100%. The CDR can
automatically detect the transition
density of the incoming data
pattern and compensates the loop
bandwidth accordingly.
Tracking range (SSC)
+0.05% to -0.55% (5500 ppm)
deviation of data rate. User can
disable/enable SSC tracking. Loop
bandwidth > 1 MHz and medium or
max peaking enabled
Jitter peaking
Three customer selectable values
between 0 and 3 dB; see frequency
response in Figure 28
Fine adjust
Manual adjustment -1.0 to + 1.0
of CDR settings to minimize CDR
output jitter
Compliant CDR settings
PCIe , SATA, FC, FB-DIMM, CEI,
GE,10 GbE, XAUI, XFP/XFI, SONET
OC-48/192 (see Table 23). User can
add own CDR settings
4.0
0.5
0.1
1.0 1.46
Data rate
(Gb/s)
Figure 26. CDR loop bandwidth
TM
Figure 27. Three selectable frequency response settings. The example
shows JTF loop bandwidth of 900 kHz and 0 dB, 1.2 dB, 2.8 dB peaking
Table 23. Compliance settings for CDR
Standard
11.5 12.5
Revision
Data rate (Gb/s)
JTF loop bandwidth (MHz)
Jitter peaking (dB)
SSC possible
1.0
1.1
2.0
3.0
2.5
2.5
5.0
8.0
1.5
5
8
10
0
1
0.9
TBD
Yes
I
II
III
1.5
3.0
6.0
0.9, 3.0
1.8, 6.0
TBD
1.3
1.7, 1.8
TBD
Yes
FB-DIMM
1
2
3.2, 4.0, 4.8
4.8, 6.4, 8.0, 9.6
111
0.9
Yes
Fibre Channel
1
2
4
8
10
1.063
2.125
4.25
8.5
10.518
0.638
1.275
2.55
2.55
4.0
0
No
6.02
11.0
6.0
11.0
4.0 (fbaud/1667)
8.0 (fbaud/1667)
0
0.1
No
1.25
4
0
No
PCIe
SATA
CEI
1 GbE
10 GbE
10 GbE
SONET/SDH
10.312
4
0
No
XAUI
3.125
1.875
0
No
OC-48/STM-16
OC-192/STM-64
9.953
4
0
No
9.953
RX: 8.0
TX: 4.0
0.1
0
No
XFP/XFI
1. The standard allows 11 MHz to 22 MHz.
2. CEI standard allows data rates of 4.976 to 6.375 Gb/s and 9.95 to 11.1 Gb/s.
3. XFP/XFI standard allows data rates of 9.95 to 11.2 Gb/s.
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Error Detector Specifications
J-BERT measurements
Trigger output (TRIG OUT)
• BER results
Pattern trigger mode
• Accumulated BER results
This provides a trigger synchronized with the selected error
detector reference pattern. In pattern mode the pulse is synchronized to repetitions of the output pattern. It generates 1 pulse for
every 4th PRBS pattern.
◦ Accumulated errored O’s and 1’s
◦ G.821
◦ Error-free intervals
Divided clock mode
◦ Accumulated parameters
In divided clock mode, the trigger is a square wave.
◦ Burst results
Table 24. Specifications for trigger output
• Eye diagram results
◦ 1-/0- level
◦ Eye height/amplitude/width
Clock divider
4, 8, 16 up to 11 Gb/s
32, 40, 64, 128 up to 12.5 Gb/s
◦ Jitter p-p and rms
Levels
High: +0.5 V typical
Low: - 0.5 V typical
Minimum pulse width
Pattern length x clock period/2
e.g. 10 Gb/s with 1000 bits = 50 ns
◦ Duty cycle distortion
Interface
DC coupled, 50 Ω nominal
◦ Extinction ratio
Connector
SMA female
◦ Cross-over voltage
◦ Signal to noise ratio
• Measurement suite
◦ BERT scan with RJ/DJ separation
Error output (ERR OUT)
◦ Spectral jitter decomposition
◦ Eye contour
This provides a signal to indicate received errors. The output is
the logical ‘OR’ of errors in a 128 bit segment of the data.
◦ Quick eye diagram and BER contour
Table 25. Specifications for error output
◦ Fast eye mask
◦ Output level and Q factor
◦ Error location capture
Interface format
RZ, active high
Levels
High: 1 V typical
Low: 0 V typical
Pulse width
128 clock periods
Interface
DC coupled, 50 Ω nominal
Connector
SMA female
◦ Fast total jitter
• Pattern capture
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Error Detector Specifications
Auxiliary output (AUX OUT)
Table 27. Specifications for gating input
This output can be used to provide either clock or data signals:
Burst synchronization time
1536 bits for PRBS
15 kbit for pattern
Backlash
1536 bits in non-CDR mode
Clock: clock signals from the input or the recovered clock signals
in CDR mode.
Data: weighted and sampled data.
1.5 µs in CDR-mode
Table 26. Specifications for the auxiliary output
Amplitude
600 mV typical
Interface
AC coupled, 50 Ω nominal
Connector
SMA female
Gate passive time
2560 bits in non-CDR mode
2560 bits or 1.5 µs whichever
is longer, in CDR mode
Interface levels
TTL levels
Pulse width
256 clock periods
Connector
SMA female
Pattern capture
Gating input (GATE IN)
The error detector can capture up to 32 MB data bits from the
device under test. The captured data bits are displayed in the
pattern editor in hex or binary format. The data bits can be
used as expected data for BER testing or can be saved for post
processing.
If a logical high is applied to the gating input the analyzer will
ignore the incoming bits during a BER measurement. The ignored
bit sequence is a multiple of 512 bits. For measuring data in
bursts of bits, rather than a continuous stream of bits, a special
operating mode is used. This is the burst sync mode. In this case,
the signal at the gating input controls the synchronization and the
error counting for each burst.
This is an important feature for recirculation loop measurements.
If clock data recovery (CDR) is used to recover the clock from the
burst data, the CDR takes 2 µs from the start of the burst data
to settle. The number of bits needed to synchronize itself during
a burst depends on whether the pattern consists of hardware
based PRBS data or memory based data. To run properly in burst
mode the system needs a backlash of data after the gating input
returns to high. During each burst, the gating input has to remain
passive.
Data input
CDR
settling Sync. time
time
Checked data
Backlash
Burst
Gate input
High
Low
Figure 28. Burst mode allows recirculation loop testing
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Mainframe Characteristics
Remote control interfaces
Table 28. General mainframe characteristics
Connectivity: GPIB (IEEE 488), LAN, USB 2.0.
Language: SCPI, IVI.COM. SCPI commands can be exported via
copy/paste from the utility menu/output window.
Built-in web server: provides remote GUI access and control
of J-BERT via a standard Java™ enabled web browser on your
computer.
Operating temperature
5 ºC to 40 ºC (-23 to +104 ºF)
Storage temperature
-40 ºC to +70 ºC (-65 to +158 ºF)
Operating humidity
95% relative humidity,
non-condensing
Storage humidity
50% relative humidity
Power requirements
100 to 240 V, ± 10%, 47 to 63 Hz,
450 VA
Physical dimensions
Width: 424.5 mm (16.75 in)
Height: 221.5 mm (8.7 in)
Depth: 580.0 mm (22.9 in)
Weight (net)
26.3 kg (58.0 lb)
Weight (shipping, max)
36.3 kg (80.0 lb)
Recommended
recalibration period
1 year
Parallel printer port, 2 x LAN, VGA output, 4 x USB 2.0, 1 x USB
1.1 (front).
Warranty period
1 year return to Agilent. See ordering
instructions for extended warranty
Operating system
IO libraries
Agilents IO libraries suite ships with the N4903B to help quickly
establish an error-free connection between your PC and instruments regardless of the vendor.
Other interfaces
Microsoft® Windows® XP Professional
Regulatory standards
Safety:IEC 61010-1:2001 EN 61010-1:2001 CAN/CSA-C22.2
No.61010-1-04
UL 61010-1:2004
EMC: EN 61326:1997 + A1:1998 + A2:2001
IEC 61326:1997 + A1:1998 + A2:2000
Quality management: ISO 9004
Specification assumptions
Figure 29. Rear panel view
The specifications in this document describe the instrument’s
warranted performance.
Display
Preliminary values are shown in italics.
8” color LCD touch screen
Non-warranted values are described as typical.
Data entry
All specifications are valid in a range from 5 °C to 40 °C ambient
temperature after a warm-up phase of 30 minutes.
• Color touch screen display, numeric keypad with up/down
arrows, dial-knob control or external key board and mouse via
USB interface
If not otherwise stated, all inputs and outputs need to be terminated with 50 Ω to ground.
• Pattern export/import
All specifications, if not otherwise stated, are valid using the
recommended cable set N4910A (2.4 mm, 24” matched pair).
Hard disk
For local storage of user patterns and data. An external disk is
also available for using over the USB interface.
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Ordering Instructions
J-BERT N4903B high-performance serial BERT
Includes six 50-Ω SMA terminations, ten adaptors 3.5 mm female to 2.4 mm male, commercial calibration report and certificate (“UK6”),
getting started guide, USB cable, keyboard, mouse, and Agilent I/O library.
Table 29. Option information
J-BERT Options
Description
Data rate
150 Mb/s to 12.5 Gb/s
150 Mb/s to 7 Gb/s
Extended data rate for pattern generator up
to 14.2 Gb/s
BERT with built-in and
tunable CDR N4903B
Pattern Generator
N4903B
N4903B-C13
N4903B-C07
N4903B-G13
N4903B-G07
N4903B-D14 [3]
Generator capabilities
Half-rate clock with variable duty cycle
N4903B-003
Jitter tolerance options
RJ, sRJ, PJ1, PJ2, SJ, BUJ injection
SSC, rSSC generation
Interference channel
(includes short cable kit N4915A-008)
Jitter tolerance compliance suite
N4903B-J10
N4903B-J11 [1]
N4903B-J20 [1]
N4903B-J12 [1]
Analyzer capabilities
Bit recovery mode
Upgrade from N4903B
Upgrade from N4903A version (factory)
N4903B-A01
—
Upgrade options for
N4903B
Description
Data rate
To 12.5 Gb/s (N4903B-C13/ N4903B-G13)
from 7 Gb/s (N4903B-C07/ N4903B-C13)
To 14.2 Gb/s data rate extension (factory)
N4903BU-D14 [3]
Generator capabiltiies
To half-rate clock with variable duty cycle
N4903BU-U03
Jitter tolerance options
To RJ,sRJ,PJ1,PJ2,SJ,BUJ injection
To SSC, rSSC generation
To interference channel
To jitter tolerance compliance suite
N4903BU -U10
N4903BU-U11
N4903BU-J20
N4903BU-U12
Analyzer capabilities
To bit recovery mode
To BERT from pattern generator (factory)
N4903B-UAB [2]
BERT with built-in and
tunable CDR N4903BU
Pattern Generator
N4903BU
N4903BU-U13
N4903BU-U01
—
—
N4903BU-UED
1. Only available with Option J10
2. Requires N4903A-J10/-U10 or N4903B-J10 and N4903A-CTR/-UTR or N4903B-UTR
3. Requires Option -G13, -C13, or -U13
Table 30. Warranty, calibration, and productivity services
Warranty
1 year return-to-Agilent warranty
1 year return-to-Agilent warranty
extended to 3 years
1 year return-to-Agilent warranty extended to 5 years
R1280: R-51 B-001-C
R1280: R-51 B-001-3C
Calibration
Agilent calibration upfront support plan
3 year coverage
Agilent calibration upfront support plan
5 year coverage
R1282: R-50C-011-3
Productivity assistance, remote or on-site
R1380-N49xx PS-S20 and PS-S10
Productivity
R1280 R-51 B-001-5C
R1282: R-50C-011-5
23
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an Agilent Authorized Technology Partner
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(800) 688-1111
Ordering Instructions
Table 31. Recommended accessories
Recommended accessories
Description
Model number
2.4 mm matched pair cable
N4910A
Adapter 3.5 mm (f) to 2.4 mm(m)
N4911A-002
50 Ω termination, 2.4 mm
N4912A
Short cable kit, 2.4 mm(m) to 2.4 mm(m) for ISI ports
N4915A-008
Clock cable, 2.4 mm to SMA
N4915A-009
2.4 mm cable
N4915A-004
Serial bus switch 6.5 Gb/s
N4915A-005
DisplayPort ISI generator
N4915A-006
SATA ISI channel
N4915-60001
2-tap de-emphasis signal converter
N4916A
4-tap de-emphasis converter with optional clock doubler
N4916B, N4916B-001
Optical receiver stress test
N4917A
Cables, adapters
Signal stress conditioning
47 ps transition time converter
N4915A-001
Filter set for PCIe 2.0 testing with 81150A
15431A
Test automation software platform
N5990A
Software
Accessories
Figure 31. De-emphasis signal converter N4916A
Figure 30. Optical receiver stress testing with N4917A allows calibrated
stressed receiver sensitivity tests
24
Electro Rent Corporation
an Agilent Authorized Technology Partner
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(800) 688-1111
Related Literature
Title
Publication number
J-BERT N4903A High-Performance Serial BERT Brochure
5989-3882EN
Bit Recovery Mode for Characterizing Idle and Framed Data Traffic Application Note
5989-3796EN
Calibrated Jitter, Jitter Tolerance Test and Jitter Laboratory with the J-BERT N4903A Application Note
5989-4967EN
Mastering Jitter Characterization with J-BERT & DCA-J Poster
5989-4823EN
®
PCIe Revision 2 Receiver Jitter Tolerance Testing with J-BERT N4903B Application Note
5989-4087EN
N4906B Serial BERT 3 and 12.5 Gb/s Data sheet
5989-2406EN
Agilent Physical Layer Test Brochure
5988-9514EN
ParBERT 81250 Product Overview
5968-9188E
Infiniium DCA-J Agilent 86100C Wide-Bandwidth Oscilloscope Mainframe and Modules Data Sheet
5989-0278EN
Infiniium DSO90000 Series High-Performance Oscilloscopes Data Sheet
5989-7819EN
Fast Total Jitter Solution Application Note
5989-3151EN
N5990A Test Automation Software Platform Data Sheet
5989-5483EN
N4916A De-Emphasis Signal Converter Data Sheet
5989-6062EN
N4916B 4-Tap De-Emphasis Signal Converter Data Sheet
5990-4630EN
PCIe2.0 Receiver Testing Application Note
5990-3233EN
N4917A Optical Receiver Stress Test Data Sheet
5989-6315EN
Calibrating Optical Stress Signals for Characterizing 10 Gb/s Optical Transceiver Application Note
5989-8393EN
N4915A-006 DisplayPort ISI Generator Data Sheet
5989-8688EN
Agilent Method of Implementation (MOI) for DisplayPort Sink Compliance Test Application Note
5989-9147EN
Forward Clocking - Receiver Jitter Tolerance Test with J-BERT N4903B Application Note
5990-3575EN
25
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Revised: October 1, 2009
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© Agilent Technologies, Inc. 2009
Printed in USA, October 15, 2009
5990-3217EN
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