Clevo E4121D-C Service manual

Preface
Notebook Computer
E4120 / E4121-C / E4125-C / E4121D-C
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes.
Preface
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Version 1.0
March 2010
Trademarks
Intel, Celeron and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and/or registered trademarks of their respective companies.
II
Preface
About this Manual
This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the E4120 /
E4121-C / E4125-C / E4121D-C series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Preface
Appendix A, Part Lists
Appendix B, Schematic Diagrams
III
Preface
IMPORTANT SAFETY INSTRUCTIONS
Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment:
Preface
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A OR 18.5V, 3.5A (65 Watts) minimum AC/DC Adapter.
CAUTION
Always disconnect all telephone lines from the wall outlet before servicing or disassembling this equipment.
TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,
TELECOMMUNICATION LINE CORD
This Computer’s Optical Device is a Laser Class 1 Product
IV
Preface
Instructions for Care and Operation
The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1.
Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer
to any shock or vibration.
2.
Do not place anything heavy
on the computer.
Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not leave it in a place
where foreign matter or moisture may affect the system.
Don’t use or store the computer in a humid environment.
Do not place the computer on
any surface which will block
the vents.
Preface
Do not expose it to excessive
heat or direct sunlight.
3.
Do not place it on an unstable
surface.
Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power
until you properly shut down
all programs.
Do not turn off any peripheral
devices when the computer is
on.
Do not disassemble the computer by yourself.
Perform routine maintenance
on your computer.
V
Preface
4.
5.
Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data.
Take care when using peripheral devices.
Use only approved brands of
peripherals.
Unplug the power cord before
attaching peripheral devices.
Preface
Power Safety
The computer has specific power requirements:

VI
•
•
Power Safety
Warning
•
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.
•
•
•
Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
Before cleaning the computer, make sure it is disconnected from any external power supplies.
Do not plug in the power
cord if you are wet.
Do not use the power cord if
it is broken.
Do not place heavy objects
on the power cord.
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
Preface
The following can also apply to any backup batteries you may have.
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon
in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
Preface
User’s Manual on CD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.
VIII
Preface
Contents
Part Lists ..................................................A-1
Overview .........................................................................................1-1
System Specifications .....................................................................1-2
External Locator - Top View with LCD Panel Open ......................1-4
External Locator - Front & Right side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) .........................................1-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9
Mainboard Overview - Top (Connectors) .....................................1-10
Mainboard Overview - Bottom (Connectors) ...............................1-11
Part List Illustration Location ........................................................ A-2
Top (E4120 / E4121-C / E4121D-C) ............................................. A-3
Top (E4125) ................................................................................... A-4
Bottom ........................................................................................... A-5
LCD (E4120 / E4121-C) ................................................................ A-6
LCD (E4125) ................................................................................. A-7
LCD (E4121D-C) .......................................................................... A-8
HDD ............................................................................................... A-9
Blu-Ray Combo ........................................................................... A-10
DVD-Super Multi Drive .............................................................. A-11
Disassembly ...............................................2-1
Schematic Diagrams................................. B-1
Overview .........................................................................................2-1
Maintenance Tools ..........................................................................2-2
Connections .....................................................................................2-2
Maintenance Precautions .................................................................2-3
Disassembly Steps ...........................................................................2-4
Removing the Battery ......................................................................2-5
Removing the Hard Disk Drive .......................................................2-6
Removing the Optical (CD/DVD) Device ......................................2-8
Removing the System Memory (RAM) ..........................................2-9
Removing and Installing the Processor .........................................2-11
Removing the Wireless LAN Module ...........................................2-14
Removing the 3.75G Module ........................................................2-15
Removing the Modem ...................................................................2-16
Removing the Bluetooth Module ..................................................2-17
Removing the LCD Back Cover (for E4121D-C only) .................2-18
Removing the LCD Front Cover ...................................................2-20
Removing the Keyboard ................................................................2-21
System Block Diagram ...................................................................B-2
Clock Generator ..............................................................................B-3
Processor 1/7 ...................................................................................B-4
Processor 2/7 ...................................................................................B-5
Processor 3/7 ...................................................................................B-6
Processor 4/7 ...................................................................................B-7
Processor 5/7 ...................................................................................B-8
Processor 6/7 ...................................................................................B-9
Processor 7/7 .................................................................................B-10
DDRIII SO-DIMM_0 ...................................................................B-11
DDRIII SO-DIMM_1 ...................................................................B-12
LVDS, Inverter .............................................................................B-13
HDMI, CRT ..................................................................................B-14
IBEXPEAK - M 1/9 ......................................................................B-15
IBEXPEAK - M 2/9 ......................................................................B-16
IBEXPEAK - M 3/9 ......................................................................B-17
IBEXPEAK - M 4/9 ......................................................................B-18
IX
Preface
Introduction ..............................................1-1
Preface
Preface
IBEXPEAK - M 5/9 ..................................................................... B-19
IBEXPEAK - M 6/9 ..................................................................... B-20
IBEXPEAK - M 7/9 ..................................................................... B-21
IBEXPEAK - M 8/9 ..................................................................... B-22
IBEXPEAK - M 9/9 ..................................................................... B-23
New Card, Mini PCIE .................................................................. B-24
CCD, 3G, TPM ............................................................................. B-25
Card Reader, LAN (JMB251) ...................................................... B-26
LAN (JMC251), SATA HDD, ODD ........................................... B-27
Audio Codec VIA 1812 ................................................................ B-28
KBC-ITE IT8502E ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
USB, Fan, TP, Multi Con1 ........................................................... B-31
5VS, 3VS, 1.05VS ........................................................................ B-32
Power 3.3V/5V ............................................................................. B-33
Power 1.5V/0.75V/1.8VS ............................................................. B-34
Power 1.1VS_VTT ....................................................................... B-35
Power VGFX_CORE ................................................................... B-36
V-Core .......................................................................................... B-37
DC-In, Charger ............................................................................. B-38
Click Board .................................................................................. B-39
Audio / USB / RJ11 Board ........................................................... B-40
Power Switch & LID Board ......................................................... B-41
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the E4120 / E4121-C / E4125-C / E4121D-C series
notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s
Manual. Information about drivers (e.g. VGA & audio) is also found in User’s Manual. That manual is shipped with the
computer.
Operating systems (e.g. Windows 7, Windows Vista, etc.) have their own manuals as do application software (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
1.Introduction
The E4120 / E4121-C / E4125-C / E4121D-C series notebook is designed to be upgradeable. See Disassembly on page 2
- 1 for a detailed description of the upgrade procedures for each specific component. Please note the warning and safety
information indicated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
System Specifications
Processor
Core Logic
Keyboard & Pointing Device
Intel® Core™ i7-620M Processor:
(2.66GHz)
32nm (32 Nanometer) Process Technology,
4MB L2 Cache & 1066MHz FSB - TDP 35W
rPGA988A Socket P Package
Intel® HM55 Chipset
Display
Isolated WinKey Keyboard
Built-in TouchPad with Multi-Gesture
Functionality
14.0” / 35.56cm 16:9 HD (1366 * 768)
Interface
Memory
Three USB 2.0 Ports
One External Monitor Port
One HDMI Out Port
One Headphone-Out Jack
One Microphone-In Jack
One RJ-45 LAN Jack
One RJ-11 Modem Jack
One DC-In Jack
1.Introduction
Intel® Core™ i5-540M Processor:
(2.53GHz)
32nm (32 Nanometer) Process Technology,
3MB L2 Cache & 1066MHz FSB - TDP 35W
rPGA988A Socket P Package
Intel® Core™ i5-520M Processor:
(2.4GHz)
32nm (32 Nanometer) Process Technology,
3MB L2 Cache & 1066MHz FSB - TDP 35W
rPGA988A Socket P Package
Intel® Core™ i5-430M Processor:
(2.26GHz)
32nm (32 Nanometer) Process Technology,
3MB L2 Cache & 1066MHz FSB, - TDP 35W
rPGA988A Socket P Package
Intel® Core™ i3-350M Processor:
(2.26GHz)
32nm (32 Nanometer) Process Technology,
3MB L2 Cache & 1066MHz FSB - TDP 35W
rPGA988A Socket P Package
Intel® Core™ i3-330M Processor:
(2.13GHz)
32nm (32 Nanometer) Process Technology,
3MB L2 Cache & 1066MHz FSB - TDP 35W
rPGA988A Socket P Package
1 - 2 System Specifications
Dual Channel DDRIII (DDR3)
Two 204 Pin SO-DIMM sockets supporting
DDR3 1066 MHz
Memory Expandable up to 4GB (using 2GB
SO-DIMM Modules)
Video
Intel® HM55 Integrated Video:
High Preference 3D/2D Graphic Accelerator
Shared Memory Architecture of up to 1748MB
Supports Microsoft DirectX10 Compatible
BIOS
One 32Mbit SPI Flash ROM
Phoenix™ BIOS
Storage
One Changeable 12.7mm(h) Super Multi/Blu-
ray Combo Optical Device Drive with SATA
Interface
One Changeable 2.5" / 9.5 mm (h) HDD with
SATA (Serial) Interface
Audio
High Definition Audio Interface
3D Enhanced Stereo System
Built-In Microphone
2 * Built-In Speakers
Card Reader
Embedded 7-in-1 Card Reader (MS/ MS Pro/
SD/ Mini SD/ MMC/ RS MMC/ MS Duo) Note:
MS Duo/ Mini SD/ RS MMC Cards require a
PC adapter
Slots
One ExpressCard 34 Slot Supporting USB &
PCIe Interfaces
Two Mini-Card Slots with PCIe (Slot 1) & USB
(Slot 2) interface:
Slot 1 for WLAN Module (Factory Option)
Slot 2 for 3.75G Module (Factory Option)
Introduction
Communication
Security
56K Fax/Modem
Security (Kensington® Type) Lock Slot
BIOS Password
Built-In 10/100/1000Mb Base-TX Ethernet LAN
Intel® WiFi Link 1000 (802.11 b/g/n) Half MiniCard PCIe WLAN Module (Factory Option)
3rd Party WLAN 802.11b/g/n Half Mini-Card
Module with PCIe Interface(Option)
Bluetooth 2.1 + EDR (Enhanced Data Rate)
Module (Factory Option)
1.3M Pixel PC Camera Module with USB
interface (Factory Option)
Power Management
Supports Wake on LAN
Supports Wake on USB
Windows® Vista (with Service Pack 2)
Windows® 7
Design Feature
IMR Changeable LCD Back Covers (Factory
Option)
Environmental Spec
Temperature
Operating:
Non-Operating:
Relative Humidity
Operating:
Non-Operating:
1.Introduction
UMTS/HSPDA-based 3.75G Module with USB
Half Mini-Card Interface (Factory Option)
Quad-band GSM/GPRS (850 MHz, 900 MHz,
1800 MHz, 1900 MHz)
UMTS WCDMA FDD (2100 MHz)
Note that UMTS modes CAN NOT be used
in North America
Operating System
5°C - 35°C
-20°C - 60°C
20% - 80%
10% - 90%
Dimensions & Weight
340mm (w) * 238mm (d) * 15.6 - 35.2mm (h)
2.2 kg with 6 Cell Battery & ODD
Power
Full Range AC/DC Adapter
AC input 100 - 240V, 50 - 60Hz,
DC Output 19V, 3.42A or 18.5V, 3.5A (65
Watts)
Removable 6 Cell Smart Lithium Ion Battery
Pack 48.84WH
(Factory Option) Removable 6 Cell Smart
Lithium Ion Battery Pack 62.16WH
System Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
1.Introduction
Top View
1
1. Optional Built-In
PC Camera
2. LCD
3. Power Button
4. Hot Key Buttons
5. LED Status
Indicators
6. Keyboard
7. Built-In
Microphone
8. Touchpad &
Buttons
2
4
5
6
7
8
1 - 4 External Locator - Top View with LCD Panel Open
3
Introduction
External Locator - Front & Right side Views
Figure 2
Front Views
1. LED Power
Indicators
1
Right Side Views
1
2
3
4
5
6
1. Microphone-In
Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
4. RJ-11 Phone
Jack
5. Optical Device
Drive Bay
6. Security Lock
Slot
External Locator - Front & Right side Views 1 - 5
1.Introduction
Figure 3
Introduction
External Locator - Left Side & Rear View
Figure 4
1.Introduction
Left Side View
1. DC-In Jack
2. External Monitor
Port
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. Vent/Fan Intake/
Outlet
6. 2 * USB 2.0 Ports
7. ExpressCard Slot
8. 7-in-1 Card
Reader
1
2
3
4
6
Figure 5
Rear View
1. Battery
1 - 6 External Locator - Left Side & Rear View
1
5
6
7
8
Introduction
External Locator - Bottom View
Figure 6
Bottom View
1
1
3
3
2
2
3
4
3
WITHOUT 3G
3
4
5
WITH 3G

Overheating
To prevent your computer from overheating
make sure nothing
blocks the vent/fan intakes while the computer is in use.
External Locator - Bottom View 1 - 7
1.Introduction
3
1. Battery
2. Component Bay
Cover
3. Vent/Fan Intake/
Outlet
4. Hard Disk Bay
Cover
5. 3.75G/HSPA
USIM Card
Cover (optional)
Introduction
Figure 7
Mainboard Overview - Top (Key Parts)
Mainboard Top
Key Parts
1. ExpressCard
Connector
2. JMC251
3. KBC ITE IT8512E
1.Introduction
1
2
3
3
1 - 8 Mainboard Overview - Top (Key Parts)
4
Introduction
Mainboard Overview - Bottom (Key Parts)
Figure 8
Mainboard Bottom
Key Parts
7
6
1
3
5
2
4
Mainboard Overview - Bottom (Key Parts) 1 - 9
1.Introduction
1. CPU Socket (no
CPU installed)
2. Memory Slots
DDR3 SO-DIMM
3. Intel HM55
4. Mini-Card
Connector (3G
Module)
5. Audio Codec
6. Mini-Card
Connector (WLAN
Module)
7. Card Reader
Socket
Introduction
Figure 9
Mainboard Overview - Top (Connectors)
1.Introduction
Mainboard Top
Connectors
1
1
1. USB Port
2. Microphone
Cable Connector
3. Audio Cable
Connector
4. TouchPad Cable
Connector
5. Keyboard Cable
Connector
9
10
2
6
8
5
11
4
7
3
1 - 10 Mainboard Overview - Top (Connectors)
Introduction
Mainboard Overview - Bottom (Connectors)
Figure 10
Mainboard Bottom
Connectors
1
2
8
7
3
4
5
6
Mainboard Overview - Bottom (Connectors) 1 - 11
1.Introduction
1. CCD Connector
2. LCD Cable
Connector
3. CMOS Cable
Connector
4. BT Cable
Connector
5. ODD Connector
6. HDD Connector
7. MDC Cable
Connector
8. Fan Cable
Connector
1.Introduction
Introduction
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the E4120 / E4121-C / E4125-C / E4121D-C series
notebook’s parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a 
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also.

Information
A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar.

Warning
Overview 2 - 1
2.Disassembly
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
2.Disassembly
•
•
•
•
•
•
M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap
Connections
Connections within the computer are one of four types:
2 - 2 Overview
Locking collar sockets for ribbon connectors
To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors
To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors
To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When replacing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets
To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions:
Power Safety
Warning
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
2.Disassembly
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
components could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight.
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor
the position of magnetized tools (i.e. screwdrivers).
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly
damaged.
5. Be careful with power. Avoid accidental shocks, discharges or explosions.
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies.
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire.
6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.

Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery:
1. Remove the battery
To remove the Modem:
page 2 - 5
1. Remove the battery
2. Remove the modem
page 2 - 5
page 2 - 6
To remove the Bluetooth Module:
To remove the HDD:
2.Disassembly
1. Remove the battery
2. Remove the HDD
To remove the Optical Device:
1. Remove the battery
2. Remove the Optical device
page 2 - 5
page 2 - 8
To remove the System Memory:
1. Remove the battery
2. Remove the system memory
page 2 - 5
page 2 - 9
To remove and install a Processor:
1. Remove the battery
2. Remove the processor
3. Install the processor
page 2 - 5
page 2 - 11
page 2 - 13
To remove the WLAN Module:
1. Remove the battery
2. Remove the wireless LAN
page 2 - 5
page 2 - 14
To remove the 3.75G Module:
1. Remove the battery
2. Remove the 3.75G
2 - 4 Disassembly Steps
page 2 - 5
page 2 - 15
1. Remove the battery
2. Remove the Bluetooth
page 2 - 5
page 2 - 16
page 2 - 5
page 2 - 17
To remove the LCD Back Cover (E4121D-C):
1. Remove the battery
2. Remove the LCD Back Cover
page 2 - 5
page 2 - 18
To remove the LCD Front Cover:
1. Remove the battery
2. Remove the LCD Front Cover
page 2 - 5
page 2 - 20
To remove the Keyboard:
1. Remove the battery
2. Remove the keyboard
page 2 - 5
page 2 - 21
Disassembly
Removing the Battery
1.
2.
3.
4.
Turn the computer off, and turn it over.
Slide the latch 1 in the direction of the arrow.
Slide the latch 2 in the direction of the arrow, and hold it in place.
Slide the battery 63 in the direction of the arrow 4 .
a.
2
Figure 1
Battery Removal
a. Slide the latch and hold
in place.
b. Slide the battery in the direction of the arrow.
1
2.Disassembly
b.
3

3. Battery
4
Removing the Battery 2 - 5
Disassembly
Removing the Hard Disk Drive
Figure 2
HDD Assembly
Removal
a. Locate the HDD bay
cover and remove the
screw(s).
The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
(h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Chapter 4 of the User’s Manual) when setting up a new hard disk.
Hard Disk Upgrade Process
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 .
2.Disassembly
a.
1
2

HDD System Warning

New HDD’s are blank. Before you begin make sure:
You have backed up any data you want to keep from your old HDD.
• 2 Screws
You have all the CD-ROMs and FDDs required to install your operating system and programs.
If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan
to install. Copy these to a removable medium.
2 - 6 Removing the Hard Disk Drive
Disassembly
3.
4.
5.
6.
7.
Remove the hard disk bay cover 63 .
Grip the tab and slide the hard disk in the direction of arrow 4 .
Lift the hard disk out of the bay 5 .
Remove the screw 6 - 9 and the adhesive cover 10 from the hard disk 11 .
Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
d.
b.
Figure 3
HDD Assembly
Removal (cont’d.)
b. Remove the HDD bay
cover.
c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
e. Remove the screw and
adhesive cover.
2.Disassembly
5
3
e.
9
c.
6
8
4
10

7
11
3. HDD Bay Cover
10. Adhesive Cover
11. HDD
• 4 Screws
Removing the Hard Disk Drive 2 - 7
Disassembly
Figure 4
Optical Device
Removal
a. Remove the screws.
b. Remove the cover.
c. Remove the screw and
push the optical device
out off the computer at
point 8.
Removing the Optical (CD/DVD) Device
1.
2.
3.
4.
5.
6.
Turn off the computer, and remove the battery (page 2 - 5).
Locate the RAM & CPU bay cover 1 , and remove screws 2 - 5 .
Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
Carefully disconnect the fan cable 6 , and remove the cover 1 .
Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 .
Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
screw holes should line up).
7. Restart the computer to allow it to automatically detect the new device.
2.Disassembly
a.
c.
2
3
1
4
7
5
b.

1. Component Bay Cover
9. Optical Device
• 5 Screws
2 - 8 Removing the Optical (CD/DVD) Device
1
9
6
8
Disassembly
Removing the System Memory (RAM)
Figure 5
The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
DDR3 1066MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1GB, 2GB and
4GB and DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your
computer.
Memory Upgrade Process
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
2. The RAM module (s) will be visible at point 1 on the main board.
3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the
arrows (Figure 6c).
RAM Module
Removal
a. Locare the memory
socket.
b. Pull the release
latch(es).
c. Remove the module(s).
a.
Contact Warning
2
4
1
3
4.
5.
6.
7.
The RAM module(s) 4 will pop-up (Figure 6d), and you can then remove it.
Pull the latches to release the second module if necessary.
Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
will go. DO NOT FORCE the module; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
Be careful not to touch
the metal pins on the
module’s connecting
edge. Even the cleanest hands have oils
which can attract particles, and degrade the
module’s
performance.

4. RAM Module
Removing the System Memory (RAM) 2 - 9
2.Disassembly

c.
b.
Disassembly
Figure 6
RAM Module
Removal (cont’d.)
d. Properly re-insert
bay cover pins.
9. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay
cover).
Note that there are four 5 - 8 cover pins which need to be aligned with slots in the case, to insure a proper cover
fit, before screwing down the bay cover.
the
d.
5
6
2.Disassembly
7
8
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
2 - 10 Removing the System Memory (RAM)
Disassembly
Removing and Installing the Processor
Figure 7
Processor Removal Procedure
1. Turn off the computer, remove the battery (page 2 - 5), and the component bay cover (page 2 - 9).
2. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label).
3. Carefully lift up the heat sink 4 (Figure 7c) off the computer.
a.
Processor
Removal
a. Remove the cover
and Iocate the heat
sink.
b. Loosen the screws
in the order indicated.
c. Remove the heat
sink.
CPU Warning
b.
c.
1
4
2
In order to prevent
damaging the contact
pins when removing
the CPU, it is necessary to first remove the
WLAN module from
the computer.
3

4. Heat Sink
Note: Loosen the screws in the reverse order
3, 2, 1 as indicated on the label.
• 3 Screws
Removing and Installing the Processor 2 - 11
2.Disassembly

Disassembly
Figure 8
Processor Removal
(cont’d)
d. Turn the release latch to
unlock the CPU.
e. Lift the CPU out of the
socket.
4.
5.
6.
7.
Turn the release latch 6 towards the unlock symbol
, to release the CPU (Figure 8a).
Carefully (it may be hot) lift the CPU 7 up out of the socket (Figure 8b).
See page 2 - 13 for information on inserting a new CPU.
When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d.
6
2.Disassembly
6
Unlock
Lock
e.

7

7. CPU
2 - 12 Removing and Installing the Processor
Caution
The heat sink, and CPU area in
general, contains parts which are
subject to high temperatures. Allow the area time to cool before removing these parts.
Disassembly
Processor Installation Procedure
Figure 9
1. Insert the CPU A , pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and turn
the release latch B towards the lock symbol
(Figure 9b).
2. Remove the sticker C (Figure 9c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 9c.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 9d).
5. Replace the component bay cover and tighten the screws (page 2 - 11).
c.
a.
Processor
Installation
a. Insert the CPU.
b. Turn the release latch towards the lock symbol.
c. Remove the sticker from
the heat sink and insert
the heat sink.
d. Tighten the screws.
A
b.
2.Disassembly
C
D
d.
1
Note:
2
B
3
Tighten the screws
in the order 1, 2, 3 as
indicated on the label.

A. CPU
D. Heat Sink
• 3 Screws
Removing and Installing the Processor 2 - 13
Disassembly
Figure 10
Wireless LAN
Module Removal
1.
2.
3.
4.
Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The Wireless LAN module will be visible at point 1 on the mainboard.
Carefully disconnect cables 2 - 3 , then remove screw 4 from the module socket.
Lift the Wireless LAN module 5 (Figure 11d) up and off the computer.
a.
2.Disassembly
a. Remove the cover.
b. Disconnect the cables
and remove the screw.
c. Lift the WLAN module
out.
Removing the Wireless LAN Module
c.
5
1
b.
4
3

5. WLAN Module.
2
• 1 Screw
2 - 14 Removing the Wireless LAN Module
Disassembly
Removing the 3.75G Module
1.
2.
3.
4.
5.
Figure 11
3.75G Module
Removal
Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The 3.75G module will be visible at point 1 on the mainboard.
Carefully disconnect the cable 2 , then remove the screw 3 from the module socket.
The 3.75G module 4 will pop-up.
Lift the 3.75G module (Figure 11d) up and off the computer.
a. Remove the cover.
b. Disconnect the cable
and remove the screw.
c. The 3.75G module will
pop up.
d. Lift the 3.75G module
out.
a.
2.Disassembly
d.
1
c.
b.

4
4. 3.75G Module.
2
3
4
• 1 Screw
Removing the 3.75G Module 2 - 15
Disassembly
Figure 12
Modem Removal
a. Locate the modem.
b. Remove the screws and
disconnect the cable.
c. Lift the modem up and
off the sockets.
Removing the Modem
1.
2.
3.
4.
Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The modem will be visible at point 1 on the mainboard.
Remove the screws 2 - 3 and disconnect the cable 4 .
Carefully lift the modem 6 up and off the socket 5 .
c.
a.
2.Disassembly
5
1
b.
2
6

4
6. Modem
3
• 2 Screws
2 - 16 Removing the Modem
Disassembly
Removing the Bluetooth Module
1.
2.
3.
4.
5.
Figure 13
Turn off the computer, remove the battery (page 2 - 5), and component bay cover (page 2 - 9).
The Bluetooth module will be visible at point 1 on the mainboard.
Remove the screw 2 and turn the module over.
Carefully disconnect the cable 3 and separate the connector 4 (Figure 13b) from the Bluetooth Module.
Lift the Bluetooth module 5 (Figure 13c) up and off the computer.
a.
d.
Bluetooth Module
Removal
a. Locate the Bluetooth module.
b. Remove the screw.
c. Disconnect the cable and
the connector from the
Bluetooth module.
d. Lift the Bluetooth module
out.
2.Disassembly
1
b.
c.
4
3
5

5. Bluetooth Module
2
• 1 Screw
Removing the Bluetooth Module 2 - 17
Disassembly
Removing the LCD Back Cover (for E4121D-C only)
Figure 14
LCD Back Cover
Removal
2.Disassembly
a. Remove the rubber covers and screws.
b. Slide the cover forward.
c. Remove the LCD back
cover.
1. Turn off the computer, and turn the computer over to remove the battery (page 2 - 5).
2. Open the LCD and carefully remove the rubber screw covers 1 & 2 (2 corner rubber screw covers only) and set
them aside.
3. Remove screws 3 & 4 from the front cover.
4. Carefully slide the cover forward in the direction of the arrows 5 & 6 as illustrated below.
5. Remove the LCD back cover 7 .
a.
2
1
3
b.
5
6
4
c.

7. LCD Back Cover
• 2 Screws

Rubber Screw Covers
After removing the rubber screw covers, place them on a
clean dry surface (or attach them to the front cover itself) in
order to prevent loss of adhesive.
2 - 18 Removing the LCD Back Cover (for E4121D-C only)
7
Disassembly
6. Align the replacement cover with the dotted line 8 as illustrated below (and as marked on the cover).
Figure 15
LCD Back Cover
Removal (cont’d)
d.
d. Align the replacement
cover and slide forward to
click firmly into place.
8
10
10
2.Disassembly
9
9
10
7. Slide the back cover forward until it clicks firmly into place 9 .
8. Run your hands around the sides and front of the cover 10 to make sure it is firmly aligned in place (carefully press
down to make sure the fit is secure).
9. Replace the screws and rubber covers.
Removing the LCD Back Cover (for E4121D-C only) 2 - 19
Disassembly
Figure 16
LCD Front Cover
Removal
2.Disassembly
a. Remove the screws and
unsnap the LCD front
cover from the LCD panel.
b. Slide the LCD panel cover in the direction of the
arrow.
Removing the LCD Front Cover
1. Turn off the computer, and remove the battery (page 2 - 5), and remove the LCD back cover (page 2 - 18).
2. Remove the rubber covers and screws 1 - 4 (Figure 16a), then run your finger around the middle of the frame to
carefully unsnap the LCD front cover 5 from the LCD panel.
3. After unsnapping all four sides of the LCD front cover, carefully slide the LCD front cover downwards in the direction of the arrow 6 (be careful of the LCD hinges at point 7 ).
4. You can now remove the LCD front cover.
a.
2
3
b.
5
6
1
5
4
7

5. LCD Front Cover
• 4 Screws
2 - 20 Removing the LCD Front Cover

Rubber Screw Covers
After removing the rubber screw covers, place them on a
clean dry surface (or attach them to the front cover itself) in
order to prevent loss of adhesive.
7
Disassembly
Removing the Keyboard
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Press the four keyboard latches at the top of the keyboard to elevate the keyboard from its normal position (you
may need to use a small screwdriver to do this).
3. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable (Figure 17b).
4. Disconnect the keyboard ribbon cable 5 from the locking collar socket 6 .
5. Carefully lift up the keyboard 7 (Figure 17c) off the computer.
a.
1
2
3
4
c.
Figure 17
Keyboard Removal
a. Press the four latches to
release the keyboard.
b. Lift the keyboard up and
disconnect the cable
from the locking collar.
c. Remove the keyboard.
Re-Inserting the Keyboard
b.
5
7
When re-inserting the
keyboard firstly align
the four keyboard tabs
at the bottom of the
keyboard with the slots
in the case.
6

Keyboard Tabs
7. Keyboard
Removing the Keyboard 2 - 21
2.Disassembly

2.Disassembly
Disassembly
2 - 22
Part Lists
Appendix A: Part Lists
This appendix breaks down the E4120 / E4121-C / E4125-C / E4121D-C series notebook’s construction into a series of
illustrations. The component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
A.Part Lists
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part Lists
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A- 1
Part List Illustration
Location
Parts
Top
E4120
E4121-C
page A - 3
A.Part Lists
Bottom
LCD
E4121D-C
page A - 4
page A - 3
page A - 7
page A - 8
page A - 5
page A - 7
HDD
page A - 9
Blu-Ray Combo
page A - 10
DVD-Super Multi Drive
page A - 11
A - 2 Part List Illustration Location
E4125-C
Part Lists
Top (E4120 / E4121-C / E4121D-C)
Figure A - 1
香檳銀色
黑色
(灰色)
非耐落
導電布
度
黑色
Top (E4120 / E4121-C / E4121D-C) A - 3
A.Part Lists
Top
(E4120 / E4121-C)
Part Lists
Top (E4125)
A.Part Lists
Figure A - 2
Top
(E4125)
黑色
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
(灰色)
無鉛
無鉛
無鉛
無鉛
非耐落
無鉛
無鉛
無鉛
無鉛
無鉛
度
導電布
A - 4 Top (E4125)
黑色
Part Lists
Bottom
Figure A - 3
Bottom A - 5
A.Part Lists
Bottom
Part Lists
LCD (E4120 / E4121-C)
無鉛
無鉛
無鉛
無鉛
銘板
無鉛
無鉛
A.Part Lists
Figure A - 4
非耐落
無鉛
無鉛
無鉛
LCD
(E4120 / E4121-C)
無鉛
無鉛
無鉛
精乘 無鉛
精乘
無鉛
(華力)無鉛
精乘 (銅箔接地)無鉛
精乘
精乘
無鉛
無鉛
今皓 / 泰林
無鉛
華力 / 訊裕
無鉛
精乘
無鉛
精乘
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
中性
電鑄薄膜鍍亮鉻(字體連結)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
A - 6 LCD (E4120 / E4121-C)
一般漆
Part Lists
LCD (E4125)
Figure A - 5
無鉛
無鉛
無鉛
銘板
無鉛
無鉛
非耐落
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
精乘
無鉛
精乘
無鉛
(華力)無鉛
精乘 (銅箔接地)無鉛
精乘
無鉛
今皓 / 泰林
無鉛
華力 / 訊裕
無鉛
精乘
無鉛
精乘
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
中性
電鑄薄膜鍍亮鉻(字體連結)
無鉛
FOR C4801M
無鉛
FOR C4801M-C
FOR E4121D-C
無鉛
FOR MOFA
無鉛
FOR C4801M-C
FOR E4121D-C
無鉛
FOR E4121D-C
無鉛
FOR E4121M/D-C
無鉛
FOR C4801M/-C
無鉛
無鉛
無鉛
LCD (E4125) A - 7
A.Part Lists
LCD
(E4125)
無鉛
Part Lists
LCD (E4121D-C)
A.Part Lists
Figure A - 6
LCD
(E4121D-C)
無鉛
無鉛
無鉛
無鉛
銘板
無鉛
無鉛
非耐落
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
精乘
無鉛
精乘
無鉛
(華力)無鉛
精乘 (銅箔接地)無鉛
精乘
無鉛
今皓 / 泰林
無鉛
華力 / 訊裕
無鉛
精乘
無鉛
精乘
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
中性
電鑄薄膜鍍亮鉻(字體連結)
無鉛
FOR C4801M
無鉛
FOR C4801M-C
FOR E4121D-C
無鉛
FOR MOFA
無鉛
FOR C4801M-C
FOR E4121D-C
無鉛
FOR E4121D-C
無鉛
FOR E4121M/D-C
無鉛
FOR C4801M/-C
無鉛
無鉛
無鉛
A - 8 LCD (E4121D-C)
Part Lists
HDD
Figure A - 7
無鉛
(無鉛)
HDD A - 9
A.Part Lists
HDD
Part Lists
Blu-Ray Combo
A.Part Lists
Figure A - 8
Blu-Ray Combo
*(非耐落)
無鉛
無鉛
已內縮
無鉛
無鉛
反銀龍_霧膜
A - 10 Blu-Ray Combo
無鉛
Part Lists
DVD-Super Multi Drive
Figure A - 9
*(非耐落)
無鉛
無鉛
已內縮
無鉛
已內縮
無鉛
內縮
無鉛
無鉛
無鉛
DVD-Super Multi Drive A - 11
A.Part Lists
DVD-Super Multi
Drive
A.Part Lists
Part Lists
A - 12
Schematic Diagrams
Appendix B: Schematic Diagrams
This appendix has circuit diagrams of the E412P-C notebook’s PCB’s. The following table indicates where to find the
appropriate schematic diagram.
Diagram - Page
Diagram - Page
Diagram - Page
IBEXPEAK - M 2/9 - Page B - 16
LED, MDC, BT - Page B - 30
Clock Generator - Page B - 3
IBEXPEAK - M 3/9 - Page B - 17
USB, Fan, TP, Multi Con1 - Page B - 31
Processor 1/7 - Page B - 4
IBEXPEAK - M 4/9 - Page B - 18
5VS, 3VS, 1.05VS - Page B - 32
Processor 2/7 - Page B - 5
IBEXPEAK - M 5/9 - Page B - 19
Power 3.3V/5V - Page B - 33
Processor 3/7 - Page B - 6
IBEXPEAK - M 6/9 - Page B - 20
Power 1.5V/0.75V/1.8VS - Page B - 34
Processor 4/7 - Page B - 7
IBEXPEAK - M 7/9 - Page B - 21
Power 1.1VS_VTT - Page B - 35
Processor 5/7 - Page B - 8
IBEXPEAK - M 8/9 - Page B - 22
Power VGFX_CORE - Page B - 36
Processor 6/7 - Page B - 9
IBEXPEAK - M 9/9 - Page B - 23
V-Core - Page B - 37
Processor 7/7 - Page B - 10
New Card, Mini PCIE - Page B - 24
DC-In, Charger - Page B - 38
DDRIII SO-DIMM_0 - Page B - 11
CCD, 3G, TPM - Page B - 25
Click Board - Page B - 39
DDRIII SO-DIMM_1 - Page B - 12
Card Reader, LAN (JMB251) - Page B - 26
Audio / USB / RJ11 Board - Page B - 40
LVDS, Inverter - Page B - 13
LAN (JMC251), SATA HDD, ODD - Page B - 27
Power Switch & LID Board - Page B - 41
HDMI, CRT - Page B - 14
Audio Codec VIA 1812 - Page B - 28
IBEXPEAK - M 1/9 - Page B - 15
KBC-ITE IT8502E - Page B - 29
Schematic
Diagrams
B.Schematic Diagrams
System Block Diagram - Page B - 2
Table B - 1

Version Note
The schematic diagrams in this chapter
are based upon version 6-7P-E4124-002.
If your mainboard (or
other boards) are a later version, please
check with the Service
Center for updated diagrams (if required).
B - 1
Schematic Diagrams
System Block Diagram
CLICK BOARD
Calpella System Block Diagram
6-71-C4502-D02
VDD3,VDD5
14.318 MHz
POWER GPU
POWER SWITCH BOARD
Clock Generator
SLG8SP585V
POWER SWITCH+HOTKEY X 3
6-71-C450S-D02
Arrandale
PROCESSOR
rPGA989/988
AUDIO BOARD
B.Schematic Diagrams
PJ11+USB+EARPHONE+EXT.MIC
6-71-C410A-D01
FDI
Sheet 1 of 40
System Block
Diagram
800/1067 MHz
DDR3 / 1.5V
5V,3V,5VS,3VS,1.5VS,
DDRIII
SO-DIMM0
SYSTEM SMBUS
0.1"~13
HDMI
0.5"~6.5"
DDRIII
SO-DIMM1
CRT CONNECTOR
CR T SW IT CH
L VD S SW IT CH
INTERNAL
GRAPHICS
HP
OUT
INT SPK R
AZALIA
MDC
MODULE
TPM
SPI
MIC
IN
RJ-11
32.768 KHz
EC
ITE 8502E
1.1VS_VTT
<=8"
Ibex Peak-M
Platform
Controller
Hub (PCH)
810602-1703
<8"
VCORE
AUDIO BOARD
INTERNAL
GRAPHICS
Synaptic
LCD CONNECTOR,
1.5V,0.75VS(VTT_MEM)
DMI*4
<15"
CLICK BOARD
TOUCH PAD
1.8VS
Memory Termination
Azalia Codec
VIA VT1812
AMP
N7101
INT SPK L
128pins LQFP
1 4*1 4*1. 6mm
MDC CON
33 MHz
27x27mm
1071 Ball FCBGA
LPC
0.5"~11"
INT. K/B
EC SMBUS
BIOS
SPI
INT MIC
AZALIA LINK
PCIE
THERMAL
SENSOR
W83L771AWG
SMART
FAN
SMART
BATTERY
SATA I/II 3.0Gb/s
100 MHz
24 MHz
<12"
32.768KHz
USB2.0
480 Mbps
<12"
New Card
SOCKET
(USB3)
3G CARD
(USB9)
(Optional)
Mini PCIE
SOCKET
(USB2)
JMICRO
JMC251
LAN
1"~16"
MHz
RJ-45
SATA HDD
SATA ODD
USB0
USB1
USB4
AUDIO
BOARD
B - 2 System Block Diagram
Bluetooth
(USB11)
CCD
(USB5)
CARD READER 25
7IN1
SOCKET
Schematic Diagrams
Clock Generator
CLKGEN POWER
CLOCK GENERATOR
C LK _V C C 1
CL K _ V CC2
3 .3 V S
CL K _ V CC 1
U7
1
5
17
24
29
X OU T
XIN
3 3 _0 4
R E F _0 / C P U _ S E L
30
CL K _ S DA T A
CL K _ S CL K
31
32
2
8
9
12
21
26
33
_ D OT
_ 27
_ S RC
_ CP U
_ RE F
V D D _ S R C _I / O
V D D _ C P U _I / O
D OT _9 6
D OT _ 96 #
2 7M
2 7 M_ S S
X TA L _ OU T
X TA L _ I N
RE F _ 0 /CP U _ S E L
S DA
S CL
S RC_ 1 /S A T A
S R C _ 1# / S A T A #
S RC_ 2
S R C _2 #
15
18
L 15
3
4
C L K _B U F _ D OT 9 6 _P 1 5
C L K _B U F _ D OT 9 6 _N 15
C K P W R GD / P D #
C2 1 5
0. 1 u _ 10 V _ X 7R _0 4
1 u _6 . 3 V _ X5 R _ 0 4
Sheet 2 of 40
Clock Generator
0 .1 u F n e a r t h e e v er y p ow e r p i n
10
11
13
14
16
CP U_ 1
C P U _1 #
CP U_ 0
C P U _0 #
C2 0 5
0 . 1 u_ 1 0 V _X 7 R _ 0 4
6
7
C L K _S A T A 1 5
C L K _S A T A # 1 5
C L K _P C I E _ I C H 1 5
C L K _P C I E _ I C H # 1 5
C P U _ S T OP #
R 1 44
2. 2 1 K _1 % _ 04
C P U _ S T OP #
V S S _ DO T
VSS_ 2 7
VSS_ SATA
V S S _ S RC
V S S _ CP U
V S S _ RE F
GN D
C 21 3
*1 5 m li _ sh o rt _ 06
20
19
23
22
25
3 .3 V S
B.Schematic Diagrams
R1 3 0
15 C LK _ B U F _R E F 1 4
27
28
V DD
V DD
V DD
V DD
V DD
1 . 1V S _V T T
CL K _ V CC 2
L14
C L K _B U F _ B C L K _ P 15
C L K _B U F _ B C L K _ N 1 5
C2 1 4
C 2 04
0 . 1 u_ 1 0V _ X 7 R _ 04
1 u _ 6. 3 V _ X 5R _0 4
*1 5m i l _s h ort _0 6
C L K _P W R GD
V D D_ I / O c a n b e
r a ng i n g f r om
3 .3 VS
S L G8 S P 5 85
I C S 9 L RS 3 1 97
R e al t e k R T M8 7 5 N6 3 2 -V B
1 . 05 V to 3 .3 V
R 14 5
0 . 1 uF n ea r th e ev e r y p o we r pi n
D
1 0 K _0 4
SMBus
CL K E N#
Q 12
R 14 2
M T N 7 00 2 Z H S 3
1 M_ 0 4
G
S
36
Q1 1 A
MT D N 7 00 2 Z H S 6 R
S
D
2
EMI
C L K _S C L K
C L K _S C L K 10 , 1 1
1
S MB _ C L K
6
15
G
3 .3 V S
X1
5 VS
4 R N1 5
3 2 . 2 K _ 4P 2 R _0 4
X IN
2
F S X8 L _ 14 . 3 1 81 8 MH z
1
X OU T
R E F _ 0 / C P U _S E L
C2 0 2
* 1 0p _ 50 V _ N P O _0 6
C L K _S D A T A
C L K _S D A T A 1 0, 1 1
C 2 07
C 20 8
3 3 p _5 0 V _ N P O_ 0 4
3 3 p_ 5 0 V _N P O_ 0 4
E M I C a p ac t i or
S
D
S MB _ D A T A
5
15
4
3
G
1
2
Q1 1 B
MT D N 7 00 2 Z H S 6 R
CPU_SEL_During
CK_PEWGD Latch Pinl
3 .3 VS
PI N _ 30
R1 3 2
* 4. 7 K _ 0 4
R1 3 3
1 0 K _0 4
C PU _ 0
C P U_ 1
0 ( de f a ul t )
1 33 M H z
1 3 3M H z
1 ( 0. 7 V -1 . 5 V)
1 00 M H z
1 0 0M H z
R E F _ 0/ C P U _ S E L
5 VS
13 , 1 7 , 20 , 2 1 , 26 , 2 7, 3 0 , 3 1, 3 5 , 3 6
3 .3 V
3, 4 , 1 2 , 14 , 1 5 , 16 , 1 8, 19 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 0, 3 1 , 33 , 3 4 , 35
3 .3 VS
10 , 1 1 , 12 , 1 3 , 14 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 2 5 , 26 , 2 7 , 28 , 2 9 , 30 , 3 1 , 35 , 3 6
1 . 1 V S _V TT 4 , 6, 7, 1 4 , 15 , 1 6 , 19 , 2 0 , 21 , 3 4 , 35 , 3 6
Clock Generator B - 3
Schematic Diagrams
Processor 1/7
PROCESSOR
1/7
( DMI,PEG,FDI )
U 16 A
It applies to Auburndale and Clarksfield discrete graphic designs.
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected
to GND if motherboard only supports discrete graphics and also in a common
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed,
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from
floating).
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale.
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and
D MI _ T X P 0
D MI _ T X P 1
D MI _ T X P 2
D MI _ T X P 3
16
16
16
16
D
D
D
D
MI _ R X N
MI _ R X N
MI _ R X N
MI _ R X N
16
16
16
16
D
D
D
D
MI _ R X P 0
MI _ R X P 1
MI _ R X P 2
MI _ R X P 3
16
16
16
16
16
16
16
16
FD
FD
FD
FD
FD
FD
FD
FD
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
16
16
16
16
16
16
16
16
FD
FD
FD
FD
FD
FD
FD
FD
I _ TX P 0
I _ TX P 1
I _ TX P 2
I _ TX P 3
I _ TX P 4
I _ TX P 5
I _ TX P 6
I _ TX P 7
D 24
G 24
F23
H 23
0
1
2
3
D 25
F24
E2 3
G 23
E2 2
D 21
D 19
D 18
G 21
E1 9
F21
G 18
0
1
2
3
4
5
6
7
D 22
C 21
D 20
C 18
G 22
E2 0
F20
G 19
16
16
F D I_ F S Y NC 0
F D I_ F S Y NC 1
16
F D I_ INT
16
16
F D I_ L S Y N C0
F D I_ L S Y N C1
F17
E1 7
C 17
F18
D 17
DM I_ RX [0 ]
DM I_ RX [1 ]
DM I_ RX [2 ]
DM I_ RX [3 ]
DM
DM
DM
DM
I _ TX # [ 0 ]
I _ TX # [ 1 ]
I _ TX # [ 2 ]
I _ TX # [ 3 ]
DM
DM
DM
DM
I _ TX [ 0 ]
I _ TX [ 1 ]
I _ TX [ 2 ]
I _ TX [ 3 ]
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_T X # [ 0 ]
_T X # [ 1 ]
_T X # [ 2 ]
_T X # [ 3 ]
_T X # [ 4 ]
_T X # [ 5 ]
_T X # [ 6 ]
_T X # [ 7 ]
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_T X [ 0 ]
_T X [ 1 ]
_T X [ 2 ]
_T X [ 3 ]
_T X [ 4 ]
_T X [ 5 ]
_T X [ 6 ]
_T X [ 7 ]
Intel(R) FDI
F D I _F S Y N C [ 0 ]
F D I _F S Y N C [ 1 ]
F D I _I N T
F D I _L S Y N C [ 0 ]
F D I _L S Y N C [ 1 ]
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common
motherboard design case. Please not that if these signals are left floating, there are no
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on Auburndale can be left as no connect.
P E G_ R X# [ 0 ]
P E G_ R X# [ 1 ]
P E G_ R X# [ 2 ]
P E G_ R X# [ 3 ]
P E G_ R X# [ 4 ]
P E G_ R X# [ 5 ]
P E G_ R X# [ 6 ]
P E G_ R X# [ 7 ]
P E G_ R X# [ 8 ]
P E G_ R X# [ 9 ]
P E G_ R X #[ 1 0 ]
P E G_ R X #[ 1 1 ]
P E G_ R X #[ 1 2 ]
P E G_ R X #[ 1 3 ]
P E G_ R X #[ 1 4 ]
P E G_ R X #[ 1 5 ]
P E G_ R X [ 0 ]
P E G_ R X [ 1 ]
P E G_ R X [ 2 ]
P E G_ R X [ 3 ]
P E G_ R X [ 4 ]
P E G_ R X [ 5 ]
P E G_ R X [ 6 ]
P E G_ R X [ 7 ]
P E G_ R X [ 8 ]
P E G_ R X [ 9 ]
P E G_ R X[ 1 0 ]
P E G_ R X[ 1 1 ]
P E G_ R X[ 1 2 ]
P E G_ R X[ 1 3 ]
P E G_ R X[ 1 4 ]
P E G_ R X[ 1 5 ]
P E G _ T X# [ 0 ]
P E G _ T X# [ 1 ]
P E G _ T X# [ 2 ]
P E G _ T X# [ 3 ]
P E G _ T X# [ 4 ]
P E G _ T X# [ 5 ]
P E G _ T X# [ 6 ]
P E G _ T X# [ 7 ]
P E G _ T X# [ 8 ]
P E G _ T X# [ 9 ]
P E G_ T X #[ 1 0 ]
P E G_ T X #[ 1 1 ]
P E G_ T X #[ 1 2 ]
P E G_ T X #[ 1 3 ]
P E G_ T X #[ 1 4 ]
P E G_ T X #[ 1 5 ]
P E G _ TX [ 0 ]
P E G _ TX [ 1 ]
P E G _ TX [ 2 ]
P E G _ TX [ 3 ]
P E G _ TX [ 4 ]
P E G _ TX [ 5 ]
P E G _ TX [ 6 ]
P E G _ TX [ 7 ]
P E G _ TX [ 8 ]
P E G _ TX [ 9 ]
P E G _ T X[ 1 0 ]
P E G _ T X[ 1 1 ]
P E G _ T X[ 1 2 ]
P E G _ T X[ 1 3 ]
P E G _ T X[ 1 4 ]
P E G _ T X[ 1 5 ]
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale
directly if motherboard only supports discrete graphics. In a common motherboard
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no
external termination is required.
On Board DDR3 Thermal Sensor
20 mil
B2 6
A2 6
B2 7
A2 5
P E G _I R C OM P _R
R 2 06
4 9 . 9 _ 1% _ 0 4
EX P _ RBIA S
R 2 05
7 5 0 _1 % _ 0 4
K3 5
J34
J33
G 35
G 32
F3 4
F3 1
D 35
E3 3
C 33
D 32
B3 2
C 31
B2 8
B3 0
A3 1
J35
H 34
H 33
F3 5
G 33
E3 4
F3 2
D 34
F3 3
B3 3
D 31
A3 2
C 30
A2 8
B2 9
A3 0
L33
M 35
M 33
M 30
L31
K3 2
M 29
J31
K2 9
H 30
H 29
F2 9
E2 8
D 29
D 27
C 26
L34
M 34
M 32
L30
M 31
K3 1
M 28
H 31
K2 8
G 30
G 29
F2 8
E2 7
D 28
C 27
C 25
P Z 9 8 9 27 -3 6 4 1- 01 F
3 .3 V
Analog Thermal Sensor
C 36 4
R2 2 5
*1 0 m i _l s h ort
3 . 3V
C R I T _T E M P _ R E P # 1 9
Q 16
2
* 0. 1 u _ 1 0V _X 5 R _ 0 4
U 18
C
1
2
D1 5
VDD
D+
T H ERM
A LE R T
DGN D
SD ATA
SC L K
4
6
C
* RB7 5 1 V
A
3
5
P M_ E X T T S #_ E C
4
*W 83 L 7 7 1A W G
B - 4 Processor 1/7
OU T
1
1:2 (4mils:8mils)
T H E R M _V OL T 2 8
4, 1 2 , 1 4 , 15 , 1 6 , 1 8 , 19 , 2 0 , 2 1, 23 , 2 4 , 2 5, 29 , 3 0 , 3 1, 3 3 , 3 4 , 3 5 3 . 3 V
C 3 66
3
0 . 1 u _ 10 V _ X 7 R _ 0 4
7
8
VC C
T H E R M_ A L E R T# 2 8
B
Q 10
*2 N 3 9 0 4
E
B.Schematic Diagrams
Sheet 3 of 40
Processor 1/7
B2 4
D 23
B2 3
A2 2
P E G_ I C OM P I
P E G_ I C O MP O
P E G _R C O MP O
P E G_ R B I A S
DM I_ RX # [0 ]
DM I_ RX # [1 ]
DM I_ RX # [2 ]
DM I_ RX # [3 ]
DMI
16
16
16
16
A2 4
C 23
B2 2
A2 1
D MI _ T X N 0
D MI _ T X N 1
D MI _ T X N 2
D MI _ T X N 3
PCI EXPRESS -- GRAPHICS
16
16
16
16
S MD _ C P U _T H E R M
S MC _ C P U _T H E R M
GN D
G7 1 1 S T 9U
C3 6 7
0 . 1u _ 1 0 V _ X7 R _0 4
1 5 , 28
1 5 , 28
PLACE NEAR U3
1
2
3
Schematic Diagrams
Processor 2/7
PROCESSOR
2/7
( CLK,MISC,JTAG )
1 .5 V
Processor Compensation
Signals
4 9 . 9 _ 1% _ 0 4
H _C OM P 0
R2 1 2
4 9 . 9 _ 1% _ 0 4
H _C OM P 1
R2 3 4
2 0 _ 1 %_ 0 4
H _C OM P 2
R2 3 3
2 0 _ 1 %_ 0 4
H _C OM P 3
R 20 0
* 1K _0 4
R 2 01
DDR3 Compensation Signals
S M _R C O MP _ 0
R2 2 6
1 0 0 _ 1% _ 0 4
S M _R C O MP _ 1
R2 2 7
2 4 . 9 _ 1% _ 0 4
S M _R C O MP _ 2
R2 2 8
1 3 0 _ 1% _ 0 4
0_04
BSS138 ( VGS 1.5V )
Q 15
* R J U 00 3 N 0 3 T 1 06
S
D
S M _D R A M R S T#
R 2 02
* 10 0 K _ 0 4
D D R 3 _ D R A MR S T # 1 0, 1 1
G
R2 3 6
D R A MR S T _C T R L 9 , 1 9
TRACE WIDTH 10MIL, LENGTH <500MILS
? ? IBEX CONTROL
C3 1 8
68_04
R2 4 5
* 6 8_ 0 4
H _C P U R S T #
AT2 6
A H2 4
H _ C A TE R R #
3 6 H _ P R OC H O T #
C O MP 0
S K T OC C #
C A TE R R #
AT1 5
1 9 ,2 8 H _ P E CI
R2 4 6
AK1 4
C O MP 1
PEC I
0 _0 4
H _ P R OC H O T# _ D
A N2 6
P R OC H OT #
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
AK1 5
1 9 H _ TH R M T R I P #
B CL K
B CL K #
CLOCKS
R2 3 7
H _P R OC H O T #_ D
G1 6
H _ C O MP 0
C O MP 2
B CL K _ IT P
B C LK _I T P #
P E G _ CL K
P E G_ C L K #
D P LL _ R E F _S S C L K
D P L L_ R E F _ S S C L K #
S M_ D R A M R S T #
DDR3
MISC
H _C A T E R R #
H _ C O MP 1
C O MP 3
THERMAL
4 9 . 9 _ 1% _ 0 4
R2 1 6
AT2 4
MISC
Processor Pullups
1 .1 V S _ V T T
AT2 3
H _ C O MP 2
S M_ R C O MP [ 0 ]
S M_ R C O MP [ 1 ]
S M_ R C O MP [ 2 ]
P M_ E X T _T S # [ 0 ]
P M_ E X T _T S # [ 1 ]
* 1 0m i l _s h o rt
A N2 7
1 9 H _ C P U P W R GD
R 52
1 6 P M _ D R A M_ P W R GD
V C C P W R GO OD _ 1
* 1 0m i l _s h o rt
V D D P W R GO OD _R
V C C P W R GO OD _ 0
AK1 3
S M _D R A M P W R OK
A M1 5
1 6 H _ V T TP W R G D
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
R 60
1 8 , 2 3, 2 5 , 2 8 B U F _P L T _ R S T #
H _ P W R GD _ XD P
1 . 5 K _ 1% _ 0 4
P L T_ R S T #_ R
A M2 6
V T T P W R G OO D
T A P P W R GO OD
TC K
TM S
T RS T #
JTAG & BPM
S Y S _ A G E N T _ P W R OK A N 1 4
PWR MANAGEMENT
P M _S Y N C
*0 _ 0 4
R 24 8
R E S E T _O B S #
AL 1 5
1 6 H _ P M_ S Y N C
R 24 7
1 6 , 3 6 D E L A Y _ P W R GD
AP2 6
B C L K _C P U _P
B C L K _C P U _N
19
19
AR 3 0
AT3 0
E1 6
D 16
C LK _E X P _ P 1 5
C LK _E X P _ N 1 5
A1 8
A1 7
C LK _D P _ P 1 5
C LK _D P _ N 1 5
Sheet 4 of 40
Processor 2/7
F6
S M_ D R A M R S T #
AL 1
AM 1
AN 1
S M_ R C O MP _ 0
S M_ R C O MP _ 1
S M_ R C O MP _ 2
R 2 30
R 54
1 0 K _ 04
1 0 K _ 04
AN 1 5
A P 15
P M_ E X T T S #[ 0]
P M_ E X T T S #[ 1]
R 53
R 2 29
* 0_ 0 4
* 0_ 0 4
R 2 31
* 12 . 4 K _ 1 % _0 4
R
R
R
R
R
2 50
2 42
2 49
2 40
2 39
* 51 _ 0 4
5 1 _ 04
* 51 _ 0 4
* 51 _ 0 4
* 51 _ 0 4
X D P _T C LK
X D P _T R S T #
R 2 43
R 2 38
* 51 _ 0 4
5 1 _ 04
X D P _T D O_ M
R 2 41
*1 0 mi l _ sh o rt
1 .1 V S _ V T T
T H E R MT R I P #
P RD Y #
P R E Q#
H _ C P U R S T#
A1 6
B1 6
TD I
TD O
T D I_ M
T DO _ M
D B R#
B P M# [ 0 ]
B P M# [ 1 ]
B P M# [ 2 ]
B P M# [ 3 ]
B P M# [ 4 ]
B P M# [ 5 ]
B P M# [ 6 ]
B P M# [ 7 ]
AT2 8
A P 27
XD P _ P R E Q#
AN 2 8
A P 28
AT2 7
XD P _ T C L K
XD P _ T MS
XD P _ T R S T #
AT2 9
AR 2 7
AR 2 9
A P 29
XD
XD
XD
XD
AN 2 5
AJ 2 2
A K 22
A K 24
AJ 2 4
AJ 2 5
AH 2 2
A K 23
AH 2 3
P _ T DI_ R
P _ T D O _R
P _ T DI_ M
P _ T D O _M
P M_ E X T T S # _E C 3
T S #_ D I MM 0 _1 1 0 , 1 1
1 .1 V S _ V T T
X DP
X DP
X DP
X DP
X DP
_T M S
_T D O_ M
_T D I _R
_P R E Q #
_T D O_ R
AL 1 4
R S TI N #
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
R6 1
7 50 _ 1 % _0 4
P Z 9 8 9 2 7-3 6 4 1- 01 F
XD P _ T D I _ M
1 .5 V S _ CP U
3 .3 V
R 50
1 . 1 K _ 1% _ 0 4
R2 3 2
* 8 . 2K _ 0 4
3 .3 V
3, 12 , 1 4 , 1 5, 1 6 , 1 8 , 19 , 2 0 , 2 1, 2 3 , 2 4 , 25 , 2 9 , 3 0, 31 , 3 3 , 3 4, 3 5
1 .5 V
9, 10 , 1 1 , 2 1, 2 3 , 2 7 , 29 , 3 1 , 3 3, 3 6
1 .5 V S _ C P U 7 ,3 1
1 . 1 V S _ V T T 2 , 6 , 7, 1 4 , 1 5 , 16 , 1 9 , 2 0, 21 , 3 4 , 3 5, 3 6
U1 7
5
V D D P W R G OO D _ R
1
R 62
R2 4 4
* 1 . 5K _ 1 % _ 04
D R A MP W R G D _ C P U
IN3 .3 V
4
2
3
3 K _ 1% _ 0 4
1 . 1 V S _ V T T _P W R G D 1 6 , 3 3, 3 4
*M C 7 4 V H C 1 G0 8 D F T 1 G
Intel change
4.75K -->1.1K
12K -->3K
Processor 2/7 B - 5
B.Schematic Diagrams
*4 7 n_ 5 0 V _ 04
U 16 B
H _ C O MP 3
Schematic Diagrams
Processor 3/7
PROCESSOR
3/7
( DDR3 )
U16C
U16D
Sheet 5 of 40
Processor 3/7
10
10
10
M_A_BS0
M_A_BS1
M_A_BS2
10
10
10
M_A_CAS#
M_A_RAS#
M_A_WE#
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
AC3
AB2
U7
AE1
AB3
AE9
SA_DQ
[0]
SA_DQ
[1]
SA_DQ
[2]
SA_DQ
[3]
SA_DQ
[4]
SA_DQ
[5]
SA_DQ
[6]
SA_DQ
[7]
SA_DQ
[8]
SA_DQ
[9]
SA_DQ
[10]
SA_DQ
[11]
SA_DQ
[12]
SA_DQ
[13]
SA_DQ
[14]
SA_DQ
[15]
SA_DQ
[16]
SA_DQ
[17]
SA_DQ
[18]
SA_DQ
[19]
SA_DQ
[20]
SA_DQ
[21]
SA_DQ
[22]
SA_DQ
[23]
SA_DQ
[24]
SA_DQ
[25]
SA_DQ
[26]
SA_DQ
[27]
SA_DQ
[28]
SA_DQ
[29]
SA_DQ
[30]
SA_DQ
[31]
SA_DQ
[32]
SA_DQ
[33]
SA_DQ
[34]
SA_DQ
[35]
SA_DQ
[36]
SA_DQ
[37]
SA_DQ
[38]
SA_DQ
[39]
SA_DQ
[40]
SA_DQ
[41]
SA_DQ
[42]
SA_DQ
[43]
SA_DQ
[44]
SA_DQ
[45]
SA_DQ
[46]
SA_DQ
[47]
SA_DQ
[48]
SA_DQ
[49]
SA_DQ
[50]
SA_DQ
[51]
SA_DQ
[52]
SA_DQ
[53]
SA_DQ
[54]
SA_DQ
[55]
SA_DQ
[56]
SA_DQ
[57]
SA_DQ
[58]
SA_DQ
[59]
SA_DQ
[60]
SA_DQ
[61]
SA_DQ
[62]
SA_DQ
[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM
[0]
SA_DM
[1]
SA_DM
[2]
SA_DM
[3]
SA_DM
[4]
SA_DM
[5]
SA_DM
[6]
SA_DM
[7]
DDR SY STEM MEM ORY A
B.Schematic Diagrams
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_
DQS[0]
SA_
DQS[1]
SA_
DQS[2]
SA_
DQS[3]
SA_
DQS[4]
SA_
DQS[5]
SA_
DQS[6]
SA_
DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
AA7
P7
Y6
Y5
P6
M_CLK_DDR0 10
M_CLK_DDR#0 10
M_CKE0 1
0
11 M_B_DQ
[ 63:0]
M_B_DQ
0
M_B_DQ
1
M_B_DQ
2
M_B_DQ
3
M_B_DQ
4
M_B_DQ
5
M_B_DQ
6
M_B_DQ
7
M_B_DQ
8
M_B_DQ
9
M_B_DQ
10
M_B_DQ
11
M_B_DQ
12
M_B_DQ
13
M_B_DQ
14
M_B_DQ
15
M_B_DQ
16
M_B_DQ
17
M_B_DQ
18
M_B_DQ
19
M_B_DQ
20
M_B_DQ
21
M_B_DQ
22
M_B_DQ
23
M_B_DQ
24
M_B_DQ
25
M_B_DQ
26
M_B_DQ
27
M_B_DQ
28
M_B_DQ
29
M_B_DQ
30
M_B_DQ
31
M_B_DQ
32
M_B_DQ
33
M_B_DQ
34
M_B_DQ
35
M_B_DQ
36
M_B_DQ
37
M_B_DQ
38
M_B_DQ
39
M_B_DQ
40
M_B_DQ
41
M_B_DQ
42
M_B_DQ
43
M_B_DQ
44
M_B_DQ
45
M_B_DQ
46
M_B_DQ
47
M_B_DQ
48
M_B_DQ
49
M_B_DQ
50
M_B_DQ
51
M_B_DQ
52
M_B_DQ
53
M_B_DQ
54
M_B_DQ
55
M_B_DQ
56
M_B_DQ
57
M_B_DQ
58
M_B_DQ
59
M_B_DQ
60
M_B_DQ
61
M_B_DQ
62
M_B_DQ
63
M_CLK_DDR1 10
M_CLK_DDR#1 10
M_CKE1 1
0
AE2
AE8
M_CS#0 10
M_CS#1 10
AD8
AF9
M_ODT0 1
0
M_ODT1 1
0
B9
D7
H7
M7
AG6
AM7
AN10
AN13
M
_A_
DM0
M
_A_
DM1
M
_A_
DM2
M
_A_
DM3
M
_A_
DM4
M
_A_
DM5
M
_A_
DM6
M
_A_
DM7
C9
F8
J9
N9
AH7
AK9
AP11
AT13
M
_A_
DQS#0
M
_A_
DQS#1
M
_A_
DQS#2
M
_A_
DQS#3
M
_A_
DQS#4
M
_A_
DQS#5
M
_A_
DQS#6
M
_A_
DQS#7
C8
F9
H9
M9
AH8
AK10
AN11
AR13
M
_A_
DQS0
M
_A_
DQS1
M
_A_
DQS2
M
_A_
DQS3
M
_A_
DQS4
M
_A_
DQS5
M
_A_
DQS6
M
_A_
DQS7
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M
_A_
A0
M
_A_
A1
M
_A_
A2
M
_A_
A3
M
_A_
A4
M
_A_
A5
M
_A_
A6
M
_A_
A7
M
_A_
A8
M
_A_
A9
M
_A_
A10
M
_A_
A11
M
_A_
A12
M
_A_
A13
M
_A_
A14
M
_A_
A15
M_A_DM
[7: 0
] 10
M_A_DQS#
[ 7:0] 10
M_A_DQS[7:0] 10
M_A_A[15:0] 10
11
11
11
M_B_BS0
M_B_BS1
M_B_BS2
11
11
11
M_B_CAS#
M_B_RAS#
M_B_WE#
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G
4
H6
G
2
J6
J3
G
1
G
5
J2
J1
J5
K2
L
3
M
1
K5
K4
M
4
N5
AF3
AG
1
AJ3
AK1
AG
4
AG
3
AJ4
AH4
AK3
AK4
AM
6
AN2
AK5
AK2
AM
4
AM
3
AP3
AN5
AT
4
AN6
AN4
AN3
AT
5
AT
6
AN7
AP6
AP8
AT
9
AT
7
AP9
AR1
0
AT1
0
AB1
W5
R7
AC5
Y7
AC6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
PZ98927-3641-01F
PZ9892
7- 36
41-01F
B - 6 Processor 3/7
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_O
DT[0]
SB_O
DT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
DDR SYS TEM MEMO RY - B
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
10 M_A_DQ[63:0]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
W8
W9
M3
V7
V6
M2
M_CLK_DDR2 11
M_CLK_DDR#2 11
M_CKE2 11
M_CLK_DDR3 11
M_CLK_DDR#3 11
M_CKE3 11
AB8
AD6
M_CS#2 11
M_CS#3 11
AC7
AD1
M_O
DT2 11
M_O
DT3 11
M
_B_DM[7:0] 11
D4
E1
H3
K1
AH1
AL2
AR4
AT8
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
D5
F4
J4
L4
AH2
AL4
AR5
AR8
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M
_B_
DQS#[7:0] 11
C5
E3
H4
M5
AG2
AL5
AP5
AR7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M
_B_
DQS[7:0] 11
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M
_B_A[15:0] 1
1
Schematic Diagrams
Processor 4/7
PROCESSOR
4/7
( POWER )
U1 6 F
P ROCESSOR CORE POWE R
*2 2 u _ 6. 3V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 08
C3 3 9
C3 6 3
C3 6 2
C3 6 1
*2 2 u _ 6. 3V _ X 5 R _ 0 8
*2 2 u _ 6. 3V _ X 5 R _ 0 8
C3 5 5
C3 5 3
C3 5 2
C3 5 1
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6
*1 0 u _ 6. 3V _ X 5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 06
V CO R E
10 u _ 6 . 3 V _ X 5 R _ 06
C3 4 6
C3 4 5
C3 4 0
10 u _ 6 . 3 V _ X 5 R _ 06
*1 0 u _ 6. 3V _ X 5 R _ 0 6
C3 4 7
0. 01 u _ 5 0 V _ X 7 R _ 04
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C3 5 4
*1 0 u _ 6. 3V _ X 5 R _ 0 6
C3 3 4
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C3 3 2
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C3 3 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VTT0 _ 1
VTT0 _ 2
VTT0 _ 3
VTT0 _ 4
VTT0 _ 5
VTT0 _ 6
VTT0 _ 7
VTT0 _ 8
VTT0 _ 9
VT T 0 _ 1 0
VT T 0 _ 1 1
VT T 0 _ 1 2
VT T 0 _ 1 3
VT T 0 _ 1 4
VT T 0 _ 1 5
VT T 0 _ 1 6
VT T 0 _ 1 7
VT T 0 _ 1 8
VT T 0 _ 1 9
VT T 0 _ 2 0
VT T 0 _ 2 1
VT T 0 _ 2 2
VT T 0 _ 2 3
VT T 0 _ 2 4
VT T 0 _ 2 5
VT T 0 _ 2 6
VT T 0 _ 2 7
VT T 0 _ 2 8
VT T 0 _ 2 9
VT T 0 _ 3 0
VT T 0 _ 3 1
VT T 0 _ 3 2
VTT T OTAL 21A
AH 1 4
AH 1 2
AH 1 1
AH 1 0
J14
J13
H 14
H 12
G 14
G 13
G 12
G 11
F14
F13
F12
F11
E1 4
E1 2
D 14
D 13
D 12
D 11
C 14
C 13
C 12
C 11
B1 4
B1 2
A1 4
A1 3
A1 2
A1 1
C 28
C2 9
C 331
C 34
C 32
C3 0 8
C 341
1 0 u _ 6. 3V _ X5 R _ 0 6
*1 0 u _ 6 . 3 V _ X 5R _ 0 6
1 0 u _ 6 .3 V_ X 5 R_ 0 6
* 10 u _ 6 . 3 V _ X 5 R _ 0 6
* 1 0 u _6 . 3 V _X 5 R _ 06
2 2 u_ 6 . 3 V _ X 5 R _ 08
2 2 u _ 6 . 3 V _ X 5R _ 0 8
C 36
C3 1 0
C 33
C 335
1 0 u _ 6. 3V _ X5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6
1 0 u _6 . 3 V _ X 5 R _ 06
* 1 0 u_ 6 . 3 V _ X 5 R _0 6
A F 10
A E 10
AC 1 0
A B 10
Y 10
W 10
U 10
T10
J12
J11
J16
J15
ICCMAX_VTT Max Current
for VTT Rail
SV 18
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide
1 .1 VS _ V T T
VT T 0 _ 3 3
VT T 0 _ 3 4
VT T 0 _ 3 5
VT T 0 _ 3 6
VT T 0 _ 3 7
VT T 0 _ 3 8
VT T 0 _ 3 9
VT T 0 _ 4 0
VT T 0 _ 4 1
VT T 0 _ 4 2
VT T 0 _ 4 3
VT T 0 _ 4 4
CPU CORE SUPPLY
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C3 2 5
*2 2 u _ 6 . 3 V _ X 5 R _ 0 8
C3 3 6
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C3 5 9
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C3 4 9
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
C 311
C3 1 2
C 319
2 2 u _ 6 .3 V _ X 5 R_ 0 8
2 2u _ 6 . 3 V _ X 5 R _0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
Sheet 6 of 40
Processor 4/7
1.1VS_VTT
+ V T T _4 3
+ V T T _4 4
R 209
R 211
Please note that the
VTT Rail Values are
*1 0 m i _l s h o rt _ 0 4
*1 0 m i _l s h o rt _ 0 4
Auburndale VTT=1.05V
1 . 1 V S _ V TT
1K PU t o V TT an d 1 K P D t o GN D
fo r P OC
VCORE
R 222
* 1 K_ 0 4
AN 3 3
PSI #
A K 35
A K 33
A K 34
AL 3 5
AL 3 3
AM 3 3
AM 3 5
AM 3 4
H
H
H
H
H
H
H
P S I#
P S I#
36
1 .1 V S_ V T T
V ID [0 ]
V ID [1 ]
V ID [2 ]
V ID [3 ]
V ID [4 ]
V ID [5 ]
V ID [6 ]
P R OC _ D P R S L P V R
_V
_V
_V
_V
_V
_V
_V
ID0
ID1
ID2
ID3
ID4
ID5
ID6
R 223
36
36
36
36
36
36
36
1 K _0 4
R 220
1 K_ 0 4
P M _D P R S L P V R
36
R 219
VT T _ SEL EC T
G 15
H _V T TV I D 1
* 1 K_ 0 4
TO VCORE POWER CONTROL
AN 3 5
IS E NS E
V C C_ S E NS E
V S S _ S E NS E
V T T _ S E NS E
V S S _ S E NS E _ V T T
AJ 3 4
AJ 3 5
B1 5
A1 5
IM O N
36
VC C _ SEN SE 3 6
V S S _ S E N S E 36
V T T _ S E NSE
34
V CO RE
36
1 . 1 V S _ V T T 2 , 4 , 7 , 1 4, 15 , 1 6 , 1 9 , 2 0 , 2 1 , 3 4 , 3 5, 36
P Z 9 8 9 2 7- 36 4 1 -0 1 F
Processor 4/7 B - 7
B.Schematic Diagrams
22 u _ 6 . 3 V _ X 5 R _ 08
C3 4 4
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C3 4 2
*2 2 u _ 6. 3V _ X 5 R _ 0 8
C3 3 8
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C3 3 0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1.1V RAIL POWER
V CO R E
1 .1 V S _ V T T
A G3 5
A G3 4
A G3 3
A G3 2
A G3 1
A G3 0
A G2 9
A G2 8
A G2 7
A G2 6
AF3 5
AF3 4
AF3 3
AF3 2
AF3 1
AF3 0
AF2 9
AF2 8
AF2 7
AF2 6
A D3 5
A D3 4
A D3 3
A D3 2
A D3 1
A D3 0
A D2 9
A D2 8
A D2 7
A D2 6
A C3 5
A C3 4
A C3 3
A C3 2
A C3 1
A C3 0
A C2 9
A C2 8
A C2 7
A C2 6
AA3 5
AA3 4
AA3 3
AA3 2
AA3 1
AA3 0
AA2 9
AA2 8
AA2 7
AA2 6
Y3 5
Y3 4
Y3 3
Y3 2
Y3 1
Y3 0
Y2 9
Y2 8
Y2 7
Y2 6
V3 5
V3 4
V3 3
V3 2
V3 1
V3 0
V2 9
V2 8
V2 7
V2 6
U3 5
U3 4
U3 3
U3 2
U3 1
U3 0
U2 9
U2 8
U2 7
U2 6
R3 5
R3 4
R3 3
R3 2
R3 1
R3 0
R2 9
R2 8
R2 7
R2 6
P3 5
P3 4
P3 3
P3 2
P3 1
P3 0
P2 9
P2 8
P2 7
P2 6
POWER
S V 48
CPU VIDS
I C CM AX Ma xi m um Pr oc e ss or
PROCE SSOR UNCO RE POWER
48A
SENSE LINES
VCO R E
Schematic Diagrams
Processor 5/7
PROCESSOR
( GRAPHICS POWER )
C 369
22 u _ 6 . 3 V _ X 5 R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
C 37 1
+
2 2 0 u_ 4 V _ V _ A
Sheet 7 of 40
Processor 5/7
Please note that the
VTT Rail Values are
Auburndale VTT=1.05V
Clarksfield VTT=1.1V
C 32 1
C 3 15
2 2 u _6 . 3 V _ X 5 R _0 8
2 2 u _ 6. 3V _X 5 R _ 08
J 24
J 23
H 25
V T T 1_ 4 5
V T T 1_ 4 6
V T T 1_ 4 7
VAXG _ SEN SE
VSSAXG _ SEN SE
GF
GF
GF
GF
GF
GF
GF
X_ V I
X_ V I
X_ V I
X_ V I
X_ V I
X_ V I
X_ V I
D[0 ]
D[1 ]
D[2 ]
D[3 ]
D[4 ]
D[5 ]
D[6 ]
G F X _ V R _E N
G F X _ DP RS L P V R
GF X_ I M O N
A R 22
AT 2 2
G P U V C C S E N S E 35
G P UV S S S E NS E 3 5
A M 22
AP2 2
A N 22
AP2 3
A M 23
AP2 4
A N 24
D
D
D
D
D
D
D
A R 25
AT 2 5
A M 24
F GT _ V I D
F GT _ V I D
F GT _ V I D
F GT _ V I D
F GT _ V I D
F GT _ V I D
F GT _ V I D
GF XV R _ D P R S L P V R
T P _ GF X_ I M O N
_0
_1
_2
_3
_4
_5
_6
35
35
35
35
35
35
35
D F G T _ VR_ EN
R2 3 5
R4 5
* 1K _ 04
1 0 0 _ 1% _ 0 4
G F X _ I M ON
1 .1 VS _ VT T
35
35
1 . 5 V S _C P U
VDDQ 6A
FDI
1 .1 VS _ VT T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GRAPHICS VIDs
C3 5 7
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
- 1.5V RAILS
1 0 u _ 6 . 3 V _ X 5R _ 0 6
DDR3
C 356
10 u _ 6 . 3 V _ X 5 R _ 0 6
POWER
C3 7 3
SENSE
LINES
U1 6 G
A T 21
A T 19
A T 18
A T 16
A R 21
A R 19
A R 18
A R 16
A P 21
A P 19
A P 18
A P 16
A N 21
A N 19
A N 18
A N 16
A M 21
A M 19
A M 18
A M 16
A L 21
A L 19
A L 18
A L 16
A K 21
A K 19
A K 18
A K 16
A J 21
A J 19
A J 18
A J 16
A H 21
A H 19
A H 18
A H 16
GRAPHICS
V D D Q1
V D D Q2
V D D Q3
V D D Q4
V D D Q5
V D D Q6
V D D Q7
V D D Q8
V D D Q9
V D D Q 10
V D D Q 11
V D D Q 12
V D D Q 13
V D D Q 14
V D D Q 15
V D D Q 16
V D D Q 17
V D D Q 18
V T T 0 _ 59
V T T 0 _ 60
V T T 0 _ 61
V T T 0 _ 62
AJ 1
AF 1
AE7
AE4
AC 1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
C4 5
C 343
C3 3 7
C 58
C5 1
1 u _6 . 3 V _ X 5 R _ 04
2 2 u _ 6 . 3 V _ X5 R _ 0 8
2 2u _ 6 . 3 V _ X 5 R _ 0 8
1 0 u _ 6. 3V _X 5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6
C3 4 8
C 350
C3 9
C 57
1 u _6 . 3 V _ X 5 R _ 04
1 u _ 6 . 3 V _ X 5R _ 0 4
1 u_ 6 . 3 V _ X 5 R _0 4
1 u _ 6 . 3 V _ X5 R _ 0 4
C3 2 8
C 65
1 0 u_ 6 . 3 V _ X 5 R _0 6
1 0 u _ 6 . 3 V _ X5 R _ 0 6
+C 4 3
1 0 0 u _ 6. 3V _ B _ A
1 .1 VS _ VT T
P1 0
N1 0
L 10
K1 0
C 3 14
2 2 u _6 . 3 V _ X 5 R _0 8
2 2 u _ 6. 3V _X 5 R _ 08
C 31 6
C 3 09
C4 0 3
0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
C3 5 8
0 . 0 1u _ 5 0 V _ X 7 R _ 0 4
2 2 u _6 . 3 V _ X 5 R _0 8
2 2 u _ 6. 3V _X 5 R _ 08
V T T 1_ 4 8
V T T 1_ 4 9
V T T 1_ 5 0
V T T 1_ 5 1
V T T 1_ 5 2
V T T 1_ 5 3
V T T 1_ 5 4
V T T 1_ 5 5
V T T 1_ 5 6
V T T 1_ 5 7
V T T 1_ 5 8
PEG & DMI
C 31 3
1 .1 V S _ V T T
K 26
J 27
J 26
J 25
H 27
G 28
G 27
G 26
F 26
E 26
E 25
1.1V
1 .1 V S_ V T T
1 .1 VS _ VT T
V T T 1 _ 63
V T T 1 _ 64
V T T 1 _ 65
V T T 1 _ 66
V T T 1 _ 67
V T T 1 _ 68
J 22
J 20
J 18
H2 1
H2 0
H1 9
C3 2 2
C 320
2 2 u_ 6 . 3 V _ X 5 R _0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
1 .8 V S
1.8V
B.Schematic Diagrams
V G F X _ CO R E
5/7
V C C P L L1
V C C P L L2
V C C P L L3
L 26
L 27
M2 6
VCCPLL 0.6A
C4 1
C 37
C3 8
C4 2
C 46
C 44
1 u _6 . 3 V _ X 5 R _ 04
1 u _ 6 . 3 V _ X 5R _ 0 4
2 . 2 u_ 1 6 V _ X 5 R _ 0 6
4 . 7 u _6 . 3 V _ X 5 R _0 6
1 0 u _6 . 3 V _X 5 R _ 06
1 0 u _ 6 .3 V _ X 5 R_ 0 6
P Z 9 8 9 2 7 -3 64 1 -0 1 F
1 .5 V S _ C P U 4 ,3 1
1 .8 V S
20 , 3 3
VG F X_ CO R E 3 5
1 . 1 V S _ V T T 2 , 4 , 6 , 1 4 , 1 5 , 1 6 , 1 9, 20 , 2 1 , 3 4 , 3 5 , 3 6
1 .5 V
4, 9, 10 , 1 1 , 2 1 , 2 3 , 2 7 , 2 9, 31 , 3 3 , 3 6
B - 8 Processor 5/7
Schematic Diagrams
Processor 6/7
PROCESSOR
6/7
( GND )
PZ98 92 7- 364 1- 01F
U1 6I
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS1 00
VSS1 01
VSS1 02
VSS1 03
VSS1 04
VSS1 05
VSS1 06
VSS1 07
VSS1 08
VSS1 09
VSS1 10
VSS1 11
VSS1 12
VSS1 13
VSS1 14
VSS1 15
VSS1 16
VSS1 17
VSS1 18
VSS1 19
VSS1 20
VSS1 21
VSS1 22
VSS1 23
VSS1 24
VSS1 25
VSS1 26
VSS1 27
VSS1 28
VSS1 29
VSS1 30
VSS1 31
VSS1 32
VSS1 33
VSS1 34
VSS1 35
VSS1 36
VSS1 37
VSS1 38
VSS1 39
VSS1 40
VSS1 41
VSS1 42
VSS1 43
VSS1 44
VSS1 45
VSS1 46
VSS1 47
VSS1 48
VSS1 49
VSS1 50
VSS1 51
VSS1 52
VSS1 53
VSS1 54
VSS1 55
VSS1 56
VSS1 57
VSS1 58
VSS1 59
VSS1 60
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD1 0
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W3 5
W3 4
W3 3
W3 2
W3 1
W3 0
W2 9
W2 8
W2 7
W2 6
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R 10
P8
P4
P2
N 35
N 34
N 33
N 32
N 31
N 30
N 29
N 28
N 27
N 26
N6
M10
L 35
L 32
L 29
L8
L5
L2
K34
K33
K30
K27
K9
K6
K3
J 32
J 30
J 21
J 19
H 35
H 32
H 28
H 26
H 24
H 22
H 18
H 15
H 13
H 11
H8
H5
H2
G 34
G 31
G 20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D 33
D 30
D 26
D9
D6
D3
C 34
C 32
C 29
C 28
C 24
C 22
C 20
C 19
C 16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
VSS16 1
VSS16 2
VSS16 3
VSS16 4
VSS16 5
VSS16 6
VSS16 7
VSS16 8
VSS16 9
VSS17 0
VSS17 1
VSS17 2
VSS17 3
VSS17 4
VSS17 5
VSS17 6
VSS17 7
VSS17 8
VSS17 9
VSS18 0
VSS18 1
VSS18 2
VSS18 3
VSS18 4
VSS18 5
VSS18 6
VSS18 7
VSS18 8
VSS18 9
VSS19 0
VSS19 1
VSS19 2
VSS19 3
VSS19 4
VSS19 5
VSS19 6
VSS19 7
VSS19 8
VSS19 9
VSS20 0
VSS20 1
VSS20 2
VSS20 3
VSS20 4
VSS20 5
VSS20 6
VSS20 7
VSS20 8
VSS20 9
VSS21 0
VSS21 1
VSS21 2
VSS21 3
VSS21 4
VSS21 5
VSS21 6
VSS21 7
VSS21 8
VSS21 9
VSS22 0
VSS22 1
VSS22 2
VSS22 3
VSS22 4
VSS22 5
VSS22 6
VSS22 7
VSS22 8
VSS22 9
VSS23 0
VSS23 1
VSS23 2
VSS23 3
Sheet 8 of 40
Processor 6/7
VSS
VSS_N CTF1
VSS_N CTF2
VSS_N CTF3
VSS_N CTF4
VSS_N CTF5
VSS_N CTF6
VSS_N CTF7
AT35
AT1
AR34
B34
B2
B1
A35
PZ989 27 -36 41 -01 F
Processor 6/7 B - 9
B.Schematic Diagrams
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
VSS5 3
VSS5 4
VSS5 5
VSS5 6
VSS5 7
VSS5 8
VSS5 9
VSS6 0
VSS6 1
VSS6 2
VSS6 3
VSS6 4
VSS6 5
VSS6 6
VSS6 7
VSS6 8
VSS6 9
VSS7 0
VSS7 1
VSS7 2
VSS7 3
VSS7 4
VSS7 5
VSS7 6
VSS7 7
VSS7 8
VSS7 9
VSS8 0
NCTF
U 16H
AT2 0
AT1 7
AR3 1
AR2 8
AR2 6
AR2 4
AR2 3
AR2 0
AR1 7
AR1 5
AR1 2
AR 9
AR 6
AR 3
AP2 0
AP1 7
AP1 3
AP1 0
AP7
AP4
AP2
AN3 4
AN3 1
AN2 3
AN2 0
AN1 7
AM2 9
AM2 7
AM2 5
AM2 0
AM1 7
AM1 4
AM1 1
AM8
AM5
AM2
AL3 4
AL3 1
AL2 3
AL2 0
AL1 7
AL1 2
AL 9
AL 6
AL 3
AK2 9
AK2 7
AK2 5
AK2 0
AK1 7
AJ3 1
AJ2 3
AJ2 0
AJ1 7
AJ1 4
AJ1 1
AJ 8
AJ 5
AJ 2
AH3 5
AH3 4
AH3 3
AH3 2
AH3 1
AH3 0
AH2 9
AH2 8
AH2 7
AH2 6
AH2 0
AH1 7
AH1 3
AH 9
AH 6
AH 3
AG1 0
AF8
AF4
AF2
AE3 5
Schematic Diagrams
Processor 7/7
PROCESSOR
7/7
( RESERVED )
1 .5 V
U 16E
AP2302GN
Sheet 9 of 40
Processor 7/7
R 2 24
* 3 . 0 1K _0 4
R3 5
R3 9
1 0 M V R E F _ D Q _D I M 0
1 1 M V R E F _ D Q _D I M 1
* 0 _0 4
* 0 _0 4
V R E F _ CH _ A _ DIM M
V R E F _ CH _ B _ DIM M
CFG3 - PCI-Express Static Lane Reversal
1 : Normal Operation
0 : Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R S V D 34
R S V D 35
R S V D 36
R S V D _ N C T F _ 37
R S V D 38
R S V D 39
R 2 18
R S V D _ N C T F _ 40
R S V D _ N C T F _ 41
R S V D _ N C T F _ 42
R S V D _ N C T F _ 43
* 3 . 0 1K _0 4
C F G0
C F G3
C F G4
C F G7
1 : Di sa b ll ed ; No p h ys ic al D is p la y Po rt
a tt ac he d t o Em be dd e d Di sp la y P or t
0 : En ab l ed ; An e xt e rn al D is pl a y Po rt
de vi ce i s c on ne ct ed to t he E mb e dd ed
is pl ay P o rt
? ?? ? ,? ?? ?
CF G 4
R 2 17
* 3 . 0 1K _0 4
R 20 8
* 0 _ 04
RS V D8 6
A M3 0
A M2 8
AP3 1
AL 3 2
AL 3 0
A M3 1
A N2 9
A M3 2
AK3 2
AK3 1
AK2 8
AJ 2 8
A N3 0
A N3 2
AJ 3 2
AJ 2 9
AJ 3 0
AK3 0
H1 6
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
R
F G [ 0]
F G [ 1]
F G [ 2]
F G [ 3]
F G [ 4]
F G [ 5]
F G [ 6]
F G [ 7]
F G [ 8]
F G [ 9]
F G [ 10 ]
F G [ 11 ]
F G [ 12 ]
F G [ 13 ]
F G [ 14 ]
F G [ 15 ]
F G [ 16 ]
F G [ 17 ]
S V D _ TP _8 6
RSVD86
Connect to GND
B1 9
A1 9
CF G 7
R 2 21
* 3 . 0 1K _0 4
CFG7
Clar ksf ield (on ly f or earl y sa mpl es
pre- ES1 ) - Conn ect to GND with 3. 01K Ohm/ 5%
resi sto r
A L 26
A R2
R2 0 4
R2 0 3
* 1 0 mi l _ s ho rt _ 0 4
* 1 0 mi l _ s ho rt _ 0 4
H _ R S V D 17 _ R
H _ R S V D 18 _ R
A2 0
B2 0
U9
T9
A C9
AB9
C1
A3
J29
J28
A3 4
A3 3
C3 5
B3 5
R
R
R
R
SVD
SVD
SVD
SVD
R S V D 45
R S V D 46
R S V D 47
R S V D 48
R S V D 49
R S V D 50
R S V D 51
R S V D 52
R S V D 53
_ N C T F _ 54
_ N C T F _ 55
_ N C T F _ 56
_ N C T F _ 57
R S V D 58
R S V D _ T P _ 59
R S V D _ T P _ 60
K EY
R S V D 62
R S V D 63
R S V D 64
R S V D 65
R2 1 0
*1 0 0 K _ 0 4
* 1 K _ 1% _ 0 4
M V R E F _ D Q _D I M 0
R 37
* 1 K _ 1% _ 0 4
A J 26
A J 27
D R A MR S T _ C T R L 4 , 1 9
AP1
AT2
1 .5 V
AT3
A R1
A L 28
A L 29
AP3 0
AP3 2
A L 27
A T 31
A T 32
AP3 3
A R3 3
A T 33
A T 34
AP3 5
A R3 5
A R3 2
E1 5
F15
A2
D1 5
C1 5
A J 15
A H1 5
V R E F _ C H _ B _ D I MM
R 38
Q9
* A O 34 0 2 L
S
D
R2 1 3
*1 0 0 K _ 0 4
* 1 K _ 1% _ 0 4
M V R E F _ D Q _D I M 1
R 40
* 1 K _ 1% _ 0 4
D R A MR S T _ C T R L 4 , 1 9
? ? IBEX CONTROL
RS V D6 4 _ R
RS V D6 5 _ R
R2 1 4
R2 1 5
* 1 0 mi l _ s ho rt _ 0 4
* 1 0 mi l _ s ho rt _ 0 4
R SVD 1 5
R SVD 1 6
R SVD 1 7
R SVD 1 8
R SVD 1 9
R SVD 2 0
R SVD 2 1
R SVD 2 2
R S V D _ N C TF _2 3
R S V D _ N C TF _2 4
R SVD 2 6
R SVD 2 7
R S V D _ N C TF _2 8
R S V D _ N C TF _2 9
R S V D _ N C TF _3 0
R S V D _ N C TF _3 1
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
_ T P _ 66
_ T P _ 67
_ T P _ 68
_ T P _ 69
_ T P _ 70
_ T P _ 71
_ T P _ 72
_ T P _ 73
_ T P _ 74
_ T P _ 75
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
_ T P _ 76
_ T P _ 77
_ T P _ 78
_ T P _ 79
_ T P _ 80
_ T P _ 81
_ T P _ 82
_ T P _ 83
_ T P _ 84
_ T P _ 85
VSS
AA5
AA4
R8
A D3
A D2
AA2
AA1
R9
A G7
AE3
V4
V5
N2
A D5
A D7
W3
W2
N3
AE5
A D9
AP3 4
P Z 9 89 2 7 -3 6 41 -0 1 F
1. 5V
B - 10 Processor 7/7
Q8
* A O 34 0 2 L
S
D
AP2302GN
CFG4 - Display Port Presence
CFG4
R 36
V R E F _ C H _ A _ D I MM
A H2 5
AK2 6
? ? IBEX CONTROL
CFG3
CF G 3
A J 13
A J 12
G
CF G 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RESERVED
B.Schematic Diagrams
CFG0
1 : Single PEG
0 : Bifurcation enable
AP2 5
AL 2 5
AL 2 4
AL 2 2
AJ 3 3
A G9
M2 7
L28
J17
H1 7
G2 5
G1 7
E3 1
E3 0
G
R S V D 32
R S V D 33
PCI-Express Configuration Select
4 , 1 0 , 1 1, 2 1 , 2 3 , 2 7 , 29 , 3 1 , 3 3 , 3 6
T P _ RS V D8 6
VSS (AP34) can be left NC is
CRB implementation ; EDS/DG
recommendation to GND
Schematic Diagrams
DDRIII SO-DIMM_0
SO-DIMM A
5
JD I M M2 A
M_ A _ A [ 1 5 : 0 ]
si gna l /spa c e/ signa l :
8/4/8
M _ A _B S 0
M _ A _B S 1
M _ A _B S 2
M _ CS # 0
M _ CS # 1
M_ C L K _ D D R 0
M_ C L K _ D D R # 0
M_ C L K _ D D R 1
M_ C L K _ D D R # 1
M _ CK E 0
M _ CK E 1
M _ A_ CAS #
M _ A_ RAS #
M _ A_ W E#
S A 0 _D I M 0
S A 1 _D I M 0
2 , 1 1 C L K _ S C LK
2 , 1 1 C L K _ S D A TA
3 .3 VS
R N3
1 0 K _ 8 P 4 R_ 0 4
1
8 S A 1 _ DIM
2
7 S A 0 _ DIM
3
6 S A 1 _ DIM
4
5 S A 0 _ DIM
5
5
5
1
1
0
0
1 09
1 08
79
1 14
1 21
1 01
1 03
1 02
1 04
73
74
1 15
1 10
1 13
1 97
2 01
2 02
2 00
1 16
1 20
M _ OD T0
M _ OD T1
M _A _D M[ 7 : 0 ]
S A 1 _ DIM 1 1 1
S A 0 _ DIM 1 1 1
5
98
97
96
95
92
91
90
86
89
85
1 07
84
83
1 19
80
78
M _A _D QS [ 7: 0 ]
5 M _ A _ D Q S # [ 7: 0 ]
M_ A _ D M
M_ A _ D M
M_ A _ D M
M_ A _ D M
M_ A _ D M
M_ A _ D M
M_ A _ D M
M_ A _ D M
0
1
2
3
4
5
6
7
11
28
46
63
1 36
1 53
1 70
1 87
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
S0
S1
S2
S3
S4
S5
S6
S7
12
29
47
64
1 37
1 54
1 71
1 88
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
S# 0
S# 1
S# 2
S# 3
S# 4
S# 5
S# 6
S# 7
10
27
45
62
1 35
1 52
1 69
1 86
1 .5 V
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
10 / A P
11
12 / B C #
13
14
15
B A0
B A1
B A2
S 0#
S 1#
C K0
C K0 #
C K1
C K1 #
C KE0
C KE1
C AS#
R AS#
W E#
S A0
S A1
S CL
S DA
O D T0
O D T1
D
D
D
D
D
D
D
D
M
M
M
M
M
M
M
M
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
S0
S1
S2
S3
S4
S5
S6
S7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
S 0#
S 1#
S 2#
S 3#
S 4#
S 5#
S 6#
S 7#
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 1 0
DQ 1 1
DQ 1 2
DQ 1 3
DQ 1 4
DQ 1 5
DQ 1 6
DQ 1 7
DQ 1 8
DQ 1 9
DQ 2 0
DQ 2 1
DQ 2 2
DQ 2 3
DQ 2 4
DQ 2 5
DQ 2 6
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
DQ 3 1
DQ 3 2
DQ 3 3
DQ 3 4
DQ 3 5
DQ 3 6
DQ 3 7
DQ 3 8
DQ 3 9
DQ 4 0
DQ 4 1
DQ 4 2
DQ 4 3
DQ 4 4
DQ 4 5
DQ 4 6
DQ 4 7
DQ 4 8
DQ 4 9
DQ 5 0
DQ 5 1
DQ 5 2
DQ 5 3
DQ 5 4
DQ 5 5
DQ 5 6
DQ 5 7
DQ 5 8
DQ 5 9
DQ 6 0
DQ 6 1
DQ 6 2
DQ 6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
1 29
1 31
1 41
1 43
1 30
1 32
1 40
1 42
1 47
1 49
1 57
1 59
1 46
1 48
1 58
1 60
1 63
1 65
1 75
1 77
1 64
1 66
1 74
1 76
1 81
1 83
1 91
1 93
1 80
1 82
1 92
1 94
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D Q [ 6 3 : 0]
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q1 0
Q1 1
Q1 2
Q1 3
Q1 4
Q1 5
Q1 6
Q1 7
Q1 8
Q1 9
Q2 0
Q2 1
Q2 2
Q2 3
Q2 4
Q2 5
Q2 6
Q2 7
Q2 8
Q2 9
Q3 0
Q3 1
Q3 2
Q3 3
Q3 4
Q3 5
Q3 6
Q3 7
Q3 8
Q3 9
Q4 0
Q4 1
Q4 2
Q4 3
Q4 4
Q4 5
Q4 6
Q4 7
Q4 8
Q4 9
Q5 0
Q5 1
Q5 2
Q5 3
Q5 4
Q5 5
Q5 6
Q5 7
Q5 8
Q5 9
Q6 0
Q6 1
Q6 2
Q6 3
5
J D I MM 2 B
1 .5 V
75
76
81
82
87
88
93
94
99
10 0
10 5
10 6
11 1
11 2
11 7
11 8
12 3
12 4
3 .3 V S
20mils
C1 0 1
C 10 2
1u _ 6 . 3 V _ X5 R _ 04
0 . 1 u_ 1 0 V _ X 7R _ 04
19 9
3 .3 VS
R 72
77
12 2
12 5
10 K _ 0 4
19 8
30
4 , 11 T S # _ D I MM 0_ 1
4 , 11 D D R 3 _ D R A MR S T #
20mils
C1 7
C1 8
2 . 2u _ 6 . 3 V _ X5 R _ 04
0 . 1u _ 1 0 V _ X7 R _0 4
CU? ?
R1 9
9 MV R E F _ D Q _ D I M 0
*0 _ 0 4
M VR EF _ DIM 0
C 89
C 88
? ? CPU SUPPORT
R1 8
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V D DS P D
N C1
N C2
N CT E ST
EV ENT #
R ESET#
VR EF _ D Q
VR EF _ C A
0 _0 4
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
2 . 2 u _6 . 3 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 7 R _ 0 4
2010/01/08
2.2U? ? :6-07-22511-2A0
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
S 14
S 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
Sheet 10 of 40
DDRIII SO-DIMM _0
V TT _ ME M
V T T1
V T T2
G1
G2
203
204
G ND 1
G ND 2
A S 0 A 62 1 -U 2S N -7 F
C LOSE TO SO- DI MM _ 0
A S 0 A 6 2 1-U 2 S N -7 F
1 .5 V
+
1
12 6
2010/01/08
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
+
C3 6 0
C 32 9
5 6 0 u_ 2 . 5 V _ 6 . 6* 6 . 6 *5 . 9
*2 2 0 u_ 2 . 5 V _ B _ A
C4 9
1 0u _ 6 . 3 V _ X5 R _ 06
C 69
1 0 u _6 . 3 V _ X 5 R _ 0 6
C 84
* 1 0 u_ 6 . 3 V _ X 5R _ 06
C6 2
1 u_ 6 . 3 V _ X 5R _ 0 4
C 82
* 1u _ 6 . 3 V _ X5 R _0 4
C 76
* 1 u_ 6 . 3 V _ X 5R _ 0 4
C7 1
1 u_ 6 . 3 V _ X 5R _ 04
C 75
+
C 32 3
*5 6 0 u _2 . 5 V _ 6 . 6 *6 . 6 *5 . 9
R 63
1 K _ 1 % _0 4
M V R E F _D I M 0
R6 5
C9 2
1 K _ 1 %_ 0 4
0. 1u _ 1 0 V _ X7 R _0 4
* 1u _ 6 . 3 V _ X5 R _0 4
1. 5V
C8 0
C 52
C 59
C5 5
C 60
C 64
C6 6
C 72
C 85
C4 8
0 . 1 u_ 1 0 V _ X7 R _ 04
0 . 1 u _1 0 V _ X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1u _ 1 0 V _ X7 R _ 04
* 0. 1 u _ 1 0V _X 7 R _ 0 4
* 0 . 1 u_ 1 0 V _ X 7R _ 04
*0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _1 0 V _ X 7 R _ 0 4
0 . 1 u _ 1 0V _ X 7 R _ 0 4
*0 . 1 u _1 0 V _ X 7 R _ 0 4
C1 0 6
C 11 0
C 108
C1 1 1
C 11 2
1 0u _ 6 . 3 V _ X5 R _ 06
* 1u _ 6 . 3 V _ X5 R _ 04
1 u _ 6 . 3 V _ X5 R _0 4
1 u_ 6 . 3 V _ X 5R _ 0 4
* 1u _ 6 . 3 V _ X5 R _0 4
4 , 9 , 11 , 2 1 , 2 3 , 27 , 2 9 , 3 1 , 33 , 3 6 1 . 5 V
11 , 3 3 V T T _ ME M
2 , 1 1 , 1 2, 13 , 1 4 , 1 5, 16 , 1 7 , 1 8, 19 , 2 0 , 2 1, 23 , 2 4 , 2 5 , 26 , 2 7 , 2 8 , 29 , 3 0 , 3 1 , 35 , 3 6 3 . 3 V S
V T T _ ME M
DDRIII SO-DIMM_0 B - 11
B.Schematic Diagrams
M_ A _ A 0
M_ A _ A 1
M_ A _ A 2
M_ A _ A 3
M_ A _ A 4
M_ A _ A 5
M_ A _ A 6
M_ A _ A 7
M_ A _ A 8
M_ A _ A 9
M_ A _ A 1 0
M_ A _ A 1 1
M_ A _ A 1 2
M_ A _ A 1 3
M_ A _ A 1 4
M_ A _ A 1 5
La yout Note :
5
5
5
5
5
5
5
5
5
5
5
5
5
5
CHANGE TO STANDARD
Schematic Diagrams
DDRIII SO-DIMM_1
SO-DIMM B
5
CHANGE TO STANDARD
JD I M M1 A
M_ B _ A [ 1 5 : 0 ]
M_ B _ A 0
M_ B _ A 1
M_ B _ A 2
M_ B _ A 3
M_ B _ A 4
M_ B _ A 5
M_ B _ A 6
M_ B _ A 7
M_ B _ A 8
M_ B _ A 9
M_ B _ A 1 0
M_ B _ A 1 1
M_ B _ A 1 2
M_ B _ A 1 3
M_ B _ A 1 4
M_ B _ A 1 5
B.Schematic Diagrams
La y out Not e:
si gnal /spa c e /si gna l :
8/4/8
5
5
5
5
5
5 M
5 M
5 M
5 M
5
5
5
5
5
10
10
2 , 10
2 ,1 0
Sheet 11 of 40
DDRIII SO-DIMM _1
5
5
5
5
M_ B _ B S 0
M_ B _ B S 1
M_ B _ B S 2
M_ C S #2
M_ C S #3
_C L K _ D D R 2
_C L K _ D D R # 2
_C L K _ D D R 3
_C L K _ D D R # 3
M_ C K E 2
M_ C K E 3
M_ B _ C A S #
M_ B _ R A S #
M_ B _ W E #
S A 0 _ DIM 1
S A 1 _ DIM 1
C LK _S C L K
CL K_ SD A T A
SA 0 _ DIM 1
SA 1 _ DIM 1
98
97
96
95
92
91
90
86
89
85
1 07
84
83
1 19
80
78
1 09
1 08
79
1 14
1 21
1 01
1 03
1 02
1 04
73
74
1 15
1 10
1 13
1 97
2 01
2 02
2 00
1 16
1 20
M_ OD T 2
M_ OD T 3
M_ B _ D M [ 7 : 0]
M_ B _ D Q S [ 7 : 0 ]
5 M_ B _ D Q S # [ 7 : 0 ]
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
0
1
2
3
4
5
6
7
11
28
46
63
1 36
1 53
1 70
1 87
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
S0
S1
S2
S3
S4
S5
S6
S7
12
29
47
64
1 37
1 54
1 71
1 88
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
S# 0
S# 1
S# 2
S# 3
S# 4
S# 5
S# 6
S# 7
10
27
45
62
1 35
1 52
1 69
1 86
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
10 / A P
11
12 / B C #
13
14
15
B A0
B A1
B A2
S 0#
S 1#
C K0
C K0 #
C K1
C K1 #
C KE0
C KE1
C AS#
R AS#
W E#
S A0
S A1
S CL
S DA
O DT 0
O DT 1
D
D
D
D
D
D
D
D
M0
M1
M2
M3
M4
M5
M6
M7
D
D
D
D
D
D
D
D
QS
QS
QS
QS
QS
QS
QS
QS
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
D
QS
QS
QS
QS
QS
QS
QS
QS
0#
1#
2#
3#
4#
5#
6#
7#
D Q0
D Q1
D Q2
D Q3
D Q4
D Q5
D Q6
D Q7
D Q8
D Q9
D Q 10
D Q 11
D Q 12
D Q 13
D Q 14
D Q 15
D Q 16
D Q 17
D Q 18
D Q 19
D Q 20
D Q 21
D Q 22
D Q 23
D Q 24
D Q 25
D Q 26
D Q 27
D Q 28
D Q 29
D Q 30
D Q 31
D Q 32
D Q 33
D Q 34
D Q 35
D Q 36
D Q 37
D Q 38
D Q 39
D Q 40
D Q 41
D Q 42
D Q 43
D Q 44
D Q 45
D Q 46
D Q 47
D Q 48
D Q 49
D Q 50
D Q 51
D Q 52
D Q 53
D Q 54
D Q 55
D Q 56
D Q 57
D Q 58
D Q 59
D Q 60
D Q 61
D Q 62
D Q 63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
12 9
13 1
14 1
14 3
13 0
13 2
14 0
14 2
14 7
14 9
15 7
15 9
14 6
14 8
15 8
16 0
16 3
16 5
17 5
17 7
16 4
16 6
17 4
17 6
18 1
18 3
19 1
19 3
18 0
18 2
19 2
19 4
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
M_ B _ D Q[ 6 3 : 0 ] 5
J D I M M1 B
1 .5 V
75
76
81
82
87
88
93
94
99
1 00
1 05
1 06
1 11
1 12
1 17
1 18
1 23
1 24
3 . 3V S
20mils
C1 0 3
C1 0 4
1 u _6 . 3 V _ X 5R _ 0 4
0. 1u _ 1 0 V _X 7 R _0 4
1 99
9 M V R E F _D Q_ D I M1
R 22
* 0 _0 4
R2 1
M V R E F _D I M1
C 91
C 90
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
NC 1
NC 2
N C TE S T
1 98
30
2 . 2 u _6 . 3 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VDD SP D
77
1 22
1 25
4 , 1 0 T S # _D I MM 0 _ 1
4 ,1 0 DD R3 _ DR A M RS T #
C 21
C 22
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EV ENT #
RE S E T #
1
1 26
VREF _ D Q
VREF _ C A
0 _0 4
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
2 . 2 u _6 . 3 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4
2.2U? ? :6-07-22511-2A0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
S 28
S 29
S 30
S 31
S 32
S 33
S 34
S 35
S 36
S 37
S 38
S 39
S 40
S 41
S 42
S 43
S 44
S 45
S 46
S 47
S 48
S 49
S 50
S 51
S 52
44
48
49
54
55
60
61
65
66
71
72
12 7
12 8
13 3
13 4
13 8
13 9
14 4
14 5
15 0
15 1
15 5
15 6
16 1
16 2
16 7
16 8
17 2
17 3
17 8
17 9
18 4
18 5
18 9
19 0
19 5
19 6
V TT _ ME M
V T T1
V T T2
G1
G2
20 3
20 4
GN D 1
GN D 2
A S 0 A 6 2 1-U A S N -7 F
A S 0 A 6 2 1-U A S N -7 F
CLOS E TO SO -DI M M_ 1
La y out Not e:
S O- DIM M _ 1 i s pl a ce d f a rt he r from the G M CH t ha n SO -DI M M _0
1 .5 V
1 .5 V
C 86
C 50
C 68
C7 7
C5 4
C7 8
C 70
C 61
*1 0 u _ 6. 3 V _ X 5 R _ 0 6
1 0 u _6 . 3 V _ X 5R _ 0 6
1 0 u _ 6. 3 V _ X 5 R _ 0 6
*1 u _6 . 3 V _ X 5R _ 0 4
1u _ 6 . 3 V _ X5 R _0 4
1 u_ 6 . 3 V _ X 5R _ 04
1 u _6 . 3 V _ X 5 R _ 0 4
* 1u _ 6 . 3 V _ X5 R _0 4
C 11 6
C 24
C 56
C2 3 9
C6 3
C7 3
C 79
C 83
C 47
C7 4
0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0. 1 u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _X 7 R _ 0 4
0 . 1 u_ 1 0 V _ X7 R _0 4
0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0. 1 u _ 1 0V _ X 7 R _ 0 4
C 10 7
C 11 4
C 1 15
C1 0 9
C1 1 3
1 0 u_ 6 . 3 V _ X 5R _ 06
1 u _ 6. 3 V _ X 5 R _ 0 4
* 1 u_ 6 . 3 V _ X 5R _ 04
1u _ 6 . 3 V _X 5 R _0 4
*1 u _6 . 3 V _ X 5 R _ 0 4
R 64
1 K _ 1 % _ 04
M V R E F _D I M 1
R 66
C9 3
1 K _ 1 %_ 0 4
0. 1u _ 1 0V _X 7 R _ 0 4
1 .5 V
V T T _ ME M
B - 12 DDRIII SO-DIMM_1
4 , 9, 10 , 2 1 , 2 3, 27 , 2 9 , 3 1, 3 3 , 3 6 1 . 5V
1 0 , 3 3 V T T _M E M
2, 10 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 1 , 23 , 2 4 , 2 5, 26 , 2 7 , 2 8, 29 , 3 0 , 3 1, 3 5 , 3 6 3 . 3V S
Schematic Diagrams
LVDS, Inverter
PANEL CONNECTOR
3 .3 V S
EDID Mode
COSTDOWN
2
1
VIN
? ? ? ?
V IN_ L CD
L25
3 R N6
4 2 . 2 K _ 4P 2R _0 4
J _ LC D 1
8 0mi ls
*1 5 m il _ s ho rt _ 0 6
C 30 7
C 3 04
C 30 1
0 . 1 u_ 5 0 V _Y 5 V _ 06
0 . 1 u _5 0 V _ Y 5 V _ 06
0 . 1 u _5 0 V _ Y 5 V _ 06
L V D S -LC L K N
LV D S -L C L K P
17
17
L V D S -L 1 N
L V D S -L1 P
17
17
L V D S -L 0 N
L V D S -L0 P
L V D S -L C L K N
L V D S -L C L K P
L V D S -L 1N
L V D S -L 1P
L V D S -L 0N
L V D S -L 0P
CLOSE TO LVDS CONN.
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
87 2 1 6-3 0 0 6
P _ D D C _D A T A
P _ D D C _C LK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
B R I GH TN E S S
I N V _ B L ON
LV D S -L 2N
LV D S -L 2P
L V D S -L 2 N 1 7
L V D S -L 2 P 1 7
3 . 3V S
C2 9 8
2A
PL VD D
PANEL POWER
P _ DDC _ DA T A 1 7
P _ DDC _ CL K 1 7
B RIG HT N E S S 2 8
0. 1u _ 10 V _ X 7 R _ 04
C4
C 6
4. 7 u _ 6. 3 V _ X 5R _ 06
0 . 1 u _1 0 V _ X7 R _0 4
Sheet 12 of 40
LVDS, Inverter
3. 3 V S
2A
3 .3 V
C 15
D1 4
PL VD D
U 1
0. 1 u _ 10 V _ X 7 R _ 04
4
5
VIN
VIN
V O UT
1
C
2A
B R I GH T N E S S
AC
C 2 97
* 0 . 1u _ 1 0V _ X 5 R _ 0 4
A
*B A V 9 9 R E C T I F I E R
3
1 7 N B _ E NA V D D
EN
R 13
GN D
2
G5 2 4 3A
1 0 0 K _ 04
INVERTER CONNECTOR
B K L _ E N_ R
R6 7
C 96
10 0 K _ 0 4
0 . 4 7u _ 1 0V _ Y 5V _ 0 4
3 .3 V
3. 3V
U3 A
7 4L V C 08 P W
1
3
B LO N
Z 1 2 01
C 95
4
2
6
* 0. 1u _ 1 0V _ X 5 R _ 04
5
7
R6 9
14
10 0 K _ 0 4
19
S B _B L O N
Z12 02
L ID_ S W #
I N V _ B L ON
8
1 00 K _ 0 4
Z12 03 10
14
28 , 3 0
16 , 2 8 A L L_ S Y S _P W R G D
U 3C
7 4 L V C0 8 P W
9
3. 3V
R 70
U 3D
7 4 LV C 0 8P W
R7 1
C 99
1 M_ 04
0 . 1 u _1 0 V _ X7 R _ 0 4
12
11
13
7
1 7 BL O N
3 .3 V
U 3B
7 4 LV C 0 8P W
7
1 0K _ 0 4
14
R6 8
14
BKL _ EN
7
28
3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7
3 , 4 , 1 4 , 15 , 1 6 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 3 4 , 3 5
2 , 1 0, 1 1 , 1 3, 1 4 , 1 5, 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 25 , 2 6 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6
3 1 ,3 2
V IN
3. 3 V
3. 3 V S
SYS1 5 V
LVDS, Inverter B - 13
B.Schematic Diagrams
17
17
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Schematic Diagrams
HDMI, CRT
L 27
1 _0 4
For ESD
5V S
HDMI PORT
5 VS
RD2
RD3
B A V9 9 R E C TI F I E R B A V 99 R E C T FI I E R
Sheet 13 of 40
HDMI, CRT
Z4 30 6
Z4 30 7
34
35
PC0
PC1
R E XT
G N D [1 ]
G N D [2 ]
G N D [3 ]
G N D [4 ]
G N D [5 ]
G N D [6 ]
G N D [7 ]
G N D [8 ]
G N D [9 ]
GN D [ 10 ]
OE _1
QE _2
? ? ?
49
V C C [1 ]
V C C [2 ]
V C C [3 ]
V C C [4 ]
V C C [5 ]
V C C [6 ]
V C C [7 ]
V C C [8 ]
GN D
12
4
3
* H D MI 201 2F 2 SF -90 0T 04 -sho rt
R4 8
C 40
C3 1
0. 1u _1 0V _X 7R _ 04
0. 1 u_ 10V _ X7 R _0 4
0 1. u_ 10 V_ X7 R _0 4
C2 6
2 0K _1 %_0 4
H D MI B_ D A TA 1N
1
2
H D MI B_ D A TA 1P
4
3
C 67
0 . 1u _1 0V _X 7R _ 04
L7
*H D MI2 01 2F 2S F -90 0T 04 -s ho rt
0. 1u _1 0V _X 7R _ 04
3 . 3V S
R 26
P OR T C _H P D
M_ P OR TB _H P D # _R
P T N 33 60B B S
P I N 4 9 =G N D
R3 4
*1 0mi l _sh ort
* 20 K_ 1% _04
PS 810 1 ( 6-0 3-0 810 1-0 32) PI N T O P IN
3. 3V S
R 57
4. 7 K_ 04
D C C _ EN #
R 30
4. 7 K_ 04
P C0
R 29
*4 .7 K _0 4
P C1
6
4
2
C 35
*0 . 1u _10 V _X 7R _ 04
R3 3
*7 . 5K _1 %_0 4
CE C
13
T MD S C L OC K C L K S H I E LD
T MD S C L OC K +
TMD S D A TA 0S H I E LD 0
T MD S D A TA 0 +
T MD S D A T A1 S H IE L D 1
T MD S D A T A1 +
L6
4
9
5
TMD S D A TA 2-
3
1
3 . 3V S
Q7
*MT N 70 02 Z H S3
M_P OR TB _ H PD #_R
G
FOR E MI
H D MI_ C E C
7
T MD S D A TA 2 +
S H I E LD 2
H D MI B_ E XT1 _S C L
11
C 1 28 17 -119 A 5-L
P OR TC _ H P D
P OR TC _ H P D
D
17
8
S
6-03-03360-030
10
17
15
C 31 7
C 53
0. 1u _1 0V _X 7R _ 04
0. 1 u_ 10V _ X7 R _0 4
R4 4
AC
AC
3 3. V S
C1
1
5
12
18
24
27
31
36
37
43
2
H D MI B_ E XT1 _H P D
19
S CL
R E S E R VE D
*L VA R 0 40 2-24 0E 0 R 05P -L F
*4. 7 K _04
*4. 7 K _04
D C C _E N #
R T_ E N #
2
11
15
21
26
33
40
46
L5
D D C / C E C GN D
S DA
R5 9
49 9_ 1%_ 04
R4 9
R5 8
OE #
H D MI B_ E XT1 _H P D
1
H OT PL U G D ET E C T
+ 5V
*L VA R 0 40 2-24 0E 0 R 05P -L F
R2 8
3. 3 VS
3
4
6
H D MI B_ C LOC K N
14
R 43
32
10
PC 0
PC 1
Z4 30 5
H D MI B_ E XT1 _S C L
H D MI B_ E XT1 _S D A
30
16
F OR E MI
H D MI B_ C LOC K P
28
29
18
H D MI B_ E XT1 _S D A
4
3
*LV A R 04 02 -2 40 E 0R 05 P -LF
D C C _E N #
? ? ?
H P D _S I N K
H D MI B_ C LOC K P
H D MI B_ C LOC K N
200 9. 06 .1 8
RN2
2. 2 K_ 4P 2 R _0 4
1
2
R 55
25
SC L _S I N K
S D A _S I N K
HP D
13
14
5 VS
*LV A R 04 02 2- 40 E 0R 05 P -LF
Z4 30 4
SCL
SDA
H D MI B_ D A TA 0P
H D MI B_ D A TA 0N
3
H D MI B _D A TA 0 N
1
2
H D MI B _ D AT A 0P
*H D MI 20 12 F2 S F-9 00 T0 4-sh ort
L8
4
3 H D MI B _D A TA 2 N
1
2 H D MI B _ D AT A 2P
*H D MI 20 12 F2 S F-9 00 T0 4-sh ort
R3 2
*2 0K _1 %_ 04
? ? ?
5 VS
R ED
C 303
V I D E O_1
VC C _ V ID EO
V I D E O_2
VC C _ D D C
V I D E O_3
BY P
I P 47 72 C Z1 6
GN D
3
BL U E
4
GR N
5
RE D
C M20 09- 02Q R P N:6 -02 -200 90- B60
I P47 72C Z16 PN :6- 02- 4772 1-B 60
2 , 10 , 11, 1 2, 1 4, 15 , 16 , 17, 1 8, 1 9, 20 , 21 ,2 3, 2 4, 2 5, 26 , 27 ,2 8, 2 9, 30 , 31 , 35, 3 6 3. 3 V S
2, 1 7, 20 , 21 ,2 6, 2 7, 30 , 31 , 35, 3 6 5V S
6 p_ 50V _ N PO _04
6 p_ 50 V_ N P O_0 4
6
11
C1 6
VS Y N C
6p _5 0V _N P O_0 4
33 _04
C1 4
R1 4
C 11
C R T _V S Y N C
6p _5 0V _N PO_ 04
16
6 p_ 50 V_ N P O_04
HS Y NC
C 13
33 _04
15 0_ 1% _0 4
10
4
12
DDCDA T A
13
HS Y NC
14
V S Y NC
15
DDCL K
5
6
7
8
C 7 10 00 p_5 0V _ X7 R _0 4
VC C _ S Y N C
R1 5
15 0_1 %_ 04
2 4 m il
3
C 2 99 2 20p _5 0V _N PO_ 04
0 . 22 u_ 50V _ 06
0. 22 u_ 50 V _06
C 30 6
C 3 05
0. 2 2u _5 0V _0 6
8
S Y N C _ OU T2
C R T _H S Y N C
1 50 _1% _0 4
GR N
BL U E
C 3 00 2 20 p_ 50 V_ N P O_0 4
7
3. 3 VS
SY N C _ I N 2
14
R 10
2
C 30 2 10 00 p_5 0V _ X7 R _0 4
2
3 . 3V S
S Y N C _ OU T1
D D C LK
R 11
F C M10 05 K F-3 00 T03
F C M10 05 K F-3 00 T03
F C M10 05 K F-3 00 T03
GN D 1
GN D 2
1
5V S
SY N C _ I N 1
12
R1 2
C1 2
15
D AC _ V SY N C
D D C _ OU T2
D D C D A TA
6 p_ 50 V _N P O_0 4
13
1 7 D A C _ H SY N C
D D C _ OU T1
D D C _I N 2
9
C 10
4
3
11
17 D A C _ D D C AC L K
U1 5
D D C _I N 1
1
2
1
2
10
L4
L3
L2
1 7 D A C _R E D
1 7 D A C _GR E E N
1 7 D A C _B L U E
RN1
2. 2K _ 4P 2R _ 04
17 D A C _ D D C AD A T A
B - 14 HDMI, CRT
1
9
RN7
2. 2K _ 4P 2R _ 04
17
J _C R T 1
108 A H 15 FS T 04N 1C 3
6-19-31001-264
3. 3V S
4
3
CRT PORT
.
.
.
B.Schematic Diagrams
*4. 7 K_ 04
*0_ 04
OU T_ D 4+
OU T_D 4 -
H D MI B_ D A TA 1P
H D MI B_ D A TA 1N
16
17
R 41
7
I N _D 4 +
I N _D 4 -
19
20
*LV A R 04 02 -240 E 0R 0 5P -LF
9
8
OU T_ D 3+
OU T_D 3 -
R 46
H D MI _C T R LC L K
H D MI _C T R LD A T A
M_P OR T B_ H P D #_ R
OU T_ D 2+
OU T_D 2 -
I N _D 3 +
I N _D 3 -
22 u_ 6. 3V _ X5 R _0 8
*LV A R 04 02 -240 E 0R 0 5P -LF
48
47
17 H D MI B_ C LK B P
17 H D MI B_ C LK B N
I N _D 2 +
I N _D 2 -
C 32 4
10 u_6 . 3V _X 5R _ 06
R4 2
45
44
C 32 7
*L VA R 0 40 2-24 0E 0 R 05P -L F
42
41
17 H D MI B_ D 0B P
17 H D MI B_ D 0B N
OU T_ D 1+
OU T_D 1 -
H D MI B_ D A TA 2P
H D MI B_ D A TA 2N
R5 1
17 H D MI B_ D 1B P
17 H D MI B_ D 1B N
I N _D 1 +
I N _D 1 -
22
23
*L VA R 0 40 2-24 0E 0 R 05P -L F
39
38
3 . 3V S
A
J _H D MI 1
AC
17 H D MI B_ D 2B P
17 H D MI B_ D 2B N
R5 6
R4 7
C
1_ 04
RD1
B A V9 9 R E C TI F I E R
U2
1 7 H D MI _C TR LC LK
1 7 H D MI _C T R LD A TA
A
A
C
C
R 20 7
FOR INTEL GRAPHIC
Schematic Diagrams
IBEXPEAK - M 1/9
IBEXPEAK - M (HDA,JTAG,SATA)
RT C V CC
20 mils
C 382
C 408
1 5 p_ 5 0 V _ N P O_ 0 4
2 . 2 u_ 1 6 V _ X 5 R _ 0 6
A
2
2
1
R T C_ V B A T _ 1
3
R 299
2 0 K_ 1 % _ 0 4
X6
C M 20 0 S 3 2 7 6 8 12 2 0 _ 3 2. 76 8 K H z
D 16
B A T5 4 C S 3
1
C4 0 5
1 K_ 0 4
2 . 2 u_ 1 6 V _ X 5 R _ 0 6
R T C_ V B A T 1
1
2
R T C_ R S T #
C 14
S R T C _R T C #
D 17
S M_ I N TR U D E R #
A 16
P C H _ I N T V R ME N
A 14
RT C X 1
RT C X 2
FW H
FW H
FW H
FW H
0
1
2
3
/
/
/
/
L AD
L AD
L AD
L AD
0
1
2
3
C4 0 6
1M _ 0 4
2 . 2 u_ 1 6 V _ X 5 R _ 0 6
TPM CLEAR
J O PEN 1
* OP E N _ 1 0 m i -l 1 M M
R2 9 3
R T CV CC
3 3 0 K_ 0 4
F W H 4 / L F R A ME #
S RT C RS T #
INT R UD E R #
INT V R M E N
L D RQ 0 #
L D R Q1 # / G P I O 2 3
S E RIR Q
LP
LP
LP
LP
C3 4
C_ A D
C_ A D
C_ A D
C_ A D
0
1
2
3
2 4 , 28
2 4 , 28
2 4 , 28
2 4 , 28
LP C _ F R A M E # 2 4 , 28
A3 4
F34
AB9
S E R IRQ
AK7
AK6
AK1 1
AK9
S A T A R X N0
SATAR XP0
S A T A T X N0
SATATXP0
AH 6
AH 5
AH 9
AH 8
S A T A R X N1
SATAR XP1
S A T A T X N1
SATATXP1
S E R IRQ
2 4 ,2 8
2
R2 9 4
D3 3
B3 3
C3 2
A3 2
A 30
2 7, 29 H D A _ B I T C L K
BIOS ROM
27
32Mbit
R 159
3 .3 K _ 1 % _ 0 4
S P I_ W P #
3
U 11
V DD
S I
W P#
C E#
SO
R 152
3 .3 K _ 1 % _ 0 4
S P I _ H OL D # 7
SC K
HO L D#
VS S
5
SPI_ SI
2
SPI_ SO
1
SPI_ C S0 #
6
SPI_ SC L K
SPI_ VD D
8
SPI_ W P#
3
VD D
SI
W P#
C E#
SO
SC K
4
S P I _ H OL D #7
MX 2 5 L 3 20 5 D M2 I -1 2 G
HO L D#
VS S
5
SPI_ SI
27
HD A _ S D IN0
29
HD A _ S D IN1
2
SPI_ SO
1
SPI_ C S1 #
6
SPI_ SC L K
G 30
F 30
S A TA 1R X N
S A T A 1 RX P
SATA1 TXN
S A TA 1 TX P
HD A _ S D IN0
HD A _ S D IN1
4
B 29
2 7, 29 H D A _ S D O U T
HD A _ S D IN3
S A TA 2R X N
S A T A 2 RX P
SATA2 TXN
S A TA 2 TX P
S A TA 3R X N
S A T A 3 RX P
SATA3 TXN
S A TA 3 TX P
HD A _ S D O
*M X 2 5 L3 2 0 5 D M 2 I -1 2 G
1 K_ 0 4
H DA _ DO CK _ E N#
H 32
H D A _ D O C K _ E N # / GP I O3 3
J 30
28
D 17
C
ME _ W E #
HD A _ DO C K _ RS T # / G P IO 1 3
R B7 5 1 V
A
1
P C H _ JT A G _ T C K _B U F M3
J OP E N 3
*O P E N _ 10 m i l -1 MM
2
Flash Descriptor
Security Overide
P C H _ JT A G _ T MS
K3
P C H _ JT A G _ T D I
K1
P C H _ JT A G _ T D O
J2
P C H _ JT A G _ R S T #
J4
J TA G_ T C K
3 .3 V
BA2
SPI_ C S0 #
S P I_ CS 0 # _ R
AV3
SPI_ C S1 #
S P I_ CS 1 # _ R
AY3
R 262
33_04
S P I _ S O_ R
AV1
* 20 0 _ 0 6
* 1 0K _0 4
R 28 5
*1 0 0 _1 % _ 0 4
R 2 84
H _ J T A G_ T M S
H _ J T A G_ T D I
H _ J T A G_ T D O
H _ J T A G_ R S T #
3 .3 VS
R 93
R 2 78
R 282
* 10 0 _ 1 % _ 04
1 0 K _ 04
*1 K _ 0 4
S E R IR Q
H DA _ S P K R
NO REBOOT STRAP: HDA_SPKR High Enable
* 1 00 _ 1 % _ 0 4
3 .3 VS
SATA ODD
Sheet 14 of 40
IBEXPEAK - M 1/9
AH 3
AH 1
AF3
AF1
AD 9
AD 8
AD 6
AD 5
S A T A R X N2
SATAR XP2
S A T A T X N2
SATATXP2
AD 3
AD 1
AB3
AB1
AF1 6
S A T A I C OM P
R8 9
37 . 4 _ 1 % _ 0 4
R2 7 5
*1 0 K _ 0 4
S A T A ICO M P O
S A T A I C O MP I
AF1 5
3 .3 V S
S P I _ C LK
SPI_ C S 0 #
T3
SPI_ C S 1 #
S ATAL ED #
S P I _ M OS I
SAT A0 G P / G PIO 2 1
Y9
SPI_ M ISO
SAT A1 G P / G PIO 1 9
SATA_ L ED #
S A T A _ LE D # 2 9
O DD _ DE T E C T #
R1 0 8
SATA_ D ET# 1
R2 7 1
V1
3 .3 VS
10 K _ 0 4
O D D _ D E TE C T # 2 6
10 K _ 0 4
ESATA
S A T A T XP 2
C 17 4
* 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
S A T A T XN 2
C 17 1
* 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
S A T A RX N 2
C 16 1
* 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
S A T A RX P 2
C 17 0
* 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
iTPM ENABLE/DISABLE
R 2 61
R2 8 1
26
26
26
26
* 2 00 _ 0 6
PC
PC
PC
PC
R 289
S A T A R X N1
SATAR XP1
SATATXN 1
SATATXP1
SATA HDD
1 .1 VS_ VT T
J TA G_ R S T #
R 283
* 20 0 _ 0 6
26
26
26
26
AF1 1
AF9
AF7
AF6
I b e xP e ak -M _ R e v 0 _ 9
* 2 0K _1 % _ 0 4
S A T A R X N0
SATAR XP0
SATATXN 0
SATATXP0
J TA G_ T D I
AY1
SPI_ SI
SPI_ SO
S A TA 4R X N
S A T A 4 RX P
SATA4 TXN
S A TA 4 TX P
S A TA 5R X N
S A T A 5 RX P
SATA5 TXN
S A TA 5 TX P
J TA G_ T MS
J TA G_ T D O
SPI_ SC L K
R 2 86
HD A _ RS T #
HD A _ S D IN2
F 32
R 298
R 28 8
SPKR
E 32
SPI_* = 1.5"~6.5"
R 290
S A TA 0R X N
S A T A 0 RX P
SATA0 TXN
S A TA 0 TX P
HD A _ S Y NC
SATA
8
P1
C 30
2 7, 29 H D A _ R S T #
32Mbit
U1 0
S P I_ V D D
H DA _ S P K R
H D A_ SPKR
IHDA
S H O RT
C 21 7
0 . 1 u _1 0 V _ X 7 R _ 0 4
D 29
2 7, 29 H D A _ S Y N C
JTAG
N C1
SPI
3 .3 V S
HD A _ B C L K
*1 K _ 0 4
S P I _S I
*4 . 7 K _ 0 4 P C H _ JT A G_ T C K _B U F
TPM FUNCTION:SPI_SI High Enable
? ? ? ? , ESATA REDRIVER? ? ? ? ? ?
2 3, 25 , 2 8 , 2 9 , 3 1 , 3 2, 3 7 V D D 3
21
R T CV CC
2 , 4 , 6 , 7 , 1 5 , 1 6 , 1 9 , 20 , 2 1 , 3 4 , 3 5 , 3 6 1 . 1V S _ V T T
3 , 4 , 12 , 1 5 , 1 6 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 2 4 , 2 5, 29 , 3 0 , 3 1 , 3 3 , 3 4, 3 5 3 . 3 V
2, 10 , 1 1 , 1 2 , 1 3 , 1 5, 16 , 1 7 , 1 8 , 1 9 , 2 0, 2 1 , 2 3 , 2 4 , 2 5 , 26 , 2 7 , 2 8 , 2 9 , 3 0, 31 , 3 5 , 3 6 3 . 3 V S
IBEXPEAK - M 1/9 B - 15
B.Schematic Diagrams
8 5 2 05 -0 2 7 0 1
B 13
D 13
RT C RS T #
1
2
U 20A
R T C_ X 1
R T C_ X 2
Z o= 50O ? 5%
R 300
2 0 K_ 1 % _ 0 4
J _ RT C 1
J_RTC1
1
J O PEN 2
* OP E N _ 1 0 m i -l 1 M M
2
10 m ils
R 297
1 0 M _ 04
R 251
C 404
1 5 p_ 5 0 V _ N P O_ 0 4
RTC CLEAR
RTC
C
LPC
A
1
3
4
2 0m ils
V DD 3
Schematic Diagrams
IBEXPEAK - M 2/9
IBEXPEAK - M (PCI-E,SMBUS,CLK)
SM B_ C L K
SM B_ D ATA
R N 16
2 . 2 K _4 P 2 R _ 0 4
3
2
4
1
S M L 0 _ DAT A
S M L 0 _ CL K
R N 11
2 . 2 K _4 P 2 R _ 0 4
3
2
4
1
U2 0 B
2 5 P C I E _ R X N 4 _ GL A N
2 5 PC IE_ RXP4 _ G L AN
25 P C I E _ TX N 4 _ GL A N
25 P C I E _ TX P 4 _ G L A N
Sheet 15 of 40
IBEXPEAK - M 2/9
PCI-E x1
Lane
Lane
Lane
Lane
Lane
Lane
Lane
Lane
3 .3 V
1
2
3
4
5
6
7
8
0 . 1 u _ 10 V _ X 7 R _0 4
0 . 1 u _ 10 V _ X 7 R _0 4
P C I E _ T XN 2 _ C
P C I E _ T XP 2 _C
C1 3 1
C1 3 0
0 . 1 u _ 10 V _ X 7 R _0 4
0 . 1 u _ 10 V _ X 7 R _0 4
P C I E _ T XN 3 _ C
P C I E _ T XP 3 _C
AU3 0
A T3 0
AU3 2
AV3 2
C1 2 6
C1 2 7
0 . 1 u _ 10 V _ X 7 R _0 4
0 . 1 u _ 10 V _ X 7 R _0 4
P C I E _ T XN 4 _ C
P C I E _ T XP 4 _C
BA3 2
BB3 2
BD3 2
BE3 2
BF 3 3
BH3 3
B G3 2
B J3 2
Usage
BA3 4
AW 3 4
BC3 4
BD3 4
WLAN
NEW CARD
3G
GLAN / CARD READER
X
X
X
X
A T3 4
AU3 4
AU3 6
AV3 6
B G3 4
B J3 4
B G3 6
B J3 6
3 .3 V S
AK4 8
AK4 7
R N8
1 0 K_ 8 P4 R_ 0 4
1
8
2
7
3
6
4
5
P C IE CL K RQ 0 #
P
P
P
P
C I E C L K R Q1 #
C I E C L K R Q0 #
C I E C L K R Q5 #
E G_ B _ C L K R Q #
P C IE CL K RQ 1 #
U4
A M4 7
A M4 8
2 3 CL K _ P C IE _ N E W _ C A RD #
23 C L K _ P C I E _ N E W _ C A R D
2 3 N E W C A R D _ C LK R E Q #
P9
A M4 3
A M4 5
R 279
0_04
C L K _ S L O T 2 _O E #
N4
AH4 2
AH4 1
2 3 C L K _ P C I E _ MI N I #
2 3 C LK _P C I E _M I N I
A8
S M L 0 A L E R T # / GP I O 6 0
S ML 0 C LK
PE R N3
PER P3
P E T N3
PETP3
PE R N4
PER P4
P E T N4
PETP4
PE R N5
PER P5
P E T N5
PETP5
PE R N6
PER P6
P E T N6
PETP6
P C H _ B T_ E N #
H 14
S M B _ C LK
C 8
SM B_ D ATA
J14
P C H _ U P E K _I N I T #
C 6
S M L 0 _C L K
G 8
S M L 0 _D A T A
S ML 0 D A TA
S M L 1 A L E R T # / GP I O 7 4
S M L 1 C L K / GP I O 5 8
M 14
L P D _ S P I _ I N TR #
E1 0
S M C _ C P U _ TH E R M
G 12
S M D _ C P U _ TH E R M
S M L1 D A T A / GP I O 7 5
PE R N8
PER P8
P E T N8
PETP8
CL _ D A T A 1
C L _R S T 1 #
P C I E C L K R Q1 # / GP I O 1 8
CL K O UT _ P C IE 2 N
CL K O UT _ P C IE 2 P
P C I E C L K R Q2 # / GP I O 2 0
18
P C H _ B T _E N #
U S B _ OC # 89
L P D _ S P I_ IN T R#
U S B _O C #8 9
P CH _ UP E K _ INIT # 1 8
S ML 0 _ C LK
23
S ML 0 _ D A T A 2 3
S M D _ CP U _ T HE R M
S M C _ CP U _ T HE R M
S M C_ C P U_ T H E RM
3 ,2 8
S M D_ C P U_ T H E RM
3 ,2 8
R N 13
1 0 K _ 8 P 4 R _ 04
1
8
2
7
3
6
4
5
R N 10
2 . 2 K _4 P 2 R _ 0 4
3
2
4
1
PEG _ CL KR EQ #
R 287
1 0K _0 4
L A N _ C L K R E Q#
R 112
1 0K _0 4
T11
T9
10K pull-down to
GND
C L K O U T _ P E G_ A _ N
C LK OU T _ P E G _A _P
C L K O U T _ D MI _ N
C L K O U T _D M I _P
C LK OU T _D P _ N / C LK OU T _ B C L K 1 _ N
C L K O U T_ D P _ P / C L K O U T _ B C L K 1 _P
CL K O UT _ P C IE 1 N
CL K O UT _ P C IE 1 P
S MB _ D A T A 2
C L_ C L K 1
CL K O UT _ P C IE 0 N
CL K O UT _ P C IE 0 P
P C I E C L K R Q0 # / GP I O 7 3
S MB _ C L K 2
T13
Controller
Link
P E G _A _ C L K R Q# / GP I O 4 7
PE R N7
PER P7
P E T N7
PETP7
PCH _ B T _ E N # 2 9
CL K O UT _ P C IE 3 N
CL K O UT _ P C IE 3 P
C L K I N _ D MI _ N
C L K I N _D M I _P
C L K I N _B C L K _ N
C L K I N _ B C LK _P
C L K I N _ D O T _9 6 N
C L K I N _ D OT _ 9 6P
C L K IN _ S A T A _ N / CK S S C D_ N
C L K I N _ S A T A _ P / C K S S C D _P
RE F CL K 1 4 IN
H 1
100-MHz Gen2 differential clock to PCIe Graphics
device.
P E G _ C LK R E Q #
AD 4 3
AD 4 5
AN 4
AN 2
AT1
AT3
C L K_ EXP_ N
C L K_ EXP_ P
P C H _ C L K _ D P _N _ R
P C H _ C L K _ D P _P _ R
R 26 4
R 26 5
* 10 m i l _ sh o rt
* 10 m i l _ sh o rt
AW 2 4
B A 24
C L K _ P C IE _ IC H# 2
C L K _ P C IE _ IC H 2
AP 3
AP 1
C L K _ B U F _ B C LK _N
C L K _ B U F _ B C LK _P
F18
E1 8
C L K _ B U F _ D O T 9 6_ N
C L K _ B U F _ D O T 9 6_ P
AH 1 3
AH 1 2
4
4
CL K _ D P _ N 4
CL K _ D P _ P 4
100-MHz differential clock from PCH to Processor.
Connect to PEG_CLK#/PEG_CLK pins of the
processo
2
2
2
2
C3 9 8
C L K_ SATA# 2
C L K_ SATA 2
P4 1
C L K _ BU F _ RE F 1 4 2
R 266
2 2 p _5 0 V _ N P O _0 4
X5
P C I E C L K R Q3 # / GP I O 2 5
C L K I N _ P C I L O OP B A C K
J42
1 M _ 04
C L K _ P C I_ F B 1 8
X 8 A 0 2 5 0 0 0F G1 H _2 5 M H z
2
2 3 W L A N _ C LK R E Q #
S M B C LK
S M B D A TA
PE R N2
PER P2
P E T N2
PETP2
A M5 1
A M5 3
2 5 C L K _ P C I E _ GL A N #
2 5 C L K _ P C I E _ GL A N
L A N _ CL K R E Q #
CL K O UT _ P C IE 4 N
CL K O UT _ P C IE 4 P
X TA L2 5 _ I N
X T A L 2 5 _ OU T
M9
P C I E C L K R Q4 # / GP I O 2 6
A J5 0
A J5 2
P C I E C L K R Q5 #
H6
AK5 3
AK5 1
P E G_ B _ C L K R Q#
P1 3
CL K O UT _ P C IE 5 N
CL K O UT _ P C IE 5 P
P C I E C L K R Q5 # / GP I O 4 4
CL K O UT _ P E G _ B _ N
CL K O UT _ P E G _ B _ P
P E G _B _C L K R Q# / G P I O 5 6
AH 5 1
AH 5 3
X T A L 2 5 _I N
X T A L 2 5 _O U T
A F 38
X C L K _R C OM P
X C L K _ R C O MP
Clock Flex
B.Schematic Diagrams
2 3 P CIE _ R X N3 _ W L A N
2 3 P CIE _ R X P 3 _ W L A N
2 3 P C IE _ T X N3 _ W L A N
2 3 P C IE _ T X P 3 _ W L A N
C1 2 4
C1 2 5
AW 3 0
BA3 0
BC3 0
BD3 0
B9
1
AR D
A RD
AR D
A RD
SMBus
E W _C
EW _ C
E W _C
EW _ C
PEG
P C I E _ R X N 2 _N
P C IE _ RX P 2 _ N
P C I E _T X N 2 _N
P C I E _T X P 2 _ N
S MB A L E R T # / GP I O 1 1
From CLK BUFFER
23
23
23
23
PE R N1
PER P1
P E T N1
PETP1
PCI-E*
B G3 0
B J3 0
BF 2 9
BH2 9
C3 9 5
R 87
9 0 . 9_ 1 % _ 0 4
1 . 1 V S _V T T
T45
C L K O U T F L E X 0 / GP I O 6 4
C L K O U T F L E X 1 / GP I O 6 5
C L K O U T F L E X 2 / GP I O 6 6
C L K O U T F L E X 3 / GP I O 6 7
P4 3
T42
N 50
I b ex P ea k -M _ R e v 0 _ 9
3 .3 V S
2 , 1 0, 1 1 , 1 2 , 1 3 , 1 4 , 1 6, 1 7 , 1 8 , 1 9 , 2 0 , 2 1, 23 , 2 4 , 2 5 , 2 6 , 2 7, 28 , 2 9 , 3 0 , 3 1 , 3 5, 36
1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4 , 1 6 , 19 , 2 0 , 2 1 , 3 4 , 3 5 , 36
3 .3 V
3 , 4 , 12 , 1 4 , 1 6 , 1 8 , 1 9 , 20 , 2 1 , 2 3 , 2 4 , 2 5 , 2 9, 3 0 , 3 1 , 3 3 , 3 4 , 3 5
B - 16 IBEXPEAK - M 2/9
90.9-O ? % pullup
to +VccIO
(1.05V, S0 rail)
2 2 p _5 0 V _ N P O _0 4
3 .3 V
Schematic Diagrams
IBEXPEAK - M 3/9
IBEXPEAK - M (DMI,FDI,GPIO)
U2 0 C
XN
XN
XN
XN
0
1
2
3
3
3
3
3
D
D
D
D
MI _ R
MI _ R
MI _ R
MI _ R
XP
XP
XP
XP
0
1
2
3
3
3
3
3
DM
DM
DM
DM
I _ T XN
I _ T XN
I _ T XN
I _ T XN
0
1
2
3
3
3
3
3
DM
DM
DM
DM
I _ T XP
I _ T XP
I _ T XP
I _ T XP
0
1
2
3
4 9 . 9 _ 1 % _0 4
B C2 4
B J2 2
AW 2 0
B J2 0
B D2 4
B G2 2
BA2 0
B G2 0
BE2 2
BF2 1
B D2 0
BE1 8
B D2 2
B H2 1
B C2 0
B D1 8
B H2 5
D MI _ C OM P _ R
BF2 5
D
D
D
D
M
M
M
M
I0 RXN
I1 RXN
I2 RXN
I3 RXN
D
D
D
D
M
M
M
M
I0 RXP
I1 RXP
I2 RXP
I3 RXP
D
D
D
D
M
M
M
M
I 0 TX N
I 1 TX N
I 2 TX N
I 3 TX N
D
D
D
D
M
M
M
M
I 0 TX P
I 1 TX P
I 2 TX P
I 3 TX P
F
F
F
F
F
F
F
F
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
DI_ R
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_R
_R
_R
_R
_R
_R
_R
_R
XN
XN
XN
XN
XN
XN
XN
XN
0
1
2
3
4
5
6
7
XP0
XP1
XP2
XP3
XP4
XP5
XP6
XP7
F DI_ IN T
D M I _ Z C O MP
FDI
MI _ R
MI _ R
MI _ R
MI _ R
DMI
R2 5 9
D
D
D
D
F D I_ F SY NC 0
F D I_ F SY NC 1
D M I _ I R C OM P
F DI_ L S Y NC 0
F DI_ L S Y NC 1
B A 18
BH 1 7
BD 1 6
BJ 1 6
B A 16
B E 14
B A 14
BC 1 2
FD
FD
FD
FD
FD
FD
FD
FD
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
0
1
2
3
4
5
6
7
3
3
3
3
3
3
3
3
B B 18
B F 17
BC 1 6
BG 1 6
AW 1 6
BD 1 4
B B 14
BD 1 2
FD
FD
FD
FD
FD
FD
FD
FD
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
I _ T XP
0
1
2
3
4
5
6
7
3
3
3
3
3
3
3
3
BJ 1 4
F DI_ IN T 3
B F 13
F DI_ F S Y N C0 3
BH 1 3
F DI_ F S Y N C1 3
BJ 1 2
F DI_ L S Y NC 0 3
BG 1 4
Sheet 16 of 40
IBEXPEAK - M 3/9
F DI_ L S Y NC 1 3
FOR RESET SWITCH
R 11 1
1 0 K_ 0 4
S Y S _ RE S E T #
T6
S Y S _ P W R OK
M6
S B _ P W RO K
B1 7
K5
P M _ MP W R O K
R2 9 1
1 0 K_ 0 4
A U X P P W R OK _ R
A1 0
EXT-LAN
D9
4 P M_ D R A M _ P W R GD
28
R SM RST #
R2 9 5
P W R _ B T N#
M1
S US _ P W R_ A C K
2 8 SU S_ PW R _ AC K
28
C1 6
R S MR S T #
1 0 K_ 0 4
P W R_ B T N #
P5
A C_ PR E SE N T
1 8 ,2 8 A C _ P RE S E N T
P7
A6
P M _ B A T L OW #
28
S W I#
S W I#
F1 4
S YS_ R ESET#
W A KE#
S YS _ P W RO K
C L K R U N # / GP I O3 2
System Power Management
3 .3 VS
P W R OK
M E P W RO K
L A N_ RS T #
D R A MP W R O K
R S M R S T#
S US _ P W R_ A C K / G P IO 3 0
P W R B T N#
J12
P CI E _ W A K E #
P CIE _ W A K E # 2 3 ,2 5
Y 1
P M_ C L K R U N #
P M_ C L K R U N # 2 4
P8
S4 _ STATE#
3 . 3V
S U S _ S T A T # / GP I O6 1
S U S C L K / GP I O6 2
S L P _ S 5 # / GP I O6 3
SL P_ S4 #
SL P_ S3 #
S LP _M #
A CP R E S E NT / G P IO 3 1
TP2 3
B A T L OW # / GP I O 7 2
P MS Y N C H
R I#
S LP _L A N #
S 4_ S T A T E # 2 4
P CIE _ W A K E #
R1 2 0
1K _0 4
P M_ S L P _ L A N #
R1 2 5
*1 0 K _ 0 4
S W I#
R1 2 8
10 K _ 0 4
S US _ P W R_ A C K
R2 8 0
10 K _ 0 4
P W R_ BT N #
R1 0 9
*1 0 K _ 0 4
A C_ P R E S E N T
R1 1 4
10 K _ 0 4
P M_ B A T L O W #
R2 9 2
8. 2K _0 4
P M_ C L K R U N #
R2 6 8
8. 2K _0 4
A L L _S Y S _ P W R G D
R1 3 9
10 K _ 0 4
F3
E4
H 7
P1 2
S U S C # 2 8 ,3 3
S US B #
SU SB#
2 3 , 2 8, 31
3 . 3V S
K8
N 2
BJ 1 0
F6
H _ P M_ S Y N C 4
P M_ S LP _L A N #
I b ex P e a k -M _R e v 0 _ 9
3 .3 V
3 .3 V
14
14
1 . 1 V S _V TT _ E N
6
4 , 36
D E L A Y _ P W R GD
8
A L L _ S Y S _ P W R GD
3 5 V G F X _ V OR E _ P G
U8 D
74 L V C 0 8 P W
R 135
* 1 0m i l _ sh o rt
P M _ MP W R O K
R 140
* 1 0m i l _ sh o rt
S B_ P W RO K
R 138
* 1 0m i l _ sh o rt
S Y S _ P W R OK
12
11
13
10
5
R 141
2
7
SU SB#
3
4
U 8C
7 4 L V C 08 P W
9
7
3 3 D D R 1 . 5 V _ P W R GD
4 , 3 3 , 3 4 1 . 1 V S _ V T T _ P W R GD
1
U8 B
7 4L V C 0 8 P W
14
3 .3 V
U 8A
7 4 L VC0 8 PW
14
3 .3 V
1 0 K_ 0 4
7
7
A L L _S Y S _ P W R G D
12 , 2 8
3 4 1 .1 VS _ V T T _ EN
R 13 7
2K _ 04
H _V TT P W R G D
4
ON
R 13 4
1 K_ 0 4
3 .3 V S
2, 10 , 1 1 , 1 2 , 1 3 , 14 , 1 5 , 1 7 , 1 8 , 1 9, 2 0 , 2 1 , 2 3 , 2 4, 25 , 2 6 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 5 , 36
3 .3 V
3, 4, 12 , 1 4 , 1 5 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 3 0 , 3 1, 3 3 , 3 4 , 3 5
1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4 , 15 , 1 9 , 2 0 , 2 1 , 3 4, 3 5 , 3 6
IBEXPEAK - M 3/9 B - 17
B.Schematic Diagrams
1 . 1 V S _V TT
3
3
3
3
Schematic Diagrams
IBEXPEAK - M 4/9
IBEXPEAK - M (LVDS,DDI)
U20D
SDVO_TVCLKI NN BJ46
SDVO_TVCLKINP BG46
L_BKLTCTL
SDVO_STALL N BJ48
SDVO_STALLP BG48
AB46
V48
L_CTRL_CLK
L_CTRL_DATA
R83
2.37K_1%_04
LVDS_IBG
AP39
AP41
LVD_IBG
LVD_VBG
12 LVDS- LCLKN
12 LVDS- LCLKP
LVDSA_CLK#
LVDSA_CLK
12 LVDS- L0N
12 LVDS- L1N
12 LVDS- L2N
BB47
BA52
AY48
AV47
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
12 LVDS- L0P
12 LVDS- L1P
12 LVDS- L2P
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
EMI
13
DAC_GREEN
13
DAC_RED
R105
*15mil_short
*33 p_50V_NPO_04R99
*15mil_short
DAC_GREEN_R
C176
DAC_RED_R
*33 p_50V_NPO_04R91
LVDSB_CLK#
LVDSB_CLK
AY53
AT49
AU52
AT53
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
DAC_BLUE_R
C180
C172
LVD_VREFH
LVD_VREFL
AV53
AV51
AP48
AP47
DAC_BL UE
SDVO_CTRLCLK
SDVO_CTRL DATA
*15mil_short
*33 p_50V_NPO_04
R1 04
R9 8
R9 2
NEAR PCH
15 0_1%_04
15 0_1%_04
15 0_1%_04
DAC_BLUE_R
DAC_GREEN_R
DAC_RED_ R
13 DAC_DDCACLK
13 DAC_DDCADATA
13
13
R88
1K_1%_04
DAC_HSYNC
DAC_VSYNC
DAC_I REF_R
AA52
AB53
AD53
V51
V53
Y53
Y51
AD48
AB51
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
DDPB_0 N
DDPB_0P
DDPB_1 N
DDPB_1P
DDPB_2 N
DDPB_2P
DDPB_3 N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRL DATA
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
DDPC_0 N
DDPC_0P
DDPC_1 N
DDPC_1P
DDPC_2 N
DDPC_2P
DDPC_3 N
DDPC_3P
3.3VS
HDMI _CTRL CLK 13
HDMI _CTRL DATA 13
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
PCH_DDPC_HPD
HDMIB_D2BN_C
HDMIB_D2BP_C
HDMIB_D1BN_C
HDMIB_D1BP_C
HDMIB_D0BN_C
HDMIB_D0BP_C
HDMIB_CLKBN_C
HDMIB_CLKBP_C
C132
C133
C118
C119
C120
C121
C122
C123
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
U50
U52
HDMI B_D2BN 13
HDMI B_D2BP 1 3
HDMI B_D1BN 13
HDMI B_D1BP 1 3
HDMI B_D0BN 13
HDMI B_D0BP 1 3
HDMI B_CLKBN 13
HDMI B_CLKBP 13
5VS
BC46
DDPD_AUXN
DDPD_ AUXP BD46
DDPD_HPD AT38
DDPD_0 N
DDPD_0P
DDPD_1 N
DDPD_1P
DDPD_2 N
DDPD_2P
DDPD_3 N
DDPD_3P
RN5
2. 2K_4P2R_04
3
2
4
1
Y49
AB49
BE44
DDPC_AUXN
DDPC_ AUXP BD44
DDPC_HPD AV40
DDPD_CTRLCLK
DDPD_CTRL DATA
CRT_DDC_CLK
CRT_DDC_DATA
T51
T53
BG44
DDPB_AUXN BJ44
DDPB_ AUXP
DDPB_HPD AU38
L VDS
Sheet 17 of 40
IBEXPEAK - M 4/9
BF45
SDVO_I NTN BH45
SDVO_INTP
PCH_DDPC_HPD
S
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
Q18
MTN7002ZHS3
D
PORTC_HPD 13
R339
100K_ 04
IbexPeak-M_Rev0_9
Connec t to GND
PCH_DDPC_HPD
R342
*0_04
PORTC_HPD
No Conn ect
Ext ernal Gra phics (P CH Integr ated Gra phics Dis able)
Extern al Graphi cs (PCH Integrat ed Graphi cs Disab le)
2,10,11, 12,13,14 ,15,16,1 8,19,20, 21,23,24, 25,26,27, 28,29,30 ,31,35,3 6 3.3VS
2, 13,20,21, 26,27,30 ,31,35,3 6 5VS
B - 18 IBEXPEAK - M 4/9
SD VO
L_CTRL_CLK
L_CTRL_DATA
D isp lay Por t B
*1 0K_04
*1 0K_04
D isp lay Por t C
R96
R97
AT43
AT42
13
L_DDC_ CLK
L_DDC_ DATA
D isp lay Por t D
AB48
Y45
C RT
B.Schematic Diagrams
L_BKLTEN
L_VDD_EN
Y48
G
12 P_DDC_CLK
12 P_DDC_DATA
3. 3VS
T48
T47
Digi tal Displ ay Inter face
12 BLON
12 NB_ENAVDD
Schematic Diagrams
IBEXPEAK - M 5/9
IBEXPEAK - M (PCI,USB,NVRAM)
U2 0E
Boot BIOS Location
0
1
0
1
LPC
Reserved
PCI
SPI
R11 6
*1 K_ 04
PC I_G NT#0
R11 8
*1 K_ 04
PC I_G NT#1
(NAND)
Understand the RED FONT define
R12 1
*1 K_04
PC I_ GNT#3
J50
G42
H47
G34
3. 3VS
4
RN2 3
3
8.2 K_8P4 R_0 4 2
1
4
RN1 2
3
8.2 K_8P4 R_0 4 2
1
4
RN2 2
3
8.2 K_8P4 R_0 4 2
1
5
6
7
8
5
6
7
8
5
6
7
8
INT_PIR QE#
PC I_ IRD Y#
I NT_ PIRQ D#
PCI_ FRAME#
PC I_ PER R#
PCI _LO CK#
PCI_ DEVSEL#
PC I_ SER R#
PCI _REQ #1
PC I_ TRD Y#
I NT_ PIRQ H#
PCI _REQ #0
4
RN2 4
3
8.2 K_8P4 R_0 4 2
1
4
RN2 0
3
8.2 K_8P4 R_0 4 2
1
I NT_ PIRQ G#
5
I NT_ PIRQ C#
6
7
INT_PIR QA#
8
PC I_ STOP#
5
INT_PIR QB#
INT_PIR QF#
6
PCI _REQ #3
7
8DG PU_PW M_SELEC T#
IN T_PI RQA#
IN T_PI RQB#
IN T_PI RQC #
IN T_PI RQD #
G38
H51
B37
A44
PCI_ REQ# 0
PCI_ REQ# 1
F51
A46
B45
M53
PCI_ REQ# 3
BA CKL IG HT CO NTR OL FR OM IG PU/ DG PU
PCI_ GN T#0
PCI_ GN T#1
DG PU_PWM_SELEC T#
PCI_ GN T#3
F48
K45
F36
H53
IN T_PI RQE#
IN T_PI RQF#
IN T_PI RQG #
IN T_PI RQH #
B41
K53
A36
A48
PCI_ SERR#
PCI_ PERR#
E44
E50
K6
PCI_ IR DY#
PIN PL T_RS T# to Buf fer
28
2 4 PCLK_ TPM
A42
H44
F46
C46
PCI_ LO CK#
D49
PCI_ STOP#
PCI_ TR DY#
D41
C48
M7
PME#
PLT_ RST#
2 4 PLT_RST#
1 5 CL K_ PCI _FB
2 8 PCLK_ KBC
PCI_ DEVSEL#
PCI_ FRAME#
R1 23
R1 19
22_ 04
22_ 04
R3 43
*22_ 04
CL K_ PCI_ FB_R
CL K_ PCI_ KBC_R
PC LK_TPM_PC H
D5
N52
P53
P46
P51
P48
NV_ DQS0
NV_ DQS1
NV_D Q0 / NV_ IO0
NV_D Q1 / NV_ IO1
NV_D Q2 / NV_ IO2
NV_D Q3 / NV_ IO3
NV_D Q4 / NV_ IO4
NV_D Q5 / NV_ IO5
NV_D Q6 / NV_ IO6
NV_D Q7 / NV_ IO7
NV_D Q8 / NV_ IO8
NV_D Q9 / NV_ IO9
NV_ DQ1 0 / NV_I O10
NV_ DQ1 1 / NV_I O11
NV_ DQ1 2 / NV_I O12
NV_ DQ1 3 / NV_I O13
NV_ DQ1 4 / NV_I O14
NV_ DQ1 5 / NV_I O15
NVRAM
PCI_GNT#1
0
0
1
1
NV_ CE#0
NV_ CE#1
NV_ CE#2
NV_ CE#3
NV_ AL E
N V_CL E
NV_R COMP
PCI
PCI_GNT#0
AD 0
AD 1
AD 2
AD 3
AD 4
AD 5
AD 6
AD 7
AD 8
AD 9
AD 10
AD 11
AD 12
AD 13
AD 14
AD 15
AD 16
AD 17
AD 18
AD 19
AD 20
AD 21
AD 22
AD 23
AD 24
AD 25
AD 26
AD 27
AD 28
AD 29
AD 30
AD 31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
N V_RB#
NV_W R#0 _RE#
NV_W R#1 _RE#
N V_WE# _CK0
N V_WE# _CK1
PI RQ A#
PI RQ B#
PI RQ C#
PI RQ D#
REQ0#
REQ1# / G PI O5 0
REQ2# / G PI O5 2
REQ3# / G PI O5 4
GNT0#
GNT1# / GPIO 51
GNT2# / GPIO 53
GNT3# / GPIO 55
PI RQ E# / GPI O2
PI RQ F# / GPI O3
PI RQ G# / GPIO 4
PI RQ H# / GPIO 5
PC IR ST#
SER R#
PER R#
IRD Y#
PAR
DEVSEL #
FR AME#
USB
Boot BIOS Strap
USBP0N
U SBP0 P
USBP1N
U SBP1 P
USBP2N
U SBP2 P
USBP3N
U SBP3 P
USBP4N
U SBP4 P
USBP5N
U SBP5 P
USBP6N
U SBP6 P
USBP7N
U SBP7 P
USBP8N
U SBP8 P
USBP9N
U SBP9 P
USBP10N
USBP10 P
USBP11N
USBP11 P
USBP12N
USBP12 P
USBP13N
USBP13 P
PL OCK#
USBRBI AS#
STOP#
TRD Y#
U SBR BIAS
PME#
PL TR ST#
CLKOU T_ PCI0
CLKOU T_ PCI1
CLKOU T_ PCI2
CLKOU T_ PCI3
CLKOU T_ PCI4
OC 0# / GPI O59
OC 1# / GPI O40
OC 2# / GPI O41
OC 3# / GPI O42
OC 4# / GPI O43
O C5 # / G PIO9
OC 6# / GPI O10
OC 7# / GPI O14
AY 9
BD 1
AP1 5
BD 8
AV9
BG 8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD 6
BB7
BC 8
BJ 8
BJ 6
BG 6
BD 3
AY 6
AU 2
NV_ RCO MP
R 26 3
Sheet 18 of 40
IBEXPEAK - M 5/9
3 2.4 _1 %_ 04
AV7
AY 8
AY 5
AV1 1
BF5
H 18
J 18
A1 8
C 18
N 20
P2 0
J 20
L 20
F2 0
G 20
A2 0
C 20
M22
N 22
B2 1
D 21
H 22
J 22
E2 2
F2 2
A2 2
C 22
G 24
H 24
L 24
M24
A2 4
C 24
B2 5
U SB_ PN0
U SB_ PP0
U SB_ PN1
U SB_ PP1
U SB_ PN2
U SB_ PP2
U SB_ PN3
U SB_ PP3
U SB_ PN4
U SB_ PP4
U SB_ PN5
U SB_ PP5
30
30
30
30
23
23
23
23
30
30
24
24
USB PORT0
USB PORT1
WLAN
NEW CARD
USB PORT2
CCD
? ? ? ?
USB_ BI AS
U SB_ PN9 2 4
U SB_ PP9 2 4
3G
U SB_ PN11 29
U SB_ PP1 1 2 9
BT
R 29 6
2 2.6 _1 %_ 06
D 25
N 16
J 16
F1 6
L 16
E1 4
G 16
F1 2
T15
USB_ OC# 23
USB_ OC# 45
USB_ OC# 67
USB_ OC# 89
USB_ OC# 101 1
USB_ OC# 121 3
GPIO 14
USB_O C#0 1 30
USB_O C#2 3 23
3. 3V
USB_O C#8 9 15
R 12 4
R 11 0
R 11 3
1 0K_0 4
1 0K_0 4
*0_ 04
AC_ PRESENT 1 6,2 8
I bex Peak -M_Re v 0_9
3.3 V
3 .3 VS
*0. 1u _10 V_X7 R_ 04
5
C1 91
U6
MC74 VHC1 G0 8DFT1G
1
4
15 PC H_ UPEK_ IN IT#
5
6
7
8
4
3
2
1
RN1 4
10K_ 8P4R _04
BUF_ PL T_ RST# 4 ,2 3, 25, 28
2
3
PL T_R ST#
USB_OC #6 7
USB_OC #1 011
USB_OC #4 5
PCH _UPEK_I NI T#
R 117
1 00K_ 04
2, 10, 11 ,12 ,1 3,1 4, 15, 16 ,1 7,1 9, 20, 21 ,23 ,2 4, 25, 26 ,27 ,2 8,2 9, 30, 31 ,3 5,3 6 3. 3VS
3 ,4, 12 ,1 4,1 5, 16, 19 ,20 ,2 1, 23, 24 ,25 ,2 9,3 0, 31, 33 ,3 4,3 5 3. 3V
IBEXPEAK - M 5/9 B - 19
B.Schematic Diagrams
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
Schematic Diagrams
IBEXPEAK - M 6/9
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
U20F
EDP_CARD_DET#
28
EDP_CARD_DET#
28
27
D37
SCI#
R349
SCI#
J32
PCH_M
UTE#
F10
R101
10K_04
*10K_04
B IO S R E CO VE R Y
D IS A BL E -- -- N O S TU FF (D E FA U LT )
Sheet 19 of 40
IBEXPEAK - M 6/9
R102
3.3VS
R350
*10K_04
AA2
R351
*10K_04
F38
BIO
S_
REC
*0_04
Y7
E NA B LE - -- -- S TU F F
H10
R277
3.3VS
*10K_04
C RB / SV DE T EC T
N O S TU F F [ DE TE C T]
12
CRB_SV_DET
SB_BLO
N
SB_BLON
SPI_CS#2
V13
ST
P_PCI #
M11
1
00K_04
GPIO35
R352
*1K_04
DGPU_PRSNT#
3.3VS
R95
10K_04
R100
CRB_SV_DET
*0_04
AB7
AB13
V3
DRAM
RST_CTRL
SV_SET_UP
R267
3 CRIT_TEMP_REP#
3.3V
R126
LAN_PHY_PWR_CTRL / G
PIO
12
A20G
AT
E
AH45
AH46
*0_04 CRIT_
TEM
P_REP#_R
1
0K_
04
PCH_G
PIO
57
R272
3.3VS
G
A20
AM
3
SATA4G
P / GPIO16
CLKOUT_
BCLK0_N / CLKOUT_PCIE8N
TACH0 / GPIO1
7
CLKOUT_BCLK0_P/ CLKOUT
_PCIE8
P
SCLOCK / GPIO22
MEM_LED / G
PIO
24
GPIO27
PECI
RCIN#
GPIO28
28
PROCPWRGD
THRMTRI P#
BCLK_CPU_
N 4
AM
1
BG
10
T1
BCLK_CPU_
P 4
H_PECI_R
R274
10K_04
R254
*10K_04
R258
0_04
BD10
1.1VS_VT
T
H_PECI 4,28
3.3VS
KBC_RST# 28
H_CPUPWRGD 4
BE10
R257
56_04
R253
56_04
1.1VS_VTT
H_THRMTRIP# 4
ST
P_PCI # / G
PIO
34
Connected to PCH (THRMTRIP#)
SATACL
KREQ
# / GPIO35
SATA2G
P / GPIO36
TP1
SATA3G
P / GPIO37
TP2
SL
OAD / GPIO38
TP3
SDATAO
UT0 / GPIO39
TP4
PCIECLKRQ6# / G
PIO
45
TP5
PCIECLKRQ7# / G
PIO
46
TP6
SDATAO
UT1 / GPIO48
TP7
SATA5G
P / GPIO49
TP8
GPIO57
TP9
BA22
Routing guidelines available in
Calpella Design Guide.
AW22
NOTE: CRB uses a 54.9 O ? %
series resistor and 56-O pull-up.
BB22
AY45
AY46
AV43
AA4
F8
10
K_04
GPIO15
F1
AB6
AF48
AF47
U2
P3
H3
4, 9 DRAMRST_CTRL
1K_04
V6
SV_SET_UP
MFG_M
ODE
R107
AB12
R276
3.3VS
CLKOUT_PCIE7N
CLKOUT
_PCIE7
P
GPIO8
K9
T7
BIO
S_
REC
3.3VS
TACH2 / GPIO6
TACH3 / GPIO7
HOST_ALERT
#1
3.3VS
CLKOUT_PCIE6N
CLKOUT
_PCIE6
P
TACH1 / GPIO1
PCH_
MUTE#
3.3V
BM
BUSY# / GPIO0
AV45
AF13
HOST_ALERT
#1
M18
N18
TP10
PCH_MUTE#
SPI_CS#2
DRAMRST
_CTRL
3.3VS
RN2
1
10K_8P4R_04
1
8
2
7
3
6
4
5
RN4
10K_8P4R_04
1
8
2
7
3
6
4
5
R103
SCI#
SMI#
MFG_MODE
STP_PCI#
DG
PU_HPD_
I NTR#
CRIT_TEMP_REP#_R
DG
PU_PRSNT#
GPIO35
*10K_04
DGPU_PRSNT#
LOW: DGPU PRESENT
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
TP11
RSVD
RN9
10K_8P4R_04
1
8
2
7
3
6
4
5
AJ24
AK41
TP12
TP13
TP14
TP15
TP16
TP17
TP18
NCTF
B.Schematic Diagrams
*0_04
DGPU_HPD_INTR#
SM
I#
DGPU HDP (NV CONTROL BYSELF)
R269
C38
MISC
1K_1%_04
SM
I#
GPIO
R270
3.3VS
Y3
S_GPIO CHANGE TO EDP_CARD_DET#
CPU
0213
TP19
NC_1
NC_2
NC_3
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
NC_4
NC_5
INIT3_3V#
TP24
T39
P6
C10
I bexPeak-M_Rev0_9
2,4,6,7,14,15,16
, 20,21,34,35,36 1.1VS_VTT
3,4,12,14, 1
5,16,18,20,21,23,24,25,29
, 30,31,33,34,35 3.3V
2
, 10,11,12,13,14,15,16,17, 1
8,20,21,23,24,25,26,27,28
, 29,30,31,35,36 3.3VS
B - 20 IBEXPEAK - M 6/9
Schematic Diagrams
IBEXPEAK - M 7/9
IBEXPEAK - M (POWER)
3 .3 V S
R 90
V C CA DA C [1 ]
L12
H C B 1 6 0 8K F -1 2 1 T 25
5 VS
U5
.
AE5 0
4
AE5 2
C 400
C 399
C 47 0
C1 5 1
C 139
C 152
R 80
AF5 3
0 . 0 1 u _ 5 0 V _ X 7R _ 0 4
1 0u _ 6 . 3 V _ X 5 R _0 6
2 2 u _ 6 . 3 V _ X 5 R _ 08
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
[ 1 0]
[ 1 1]
[ 1 2]
[ 1 3]
[ 1 4]
[ 1 5]
0 . 1 u _ 1 0 V _ X 7 R _ 04
RE
RE
RE
RE
RE
RE
RE
RE
RE
RE
RE
RE
RE
RE
RE
2 2 u _6 . 3 V _X 5 R _ 0 8
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1 7 .4 K _ 1 % _ 0 4
OU T
IN
5
C 15 6
V C CA DA C [2 ]
V S S A _ DA C [1 ]
AF5 1
V S S A _ DA C [2 ]
3 . 3 V S _ V C C A _ LV D
V CC A L V D S
R8 6
A H 38
A H 39
3. 3V S
3
R 81
SH D N
A DJ
G N D
1
2
S C 1 5 63 I S K -3 . 0 T R T
1 0 K_ 1 % _ 0 4
*1 5 m i l _ sh o rt _ 0 6
C 1 62
V SSA_ L VD S
AK 2 4
L29
* B K P 10 0 5 H S 1 2 1 _0 4
BJ 2 4
LVDS
1 0 u _ 6. 3 V _X 5 R _ 0 6
1 .1 VS_ VC C APL L _ EXP
V C C I O[ 2 4 ]
V C CA PL L E X P
VC
VC
VC
VC
CT X _ L V D
CT X _ L V D
CT X _ L V D
CT X _ L V D
V C C3 _ 3 [2 ]
.
C 378
C1 6 6
C 167
C 142
1 0 u _6 . 3 V _X 5 R _ 0 6
1 u_ 6 . 3 V _ X 5 R _ 04
1 u _ 6 .3 V _ X 5 R_ 0 4
C1 4 7
1 u _ 6 . 3 V _ X 5R _ 0 4
1 u _6 . 3 V _X 5 R _ 0 4
AN 3 0
AN 3 1
1 . 5 V S _ 1. 8V S
3 .3 V S
AN 3 5
1 .1 V S _ V T T
1 .1 V S _ VC C A P L L _ F DI
L28
* H C B 1 0 0 5 K F - 12 1 T 2 0
AT2 2
O[ 2 5 ]
O[ 2 6 ]
O[ 2 7 ]
O[ 2 8 ]
O[ 2 9 ]
O[ 3 0 ]
O[ 3 1 ]
O[ 3 2 ]
O[ 3 3 ]
O[ 3 4 ]
O[ 3 5 ]
O[ 3 6 ]
O[ 3 7 ]
O[ 3 8 ]
O[ 3 9 ]
O[ 4 0 ]
O[ 4 1 ]
O[ 4 2 ]
O[ 4 3 ]
O[ 4 4 ]
O[ 4 5 ]
O[ 4 6 ]
O[ 4 7 ]
O[ 4 8 ]
O[ 4 9 ]
O[ 5 0 ]
O[ 5 1 ]
O[ 5 2 ]
O[ 5 3 ]
C1 4 6
C 14 5
C 14 1
C 140
0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
0 . 0 1 u _5 0 V _ X 7 R _ 04
1 0 u _6 . 3 V _X 5 R _ 0 6
1 0 u _ 6 . 3 V _ X 5R _ 0 6
A D 35
3. 3V S
C1 6 5
AT2 4
1. 1V S _ V T T
AT1 6
V C C DM I[ 1 ]
V C C DM I[ 2 ]
A U 16
C 1 34
V C C I O[ 5 4 ]
V C C I O[ 5 5 ]
V C C3 _ 3 [1 ]
V C CV RM [1 ]
FDI
V C C I O[ 1 ]
I b e x P e a k -M_ R e v 0 _ 9
1u _ 6 . 3 V _ X 5 R _ 0 4
VC
VC
VC
VC
VC
VC
VC
VC
VC
C
C
C
C
C
C
C
C
C
PN
PN
PN
PN
PN
PN
PN
PN
PN
A ND
A ND
A ND
A ND
A ND
A ND
A ND
A ND
A ND
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
A M 16
AK1 6
AK2 0
AK1 9
AK1 5
AK1 3
A M 12
A M 13
A M 15
V _ N V R A M_ V C C Q
1 .8 V S
R 76
C1 5 8
* 1 5 m il _ s h o rt _ 0 6
0 . 1 u _1 0 V _ X 7 R _0 4
3 .3 V S
V C C ME 3 _ 3 [ 1 ]
V C C ME 3 _ 3 [ 2 ]
V C C ME 3 _ 3 [ 3 ]
V C C ME 3 _ 3 [ 4 ]
AM 8
AM 9
AP1 1
AP9
3 .3 V S
* 0 _0 4
R 75
3 .3 V
V C C ME 3 . 3 V
R 79
*1 5 m i l_ s h o rt _ 0 6
R 82
* 0_04
C 14 4
0 . 1 u _ 10 V _X 7 R _ 0 4
1 . 1 V S _V C C D P L L _F D I
R2 5 5
* 1 5 m il _ s h o rt _ 0 6
3, 4, 12 , 1 4 , 1 5 , 1 6 , 1 8 , 1 9 , 2 1 , 2 3, 24 , 2 5 , 2 9 , 3 0 , 3 1 , 3 3 , 3 4 , 3 5
2 3 ,3 1 ,3 6
2 , 1 3, 17 , 2 1 , 2 6 , 2 7 , 3 0 , 3 1 , 3 5 , 3 6
21
7 ,3 3
2 , 1 0 , 1 1 , 1 2 , 1 3 , 1 4 , 1 5, 16 , 1 7 , 1 8 , 1 9 , 2 1 , 2 3 , 2 4 , 2 5, 26 , 2 7 , 2 8 , 2 9 , 3 0 , 3 1 , 3 5 , 3 6
2, 4, 6, 7, 14 , 1 5 , 1 6 , 1 9 , 2 1 , 3 4 , 3 5 , 3 6
1 .5 V S
Sheet 20 of 40
IBEXPEAK - M 7/9
1. 5V S _ 1 . 8 V S
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6
1 .1 V S _ V T T
V C C3 _ 3 [4 ]
VC C V RM [2 ]
V C CF DI P L L
AM 2 3
.
0 . 1 u _1 0 V _ X 7 R _0 4
BJ 1 8
C3 7 7
AB3 4
1 .8 VS
L11
H C B 1 6 0 8K F -1 2 1 T 25
V C C3 _ 3 [3 ]
HVCMOS
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
DMI
C 38 1
1 . 8 V S _ V C C TX _ L V D
AP4 3
AP4 5
AT4 6
AT4 5
AB3 5
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
NAND / SPI
1 .1 VS_ VT T
AN 2 0
AN 2 2
AN 2 3
AN 2 4
AN 2 6
AN 2 8
BJ 2 6
BJ 2 8
AT2 6
AT2 8
AU 2 6
AU 2 8
AV 2 6
AV 2 8
AW 2 6
AW 2 8
BA 2 6
BA 2 8
BB 2 6
BB 2 8
BC 2 6
BC 2 8
BD 2 6
BD 2 8
BE 2 6
BE 2 8
BG 2 6
BG 2 8
BH 2 7
PCI E*
1 0 u _ 6 .3 V _ X 5 R_ 0 6
S[1 ]
S[2 ]
S[3 ]
S[4 ]
1. 8V S
3 .3 V
1 .5 V S
5 VS
1 .5 V S _ 1 .8 V S
1 .8 V S
3 .3 V S
1 .1 V S _ VT T
1 .5 V S _ 1 .8 V S
R 256
R 252
*1 5 m i l _s h o rt _ 0 6
*0 _ 0 4
IBEXPEAK - M 7/9 B - 21
B.Schematic Diagrams
1 .1 VS_ VT T
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
0 . 1 u _ 1 0 V _ X 7 R _ 04
1 u _ 6 . 3 V _ X 5R _ 0 4
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
CRT
1 0 u _ 6 .3 V _ X 5 R_ 0 6
AB 2 4
AB 2 6
AB 2 8
AD 2 6
AD 2 8
AF 2 6
AF 2 8
AF 3 0
AF 3 1
AH 2 6
AH 2 8
AH 3 0
AH 3 1
AJ 3 0
AJ 3 1
VCC CORE
C1 5 7
V C C A _D A C _ 3 . 3 V S
POWER
U 2 0G
C 182
1 u _ 6. 3V _ X 5 R _ 0 4
1 .1 V S _ V T T
*0 _ 0 6
Schematic Diagrams
IBEXPEAK - M 8/9
V ol ta ge Ra il V ol tag e
IBEXPEAK - M (POWER)
1. 1 V S _ V C C A _ C L K
L32
*H C B 1 0 0 5K F -12 1 T 20
U2 0 J
52mA
1 .1 VS _ V T T
C 3 91
C 39 2
1 0 u _6 . 3 V _ X 5R _0 6
* 0. 1 u _ 10 V _ X 5 R _ 04
A P 51
A P 53
A F 23
320mA
A F 24
1 . 1 V S _ V TT
PO WE R
VC CAC L K[1 ]
VC CAC L K[2 ]
V C C L A N [ 1]
V C C L A N [ 2]
C 1 49
Y 20
T P _ P C H _V C C D S W
1 u _ 6. 3 V _ X 5 R _ 04
D CP S U S B Y P
C 17 8
A D 38
VC CM E[1 ]
0 . 1 u _1 0 V _ X7 R _0 4
C 15 4
A F 43
2 2 u _6 . 3 V _ X 5R _0 8
1 u _ 6. 3 V _ X 5R _ 04
A F 41
A F 42
V 39
Sheet 21 of 40
IBEXPEAK - M 8/9
C 3 80
C 14 8
2 2 u _6 . 3 V _ X 5R _0 8
1 u _ 6. 3 V _ X 5R _ 04
V 41
V 42
Y 39
Y 41
Y 42
1 .1 V S_ VT T
C 1 83
1 . 1V S _V C C A _ A _ D P L
L 31
H C B 1 00 5 K F -1 2 1T 2 0
0 . 1u _ 1 0V _X 7 R _ 0 4
V9
V CCR T CE X T
VC CM E[3 ]
VC CM E[4 ]
VC CM E[5 ]
VC CM E[6 ]
VC CM E[7 ]
VC CM E[8 ]
VC CM E[9 ]
V C C M E [ 1 0]
V C C M E [ 1 1]
V C C M E [ 1 2]
D CP R T C
1 . 5 V S _ 1. 8 V S
C3 9 3
C 3 89
22 u _ 6. 3 V _ X 5R _ 08
1u _ 6. 3V _ X 5 R _ 0 4
+ C3 9 4
R2 6 0
*2 2 0u _ 4 V _V _B
68mA
*0 _ 0 4
L 30
H C B 1 00 5 K F -1 2 1T 2 0
1 . 1 V S _ V C C A _B _D P L
C3 8 6
C 3 85
22 u _ 6. 3 V _ X 5R _ 08
1u _ 6. 3V _ X 5 R _ 0 4
69mA
+ C3 9 0
A U 24
B B 51
B B 53
B D 51
B D 53
*2 2 0u _ 4 V _V _B
C1 6 0
1 u _ 6. 3 V _ X 5R _ 04
A H 23
A J 35
A H 35
C1 3 8
1 u _ 6. 3 V _ X 5R _ 04
A F 34
C1 6 3
1 u _ 6. 3 V _ X 5R _ 04
VCCIO 3062mA
A H 34
1 .1 VS _ V T T
A F 32
V 12
C 1 81
C 1 79
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
V C C V R M[ 3 ]
V C C A D P L LA [ 1]
V C C A D P L LA [ 2]
V C C A D P L LB [ 1]
V C C A D P L LB [ 2]
V C C I O [ 2 1]
V C C I O [ 2 2]
V C C I O [ 2 3]
[5 ]
[6 ]
[7 ]
[8 ]
V C C S U S 3_ 3 [ 1 ]
V C C S U S 3_ 3 [ 2 ]
V C C S U S 3_ 3 [ 3 ]
V C C S U S 3_ 3 [ 4 ]
V C C S U S 3_ 3 [ 5 ]
V C C S U S 3_ 3 [ 6 ]
V C C S U S 3_ 3 [ 7 ]
V C C S U S 3_ 3 [ 8 ]
V C C S U S 3_ 3 [ 9 ]
V C C S U S 3 _3 [ 1 0 ]
V C C S U S 3 _3 [ 1 1 ]
V C C S U S 3 _3 [ 1 2 ]
V C C S U S 3 _3 [ 1 3 ]
V C C S U S 3 _3 [ 1 4 ]
V C C S U S 3 _3 [ 1 5 ]
V C C S U S 3 _3 [ 1 6 ]
V C C S U S 3 _3 [ 1 7 ]
V C C S U S 3 _3 [ 1 8 ]
V C C S U S 3 _3 [ 1 9 ]
V C C S U S 3 _3 [ 2 0 ]
V C C S U S 3 _3 [ 2 1 ]
V C C S U S 3 _3 [ 2 2 ]
V C C S U S 3 _3 [ 2 3 ]
V C C S U S 3 _3 [ 2 4 ]
V C C S U S 3 _3 [ 2 5 ]
V C C S U S 3 _3 [ 2 6 ]
V C C S U S 3 _3 [ 2 7 ]
V C C S U S 3 _3 [ 2 8 ]
V C C I O[ 5 6 ]
V 5 REF _ S U S
1 .1 V _ INT _ V CC S US
Y 22
V 5 RE F
V C C 3_ 3 [ 8 ]
V C C 3_ 3 [ 9 ]
V C C 3 _3 [ 1 0 ]
V C C 3 _3 [ 1 1 ]
V C C 3 _3 [ 1 2 ]
V C C 3 _3 [ 1 3 ]
VC CIO [2 ]
0 . 1 u_ 1 0 V _ X7 R _ 0 4
3. 3 V _ V C C P U S B
R 10 6
* 15 m i _l s ho rt _ 0 6
C 18 4
0 . 1 u_ 1 0 V _ X7 R _ 0 4
1 . 1 V S _ V TT
5 V _ P C H _V C C 5 R E F S U S
D 11
C
U2 3
V2 3
R B 5 5 1V 3 0
A
R1 2 2
F24
3 .3 V
< 1 ( mA )
0.3 57
0.0 52
V cc AD AC
V cc AD PL LA
3. 3
1. 05
0.0 69
0.0 68
V cc AD PL LB
V cc ap ll EXP
1. 05
1. 05
0.0 69
0.0 40
V cc Co re
V cc DM I
V cc DM I
V cc FD IP LL
V cc IO
V cc LA N
V cc ME
V cc ME 3_ 3
1. 05
1. 05
1. 1
1. 05
1. 05
1. 05
1. 05
3. 3
1.4 32
0.0 58
0.0 61
0.0 37
3.0 62
0.3 20
1.8 49
0.0 85
V cc pN AN D
V cc RT C
1. 8
3. 3
0.1 56
2 ( mA )
V cc SA TA PLL
V cc Su s3 _3
1. 05
3. 3
0.0 31
0.1 63
V cc Su sH DA
V cc VR M
V cc VR M
V cc AL VD S
V cc TX _L VDS
3. 3
1. 8/1 .5
1. 05
3. 3
1. 8
0.0 06
0.1 96
< 1 ( mA )
< 1 ( mA )
0.0 59
5V
1 0 0_ 1 % _0 4
C 18 8
D1 0
C
R B 5 51 V 3 0
A
R 1 15
K4 9
J 38
1 00 _ 1 %_ 0 4
3 . 3V S
5V S
3 .3 VS
1 u_ 6 . 3 V _ X5 R _ 0 4
L 38
C 17 5
M3 6
0 . 1 u_ 1 0 V _ X7 R _ 0 4
N3 6
P3 6
3 .3 VS
C 18 6
U3 5
A D1 3
V C C 3 _3 [ 1 4 ]
VC CIO [3 ]
L33
*H C B 1 0 0 5K F -12 1 T 20
1. 1 V S _ V C C A P L L
VC CIO [4 ]
V C CS A T A P L L [1 ]
V C CS A T A P L L [2 ]
D CP S S T
D CP S U S
U 20
C 18 5
V 15
V 16
0 . 1 u _1 0 V _ X7 R _0 4
<1mA
1 . 1 V S _ V TT
Y 16
A T 18
V C C S U S 3 _3 [ 2 9 ]
V C C S U S 3 _3 [ 3 0 ]
V C C S U S 3 _3 [ 3 1 ]
V C C S U S 3 _3 [ 3 2 ]
V C C 3 _ 3 [ 5]
V C C 3 _ 3 [ 6]
V C C 3 _ 3 [ 7]
0 . 1 u _1 0 V _ X7 R _0 4
2mA
RT C V CC
C 1 92
C 19 3
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X7 R _0 4
A 12
V C C I O[ 1 0 ]
V C C I O[ 1 1 ]
V C C I O[ 1 2 ]
VCC
VCC
VCC
VCC
I O[ 1 3 ]
I O[ 1 4 ]
I O[ 1 5 ]
I O[ 1 6 ]
VCC
VCC
VCC
VCC
I O[ 1 7 ]
I O[ 1 8 ]
I O[ 1 9 ]
I O[ 2 0 ]
V _ C P U _ I O[ 1 ]
C 16 8
A U 18
V CC V RM [4 ]
SATA
U 19
0 . 1 u _1 0 V _ X7 R _0 4
357mA
V _ C P U _ I O[ 2 ]
VC CR T C
I be x P e a k-M _R e v 0 _9
B - 22 IBEXPEAK - M 8/9
C 18 7
5
3. 3
1. 05
0 . 1 u_ 1 0 V _ X7 R _ 0 4
PC I/ GPI O/ LP C
C 19 4
3. 3 V S
0 . 1 u _1 0 V _ X 7R _0 4
142.6mA
V 5R EF _S us
V cc 3_ 3
V cc AC lk
C1 8 9
CP U
P 18
U 22
1 u _6 . 3 V _ X5 R _0 4
3 .3 V
1 u _6 . 3 V _ X5 R _0 4
V C CIO [9 ]
20.4mA
C 1 43
C 15 3
1 u _6 . 3 V _ X 5R _0 4
V2 8
U2 8
U2 6
U2 4
P2 8
P2 6
N2 8
N2 6
M2 8
M2 6
L 28
L 26
J 28
J 26
H2 8
H2 6
G2 8
G2 6
F28
F26
E2 8
E2 6
C2 8
C2 6
B2 7
A2 8
A2 6
1. 1/1 .0 5 < 1 ( mA )
5
< 1 ( mA )
AK3
AK1
1 .1 VS _ V T T
C 39 6
C 39 7
* 1u _ 6 . 3V _ X 5 R _ 0 4
*1 0 u _6 . 3 V _ X 5R _ 06
V CCS S T
3. 3 V
C1 5 0
V2 4
V2 6
Y2 4
Y2 6
V C C5 RE F
PCI /G PI O/ LP C
C 3 79
Cl oc k a nd M is ce ll an eo us
A D 41
1 . 1 V S _ V TT
USB
VC CM E[2 ]
CIO
CIO
CIO
CIO
V C C ME [ 1 3 ]
V C C ME [ 1 4 ]
V C C ME [ 1 5 ]
V C C ME [ 1 6 ]
RT C
B.Schematic Diagrams
A D 39
1849mA
1. 1 V S _ V T T
VC
VC
VC
VC
S0 Ic cm ax Cu rr en t (A)
V _C PU _I O
V 5R EF
V C CS U S HD A
HDA
A H2 2
A T 20
1. 5V S _ 1 . 8 V S
A H1 9
A D2 0
1. 1 V S _ V T T
AF2 2
A D1 9
AF2 0
AF1 9
A H2 0
C 17 3
1 u _6 . 3 V _ X 5R _0 4
14
2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 6, 2 7 , 2 8, 2 9 , 3 0, 31 , 3 5 , 36
20
2, 1 3 , 1 7, 2 0 , 2 6, 2 7 , 3 0, 31 , 3 5 , 36
4 , 9 , 1 0, 1 1 , 2 3, 2 7 , 2 9, 31 , 3 3 , 36
2 4, 2 7 , 3 0, 31 , 3 3 , 34
3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 9, 3 0 , 3 1, 33 , 3 4 , 35
2, 4 , 6 , 7 , 1 4, 1 5 , 1 6, 1 9 , 2 0, 34 , 3 5 , 36
AB1 9
AB2 0
AB2 2
A D2 2
AA3 4
Y3 4
Y3 5
AA3 5
1 . 1V S _V T T
1. 5 V _ V C C S U S H D A
R 12 7
L 30
C 19 5
R 12 9
1 u _ 6. 3 V _ X 5R _ 04
1 .5 V
* 15 m i _l s ho rt _ 0 6
*0 _ 04
3 .3 V
RT CV CC
3 .3 V S
1 . 5 V S _ 1. 8 V S
5 VS
1 .5 V
5V
3 .3 V
1 . 1 V S _ V TT
Schematic Diagrams
IBEXPEAK - M 9/9
IBEXPEAK - M (GND)
U 20 H
AB 1 6
VS S [0 ]
VS S [1 ]
VS S [2 ]
VS S [3 ]
VS S [4 ]
VS S [5 ]
VS S [6 ]
VS S [7 ]
VS S [8 ]
VS S [9 ]
VS S [1 0 ]
VS S [1 1 ]
VS S [1 2 ]
VS S [1 3 ]
VS S [1 4 ]
VS S [1 5 ]
VS S [1 6 ]
VS S [1 7 ]
VS S [1 8 ]
VS S [1 9 ]
VS S [2 0 ]
VS S [2 1 ]
VS S [2 2 ]
VS S [2 3 ]
VS S [2 4 ]
VS S [2 5 ]
VS S [2 6 ]
VS S [2 7 ]
VS S [2 8 ]
VS S [2 9 ]
VS S [3 0 ]
VS S [3 1 ]
VS S [3 2 ]
VS S [3 3 ]
VS S [3 4 ]
VS S [3 5 ]
VS S [3 6 ]
VS S [3 7 ]
VS S [3 8 ]
VS S [3 9 ]
VS S [4 0 ]
VS S [4 1 ]
VS S [4 2 ]
VS S [4 3 ]
VS S [4 4 ]
VS S [4 5 ]
VS S [4 6 ]
VS S [4 7 ]
VS S [4 8 ]
VS S [4 9 ]
VS S [5 0 ]
VS S [5 1 ]
VS S [5 2 ]
VS S [5 3 ]
VS S [5 4 ]
VS S [5 5 ]
VS S [5 6 ]
VS S [5 7 ]
VS S [5 8 ]
VS S [5 9 ]
VS S [6 0 ]
VS S [6 1 ]
VS S [6 2 ]
VS S [6 3 ]
VS S [6 4 ]
VS S [6 5 ]
VS S [6 6 ]
VS S [6 7 ]
VS S [6 8 ]
VS S [6 9 ]
VS S [7 0 ]
VS S [7 1 ]
VS S [7 2 ]
VS S [7 3 ]
VS S [7 4 ]
VS S [7 5 ]
VS S [7 6 ]
VS S [7 7 ]
VS S [7 8 ]
VS S [7 9 ]
I be x Pe ak -M_R e v 0_ 9
VS S[ 8 0]
VS S[ 8 1]
VS S[ 8 2]
VS S[ 8 3]
VS S[ 8 4]
VS S[ 8 5]
VS S[ 8 6]
VS S[ 8 7]
VS S[ 8 8]
VS S[ 8 9]
VS S[ 9 0]
VS S[ 9 1]
VS S[ 9 2]
VS S[ 9 3]
VS S[ 9 4]
VS S[ 9 5]
VS S[ 9 6]
VS S[ 9 7]
VS S[ 9 8]
VS S[ 9 9]
VS S[ 1 0 0]
VS S[ 1 0 1]
VS S[ 1 0 2]
VS S[ 1 0 3]
VS S[ 1 0 4]
VS S[ 1 0 5]
VS S[ 1 0 6]
VS S[ 1 0 7]
VS S[ 1 0 8]
VS S[ 1 0 9]
VS S[ 1 1 0]
VS S[ 1 1 1]
VS S[ 1 1 2]
VS S[ 1 1 3]
VS S[ 1 1 4]
VS S[ 1 1 5]
VS S[ 1 1 6]
VS S[ 1 1 7]
VS S[ 1 1 8]
VS S[ 1 1 9]
VS S[ 1 2 0]
VS S[ 1 2 1]
VS S[ 1 2 2]
VS S[ 1 2 3]
VS S[ 1 2 4]
VS S[ 1 2 5]
VS S[ 1 2 6]
VS S[ 1 2 7]
VS S[ 1 2 8]
VS S[ 1 2 9]
VS S[ 1 3 0]
VS S[ 1 3 1]
VS S[ 1 3 2]
VS S[ 1 3 3]
VS S[ 1 3 4]
VS S[ 1 3 5]
VS S[ 1 3 6]
VS S[ 1 3 7]
VS S[ 1 3 8]
VS S[ 1 3 9]
VS S[ 1 4 0]
VS S[ 1 4 1]
VS S[ 1 4 2]
VS S[ 1 4 3]
VS S[ 1 4 4]
VS S[ 1 4 5]
VS S[ 1 4 6]
VS S[ 1 4 7]
VS S[ 1 4 8]
VS S[ 1 4 9]
VS S[ 1 5 0]
VS S[ 1 5 1]
VS S[ 1 5 2]
VS S[ 1 5 3]
VS S[ 1 5 4]
VS S[ 1 5 5]
VS S[ 1 5 6]
VS S[ 1 5 7]
VS S[ 1 5 8]
AK 3 0
AK 3 1
AK 3 2
AK 3 4
AK 3 5
AK 3 8
AK 4 3
AK 4 6
AK 4 9
AK 5
AK 8
AL 2
AL 5 2
AM1 1
BB 4 4
AD 2 4
AM2 0
AM2 2
AM2 4
AM2 6
AM2 8
BA 4 2
AM3 0
AM3 1
AM3 2
AM3 4
AM3 5
AM3 8
AM3 9
AM4 2
AU 2 0
AM4 6
AV 2 2
AM4 9
AM7
AA 5 0
BB 1 0
AN 3 2
AN 5 0
AN 5 2
AP 1 2
AP 4 2
AP 4 6
AP 4 9
AP 5
AP 8
AR 2
AR 5 2
AT1 1
BA 1 2
AH 4 8
AT3 2
AT3 6
AT4 1
AT4 7
AT7
AV 1 2
AV 1 6
AV 2 0
AV 2 4
AV 3 0
AV 3 4
AV 3 8
AV 4 2
AV 4 6
AV 4 9
AV 5
AV 8
AW 14
AW 18
AW 2
BF 9
AW 32
AW 36
AW 40
AW 52
AY 1 1
AY 4 3
AY 4 7
VS S[ 1 59 ]
VS S[ 1 60 ]
VS S[ 1 61 ]
VS S[ 1 62 ]
VS S[ 1 63 ]
VS S[ 1 64 ]
VS S[ 1 65 ]
VS S[ 1 66 ]
VS S[ 1 67 ]
VS S[ 1 68 ]
VS S[ 1 69 ]
VS S[ 1 70 ]
VS S[ 1 71 ]
VS S[ 1 72 ]
VS S[ 1 73 ]
VS S[ 1 74 ]
VS S[ 1 75 ]
VS S[ 1 76 ]
VS S[ 1 77 ]
VS S[ 1 78 ]
VS S[ 1 79 ]
VS S[ 1 80 ]
VS S[ 1 81 ]
VS S[ 1 82 ]
VS S[ 1 83 ]
VS S[ 1 84 ]
VS S[ 1 85 ]
VS S[ 1 86 ]
VS S[ 1 87 ]
VS S[ 1 88 ]
VS S[ 1 89 ]
VS S[ 1 90 ]
VS S[ 1 91 ]
VS S[ 1 92 ]
VS S[ 1 93 ]
VS S[ 1 94 ]
VS S[ 1 95 ]
VS S[ 1 96 ]
VS S[ 1 97 ]
VS S[ 1 98 ]
VS S[ 1 99 ]
VS S[ 2 00 ]
VS S[ 2 01 ]
VS S[ 2 02 ]
VS S[ 2 03 ]
VS S[ 2 04 ]
VS S[ 2 05 ]
VS S[ 2 06 ]
VS S[ 2 07 ]
VS S[ 2 08 ]
VS S[ 2 09 ]
VS S[ 2 10 ]
VS S[ 2 11 ]
VS S[ 2 12 ]
VS S[ 2 13 ]
VS S[ 2 14 ]
VS S[ 2 15 ]
VS S[ 2 16 ]
VS S[ 2 17 ]
VS S[ 2 18 ]
VS S[ 2 19 ]
VS S[ 2 20 ]
VS S[ 2 21 ]
VS S[ 2 22 ]
VS S[ 2 23 ]
VS S[ 2 24 ]
VS S[ 2 25 ]
VS S[ 2 26 ]
VS S[ 2 27 ]
VS S[ 2 28 ]
VS S[ 2 29 ]
VS S[ 2 30 ]
VS S[ 2 31 ]
VS S[ 2 32 ]
VS S[ 2 33 ]
VS S[ 2 34 ]
VS S[ 2 35 ]
VS S[ 2 36 ]
VS S[ 2 37 ]
VS S[ 2 38 ]
VS S[ 2 39 ]
VS S[ 2 40 ]
VS S[ 2 41 ]
VS S[ 2 42 ]
VS S[ 2 43 ]
VS S[ 2 44 ]
VS S[ 2 45 ]
VS S[ 2 46 ]
VS S[ 2 47 ]
VS S[ 2 48 ]
VS S[ 2 49 ]
VS S[ 2 50 ]
VS S[ 2 51 ]
VS S[ 2 52 ]
VS S[ 2 53 ]
VS S[ 2 54 ]
VS S[ 2 55 ]
VS S[ 2 56 ]
VS S[ 2 57 ]
VS S[ 2 58 ]
V SS [ 2 59 ]
V SS [ 2 60 ]
V SS [ 2 61 ]
V SS [ 2 62 ]
V SS [ 2 63 ]
V SS [ 2 64 ]
V SS [ 2 65 ]
V SS [ 2 66 ]
V SS [ 2 67 ]
V SS [ 2 68 ]
V SS [ 2 69 ]
V SS [ 2 70 ]
V SS [ 2 71 ]
V SS [ 2 72 ]
V SS [ 2 73 ]
V SS [ 2 74 ]
V SS [ 2 75 ]
V SS [ 2 76 ]
V SS [ 2 77 ]
V SS [ 2 78 ]
V SS [ 2 79 ]
V SS [ 2 80 ]
V SS [ 2 81 ]
V SS [ 2 82 ]
V SS [ 2 83 ]
V SS [ 2 84 ]
V SS [ 2 85 ]
V SS [ 2 86 ]
V SS [ 2 87 ]
V SS [ 2 88 ]
V SS [ 2 89 ]
V SS [ 2 90 ]
V SS [ 2 91 ]
V SS [ 2 92 ]
V SS [ 2 93 ]
V SS [ 2 94 ]
V SS [ 2 95 ]
V SS [ 2 96 ]
V SS [ 2 97 ]
V SS [ 2 98 ]
V SS [ 2 99 ]
V SS [ 3 00 ]
V SS [ 3 01 ]
V SS [ 3 02 ]
V SS [ 3 03 ]
V SS [ 3 04 ]
V SS [ 3 05 ]
V SS [ 3 06 ]
V SS [ 3 07 ]
V SS [ 3 08 ]
V SS [ 3 09 ]
V SS [ 3 10 ]
V SS [ 3 11 ]
V SS [ 3 12 ]
V SS [ 3 13 ]
V SS [ 3 14 ]
V SS [ 3 15 ]
V SS [ 3 16 ]
V SS [ 3 17 ]
V SS [ 3 18 ]
V SS [ 3 19 ]
V SS [ 3 20 ]
V SS [ 3 21 ]
V SS [ 3 22 ]
V SS [ 3 23 ]
V SS [ 3 24 ]
V SS [ 3 25 ]
V SS [ 3 26 ]
V SS [ 3 27 ]
V SS [ 3 28 ]
V SS [ 3 29 ]
V SS [ 3 30 ]
V SS [ 3 31 ]
V SS [ 3 32 ]
V SS [ 3 33 ]
V SS [ 3 34 ]
V SS [ 3 35 ]
V SS [ 3 36 ]
V SS [ 3 37 ]
V SS [ 3 38 ]
V SS [ 3 39 ]
V SS [ 3 40 ]
V SS [ 3 41 ]
V SS [ 3 42 ]
V SS [ 3 43 ]
V SS [ 3 44 ]
V SS [ 3 45 ]
V SS [ 3 46 ]
V SS [ 3 47 ]
V SS [ 3 48 ]
V SS [ 3 49 ]
V SS [ 3 50 ]
V SS [ 3 51 ]
V SS [ 3 52 ]
V SS [ 3 53 ]
V SS [ 3 54 ]
V SS [ 3 55 ]
V SS [ 3 56 ]
V SS [ 3 66 ]
H 49
H5
J 24
K 11
K 43
K 47
K7
L 14
L 18
L2
L 22
L 32
L 36
L 40
L 52
M 12
M 16
M 20
N 38
M 34
M 38
M 42
M 46
M 49
M5
M8
N 24
P 11
A D 15
P 22
P 30
P 32
P 34
P 42
P 45
P 47
R2
R 52
T12
T41
T46
T49
T5
T8
U 30
U 31
U 32
U 34
P 38
V 11
P 16
V 19
V 20
V 22
V 30
V 31
V 32
V 34
V 35
V 38
V 43
V 45
V 46
V 47
V 49
V5
V7
V8
W2
W 52
Y 11
Y 12
Y 15
Y 19
Y 23
Y 28
Y 30
Y 31
Y 32
Y 38
Y 43
Y 46
P 49
Y 5
Y 6
Y 8
P 24
T43
A D 51
A T8
A D 47
Y 47
A T12
A M6
A T13
A M5
A K45
A K39
A V14
Sheet 22 of 40
IBEXPEAK - M 9/9
Ibe x P ea k -M _R e v 0 _9
IBEXPEAK - M 9/9 B - 23
B.Schematic Diagrams
AA 1 9
AA 2 0
AA 2 2
A M1 9
AA 2 4
AA 2 6
AA 2 8
AA 3 0
AA 3 1
AA 3 2
AB 1 1
AB 1 5
AB 2 3
AB 3 0
AB 3 1
AB 3 2
AB 3 9
AB 4 3
AB 4 7
AB 5
AB 8
A C2
A C 52
A D 11
A D 12
A D 16
A D 23
A D 30
A D 31
A D 32
A D 34
A U 22
A D 42
A D 46
A D 49
A D7
AE 2
AE 4
AF 1 2
Y 13
A H 49
A U4
AF 3 5
AP 1 3
A N 34
AF 4 5
AF 4 6
AF 4 9
AF 5
AF 8
A G2
A G5 2
A H 11
A H 15
A H 16
A H 24
A H 32
AV 1 8
A H 43
A H 47
A H7
A J 19
AJ2
A J 20
A J 22
A J 23
A J 26
A J 28
A J 32
A J 34
A T5
AJ4
AK 1 2
A M4 1
A N 19
AK 2 6
AK 2 2
AK 2 3
AK 2 8
U 20I
AY 7
B 11
B 15
B 19
B 23
B 31
B 35
B 39
B 43
B 47
B7
BG 1 2
B B 12
B B 16
B B 20
B B 24
B B 30
B B 34
B B 38
B B 42
B B 49
BB5
BC 1 0
BC 1 4
BC 1 8
BC 2
BC 2 2
BC 3 2
BC 3 6
BC 4 0
BC 4 4
BC 5 2
BH 9
BD 4 8
BD 4 9
BD 5
B E 12
B E 16
B E 20
B E 24
B E 30
B E 34
B E 38
B E 42
B E 46
B E 48
B E 50
BE6
BE8
BF3
B F 49
B F 51
BG 1 8
BG 2 4
BG 4
BG 5 0
BH 1 1
BH 1 5
BH 1 9
BH 2 3
BH 3 1
BH 3 5
BH 3 9
BH 4 3
BH 4 7
BH 7
C 12
C 50
D 51
E 12
E 16
E 20
E 24
E 30
E 34
E 38
E 42
E 46
E 48
E6
E8
F 49
F5
G 10
G 14
G 18
G2
G 22
G 32
G 36
G 40
G 44
G 52
A F 39
H 16
H 20
H 30
H 34
H 38
H 42
Schematic Diagrams
New Card, Mini PCIE
3 . 3V
C 46 1
3. 3V
*0 . 1 u_ 1 0 V _X 7 R _ 0 4
5
NEW CARD(Port 8)
B U F _ P L T_ R S T#
1
4
U2 6
MC 74 V H C 1 G0 8 D F T 1 G
3
2
1. 5 V S 3 . 3 V S
3. 3 V
R3 2 4
R3 2 5
C2 1 8
C2 3 4
C 2 30
*1 0 0 K _0 4
*1 0 0 K _0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1 u _1 0 V _ X7 R _0 4
U2 4
17
J _N E W 1
AUX IN
P E R S T#
A U XO U T
2
3. 3 V I N
3. 3V O U T
1. 5V O U T
B.Schematic Diagrams
12
1. 5 V I N
6
19
1 6 , 2 8, 31
Sheet 23 of 40
New Card, Mini
PCIE
1 .5 VS
1
SU SB#
R3 3 3
3 . 3V
3. 3 V S
NC _ RS T #
N C _ 3. 3 V A U X
3
N C _ 3. 3 V
36mils
48mils
11
N C _ 1. 5 V
48mils
NC_ P E R S T #
13
12
14
15
10
9
N C_ CP P E #
N C_ CP US B #
10
9
CP P E #
C PUS B #
4 , 1 8 , 2 5, 2 8 B U F _P L T _ R S T #
1 8 U S B _ OC #2 3
8
15
P C I E _W A K E #
1 6 , 25 P C I E _ W A K E #
1 5 N E W C A R D _ C L K R E Q#
SYSR ST #
OC #
R1 6 6
3. 3 V S
S TB Y #
17
4
11
16
1 0K _ 0 4
1 5 C L K _ P C I E _N E W _ C A R D
1 5 C L K _ P C I E _N E W _ C A R D #
19
18
15
15
15
15
22
21
25
24
PE RS T #
+3 . 3 V A U X
+3 . 3 V
+3 . 3 V
+1 . 5 V
+1 . 5 V
CP P E #
CP U S B #
W AKE#
CL K RE Q #
R E F C LK +
R E F C LK -
1 0 K _ 04
4
5
13
14
16
3 .3 V
NC
NC
NC
NC
NC
18
20
R C LK E N
S HD N#
N C _ R C L K E N R 32 6
N C _ S H D N # R 33 7
*1 0 K _0 4
*1 0 K _0 4
3 . 3V
7
21
GN D
GN D
Port 3
W 8 3L 3 5 1Y G
C4 4 9
C4 6 6
C 4 53
0 . 1 u_ 1 0 V _X 7 R _ 0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4
0 . 1 u _1 0 V _ X 7R _0 4
PCIE _ RX P2 _ NEW _ C A RD
P C I E _ R X N 2_ N E W _ C A R D
P C I E _T X P 2 _N E W _ C A R D
P C I E _T X N 2 _ N E W _ C A R D
1 8 US B _ P P 3
1 8 US B _ P N 3
3
2
1 5 S M L 0_ D A TA
1 5 S M L 0_ C LK
8
7
P E Tp 0
P E Tn 0
PE Rp 0
PE Rn 0
R E SE RV E D
R E SE RV E D
US B _ D+
US B _ D-
6-02-83351-9Q0
EN E P2 231 p in 3, 4,1 5, 22
ha s in ter na ll y
S MB _ D A T A
S MB _ C L K
1 30 8 0 1-0 2
pu ll ed hi gh ( 17 0Ko hm )
6-21-G3A60-126 Connect
6-21-G3A60-126-S ? ?
MINI CARD (WLAN,Port 5)
L ayou t Sho w "WL AN( Wimax, 802 .11N) "Not e
20 mil
J _ MI N I 1
3 .3 V S
R 3 05
1 0 K _ 04
29
2 8 ,2 9
R3 4 0
R3 4 1
B T _E N #
B T _E N
P C I E _W A K E #
*0 _ 04
* 10 m i _l s h ort
1
3
5
7
11
13
9
15
1 5 W L A N _ C L K R E Q#
1 5 CL K_ P CIE _ M INI#
1 5 CL K _ P CIE _ M INI
3. 3 V
W L A N1 .5 V
W AKE#
CO E X1
CO E X2
3 . 3V A U X _ 0
1 .5 V _ 0
UIM _ P W R
U I M_ D A T A
U I M_ C L K
U I M_ R E S E T
U I M_ V P P
C L K R E Q#
RE F CL K RE F CL K +
GN D 0
GN D 1
G ND 5
2
6
8
10
12
14
16
U
U
U
U
U
20 mil
1 .5 V
R 3 15
I M_ P W R _1
I M_ D A T A _ 1
I M_ C L K _ 1
I M_ R S T _ 1
I M_ V P P _ 1
* 1 5m i l _s h o rt _0 6
C 4 44
* 0 . 1u _ 1 0V _X 7 R _ 0 4
4
KEY
21
27
29
15
15
15
15
35
23
25
31
33
2 8 W LA N _ D E T #
P C I E _ R XN 3 _W L A N
P CIE _ RX P 3 _ W L A N
P C I E _ T XN 3 _W L A N
P C I E _ TX P 3 _ W L A N
28
28
8 0 D E T#
3 IN1
3 .3 V
MI N I _ C L K 1
MI N I _ D A T A 1
MI N I _ R S T # 1
V DD 3
R3 0 6
*1 5 mi l _ sh o rt _ 06
17
19
37
39
41
43
45
47
49
51
GN D 2
GN D 3
GN D 4
GN D 1 1
PET n 0
PET p 0
P E R n0
P E R p0
R e s e rv ed 0
R e s e rv ed 1
GN D 1 2
3 . 3V A U X _ 3
3 . 3V A U X _ 4
GN D 1 3
R e s e rv ed 2
R e s e rv ed 3
R e s e rv ed 4
R e s e rv ed 5
G ND 6
G ND 7
G ND 8
G ND 9
G ND 1 0
W _ D I S A B LE #
PER SET #
S MB _ C L K
S MB _ D A T A
U S B_ DUS B _ D +
3 . 3V A U X _ 1
1 .5 V _ 1
1 .5 V _ 2
3 . 3V A U X _ 2
LE D _ W W A N #
L ED_ W L A N #
LE D _ W P A N #
18
26
34
40
50
20
22
30
32
36
38
24
28
48
52
42
44
46
R 3 16
* 1 0K _ 0 4
3 .3 V S
W LA N _ E N 2 8 , 2 9
B U F _ P LT _ R S T #
BT _ DE T #
20 mil
3 .3 V AUX _ 1
40 mil
20 mil
28
USB _ P N 2 1 8
USB _ P P2 1 8
R 3 17
* 1 5m i l _s h o rt _0 6
W L A N1 .5 V
3 .3 V
8 8 91 0 -5 20 4 M-0 1
4 , 9 , 10 , 1 1 , 21 , 2 7 , 2 9, 3 1 , 3 3, 3 6 1 . 5 V
2 0 , 3 1, 3 6 1 . 5 V S
3 , 4 , 12 , 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 3 5 3 . 3 V
2, 1 0 , 1 1, 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 4, 2 5 , 2 6 , 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 3 6 3 . 3 V S
14 , 2 5 , 28 , 2 9 , 31 , 3 2 , 3 7 V D D 3
B - 24 New Card, Mini PCIE
3. 3 V
80 C LK
28
Port 2
GN D
GN D
GN D
GN D
GN D 1
GN D 2
5
6
1
20
23
26
G ND 1
G ND 2
Schematic Diagrams
CCD, 3G, TPM
MINI CARD 3G(Port 6)
3G POWER
R 17 8
Layo ut Sho w "3.5G(HSDPA)" No te
3G _ 3. 3 V
3 .3 V
7
11
13
9
15
W A KE#
C OE X 1
C OE X 2
C
R
R
G
G
2
6
8
10
12
14
16
3 .3 V A UX _ 0
1 .5 V _ 0
U I M_ P W R
U I M_ D A T A
U I M_ C L K
U I M_ R E S E T
U I M_ V P P
L K R E Q#
EF CL KEF CL K+
ND 0
ND 1
6 0mi ls
UIM
UIM
UIM
UIM
UIM
_ PW R
_ DAT A
_ CL K
_ RST
_ VPP
+C 2 48
C 1 96
C 2 41
C 20 1
2 2 0 u_ 4 V _ V _B
1u _ 6 . 3V _ X 5 R _ 04
1 0 u_ 6 . 3 V _X 5 R _ 0 6
35
23
25
31
33
3 G _D E T#
3 G_ 3 . 3V
C2 2 1
17
19
37
39
41
43
45
47
49
51
C4 2 0
0. 1 u _ 10 V _ X 7R _0 4
10 u _ 6. 3 V _ X 5R _ 06
18
26
34
40
50
G N D 11
P E Tn 0
P E Tp 0
P E Rn 0
P E Rp 0
20
22
30
32
36
38
W _ D I S A B LE #
PER SET#
S MB _ C L K
S MB _ D A T A
US B _ DUS B _ D +
R e se rv e d 0
R e se rv e d 1
G N D 12
3 .3 V A UX _ 3
3 .3 V A UX _ 4
G N D 13
R e se rv e d 2
R e se rv e d 3
R e se rv e d 4
R e se rv e d 5
24
28
48
52
42
44
46
3 .3 V A UX _ 1
1 .5 V _ 1
1 .5 V _ 2
3 .3 V A UX _ 2
L E D_ W W A N #
L E D_ W L A N #
L E D_ W P A N #
D
G
28 3 G_ P O W E R
Q1 3
MT N 70 0 2 Z H S 3
S
G ND 6
G ND 7
G ND 8
G ND 9
GN D 1 0
3 G_ E N
28
3
L19
*W C M2 0 12 F 2 S -1 61 T 0 3-s h o rt
4
2
R1 5 6
* 1 5m i l_ s h ort _ 0 6
1
F ro m SB G PIO Pin de f au lt HI
Po w er Pl a ne : Su sp en d
S3: De fi n ed
US B _ P N9
18
US B _ P P 9
18
SIM CONN
3 G_ 3 . 3 V
R1 3 6
4 . 7K _0 4
+C 20 6
C 4 21
*0 . 1u _ 1 0V _ X 5 R _ 04
88 9 1 0-5 2 04 M -01
Sheet 24 of 40
CCD, 3G, TPM
3 G_ 3. 3 V
6 0mil s
2 2 0u _ 4 V _V _ B
J _S I M 1
L OCK
( TO P V IE W)
R 30 7
* 10 m i l_ s ho rt
U I M_ C L K
C 3
C 2
C 1
U I M_ R S T
U I M_ P W R
U I M_ C LK
U I M_ R S T
U I M_ P W R
C 4 30
R3 0 4
*1 0 m il _ sh o rt
U I M_ D A TA
U I M _V P P
U I M _G N D
C7
C6
C5
U I M_ D A T A
U I M_ V P P
OPE N
2 2 p _5 0 V _ N P O _0 4
C 1 7 70 6 6 1-1
S I ML O C K
C4 1 1
C4 1 0
C 4 12
2 2p _ 5 0V _ N P O_ 04
2 2p _ 5 0V _ N P O_ 04
22 p _5 0 V _ N P O _0 4
1 6 S 4 _ S T A TE #
R 19 7
* 0 _0 4
TP M _L P C P D #
28
TP M _B A D D
9
T P M_ P P
7
LC LK
8
CCD
5V
L1
* 15 m i l_ s h ort _ 0 6
LP C P D #
C2
G
C 3
C5
C8
C9
1 00 K _ 0 4
1u _ 6. 3V _ X 5R _ 04
0. 1 u _ 10 V _ X 7R _0 4
1u _ 6 . 3V _ X 5 R _ 04
0. 1 u _ 10 V _ X 7R _0 4
5
R 8
1 0 0K _ 0 4
*0 . 1 u_ 1 0 V _X 7 R _ 0 4
GP I O
GP I O 2
6
2
13
J_ C C D 1
T P M3 0 04
T P M3 0 05
R 7
X TA L O
GN
GN
GN
GN
D_ 1
D_ 2
D_ 3
D_ 4
14
4
11
18
25
3 3 0 K _0 4
XTAL I
PP
TE S T I
MJ_CCD1
R9
1
1 u _6 . 3 V _ X5 R _0 4
5
C2 6 5
XT AL I
NC_ 1
NC_ 2
NC_ 3
48 mil
*1 u _6 . 3 V _ X5 R _0 4
3 . 3V S
VS B
5 V_ CC D
Q4
M TP 3 4 0 3N 3
S
D
C2 8 3
TPM
LF R A ME #
LR E S E T #
S E RIR Q
CL K RU N#
TE S T B I / B A D D
T P M3 0 01 1
T P M3 0 02 3
T P M3 0 03 1 2
10
19
24
*0 . 1 u_ 1 0V _ X 7 R _ 0 4
VDD 1
VDD 2
VDD 3
C2 9 0
0
1
2
3
D
22
16
27
15
L P C _F R A ME #
P L T _ RS T #
S E RIRQ
P M _ CL K RU N#
LA D
LA D
LA D
LA D
XTAL O
4
3
1
2
C 2 54
X3
* C M2 0 0 S 32 7 6 81 2 2 0_ 3 2. 7 6 8 K H z
CC D_ E N
Q 5
M TN 70 0 2 Z H S 3
G
18
U S B_ PN5
18
US B _ P P 5
2 8 CC D_ DE T #
C C D _D E T#
1
2
3
4
5
85 2 0 5-0 5 0 01
From H8 default HI
C 26 0
* 18 p _5 0 V _ N P O _0 4
28
CC D_ E N
S
21
1 8 P C L K _T P M
1 4 ,2 8
18
1 4 ,2 8
16
U1 4
26
23
20
17
0
1
2
3
*0 . 1 u _1 0 V _ X 7R _0 4
_A D
_A D
_A D
_A D
C2 8 7
L PC
L PC
L PC
L PC
C 26 6
[ PVT- 1]
1 4, 2 8
1 4, 2 8
1 4, 2 8
1 4, 2 8
* 0. 1 u _ 10 V _ X 7 R _ 0 4
3 . 3V S
TPM 1.2
* 18 p _ 50 V _ N P O _0 4
*S L B 9 6 35 T T
As se rte d be fore e nte rin g S 3
L PC r es et timing :
P C LK _ T P M
R1 8 5
*3 3 _0 4
HI: ACCESS
LOW: NORMAL ( Int er nal PD)
HI: 4E/ 4F H
T PM _BADD LOW: 2E/ 2F H
T PM _PP
C 27 8
* 1 0p _ 50 V _ N P O _ 06
3, 4 , 1 2 , 14 , 1 5 , 16 , 1 8 , 19 , 2 0 , 21 , 2 3 , 25 , 2 9 , 30 , 3 1, 33 , 3 4, 35 3 . 3 V
2, 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 19 , 2 0 , 21 , 2 3 , 25 , 2 6 , 27 , 2 8 , 29 , 3 0, 31 , 3 5, 36 3 . 3 V S
2 1 , 27 , 3 0, 31 , 3 3, 34 5 V
3 .3 V S
L PCPD# ina ct ive t o L RST# in ac tive 3 2~96 us
T P M _L P C P D #
R1 9 8
*1 0 K _ 04
T P M _P P
R1 9 0
*1 0 K _ 04
T P M _B A D D
R1 8 8
*1 0 K _ 04
R1 8 4
*1 0 K _ 04
CCD, 3G, TPM B - 25
B.Schematic Diagrams
28
0. 1 u _ 10 V _ X 7R _ 04
20 K _ 1 %_ 0 4
R 1 67
10 0 K _ 04
G ND 2
G ND 3
G ND 4
C2 4 2
10 0 K _ 04
R 1 68
KE Y
21
27
29
R1 7 0
C 25 1
0 . 1 u _1 0 V _ X7 R _ 0 4
0 . 1 u _1 0 V _X 7 R _ 0 4
4
G ND 5
3 G_ 3. 3 V
3A 120mils
G
1
3
5
* 0 _0 6
Q 14
A O3 4 15
S
D
3A 120mils
J_ 3 G1
Schematic Diagrams
Card Reader, LAN (JMB251)
Sw it ch in g Re gu la to r
cl os e to P IN 6
R 18 7
2 2 _0 4
( >2 0m il )
3 .3 V_ L AN
S5 WAKE ON LAN
D V DD
L35
REG L X
3 .3 V _ L A N
V D D3
DV DD
.
JMC251
S D _C L K
S W F 25 2 0 C F -4 R 7M -M
( >2 0m il )
C 4 36
C2 9 3
1 0 u _6 . 3 V _ X 5R _ 06
Pin#7
0 . 1u _ 1 0V _X 7 R _ 0 4
Pin#7
2A
1 0 K _ 04
U1 3
Sheet 25 of 40
Card Reader,
LAN (JMB251)
L A N_ L E D0
L A N_ L E D1
SD _ W P
SD _ BS
M D I O 13
D VDD
26
26
Card Reader Pull
High/Low
Resistors
26
26
26
26
26
26
3 .3 VS
R 1 86
* 10 K _ 0 4 M D I O 7
R 3 12
R 1 74
* 20 0 K _ 0 4 M D I O 12
* 20 0 K _ 0 4 M D I O 14
L A N _M D I P 0
L A N _M D I N 0
D VDD
L A N _M D I P 1
L A N _M D I N 1
3 .3 V _ L A N
L A N _M D I P 2
L A N _M D I N 2
D VDD
L A N _M D I P 3
L A N _M D I N 3
L A N_ M DIP 2
L A N_ M DIN 2
L A N_ M DIP 3
L A N_ M DIN 3
R 17 8
0
NC
NC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
L ED 0
L ED 1
VD D
G ND
V I P _1
V I N_ 1
A V D D 12
V I P _2
V I N_ 2
G ND
A V D D 33
V I P _3 (N C )
V I N _ 3 (N C )
A V D D 12 (N C )
V I P _4 (N C )
V I N _ 4 (N C )
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M D I O 12
S D_ W P
M D I O7
G ND
M D I O1 3
M D I O1 4
S MB _ S D A / C R _ LE D N
T EST N
V D DIO
V DD
V C C3 O
C R _C D 0 N
C R _C D 1 N
S MB _ S C L/ L E D 2
C R E QN
M PD
W AKEN
RS T N
A V DD X
JMC251
JMC261
(LQFP 64)
M DIO 1 3
M DIO 1 4
C R1 _ L E DN
S D _ CD #
M S _ INS #
L A N _L E D 2
3 .3 V_ L AN
D VD D
V C C _C A R D
R1 88
NC
NC
10 0K
R4 32
NC
0
NC
1. For JM C251/JMC261 on ly.
2. MPD co nnect to Main Po wer or
RSTN for D3E applicaion, t o AUX
po wer ot herwise.
JM C 2 5 1
R1 9 9
V IN
V IN
1
V O UT
L37
2A
2
1
H C B 2 0 1 2 K F -5 00 T 4 0
EN
R 34 5
2
GN D
*G 52 4 3 A
*1 0 0 K _ 04
Card Reader
Power
V CC_ C A RD
3. 3V _ L A N
3 .3 V_ L AN
L A N _L E D 2
C R1 _ L E DN
L A N _ P CIE _ W A K E # 2 8
R3 0 8
D VD D
4
5
3
C5 66 F un ct io n
NC
Di sa bl e D3 E
NC
En ab le D 3E (1 )
0. 1u En ab le D 3E (2 )
R3 0 9
R3 1 0
* 0 _0 4
* 1 00 K _ 0 4
C2 4 7
* 0 . 1u _ 1 0V _X 5 R _ 0 4
R 1 77
R 1 72
* 4. 7 K _ 0 4
* 4. 7 K _ 0 4
R 3 30
7 5 _ 1% _ 0 4
3 .3 VS
0 _0 4
R EXT
V D DX 3 3
X IN
X O UT
GN D
LX
F B1 2
V D DR E G
CL KN
C L KP
A VD DH
RXP
R XN
GN D
T XN
T XP
B.Schematic Diagrams
R N2 5
1 0 K _8 P 4 R _0 4
8
1
7
2
6
3
5
4
3 . 3V _ L A N
U 27
*0 . 1 u_ 1 0 V _ X7 R _0 4
on ly
M DIO 0
M D I O1
M DIO 2
V DD IO
M DIO 3
MD I O 4
M D I O5
GN D
M D I O6
M DIO 7
V DD IO
M DIO 8
MD I O9
M DIO 1 0
MD I O1 1
M D I O1 2
M S _ INS#
S5 WAKE ON LAN
PC Ie D if fe re nt ia l
Pa ir s = 10 0 Oh m
B U F _ P L T _ R S T # 4 , 18 , 2 3 , 2 8
R 346
3 .3 V_ L AN
0_04
R3 4 7
C 2 49
C 2 50
RE G L X
D VDD
R 1 76
V C C_ C A RD
C 47 2
2 8 S 5 _ L A NO N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4 .7 K _ 0 4 S D _ CD #
L ANX IN
LA N X O U T
R 1 75
Fo r JM C2 51 /2 61
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3 .3 V_ L AN
S D_ D3
SD _ BS
S D_ D0
S D _D 1
S D_ D2
3 .3 V
M DI O Si ng le
E nd = 5 0
O hm
0 . 1 u_ 1 0 V _ X7 R _0 4
0 . 1 u_ 1 0 V _ X7 R _0 4
P C I E _W A K E #
1 6 , 2 3 P C I E _W A K E #
12 K _ 1 % _ 04
2009/11/17
* 1 0K _ 0 4
D 22
P C I E _ R X P 4 _ GL A N 1 5
P C I E _R X N 4 _ GL A N 15
A
L A N _ P CIE _ W A K E #
C
L A N _ P CIE _ W A K E # 2 8
*S C S 7 5 1 V -4 0
P C I E _ T XN 4 _G L A N 1 5
P C I E _T X P 4 _ GL A N 15
DV D D
3. 3 V _ L A N
3. 3V _ L A N
C LK _P C I E _ GL A N 1 5
C L K _ P C I E _ GL A N # 1 5
C 2 96
4 IN 1 SOCKET SD/MMC/MS/MS Pro
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#26
J _ C A R D -R E V 1
3 . 3 V _ LA N
DV D D
C 24 4
C 44 8
0 . 1 u _1 0 V _ X 7R _ 04
C 2 94
C2 7 5
C 2 45
C 4 31
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#51
0 . 1 u_ 1 0 V _ X7 R _0 4
Pin#62
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#55
1 0 u _6 . 3 V _ X 5 R _ 0 6
Pin#55
Reserved
Pin#8
S D_ C D#
S D_ D 2
S D_ D 3
S D_ B S
Fo r JM C2 51 /2 61
on ly
1 0u _ 6 . 3 V _X 5 R _ 0 6
V CC _ CA R D
Pin#8
S D _ C LK
C 4 26
0 . 1 u _ 10 V _ X 7 R _ 0 4
LA N X OU T
V CC _ CA R D
3 .3 V_ L AN
C 4 25
R1 8 3
1 M_ 0 4
L A N XI N
0 . 1 u _ 10 V _ X 7 R _ 0 4
X4
C 2 95
C2 3 5
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#38
0 . 1 u_ 1 0 V _ X7 R _0 4
Pin#27
2
1
X 8 A 0 2 50 0 0 F G1 H _2 5 MH z
C 2 58
C2 7 1
S D_ D 0
S D_ D 1
S D_ W P
S D _ C LK
S D_ D 3
MS _ I N S #
S D_ D 2
S D_ D 0
S D_ D 1
S D_ B S
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
P1 6
P1 7
P1 8
P1 9
P2 0
P2 1
C D_ S D
D A T 2_ S D
C D / D A T 3_ S D
C MD _S D
V S S _S D
V D D_ S D
C LK _S D
V S S _S D
D A T 0_ S D
D A T 1_ S D
W P _S D
V S S _M S
V C C_ M S
S C L K _ MS
D A T 3_ M S
I N S _ MS
D A T 2_ M S
S D I O/ D A T 0 _M S
D A T 1_ M S
BS_ M S
V S S _M S
M D R 0 19 -C 0 -10 4 2
22 p _ 50 V _ N P O_ 0 4
2 2p _ 5 0 V _N P O _0 4
3 .3 V_ L AN
V C C_ C A RD
C 4 63
C4 1 9
C 2 72
C 2 82
1 0 u _6 . 3 V _ X 5 R _ 0 6
Pin#59
Reserved
0 . 1 u_ 1 0 V _ X7 R _0 4
Pin#59
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#2
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#11
V C C_ CA RD
S D _C L K
Place all capac itors clo sed to chip .
The subscript in eac h CAP incicat es th e pi n
n umber of JM C251/JMC261 tha t should b e
closed to .
B - 26 Card Reader, LAN (JMB251)
C2 8 1
C4 2 8
C4 2 9
C4 5 6
C 2 46
*1 0 p _5 0 V _ N P O_ 0 6
0 . 1 u_ 1 0 V _ X7 R _0 4
4 . 7 u_ 6 . 3 V _ X5 R _0 6
0 . 1 u_ 1 0 V _ X7 R _0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
Near Cardreader CONN
14 , 2 3 , 2 8, 2 9 , 3 1 , 32 , 3 7 V D D 3
26
D V DD
2 , 1 0 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 1, 23 , 2 4 , 2 6, 2 7 , 2 8 , 29 , 3 0 , 3 1, 3 5 , 3 6 3 . 3V S
3 , 4 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9, 20 , 2 1 , 2 3, 2 4 , 2 9 , 30 , 3 1 , 3 3, 3 4 , 3 5 3 . 3V
G ND
G ND
P2 2
P2 3
Schematic Diagrams
LAN (JMC251), SATA HDD, ODD
GIGA LAN (JMC251)
L2 6
L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD
IP 0
IN0
IP 1
IN1
25
25
25
25
L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD
IP 2
IN2
IP 3
IN3
L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD
IP 0
IN0
IP 1
IN1
12
11
9
8
L A N _ MD
L A N _ MD
L A N _ MD
L A N _ MD
IP 2
IN2
IP 3
IN3
6
5
3
2
D V DD
10
7
4
1
R2 7
TD
TD
TD
TD
4+
43+
3-
MX 4 +
MX 4 MX 3 +
M X 3-
T D 2+
T D 2T D 1+
T D 1-
MX 2 +
MX 2 MX 1 +
MX 1 -
TC
TC
TC
TC
T4
T3
T2
T1
MC
MC
MC
MC
13
14
16
17
L MX 1 +
L MX 1 L MX 2 +
L MX 2 -
19
20
22
23
L MX 3 +
L MX 3 L MX 4 +
L MX 4 -
L P2
*S B 0 4 02 T L -04 0 -s ho rt
1
8
D L MX 1 +
2
7
D L MX 1 3
6
D L MX 2 +
4
5
D L MX 2 L P1
*S B 0 4 02 T L -04 0 -s ho rt
4
5
D L MX 3 +
3
6
D L MX 3 2
7
D L MX 4 +
1
8
D L MX 4 -
J _R J 1
1
2
3
6
4
5
7
8
15
18
21
24
T4
T3
T2
T1
DA +
DA DB +
DB DC
DC
DD
DD
s h ei l d
s h ei l d
GN D 1
GN D 2
G ND
+
+
-
P J S -0 8S L3 B
GS T 5 00 9 L F
*0 _ 04
PN:6-19-41001-239
4 0 mil
NM
NM
NM
NM
C3 0
C2 7
C2 5
C2 3
0 . 01 u _ 50 V _ X 7R _ 04
0 . 01 u _ 50 V _ X 7R _ 04
0. 01 u _ 50 V _ X 7R _ 04
0. 0 1 u _5 0 V _ X 7R _0 4
CT _ 1
CT _ 2
CT _ 3
CT _ 4
R2 3
R2 4
R2 5
R3 1
7 5 _ 1%
7 5 _ 1%
7 5 _ 1%
7 5 _ 1%
Sheet 26 of 40
LAN (JMC251),
SATA HDD, ODD
_ 0 4 NM CT _ R
_04
_04
_04
C 3 26
1 0 0 0p _ 2 K V _ X7 R _1 2
SATA HDD
SATA ODD
J_ H D D 1
S
S
S
S
S
S
S
1
2
3
4
5
6
7
S A T A _T X P 0
S A T A _T X N 0
C 4 27
C 4 24
0 . 01 u _ 50 V _ X 7R _ 04
0 . 01 u _ 50 V _ X 7R _ 04
S A T A _R X N 0
S A T A _R X P 0
C 4 23
C 4 22
0 . 01 u _ 50 V _ X 7R _ 04
0 . 01 u _ 50 V _ X 7R _ 04
J _ OD D 1
S A T A T X P 0 14
S A T A T X N0 1 4
S1
S2
S3
S4
S5
S6
S7
S A T A R XN 0 14
S A T A R XP 0 1 4
3 .3 V S
C 4 17
0 . 0 1 u_ 5 0 V _ X7 R _ 0 4
* 10 u _ 6. 3V _ X 5 R _ 0 6
2 2 u _6 . 3 V _ X 5 R _ 08
C 19 9
1 u _ 6. 3 V _ X 5 R _ 0 4
C 4 14
2 2 u _6 . 3 V _ X 5 R _ 08
0 . 1 u _1 0 V _ X 7 R _ 0 4
C 2 00
0 . 1 u _1 0 V _ X 7 R _ 0 4
HD D_ NC 1
HD D_ NC 2
HD D_ NC 3
C 4 13
HD D_ NC 0
C3 8 8
C3 8 7
0 . 0 1 u _5 0 V _ X7 R _0 4
0 . 0 1 u _5 0 V _ X7 R _0 4
S A T A _ RX N 1
S A T A _ RX P 1
C3 8 4
C3 8 3
0 . 0 1 u _5 0 V _ X7 R _0 4
0 . 0 1 u _5 0 V _ X7 R _0 4
P1
P2
P3
P4
P5
P6
5 VS
0 . 1 u _1 0 V _ X 7 R _ 0 4
A C E S -9 19 0 7 -02 2 0 A -H 0 1
P I N GN D 1 ~ 2 = GN D
C 4 18
C 4 15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C 4 16
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
SATA_ TXP1
S A T A _ T X N1
S A T A TX P 1 1 4
S A T A TX N 1 1 4
S A T A RX N1 1 4
S A T A RX P 1 1 4
5V S
OD D _ D E T E C T# 1 4
C3 6 8
C3 7 0
C 3 65
C3 7 5
C3 7 6
C 37 4
*0 . 1 u _1 0 V _ X 5R _0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4
0 . 1 u _1 0 V _ X 7R _0 4
*0 . 1 u _1 0 V _ X5 R _0 4
1 u_ 6 . 3 V _X 5 R _ 0 4
1 0 u _6 . 3 V _ X5 R _0 6
+ C 37 2
1 0 0u _ 6 . 3V _B _ A
C 1 8 55 3 -1 13 0 5 -L
P I N GN D 1 ~ 2 = GN D
+
C 21 1
* 10 0 u _6 . 3 V _ B _ A
5 VS
DV DD
3 .3 V
1 .5 V
3 .3 V S
5 VS
C 28 5
C 81
C 4 39
0 . 0 1u _ 5 0V _X 7 R _ 0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
0. 0 1 u _5 0 V _ X7 R _0 4
2 , 13 , 1 7 , 20 , 2 1 , 2 7, 3 0 , 3 1, 3 5 , 3 6
25
3 , 4, 1 2 , 1 4, 1 5 , 1 6 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 34 , 3 5
4 , 9, 1 0 , 1 1, 2 1 , 2 3 , 27 , 2 9 , 31 , 3 3 , 36
2 , 10 , 1 1 , 12 , 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0 , 21 , 2 3 , 24 , 2 5 , 27 , 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6
LAN (JMC251), SATA HDD, ODD B - 27
B.Schematic Diagrams
25
25
25
25
Schematic Diagrams
Audio Codec VIA 1812
CODEC (VIA1812 /ALC272)
3 .3 V S
1 .5 V
P IN2 5, PI N3 8 ?
R 31 9
1? 1 0u F/. 1u F
*1 5 m li _ s ho rt _ 0 6
R 31 3
*0 _0 4
D1 9
C
C 29 1
C4 4 2
0 . 1 u _1 0 V _ X7 R _ 0 4
10 u _ 6. 3 V _ X 5R _ 06
*R B 5 51 V 3 0
A
5V
5 V S_ A UD
PC BEEP
L2 3
3. 3 V S _ A U D
L 21
K B C _B E E P
1
A
2
A
.
28
H C B 1 6 0 8K F -12 1 T 25
C 4 38
C4 6 7
0 . 1 u _1 0 V _ X 7R _0 4
1 0u _ 6 . 3V _ X 5 R _ 0 6
HD A _ S P K R
BEEP
3
C 2 88
C4 6 5
C 46 4
C2 7 3
0. 1 u _ 10 V _ X 7R _ 04
1 0u _ 6 . 3V _ X 5 R _ 0 6
0 . 1 u_ 1 0 V _X 7 R _ 0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4
C4 3 3
*0 . 1 u_ 1 0V _X 5 R _ 0 4
* 0 . 1u _ 1 0V _ X 5 R _ 0 4
* 0 . 1u _ 1 0V _ X 5 R _ 0 4
C2 7 4
R3 3 1
R3 2 9
R3 2 3
R3 2 2
R3 1 8
1 4, 2 9 H D A _ S D O U T
1 4, 2 9 H D A _ B I T C L K
14
H DA_ S D IN0
1 4, 29 H D A _ S Y N C
1 4 , 2 9 H D A _ R S T#
A UD G
* 2 2p _ 5 0V _ N P O_ 0 4
2 2 _ 04
2 2 _ 04
2 2 _ 04
2 2 _ 04
2 2 _ 04
A LC _G P I O0
A LC _G P I O1
2
3
A Z _ S DO UT _ R
A Z _ B IT CL K _ R
A Z _ S D I N 0 _R
A Z _ S Y N C_ R
A Z _ RS T # _ R
5
6
8
10
11
47
E A P D _M OD E
La yo ut No te :
C4 4 5
2 2 p _5 0 V _ N P O _0 4
Ver y cl os e t o Au di o C od ec
C4 5 1
2 2 p _5 0 V _ N P O _0 4
48
45
46
44
R3 1 1
R3 1 4
C4 3 4
1 0K _ 0 4
PC BEEP_ C
5 . 1K _1 % _ 04
1 00 p _ 50 V _ N P O _ 04
R314
1. 5V V IA 181 2 10 K
3. 3V V IA 181 2 5. 1K
AL C27 2 1K
C 43 5
30
30
1u _ 6. 3V _ X 5 R _ 0 4
C 25 5
C 28 6
*0 . 1 u_ 1 0 V _X 7 R _ 0 4
*0 . 1 u_ 1 0 V _X 7 R _ 0 4
I N T _ MI C R 17 9
1 K _ 04
P CB E E P _ R
43
12
JD 1
JD 2
13
34
M I C _ S E N S E R 1 81
2 0 K _ 1% _ 0 4
H P _S E N S E R 3 34
5 . 1 K _ 1% _ 0 4
C2 6 2
* 10 0 p _5 0 V _ N P O _0 4
C2 8 9
* 10 0 p _5 0 V _ N P O _0 4
MI C _ S E N S E
HP _ S E NS E
C 2 56
C 2 57
I N T _ MI C _R
4 . 7u _ 6 . 3V _X 5 R _ 0 6
4 . 7u _ 6 . 3V _X 5 R _ 0 6
14
15
16
17
MI C 2 _L
MI C 2 _R
18
19
20
MI C 2 -V R E F O
M I C 1 -L
M I C 1 -R
M I C 1 -L
MI C 1-R
R 18 2
R 18 0
M I C 1 _ L_ C
M IC1 _ R_ C
7 5 _1 % _ 04
7 5 _1 % _ 04
C 2 61
C 2 53
4 . 7u _ 6 . 3V _X 5 R _ 0 6
4 . 7u _ 6 . 3V _X 5 R _ 0 6
C4 4 1
C 44 0
L ay ou t N ot e:
6 80 p _ 50 V _ X 7R _ 04
6 8 0p _ 5 0V _X 7 R _ 0 4
V ery c lo se to A ud io Co de c
A UD G
MI C 1 _L
MI C 1 _R
21
22
1
9
A V DD1
A V DD 2
A L C_ V RE F
S D A T A -OU T
B I T -C LK
S D A T A -I N
S Y NC
R ESET#
C 4 52
FOR EMI
A U DG
27
V RE F
28
MI C 1 -V R E F O
M I C 1 -V R E F O
MI C 1 -V R E F O -R
A
1
A
D2 0
B A T 5 4A S 3
2
MI C 1 -V R E F O -L
R3 2 1
R 32 0
S P D I F O1
S P D I F O2
31
30
29
CP V E E
C BN
CB P
C 45 9
C 45 7
2 . 2 u _ 16 V _ X 5R _0 6
2 . 2 u _ 16 V _ X 5R _0 6
N C
P C B E E P -I N
LO U T 1 -L
L OU T 1 -R
S e n s e A ( JD 1)
S e n s e B ( JD 2)
LO U T 2 -L
L OU T 2 -R
L I N E 2-L
L I N E 2-R
La yo ut N ote :
ANALOG
39
41
33
32
H P OU T -L
H P O U T -R
M I C 2 -L
M I C 2 -R
H E A D P H ON E -L 30
H E A D P H ON E -R 3 0
23
24
LI N E 1 -L
L I N E 1 -R
L I N E 1-V R E F O
M I C 2 -V R E F O
L I N E 2-V R E F O
F R ON T-L
F R ON T-R
35
36
J DR E F
R1 9 1
M I C 1 -L
M I C 1 -R
2
5 . 1K _ 1 % _ 04
C2 7 9
* 1 00 p _5 0 V _ N P O _ 04
2 . 2 1K _ 1 % _0 4
J _ I N T MI C 1
I N T _ MI C
V T 18 1 2
A UD G
R 3 35
0_04
F R O N T -R
R 3 38
0_04
C4 6 0
C2 6 4
1 u _6 . 3 V _ X5 R _0 4
1 u _6 . 3 V _ X5 R _0 4
LI N LI N +
C4 6 2
C2 7 0
1 u _6 . 3 V _ X5 R _0 4
1 u _6 . 3 V _ X5 R _0 4
RIN RIN +
SPK_ EN
A UD G
A UD G
R3 2 8
10 0 K _ 04
A
* S CS 3 5 5 V
E A P D _ MO D E _ R
C 4 54
10 0 K _ 04
*1 00 K _ 0 4
R1 8 9
R3 2 7
*1 00 K _ 0 4
10 0 K _ 04
GA I N 0
GA I N 1
? 6 db
5
SPK_ EN
3
2
U 25
M C 7 4V H C 1 G 08 D F T1 G
Gain Settings
GAIN0 GAIN1 AV(inv)
0
0
6 dB
0
1
10 dB
1
1
0
1
15.6 dB
21.6 dB
17
7
19
2
3
1
11
13
20
21
*0 . 1u _ 1 0V _X 5 R _ 0 4
1
4
2 8 K B C _ MU TE #
R3 3 2
R1 9 6
5
9
L INL IN+
R INR IN+
SD #
G AIN0
G AIN1
P V DD
P V DD
V DD
Thermal Pad
F R O N T -L
5 VS
C
D2 1
L OU T +
LO U T -
R OU T +
RO UT G ND
G ND
G ND
BY PASS
G ND
E X P OS E D P A D
NC
L3 4
H C B 10 0 5 K F -12 1 T 20
C4 5 5
C 4 46
C4 3 7
C 45 0
0 . 1 u_ 1 0 V _X 7 R _ 0 4
* 1 u_ 6 . 3 V _X 5 R _ 0 4
10 u _ 6. 3V _ X 5 R _ 06
*1 0 u _6 . 3 V _ X 5R _0 6
6
15
16
5 VS
J_SPK1
2 1
A UD G
J _S P K L1
4
S P K OU T L +
L 22
8
S P K OU T L -
L 20
18
S P K O UT R + 3 0
14
S P K O U T R - 30
10
A UDG
F C M 1 00 5 K F -1 2 1T 0 3
S P K OU T L + _R
S P K OU T L -_ R
12
8 5 2 04 -0 2 00 1
P C B F oo t p ri nt = 8 5 2 04 -0 2 R
C2 7 7
L24
*1 0 m li _ sh o rt
C 2 84
18 0 p _5 0 V _ N P O _0 4
18 0 p _5 0 V _ N P O _0 4
FOR E MI
C 2 59
4 . 7 u _ 6. 3 V _ X 5R _ 06
6-02-07010-AL0
1
2
F C M 1 00 5 K F -1 2 1T 0 3
A MP _ B Y P A S S
N 7 01 0
INPUT IMPEDANCE
90 k
70 k
AU DG
45 k
25 k
1 .5 V
3 .3 V
3 .3 V S
5V
5 VS
B - 28 Audio Codec VIA 1812
8 8 2 66 -0 2 00 1
P C B F o o t pri n t = 88 2 6 6-2 L
R311 VIA1812 5.1K_1%_04
ALC272 20K_1%_04
10/16 change
footprinter
3 . 3V S
0 _0 4
1
2
C1 2 9
U 22
AUD G
R 3 36
1
R7 8
3 30 p _ 50 V _ X 7R _ 04
AUD G
Low mute!
J_INTMIC1
MI C 2- V R E F O
NEAR CODEC
40
JD R E F
AMP (N7010)
PIN 13 ,PIN34 JD_SENSE
19 P C H _ M U T E #
L ay ou t No te :
A UDG
5 V S _ RE A R
E A P D _M OD E
M I C 1 -L
Ne ar MI C con ne ct
D MI C -C L K 1 / 2
D MI C -C L K 3 / 4
A UDG
L ay ou t N ot e:
M I C 1 -R
4 . 7 K _0 4
EAP D
A UD G
C ode c pi n 1 ~ p in 11 a nd p in 44 ~ pi n 48
a re Di gi tal s ig na ls.
T he ot he rs ar e An alo g si gn als .
4 . 7 K _0 4
V er y clo se t o A ud io C ode c
C
3
37
MO N O -OU T
DIGITAL
* 1 5m i _l s h ort _0 6
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
1 0 u_ 6 . 3 V _X 5 R _ 0 6
A U DG
G P I O0 / D MI C - D A T A 1 / 2
G P I O1 / D MI C - D A T A 3 / 4
26
42
30
30
D VDD
D V D D -I O
C2 6 3
C2 5 2
BEEP
C 29 2
L3 6
C 4 69
C 4 68
C 2 67
C 4 32
C 4 43
*0 . 1 u_ 1 0 V _ X7 R _ 0 4
U2 3
AVSS1
A VSS2
MI C 1_ L
MI C 1_ R
* 2 2p _ 5 0V _ N P O_ 0 4
DV SS 1
D VSS2
4
7
* 0 . 1u _ 1 0V _ X 5 R _ 0 4
* 0 . 1u _ 1 0V _ X 5 R _ 0 4
2 2 p _5 0 V _ N P O _0 4
C2 8 0
.
.
B.Schematic Diagrams
C2 6 8
C2 6 9
C4 5 8
25
38
C 4 47
MI C 2_ L
MI C 2_ R
A UD G
5V S
AU DG
A U DG
Sheet 27 of 40
Audio Codec
VIA1812
H C B 1 6 0 8K F -12 1 T 25
* 1u _ 6 . 3V _X 5 R _ 0 4
C
14
.
3. 3 V S
D1 8
B A T 5 4C S 3
4 , 9 , 10 , 1 1 , 21 , 2 3 , 2 9, 3 1 , 3 3, 3 6
3 , 4 , 12 , 1 4 , 15 , 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 34 , 3 5
2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 15 , 1 6 , 17 , 1 8 , 19 , 2 0 , 21 , 2 3 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6
2 1 , 24 , 3 0 , 31 , 3 3 , 34
2 , 1 3, 1 7 , 2 0, 2 1 , 2 6, 30 , 3 1 , 35 , 3 6
Schematic Diagrams
KBC-ITE IT8502E
K B C _A V D D
*1 5 m li _ sh o rt _ 06
C 2 16
C2 4 3
0 . 1 u _1 0 V _ X 7R _0 4
C 24 0
1 0u _ 6. 3V _ X 5 R _ 0 6
C 2 36
L17
H C B 1 0 05 K F -1 2 1 T2 0
.
R3 4 8
V D D3
C2 0 3
0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X7 R _0 4
V D D3
C 2 28
C2 2 9
C2 3 2
0 . 1 u _ 10 V _ X 7R _0 4
*0 . 1 u_ 1 0 V _ X5 R _ 0 4
*0 . 1 u_ 1 0 V _X 5 R _ 0 4
V DD 3
0. 1 u _ 10 V _ X 7 R _ 04
R1 5 4
C 2 37
L 18
H C B 1 00 5 K F -1 21 T 2 0
1 00 K _ 0 4
23
15
30
A P _K E Y #
3 0 W E B _E MA I L #
30
25
S 5 _ LA N ON
2 3 , 29 W L A N _E N
24
3 G_ P O W E R
27
K B C _ MU T E #
37
B A T _ DE T
3 TH E R M _V OL T
2 5 LA N _ P C I E _ W A K E #
24
3 G_ D E T#
24
CCD _ DE T #
37
37
S M C_ B A T
S M D_ B A T
3 , 15 S M C _ C P U _ TH E R M
3 , 15 S M D _ C P U _ TH E R M
27
76
77
78
79
80
81
C P U _F A N
S 5 _ L A NO N
B A T_ D E T
B A T_ V O LT
C U R _S E N S E _ R
66
67
68
69
L A N _ C A B L E _ D E TE C T 7 0
3 G _D E T #
71
C C D _D E T #
72
M OD E L_ I D
73
S M C_ B A T
S M D_ B A T
110
111
115
116
S M C _ C P U _ TH E R M 1 1 7
S M D _ C P U _ TH E R M 1 1 8
L C D_ B RIG HT NE S S
K B C_ B E E P
K B C_ B E E P
LOW ACTIVE
2 9 L E D _ S C R OL L #
29
L E D _ N U M#
29
L E D_ C A P #
2 9 L E D _B A T_ C H G#
2 9 LE D _ B A T _F U L L#
29
L E D_ PW R#
23
23
23
18
30
30
80 C L K
3I N 1
8 0 DE T #
PM E#
T P_ CL K
T P _ DA T A
37
V C H G_ S E L
85
86
87
88
89
90
8 0 CL K
3 IN 1
8 0 DE T #
125
18
21
31
PW R_ S W #
1 2, 3 0
L ID_ S W #
33
3 0 W E B _W W W #
2 3, 2 9
12
24
25
28
29
30
31
32
34
108
109
B T _E N
B K L_ E N
12
B RIG HT NE S S
R1 4 7
C2 1 9
* 10 m i _l s ho rt
74
3
VBAT
AVC C
26
50
92
11 4
121
12 7
E C S C I # / GP D 3( P U )
E C S M I # / GP D 4( P U )
DAC
DA C
DA C
DA C
DA C
DA C
DA C
0/ G
1/ G
2/ G
3/ G
4/ G
5/ G
PJ 0
PJ 1
PJ 2
PJ 3
PJ 4
PJ 5
IT8502E
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
0/ G
1/ G
2/ G
3/ G
4/ G
5/ G
6/ G
7/ G
F L F R A M E #/ G P G2
F L A D0 /S CE#
F L A D1 /S I
F LA D 2 / S O
F L A D 3/ G P G6
F LC LK / S C K
( P D )F L R S T # / W U I 7 / T M/ G P G0
GPIO
SMBUS
S MC
S MD
S MC
S MD
S MC
S MD
LK 0 / G
A T0 / G
LK 1 / G
A T1 / G
LK 2 / G
A T2 / G
( P D )K S O1 6/ G P C 3
( P D )K S O1 7/ G P C 5
PB3
PB4
P C1
P C2
PF6 ( PU )
PF7 ( PU )
(
(
(
(
(
(
(
PWM
PW
PW
PW
PW
PW
PW
PW
PW
M0 / G
M1 / G
M2 / G
M3 / G
M4 / G
M5 / G
M6 / G
M7 / G
P A 0(
P A 1(
P A 2(
P A 3(
P A 4(
P A 5(
P A 6(
P A 7(
PU
PU
PU
PU
PU
PU
PU
PU
)
)
)
)
)
)
)
)
0/ G
1/ G
2/ G
3/ G
4/ G
5/ G
6/ G
P H0
P H1
P H2
P H3
P H4
P H5
P H6
( P D )I D 7/ G P G1
)
)
)
)
)
)
( P D )W U I 5 / GP E 5
( P D )L P C P D #/ W U I 6 / GP E 6
PWM/COUNTER
( P D )T A C H 0/ G P D 6
( P D )T A C H 1/ G P D 7
( P D )TM R I 0 / W U I 2/ G P C 4
( P D )TM R I 1 / W U I 3/ G P C 6
CIR
RI1 # /W UI0 /G P D0 ( P U )
RI2 # /W UI1 /G P D1 ( P U )
( P D )C R X/ G P C 0
( P D )C T X / GP B 2
GP INTERRUPT
K B -S O0
K B -S O1
K B -S O2
K B -S O3
K B -S O4
K B -S O5
K B -S O6
K B -S O7
K B -S O8
K B -S O9
K B -S O1 0
K B -S O1 1
K B -S O1 2
K B -S O1 3
K B -S O1 4
K B -S O1 5
1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24
( P D )L8 0 H L A T / GP E 0
( P D )R I N G# / P W R F A I L #/ LP C R S T # / GP B 7
CLOCK
0 . 1 u _1 0 V _ X 7R _0 4
100
101
102
103
104
105
106
L C D_ B RIG HT NE S S
EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)
V ER .
RX
V OL TA GE
MO DE L_I D
V 1. 0
R1 53 10 K/ R 149 X
3. 3V
E4120
R1 53 X /R 14 9 1 0K
0V
MO D E L _ I D
R1 5 3
1 0K _ 0 4
R1 4 9
V DD3
S M D_ B A T
S M C_ B A T
V DD 3
*1 0 K _ 04
Sheet 28 of 40
KBC-ITE IT8502E
RX
R N 19
2. 2K _ 4 P 2 R _ 0 4
3
2
4
1
3 G _D E T #
C C D _D E T #
R 1 43
R 1 46
C K 32 K E
C K 32 K
1 0 K _ 04
1 0 K _ 04
KB C_ S P I_ S CL K
CC D_ E N
24
56
57
S USB #
S USC #
16 , 2 3 , 31
16 , 3 3
93
94
95
96
97
98
99
S US _ P W R _ A CK 1 6
ME _ W E #
14
A C _ P R E S E N T 1 6 , 18
D D _O N _ L A T C H 31
W L A N _ D E T# 2 3
B T _D E T # 29
D D _O N
31
107
3 G_ E N
82
83
84
C2 2 3
P CL K _ K B C
R1 6 0
*1 0_ 0 4 P C L K _ K B C _ R
* 10 p _ 50 V _ N P O_ 06
C2 0 9
24
B A T _ V OL T
1 u _ 6. 3 V _ X 5R _ 04
S MI #
19
S CI#
19
P W R _B T N # 1 6
35
17
RS M RS T # 1 6
K B C _ R S T# 1 9
47
48
MC H _ TS A TN _E C
120
124
CP U _ F A NS E N
4 ,1 9
S M C _ C P U _ TH E R M
H _P E C I
R1 7 3
*0 _ 0 4
30
V CO RE _ O N 3 6
A L L_ S Y S _ P W R G D 1 2 , 16
V DD 3
119
123
C2 1 0
0 . 1 u _1 0 V _ X7 R _0 4
KBC_SPI_*_R = 0.1"~0.5"
51 2K bit
U9
19
S W I#
112
2
128
C H G_ E N
16
R1 3 1 1 K _ 0 4
37
R 16 5
R 1 5 8 4 . 7 K _ 04
K B C _ H O LD #
* 10 M_ 0 4
X2
C M2 0 0S 3 2 7 68 1 2 20 _ 3 2. 7 6 8 K H z
1
4
2
3
VD D
? ? ?
K B C_ F L A S H
CK 3 2 K E
CK 3 2 K
C2 3 8
N C3
24
J_KB1
KB C_ S P I_ CE #
KB C_ S P I_ S I
KB C_ S P I_ S O
1 2p _ 5 0V _N P O_ 0 4
W/ 0 CI R)
1
8
LPC/WAKE UP
GI N T/ G P D 5 ( P U )
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
1 u_ 6 . 3 V _ X5 R _ 0 4
3 7 B A T_ V O LT
WAKE UP
PU
PU
PU
PU
PU
PU
WAKE UP
RX D/G P B 0 ( P U )
TX D / GP B 1 ( P U )
)I D
)I D
)I D
)I D
)I D
)I D
)I D
( P D )E GA D / GP E 1
( P D )E G C S # / GP E 2
( P D )E G C L K / GP E 3
P W R S W / GP E 4 ( P U )
UART
PD
PD
PD
PD
PD
PD
PD
EXT GPIO
PS/2
P S 2 C L K 0 / GP F 0 (
P S 2 D A T 0 / GP F 1 (
P S 2 C L K 1 / GP F 2 (
P S 2 D A T 1 / GP F 3 (
P S 2 C L K 2 / GP F 4 (
P S 2 D A T 2 / GP F 5 (
4
5
6
8
11
12
14
15
VDD 3
FLASH
P I0
P I1
P I2
P I3
P I4
P I5
P I6
P I7
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
*0 _ 0 4 E C _V S S
R1 6 4
C2 3 3
K S O0 / P D 0
K S O1 / P D 1
K S O2 / P D 2
K S O3 / P D 3
K S O4 / P D 4
K S O5 / P D 5
K S O6 / P D 6
K S O7 / P D 7
K S O8 / A C K #
K S O9 / B U S Y
K S O1 0 / P E
K S O1 1/ E R R #
K S O 12 / S L C T
K S O 13
K S O 14
K S O 15
GA 2 0 / GP B 5
K B R S T # / GP B 6( P U )
P W U R E Q# / G P C 7 ( P U )
L8 0 L LA T / G P E 7 ( P U )
I T 85 0 2 E -J
0 _0 4 FO R I T8 51 2CX /E X
0 .1 U_ 04 FO R IT E85 12 -J (I TE8 50 2- J
E C Co st Do wn
VS TBY
VST BY
VS TBY
VST BY
VST BY
VST BY
W RS T #
58
59
60
61
62
63
64
65
3
7
SI
SO
CE #
SCK
5
2
1
6
K B C_ S P I_ S I_ R 1
K B C _ S P I _ S O_ R 2
K B C_ S P I_ CE # _ R 1
K B C _ S P I _ S C L K _ R2
4
3
4
3
R N 18
15 _ 4 P 2R _ 04
R N 17
15 _ 4 P 2R _ 04
KBC
KBC
KBC
KBC
_ S P I_ S I
_ S P I_ S O
_ S P I_ CE #
_ S P I_ S CL K
C 2 26
C 2 27
C 1 97
C 1 98
*3 3 p_ 5 0 V _N P O_ 0 4
*3 3 p_ 5 0 V _N P O_ 0 4
*3 3 p_ 5 0 V _N P O_ 0 4
*3 3 p_ 5 0 V _N P O_ 0 4
WP #
H OL D #
VSS
4
E N 2 5 P 05 -5 0 GC P
C 2 31
1 2 p _5 0 V _ N P O _0 4
V DD 3
3 . 3V S
14 , 2 3 , 25 , 2 9 , 31 , 3 2 , 3 7
2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 6 , 2 7, 2 9 , 3 0, 3 1 , 3 5, 3 6
S HO RT
K B C _ A GN D
*0 . 1 u_ 1 0 V _X 5 R _ 0 4
KBC-ITE IT8502E B - 29
B.Schematic Diagrams
126
4
16
20
19
GA 2 0
37
A C_ IN #
29
LE D _ A C I N #
3 TH E R M _A LE R T #
K S I 0/ S TB #
K S I1 /A F D#
K S I 2 / I N I T#
K S I3 /S L I N#
K S I4
K S I5
K S I6
K S I7
K/B MATRIX
AVSS
14
LPC
J_ K B 1
8 5 20 1 -2 40 5 1
75
K B C _ W R E S E T#
LA D 0
LA D 1
LA D 2
LA D 3
LP C C L K
LF R A ME #
SE RIR Q
LP C R S T # / W U I 4/ G P D 2 ( P U )
VS S
VSS
VS S
VSS
VSS
VSS
VSS
P C L K _K B C
V CC
10
9
8
7
13
6
5
22
C2 2 4
1
12
27
49
91
11 3
122
.
U1 2
1 4, 2 4
L P C _A D 0
1 4, 2 4
L P C _A D 1
1 4, 2 4
L P C _A D 2
1 4, 2 4
L P C _A D 3
18
P CL K _ K B C
1 4, 24 L P C _ F R A ME #
1 4, 2 4
S E RIR Q
4 , 1 8 , 23 , 2 5 B U F _ P L T _R S T #
K B C_ W R E S E T #
11
3 .3 V S
K B C _A G N D
0. 1 u _ 10 V _ X 7R _ 04
E C _V C C
Schematic Diagrams
LED, MDC, BT
3 V_ BT
Bluetooth(Port8)
COSTDOWN
Port 11
3 .3 V
MJ_MDC1
12
20 MIL
R3 4 4
11
R 16 3
2
1. 5 V
18
18
28
23
*1 5 m li _ sh o rt _ 06
47 K _ 0 4
1
1
2
3
4
5
6
B T_ E N #
3 .3 V
8 7 2 12 -0 6 G0
3 .3 V
3 3_ 0 4 H D A _ S Y N C _ R
2 2_ 0 4 H D A _ S D I N 1_ R
3 3_ 0 4 H D A _ R S T # _R
GN D
RE S E R VE D
A za l ai _ S D O
RE S E R VE D
GN D
3 . 3V Ma ni / a u x
A za l ai _ S Y N C
G ND
A za l ai _ S D I
G ND
A za l ai _ R S T #
A z al i a_ B C LK
8 8 01 8 -1 20 G
2
4
6
8
10
12
R 1 62
*0 _ 06
C4 7 3
10mil L1 6
M D C _3 . 3 V
3. 3 V
* 18 0 p _5 0 V _ N P O _0 4
R 14 8
3 3 _ 04
C2 2 5
C 22 0
0 . 1u _ 1 0V _ X 7 R _ 0 4
2 2 p_ 5 0 V _N P O_ 0 4
*0 _ 04
From EC default HI
*1 5m i l _s h o rt _0 6
H D A _B I T C LK _ R
R3 0 2
P C H _ B T_ E N #
R3 0 3
1 0K _0 4
2 3, 28
50m il
* 15 m i _l s h ort _ 0 6
Q1 7
MT N 70 0 2 Z H S 3
G
BT_ EN
3 V _B T
R3 0 1
50m il
B T_ E N #
H D A _B I T C LK 1 4 , 2 7
C4 7 4
C 40 9
1 80 p _5 0 V _ N P O _0 4
R1 5 7
R1 5 5
R1 5 1
1
3
5
7
9
11
1 0 u_ 6 . 3 V _X 5 R _ 0 6
S
1 4 , 27 H D A _ S Y N C
14
H DA _ S DIN 1
1 4 , 27 H D A _ R S T #
3 3_ 0 4 H D A _ S D O U T _ R
3 .3 V
D
1 4 , 27 H D A _ S D O U T
R1 6 1
15
B T _ DE T #
J _ MD C 1
G ND
C 4 07
1 0 u _6 . 3 V _ X5 R _0 6
U2 1
4
5
3
B T _E N
V IN
V IN
1
V OU T
EN
2
G ND
* G5 2 43 A
3. 3 V S
V D D3
L E D _ N U M# 2 8
L E D _C A P # 28
R 19 4
2 2 0_ 0 4
2 2 0_ 0 4
2 20 _ 0 4
2 20 _ 04
2 2 0_ 0 4
2 2 0_ 0 4
3
1
3
D1 3
Y
SG
1
R Y -S P 15 5 H Y Y G 4
BAT LED
D 12
R Y -S P 1 5 5 H Y Y G4
R Y -S P 15 5 H Y Y G 4
4
4
2
POWER ON
LED
2
D1
Y
3
1
SG
2
WLAN
LED
4
1
2
D5
SCROLL
LOCK
LED
R 19 5
C
A
BT
LED
R1 9 3
L E D_ P W R # 2 8
B
L E D _ S C R OL L # 28
E
C
V D D3
R1 9 2
W L A N_ E N
L E D _B A T _ F U L L # 28
2 3, 2 8
L E D _A C I N # 2 8
Q2
D TC 11 4 E U A
LE D _ B A T _C H G # 2 8
C
C
D4
CAPS
LOCK
LED
C
D 3
D 2
NUM
LOCK
LED
V DD 3
R5
1
2 2 0 _0 4
R Y -S P 17 2 Y G3 4
HDD/ODD
LED
V DD 3
R 6
Y
2 2 0_ 0 4
A
22 0 _ 04
A
22 0 _ 04
R 4
A
R1
R 3
C
Q 3
D T A 1 14 E U A
R2
R Y -S P 1 7 2 Y G3 4
S A T A _L E D # 14
R Y -S P 1 72 Y G 34
C
B
3 .3 V S
3. 3 V S
2
3. 3 V S
3
3 .3 V S
4
3 .3 V S
SG
LED
E
Sheet 29 of 40
LED, MDC, BT
PN:G5 24 3A-- 6-0 2- 05 243 -9 C0
R Y -S P 1 72 Y G 34
B
BT_ EN
E
B.Schematic Diagrams
J _B T1
U S B _P N 1 1
U S B _P P 11
B T _ DE T #
B T_ E N #
H2
C 1 5 8 D 1 58
M2
M-M A R K 1
M6
M -MA R K 1
M7
M-MA R K 1
M8
M-M A R K 1
H1
C 1 58 D 1 5 8
H 12
H 6_ 3 D 3 _ 8
4 , 9 , 10 , 1 1 , 21 , 2 3 , 27 , 3 1 , 33 , 3 6 1. 5V
3 , 4, 1 2 , 1 4, 1 5 , 1 6, 18 , 1 9, 20 , 2 1 , 23 , 2 4 , 25 , 3 0 , 31 , 3 3 , 34 , 3 5 3. 3V
14 , 2 3 , 25 , 2 8 , 31 , 3 2 , 37 V D D 3
2, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 20 , 2 1, 23 , 2 4 , 25 , 2 6 , 27 , 2 8 , 30 , 3 1 , 35 , 3 6 3. 3V S
H 10
H 8
H 6_ 3 D 3 _ 8 H 6 _3 D 4_ 4
H 11
3
4
5
M1
M -MA R K 1
H7
1
9
8
7
6
MT H 3 1 5D 1 11
M5
M-MA R K 1
M3
M-M A R K 1
M4
M -MA R K 1
H 20
H 6 _0 D 3_ 7
H 16
H 6_ 0 D 3 _ 7
H 13
H 6_ 0 D 3 _ 7
H1 7
H 19
H 4 _ 7 B 6_ 0 D 3 _ 7 H 4_ 7 B 6 _0 D 3_ 7
B - 30 LED, MDC, BT
H 23
C 15 8 D 1 5 8
H2 2
C1 5 8 D1 5 8
H2 1
H 18
H 4 _ 0B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7
H2 4
1
9
8
7
6
3
4
5
MT H 3 1 5 D 1 11
H 27
1
9
8
7
6
3
4
5
MT H 31 5 D 1 1 1
H 9
H1 5
1
9
8
7
6
3
4
5
MT H 3 1 5D 1 11
H4
1
MT H 3 1 5D 1 11
H 6
C 67 D 67
3
4
5
H1 4
1
9
8
7
6
3
4
5
MT H 31 5 D 1 1 1
1
9
8
7
6
M TH 3 15 D 1 1 1
2009/11/5
3
4
5
H 25
C 6 7D 6 7
2 3, 2 8
Q 1
D TC 1 14 E U A
9
8
7
6
3
4
5
H 5
1
MT H 31 5 D 1 1 1
9
8
7
6
3
4
5
H3
1
MT H 3 1 5D 1 11
9
8
7
6
3
4
5
H2 6
1
MT H 31 5 D 1 1 1
9
8
7
6
3
4
5
1
M TH 3 15 D 1 1 1
9
8
7
6
Schematic Diagrams
USB, Fan, TP, Multi Con1
USB PORT*2(Port 0,Port1)
FAN CONTROL
5 V S _F A N
5 VS
U1 9
F O N#
U4
5V
U S B _F L G #
5
C 10 0
3
1 0 u_ 6 . 3 V _ X5 R _ 0 6
4
31 , 3 3
VIN 1
V OU T2
VIN 2
V OU T3
EN #
GN D
1
2
3
4
U S B V C C 01
6
F L G # V OU T1
2
7
100 MIL
8
C1 1 7
C 12 8
C 13 5
1
0 . 1u _ 1 0V _ X 7 R _ 0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4
* 10 u _ 6. 3 V _ X 5R _0 6
28
CP U_ F A N
F ON
V IN
V OU T
VSET
8
7
6
5
GN D
GN D
GN D
GN D
G9 9 0 P 11 U
R T 97 1 5 B GS
D D _O N #
5 VS
5V S _F A N
J _F A N 1
1
2
3
C4 0 2
US B V C C0 1
C 4 01
0 . 1u _ 1 0V _ X 7 R _ 04
U S B _ V C C 0 1_ 0
8 5 2 05 -0 3 70 1
1 0 u _6 . 3 V _ X5 R _0 6
60 mil
.
+C 9 8
C8 7
1 00 u _ 6. 3 V _ B _ A
Port 0
0. 1 u _ 10 V _ X 7R _0 4
28 C P U _ F A N S E N
R2 7 3
3 .3 V S
4 . 7 K _0 4
JFAN
Sheet 30 of 40
USB, Fan, TP,
Multi Con
3
J _U S B 1
1
4
U S B _ P N0
18
L9
3
2
1
2
*W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt
US B _ P P 0
DA T A _ L
3
GN D
3 .3 V
R7 4
1 0K _ 0 4
R 77
*1 0 K _ 04
FO R CL IC K BO AR D
GN D 1
G ND2
GN D 3
GN D 4
C 1 07 7 0 -10 4 A 3
18
CLICK CONN
DA T A _ H
4
3 .3 V
GN D 1
G ND2
GN D 3
G ND4
18
1
V+
U S B _ V CC0 1 _ 0
5 V S _T P
5 VS
U S B _ F L G#
U S B _ OC # 0 1
R9 4
*1 5m i l _s h or t _0 6
C1 6 4
80 mil
R7 3
*0 _ 04
R 85
R 84
1 0 K _0 4
1 0 K _ 04
C 1 69
*1 0 u _6 . 3 V _ X5 R _0 6
+
C1 3 6
C 1 77
J _T P 1
10 0 u _6 . 3 V _ B _ A
0 . 1 u _1 0 V _ X7 R _0 4
1
2
3
4
Port 1
18
US B _ P P 1
4
L1 3
3
2
1
2
*W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt
3
4
4 7 p_ 5 0 V _N P O_ 0 4
D A TA _ L
D A TA _ H
G ND 1
GN D 2
G ND3
GN D 4
U S B _ P N1
C 15 5
4 7 p_ 5 0 V _N P O_ 0 4
V+
G ND
C 1 0 7 70 -1 0 4A 3
G ND 1
GN D 2
G ND3
GN D 4
18
C 15 9
28
28
8 5 20 1 -04 0 5 1
J _ US B 2
1
1u _ 6 . 3V _ X 5 R _ 04
TP _ D A TA
TP _ C LK
POWER SWITCH CONN.
CLOSE TO J_SW1
FO R PO WE R SW IT CH B OA RD
AP_ KEY#
AP_ KEY # 2 8
3 . 3V S
3 .3 V
3 . 3V
D
3 .3 VS
C2 0
CONN.(Port 2)
C1 9
Q 6
G
5V
0 . 0 1u _ 5 0V _ X 7 R _ 04
J _ SW 2
1
2
3
4
5
6
7
8
MT N 7 0 0 2Z H S 3
S
Audio/B
0 . 01 u _ 50 V _ X 7R _0 4
1.1A 60mils
C 2 22
0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
F OR A UD IO B OA RD
J _ A U D I O1
R1 5 0
27 M I C 1 -R
27 M I C 1 -L
2 7 H E A D P H O N E -R
2 7 H E A D P H O N E -L
27 M I C _ S E N S E
18
18
U S B _P N 4
R 1 69
U SB_ PP4
R 1 71
*1 0 mi l _ sh o rt
*1 0 mi l _ sh o rt
U S B N4 _ R
27 H P _S E N S E
U S B P 4 _R
27 S P K O U T R +
27 S P K O U T R -
* 1 5m i l_ s h ort _ 0 6
M I C 1 -R
M IC1 -L
H E A D P H ON E -R
H E A D P H ON E -L
M IC_ SE NS E
SPK_ H P#
H P _S E N S E
U S B N4 _ R
U S B P 4 _R
S P K O UT R+
S P K O UT R-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J_ S W 1
2 0m il
1
2
3
4
5
6
7
8
9
10
*5 0 50 0 -01 0 4 1-0 0 1 L
R 20
M _ B TN # _R
W E B _W W W #
W E B _E MA I L #
L I D _S W #
A P _O N
1 00 K _ 0 4
M _B T N #
31
W EB_ W W W # 2 8
W E B _ EM A IL # 2 8
L I D _ S W # 1 2, 2 8
2 0m il
M BTN
R1 7
W E B _W W W #
W E B _E M A I L #
L I D _S W #
1 00 K _ 0 4 M _B TN #
A P _K E Y #
8 8 4 86 -0 80 1
A P _O N
31
3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 1, 3 3 , 3 4, 3 5 3 . 3V
2, 1 3 , 1 7, 2 0 , 2 1, 2 6 , 2 7, 3 1 , 3 5, 3 6 5 V S
2 1, 2 4 , 2 7, 3 1 , 3 3, 3 4 5 V
VIN
1 2, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 V I N
2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 8 , 2 9, 3 1 , 3 5, 3 6 3 . 3V S
8 7 21 3 -1 40 0 G
If system has APON function, uses J_SW1
If system has no APON function, uses J_SW2
USB, Fan, TP, Multi Con1 B - 31
B.Schematic Diagrams
L 10
H C B 16 0 8 K F -1 21 T 25
Schematic Diagrams
5VS, 3VS, 1.05VS
VA
V IN
V IN 1
S Y S 5V
PC 6 5
P C 64
PC 6 3
0 . 1 u _5 0 V _ Y 5 V _ 0 6
0 . 1 u_ 5 0 V _ Y 5 V _ 0 6
0 . 1 u _ 50 V _ Y 5V _0 6
ON
DD_ON "L " TO
"H" FROM EC
PU 3
1
VA
2
V IN
30
3
M _B TN #
P_ SW 1
*T J G -53 3 -S -T / R
2
4
30
4
A P _ ON
VA
8
V IN1
VIN
I N S T A N T -ON
D D _O N _ L A T C H
6
P W R_ S W #
GN D
P R1 9 4
1 0 K_ 0 4
10 K _ 0 4
S US B
28
D D _ ON #
PW R _ SW # 2 8
5
P Q4 5 A
MT D N 7 0 02 Z H S 6 R
P R 85
1 0 K _ 04
P 2 8 08 A 1
1
3
P R1 9 3
D D _ ON #
7
D D _ ON _L A T C H
M_ B T N #
V IN 1
SY S5 V
V DD 3
28
6
P Q4 5 B
MT D N 7 0 0 2Z H S 6 R
2 G
D D _O N
P C1 8 9
6
5
S US B #
3
D
5 G
P C1 9 0
S
4
* 0 . 1 u_ 1 0 V _ X5 R _0 4
*0 . 1 u_ 1 0 V _ X 5R _ 04
ON
P R 1 95
ON
1 0 0K _ 0 4
1 0 0K _0 4
5V
ON
ON
5V
C2 7 6
C9 7
0 . 0 1u _ 5 0 V _X 7 R _0 4
0 . 0 1u _ 5 0V _X 7 R _ 0 4
0. 0 1 u _ 50 V _ X 7 R _ 0 4
5VS
S Y S 1 5 V V D D5
3A
PR 9 8
1.5VS
NMO S
P Q 47
P 1 2 03 B V
8
7
3
6
2
5
1
S Y S 1 5V
V D D5
P Q4 6
P 12 0 3 B V
8
7
3
6
2
5
1
5V
3A
5V
P R 97
Power Plane
SYS1 5 V
1M _ 04
Z 3 50 7
6
P C 74
S
1 .5 V S _ E N
S
PJ 1 1
4
P C1 9 4
S USB
33
P C 1 91
0 . 1 u_ 1 0 V _ X7 R _ 04
1 0 u_ 6 . 3 V _ X 5R _ 0 6
P R 19 6
3Z 3 5 1 5
D
6
D
P Q4 8 A
M T D N 7 00 2 Z H S 6 R
S US B
G
22 0 0 p _5 0 V _ X 7R _ 04
2
P Q 48 B
M TD N 7 0 0 2Z H S 6 R
5 G
S
P J1 2
S
4 0 m il
1
4
4 0m i l
2
2
P C 19 2
1 00 _ 1 % _0 4
P Q1 5 B
M T D N 7 00 2 Z H S 6R
G
4 7 0p _ 5 0V _X 7 R _ 0 4 5
1
1 .5 V S
3
D
P C 73
1
2
4 7 0 p_ 5 0 V _ X7 R _ 04
0 . 1 u _ 10 V _ X 7 R _ 0 4
PQ 1 5 A
M T D N 70 0 2 Z H S 6R
G
D D _ ON #
1
D
NMO S
P Q1 6
P 1 20 3 B V
8
7
3
6
2
5
1
P C1 9 3
4
Z 3 5 06
1 .5 V
P R1 9 7
1 M_ 0 4
4
1 M _0 4
5 VS
4
Sheet 31 of 40
5VS, 3VS, 1.05VS
C2 1 2
3 .3 V S
ON
VA
37
1. 5V S _C P U 4, 7
1. 5V
4 , 9, 10 , 1 1 , 2 1, 2 3 , 2 7 , 2 9, 3 3 , 3 6
1. 5V S
2 0, 2 3 , 3 6
SYS5 V
3 2, 3 7
5V
2 1, 2 4 , 2 7 , 3 0, 3 3 , 3 4
3. 3V
3 , 4, 12 , 1 4 , 1 5, 1 6 , 1 8 , 1 9, 2 0 , 2 1 , 2 3, 2 4 , 2 5 , 29 , 3 0 , 3 3 , 34 , 3 5
V IN1
32
V IN
1 2, 3 0 , 3 2 , 3 3, 3 4 , 3 5 , 3 6, 3 7
V DD 5
32
V DD 3
1 4, 2 3 , 2 5 , 2 8, 2 9 , 3 2 , 3 7
3. 3V S
2 , 10 , 1 1 , 1 2 , 13 , 1 4 , 1 5 , 16 , 1 7 , 1 8, 19 , 2 0 , 2 1, 2 3 , 2 4 , 2 5, 2 6 , 2 7 , 2 8, 2 9 , 3 0 , 35 , 3 6
SYS1 5 V
32
5V S
2 , 13 , 1 7 , 2 0 , 21 , 2 6 , 2 7 , 30 , 3 5 , 3 6
ON
3 .3 V
C 105
C 1 90
0 . 0 1 u_ 5 0 V _ X7 R _ 04
0 . 0 1 u _5 0 V _ X 7 R _ 0 4
0 . 0 1 u_ 5 0 V _ X 7R _ 04
1.5VS_CPU
3.3VS
1 . 5V S _ C P U
1 .5 V
2
S Y S 1 5 V V D D3
3A
P Q 41
P 1 2 03 B V
8
7
3
6
2
5
1
NMO S
S Y S 15 V
3 .3 V
3A
Power Plane
P R 1 74
VDD 3
PR9 6
1 M_ 0 4
1 M _0 4
PJ 4
O P E N _2 A
1
PJ3 MUST SHORT
SY S1 5 V
P Q1 3
P 1 2 03 B V
8
7
3
6
2
5
1
3. 3V S
PR 6 3
* 1M _ 04
P C 70
PC 7 2
0 . 1 u_ 1 0 V _ X 7R _ 04
1 0 u _6 . 3 V _ X 5 R _ 0 6
PQ 3
* P 1 20 3 B V
8
7
3
6
2
5
1
NM OS
P R 60
*2 2 0 _ 04
P C2 8
PC 2 7
*0 . 1 u_ 1 0 V _ X5 R _ 04
* 10 u _ 6 . 3 V _X 5 R _0 6
Z 35 0 9
1 .5 V S _ CP U E N
4
4
P R9 5
Z 3 5 08
Z 35 1 6
3.3V
C 13 7
4
* 1 00 _ 0 4
2 2 0 0p _ 5 0 V _X 7 R _0 4 2
PQ 1 4 A
M T D N 70 0 2 Z H S 6R
D
G
S
1
D D _ ON #
PC7 1
3
D
2 20 0 p _ 50 V _ X 7 R _ 0 4
5
S
D
6
P C 1 70
G
SU SB
G
S
B.Schematic Diagrams
1 6 , 2 3, 2 8
S
1
P R 19 2
DEBUG USE
EVT? ? ?
3 0 ,3 3
D
4
Z 35 1 0
P Q1 2
* MT N 70 0 2 Z H S 3
PC 2 9
6
D
* 22 0 0 p _5 0 V _ X 7R _ 04
2
S
3
P Q 2A
*2 N 7 00 2 K D W
G
SU SB
S
1
4
P Q1 4 B
M T D N 70 0 2 Z H S 6R
ON
B - 32 5VS, 3VS, 1.05VS
D P Q2 B
*2 N 7 0 0 2K D W
5 G
ON
Schematic Diagrams
Power 3.3V/5V
S Y S 5V
L G ATE1
PC 1 6 8
0 . 0 1u _ 5 0 V _ X 7R _ 04
Z 3 6 13
C
A
PD 6
SY S5 V
RB 0 5 4 0 S 2
C9 4
A
V IN 1
P R1 8 6
RB 0 5 4 0 S 2
P C1 6 4
2_06
A
P C1 8 5
1 00 0 p _ 5 0V _X 7 R _ 0 4
P R 1 78
2 20 0 p _ 50 V _ X 7 R _ 0 4
C
PC 1 6 9
0 . 0 1u _ 5 0 V _ X 7R _ 04
Z 3 6 14
P D 1 6 R B 0 5 4 0S 2
I N TV C C 2
C
A
PD 4
RB 0 5 4 0 S 2
2 _ 06
6 -1 3- 42 23 1 -2 8B
P R1 8 5
SY S1 0 V
0 . 0 1u _ 5 0 V _ X7 R _ 04
VI N
PD 5
Z 3 6 04
P C1 8 4
2. 2 u _ 1 6 V _ X5 R _ 06
C
A
4 2 2 K _ 1 %_ 0 6
S G ND 4
C
SY S1 5 V
Z 3 6 05
PD 3
RB 0 5 4 0 S 2
P C1 6 5
Z 3 60 6
2 20 0 p _ 50 V _ X 7 R _ 0 4
P C5 3
P C5 4
LX
4 . 7u _ 2 5 V _ X 5 R _ 0 8
4. 7 u _ 2 5V _X 5R _ 0 8
Z 3 60 7
Z 3 60 8
9
Z 3 60 9
IN T V CC 2
5
6
7
8
P C1 7 3
1 u_ 2 5 V _ 0 8
8
PQ 1 0
I R F 8 7 07 P B F
4
1 0 Z 3 61 0
VDD5
S YS5 V
V DD 5
P L8
4 . 7 U H _ 6 . 8* 7 . 3 *3 . 5
1
2
LG A T E 1
P Q6
I RF 8 7 0 7 P B F
4
OCP
P J 19
5A
1
P R 19 8
P C 1 86
PR 1 9 0
PD 7
*2 . 2 _ 0 6
* 2 20 p _ 5 0V _0 4
9 1 K _ 1 %_ 0 6
S K 3 4S A
Z3611
P R1 7 3
1 0K _1 % _ 0 4
Z3612
P R1 6 9
*1 0 0 K _ 04
A
P C 16 6
P C5 5
+
P C 19 5
P C 1 71
+
0 . 1 u _5 0 V _ Y 5V _0 6
PR 1 6 8
11 3 K _ 1 % _ 04
Sheet 32 of 40
Power 3.3V/5V
2
* OP E N -5 m m
C
4
PG N D
DH
6
7
11
15
P C4 8
P C1 8 2
1u _ 2 5 V _ 08
N C
5
3
FBL
V O UT
V DD A
2
FB
IL IM
P R 17 5
1 37 K _ 1 % _ 0 4
BST
E N/P S V
D L
P C1 7 6
*0 . 1 u _1 0 V _ X 5 R _0 4
P R1 8 0
10 K _ 0 4
1 u _ 2 5V _0 8
1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4
P C1 8 0
SC418
A GN D
V DD P
16
PC 1 7 4
V L DO
RP S V
17
VIN
RT O N
12
Z3601
E NL
13
18
PAD
21
19
P G O OD
Z3603
14
S G ND 4
Z3602
20
PU8
P C 1 87
PR 1 8 3
*2 2 0 0 p_ 5 0 V _ X 7R _ 0 4
* 1 00 p _ 5 0 V _ N P O _ 04
P C1 6 7
P C 1 78
1u _ 2 5 V _ 08
1 u _2 5 V _ 0 8
*1 5 0 u _6 . 3 V _ V _ A
P R1 9 1
* 1 5m i l _ sh o rt _ 0 6
1 5 0 u _ 6. 3 V _ V _ A
1 0 K _ 1 %_ 0 4
S G N D4
SG ND 4
S G ND 4
S GN D 4
S G ND 4
S GN D 4
S YS5 V
INT V C C2
P R1 8 4
0_06
P R1 8 2
*0 _ 06
2 . 9 4 K _ 1% _ 0 4
0 . 0 1 u _ 50 V _ X 7 R _ 0 4
P C 57
1
2
3
PQ 7
I R F 87 0 7 P B F
4 . 7 u_ 2 5 V _ X 5 R _ 0 8
5
6
7
8
4 . 7 u _ 25 V _ X 5 R _ 0 8
Z3619
1
Z3620
Z3621
4
Z3622
VDD3
S YS3 V
5A
2
17
PAD
P Q4 2
I RF 8 7 0 7 P B F
4
P C 18 1
PL 9
4. 7 U H _ 6 . 8 *7 . 3 *3 . 5
PR 2 0 1
C
2
3
PD 1 4
V D D3
PJ 1 8
1
2
* OP E N -5 m m
+
* 2 . 2_ 0 6
S K 3 4S A
A
N.C
G ND
D L
RT N
FB
P C1 7 7
PC 5 6
0. 1u _ 5 0 V _ Y 5 V _ 0 6
5
6
7
8
15
16
D H
N.C
VC C
5
9
P C5 8
0 . 1 u _ 50 V _ Y 5 V _ 06
1
SY S5 V
LX
B ST
V OU T
6
Z3617
PU 9
S C 4 12 A
P GD
N .C
10
8
*4 7 p _5 0 V _ N P O_ 0 4
0 . 0 1 u _ 50 V _ X 7 R _ 0 4
Rb
P R 1 88
Z3616
N.C
13
IL IM
EN
11
P C1 8 3
4
PC 1 7 9
12
*9 . 1 K _ 0 4
V IN
1
2
3
P R1 7 9
0_04
Z3618
14
1 0 K _ 1% _ 0 4
Z 3 6 25
P R 1 81
1 0 K _ 1 % _0 4
P R 18 9
*1 5 m i _l s h o rt _ 06
C
P R1 7 1
Z3615
P C1 7 2
P D1 7
R B 0 5 4 0S 2
OCP
Ra
7
1 0 K_ 0 4
P C 18 8
P R1 7 6
10 0 p _ 5 0V _N P O _0 4
A
PR 1 7 0
P C4 6
*1 5 0 u_ 6 . 3 V _ V _ A
+
PC 4 5
P C1 7 5
1 5 0 u _6 . 3 V _ V _ A
0. 1 u _ 5 0 V _ Y 5 V _ 0 6
PC 1 9 6
1 u_ 2 5 V _ 0 8
* 2 20 0 p _ 50 V _ X 7 R _ 0 4
2009/11/17
V I N1
SY S1 5 V
V D D3
V D D5
SY S5 V
VI N
31
31
14 , 2 3 , 2 5 , 2 8, 29 , 3 1 , 3 7
31
31 , 3 7
12 , 3 0 , 3 1 , 3 3, 34 , 3 5 , 3 6 , 37
Power 3.3V/5V B - 33
B.Schematic Diagrams
S GN D 4
1
7 5K _0 4
1
2
3
20 K _ 1 % _ 0 4
5
6
7
8
P R1 7 7
1 0 K_ 0 4
1
2
3
PR 1 7 2
0. 1u _ 5 0 V _ Y 5 V _ 06
P R 18 7
Schematic Diagrams
Power 1.5V/0.75V/1.8VS
5V
3 .3 V
V IN
P R 81
P R8 3
1 . 5 M_ 0 4
1 0_ 0 6
P R7 5
1 00 K _ 0 4
A
V D DQ
P D2
( 1 .5 V= 1 .5 17 V )
R B 0 5 40 S 2
1 0 _0 6
Z3 80 1
3
7
16
VDD P 1
P Q 36
20
4
PD 1 3
*M D S 2 6 5 5
5V
V T TE N
25
18
16
17
P C 1 57
0. 1 u _ 5 0V _ Y 5 V _ 0 6
P C 15 6
0 . 1u _ 5 0V _Y 5 V _ 0 6
PJ 5
8A
1
S K 34 S A
+
+
P C 1 46
P C 15 3
* 22 0 u _2 . 5 V _ B _ A
0. 1 u _ 50 V _ Y 5V _ 0 6
P R 1 65
*1 5 m il _ s ho rt _ 0 6
V SSA
S C4 8 6
1 .5 VE N
4
S
P Q9 B
MT D N 7 00 2 Z H S 6R
G
S
1
D
5
G
6
D
D
Z 3 81 9
1 0 0 K _0 4
PJ 7
1 6 ,2 8
S
2
1
3 0 ,3 1
D D_ O N#
5V
4 , 16 , 3 4 1 . 1V S _ V TT _ P W R GD
PR1 6 6
PR 6 9
1 0 0K _ 0 4
PR 7 0
*1 0 0 K _ 04
D
D
SUS B
G
SU SB
4
P Q5 A
2N 7 00 2 K D W
P C 43
2
0 . 1 u_ 5 0 V _ Y 5 V _ 06
S
P Q5 B
5 2 N 7 0 02 K D W
G
S USB
V TT E N
6
10 0 _ 04
3
31
DDR3 VDDQ --> 1.5V ( V POWER)
330uF*3 , 10uF*6
VTT-->0.75V ( VS POWER)
10uF*3, 1uF*4
4 0 m il
P Q9 A
MT D N 7 0 02 Z H S 6 R
V T T _M E M
0 . 1 u _5 0 V _ Y 5 V _ 0 6
2
G
S US C#
PC 4 9
PQ 8
* MT N 70 0 2 Z H S 3
1
S
ON
? ? ? ? PIN6?
5V
1.8VS
3 .3 V
P C1 6 0
D
1
G
P C1 5 2
P C 15 9
8 2p _ 5 0V _ N P O_ 0 4
MT N 70 0 2 Z H S 3
P C 41
* 0. 1 u _ 50 V _ Y 5V _ 0 6
B - 34 Power 1.5V/0.75V/1.8VS
AX6610
* 1u _ 2 5V _0 8
1 0 u_ 6 . 3 V _ X 5R _ 0 6
6 2 K _1 % _ 0 4
0 . 1 u _ 50 V _ Y 5 V _ 06
PR 7 1
S
S US B
P R1 6 3
1 . 27 K _ 1 % _0 4
2
P C1 5 1
P Q4
31
VFB
PC 3 3
1 . 8V S
PJ 6
1
3
E N
G ND
VS 1 .8
4
0 . 1 u _1 0 V _ X 7 R _ 0 4
8
V OU T
3A
P C 1 49
EN1 .8 VS
10 K _ 0 4
V OU T
6
10 u _ 6 . 3V _ X 5 R _0 6
P R6 8
1 . 8V S _P W R G D
1 u_ 2 5 V _ 08
V C N TL
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
5V
1 0K _0 4
V IN
V IN
P OK
P C1 4 7
PR1 6 7
3 .3 V
PU7
5
9
7
P C 14 8
2A
GS7113
6-02-07113-320
AX6610
6-02-06610-320
PR1 6 4
1K _1 % _ 04
1 .5 V
P C 1 55
3
P R8 0
2
OP E N _ 8 A
P Q 37
1u _ 2 5 V _0 8
P GN D 2
P GN D 1
P GN D 1
P GN D 2
EN/P S V
2 . 5 U H _ 10 * 10 * 5
C
19 Z3818
PC4 0
VDD P 2
VDD P 2
1
PL 6
MD S 2 6 55
4
VT T
VT T
11
V D DQ
OCP
7. 1 5 K _ 1 %_ 0 4
22 Z3817
VSSA
12
13
1 u _ 2 5V _ 0 8
1.5V
1
2
3
4
P C3 9
1 5 u_ 2 5 V _ 6. 3 * 4. 5 _ E L N A
MD S 2 65 9
P C1 5 0
5 60 u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9
PC 3 6
1 0u _ 6 . 3V _X 5 R _0 6
P C 35
4
PQ 3 8
5
6
7
8
P C5 0
LX
D L
Z3 80 9 1 4
15
10 u _ 6. 3 V _ X 5 R _ 0 6
P C3 4
IL IM
1 u _2 5 V _ 0 8
V DD Q
4 7K _ 0 4
Z 3 8 15
P R 74
21 Z3816
VCC A
PC 3 7
* 1 0u _ 6 . 3 V _X 5R _ 06
PR 6 6
* 2 0K _ 1 % _ 04
P R7 9
V T TS
5
Z3 80 7
P C 52
1.5A
1
+P C 1 61
PC 4 7
0 . 1 u _5 0 V _ Y 5 V _ 0 6
P R7 6
*1 5 m i _l s h ort _ 0 6
23 Z3814
A
PJ 1 6
O P E N _2 A
5V
PR 6 7
* 0 . 06 8 u _5 0 V _ 0 6 *1 5 m i l_ s h ort _ 0 6
PC 1 5 8
+
* 2 20 u _ 2. 5 V _ B _ A
BST
C O MP
DH
VSSA
2
FB
RE F
Z3 80 6 1 0
1 0 0 0 p_ 5 0 V _X 7R _ 04
P C3 8
1 u_ 2 5 V _ 08
V TT _ ME M
9
*0 . 1 u _1 0 V _ X5 R _0 4
P C 42
VTT_MEM
6
8
Z3 80 5
PC 4 4
Z3808
Sheet 33 of 40
Power 1.5V/0.75V/
1.8VS
Z3 80 3
P R7 8
*1 5 m i _l s h ort _ 0 6
Z 38 1 3
24 Z3812
1
2
3
1 0 _0 6
Rb
T ON
1 u_ 2 5 V _ 08
P R 73
P R7 7
10 0 K _ 1 %_ 0 4
2
5
6
7
8
1 u _ 25 V _ 0 8
1 0_ 0 6
D D R 1. 5 V _ P W R GD
VIN
Z3 80 2
P R 72
D D R 1 . 5 V _ P W R GD
P GD
P C 51
5
6
7
8
P C6 0
1
2
3
1 0 0 p_ 5 0 V _ N P O _0 4
P R8 4
1K _0 4
*1 0 u_ 6 . 3 V _ X 5 R _ 0 6
B.Schematic Diagrams
V D D QS
PC 5 9
C
P U2
P R8 2
Ra
2
O P E N _3 A
7 ,2 0
1 2, 3 0 , 3 1 , 32 , 3 4 , 3 5, 3 6 , 3 7
2 1 , 24 , 2 7 , 3 0, 3 1 , 3 4
3 , 4 , 1 2 , 14 , 1 5 , 1 6, 1 8 , 1 9 , 20 , 2 1 , 2 3, 2 4 , 2 5 , 29 , 3 0 , 3 1, 3 4 , 3 5
4 , 9 , 1 0, 1 1 , 2 1 , 23 , 2 7 , 2 9, 3 1 , 3 6
1 0 , 11
1. 8 V S
VIN
5V
3. 3 V
1. 5 V
V T T_ M E M
0 . 0 1 u_ 5 0 V _ X7 R _0 4
Schematic Diagrams
Power 1.1VS_VTT
5V
V IN
A
OCP
P D8
R B 0 5 4 0S 2
1.1VS_VTT=0.75 X (1+PR65 / PR67)
C
P R8 6
6 . 4 9 K _ 1 % _ 04
5
6
7
8
5
6
7
8
P C1 6 3
+
P Q4 0
MD S 2 6 59
P Q3 9
*I R F 7 4 1 3Z P B F
1 5 u _ 2 5V _6 . 3 * 4 . 5 _E LN A
1.1VS_VTT
4
VTT_ SEN SE
2
3
1
2
3
1
4
6
* OP E N -1 2 m m
2
3
PQ 4 3
M D S 26 5 5
P Q4 4
M D S 2 65 5
P D1 5
4
5V
P R9 3
P R 88
P C6 6
1 0K _ 1% _ 0 4
*2 0 p _5 0 V _ N P O_ 0 4
PC 6 9
+ P C 16 2
S K3 4 SA
17
2 2 0u _ 4 V _ V _ B
0 . 1 u _ 5 0V _Y 5 V _ 0 6
2 20 u _ 4 V _ V _ B
Sheet 34 of 40
Power 1.1VS_VTT
PC 6 1
1 u _ 25 V _ 0 8
0_04
+ P C 15 4
A
R TN
4
DL
PA D
5
D 0
D1
7
8
GN D
4
C
VC C
5
6
7
8
BST
V O UT
2
3
1
16
15
PG D
PR 9 2
2
LX
9
FB
1. 1V S _ V T T
P J1 7
1
2
3
1
10
FB
V T T 1 .1 V S
PL 7
0 . 5 6U H _1 0 * 10 * 4 . 1
*9 0 . 9 K _ 1 % _0 4
PC 6 7
P R 89
0 . 1 u _1 0 V _ X 7 R _ 0 4
2 4K _ 1% _ 0 4
(1.1VS_VTT=1.067V)
P J1 0
2
PR 9 4
5V
1
1 00 K _ 0 4
1 0 K_ 0 4
PJ 9
1
2
1. 1V S _ V T T _E N _ R
4 0 mi l
PR 8 7
*1 0 0 K _ 0 4
3
D
5
G
S
6
G
1
P R9 1
1 u _ 1 0 V _ X7 R _ 0 4
P J8
4 0 m il
2
S
PQ 1 1 B
* 2 N 7 0 0 2K D W
4
2
1 6 1 .1 V S _ V T T _ E N
PQ 1 1 A
* 2N 7 0 02 K D W
1
D
P C6 8
* 0 . 1 u _1 0 V _ X 5 R _ 0 4
2, 4 , 6 , 7 , 1 4 , 1 5 , 1 6, 19 , 2 0 , 2 1 , 3 5 , 3 6 1. 1V S _ V T T
3 , 4 , 12 , 1 4 , 1 5 , 1 6 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 3 0 , 3 1, 33 , 3 5 3 . 3 V
2 1 , 2 4 , 2 7 , 3 0, 31 , 3 3 5 V
1 2 , 30 , 3 1 , 3 2 , 3 3 , 3 5, 36 , 3 7 V I N
Power 1.1VS_VTT B - 35
B.Schematic Diagrams
11
4 , 16 , 3 3 1 . 1 V S _ V TT _ P W R G D
25A(15A)
0 . 1 u _ 50 V _ Y 5 V _ 0 6
1
5
6
7
8
EN
P U4
S C4 1 2 A
DH
12
G 1
13
I LI M
1 0 K_ 0 4
G0
1 .1 V S _ V T T _ E N _ R
PR 9 0
6
ON
3 .3 V
14
PC 6 2
Schematic Diagrams
Power VGFX_CORE
1. 1 V S _V T T
P J2
2
7
7
7
7
D F G T_ V I D _ 0
D F G T_ V I D _ 1
D F G T_ V I D _ 2
D F G T_ V I D _ 3
7
7
7
D F G T_ V I D _ 4
D F G T_ V I D _ 5
D F G T_ V I D _ 6
40 m li
1
1 K _0 4
1K _ 04
1K _ 0 4
*1 K _0 4
* 1K _ 04
1 K _ 04
*1 K _0 4
? ? JUMP? ?
1 0K _ 04
DF G
DF G
DF G
DF G
DF G
DF G
DF G
PJ4 FOR CV? ? ?
P R5 9
1 K _ 04
2
D F G T_ V R _ E N
3 .3VS
PR5 0
T_ V I D _ 0
T_ V I D _ 1
T_ V I D _ 2
T_ V I D _ 3
T_ V I D _ 4
T_ V I D _ 5
T_ V I D _ 6
5 VS
7 D F GT _ V R _ EN
P R 42
V IN
1 0K _ 1% _ 04
P R 49
PR 48
P R4 7
P R4 6
P R4 5
P R 44
P R4 3
4 . 7u _2 5 V _X 5 R _ 08
33
4
GN D _3 2 11
G N D _ 32 1 1
P R7
P R3
GN D _3 21 1
GP U V C C S E N S E 7
P R 36
1 0 0_ 1 %_ 04
2
1
+
P R 1 58
1 10 K _1 % _0 6
P C8
P C 13 4
P R 1 57
1 50 0 p_ 50 V _ 06
2 2 0p _ 50 V _N P O_0 4
1 80 K _1 % _0 4
4 22 K _ 1% _0 6
1 0 0_ 1 %_ 04
Place RTH1 close to
inductor on the same layer
P C 1 28
GN D _ 32 11
GN D _ 32 11
P R 39
P R2
RT 2
10 0 K_ N T C _ 06 _ B
2
1
+
S K 34 S A
A
MD S 2 6 55
P D1 0
1
2
3
4
P Q2 4
MD S 26 55
* 0. 1 u_ 1 0V _ X 5R _0 4
P Q2 5
C
5
6
7
8
*2 . 2_ 0 6
2. 2 u_ 1 6V _ X5 R _ 0 6
*0 . 01 u_ 5 0V _ X 7R _0 4
PC 13
P C 1 38
P R 1 54
3 2 11 _D R V L
17
2 20 u _4 V _V _ B
19
18
P C1 3 7
PL 3
1. 0 U H _ 10 *1 0 *4 . 5
1
2
5 VS
*2 20 u _4 V _V _ B
3 2 11 _S W
P C1 2 9
3 2 11 _D R V H
21
20
*2 20 0 p_ 5 0V _ X 7R _0 4
P R8
V GF X_ C O R E
P J 15
OP E N _8 A
23
22
3 2 11 _C S C OM P
GPU
*0 _ 04
3 21 1_ C S C O MP
1
P R3 1
3 32 K _1 % _0 6
CPU
2 00 K _ 1% _0 4
0
3 21 1_ C S C O MP
App.
8 0. 6 K _ 1% _0 4
GPU
(0. 7V~1 .77V)
P C 96
P C8 5
1
2
3
PC 4
5
6
7
8
15A(7A)
GP U
7. 5 K _1 % _0 4
G PU
VIN
P R6
1 K _1 % _0 4
P R 1 56
16 0 K _1 %_ 0 4
distr ibute evenly between Nside and Sside,
prefer ably on secondar y side.
GP U V SS S E N SE 7
PC7
P C2 4
10 0 0p _5 0 V _X 7R _0 4
1 00 0 p_ 50 V _ X7 R _ 04
GN D _ 3 21G1 N D _ 32 1 1
2 , 4, 6 , 7 ,1 4 , 15 , 1 6, 1 9, 2 0 , 21 , 34 , 3 6 1 . 1V S _ V TT
3, 4 , 12 , 1 4, 1 5 ,1 6 , 18 , 19 , 2 0, 2 1 ,2 3 , 24 , 2 5, 2 9, 3 0 , 31 , 33 , 3 4 3 . 3V
4 , 9, 1 0 ,1 1 , 21 , 2 3, 2 7, 2 9 , 31 , 33 , 3 6 1 . 5V
7
V GF X _C O R E
1 2 , 30 , 3 1, 3 2, 3 3 , 34 , 36 , 3 7 V I N
2, 1 3 ,1 7 , 20 , 2 1, 2 6, 2 7 , 30 , 31 , 3 6 5 V S
2 , 10 , 11 , 1 2, 1 3, 1 4 , 15 , 16 , 1 7, 1 8 ,1 9 , 20 , 21 , 2 3, 2 4 ,2 5 , 26 , 2 7, 2 8, 2 9 , 30 , 31 , 3 6 3 . 3V S
B - 36 Power VGFX_CORE
VGFX_CO RE
PC1 7
0. 2 2 u_ 5 0V _ 06
1
2
3
C S C OM P
I R EF
9
A G ND
P R 35
0 _ 06
24
5
6
7
8
26
27
28
29
25
V ID 6
V ID5
V ID4
V ID3
30
IL IM
P R2 2
5VS
GN D _ 32 11
V ID2
A G ND
47 0 p_ 50 V _ X7 R _ 04
PR 32
0_ 04
DR V L
P G ND
G PU
CS F B
P R 34
1K _ 1% _ 04
AD P 32 1 1
C OMP
16
8
FB
15
7
CS RE F
6
47 p_ 5 0V _ N P O_ 04
L LI N E
PC 18
2 0K _ 1% _0 4
P V CC
14
P R3 3
SW
P U1
R A MP
P C1 9
D RV H
C LK E N #
13
5
22 0 p_ 5 0V _ N P O_ 04
P C 21
BST
I M ON
F B RT N
P Q1 9
MD S2 6 59
4
G N D _ 32 1 1
P W RG D
12
4
31
32
EN
3
R T
32 11 _ C LK E N #
RP M
2
4 .7 K _ 1% _0 4
11
* 10 K _1 % _0 4
0. 1 u _5 0V _ Y 5 V _0 6
P R 21
0_ 04
V CC
10
1
PR 41
V ID1
P R3 8
P C2 5
V ID0
3.3 VS
P C 20
*4 . 7u _2 5 V _X 5 R _ 08
1 u_ 6 . 3V _ X5 R _ 04
* 0. 0 1u _ 50 V _X 7 R _ 04
P C2 3
GF X _I M ON
P C5
PR 40
*1 0K _ 1 %_ 04 1 6 V GF X _ VO R E _ P G
7
P C8 8
4. 7 u _2 5 V_ X 5 R _ 08
1 0_ 06
0. 1 u_ 5 0V _ Y 5V _ 0 6
P R3 7
1. 1VS_VT T
P C 1 30
47 0 _0 4
Sheet 35 of 40
Power VGFX_Core
10 0 0p _ 50 V _X 7 R _ 04
B.Schematic Diagrams
3. 3 V S
40 mi l
1
* 1K _ 04
*1K _ 0 4
*1 K _0 4
1 K _0 4
1 K _0 4
* 1K _ 0 4
1K _ 04
PJ 3
P R 57
PR 56
P R5 5
P R5 4
P R5 3
P R 52
P R5 1
PR 58
3. 3 V
Schematic Diagrams
V-Core
*3 3 0u _C A R 3 15 L
0 . 1 u_ 5 0V _ Y 5V _ 0 6
P C 10 2
P C7 7
0. 1 u_ 5 0V _ Y 5 V _0 6
0 . 1u _ 50 V _ Y 5V _ 0 6
0. 1 u _5 0 V _Y 5 V _0 6
P C8 4
P C 1 43
G
G
HD R2
+
P R 16 1
33 0 u_ 2 . 5V _ V _A
*3 3 0u _ 2. 5 V _ V _A
* 33 0 u_ 2. 5 V _ V _A
+
+
P C 14 5
PC1 4 1
*3 30 u _2 . 5 V _V _ A
5 6 0u _ 2. 5 V _ 6. 6 *6 . 6 *5. 9
3 3 0u _ 2. 5 V _V _ A
P C 13 9
P Q3 2
*I R F H 79 23
+
Sheet 36 of 40
V-Core
P R6 4
P Q27
I R F H 7 92 3
*4 . 7u _2 5 V _X 5 R _ 0 8
P C 93
CS _ P H2
+
P C 14 2
A
CS RE F
P R 1 20
10 0 _0 6
+
P C 1 40
C S _P H 1
C
D
S
1 00 _ 1% _0 4
+
5 VS
P C 1 44
0 . 1 u_ 5 0V _ Y 5V _ 0 6
P C 26
0. 1 u _5 0 V _Y 5 V _ 06
0 . 1u _ 50 V _Y 5 V _ 06
P C7 6
0 . 1u _ 50 V _ Y 5V _ 0 6
P C2 2
PC 3
P C3 1
* 4. 7 u _2 5 V _X 5 R _ 0 8
0. 1 u _5 0 V _Y 5 V _0 6
0 . 1 u_ 5 0V _ Y 5V _ 0 6
1 5u _2 5 V _6 . 3 *4 . 5_ E L N A
0 . 1u _ 50 V _ Y 5V _ 06
PC1 3 2
P C 10 6
D
S
S
D
S
1 0 _0 6
VIN
1 0 _0 6
C S _P H 2
S GN D 2
VRT T
T TS N S
A GN D
A GN D
P R 16 2
2 2 0p _ 50 V _ N P O_ 0 4
C S _P H 1
V CO RE
24A
P C 13 6
PC1 1 1
10
TT S N S 1 1
12
49
BST 1
P D1 2
S K 34 S A
* 4. 7 u _2 5 V _X 5 R _ 0 8
P R1 2 1
3 9. 2 K _ 1% _0 4
P R 1 25
10 0 _0 6
P R 16 0
5 . 1 _0 6
P Q3 4
I R F H 7 9 32
0 . 1 u_ 5 0V _ Y 5V _ 0 6
P R 1 22
1. 6 K _ 1% _ 04
+
VCORE
P C 1 33
PC9 5
15 0 p_ 5 0V _ 0 6
RS P
RS N
P R 12 4
5 . 49 K _ 1% _ 04
PC9 2
12 p _5 0 V _N P O_ 04
36
35
34
33
32
31
30
29
28
27
26
25
P Q2 9
I R FH 79 3 2
G
G
D
P C9 0
15 0 p_ 5 0V _ 0 6
BST 1
DR V H1
SW 1
SW FB1
P VCC
DRVL 1
P GN D
DRVL 2
SW FB2
SW 2
DR V H2
BST 2
P R 1 27
2_ 0 6
S
P C 97
0. 1 u _5 0 V _Y 5V _ 06
EN
P W RG D
I MO N
CL K E N#
F B RT N
FB
C O MP
T RDET #
VA RF R
P C 98
5 VS
ADP3212
P C 1 00
P C9 4
10 0 0p _ 50 V _ X7 R _ 04
S GN D 2
P U5
D
I MON
CL K E N#
V R _ ON 1
2
3
4
5
6
7
T R D E T#
8
5 VS
9
+
G
S
6
24
23
22
21
20
19
18
17
16 P R 1 08
1 5 P R1 0 5
1 4 P R 10 9
13 P R 1 12
3 K _1 % _0 4
+
PL 5
0. 3 6U H _ 12 . 9 *1 4* 3. 8
SW FB3
P W M3
OD 3#
IL IM
C S C O MP
CS S UM
C SR E F
L L INE
RA M P
RT
R PM
IREF
P R1 2 6
3 K _ 1% _ 04
G
+
5 VS
PL 4
0. 3 6 U H _ 1 2. 9 *1 4 *3 . 8
24A
4 H _P R OC H OT #
P R 15 9
5 . 1 _0 6
P Q2 8
I R F H 7 9 32
G
P Q3 3
I R F H 7 9 32
P D1 1
S
1 . 5V
P C 13 5
A
1 . 1V S _ V TT
P C 12
S K 34 S A
S
S
G
C
0 . 22 u _5 0 V _0 6
B ST 2
10 _0 6
D
P R 1 17
2_ 0 6
S GN D 2
G
D
D
P C8 7
P R 20
P Q1 8
MT N 7 00 2Z H S 3
1 . 5V S
2 2 0p _ 50 V _ N P O_ 0 4
0 _0 4
P R1 8
0 _0 4
P R 65
0 _ 04
R SP
V CC_ S E NS E 6
P C 30
P R 62
0 _ 04
* 10 0 0p _ 50 V _ X7 R _ 04
V S S _S E N S E 6
P R 1 46
H_ V ID0
H_ V ID1
H_ V ID2
H_ V ID3
H_ V ID4
H_ V ID5
H_ V ID6
PR6 1
PJ 1
10 0_ 1 %_ 0 4
1
4 0m il
*1 K _0 4
*1 K _0 4
* 1K _ 04
1 K _ 04
1K _ 0 4
*1 K _ 04
1 K _ 04
P R 30
* R _ 04
6
6
6
6
6
6
6
2 PR1 4 5
PS I#
R SN
PR2 3
PR2 4
PR2 5
P R 26
PR2 7
PR2 8
P R 29
6
P R1 9
64 9 _1 %_ 0 4
S GN D 2
6 P M_ D P R S L P V R
*6 4 9_ 1 %_ 04
1K _ 0 4
1 K _0 4
1 K _0 4
* 1K _ 0 4
*1 K _0 4
1 K _0 4
* 1K _ 0 4
1u _2 5 V _0 8
5V S
P R1 1 5
0 _0 4
5 VS
P R 1 31
3. 3 V S
V R _ ON
10 K _0 4
5. 1 K _ 1% _ 04
7. 3 2K _ 1 %_ 0 4
P R 14 7
10 0K _ 0 4
P Q 22 A
PC 86
10 0K _ N T C _ 0 6_ B
0. 0 1u _ 50 V _ X7 R _ 0 4
*R _ 0 4
6
D
M TD N 70 0 2Z H S 6R
28
V C OR E _ ON
D
5
P J1 4
2
G
1
4
2
R T1
S G ND2
3
G
P R 1 18
2
P Q2 2B
MT D N 70 0 2Z H S 6 R
T R D E T#
40 mi l
1
1
T TS N S
P R1 1
P R1 2
P R1 3
P R 14
P R1 5
P R1 6
P R 17
P R 1 19
P R 11 6
S
P C 11 4
S
PR1 3 0
*1 0 K _0 4
4, 9 , 10 , 1 1, 2 1 , 23 , 2 7, 2 9 , 31 , 33
2 0 , 23 , 31
2 , 4 , 6, 7 , 14 , 1 5, 1 6 , 19 , 2 0, 2 1 , 34 , 35
6
12 , 3 0, 3 1 , 32 , 3 3, 3 4 , 35 , 37
2 , 13 , 17 , 2 0, 2 1 , 26 , 2 7, 3 0 , 31 , 35
2 , 10 , 1 1, 1 2 , 13 , 1 4, 1 5 , 16 , 17 , 1 8, 1 9 , 20 , 2 1, 2 3 , 24 , 25 , 2 6, 2 7 , 28 , 2 9, 3 0 , 31 , 35
1 . 5V
1 . 5V S
1 . 1V S _ V T T
V CO RE
V IN
5 VS
3 . 3V S
* 0. 1 u _1 0 V _X 5R _0 4
V-Core B - 37
B.Schematic Diagrams
P R 12 3
4 , 1 6 D E LA Y _ P W R G D
2
P R 10 7
1 . 6 9K _ 1 %_ 04
VC C
PH1
PH0
D P RS L P
PS I#
VID6
VID5
VID 4
VID3
VID2
VID 1
VID0
3. 3 V S
PQ 35
*I R F H 7 9 23
FOR EMI
HDR 1
S GN D 2
37
38
39
40
41
42
43
44
45
46
47
48
3. 3 V S
S GN D 2
C S C OM P
CS S UM
CS RE F
C S C OM P
68 0 K _1 % _0 4
1 62 K _ 1% _ 06
4 7 . 5K _ 1 %_ 0 4
80 . 6 K _1 % _0 4
2
P C 81
4 7 0p _ 50 V _ X7 R _ 04
0 . 2 2u _5 0 V _0 6
P R 1 06
73 . 2 K _1 % _0 4
4 . 7 u_ 2 5V _ X 5R _0 8
1
RT 3
1 00 K _N TC _0 6 _B
P Q3 0
I R F H 7 9 23
1 00 0 p_ 5 0V _ X 7R _0 4
P C7 8
1 K _0 4
PC7 9
D
PR1 0 4
P C8 3
15 0 0p _ 50 V _ 06
PC8 9
16 2 K_ 1 %_ 0 6
P C 32
VIN
P R 1 10
RT1 close to PL6
P C 1 07
* 15 u_ 2 5V _ 6 . 3* 4. 5 _ E LN A
P C8 2
1u _ 25 V _ 08
2 0 0K _ 1% _ 04
2 0 0K _ 1% _ 04
1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A
P R 1 13
P R 1 14
P C 1 12
P R 1 11
*4 7K _ 0 4
CS _ P H1
CS _ P H2
P C9 1
S G ND2
*1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A
V IN
P C 80
* 1n _ 50 V _ 04
Schematic Diagrams
DC-In, Charger
CHARGER
# Char ge Cur r en t 3.0A
VA
P Q1 7
P 20 0 3 E V G
PR 4
0 . 1 u _5 0 V _ Y 5 V _ 0 6
0 . 1 u _ 50 V _ Y 5 V _ 0 6
TOTAL
POWER
ADJ
P R 15 5
10 K _ 1 % _0 4
P R1 5 3
S G ND 6
V DD 3
32
31
30
29
28
27
26
25
V CC
-I N C 1
+I N C 1
A CIN
A CO K
-I N E 3
A DJ 1
C O MP 1
MB 3 9 A 1 3 2
10 K _ 1 % _0 4
P C9 9
1 0 0 p_ 5 0 V _N P O_ 0 4
CT L 2
C B
OU T -1
LX
VB
O U T -2
P GN D
C E LL S
0 . 1u _ 5 0V _ Y 5V _0 6
1
2
3
4
5
6
7
8
TRERMAL PAD
V IN
C TL 1
G ND
VR EF
RT
C S
A DJ 3
BATT
S G ND
24
23
22
21
20
19
18
17
33
P C1 0 3
V OL T _ S E L
P R1 3 4
1 K _ 1 % _0 4
P R1 4 0
S M C_ B A T
S GN D 6
4 9. 9 K _ 1 % _0 4
S M D_ B A T
CHARGE
CURRENT
ADJ
P R1 4 2
1 K _1 % _ 0 4
A
P Q3 1
*0 . 1 u _5 0 V _ Y 5 V _ 06
P C1 1
P R 1 32
P R1 4 4
C
AC
A
D9
B A V 9 9 R E C TI F I E R
C
AC
A
D8
B A V 9 9 R E C TI F I E R
C
AC
A
D7
B A V 9 9 R E C TI F I E R
S G ND 6
2 2 K _ 1% _ 0 4
P C1 0 8
1 0 0 0p _ 5 0V _ X 7 R _ 0 4 P R 1 4 3
S G ND 6
D T C 11 4 E U A
P C1 1 5
P C1 0 4
* 2 2p _ 5 0V _ N P O_ 0 4
P C1 0 1
1 0 0 0p _ 5 0V _ X 7 R _ 0 4 P R 1 3 7
1 0 K _ 04
S G ND 6 S G ND 6 S G ND 6
2 2K _ 1 % _ 04
B A T _ V O LT
1 0K _ 1 % _ 04
S GN D 6
C
AC
A
D6
B A V 9 9 R E C TI F I E R
E
PD 9
U DZ 1 6 B
B
P R 15 2
20 K _ 1 % _0 4
28
C
A C _I N #
C
PC 6
B A T _ DE T
0. 01 u _ 50 V _ X 7R _ 04
0 . 1 u _5 0 V _ Y 5V _0 6
V D D3
R1 6
P C1 3 1
1 0K _0 4
P C 12 1
C T L1
P R1 4 9
VA
4. 7 u _ 25 V _ X 5 R _ 0 8
P C1 2 2
4 . 7 u_ 2 5 V _X 5 R _0 8
4 . 7u _ 2 5V _X 5 R _0 8
P C1 2 3
4 . 7u _ 2 5V _X 5 R _0 8
P C1 2 6
4 . 7u _ 2 5V _X 5 R _0 8
0 . 1 u _5 0 V _ Y 5 V _ 06
0 . 1 u_ 5 0 V _ Y 5V _0 6
0 . 1u _ 5 0 V _Y 5 V _0 6
P C1 1 6
-I N E 1
O UT C 1
OU T C 2
+ INC 2
-I N C 2
AD J 2
C O MP 2
C OM P 3
P U6
P C 1 17
*0 _ 04
VA
9
10
11
12
13
14
15
16
V IN
P C1 1 8
P C1 2 5
P C1 2 4
0 . 1 u_ 5 0 V _ Y 5 V _ 06
VA
P C 1 19
4 . 7u _ 2 5V _ X 5 R _0 8
5
6
PIN 25t h
FOR 2S CONNECT T O GND
FOR 3S CONNECT N.C.
FOR 4S CONNECT T O VREF PIN
0. 1u _ 5 0V _ Y 5 V _ 0 6
0 . 1u _ 5 0V _ Y 5V _0 6
0_ 0 4
R B 0 5 4 0S 2
P R5
0 . 1 u _5 0 V _ Y 5 V _ 06
P R1 3 6
3 9 . 2 K _1 % _ 04
P C 1 20
P Q 26 B
A P 6 9 0 1G S M
4
P C 11 3
1 u_ 2 5 V _ 08
A
P R 10 0
P C1 1 0
3
0_04
0 . 1 u _ 50 V _ Y 5 V _ 0 6
C
P C 1 09
V_ BAT
P R1 3 9
0 . 0 2 _ 1% _ 3 2
8
P R1 4 8
P D1
V_ BAT
Sheet 37 of 40
DC-In, Charger
# To tal Pow er 60W
PL 2
4. 7 U H _ 6 . 8* 7 . 3* 3 . 5
*0 _ 04
PC 1 4
# Char ge Volt age 12.6V
7
0 . 1 u _ 50 V _ Y 5 V _ 06
0 . 1 u _5 0 V _ Y 5 V _ 06
P C1 5
PC 1 6
4 . 7u _ 2 5V _X 5 R _0 8
0_04
4 . 7u _ 2 5V _ X 5 R _0 8
P C1 0
1 0 K _1 % _ 04
P C9
P R 10 2
P R 15 1
1 0 K_ 0 4
2
1
P R 1 50
0 _ 04
1 3 0K _ 1 % _0 4
P R1
P Q2 6 A
A P 69 0 1 GS M
P R9 9
0. 0 2 _ 1 %_ 3 2
3
2
1
1 0 0K _ 0 4
0 . 1 u _5 0 V _ Y 5 V _ 06
8
7
6
5
P R 10 3
4
P C2
0 . 1u _ 5 0V _Y 5 V _ 0 6
PC 1
0 . 1u _ 5 0V _ Y 5 V _ 0 6
P C7 5
VA
P R1 0 1
2 0 0K _ 1 % _ 04
PL 1
H C B 4 5 3 2K F -80 0 T 60
1
2
G ND 1
G ND 2
V_ BAT
0. 5V/ 1A
T OT A L _ C U R
0. 5V/ 1A
CU R_ S E N S E
PIN17t h CONNECT
T OBAT CONN.
B T D - 05 T I 1 G
10
P R 13 3
1 0 2K _ 1 % _ 04
P R2 0 0
28
28
28
28
V OL T _ S E L
P R1 3 5
1 0 0 K _0 4
1 00 K _ 0 4
G
G
P Q2 0 A
P C 10 5
6 0 . 4 K _ 1% _ 0 4
0 . 1 u_ 5 0 V _Y 5 V _ 06
6
3
D
28
C H G_ E N
D
2
G
1
5
G
S
4
PJ 1 3
OP E N -1 m m
P Q1
S
P Q 20 B
MT D N 7 0 02 Z H S 6 R
P R 12 9
*1 5m i l _s h o rt _ 06
2
D
S Y S 5V
G
MT N 7 0 0 2Z H S 3
B - 38 DC-In, Charger
V C H G_ S E L 2 8
PQ 4 9
M TN 7 00 2 Z H S 3
CT L 1
MT D N 7 00 2 Z H S 6R
1
P R 1 38
P R9
S G ND 6
5
6
7
8
5
1
2
3
4
S MC _ B A T_ R
S MD _ B A T_ R
B A T _D E T _ R
B A T _V OL T _R
4
3
2
1
J BAT TA1
P R 19 9
P R 1 41
7 6 . 8K _1 % _ 04
0 _0 4
S M C_ B A T
S M D_ B A T
B A T _ DE T
B A T_ V O LT
9
2M _ 1% _ 0 4
B A T _ V OL T _ R
P R1 0
20 0 K _ 1 %_ 0 4
S
V _B A T
SY S5 V
P R1 2 8
3 00 K _ 1 % _0 4
D
SYS5 V
PQ 2 1
A O 3 40 9
S
D
S
B.Schematic Diagrams
1
2
3
P C1 2 7
? ? :6-20-B3410-003
JA C K 1
50 9 3 2- 00 3 0 1-0 0 1
PQ 2 3
P 2 0 0 3E V G
5
6
7
8
4
V IN
S YS5 V
V DD3
VA
V IN
3 1 , 32
1 4, 2 3 , 2 5, 2 8 , 2 9 , 31 , 3 2
31
1 2, 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 36
P L C1
E F 0 8 05 V 0 5 4 00
Schematic Diagrams
Click Board
CLICK BOARD
CC2
0.1u_10V_X7R_04
CC1
0.1u_10V_X7R_04
C5VS
C5VS
CGND
CJ_TP2
1
CTP_DATA
2
CTP_CLK
3
4
85201-04051
1
2
3
4
5
6
CGND
CTP_CLK
CTP_DATA
CTPBUTTON_L
CTPBUTTON_R
Sheet 38 of 40
Click Board
85201-06051
CGND
CSW1~2
2
1
4
3
LIFT
KEY
RIGHT
KEY
CSW1
TJG-533-S-T/R
CSW2
TJG-533-S-T/R
2
4
1
3
CGND
1
CH1
9
8
7
6
2
3
4
5
MTH237D91
CGND
CTPBUTTON_R
CGND
CH3
2
3
4
5
2
4
5
6
CTPBUTTON_L
5
6
1
3
1
CH4
9
8
7
6
2
3
4
5
MTH237D91
CGND
CGND
1
CH2
9
8
7
6
2
3
4
5
MTH237D91
CGND
CGND
1
9
8
7
6
MTH237D91
CGND
CGND
CGND
Click Board B - 39
B.Schematic Diagrams
CGND
CJ_TP1
Schematic Diagrams
Audio / USB / RJ11 Board
RJ-11
USB PORT
A _ US B V C C
A _U S B V C C
AU 1
A _ 5V
5
60 mil s
2
A C1 3
3
1 0 u _1 0 V _ Y 5 V _ 08
4
F L G# V O U T 1
V IN1
V O UT 2
V IN2
V O UT 3
E N#
G ND
60 mils
6
7
A C9
A C1 0
8
0. 1 u _ 16 V _ Y 5 V _ 0 4
1
0. 1u _ 16 V _ Y 5 V _ 0 4
R T 9 7 15 B G S
A G ND
A GN D
A GN D A G N D
A GN D
A _U S B V C C 2
60 mil s
A C1 6
AC 1 1
10 0 U _ 6 . 3V _B 2
. 1 U _1 0 V _ X7 R _ 0 4
+
MODEM
A J _ US B 1
RJ-11
1
A G ND
J_MODEM1
2
1
A J_ MO D E M 1
Z 4 0 08
2
Z 4 0 09
1
8 5 2 04 -0 2 00 1
A J _ RJ 1
AL 1
AL 2
MH C 1 60 8 S 1 21 P B P Z 4 0 10 1
MH C 1 60 8 S 1 21 P B P Z 4 0 11 2
T IP
RIN G
A R7
* 10 m i l_ s h ort
A U S B _P N 4 _R
2
A U S B _P P 4_ R
3
V+
DA T A _ L
DA T A _ H
GN D 1
GN D 2
GN D 3
G ND 4
Sheet 39 of 40
Audio / USB / RJ11
Board
4
C 10 1 8 1-1 0 2 05 -L
AU SB_ PP4
PIN G ND1 ~ 2 = AG ND
A U S B _ P N4
1
AL 9
2
A R6
GN D
A U S B _P P 4 _ R
4
3
* W C M 2 01 2 F 2 S -16 1 T 03
A U S B _P N 4 _R
GN D 1
G ND 2
GN D 3
G ND 4
B.Schematic Diagrams
6-0 2-09715- 920
A_ U S B V CC
A L 10
H C B 1 6 08 K F -1 2 1 T2 5
* 10 m i l_ s h ort
A G ND
C 1 07 7 0-1 0 4 A 3
A G ND
AUDIO JACK
A M IC_ SE NS E
A M I C 1 -R
AL 4
A M I C 1 -L
AL 3
F C M1 0 05 K F -1 2 1T 0 3
Z 4 10 5
F C M1 0 05 K F -1 2 1T 0 3
Z 4 10 6
Z 4 10 7
A C5
A C6
1 0 0 P _5 0 V _ 0 4
1 00 P _ 5 0V _ 0 4
5 A J _ MI C 1
4
R
3
2
L
6
1
2 S J- S 35 1 -S 3 0
A _5 V
A J _ A U D I O1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A MI C 1 -R
A MI C 1 -L
A
A
A
A
A
A
A
H E A D P H ON E -R
H E A D P H ON E -L
MI C _ S E N S E
S P K _ HP #
HP _ S ENS E
US B _ PN4
US B _ PP 4
A S P K OU TR +
A S P K OU TR -
MIC IN
2
ASPK_ H P#
A H E A D P H ON E -R
A R3
A H E A D P H ON E -L
A R2
Z 4 1 12 A L 6
6 8_ 1 % _0 4
Z 4 1 13 A L 5
6 8_ 1 % _0 4
F C M 10 0 5K F -12 1 T 03
5 A J _ HP 1
4
R
3
Z4108
F C M 10 0 5K F -12 1 T 03
Z4109
AR 4
AR 1
A C7
A C8
* 1K _0 4
* 1K _ 0 4
1 0 0 P _5 0 V _ 0 4
1 00 P _ 5 0V _ 0 4
2
L
6
1
2 S J- S 35 1 -S 3 0
HEADP HONE
A _ A U DG A G ND
BLACK
A _ A U DG
A S P K OU T R +
AL 8 1
2
AL 7
F C M1 0 0 5K F -1 2 1 T0 3
A S P K O UT R1
2
F C M 10 0 5 K F -12 1 T 03
A C1 2
10 0 0 p_ 5 0V _X 7 R _ 0 4
A C1 5
AH3
2
3
4
5
2
3
4
5
MT H 27 6 D 1 1 1
A G ND
1 8 0p _ 50 V _ N P O_ 04
AH1
9
8
7
6
1
A G ND
9
8
7
6
1
0. 1 u _1 6 V _ Y 5 V _ 0 4
A C1
0. 1 u _1 6 V _ Y 5 V _ 0 4
A C4
0. 1 u _1 6 V _ Y 5 V _ 0 4
A C2
0. 1 u _1 6 V _ Y 5 V _ 0 4
A _ A U DG
A GN D
A G ND
B - 40 Audio / USB / RJ11 Board
A C3
MT H 27 6 D 1 1 1
A G ND
5
A _ A U DG
A H P _S E N S E
8 7 2 13 -1 4 L
AH 2
C 52 D 52
3 4
BLACK
A _ A UD G
AR 5
*1 0 m li _ sh o rt
A J _ S P K R1
A S P KO UT R+ _ R
A S P K O U T R -_ R
A C1 4
1
2
J_SPK1
2 1
8 5 2 04 -0 2 00 1
P C B F oo t p ri nt = 8 5 2 04 -0 2 R
1 8 0p _ 5 0V _ N P O_ 0 4
1
6
Schematic Diagrams
Power Switch & LID Board
POWER SW & LED & HOT KEY
S _3 . 3 V
LID SWITCH IC
C
SD 2
S _ 3 . 3V S
SU 1
1
S _3 . 3 V
22 0 _ 04
20 mi l
1
2
3
4
5
6
7
8
S M GN D
SAP_ O N
S M GN D
S _ V IN
VC C
2
OU T
S LI D _ S W #
S C1
M H -2 4 8
1 0 0 p_ 5 0 V _N P O_ 0 4
SC 6
S M GN D
S M GN D
*0 . 1 u _1 0 V _ X5 R _0 4
SD 1
L TS T -C 15 0 T B K T
S MG N D
S A P _O N
8 8 2 96 -0 8 00
* 50 5 00 -0 1 04 1 -0 01 L
Z4301
0 . 1 u_ 1 0 V _ X7 R _ 0 4
S M _ B TN #
S W E B _W W W #
S W E B _E MA I L #
S L I D _S W #
A
S M _B T N #
SW EB_ W W W #
S W E B _ E M A IL #
S L ID_ S W #
SC2
2 0m il
2 0m il
3
SJ _ SW 2
*B A V 99 R E C T I F I E R
AC
S MGN D
S M GN D
S MG N D
SU1, SU2
3
C
1
2
3
4
5
6
7
8
9
10
1 0 0K _ 0 4
A
S R2
S _ 3 . 3V S
SJ _ SW 1
SR 1
G ND
S _ 3 .3 V
1
Sheet 40 of 40
Power Switch & LID
Board
2
1 0 pin & 8 pi n co -la y
S M GN D
S _V I N
HOT KEY
WEB_WWW#
SPW R_ SW 1
TJ G -53 3 -S -T / R
1
3
WEB_EMAIL#
SW W W _ SW 1
T JG -5 33 -S -T / R
2
4
S M_ B T N #
1
3
S MA I L _ S W 1
TJ G -53 3 -S -T / R
S W E B _W W W #
2
4
1
3
2
4
5
6
PSW1~8
0 . 1 u_ 1 0 V _X 7 R _ 0 4
3
4
S MG N D
SAP_ SW 1
T JG -5 33 -S -T / R
1
3
2
4
S C3
5
6
5
6
SC 4
AP_KEY#
S R3
*1 00 K _ 0 4
S W E B _ E MA I L #
0 . 1u _ 1 0V _ X 7 R _ 04
SAP_ O N
SC 5
SR 4
0_04
5
6
POWER BUTTON
S R5
* 47 K _ 0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4
1
2
S M GN D
S M GN D
S MG N D
S MG N D
S M GN D
S M GN D
S MGN D
S M GN D
S MH 1
2
3
4
5
S MH 3
9
8
7
6
1
2
3
4
5
MT H 2 3 7D 8 7
S M GN D
S M GN D
1
S M H4
9
8
7
6
2
3
4
5
MT H 2 3 7 D 8 7
1
9
8
7
6
M TH 23 7 D 1 1 8
S MG N D
S MG N D
Power Switch & LID Board B - 41
B.Schematic Diagrams
S _ 3. 3 V S
S _ 3. 3V
POWER
SWITCH
LED
B.Schematic Diagrams
Schematic Diagrams
B - 42