Samsung LNB50 User`s manual

about.book Page 1 Monday, June 7, 1999 10:17 AM
Am186™CC/CH/CU Microcontroller
Customer Development Platform
User’s Manual
Order #22002B
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Contents
About the Am186™CC/CH/CU Microcontroller
Customer Development Platform
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Chapter 1
Quick Start
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Main Board Functional Description
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Development Module Functional Description
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Appendix A
Default Jumper and Switch Settings
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Appendix B
Platform Pin Usage
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Appendix C
Main Board Bill of Materials
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Appendix D
Development Module Bill of Materials
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Appendix E
PLD Equations
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Index
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List of Figures
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List of Tables
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About the Am186™CC/CH/CU
Microcontroller Customer
Development Platform
The AMD Am186™CC/CH/CU microcontroller customer development platform
(CDP) is a system used for customer evaluation and development for the
Am186CC/CH/CU microcontrollers. The platform provides access to the major
microcontroller interfaces and is an ideal tool for developing customer-specific
applications by using the development module interface.
The CDP consists of two boards—a main board that contains the Am186CC
communications controller and interfaces (shown in Figure 0-1), and the
development module, which can be used for the development of various
communications applications such as ISDN TAs and routers (shown in Figure 0-2).
The main board consists of a power supply that provides the necessary voltages
for typical system applications of the Am186CC/CH/CU microcontroller. The
main board also provides a glueless interface to Flash memory and DRAM or
SRAM system main memory, communication interfaces such as a universal
asynchronous receiver/transmitter (UART) and High-Speed UART, universal serial
bus (USB), and four synchronous serial DCE connections. Other features include
the debug interfaces that allow connection to the following:
• ROM-ICE
• Optional Test Interface Port (TIP) debug board
• HP logic analyzer headers to provide access to the Am186CC communications
controller signals
• Expansion interface through the development module or the 104-pin Am186
processor expansion interface
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The development module consists of an Am79C961A PCnet™-ISA II Ethernet
Controller for 10BaseT Ethernet, an Am79C32A ISDN digital subscriber
controller (DSC) circuit for an ISDN S/T connection, an ISDN U connection, and
two POTS connections featuring the Am79C031 DSLAC™ device and two
Am79R79 Ringing SLICs.
NOTE: Although the customer development board provides an Am186CC
microcontroller, you can also use the board to develop Am186CH HDLC
microcontroller applications and Am186CU USB microcontroller applications.
The Am186CH and Am186CU microcontrollers support subsets of the Am186CC
microcontroller features. The Am186CH HDLC microcontroller provides two
HDLC channels and does not support USB or GCI. The Am186CU USB
microcontroller does not support HDLC.
For more information about the Am186CC/CH/CU microcontrollers, refer to
• Am186™CC/CH/CU Microcontroller User’s Manual, order #21914
• Am186™CC Communications Controller Data Sheet, order #21915
• Am186™CH HDLC Microcontroller Data Sheet, order #22024
• Am186™CU USB Microcontroller Data Sheet, order #22025
• Am186™CC/CH/CU Microcontroller Register Set Manual, order #21916
For more information about the CDP board features, refer to “Features” on
page xvii, and Chapter 2, “Main Board Functional Description”.
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Main Board Block Diagram
Figure 0-1 shows the block diagram for the main board on the CDP.
Memory Interface
Expansion Interface
256K x 16 SRAM
SRAM/ICE Socket
Am186 Expansion
Bank 1
256K x 16 DRAM
SRAM/ICE Socket
Bank 0
256K x 16 DRAM
1 MByte Flash Memory
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Development Module Block Diagram
Figure 0-2 (or sheet 2 of the development module schematics included in your kit)
shows the block diagram for the CDP’s development module.
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Theory of Operation
The Am186CC/CH/CU microcontroller CDP provides a comprehensive evaluation
system to support Am186CC/CH/CU microcontroller-based designs. The
combined features of the Am186CC/CH/CU microcontroller CDP offer designers
a complete tool for hardware and software development with the Am186CC/CH/
CU microcontrollers.
NOTE: If you are evaluating the Am186CH or Am186CU microcontroller, all of
the features on the CDP are not available. The Am186CH and Am186CU
microcontrollers support subsets of the Am186CC microcontroller features. The
Am186CH HDLC microcontroller provides two HDLC channels and does not
support USB or GCI. The Am186CU USB microcontroller does not support
HDLC.
Features
The Am186CC/CH/CU microcontroller CDP provides the features described in
the following sections.
Main Board
• Am186CC 3.3-V, 50-MHz Microcontroller
• Power Supply (generates 3.3 V, 5.0 V, -5.0 V, -24 V, and -70 V from a 12-V DC
source)
• Memory Interfaces
– Main system memory
4-Mbit, 256K x 16, 40-ns EDO DRAM
Two 1-Mbit 128K x 8, 35-ns SRAMs configured as 128K x 16
– 8-Mbit configurable 512K x 16, or 1M x 8, 55-ns Flash memory
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• Communication Interfaces
– HDLC synchronous communications
Four RS-422, DB-25 DCE/PCM connections clocked by the main board clock
generator (Am186CH HDLC microcontroller supports only two connections)
Dedicated 2 x 5 header for GCI (supported on Am186CC microcontroller
only)
– Peripheral USB port (supported on Am186CC and Am186CU
microcontrollers only)
– UARTs
One 460-Kbaud, RS-232, DB-9 DCE connection
One 120-Kbaud, RS-232, DB-9 DCE connection
• Debug and Configuration
– 60-pin connector interface to the optional test interface port (TIP) debug board
– Two 32-pin DIP sockets for use with a x16 ROM-ICE
– Eight 2 x 10 shrouded headers to directly connect Am186CC/CH/CU
microcontroller signals to HP analyzers
– Two 4-segment switches to allow pinstrap configuration
– Two 8-segment switches to allow system-specific configuration
Development Module
• 10BaseT Ethernet port
• ISDN interface
– S/T interface
– U interface
• Two POTS Interfaces
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Documentation
The Am186™CC/CH/CU Microcontroller Customer Development Platform
User’s Manual provides information on the design and function of the Am186CC/
CH/CU microcontroller CDP.
About This Manual
Chapter 1, “Quick Start” helps you quickly set up and start using the Am186CC/
CH/CU microcontroller CDP.
Chapter 2, “Main Board Functional Description” describes the basic sections of
the platform: layout, jumper and switch settings, microcontroller, power supply,
memory interfaces, communication interfaces, debug and configuration, and
development module.
Chapter 3, “Development Module Functional Description” describes the features
and components on the development module, including a 10BaseT Ethernet port,
ISDN interface, and POTS interfaces.
Appendix A, “Default Jumper and Switch Settings” provides a table with the
default jumper and switch settings.
Appendix B, “Platform Pin Usage” provides tables describing the CDP’s PIO, chip
select, and interrupt pin usage.
Appendix C, “Main Board Bill of Materials” contains the bill of materials for the
Am186CC/CH/CU microcontroller CDP main board.
Appendix D, “Development Module Bill of Materials” contains the bill of materials
for the Am186CC/CH/CU microcontroller CDP module.
Appendix E, “PLD Equations” contains PLD code for the PLDs at locations U13,
U20, and U24.
A standard index is also included.
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Suggested Reference Material
• Am186™CC/CH/CU Microcontroller User’s Manual
Advanced Micro Devices, order #21914
• Am186™CC Communications Controller Data Sheet
Advanced Micro Devices, order #21915
• Am186™CH HDLC Microcontroller Data Sheet
Advanced Micro Devices, order #22024
• Am186™CU USB Microcontroller Data Sheet
Advanced Micro Devices, order #22025
• Am186™CC/CH/CU Microcontroller Register Set Manual
Advanced Micro Devices, order #21916
• Am186™ and Am188™ Family Instruction Set Manual
Advanced Micro Devices, order #21076
• E86MON™ Software User’s Manual
Advanced Micro Devices, order #21891
• E86™ Family Products and Development Tools CD
Advanced Micro Devices, order #21508
Documentation Conventions
Table 0-1. Notational Conventions
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Chapter 1
Quick Start
This chapter provides information that will help you quickly set up and start using
the Am186™CC/CH/CU Microcontroller CDP.
The CDP is supported by the E86MON™ board-resident debugger. The E86MON
boot monitor software enables you to load, run, and debug programs on the CDP.
For detailed information on using the E86MON software, refer to the E86MON™
Software User’s Manual included in your kit.
For information on how to:
• Connect the CDP to a PC via a serial port, see page 1-2
• Connect the CDP to a PC via a USB port, see page 1-5
• Connect the development module to the main board, see page 1-5
• Connect the TIP to the main board, see page 1-6
• Connect the ROM-ICE to the main board, see page 1-7
• Invoke the E86MON software, see step 5 on page 1-4
• Troubleshoot installation problems, see page 1-8
• Locate related sources of information, see page 1-9
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Connecting to a PC via a Serial Port
Follow the steps below to connect the Am186CC/CH/CU microcontroller customer
development platform to your PC via your PC’s serial port.
Installation Requirements
The items listed below are necessary to install and run the CDP:
• PC with an available COM port
• Terminal emulation software (such as Microsoft® Windows®Terminal or
ProComm Plus) that supports ASCII file transfers, software flow control (Xon/
Xoff), and send break capability.
• Power source for universal power supply
Main Board Installation
CAUTION: As with all computer equipment, the Am186CC/
CH/CU microcontroller CDP’s main board may be damaged by
electrostatic discharge (ESD). Please take proper precautions
when handling any board.
1. Remove the board from the shipping carton. Visually inspect the board to verify
that it was not damaged during shipment.
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2. Connect either of the CDP main board’s DB-9 serial ports to an available COM
port. Use the serial cable included in the Am186CC/CH/CU microcontroller
CDP kit and note that a DB-9 to DB-25 serial connector adapter is provided if
your host system requires it.
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3. Connect the power supply to the barrel connector (see P31 at location A-1 in
Figure 2-2 on page 2-3) on the CDP’s main board.
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4. Apply power to the board by connecting the power supply to an electrical outlet.
When the board is powered up, the LEDs (see CR12–CR8 at locations C-2–
F-2 in Figure 2-2 on page 2-3) should be illuminated.
If all of the LEDs are not illuminated, remove the power supply immediately
and contact AMD technical support. See “If You Have Questions, We’re Here
to Help You.” on page iii.
CAUTION: If using your own power supply, ensure that it is a
12-V supply and is capable of providing at least 2 A.
5. Invoke the terminal emulation program at 19200 baud, no parity, 8 data bits,
and 1 stop bit; enable the software flow control (Xon/Xoff), if supported.
6. Reset the board by depressing and releasing the RESET switch (see SW1 at
location T-23 in Figure 2-2 on page 2-3).
Type an a in the terminal window within three seconds of reset to ensure that
the E86MON software uses the correct baud rate. When the E86MON software
receives an a, it adjusts its baud rate (if necessary) and displays the welcome
message and prompt.
NOTE: If you type a character other than an a, or type no character at all, the
E86MON software still displays the welcome message and prompt, but may be
using an incorrect baud rate. Depressing and releasing the RESET switch (SW1 at
location T-23) gives you another opportunity to type an a.
7. To display the version of the monitor and the commands available, type ? and
press Enter.
For detailed information about using the E86MON software, refer to the
E86MON™ Software User’s Manual included in your kit.
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Connecting to a PC via a USB port
NOTE: USB is not supported on the Am186CH HDLC microcontroller.
Follow the steps below to connect the Am186CC/CH/CU microcontroller customer
development platform to your PC via your PC’s USB port.
1. Insert the flat end of your USB cable into the USB port that is connected to
your PC.
2. Connect the other end of the USB cable into the CDP’s main board USB
connector (see P18 at location I-1 in Figure 2-2 on page 2-3) that is located on
the edge of the board near the power supply (see P31 at location A-1).
To drive the USB, download the USB driver CodeKit software from the AMD
website. The CodeKit software package includes installation instructions for the
USB host driver and the USB driver on the CDP.
Go to www.amd.com, then click on Embedded Processors to get to the Codekit
software packages.
Connecting the Development Module to the
Main Board
Follow the steps below to connect the router/ISDN development module to the
Am186CC/CH/CU microcontroller CDP main board (see Figure 3-3 on page 3-5).
1. Orient the main board such that the AMD logo is in the lower right-hand corner,
facing you. Orient the development module such that the AMD logo is in the
lower leviathan corner, facing you.
2. Position the development module above the development module connectors
(see P12 and P19 at locations M-22 and F-22, respectively, in Figure 2-2 on
page 2-3) on the main board.
3. Carefully press the development module down onto the connectors on the main
board.
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Connecting a TIP to the Main Board
Follow the steps below to connect the test interface port (TIP) debug board to the
Am186CC/CH/CU microcontroller CDP main board:
1. Orient the main board such that the AMD logo is in the lower righthand corner,
facing you.
2. Place the TIP board to the left of the main board with the LCD display toward
you.
3. Plug the TIP connector into the TIP board with the tab facing toward the left.
4. Plug the other end of the connector into the CDP’s main board TIP (see P30 at
location A-19 in Figure 2-2 on page 2-3) with the tab facing up.
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Connecting a ROM-ICE to the Main Board
Follow the steps below to connect a ROM-ICE to the Am186CC/CH/CU
microcontroller customer development platform main board:
1. Orient the main board such that the AMD logo is in the lower righthand corner,
facing you.
2. Set the jumpers according to the configuration shown in Table 1-1 on page 1-7,
and jumper your chip select on JP10 (see location F-9 in Figure 2-2 on
page 2-3).
3. Position the ROM-ICE to the left of the main board.
4. Connect the ROM-ICE Low into the left DIP socket (see U28 at location B-12),
which is labeled SRAM/ROM LOW.
5. Connect the ROM-ICE High into the right DIP socket (see U25 at location
D-12), which is labeled SRAM/ROM HIGH.
Table 1-1. ROM-ICE Configuration
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Troubleshooting Installation Problems
Table 1-2. Installation Troubleshooting
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about.book Page 9 Monday, June 7, 1999 10:17 AM
For More Information...
If you need more information about:
• Am186CC/CH/CU microcontroller CDP hardware,
see Chapter 2 and Chapter 3.
• E86MON software,
see the E86MON™ Software User’s Manual included in your kit.
• Problems with the platform or the E86MON software,
see the customer support information on page iii.
• The Am186CC/CH/CU microcontroller CDP’s main board layout,
see Chapter 2.
• The Am186CC/CH/CU microcontroller CDP’s module layout,
see Chapter 3.
• The Am186CC/CH/CU microcontroller CDP’s main board schematics,
see the schematics document included in your kit.
• The Am186CC/CH/CU microcontroller CDP’s module schematics,
see the schematics document included in your kit.
• The Am186CC/CH/CU microcontrollers,
see the following documents, which are included in your kit:
– Am186™CC Communications Controller Data Sheet
– Am186™CH HDLC Microcontroller Data Sheet
– Am186™CU USB Microcontroller Data Sheet
– Am186™CC/CH/CU Microcontrollers User’s Manual
– Am186™CC/CH/CU Microcontrollers Register Set Manual
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Chapter 2
Main Board Functional Description
The Am186CC/CH/CU microcontroller customer development platform (CDP)
consists of two boards: a main board that contains an Am186CC communications
controller and interfaces, and the development module, which you can use to
develop ISDN and router applications. This chapter describes the main board. The
development module is described in Chapter 3, “Development Module Functional
Description”.
Read the following sections to learn more about the main board:
• “Main Board Layout” on page 2-2
• “Main Board Features” on page 2-8
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Main Board Layout
The Am186CC/CH/CU microcontroller customer development platform is easy to
configure to fit your design requirements. Figure 2-1 shows the main board block
diagram; Figure 2-2 shows the main board layout and component placement; and
Table 2-1 lists the jumpers and switches. Note that the schematics referenced are
in the separate schematic manual in your board kit.
Memory Interface
Expansion Interface
256K x 16 SRAM
SRAM/ICE Socket
Am186 Expansion
Bank 1
256K x 16 DRAM
SRAM/ICE Socket
Bank 0
256K x 16 DRAM
1 MByte Flash Memory
Am186 Expansion
Development Module
TIP Connector
Development Module
Control Bus
Address Bus
AD Bus
HDLC A–D
UART
Clocks
Communication Interface
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Am186CC
Controller
System
USB
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POTS Supply
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USB
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SSI
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Figure 2-2. Main Board Layout
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Table 2-1. Jumpers, Switches, and Adjustments
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Table 2-1. Jumpers, Switches, and Adjustments (Continued)
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Table 2-1. Jumpers, Switches, and Adjustments (Continued)
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Table 2-1. Jumpers, Switches, and Adjustments (Continued)
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1. HDLC channels C and D supported on the Am186CC communications controller only.
2. HDLC channels A and B supported on the Am186CC and Am186CH microcontrollers only.
3. USB is supported on the Am186CC and Am186CU microcontrollers only.
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Main Board Features
The main board is a single-sided, 9- x 12-inch, printed circuit board that integrates
the Am186CC communications controller, a power supply, memory interfaces, and
I/O interfaces onto one board, enabling you to develop specific applications using
the development module interface.
The main board contains debug and status features, and enables you to evaluate
and develop different configurations of memory and I/O by using on-board
configuration switches, jumper blocks, and expansion interfaces.
The following features are described in this section:
• Am186CC/CH/CU microcontroller, page 2-8
• Power supply, page 2-15
• Memory interfaces, page 2-20
• Communications interfaces, page 2-27
• Debug and configuration circuitry, page 2-39
• Expansion interfaces, page 2-49
Am186™CC/CH/CU Microcontroller (J14)
The Am186CC/CH/CU microcontroller customer development platform supports
a 160-pin PQFP Am186CC communications controller operating at 25, 40, or
50 MHz. The integrated features of the Am186CC communications controller
provide a glueless interface to DRAM or SRAM system memory and Flash
memory. The microcontroller also integrates UART and High-Speed UART (which
require only external transceivers), a high-speed (12 Mbit/s) USB peripheral
controller with internal transceiver (Am186CC and Am186CU microcontrollers
only), and HDLC channels (Am186CC and Am186CH microcontrollers only) that
provide external interfaces to gluelessly connect to communications peripherals.
NOTE: Although the CDP supports an Am186CC communications controller, you
can also use this platform to evaluate the Am186CH and Am186CU
microcontrollers. These microcontrollers support subsets of the Am186CC
communications controller’s features. Refer to the device data sheets for more
information.
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The Am186CC communications controller is designed as a cost-effective, highperformance microcontroller solution for communication applications. The
Am186CC communications controller offers the advantages of the x86
development environment’s widely available native development tools,
applications, and system software. For detailed information about the specific
features of the Am186CC/CH/CU microcontroller, refer to the corresponding data
sheet and user’s manual included in your kit. Figure 2-3 shows the Am186CC
communications controller block diagram; Figure 2-4 on page 2-10 shows the
Am186CH HDLC microcontroller block diagram; and Figure 2-5 on page 2-10
shows the Am186CU USB microcontroller block diagram.
Serial Communications Peripherals
Am186
CPU
Chip
Selects
(14)
PIOs
(48)
Watchdog
Timer
Interrupt
Controller
(17 Ext.
Sources)
UART
High-Speed
UART with
Autobaud
USB
Synchronous
Serial
Interface (SSI)
Physical
Interface
Glueless
Interface
to RAM/ROM
DRAM
Controller
Timers
(3)
GeneralPurpose
DMA (4)
SmartDMA
(8)
Controller
HDLC TSA
Raw DCE
HDLC TSA
Memory Peripherals
System Peripherals
Muxing
PCM
Highway
HDLC TSA
HDLC TSA
GCI
(IOM-2)
Figure 2-3. Am186CC™ Communications Controller Block Diagram
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Serial Communications Peripherals
Am186
CPU
Chip
Selects
(14)
PIOs
(48)
Watchdog
Timer
Interrupt
Controller
(17 Ext.
Sources)
UART
High-Speed
UART with
Autobaud
Synchronous
Serial
Interface (SSI)
Physical
Interface
Glueless
Interface
to RAM/ROM
DRAM
Controller
Memory Peripherals
Timers
(3)
GeneralPurpose
DMA (4)
SmartDMA
Channels
(4)
HDLC
TSA
System Peripherals
Raw DCE
Muxing
HDLC
PCM
Highway
TSA
Figure 2-4. Am186CH™ HDLC Microcontroller Block Diagram
Serial Communications Peripherals
Am186
CPU
Chip
Selects
(14)
Glueless
Interface
to RAM/ROM
PIOs
(48)
DRAM
Controller
Memory Peripherals
Watchdog
Timer
Timers
(3)
Interrupt
Controller
(17 Ext.
Sources)
GeneralPurpose
DMA (4)
SmartDMA
Channels
(4)
USB
UART
Synchronous
Serial
Interface (SSI)
High-Speed
UART with
Autobaud
System Peripherals
Figure 2-5. Am186CU™ USB Microcontroller Block Diagram
Am186CC™ Communications Controller Power Supply
The CDP main board provides a 3.3-V power supply for the Am186CC
communications controller. The power supply is sourced from a 3.3-V low drop
out (LDO) regulator (U29) from a 5-V switching power supply. The digital and
analog power pins are isolated by filtering to prevent noise on the digital circuitry
from affecting the internal analog block.
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Am186™CC/CH/CU Microcontroller Clocking
Four types of input clocks are used on the main board: the system clock, USB clock
(Am186CC and Am186CU microcontrollers only), UART clock, and HDLC
clocks (Am186CC and Am186CH microcontrollers only).
The system and USB clocks, shown in Figure 2-6 and Figure 2-7, respectively, use
internal oscillators and PLLs that enable the use of slower, less costly, fundamental
mode crystals for providing system clock frequencies from 16 to 50 MHz, and a
USB frequency of 48 MHz. The UART clock can be derived from the system clock
frequency, or from the UCLK input by using an external oscillator. The on-board
MACH device can be used for the DCE or PCM HDLC clocks at various
frequencies and frame syncs (PCM mode only); or if you are using the development
module interface, you can drive the HDLC clocks from a specific DCE, PCM, or
GCI peripheral. For the available clock options, see Table 2-2.
Table 2-2. CPU and USB Clock Options
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2. UCLK is limited to the maximum frequency of the system clock.
System Clock
The system clock, shown in Figure 2-6 on page 2-12 (or sheet 3 of the main board
schematics included in your kit), can be derived from a fundamental mode crystal
by doing one of the following:
• Driving X1 and X2 at location X1 into the integrated oscillator and using the
internal PLL (see locations H16 and J16 in Figure 2-2 on page 2-3)
• Driving X1 and X2 at location X1 into the integrated oscillator and bypassing
the internal PLL
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The system clock can also be derived from an external oscillator by doing one of
the following:
• Driving an external oscillator from Y5 into X1 and using the internal PLL (see
location H16 in Figure 2-2 on page 2-3)
• Driving an external oscillator from Y5 into X1 and bypassing the internal PLL
The PLL can be configured in 1x, 2x (default), or 4x PLL mode or PLL bypass
mode by appropriately setting the pinstraps on SW16. See “Debug and
Configuration Circuitry” on page 2-39 for more information.
The maximum crystal input and oscillator frequencies are 40 MHz. The CDP
provides pin sockets, allowing the designer to easily attain multiple clock
configurations.
NOTE: When using an external oscillator or clock source to drive the system, USB,
or UART clock, you must drive the clock with a source that does not exceed the
Am186CC/CH/CU microcontroller’s VCC.
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USB Clock
• The USB clock (shown in Figure 2-7or sheet 3 of the main board schematics
included in your kit), which must be 48 MHz, may be derived from one of the
following:
• System clock
• Driving USBX1 and USBX2 at location X2 into the integrated oscillator and
using the internal PLL (see location J16 in Figure 2-2 on page 2-3)
• Driving an external oscillator into USBX1 from Y3 and using the internal PLL
The PLL can be configured in 2x or 4x PLL mode by appropriately setting the
pinstraps on SW16. See “Debug and Configuration Circuitry” on page 2-39 for
more information.
The Am186CC and Am186CU microcontrollers’ USB block requires a 48-MHz
clock input. The USB clocking options are 12 MHz in 4x PLL mode, 24 MHz in
2x PLL mode, or a system clock of 48 MHz.
NOTE: When using the system clock for USB clocking, USBX1 must be
terminated to ground to prevent unwanted oscillation in the unused integrated USB
oscillator. To accomplish this, populate C42 with a
0-Ω resistor.
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The UCLK input at location Y4 (see location J11 in Figure 2-2 on page 2-3) is
used to drive the UART or High-Speed UART with a unique clock source that is
not derived from the system clock. The CDP provides oscillator pin sockets,
enabling the use of standard 3.3-V half-can oscillators.
Am186CC™ Communications Controller Reset
The Am186CC communications controller requires the RES input to be asserted
for at least 1 ms to allow the internal circuitry to stabilize. The CDP main board
uses an external device that monitors the 3.3-V VCC to provide a reset output with
an internal 21-ms RC delay to drive the 3.3-V RES input to the Am186CC
communications controller. Depressing the reset switch (SW1) causes a system
reset without cycling power. Figure 2-8 (or sheet 3 of the main board schematics
included in your kit) shows the reset circuitry.
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Power Supply (A1)
The CDP is powered by a universal power supply that converts 100–200 VAC power
to 12 VDC, 2.5 A. The 12 V enters the CDP main board through a 5.5-mm barrel
connector, where the center post is VCC and the outer ring is GND. From the
12-VDC input, the CDP on-board power supply provides 5 V, 3.3 V, –5 V,
–24 V, and –70 V. The CDP provides power indicators for these voltages at CR8–
CR12. The CDP also provides test jacks that enable you to monitor the VCC voltages
at P22–P25, P28–P29. The following sections provide details about the power
supply. Table 2-3 through Table 2-5, beginning on page 2-18, contain power
estimates for the CDP main board, development module, and CDP totals.
5V@3A
A 5-V buck switching circuit from the 12-V source generates the 5 V, which
provides power to a majority of the components on the CDP main board including
the DRAM, SRAM, and Flash memory components; the DCE and UART
transceivers; the HDLC clock generator; and the 3.3-V LDO regulator. This power
supply is also routed to the CDP development module, TIP connector, and Am186
processor expansion interface connectors. For details, see Figure 2-9 or sheet 14
of the main board schematics included in your kit.
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3.3 V @ 500 mA
The 3.3-V LDO regulator at location U29 generates the 3.3 V from the 5-V output.
This power supply is used to provide power to the Am186CC communications
controller, the USB detect circuitry, and to the optional external USB transceiver.
A population option to use the 3.3-V source for the memory components is
available. This option is available for the case where no 5-V devices are located
on the Am186CC communications controller local bus. For details, see
Figure 2-10 or sheet 14 of the main board schematics included in your kit.
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–5 V @ 200 mA
A 5-V buck-boost switching circuit from the 12-V source generates the –5 V. This
power supply provides power to the CDP development module and POTS interface.
For details, see Figure 2-11 or sheet 14 of the main board schematics included in
your kit.
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–24 V @ 50 mA and –70 V @ 60 mA
A switching flyback circuit from the 12-V source generates the –24 V and the –
70 V. These outputs are routed to the CDP development module and are used in
the POTS interface. For details, see Figure 2-12 or sheet 14 of the main board
schematics included in your kit.
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Table 2-3. Power Estimates for the CDP Main Board
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2. USB is supported on the Am186CC and Am186CU microcontrollers only.
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Table 2-4. Power Estimates for the CDP Development Module
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Table 2-5. Total Power Estimates for the CDP
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Memory Interfaces
The Am186CC/CH/CU microcontroller customer development platform main
board supports DRAM or SRAM system main memory and Flash memory.
Figure 2-13 shows the DRAM or SRAM system and Flash memory map, Figure
2-14 on page 2-21 shows the DRAM and SRAM circuitry, and Figure 2-15 on
page 2-22 shows the Flash memory circuitry.
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Figure 2-13. DRAM or SRAM System Memory and Flash Memory Map
Main Memory
The main board allows the use of two banks of DRAM, or SRAM as the main
memory for the system. The default configuration is one bank of 256K x 16 EDO
DRAM in an SOJ package, located at U21. See Figure 2-14 on page 2-21 or sheet 4
of the main board schematics included in your kit.
In the default configuration, one bank of 256K x 16 EDO, 40-ns DRAM allows
zero wait state operation at up to 50 MHz. The DRAM resides in the lower
512 Kbyte of LCS memory space (0h–7FFFFh). The Am186CC communications
controller provides the DRAM memory address on the odd Am186CC
communications controller addresses A1–A17 to provide a direct connection to
the DRAM device. The DRAM RAS and CAS signaling is provided on the LCS0/
RAS0, MCS1/CAS1, and MCS2/CAS0 signals from the Am186CC
communications controller when DRAM is selected as the main system memory.
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An unpopulated component location, U18, is available for a 256K x 16 device for
DRAM bank 1 to be used in the upper 512K of memory space (UCS space). This
enables you to boot from Flash memory located in UCS space, and then remap
UCS to DRAM bank 1. In this case, the MCS3/RAS1 signal becomes the RAS for
bank 1 and the CAS signals remain the same.
To use SRAM as main system memory, a 256K x 16 SOJ SRAM can be populated
at location U15. R89 must be depopulated, and R90 must be populated with a
10-kΩ resistor.
Another option for using SRAM as main system memory is to use two 32-pin DIP
sockets at U25 and U28 for SRAM devices. The SRAM is configurable to be used
as 128K x 8/512K x 8, or 128K x 16/512K x 16 via configuration jumper blocks
JP11 and JP12. A jumper block, JP10, is also used to route either LCS, UCS, or
MCS0 to the SRAM sockets.
The CDP main board is populated with 128K x 8, 35-ns DIP SRAM devices as the
optional system memory.
NOTE: The SRAM sockets are also used for the x16 ROM-ICE interface. Because
of this, LCS, UCS, or MCS0 can be used, allowing flexibility of chip selects
between the ROM-ICE and on-board Flash memory (see Table 2-6 on page 2-24).
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Flash Memory
A single, surface-mount, TSOP Am29F800, 55-ns, 8-Mbit Flash memory device
is populated on the CDP main board to allow for zero wait state operation at
50 MHz. See Figure 2-15 or sheet 4 of the main board schematics included in your
kit.
You can configure the Flash memory device as 512K x 16 or as a 1-Mbyte x 8
device via configuration switches SW11 and SW14. The default configuration
defines the Flash memory as 512 Kbyte (256K x 16) in UCS space (80000h–
FFFFFh). The highest order address bit of the Flash memory can be connected to
PIO35 rather than A19 by populating R93 with a 0-Ω resistor and removing R92.
This enables you to bank down to the lower half of the Flash memory to extend
available code space to 1 Mbyte. You can also map the Flash memory to MCS0
rather than UCS via jumper block JP8. For more information about jumper
configuration, see page 2-23.
Figure 2-15. Flash Memory Circuit
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Configuration Overview
This section describes the options associated with Flash memory and main system
memory interfaces.
Flash Memory
• Flash memory banking select
Populating R92 enables the highest order address bit to the Flash memory to be
routed from A19 (default). Populate R93 to use PIO35 as the Flash memory
banking select. To operate the Flash memory in a banking scheme, PIO35 (which
is normally High) should be configured to be driven Low when accessing the
lower half of the Flash memory.
• JP8: Flash memory chip select
Jumper block JP8 enables you to route UCS (default) or MCS0 as the Flash
memory chip select.
• SW11: Flash memory data bus width select
Switch SW11 is used to determine the Flash memory device data width as x8
or x16 (default). When configuring the Flash data width to 8 bits, the pinstrap
UCSX8 at SW14 segment 2 must be set to the ON position during reset to
configure the Am186CC communications controller to do 8-bit accesses.
SRAM Main Memory
• JP10: SRAM/ROM-ICE chip select
Jumper block JP10 enables you to route LCS, UCS, or MCS0 to the SRAM
socket’s chip select.
• JP11: SRAM/ROM-ICE device select
Jumper block JP11 is used along with JP12 to select the different SRAM and
ROM configurations.
• JP12: SRAM/ROM-ICE device select
Jumper block JP12 is used along with JP11 to select the different SRAM and
ROM configurations.
Table 2-6 on page 2-24 shows the jumper selections for the various SRAM and
ROM options. Figure 2-16 on page 2-25 (or sheet 5 of the main board schematics
included in your kit) shows the SRAM sockets. Table 2-7 on page 2-26 lists the
SRAM and ROM pinouts.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 24 Monday, June 7, 1999 10:17 AM
Table 2-6. DIP x8/x16 SRAM, ROM-ICE Device Selection
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about.book Page 25 Monday, June 7, 1999 10:17 AM
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about.book Page 26 Monday, June 7, 1999 10:17 AM
Table 2-7. SRAM and ROM Pinouts
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$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 27 Monday, June 7, 1999 10:17 AM
Communication Interfaces
This section describes the communication interfaces available on the Am186CC/
CH/CU microcontroller customer development platform’s main board.
The communication interface I/O ports include two RS-232 DB-9 interfaces for
the low- and high-speed serial ports derived from the integrated Am186CC
communications controller UARTs, four RS-530 DB-25 DCE/PCM ports derived
from the integrated Am186CC or Am186CH microcontroller HDLC interface, and
a peripheral USB port derived from the integrated Am186CC or Am186CU
microcontroller USB peripheral controller.
NOTE: The Am186CH HDLC microcontroller provides only two external HDLC
interfaces and does not support USB; the Am186CU USB microcontroller provides
a USB interface but does not support HDLC.
RS-232 Serial Ports
Two RS-232 serial ports (see Figure 2-17 on page 2-29 or sheet 9 of the main board
schematics included in your kit) are configured as data communication equipment
(DCE) ports to provide direct connection to a typical data terminal equipment
(DTE) port on a PC. This enables you to use a straight serial cable (no null-modem)
when connecting to a PC. The Am186CC communications controller High-Speed
UART is connected to the DB-9 connector at P15 through an RS-232 transceiver
and is capable of a data rate of up to 460 Kbit/s. The low-speed UART is connected
to the DB-9 connector at P7 through an RS-232 transceiver and is capable of a data
rate of up to 120 Kbit/s.
The CDP main board provides individual status LEDs for the high- and low-speed
serial ports (CR6 and CR5, respectively), which illuminate green when data is
being transmitted and red when data is being received by the Am186CC
communications controller UARTs.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 28 Monday, June 7, 1999 10:17 AM
The high- or low-speed serial ports can also be configured to use up to four
additional PIOs as additional hardware flow control at JP5 for the high-speed port,
and JP3 for the low-speed port. The PIOs are defined in an RS232 serial port
configuration as follows:
• PIO0 is used as an output for DCD (Data Carrier Detect).
• PIO1 is used as an input for DTR (Data Terminal Ready).
• PIO27 is used as an output for RI (Ring Indicate).
• PIO28 is used as an output for DSR (Data Set Ready).
Hardware flow control pins RTRHU and CTSHU can be isolated from the highspeed serial port at JP7, so you can use them as their alternate functions and use
the serial port without hardware flow control. An alternative is to use PIO45 and
PIO44 as the high-speed serial port RTRHU and CTSHU functions. Use this
alternative when hardware control is required, and the standard flow control pins
RTRHU and CTSHU are used as an alternate function.
You can shut down the serial port RS-232 transceivers by setting SW9 segment 5
(high speed) and 6 (low speed) to the ON position. This feature is used when the
Am186CC communications controller UART signals are used for their alternate
function.
NOTE: If HDLC Channel D pins are being used as DCE or PCM rather than the
UART, SW9 segment 6 must be set to the ON position to prevent contention
between the RS-232 transceiver and the desired function.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 29 Monday, June 7, 1999 10:17 AM
Figure 2-17. RS-232 Serial Port Routing
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 30 Monday, June 7, 1999 10:17 AM
RS-530 DCE/PCM HDLC Ports
Four HDLC DCE/PCM ports are available on the Am186CC microcontroller (two
for the Am186CH microcontroller) via RS-530 DB-25 connectors configured as
DCE devices from the integrated HDLC controllers in the two microcontrollers.
Figure 2-18 (or sheet 6 of the main board schematics included in your kit) shows
a single HDLC RS-530 circuit.
The Am186CH HDLC microcontroller only provides external HDLC interfaces A
and B and does not support USB; the Am186CU USB microcontroller provides a
USB interface but does not support HDLC.
The RS-530 ports use RS-422 differential transceivers to support up to 10-Mbit/s
data transfers. The actual pinout of the four DB-25 connectors allow an RS-530
device to directly connect to the CDP without using a null-modem-like cable
adapter. The four RS-530 ports have individual transceiver shutdown switches, a
clock generator for DCE and PCM modes, status indicators, and DCE multidrop
mode.
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You can shut down HDLC ports A–D by setting SW9 segments 1–4, respectively,
to the ON position. This enables you to use an alternate function without affecting
the board operation. For example, if you want to use GCI mode, set SW9, segment
1 to the ON position. Now you can use GCI mode as an alternate function on the
development module.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 31 Monday, June 7, 1999 10:17 AM
NOTE: An HDLC interface being used as another function on the CDP must have
that function’s RS-530 port transceiver shut down to prevent contention between
the RS-530 port and the desired HDLC function.
The CDP main board provides individual status LEDs for the four RS-530 DCE/
PCM ports A–D, at CR1–CR4, respectively. The status LEDs illuminate green
when data is being transmitted, and red when data is being received by the
Am186CC or Am186CH microcontroller HDLC RS-530 ports.
The clocking of the DCE or PCM interface is derived from the HDLC clock
generator at U11. SW12, SW10, and SW8 are used to define the clocking mode
(DCE or PCM) and frequency. JP6, JP4, JP2, and JP1 define how the clocks are
routed to each Am186CC or Am186CH microcontroller HDLC RS-530 port. See
Table 2-13 on page 2-36. If the HDLC clocks are being generated by a peripheral
on the development module, you must remove the appropriate jumper from JP6,
JP4, JP2, and JP1.
DCE Mode
The DCE transmit and receive clock to the Am186CC or Am186CH
microcontroller can be varied from 78.125 kHz to 10 MHz and can be routed to
external devices through the RS-530 ports via a set of four jumper blocks. Three
sets of switches define the DCE clocking. The DCE clock is achieved by setting
the switches as follows:
• SW9: The HDLC clock generator does not operate for a particular HDLC
RS-530 port (A–D) unless that port’s shutdown switch SW9 segments 1–4 are
in the OFF position. See Table 2-8 on page 2-32.
• SW12: Switch SW12 segments 1–4 must be in the OFF position to indicate DCE
clocking mode for RS-530 ports A–D, respectively. See Table 2-8 on page 2-32.
• SW8: Switch SW8 segments 1–3 are used to vary the DCE clock frequency in
increments from 78.125 kHz to 10 MHz. See Table 2-9 on page 2-32.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 32 Monday, June 7, 1999 10:17 AM
Table 2-8. Switch Options to Enable R-530 DCE Clocking
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about.book Page 33 Monday, June 7, 1999 10:17 AM
PCM Mode
PCM clocking mode configuration is controlled by the same switches as DCE
clocking with the addition of SW10, which provides a variable PCM frame sync.
The PCM data clock can be varied from 64 kHz to 8.192 MHz, and the frame sync
can be 1, 2, 4, 8, or 16 data clocks wide with positive or negative polarity. The
PCM data clock and frame sync are achieved by setting the switches as follows:
• The HDLC clock generator does not operate for a particular HDLC RS-530 port
(A–D) unless that port’s shutdown switch SW9 segments 1–4 are in the OFF
position. See Table 2-10.
• SW12: Switch SW12 segments 1–4 must be in the ON position to indicate PCM
clocking mode for RS-530 ports A–D, respectively. See Table 2-10.
• SW10: Switch SW10 segments 1–3 are used to vary the PCM frame sync to 1,
2, 4, 8, or 16 data clock widths (dependent upon data clock frequency) and
positive or negative polarity. See Table 2-12 on page 2-35.
• SW8: Switch SW8 segments 1–3 are used to vary the PCM clock frequency in
increments from 64 kHz to 8.192 MHz.
Table 2-10. Switch Options to Enable R-530 PCM Clocking
+'/&
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$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
On
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about.book Page 34 Monday, June 7, 1999 10:17 AM
Table 2-11. Switch Options to Set R-530 PCM Clocking Frequency
6:6ZLWFK
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9LVXDO'HWDLO
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about.book Page 35 Monday, June 7, 1999 10:17 AM
Table 2-12. Switch Options to Set R-530 PCM Frame Sync
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·
Frame sync width = Width Data Clock Period.
Only available at 64 kHz and 128 kHz data clocks.
At 64 kHz and 128 kHz data clocks only.
At 128 kHz data clock only.
Only available at 256 kHz–8.192 MHz data clocks.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 36 Monday, June 7, 1999 10:17 AM
Table 2-13. HDLC DCE/PCM Clock Routing Options
&ORFN
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±
±
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²
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²
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TCLKB
²
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²
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TCLKA
INT
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$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
EXT
TCLKD
RCLKD
TCLKD
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about.book Page 37 Monday, June 7, 1999 10:17 AM
DCE Multidrop Mode
Another feature of the CDP main board is the ability of the HDLC ports to operate
in multidrop mode by using SW3, SW5, SW6, and SW7. When any of these
switches are in the ON position, the transmit (TXD), receive (RXD), and CTS are
shorted together.
NOTE: When operating in DCE multidrop mode, the Am186CC communications
controller DCE interface TXD pins must be configured as open drain.
Peripheral USB Port
NOTE: USB is supported only on the Am186CC and Am186CU microcontrollers.
The CDP provides a full-speed (12 Mbps) peripheral USB port that enables the
CDP to be used as a self-powered USB peripheral.
You can configure the CDP to use the Am186CC or Am186CU microcontroller
full-speed (12 Mbps) USB peripheral controller’s integrated USB transceiver, or
an external transceiver. Using the internal USB transceiver enables the USB
differential signaling (USBD+ and USBD–) to directly connect to the USB
connector and to a USB host or hub through a standard USB full-speed cable.
When the USB port on the CDP is active, the Am186CC or Am186CU
microcontroller’s PIO8 signal is driven Low, which illuminates LED CR7.
Configure the optional external USB transceiver by doing the following:
• Remove R49 and R50.
• Populate R42 and R43 with 0-Ω resistors.
• Populate R55 and R56 with 24-Ω resistors.
• Set pinstrap (USBXCVR) at SW14, segment 3, to the ON position during reset.
Refer to Figure 2-19 on page 2-38 (or sheet 10 of the main board schematics
included in your kit) for the USB circuit diagram.
The Am186CC or Am186CU microcontroller can be used only as a self-powered
USB peripheral because of the power requirements needed in the typical TA/
modem applications. Because of the USB electrical requirements of self-powered
USB peripherals, there is a small amount of glue logic needed to meet the USB
specifications. The attach/detach scenarios addressed with this logic are described
in the following paragraphs.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
about.book Page 38 Monday, June 7, 1999 10:17 AM
Attach
1. The Am186CC or Am186CU microcontroller polls PIO42 for logic High level
to detect an active host/hub upstream connection (USBVCC is on). In the case
where an active USB host/hub is connected to the CDP USB port and power is
not applied to the CDP, Q2 isolates the USBVCC from the CDP to prevent
damage to the Am186CC communications controller.
2. The Am186CC or Am186CU microcontroller drives PIO43 High to enable Q1,
which pulls R58 up to 3.3 V. This pulls up the USBD+ signal to indicate to the
host that a full-speed USB device is present.
Detach
1. Am186CC or Am186CU microcontroller polls PIO42 for a logic Low level to
detect a disconnect condition from the host/hub.
2. The Am186CC or Am186CU microcontroller three states USBD+ and USBD–
in response to the disconnect.
3. The Am186CC or Am186CU microcontroller drives PIO43 to a logic Low
level, which disables Q1 and removes the pullup (R58) from USBD+.
Figure 2-19. Universal Serial Bus Circuit
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Debug and Configuration Circuitry
Several debug and configuration options make the Am186CC/CH/CU
microcontroller customer development platform a useful tool for the development
of specific applications. The CDP offers an interface to the Test Interface Port (TIP)
debug card (not included in your kit) that provides status indicators and debug
peripherals, debug headers to provide access to most critical pins on the
microcontroller, a reset configuration switch to define specific system parameters,
and a pinstrap configuration switch to define particular pin functions.
TIP Interface
The TIP is a small debug card to aid in testing, debug, and software development
of system applications based on the Am186CC communications controller. The
TIP provides the following features:
• An 8-bit on-board Flash device that you can select as the default boot device
• A 2-line x 20-character LCD to provide status information
• Eight hexadecimal LED displays to use for status codes
• Eight readable and writable LEDs for status indication
• Two RS-232 DCE serial ports to enable direct connection to a PC
• A PC-compatible parallel port
• A secondary reset button for the CDP
• A 10BaseT Ethernet port
The interface between the CDP and TIP is set up so it does not use many
microcontroller resources. Refer to Figure 2-20 on page 2-41 (or sheet 13 of the
main board schematics included in your kit) for a schematic of the TIP connector.
The general interface between the CDP and TIP is as follows:
• A19–A0, AD7–AD0, RD, and WLB on the Am186CC communications
controller are used to provide communication between the TIP peripherals and
the CDP.
• The UCS signal on the Am186CC communications controller provides a specific
chip select to the 8-bit Flash memory on the TIP. When selecting the TIP as a
boot device, the UCS signal must be routed to the TIP Flash memory by setting
jumper JP1, 1–2 on the TIP and removing the jumper on JP7 of the CDP.
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• INT0 on the Am186CC communications controller is used as the TIP Ethernet
interrupt signal.
• INT7 on the Am186CC communications controller is used as the TIP serial port
1 interrupt signal.
• INT8 on the Am186CC communications controller is used as the TIP serial port
0 interrupt signal.
• PCS3 on the Am186CC communications controller is used as a chip select
(AEN) for the TIP Ethernet controller.
• ARDY can be used to add wait states for the TIP Ethernet controller.
NOTE: AD7 is also individually interfaced to the TIP card to identify the TIP
being attached through the Am186CC/CH/CU microcontroller RESCON register.
NOTE: To share all TIP interrupts on the INT0 microcontroller input, populate
R279, remove R294, and configure the TIP appropriately.
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Figure 2-20. Test Interface Port Connector
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Debug Headers
Eight 2 x 10 shrouded headers are used to directly interface to the HP 165xx series
logic analyzer through HP series termination adapter to the CDP. Figure 2-21 on
page 2-43 shows the header layout. Figure 2-22 on page 2-44 (or sheet 11 of the
main board schematics included in your kit) shows the header circuit. A majority
of the Am186CC communications controller signals are available from these
headers with several clocking options for state mode triggering.
The headers are grouped as follows:
• P9: HDLC Ports A and B (Am186CC and Am186CH microcontrollers only),
DRQ1–DRQ0
• P10: HDLC Ports C and D (Am186CC communications controller only), UCLK
as clock input
• P13: INT8–INT0, NMI, TMRIN1–TMRIN0, TMROUT1–TMROUT0, HOLD,
HLDA
• P14: PCS7–PCS0, SSI port
• P16: UCS, LCS, MCS3–MCS0, RD, WR, WLB, WHB, RD as clock input
• P17: RESOUT, S2–S0, S6, BHE, ALE, DEN, DT/R, SRDY, ARDY, QS1–QS0,
BSIZE8
• P20: A15–A0, WR as clock input
• P21: AD15–AD0, jumper option for CLKOUT as clock input
Two additional 2 x 25 shrouded headers at locations P8 and P11 are available to
enable additional access to all PIOs, interrupt pins, chip selects, and to provide the
ability to control (via software) the transceiver shutdown signaling for the UART
and HDLC transceivers.
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.
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Figure 2-21. HP Header Grouping
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Reset Configuration
SW13 and SW15 are used to define the state of the RESCON register bits AD15–
AD0. The RESCON register identifies a bit as a logic High when a switch segment
is in the ON position. For details, see Figure 2-24 on page 2-46 or sheet 3 of the
main board schematics included in your kit.
The RESCON register provides a way to make design-specific hardware
configuration information available to software. This information is latched into
the RESCON register from the state of AD[0..15] during reset. The Am186CC/
CH/CU microcontroller’s weak internal pulldowns default AD[0..15] Low during
reset. SW13 and SW15 can be used to set individual bits AD[0..15] High by setting
the appropriate switch segment to the ON position. Figure 2-23 shows the RESCON
register bits.
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Figure 2-23. RESCON Register Bits
• Customer Development Platform: Identifies if the board is a CDP.
• Board ID: Unique board identifier that is used to determine what features are
available to the software.
• 0: Bits are reserved for future use.
• Panic Bit: Used by E86MON software to boot in a “safe mode”.
• TIP: Identifies the TIP board as being present in the system.
• Board Configuration: Identifies particular population option for the board.
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Figure 2-24. Reset Configuration Switches
Pinstrap Configuration
Pinstrap configuration is used to define a particular Am186CC communications
controller function of a pin or interface at power up. All pinstraps have a logic High
state during reset as the default. The pinstrap switches SW14 and SW16 enable
you to define and vary system configuration as needed. The following options are
available:
System and USB PLL clocking modes
SW16 segments 1 and 2 are used for the pinstraps controlling the system clock
PLL mode on the CDP. The default setting for the system PLL is 2x PLL mode to
attain a 40-MHz system frequency with the 20-MHz crystal input. Setting a
segment of SW16 to the ON position during system reset indicates a logic 0, and
setting a segment of SW16 to the OFF position indicates a logic 1.
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SW16 segments 3 and 4 are used for the pinstraps controlling the USB clock PLL
mode on the CDP. The default setting for the USB PLL is 2x PLL mode to attain
a 48-MHz USB frequency with the 24-MHz crystal input. Setting a segment of
SW16 to the ON position during system reset indicates a logic 0; setting a segment
of SW16 to the OFF position indicates a logic 1. See Figure 2-25 (or sheet 3 of the
main board schematics included in your kit), Table 2-14, and Table 2-15 for more
information.
Table 2-14. System and USB Clock Modes1
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1. If you do not want to use the USB PLL or you are using the Am186CH HDLC microcontroller, which does not
support USB, the USBX1 input must be tied to VSS.To do this, install a 0-Ω resistor at location C42.
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Table 2-15. CPU and USB Clocking Options
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1. The USB clock is supported on the Am186CC and Am186CU microcontrollers only.
2. UCLK is limited to the maximum frequency of the system clock.
Flash memory boot width
SW14 segment 2 is used to define the Flash memory boot width as x8 or x16. The
default setting is 16 bits and is set when SW14 segment 2 is in the OFF position.
Setting SW14 segment 2 to the ON position during reset defines the boot width as
8 bits. Refer to Figure 2-26 on page 2-49 (or sheet 3 of the main board schematics
included in your kit).
NOTE: If booting from the CDP Flash memory in 8-bit mode, SW14 segment 2
must be in the ON position, and SW11 must be set to the x8 position.
Turn off address phase of the AD bus
You can turn off the address phase of the AD bus by setting SW14 segment 1 to
the ON position during reset and setting the appropriate Am186CC
communications controller registers. Refer to Figure 2-26 on page 2-49 (or sheet 3
of the main board schematics included in your kit).
Use an external USB transceiver
To use an external USB transceiver, move resistors R49 and R50 to locations R42
and R43, populate R55 and R56 with 24-Ω resistors, and set SW14 segment 3 to
the ON position. Refer to Figure 2-19 on page 2-38 (or sheet 10 of the main board
schematics included in your kit) and Figure 2-26 on page 2-49 (or sheet 3 of the
main board schematics included in your kit).
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Figure 2-26. Miscellaneous Pinstrap Circuit
Expansion Interfaces
The Am186CC/CH/CU microcontroller customer development platform supports
two expansion interfaces: the Am186 processor local bus expansion interface,
which is electrically and physically compatible to the existing Am186 family
demonstration boards, and the development module interface, which can be used
for the ISDN/router development module.
Am186™ Processor Expansion Interface
The Am186 processor local bus expansion interface, located at P26 and P27,
supports the PC/104 form-factor expansion connector for additional prototyping
and testing. The traditional PC/104 signals are not present on the board; however,
the Am186 processor expansion interface enables you to attach wirewrap or
prototype boards that have the same standard physical interface. The electrical
interface is similar to the PC104, but is not fully compatible to the PC104 electrical
standard. The physical orientation and pinouts are shown in Figure 2-27 or sheet 12
of the main board schematics included in your kit.
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15 MCS2
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Development Module Interface
The development module interface, located at P19 and P12, is primarily used to
provide an interface to the ISDN/router development module. This module enables
the CDP to be used as a specific system application. The module connectors contain
all the signals needed to develop particular applications based on the Am186CC
communications controller. See Figure 2-28 on page 2-52 (or sheet 13 of the main
board schematics included in your kit) for the development module interface.
Interfaces provided include the following:
• 3.3 V, 5 V, –5 V, –24 V, and –70 V power
• Full address and data buses
• All 14 memory and peripheral chip selects
• Nine external interrupt pins
• Full control and status pins
• Four full HDLC interfaces (HDLC Channels A and B supported on the
Am186CC and Am186CH microcontrollers only. HDLC Channels C and D
supported on the Am186CC communications controller only.)
• SSI interface
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Chapter 3
Development Module Functional
Description
The Am186CC/CH/CU microcontroller customer development platform (CDP)
consists of two boards: a main board that contains an Am186CC communications
controller and interfaces, and the development module, which you can use to
develop ISDN and router applications. This chapter describes the development
module. The main board is described in Chapter 2, “Main Board Functional
Description”.
Read the following sections to learn more about the development module:
• “Development Module Layout” on page 3-2
• “Customer Development Platform Development Module Features” on page 3-4
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Development Module Layout
Figure 3-1 (or sheet 2 of the development module schematics included in your kit)
shows a block diagram of the Am186CC/CH/CU microcontroller CDP
development module; Figure 3-2 on page 3-3 shows the layout of the development
module.
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Figure 3-2. Router/ISDN Development Module Layout Diagram
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Customer Development Platform
Development Module Features
The development module is a 6-layer, 6- x 6-inch printed circuit board used to
target specific communication-based system applications using the Am186CC
communications controller. The development module interfaces to the CDP main
board through two 2 x 35 pin connectors. This interface enables you to use the
CDP development module and provides you with a vehicle to develop specific
applications.
The development module contains the system components used in developing
ISDN terminal adapter/modem and low-end router applications that use many
AMD-specific devices.
This section describes the following development module features:
• Main board interface on page 3-4
• 10BaseT Ethernet interface on page 3-7
• ISDN interface on page 3-12
• POTS interface on page 3-18
Main Board Interface
The development module is a printed circuit board that attaches to the Am186CC/
CH/CU microcontroller CDP main board through two 2 x 35, surface-mount, keyed
connectors (AMP104693-7). The connectors are three inches apart and have a 390mil mated height clearance between the main board and the development module.
Figure 3-3 on page 3-5 shows the connection between the main board and the
development module. Figure 3-4 on page 3-6 (or sheet 3 of the development module
schematics included in your kit) shows the connector layout.
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Figure 3-3. Main Board and Development Module Connection
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Figure 3-4. Router/ISDN Development Module Connector Layout Diagram
The interface between the Am186CC/CH/CU microcontroller CDP main board
and development module incorporates the full Am186CC communications
controller local bus address, data, and most control signals. The interface also
supports the four external HDLC interfaces (see note), SSI, and the 3.3-V, 5-V, –
5-V, –24-V, and –70-V power supplies.
NOTE: The Am186CC communications controller provides four HDLC channels.
The Am186CH HDLC microcontroller provides two HDLC channels. The
Am186CU USB microcontroller does not support HDLC. HDLC channel A, and
optionally, HDLC channel D, are the only HDLC channels used on the ISDN
development module.
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The two module connectors separate the high-speed Am186CC communications
controller local bus interface from the communications-specific interfaces such as
the HDLC interfaces, SSI, and the power supply.
Because of the large number of devices connected to the Am186CC
communications controller local bus on the CDP main board and development
module, the full address bus, AD bus, and heavily loaded control signals are
buffered. The buffering prevents excess loading, which can affect timing and
possibly cause functional errors at higher bus frequencies.
The development module uses three 74ACT16245 16-bit transceivers to buffer the
signals previously described. Typically, bidirectional buffering is not required for
the address and control buses; however, because the module incorporates a bus
mastering Ethernet controller (AMD Am79C961A), control of these buses is given
to the bus mastering device. Control logic for the buffers is incorporated in a
programmable logic device (PLD), U13, used on the development module (see
Figure 3-4 on page 3-6).
10BaseT Ethernet Interface
The Am186CC/CH/CU microcontroller CDP development module uses an AMD
Am79C961A PCnet™-ISA II Ethernet controller configured in bus master mode
for its Ethernet interface. The Ethernet interface consists of a connection between
the PCnet-ISA II twisted pair interface to an RJ45 connector, a 20-MHz crystal,
an optional EEPROM for Plug-n-Play (PnP) capability, three status LEDs, SRAM
used to transfer Ethernet packet data, and a small amount of glue logic required to
interface the Am186CC communications controller to the PCnet-ISA II Ethernet
controller.
The development module provides Ethernet through the PCnet-ISA II twisted pair
interface with the addition of a single 10BaseT transformer (U5) to the RJ-45
connector at P1. To link the Ethernet station to a network, connect the straightthrough cable provided in your kit to a hub that sits on the network.
Figure 3-5 on page 3-8 and Table 3-1 on page 3-8 show the pin assignment and pin
functions for the RJ-45 connector.
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Table 3-1. RJ-45 Connector Pin Functions
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Three LEDs (CR1–CR3) on the Ethernet controller interface provide status
information for the port. The function of these LEDs is controlled by the ISA bus
configuration registers on the PCnet-ISA II Ethernet controller and can be modified
through software or the EEPROM. The default functions of the LEDs are shown
in Table 3-2.
Table 3-2. PCnet™-ISA II Ethernet Controller LED Status Information
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The module can be configured to use the 64K x 16 on-board SRAM or main system
memory as the Ethernet packet SRAM. When the main system memory is DRAM,
the development module’s 64K x 16 SRAM must be used as packet memory
because the Ethernet controller DMAs directly to the SRAM and cannot bus master
to DRAM.
The default configuration of the CDP uses DRAM as main system memory and
the 64K x 16 SRAM as the Ethernet packet memory. In this configuration, the
DRAM resides in the lower 512 Kbytes of memory space from 00000h–7FFFFh,
and the 128 Kbytes of Ethernet packet SRAM uses MCS0 space located from
80000h–9FFFFh.
When SRAM is used as main system memory, the Ethernet packet SRAM and the
system memory both reside in LCS space from 00000h–7FFFFh. The packet
SRAM configuration is selected by setting jumper JP1 at the appropriate position:
LCS or MCS0.
A small amount of glue logic is required to interface the PCnet-ISA II Ethernet
controller to the Am186CC communications controller because the PCnet-ISA II
Ethernet controller is an ISA peripheral device. The required logic is achieved
through an Am22V10 PLD at location U13. Refer to location C8 in Figure 3-2 on
page 3-3. The PLD controls three signals between the Ethernet controller and the
Am186CC communications controller: SRAMCS, SBHE, and BHLDA.
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The PLD creates the Ethernet packet SRAM chip select, SRAMCS, from the
MASTER output when the PCnet-ISA II Ethernet controller is the bus master.
When the Am186CC communications controller is the bus master, the SRAMCS
output is three-stated and MCS0 is used as the packet SRAM chip select.
SBHE is modified from the Am186CC communications controller BHE signal to
meet ISA specifications required by the PCnet-ISA II Ethernet controller. BHLDA
is an inverted Am186CC communications controller HLDA and becomes the
PCnet-ISA II DMA acknowledge input (DACK). Refer to Appendix G for a full
listing of PLD equations.
Figure 3-6 (or sheet 4 of the main board schematics and sheet 5 of the development
module schematics included in your kit) show the 10BaseT Ethernet interface.
Figure 3-7 on page 3-11 (or sheet 4 of the development module schematics included
in your kit) shows the Ethernet controller.
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ISDN Interface
The Am186CC/CH/CU microcontroller CDP development module provides both
ISDN S/T and U interfaces. You must use these interfaces independently unless
you have physically configured the module as a network termination (NT1) device
through a population option. The four-wire 2B+D S/T interface connects through
an RJ-45 connection at P2 by using the Am186CC communications controller with
the AMD Am79C32A DSC circuit. This connection provides the path between a
TE (terminal equipment) and NT1 device, and is the ISDN interface commonly
used in businesses and in Europe.
The two-wire 2B+D U interface uses the Lucent T7256A NT1 device. The NT1
device provides the termination point at the RJ-45 connection at P3 between the
local exchange (LE) and ISDN Terminal Equipment (TE1), and between the
terminal adapter (TA) and non-ISDN terminal equipment (TE2). The U interface
is the main ISDN interface provided in North America and Asia. The default
configuration of the NT1 in this design is to provide a connection between a TA
interface to a PC and a TE2 interface to two plain old telephone service (POTS)
phones. Refer to Figure 3-8 for an illustration of the ISDN reference points.
Three LEDs (CR4–CR6) are used to indicate activity on the ISDN B1, B2, and D
channels using Am186CC communications controller signals PIO18, PIO39, and
PIO32, respectively.
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ISDN S/T Interface
The glueless connection between the Am186CC communications controller and
the Am79C32A ISDN DSC circuit provides the four-wire 2B+D S/T interface. The
DSC serial interface is capable of being configured as an IOM-2 or SBP serial
microprocessor interface. This interface is used to transfer data to and from the
Am186CC communications controller using the microcontroller’s integrated
HDLC in GCI or PCM mode; the Am186CC communications controller x86
microprocessor interface is used for configuration.
The Am186CC communications controller provides a full-duplex path between
the TE and NT device or the PABX linecard. It processes the ISDN BRI bit stream,
which consists of two 64-Kbit/s B channels and a single 16-Kbit/s D channel. The
four-wire ISDN S/T interface is first directed through an S transformer and line
filtering devices, which isolate and protect the modem from the outside lines. The
schematic for the S/T interface block is shown in Figure 3-9 on page 3-14 (or
sheet 6 of the development module schematics included in your kit).
In the default S/T configuration, the Am79C32A DSC circuit is operating in SBP
mode. The Am79C32A DSC circuit is also providing the clock and frame sync to
the Am186CC communications controller across the integrated HDLC A interface,
which is configured in PCM mode, and to the Am79C031dual channel codec
(DSLAC) device (PCM Codec) used for the POTS interface.
In a second configuration, the Am79C32A DSC circuit is operating in IOM-2
mode; the Am186CC communications controller is in GCI mode; and the DSLAC
device is in PCM mode. In this configuration, the data clock for the DSLAC is
generated by the BCLK output from the Am79C32A DSC circuit.
A third configuration uses the Am79C2A DSC circuit in an IOM-2 mode. The
Am186CC communications controller provides a GCI-to-PCM conversion of the
data clock and frame sync to enable the Am79C031 DSLAC device (PCM Codec),
to communicate directly between the Am79C32A DSC circuit and the Am79C031
DSLAC device for the POTS interface. Refer to “POTS Interface” on page 3-18
for more information about this configuration.
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The Am79C32A DSC circuit uses the PCS1 (peripheral chip select 1) signal, which
asserts between addresses 100h and 1FFh, and the INT6 (interrupt 6) signal is edge
triggered as an active Low interrupt. The Am79C32A DSC circuit’s MCLK output
is programmed to be 4.096 MHz and is used to drive the MCLK input to the
Am79C031 DSLAC device on the POTS interface through JP2.
A fourth configuration uses the Am79C32A DSC circuit with the T7256A
U transceiver. In this mode, the data clock and frame sync are generated by the
Am79C32A DSC circuit. Data is passed from the Am186CC communications
controller or POTS interface through the Am79C32A DSC circuit to the T7256A
U transceiver through the S/T interface. For configuration details, refer to “ISDN
U Interface” on page 3-15.
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ISDN U Interface
The Lucent T7256A NT1 device provides the two-wire 2B+D U interface to
provide two-wire network termination. The NT1 device processes the ISDN BRI
bit stream that consists of two 64-Kbit/s B channels and a single 16-Kbit/s
D channel. The U interface circuit includes a line fuse, U transformer, DC
termination IC, and opto-isolation circuitry.
The U interface default configuration uses the Am186CC or Am186CH
microcontroller SSI interface to configure the NT1; the NT1 TDM bus is used to
transfer data between the NT1 device and either the microcontroller’s integrated
HDLC in PCM mode, or the POTS interface.
The microcontroller’s SSI interface to the NT1 microprocessor’s serial interface is
controlled by the PLD (U13). The PLD is required to select the NT1
microprocessor’s serial interface because the NT1 device does not have an SSI chip
enable, and the development module’s POTS interface DSLAC device also has an
SSI interface. The PLD uses the Am186CC or Am186CH microcontroller’s PIO38
signal asserted Low to pass the SSI clock to the NT1 device during NT1
configuration.
The NT1 TDM bus is the PCM clock master and the upstream device to the
Am186CC or Am186CH microcontroller and the DSLAC device in the POTS
interface. In this configuration, the TDM bus drives the PCM data clock and frame
sync, and transmits data directly to and from the Am186CC or Am186CH
microcontroller and the DSLAC device in the POTS interface.
An alternate configuration option uses the Am79C32A DSC circuit and T7256A
device together on the module. In this configuration, data is transferred between
the Am186CC or Am186CH microcontroller’s integrated HDLC and the
Am79C32A DSC circuit. The T7256A NT1 device communicates with the
Am79C32A DSC circuit through its S/T interface. See Table 3-3 on page 3-16 for
configuration information.
CR7 is used for NT1 device status. The four states of the LED are off, on, 1 Hz,
and 8 Hz. Table 3-4 on page 3-16 shows the U interface LED status. The schematic
for the U interface block is shown in Figure 3-10 on page 3-17 (or sheet 7 of the
development module schematics included in your kit).
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Table 3-3. U Interface Configuration
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Figure 3-10. ISDN U Interface
In the ISDN U configuration, the Am186CC communications controller uses the
SSI and INT2 as an edge-triggered, active Low interrupt to configure the T7256A
device through its serial microprocessor interface. The T7256A 2B+D channel
communication is performed across the T7256A time-division multiplex (TDM)
bus, which is directly connected to Am186CC communications controller HDLC
channel A, configured in PCM mode. The T7256A device provides a 2.048-MHz
clock and frame sync to transfer data between the TDM and the Am186CC
communications controller PCM interface, and the Am79C031 codec PCM bus
for the POTS interface.
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POTS Interface
The Am186CC/CH/CU microcontroller CDP development module provides two
POTS connections on RJ-11 connectors at P5 and P4. These POTS connections
are used to plug standard POTS telephones in an ISDN terminal adapter or router
application.
To accomplish this, the development module’s Am79R79 ringing SLIC (RSLIC)
device and one half of an Am79C031 DSLAC device provide an interface to plug
in a POTS telephone to communicate across an ISDN B channel.
The basic premise of this type of application is to bring all the functions normally
performed at a central office on a normal POTS line to the user’s home or office.
The Am79R79 RSLIC device provides the DC power, ringing, and supervisory
functions to the phone. The Am79C031 DSLAC device provides the analog voiceto-digital conversion to allow communication to the ISDN interface transceivers.
The development module also provides the appropriate voltages needed for the
DSLAC and RSLIC devices, signaling for ring generation to the Am79R79 RSLIC
device, and DTMF decoders that detect dial tone pairs from the POTS telephone,
and transfer that information to the Am186CC communications controller. In
addition, a low noise board (LNB) interface enables the user to disable the DSLAC
and RSLIC used on the development module and use the LNB boards for the POTS
interface.
DSLAC™ Device PCM Interface
The DSLAC device PCM interface connects directly to the following:
• Am79C32A DSC circuit S/T transceiver peripheral port bus, configured in serial
bus port (SBP) or IOM-2 mode
• T7256A U transceiver TDM bus
• Am186CC communications controller HDLC channel A interface in PCM or
GCI mode; channel D interface in PCM mode
Figure 3-11 on page 3-19 (or sheet 10 of the development module schematics
included in your kit) shows the DSLAC device circuitry.
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Figure 3-11. DSLAC™ Device Circuitry
In the default configuration, the S/T or U transceiver provides the clock and frame
sync for the PCM interface and transfers data directly between the ISDN interface
and the POTS interface.
Six DSLAC device clocking configurations are available for use on the CDP
development module, as listed below. See Table 3-5 on page 3-21 for jumper
settings of each mode.
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S/T SBP Mode
The DSLAC device’s PCLK and MCLK can be generated from the Am79C32A
DSC circuit’s CLKA and FSCA outputs. In this case, PCLK is a 192-kHz data
clock, and MCLK is configured as a 4.096-MHz master clock driven directly into
the DSLAC device.
S/T SBP mode with PLD (module_20_u20_pcm_00)
U20 is used to modify the PCLK and MCLK inputs to the DSLAC device to address
a potential Am79C32A DSC circuit-to-DSLAC jitter anomaly. Contact customer
support for more information. In this case, the MCLK output from the Am79C32A
DSC circuit is configured as 12.288 MHz, and the PLD generates the DSLAC
device’s 768-kHz PCLK and 4.096-MHz MCLK from the 12.288-MHz source.
S/T IOM-2
The DSLAC device’s PCLK and MCLK are generated from the Am79C32A DSC
circuit’s 768-kHz BCLK and programmable 4.096-MHz MCLK outputs,
respectively.
S/T IOM-2 with PLD (module_20_u20_gci_00)
U20 is used to modify the PCLK and MCLK inputs to the DSLAC to address a
potential Am79C32A DSC circuit-to-DSLAC device jitter anomaly. Contact
customer support for more information. In this case, the MCLK output from the
Am79C32A DSC circuit is configured as 12.288 MHz, and the PLD generates the
DSLAC device’s 768-kHz PCLK and 4.096-MHz MCLK from the 12.288-MHz
source.
S/T IOM-2 with GCI-to-PCM Conversion
The DSLAC device’s PCLK and FS are generated by the Am186CC
communications controller CLKC and FSCC outputs, respectively. The DSLAC
device’s MCLK is generated by the Am79C32A DSC circuit’s MCLK output. In
this case, the Am79C32A DSC circuit generates the master data clock and frame
sync. The Am186CC communications controller receives the master clocks from
the Am79C32A DSC circuit and generates a 768-kHz PCM data clock and an
8-kHz frame sync to be used by the DSLAC device.
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U PCM
The T7256 U transceiver generates a 2.048-MHz PCLK that can be directly
connected to the DSLAC device’s PCLK and MCLK inputs.
NOTE: HDLC channel C and GCI are supported only on the Am186CC
communications controller.
MCLK is the master clock used to drive the DSLAC device’s internal DSP. MCLK
must be 2.048 MHz or 4.096 MHz and can be asynchronous to the DSLAC device’s
PCLK input. The MCLK input is derived from whichever ISDN transceiver is being
used as the upstream ISDN device. If the U interface is selected using the T7256
as the clock master, MCLK is derived directly from the 2.048-MHz CLKA output
from the T7256A. If the S/T interface is selected as the clock master, PCLK is
derived from the Am79C32A DSC circuit MCLK output (MCLK_C32) or from
the output and PLD U20, which synchronizes the DSLAC MCLK input to its PCLK
input. Table 3-5 shows MCLK jumper configuration.
Table 3-5. Am79C031 DSLAC™ Device PCLK/FS/MCLK Configuration
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1. U20 is used to modify the clocks to properly synchronize to the DSLAC device’s PCM timing.
2. Requires PAL at U20 to use PLD code module_20_u20_gci_00 for IOM-2 mode, and module_20_u20_PCM_00
for SBP mode.
3. PCLK and FS for the DSLAC device are generated by the Am186CC communications controller.
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Because the Am186CC communications controller and the Am79C031 DSLAC
device are both downstream devices to the ISDN controller, the PCM/GCI data is
driven from the ISDN device transmit pin (TXD) to the Am186CC communications
controller and the DSLAC receive pins (RXD) and vice-versa. This configuration
causes a problem when the Am186CC communications controller needs to
communicate directly with the DSLAC device on the PCM bus (e.g., for PABX
applications).
To solve this problem, the development module has a configuration option to use
Am186CC communications controller HDLC interface D to transmit directly to
the DSLAC device on the PCM bus. This is achieved by using the Am186CC
communications controller PCM time-slot control (TSCD) pin and the DSLAC
device time-slot control (TSC) to transmit only PCM data on the appropriate time
slot. PLD U24 controls these functions on the development module. Table 3-6 on
page 3-23 shows configuration options.
NOTE: Using HDLC channel D on the development module causes the CDP main
board UART to be nonfunctional because the HDLC channel D pins are
multiplexed with the UART. The High-Speed UART flow control is also
unavailable because the HDLC channel D time-slot control is multiplexed with
one of these pins.
The Am186CC communications controller SSI interfaces to the DSLAC device’s
microprocessor interface for programming and control of the DSLAC device. The
default configuration uses PIO17 for the SSI enable for POTS channel 1, and the
SDEN signal is used for the SSI enable for POTS channel 2. This allows the two
channels to be individually configured. An optional configuration allows the two
DSLAC channels to be identically programmed by using SDEN as the SSI enable
for both channels. This is achieved by populating R72 and configuring PIO17 as
a PIO input.
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Table 3-6. Am186™CC Communications Controller/Am79C031 DSLAC™
Communication Configuration
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RSLIC Device Interface
The DSLAC device provides a direct connection to the Am79R79 RSLIC through
two sets of data and control I/O signals used for each channel. The data signals are
analog signals from the RSLIC device. These analog signals are digitized and
transmitted to the PCM bus. The control signals are used to control telephone states
and to detect status.
The RSLIC device ringing is generated via a 20-Hz, CMOS-compatible signal.
The signal is created through the PLD at U24 from the Am186CC communications
controller’s PIO40 and PIO41 signals, which correspond to POTS channels 1 and
2, respectively. The PLD takes the 3.3-V, peak-to-peak PIO outputs and converts
them to 5-V peak-to-peak to satisfy the requirements for the RSLIC device. Figure
3-12 on page 3-24 (or sheet 8 of the development module schematics included in
your kit) show the DSLAC-to-RSLIC circuit interface.
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Dual Tone Multiple Frequency (DTMF) Interface
The two DTMF receivers are used to detect valid tone pairs from each POTS
telephone interface, and then translate them into digital signaling. The digital
signaling is used by the Am186CC communications controller to set up and place
a call. When a DTMF detects a valid tone pair from the RSLIC device, the DTMF
sends an active High interrupt (INT4 for POTS channel 1 and INT5 for POTS
channel 2) to the Am186CC communications controller. The DTMF becomes
available on the AD3–AD0 after the Am186CC communications controller issues
an active High output enable to the corresponding DTMF OE pin. The output
enables are generated by inverting PCS5 and PCS4 for POTS channels 1 and 2,
respectively, in the PLD device at U24. Figure 3-13 (or sheet 10 of the development
module schematics included in your kit) shows the DTMF circuit.
Figure 3-13. DTMF Interface Circuit
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Low Noise Board (LNB) Interface
The LNB interface can be used to connect Low Noise Boards developed in AMD’s
Communication Products Division (CPD). The LNB’s are evaluation boards which
contain different AMD SLAC and SLIC devices. This feature allows the user to
disable the DSLAC and RSLIC used on the development module and use the LNB
boards for the POTS interface.
To use the LNB interface, plug the LNB SLAC board into P6. This may be a direct
connection if the LNB board contains a DB-25 male connector or may require an
adapter cable to interface to the LNB 50-pin male connector. All jumpers from JP3
and R71 must be removed to disable the DSLAC on the development module. In
this configuration, the LNB uses the HDLC channel A interface from the
development module. The clock and frame sync are driven directly from the PCM
or GCI clock master on HDLC channel A and MCLK is driven from the JP3 source.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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Appendix A
Default Jumper and Switch
Settings
This appendix contains the default jumper and switch settings for the main board
and development module.
Table A-1. Main Board Default Jumper and Switch Settings
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Table A-1. Main Board Default Jumper and Switch Settings (Continued)
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Table A-1. Main Board Default Jumper and Switch Settings (Continued)
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Table A-1. Main Board Default Jumper and Switch Settings (Continued)
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Table A-1. Main Board Default Jumper and Switch Settings (Continued)
1.
3DUW
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Insert jumper on a signal pin for a no connect (NC).
Table A-2. Router/ISDN Development Module Default Jumper and Switch Settings
3DUW
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0&6
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Insert jumper on a signal pin for a no connect (NC).
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$
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Appendix B
Platform Pin Usage
This appendix provides the Am186CC/CH/CU microcontroller CDP pin usage
information in the following tables.
Table B-1. PIO Usage
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Table B-1. PIO Usage (Continued)
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Table B-1. PIO Usage (Continued)
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Am186CC communications controller only.
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Table B-2. Chip Select Usage
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Table B-3. Platform Interrupts Pin Usage
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Appendix C
Main Board Bill of Materials
This appendix provides the Am186CC/CH/CU microcontroller customer
development platform bill of materials.
Table C-1. Main Board Bill of Materials
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1
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Table C-1. Main Board Bill of Materials (Continued)
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Table C-1. Main Board Bill of Materials (Continued)
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Table C-1. Main Board Bill of Materials (Continued)
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Table C-1. Main Board Bill of Materials (Continued)
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Table C-1. Main Board Bill of Materials (Continued)
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Table C-1. Main Board Bill of Materials (Continued)
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Table C-1. Main Board Bill of Materials (Continued)
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about.book Page 9 Monday, June 7, 1999 10:17 AM
Table C-1. Main Board Bill of Materials (Continued)
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&
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Appendix D
Development Module Bill of
Materials
This appendix contains the Am186CC/CH/CU microcontroller customer
development platform development module bill of materials.
Table D-1. Router/ISDN Development Module Bill of Materials
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Table D-1. Router/ISDN Development Module Bill of Materials (Continued)
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Table D-1. Router/ISDN Development Module Bill of Materials (Continued)
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Table D-1. Router/ISDN Development Module Bill of Materials (Continued)
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Table D-1. Router/ISDN Development Module Bill of Materials (Continued)
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Table D-1. Router/ISDN Development Module Bill of Materials (Continued)
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about.book Page 7 Monday, June 7, 1999 10:17 AM
Table D-1. Router/ISDN Development Module Bill of Materials (Continued)
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about.book Page 8 Monday, June 7, 1999 10:17 AM
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about.book Page 1 Monday, June 7, 1999 10:17 AM
Appendix E
PLD Equations
This appendix contains a listing of PLD equations for the PLDs located at U13,
U20, and U24 on the Am186CC/CH/CU microcontroller CDP.
NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or
make any further information, software, technical information, know-how, or
show-how available to you.
NO WARRANTIES, LIMITATIONS OF LIABILITY: AMD is providing these
materials to you "as is, with all faults." AMD makes no warranty whatsoever,
express, implied, statutory, contractual or otherwise with respect to the materials,
and expressly disclaims any implied warranty of merchantability, fitness for a
particular purpose, title or non-infringement and any warranties arising by virtue
of custom of trade or course of dealing. AMD also advises you that the materials
specify components not manufactured or sold by AMD in the normal course of its
business.
In no event shall AMD be liable for any indirect, punitive, special, incidental or
consequential damages in connection with or arising out of your use of or inability
to use the materials, including but not limited to loss of profits, use, data or other
economic advantage. If there shall, notwithstanding the above provisions, at any
time be or arise any liability on the part of AMD by virtue of this agreement and/
or the materials furnished by AMD to you, you agree that in no event will the total
aggregate liability of AMD for any claims, losses, or damages exceed $5,000. The
foregoing limitation of liability is complete and exclusive, shall apply even if AMD
has been advised of the possibility of claims, losses, or damages exceeding such
limit, and shall apply regardless of the success or effectiveness of any other
remedies possessed by you or third parties. This limitation of liability reflects an
allocation of risk between AMD and you in view of the fact that AMD has not
charged you for the materials or their use.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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about.book Page 2 Monday, June 7, 1999 10:17 AM
PLD (U13) Equations
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“ U13 PLD code for the Am186CC CDP Development Module Revision 2.1
“
“ An AMD PLCC-28 PAL22V10 provides glue logic needed between the Am186CC and the“
“ PCNETISAII ethernet controller and ISDN devices.
“
“
“
“ Written: Oct. 1998
“ For : Advanced Micro Devices - Austin EPD
“ By : LDB - System Engineering
“ Revision 00
10/98
Original Code
“
11/98
Added DTMF data buffer direction support
“
01/99
Added more defined data buffer control
“
“
“
“
“
“
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
“
Declarations
“
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
INPUT
clkout;
“PIN 2: Am186CC CLKOUT
INPUT
/master;
“PIN 3: Am79C961A active low MASTER# output
INPUT
resout;
“PIN 4: Am186CC Active High Reset output
INPUT
/brd;
“PIN 6: Am186CC or Am79C961A Active low RD# signal
INPUT
/bwr;
“PIN 10: Am186CC or Am79C961A Active low WR#
“signal
INPUT
hlda;
“PIN 7: Am186CC Active high Hold Acknowledge
INPUT
/pio38;
“PIN 11: Am186CC Active low PIO38
INPUT
sclk;
“PIN 12: Am186CC SSI Clock
INPUT
/pcs1;
“PIN 13: Am186CC Active low PCS1# output
INPUT
/pcs2;
“PIN 16: Am186CC Active low PCS2# output
INPUT
/pcs4;
“PIN 5: Am186CC active low chip select
INPUT
/pcs5;
“PIN 9: Am186CC active low chip select
INPUT
/main;
“PIN 20: Selects location of packet SRAM (main or
“module)
BIPUT
BIPUT
BIPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
/bhe ENABLED_BY /master;
/sbhe ENABLED_BY /master;
/sramcs ENABLED_BY master;
/reset;
/bhlda;
bsclk ENABLED_BY pio38;
/dbufdir;
/dbufg
“PIN 21: Am186CC Active low BHE# output
“PIN 18: Am79C961A Active low SBHE# output
“PIN 24: Packet SRAM Chip Select
“PIN 27: Active low RESET used for the U transceiver
“PIN 23: Active low DACK# used for the Am79C961A
“PIN 19: SSI clock used for the U transceiver
“PIN 17: Active low direction control for the buffers
“PIN 25: Active low Gate enable for data buffer
NODE
/dbhe CLOCKED_BY clkout;
“Internal node used to delay SBHE# by a 1/2 clock
(
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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PLD (U13) Equations (continued)
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
Equations
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
reset
= resout;
“Inverted RESOUT driven to a 5V level for the
“T7256A (U transceiver)
bhlda
= hlda + master;
“Inverted Am186CC HLDA to the Am79C961A
“DACK# that is latched to the end of the cycle
bsclk
= sclk;
“SCLK is transmitted to T7256 U transceiver only
“when PIO38 is LOW
dbufg
= [pcs1 + pcs2 + pcs4 + pcs5]
+ [master * sramcs * main]
+[/master * sramcs * /main];
“Data buffer is enabled only when data is being
“transferred between the CDP main and module
dbufdir
= [master * bwr]
+ /master * brd;
“PCNETISA has bus:Point DATA buffer toward
“main on writes. Am186CC has bus: Point DATA
“buffer toward main on reads
sramcs
= 1;
“SRAMCS is three-state when Am186CC has the
bus “and active when Am79C961A has the bus
bhe
= sbhe;
“BHE# is three-stated when the Am186CC is
“master and the Am79C961A SBHE# output when
“it is master
sbhe
= bhe + dbhe;
“SBHE# is the Am186CC BHE# extended by 1/2
“clock to remain active after the deassertion of RD#
“or WR# to adhere to the ISA spec.
dbhe
= bhe;
“Internal node used to delay BHE# by 1/2
“CLKOUT
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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about.book Page 4 Monday, June 7, 1999 10:17 AM
PLD (U20) Equations (SBP/PCM Mode)
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“ U20 PLD code for the Am186CC CDP Development Module Revision 2.1
“
“ An AMD PLCC-28 PAL22V10 provides synchronization of clocks between the Am79C031 DSLAC “
“ and the Am79C32A when running in SBP/PCM mode.
“ Written:
“
Feb. 1999
“
“
For :
Advanced Micro Devices - Austin EPD
“
“
By :
LDB - System Engineering
“
“
“
“ Revision 00
2/99
Original Code
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
Declarations
“
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
INPUT
mclk_c32;
“PIN 2: Am79C32A 12.288 MHz MCLK output
INPUT
bclk_c32;
“PIN 3: Am79C32A BCLK output
INPUT
resout;
“PIN 4: Am186CC Active High Reset output
INPUT
pclk_c32
“PIN 5: CLKA output from the Am79C32A
OUTPUT
mclk4;
“PIN 18: 4.096 MHz Am79C031 MCLK input
OUTPUT
pclk;
“PIN 25: modified BCLK signal
(
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PLD (U20) Equations (continued)
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
“
Equations
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
STATE_MACHINE divider CLOCKED_BY mclk_c32 RESET_BY resout;
“ This state machine generates 4.096MHz clock signal for the DSLAC.
STATE one:
mclk4=0;
goto two;
STATE two:
mclk4=0;
goto three;
STATE three:
mclk4=1;
goto one;
END divider;
STATE_MACHINE DPLL CLOCKED_BY mclk_c32 RESET_BY resout;
“ Jitter reduction circuit, implemented as free running up-counter, that counts 15, 16 or 17
“ clock cycles to form a window. The entire circuit can be viewed as a DPLL
STATE one:
pclk=1;
“ set the PCLK output to one
goto two;
“ on the next rising edge of the CLK signal go to the next
“state !
STATE two:
pclk=1;
goto three;
STATE three:
pclk=1;
goto four;
STATE four:
pclk=1;
goto five;
STATE five:
pclk=1;
goto six;
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PLD (U20) Equations (continued)
STATE six:
pclk=1;
goto seven;
STATE seven:
pclk=1;
goto eight;
STATE eight:
pclk=1;
goto nine;
STATE nine:
pclk=1;
goto ten;
STATE ten:
pclk=1;
goto eleven;
STATE eleven:
pclk=1;
goto twelve;
STATE twelve:
pclk=1;
goto thirteen;
STATE thirteen:
pclk=1;
goto fourteen;
STATE fourteen:
pclk=1;
goto fifteen;
STATE fifteen:
pclk=1;
goto sixteen;
STATE sixteen:
pclk=1;
goto seventeen;
(
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PLD (U20) Equations (continued)
STATE seventeen:
pclk=0;
goto eighteen;
STATE eighteen:
pclk=0;
goto nineteen;
STATE nineteen:
pclk=0;
goto twenty;
STATE twenty:
pclk=0;
goto twentyone;
STATE twentyone:
pclk=0;
goto twentytwo;
STATE twentytwo:
pclk=0;
goto twentythree;
STATE twentythree:
pclk=0;
goto twentyfour;
STATE twentyfour:
pclk=0;
goto twentyfive;
STATE twentyfive:
pclk=0;
goto twentysix;
STATE twentysix:
pclk=0;
goto twentyseven;
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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PLD (U20) Equations (continued)
STATE twentyseven:
pclk=0;
goto twentyeight;
STATE twentyeight:
pclk=0;
goto twentynine;
STATE twentynine:
pclk=0;
goto thirty;
STATE thirty:
pclk=0;
goto thirtyone;
STATE thirtyone:
pclk=0;
goto thirtytwo;
STATE thirtytwo:
pclk=0;
goto thirtythree;
STATE thirtythree:
pclk=0;
goto thirtyfour;
STATE thirtyfour:
pclk=0;
goto thirtyfive;
STATE thirtyfive:
pclk=0;
goto thirtysix;
STATE thirtysix:
pclk=0;
goto thirtyseven;
(
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PLD (U20) Equations (continued)
STATE thirtyseven:
pclk=0;
goto thirtyeight;
STATE thirtyeight:
pclk=0;
goto thirtynine;
STATE thirtynine:
pclk=0;
goto forty;
STATE forty:
pclk=0;
goto fortyone;
STATE fortyone:
pclk=0;
goto fortytwo;
STATE fortytwo:
pclk=0;
goto fortythree;
STATE fortythree:
pclk=0;
goto fortyfour;
STATE fortyfour:
pclk=0;
goto fortyfive;
STATE fortyfive:
pclk=0;
goto fortysix;
STATE fortysix:
pclk=0;
goto fortyseven;
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PLD (U20) Equations (continued)
STATE fortyseven:
pclk=0;
goto fortyeight;
STATE fortyeight:
pclk=0;
goto fortynine;
STATE fortynine:
pclk=0;
goto fifty;
STATE fifty:
pclk=0;
goto fiftyone;
STATE fiftyone:
pclk=0;
goto fiftytwo;
STATE fiftytwo:
pclk=0;
goto fiftythree;
STATE fiftythree:
pclk=0;
goto fiftyfour;
STATE fiftyfour:
pclk=0;
goto fiftyfive;
STATE fiftyfive:
pclk=0;
goto fiftysix;
STATE fiftysix:
pclk=0;
goto fiftyseven;
(
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PLD (U20) Equations (continued)
STATE fiftyseven:
pclk=0;
goto fiftyeight;
STATE fiftyeight:
pclk=0;
goto fiftynine;
STATE fiftynine:
pclk=0;
goto sixty;
STATE sixty:
pclk=0;
goto sixtyone;
STATE sixtyone:
pclk=0;
goto sixtytwo;
STATE sixtytwo:
pclk=0;
goto sixtythree;
“ States 63 to 65 form a window to catch the PCLK signal
STATE sixtythree:
“ max. frequency
IF pclk_c32=1 THEN
pclk=0;
goto sixtyfour;
ELSE
pclk=1;
goto one;
“ return to state one if BCLK is high
END IF;
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PLD (U20) Equations (continued)
STATE sixtyfour:
“ If the DPLL is synchronized, the state machine is reset to state one in this stage.
IF pclk_c32=1 THEN
pclk=0;
goto sixtyfive;
ELSE
pclk=1;
goto one;
END IF;
STATE sixtyfive:
“ min. frequency
“ forces reset to state one
IF bclk_c32=1 THEN
pclk=0;
ELSE
pclk=1;
END IF;
goto one;
“ force reset to stage one
END DPLL;
(
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PLD (20) Equations (IOM-2/GCI Mode)
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“ U20 PLD code for the Am186CC CDP Development Module Revision 2.1
“
“ An AMD PLCC-28 PAL22V10 provides clock synchronization between the Am79C031 DSLAC “
“ and the Am79C32A when running in IOM-2/GCI mode
“ Written:
“
Feb. 1999
“
“
For :
Advanced Micro Devices - Austin EPD
“
“
By :
LDB - System Engineering
“
“
“
“ Revision 00
2/99
Original Code
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
Declarations
“
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
INPUT
mclk_c32;
“PIN 2: Am79C32A 12.288 MHz MCLK output
INPUT
bclk_c32;
“PIN 3: Am79C32A BCLK output
INPUT
resout;
“PIN 4: Am186CC Active High Reset output
INPUT
pclk_c32
“PIN 5: CLKA output from the Am79C32A
OUTPUT
mclk4;
“PIN 18: 4.096 MHz Am79C031 MCLK input
OUTPUT
pclk;
“PIN 25: modified BCLK signal
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
“
Equations
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
STATE_MACHINE divider CLOCKED_BY mclk_c32 RESET_BY resout;
“ This state machine generates 4.096MHz clock signal for the DSLAC.
STATE one:
mclk4=0;
goto two;
STATE two:
mclk4=0;
goto three;
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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PLD (20) Equations (Continued)
STATE three:
mclk4=1;
goto one;
END divider;
STATE_MACHINE DPLL CLOCKED_BY mclk_c32 RESET_BY resout;
“ Jitter reduction circuit, implemented as free running up-counter, that counts 15, 16 or 17
“ clock cycles to form a window. The entire circuit can be viewed as a DPLL
STATE one:
pclk=1;
“ set the PCLK output to one
goto two;
“ on the next rising edge of the CLK signal go to the next
“state !
STATE two:
pclk=1;
goto three;
STATE three:
pclk=1;
goto four;
STATE four:
pclk=1;
goto five;
STATE five:
pclk=1;
goto six;
STATE six:
pclk=1;
goto seven;
STATE seven:
pclk=0;
goto eight;
STATE eight:
pclk=0;
goto nine;
(
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PLD (20) Equations (Continued)
STATE nine:
pclk=0;
goto ten;
STATE ten:
pclk=0;
goto eleven;
STATE eleven:
pclk=0;
goto twelve;
STATE twelve:
pclk=0;
goto thirteen;
STATE thirteen:
pclk=0;
goto fourteen;
STATE fourteen:
pclk=0;
goto fifteen;
“ States 15 to 17 form a window to catch the BCLK signal.
STATE fifteen:
“ max. frequency
IF bclk_c32=1 THEN
pclk=0;
goto sixteen;
ELSE
pclk=1;
goto one;
“ return to state one if BCLK is high
END IF;
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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PLD (20) Equations (Continued)
STATE sixteen:
“If the DPLL is synchronized, the state machine is reset to state one in this stage.
IF bclk_c32=1 THEN
pclk=0;
goto seventeen;
ELSE
pclk=1;
goto one;
“ return to state one if BCLK is high
END IF;
STATE seventeen:
“min. frequency
“forces reset to state one
IF bclk_c32=1 THEN
pclk=0;
ELSE
pclk=1;
goto one;
END IF;
goto one;
“force reset to stage one
END DPLL;
(
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PLD (U24) Equations
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“ U24 PLD code for the Am186CC CDP Development Module Revision 2.1
“
“
“
“ An AMD PLCC-28 PAL22V10 provides glue logic needed for the POTS interface
“
“
“
“ Written:
Oct. 1998
“
“
For :
Advanced Micro Devices - Austin EPD
“
“
By :
LDB - System Engineering
“
“
“
“ Revision 00
10/98
Original Code
“
“
02/99
Removed SLIC RING-IN Ctrl
“
01
“
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
Declarations
“
““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
INPUT
/pcs4;
“PIN 9: Am186CC active low PCS4# output
INPUT
/pcs5;
“PIN 10: Am186CC active low PCS5# output
INPUT
cctxda;
“PIN 6: Am186CC HDLC channel A transmit data output
INPUT
dstsc;
“PIN 5: Am79C031 active low time slot control output
INPUT
txdd;
“PIN 11: Am186CC HDLC channel D transmit data output
INPUT
/tscd;
“PIN 7: Am186CC active low time slot control output
OUTPUT
dtmf2oe;
“PIN 24: Output enable for the DTMF for POTs channel 2
OUTPUT
dtmf1oe;
“PIN 23: Output enable for the DTMF for POTs channel 2
OUTPUT
txda ENABLED_BY dstsc;
“PIN 17: Am186CC TXDA controlled by DSLAC timeslot
“control
OUTPUT
rxda ENABLED_BY tscd;
“PIN 18: Am186CC TXDD controlled by Am186CC
“timeslot control
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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PLD (U24) Equations (continued)
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
“
Equations
“
“““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““
dtmf2oe = pcs5;
“Inverted pcs5# to create active high output enable for
“the DTMF on POTS channel 2
dtmf1oe = pcs4;
“Inverted pcs4# to create active high output enable for
“the DTMF on POTS channel 1
txda
= cctxda;
“Equals the Am186CC TXDA output when the DSLAC
“is NOT transmitting on the PCM bus. This is needed
“in case the HDLC TSA’s are configured in muxed mode
“and a POTS line is needed. The Am186CC TXDA
“output will be three-stated when the POTS interface is
“transmitting
rxda
= txdd;
“Equals the Am186CC TXDD output when PCM
“channel D is transmitting. This is used if the Am186CC
“is required to transmit data directly to the DSLAC.
(
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Index
Numerics
10BaseT Ethernet, 3-7
A
AD bus, 2-48
Am186CC/CH/CU CDP
about, xiii
connecting to a PC via serial port, 1-2
connecting to a PC via USB port, 1-5
description, xiii
development module, 3-1
development module block diagram, xvi,
3-2
development module BOM, D-1
development module layout, 3-3
documentation, xix
documentation conventions, xx
features, xvii
ID, 2-45
jumper settings, 2-4
main board, 2-1, 2-8
main board block diagram, xv, 2-2
main board BOM, C-1
overview, xiii
pin usage, B-1
PLD equations, E-1
population options, 2-45
quick start, 1-1
suggested reference material, xx
theory of operation, xvii
troubleshooting, 1-8
Am186CC/CH/CU microcontroller, xvii
block diagram, 2-9, 2-10
clocking, 2-11, 2-48
description, 2-8
power supply, 2-10
reset, 2-14
Am79C32A DSC circuit, 3-18
B
bill of materials
development module, D-1
main board, C-1
block diagram
Am186CC communications controller,
2-9
Am186CH HDLC microcontroller, 2-10
Am186CU USB microcontroller, 2-10
CDP main board, xv, 2-2
CDP main board layout, 2-3
development module, xvi, 3-2
main board, xv, 2-2
board. See main board or development
module.
BOM. See bill of materials.
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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about.book Page 2 Monday, June 7, 1999 10:17 AM
C
CDP. See Am186CC/CH/CU CDP.
chip select
jumper settings, 2-4
pin usage, B-10
clocks
Am186CC/CU/CU microcontrollers,
2-11
clock options, 2-11
CodeKit software, iii
communication interface
overview, 2-27
peripheral USB port, 2-37
RS-232 serial ports, 2-27
RS-530 DCE/PCM HDLC ports, 2-30
configuration circuitry, 2-39
CPU. See Am186CC/CH/CU
microcontroller.
CPU/PLL circuitry, 2-47
CR4–CR6, 3-12
D
DCE, 2-31
multidrop mode, 2-37
debug and configuration circuitry, 2-39
debug circuitry, 2-44
debug headers, 2-42
development module
10BaseT Ethernet, 3-7
block diagram, 3-2
BOM, D-1
connecting to main board, 1-5
connector layout, 3-6
DSLAC PCM interface, 3-18
DTMF interface, 3-25
expansion interface, 2-51
features, 3-4
functional description, 3-1
,QGH[
interface to main board, 3-4
ISDN interface, 3-12
layout diagram, 3-3
LEDs, 3-9, 3-12
main board interface, 3-5
PCnet-ISA II, 3-9
POTS interface, 3-18
power estimates, 2-19
RSLIC interface, 3-24
documentation
conventions, xx
manual contents, xix
suggested reference material, xx
support, iii
DRAM
main memory DRAM circuit, 2-21
DSLAC device
circuitry, 3-19
PCM interface, 3-18
DTMF interface, 3-25
E
E86MON utility
invoking, 1-4
Ethernet
10BaseT, 3-7
PCnet-ISA II, 3-9
expansion interfaces
Am186, 2-49
development module, 2-51
F
features
Am186CC/CH/CU CDP, xvii
development module, xviii, 3-4
main board, xvii, 2-8
Flash memory
boot width, 2-48
data bus width, 2-6
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about.book Page 3 Monday, June 7, 1999 10:17 AM
jumper settings, 2-4
on CDP, 2-22
G
getting started, 1-1
GP1–GP6, 2-6
ground post, 2-6
H
HDLC
circuit, 2-30
clocking, 2-36
jumper settings, 2-4
ports on controller, 2-30
help, iii
High-Speed UART jumper settings, 2-4
I
installation
main board, 1-2
quick start, 1-1
troubleshooting, 1-8
interface
Am186, 2-49
development module, 2-51
DSLAC, 3-18
DTMF, 3-25
expansion, 2-49
HDLC, 2-30
LNB, 3-26
memory, 2-20
RSLIC, 3-24
S/T, 3-13
serial, 2-27
TIP, 2-39
U, 3-15
USB, 2-37
interrupts
pin usage, B-11
ISDN, 3-12
S/T interface, 3-13
U interface, 3-15
J
JP1, 2-4, 2-36
JP10, 2-4
JP11, 2-4
JP12, 2-5
JP2, 2-4, 2-36
JP3, 2-4
JP4, 2-4, 2-36
JP5, 2-4
JP6, 2-4, 2-36
JP7, 2-4
JP8, 2-4
JP9, 2-4
jumpers
default settings, A-1
on main board, 2-4
L
layout
development module, 3-3
main board, 2-2
main board diagram, 2-3
LED
U interface status, 3-16
literature support, iii
LNB interface, 3-26
logic analyzer jumper settings, 2-4
$PŒ&&&+&80LFURFRQWUROOHU&'38VHU¶V0DQXDO
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about.book Page 4 Monday, June 7, 1999 10:17 AM
M
main board
block diagram, xv, 2-2
BOM, C-1
communication interface, 2-27
connecting a TIP, 1-6
connecting to a ROM-ICE, 1-7
connecting to the development module,
1-5
debug and configuration, 2-39
debug headers, 2-42
development module interface, 2-51, 3-5
expansion interface, 2-49
features, 2-8
Flash memory, 2-22
functional description, 2-1
jumper settings, 2-4
layout, 2-2
layout diagram, 2-3
main memory, 2-20
memory configuration, 2-23
memory interfaces, 2-20
microcontroller, 2-8
peripheral USB port, 2-37
pinstrap configuration, 2-46
power estimates, 2-18
power supply, 2-15
reset configuration, 2-45
RS-232 serial ports, 2-27
RS-530 DCE/PCM HDLC ports, 2-30
SRAM, 2-20
TIP, 2-39
MCLK, 3-21
memory
configuration overview, 2-23
DRAM, 2-20
Flash, 2-22
interface, 2-20
,QGH[
main, 2-20
SRAM, 2-20
microcontroller. See Am186CC/CH/CU
microcontroller.
N
notational conventions, xx
P
panic bit, 2-45
PC
connecting board to via serial port, 1-2
connecting board to via USB port, 1-5
PCLK, 3-21
PCM mode, 2-33
PCnet-ISA II, 3-9
pin usage, B-1
pinstrap
configuration, 2-46
miscellaneous, 2-49
PIO
jumper settings, 2-5
pin usage, B-1
PLD equations, E-1
POTS interface
DSLAC PCM interface, 3-18
DTMF interface, 3-25
LNB interface, 3-26
overview, 3-18
RSLIC interface, 3-24
power supply
-24 V @ 50 mA, 2-17
3.3 V @ 500 mA, 2-16
-5 V @ 200 mA, 2-16
5 V @ 3 A, 2-15
-70 V @ 60 mA, 2-17
main board, 2-15
microcontroller, 2-10
power estimates, 2-18
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Q
quick start, 1-1
R
R530
DCE clocking, 2-32
PCM clocking, 2-33
reference material, xx
RESCON, 2-45
reset
Am186CC communications controller,
2-14
configuration, 2-45
main board, 2-45
switch, 2-5, 2-46
RJ-45 connector, 3-8
ROM-ICE
configuration, 1-7
connecting to the main board, 1-7
device selection, 2-24
jumper settings, 2-4
RS-232 serial ports
on main board, 2-27
using to connect to PC, 1-2
RS-530 DCE/PCM HDLC ports, 2-30
RSLIC interface, 3-24
S
SW11, 2-6
SW12, 2-6, 2-32, 2-33
SW13, 2-6, 2-45
SW14, 2-6
SW15, 2-6, 2-45
SW16, 2-6
SW3, 2-5
SW4, 2-5
SW5, 2-5
SW6, 2-5
SW7, 2-5
SW8, 2-5, 2-32
SW9, 2-5, 2-32, 2-33
switches
default settings, A-1
on main board, 2-4
system clock modes, 2-47
T
T7256A device, 3-17
T7256A U transceiver, 3-18
technical support, iii
test point, 2-7
third-party support, iii
TIP
connecting to the main board, 1-6
interface, 2-39
TP1-TP3, 2-7
troubleshooting
installation, 1-8
S/T interface, 3-13
S/T IOM-2, 3-20
S/T SBP mode, 3-20
serial port. See RS-232 serial ports.
SRAM jumper settings, 2-4
support, iii
SW1, 2-5
SW10, 2-5
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about.book Page 6 Monday, June 7, 1999 10:17 AM
U
U interface, 3-15
LED status, 3-16
U20, 3-20
UART jumper settings, 2-4
UART. See RS-232 serial ports.
USB
circuit, 2-38
clock, 2-13
clock modes, 2-47
clocking, 2-48
external transceiver, 2-48
peripheral USB port, 2-37
pinstrap select, 2-6
using to connect to PC, 1-5
W
WWW support, iii
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