1541Ultimate-II "ultimate Audio"

1541Ultimate-II "ultimate Audio"
Ultimate Audio
Register API
Gideon Zweijtzer
All work Copyright © 2012 by
Gideon’s Logic Architectures
All rights reserved.
Version 0.2, October 26th 2012
Ultimate Audio
Register API
Table of Contents
1. Introduction ............................................................................................................................................. 3
1.1. Context................................................................................................................................................................................... 3
1.2. Features ................................................................................................................................................................................ 3
1.3. Purpose of this document .............................................................................................................................................. 3
2. Registers .................................................................................................................................................... 4
2.1. Overview............................................................................................................................................................................... 4
2.2. Register Read ...................................................................................................................................................................... 4
2.3. Register Write .................................................................................................................................................................... 4
2.4. The Audio Channel ........................................................................................................................................................... 4
2.4.1. Control register..............................................................................................................................................................................................................5
2.4.2. Volume register .............................................................................................................................................................................................................5
2.4.3. Pan register .....................................................................................................................................................................................................................5
2.4.4. Sample start address register .................................................................................................................................................................................6
2.4.5. Sample length register ...............................................................................................................................................................................................6
2.4.6. Sample rate register ....................................................................................................................................................................................................6
2.4.7. Sample repeat point registers ................................................................................................................................................................................7
2.4.8. Interrupt clear register ..............................................................................................................................................................................................7
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Ultimate Audio
Register API
1. Introduction
1.1. Context
The ‘Ultimate Audio’ feature is a new feature for the 1541 Ultimate-II module. It implements multichannel audio sample playback support from REU memory, and is an exciting addition to the
possibilities this cartridge offers.
1.2. Features
‘Ultimate Audio’ offers you the following features:







7 independent channels
8 or 16 bit audio sample playback
sample rate up to 48 kHz
volume control per channel
panning control per channel
“a-b” looping
interrupt generation
1.3. Purpose of this document
The ‘Ultimate Audio’ feature is accessible from the cartridge I/O range. In this manual, the
programming API is described.
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Ultimate Audio
Register API
2. Registers
2.1. Overview
The functional block is mapped into C64 I/O space, at the address $DF20 up to $DFFF. Mapping this
block into the I/O space is optional, and needs to be turned on in the ‘C64 and cartridge settings’ menu.
Obviously, the I/O space is only mapped, when the selected cartridge emulation allows this, just like
the REU registers. Note that the REU registers reside at $DF00-$DF1F, when enabled.
Note, that for the ‘Ultimate Audio’ feature to generate output on the stereo-jack, the audio output
selection should be set correctly as well. These settings can be found in the ‘Audio settings’ menu. Left
Channel Output should be set to “Sampler Left”, and Right Channel Output accordingly to “Sampler
Right”.
2.2. Register Read
Functional registers are write-only, just like the SID. Reading the I/O space will yield the interrupt
status register or module version (as of writing: V1.0).
Address
$DF20
$DF21
Read Data
Interrupt Status register
‘Ultimate Audio’ version register
Default
$00
$10
2.3. Register Write
Each of the 7 audio channels occupies 32 consecutive bytes of I/O space:
Channel
0
1
2
3
4
5
6
Channel Base Address
$DF20
$DF40
$DF60
$DF80
$DFA0
$DFC0
$DFE0
2.4. The Audio Channel
The (write only) registers of the audio channel are mapped as follows:
Offset
$00
$01
$02
$04–$07
$09-$0B
$0E–$0F
$11–$13
$15–$17
$1F
Register
Control
Volume
Pan
Sample Start Address
Sample Length
Sample Rate
Repeat point A
Repeat point B
Interrupt clear
Version 0.2, October 26th 2012
Default
$00
$3F
$07
$01.00.00.00
$01.00.00
283 ($01.1B)
$00.80.00
$00.C0.00
$00
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Ultimate Audio
Register API
The multi-byte fields are in big endian format. This means that the high byte comes first, and the
low(er) bytes follow. This is unlike 16-bit pointers found in the 6502; as they are little endian. Since
the interface is 8-bit only, there will be no issue. Each byte gets loaded separately.
2.4.1. Control register
The control register contains the following bits:
Bit 7
Bit 6
Interleave
Bit 5
Bit 4
Mode
Bit 3
–
Bit 2
Interrupt
Bit 1
Repeat
Bit 0
Gate
The gate and repeat bit determine how the sample is played. In simple mode (repeat = 0), the sample
starts playing from the beginning when the user sets the ‘gate’ bit to 1. The sample will then play until
the end, or until the user clears the gate bit. Thus, when repeat is off, the sample stops playing
immediately when the user sets ‘gate’ to 0.
In repeat mode (repeat = 1), the sample starts to play from the beginning when the user sets the ‘gate’
bit. When the sample reaches repeat point B, and the gate bit is still set, it reverts to point A. When the
user clears the ‘gate’ bit, repeat point B is ignored and the sample plays until the end. This behavior is
very much like the ADSR behavior of the SID chip, where the release phase starts when ‘gate’ gets
cleared.
The interrupt bit determines whether an IRQ is generated when the end of sample is reached. Each
channel has its own interrupt status bit in the interrupt status register.
The mode bits determine the format of the sample data in memory. From the four possible modes, two
are currently defined:
Mode
00
01
10
11
Description
8-bit PCM
16-bit PCM (little endian)
reserved
reserved
The interleave bit can be used to skip ‘odd’ samples. This is useful when a stereo sample is stored in
REU memory. When this bit is set, the channel skips the data that is meant for the other channel. A
second channel can be programmed such that it exactly reads the samples in between.
2.4.2. Volume register
The volume register controls the output volume of each channel. The register takes values from 0 to
63. Low volumes might generate some noise. This issue still has to be investigated further.
2.4.3. Pan register
The pan register controls where the channel is audible in the stereo image. A value of 7 or 8 put the
channel right in the middle. A value of 0 makes the channel appear completely on the left speaker,
while a value of 15 makes it sound on the right side.
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Ultimate Audio
Register API
2.4.4. Sample start address register
This 4-byte register holds the start address of the sample. The upper address byte should always be
$01 for the sampler to read data from REU memory. This register in fact holds the address of the
SDRAM memory of the Ultimate-II and the base address of the REU memory is $1 00 00 00. Note that
this register is big endian; the most significant byte comes first.
2.4.5. Sample length register
The length of the sample (in bytes) is written into this register. The maximum length of a sample can
be 16M, the complete REU memory. Note that the length comparison takes place between each sample
read from memory. This means that when you play 16 bit samples, the length should be a multiple of 2,
otherwise the end condition is never met and the sample will play forever, including a lot of garbage.
2.4.6. Sample rate register
The sample rate register is actually a divider register. The sample rate is derived from a 6.25 MHz
reference. The following table shows some common sample rates and corresponding divider settings:
Sample rate (Hz)
8000
11025
16000
22050
32000
44100
48000
Divider
781
567
391
281
195
142
130
The sample rate register can be safely updated while the sample is playing in order to create all kinds
of effects, like modulation.
When an instrument is played, the sample register is used to determine the note. The following
example table shows the values to be used when the middle ‘A’ (440 Hz) of an instrument is sampled
at 32kHz for various notes, and the error.
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Ultimate Audio
Note
A2
A#2
B2
C3
C#3
D3
D#3
E3
F3
F#3
G3
G#3
A3
A#3
B3
C4
C#4
D4
D#4
E4
F4
F#4
G4
G#4
A4
Divider
391
369
348
328
310
293
276
261
246
232
219
207
195
184
174
164
155
146
138
130
123
116
110
103
98
Register API
Frequency
219.8
232.9
246.9
262.0
277.2
293.3
311.4
329.3
349.3
370.4
392.4
415.2
440.7
467.1
493.9
524.0
554.4
588.6
622.7
661.1
698.7
740.8
781.3
834.3
876.9
Error
-0.1%
-0.1%
0.0%
0.1%
0.0%
-0.1%
0.1%
-0.1%
0.0%
0.1%
0.1%
0.0%
0.2%
0.2%
0.0%
0.1%
0.0%
0.2%
0.1%
0.3%
0.0%
0.1%
-0.3%
0.4%
-0.4%
2.4.7. Sample repeat point registers
The repeat point registers hold the positions in the sample that are used in repeat mode. Point A is the
sample point to which the sequencer returns when reaching point B, as long as both the ‘repeat’ bit
and the ‘gate’ bit are set in the control register.
Repeat = 1 & gate = 1
0
A
B
length
2.4.8. Interrupt clear register
The interrupt clear register is used to clear the IRQ condition of the channel. The IRQ can be set when
the sample reaches its end. Writing a ‘1’ to bit 0 of this register clears the IRQ of this channel. Writing
$FF to this register clears the IRQ of all channels.
Version 0.2, October 26th 2012
7
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