dec.pdp-6.PDP-6_Hardware_Maintainence_.1965.102630365.pdf

dec.pdp-6.PDP-6_Hardware_Maintainence_.1965.102630365.pdf
F-67
(166)
ARITHMETIC PROCESSOR
166
INSTRUCTION MANUAL
VOLUME
DIGITAL
EQUIPMENT
CORPORATION
l
MAYNARD,
MASSACHUSETTS
1
F-67(166)
PDP-6
ARITHMETIC
PROCESSOR
INSTRUCTION
MANUAL
VOLUME
DIGITAL
EQUIPMENT
CORPORATION
1
.
MAYNARD,
MASSACHUSETTS
166
PREFACE This instruction
manual
maintenance
of the Arithmetic
output
devices:
Printer
Type 626,
Maintenance
to those portions
chapters
the system.
present
a general
specifications
Chapter
2 provides
explaining
what
functions.
a general
panels
The next five
Drawing
chapters
Conventions
and Flow Charts,
and terminology
used in the logic
through
charts
the flow
the processor,
units
in the logic
group
describe
drawings
the final
two describe
included
in the last chapter
is strongly
manual
advised
without
first
the processor
are the control
not to embark
gaining
9 contains
information
tenance
operation,
maintenance
useful
charts.
that
with
units
understand
involved
in
formats
used
on the oper-
logic.
Chapter
the flow
appear
and arithmetic
bus and the in-out
of the material
including
and corrective
in this
processing;
bus = Also
devices.
The reader
PDP-6
presented
in
hardware
The next two chapters
in this or any other
the reader
of operations
as coherent
in-out
4,
the symbols
also escorts
chapter
the system,
of the
diagram
and describes
and logical
the memory
1
procedures.
This chapter
charts.
and preventive
Chapter
and indicators
common
in maintaining
. ..
III
hardware
for four
understanding
programs,
for the devices
of the system
neither
sequence
upon any logic
a thorough
Chapter
basic operating
from the flow
interfaces
devices
at the block
PDP-6 documentation
and flow
for the main control
Keyboard-
system and instruction
description
some sequences
nor are obvious
the hardware
the number
so that he may better
in detail
input-
characteristics
the circuit
the use of all controls
discusses
Teletype
manuals
and electrical
describing
detailed
drawings
in sequence,
and discusses
than
and outlines
a complete,
PDP-6
for the in-out
of system organization
3 explains
devices,
present
the physical
also describes
Chapter
and in-out
separate
and
of the system and its operation.
description
the system does rather
in the Type 166 Processor.
ator control
description
and describes
This chapter
information
of DEC manufacture;
with
operation
166 and four of the more common
Type 461.
lists the operating
the various
in the
and Card Reader
are furnished
level,
Type
to aid personnel
Paper Tape Punch Type 761,
themselves
system.
Processor
volumes
Type 760,
primarily
three
in two
Paper Tape Reader
is confined
The first
is published
system
in Chapter
a discussion
maintenance.
4.
of main-
Following
convenient
all other
Chapter
tables.
figures
9 are appendixes
AlI
logic
are interleaved
drawings
with
on engineering
and flow
the text.
iv
drawings
charts
referred
and spares,
a glossary,
to in the text
and several
are in Volume
2;
FOREWORD PDP-6
digital
is a general-purpose,
input-output
devices,
computing
each of which
may share memories
system consisting
has independent
and input-output
internal
of processors,
timing.
the memories
equipment;
memories,
Processors
themselves
and
in a system
may have different
speeds.
A central
operations
and governs
The Type
the Type
any number
out bus.
buses permit
The memory
the processor
request,
supplies
the addressed
system,
processors,
the memory
memory
complex
module.
an address and requests
memory
times
performs
memory
a number
its own cycle
devices.
each
restricted
uses two busses for
to its input-output
each with
a memory
to accommodate
In order
and logic
and peripheral
processor
the other
a memory
arithmetic
of programs,
The central
time.
of central
may address a single
between
allows
one to the memory
A system may contain
tion,
system that
to share processor
intercommunication,
Processor,
of information
an executive
area in core,
as many as four
166 Arithmetic
the movement
166 includes
to a definite
system
usually
processor,
cycle.
and furnishes
bus and an in-
several
to deposit
devices.
processors-
or retrieve
informa-
Upon accepting
the appropriate
the
response
to
the processor.
Through
the in-out
A priority
equipment.
service
so that
memory
interrupt
the processor
may be connected
direct
bus the processor
system
access for high-speed
devices
bus connection
connected
to the memory
system via
which
it may govern
processor
must provide
pendently,
so large
without
initial
blocks
reducing
of information
processor
allows
an autonomous
such as drums,
its own memory
up to three
transfers
time.
One
discs,
magnetic
control
which
units.
between
it needs
tape,
Although
and displays.
is itself
scats
:$)-out
the central
then operates
an in-out
that
supplies
the drum processor
the drum processor
may be transferred
when
of the Ifnits
bus, and has its own smaller
and commands,
V
to signal
drum processor
processor,
input-output
efficiency.
to and from the peripheral
a device
input-output
to the central
conditions
central
information
the actual
to the bus is the Type 167,
to its in-out
memory
all
in the processor
is free during
In addition
bus through
controls
device
indeand a
All
PDP-6
memories
store words of 36 bits but may be of different
ories usual I y have core banks of 8192 or 16,384
writing
back
shorter:
until
into memory
when
data
reading,
format
ory for an operand,
16 accumulators
in-out
allows
or in both.
In-out
bus, the transfer
addition
equipment,
to addressing
dress one of 128 devices,
For further
which
information
also describes
out devices,
system,
in-out
others
location
two of which
and still
devices.
others
A separate
manual
all
circuits
used in the memories.
with
the core stack,
the appropriate
of status
information
time
is much
writing,
psec,
only
is normally
refer
and writing
system manuals.
Vi
and one of
in an accumulator,
in both
interrupt
directions
channel
assignments,
from that equipment.
that
magnetic
circuit
In
may aditself.
(DEC publication
for the processor
Processor
and several
maintenance
described
tape,
and describes
circuits,
in-
memory
DECtape,
in the present
This
common
may be used in a PDP-6
tape equipment,
K-06),
and most in-out
by a series of manuals.
of specialized
on magnetic
instruction
Programming
is provided
in
over the
system and the processor
166 Arithmetic
Descriptions
address,
in mem-
interrupt
to PDP-6
discusses
locations
an in-out
all those used in the equipment
reading
l/2
and
register,
types of memories
including
ciated
priority
are the priority
for the Type
circuits
logic
of data
including
for the system
standard
when
less than
may be stored
the transfer
the drum equipment,
circuit
time
and discusses programming
the several
treat
is available;
the memory
results
and an index
system,
documentation
cover
govern
and the gathering
one discusses system maintenance
access
for modifying
information,
system software
data
case access
to address one of 262,144
Instruction
on the overall
Maintenance
devices.
registers
instructions
a memory
with
instructions
operand.
of control
until
in each
from
in core.
the basic
one of 15 index
times for reading
although
only
memory,
16 locations
for a second
to the peripheral
need wait
A fast flip-flop
of the bottom
The instruction
2 and 5 psec,
the processor
is accepted.
used instead
memory,
are typically
Cycle
words.
Core mem-
sizes and speeds.
and other
most
manual
and
such as those asso-
and the like,
are included
in
CONTENTS
Page
Chapter
1
1 .l
Operating
1.2
Physical
1.3
Electrical
2
2.1 2.2 Specifications
Characteristics
Characteristics
SYSTEM FUNCTION
Programming
-
b
Instruction
c
Program
b
Instruction
c
Executive
2.5
Input-Output
3
3.1 3.2 OPERATION
2-l 2-3 2-4 2-6
Format ..................................
2-8 .....................................
Logic
Control
2-l 0 2-l 0 ...................................
Execution
System
2-l 1 ...............................
2-14 ..................................
......................................... Interface
2-15 2-l 8 ........................................ System
...................................... 2-l 9 3-l ................................................. Control
Panels
a
Control
b
Bay Indicator
c
In-Out
Operation
1-5 ...........................................
Console
Memory
l-3 .................................. Flags
a
2.4
................................... System ....................................
Sequence
Arithmetic
l-2
.............................................
Number
2.3
..................................
..........................................
a
Main
l-l
.............................................
INTRODUCTION
3-l ...........................................
Operator
Panel
Panels
and Marginal
of In-Out
a
-
Tape Reader
b
Tape Punch
c
Teletype
d
Card
Check
Equipment
Panel
...................
.............................
......................................
.......................................
...................................... vii 3-2 3-10 ...............................
Keyboard-Printer
Reader
............................
..........................
3-13 3-l 8 3-l 8
3-19 3-20 3-23 C 0 N TE N T S (continued)
Paae
Chapter Processor
3.3 4
Operating
b
Operating
Keys
...................................
3-28 c
Emergency
Stop
...................................
3-31 CONVENTIONS
Logic
4.2
Signa I Notation
4.3
Instruction
4.4
Flow Charts
4.5
Execute
Drawings
Console
5.2 Processor
FLOW
...................................... ..............................................
Cycle
Flow
....................................... CONTROL
Control
............. .... .................
.......................................... Cyc les ..........................................
........................................
b
Address
c
Fetch
d
Execute
e
Store .............................................
5.4
Program
5.5
Executive
ARITHMETIC
Memory
................. .......................................... Instruction
Instruction
CHARTS
........................................... a
5.3
6.1
AND
Decod ing
SEQUENCE
5.1
6
3-27 Read In ..........................................
DRAWING
MAIN
3-27 .............................
a
4.1
5
Procedures
...........................................
............................................
..........................................
Control
........................................ 4-l 4-2 4-8 4-l 0 4-13 4-15 5-1 5-l 5-4 5-5 5-6 5-7 5-9 5-12 5-13 .......................................... 5-l 8 Logic
.......................................... 5-20 LOGIC
.......................................... 6-l Control
Buffer
............................................ ...
VIII 6-2 C 0 N TE N T S (continued)
Page
Chapter
6.2
Arithmetic
Register
Addition
c
AR Control
d
AR Subroutines
e
AR Flags ..........................................
.................................
Algorithm
Arithmetic
Shift
....................................
Register
6-15
6-17
..............................
..................................
Counting
6-9
6-12
........................................
6.4
6-18
6-20
a_
SC Gating
........................................
6-20
b
SC Control
........................................
6-22
c
SC Subroutines
6.5
Subroutine
6.6
Data
Interface
Subroutine
Block
b
Character
c
Shift
Arithmetic
....................................
Transfer
................................
.....................................
Operations
Operations
Instructions
...............................
...................................
.....................................
6-26
6-27
6-31
6-32
6-32
Fixed
b
Floating
Scale .....................................
6-33
c
Floating
Add-Subtract
6-34
d
Floating
Multiply
MEMORY
Subroutines
Exponent
LOGIC
Memory
....................................
6-25
z
Arithmetic
Multiply
6-23
6-24
.......................................
Instructions
a
a
7.1
6-6
b
- Quotient
7
........................................
AR Gating
Multiplier
6.8
6-5
a
6.3
6.7
........................................
..............................
and Divide
........................
.....................................
Co lculate
................................
6-36
6-36
7-1
.............................................
Address
6-35
Logic
.....................................
7-l
a
MA Register
.......................................
7-2
b
MA Control
.......................................
7-3
c
User Mode
Registers
................................
ix
7-5
C 0 N TE N T S (continued)
Page
Chapter 7.2
Memory
Data
7.3
Memory
Control
8
In-Out
8.2 Priority
Control
a
Priority
b
PI Control
I/O
8.4
I/O Interface
8.5 Standard
7-7 8-l .................................... ..........................................
Interrupt
Processor
9.1 ...........................................
Transfer
8.3
9
7-6 .......................................
.............................................. INPUT/OUTPUT
8.1
Logic
8-1 8-3 Chain I .....................................
8-4 . . . .....................................
8-5 Control
..................................... .......................................
Logic
In-Out
Equipment
................................
8-8 8-l 2 a
Paper Tape Reader
b
Paper Tape Punch ..................................
8-14 c
Keyboard-Printer
8-l 6 d
Card
MAINTENANCE
Operation
.................................
8-7 ..................................
Reader .......................................
8-l 9 ............................................. 9-l for Maintenance
a
Power Controls
b
Marginal
c
Maintenance
d
Single
9.2
Maintenance
9.3 Preventive
8-l 2 ................................
....................................
Check
Controls
Switches
Step Operation
...........................
9-3 9-3 9-4 ..............................
9-5 ..............................
9-7 Programs
.................................... 9-8 Maintenance
...................................
9-9 a
Schedules
and Margins
b
Arithmetic
Processor
c
In-Out
Equipment
.............................
PM ............................
PM ..............................
X
9-l 0 9-l 1 9-14 C 0 N TE N T S (continued)
Page
Chapter Corrective
9.4 Maintenance
a
Troubleshooting
b
Repair
5
Validation
. . . . . . ..e..........................
9-24 . . . . ..*............................
9-25 . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
and
Log Entry
...........................
9-29 9-31 Appendix
DRAWINGS
1
ENGINEERING
2
SPARES
3
GLOSSARY
4
INSTRUCTION
5
TELETYPE CODE
6
CARD
Al-l ...................................
A2-1 ......................................................
..................................................
........................................
CODES
READER
.............................................. 1
A4-
1
A54 .......................................... CODE
A3-
A&
ILLUSTRATIONS
Figure
Arithmetic
Processor 3-l
Conbole
Operator
3-2
Bay
3-3
In-out
and
Marginal
3-4
Paper
Tape
Reader
3-5
Paper
Tape
Punch
3-6
Keyboard-Printer
3-7
Card
4-l
Logic
9-l
Processor
9-2
Paper
Indicator
Type
Panel
Panels
Reader
Type
Symbols
..................................
l-4 ........................................ 3-3 ........................................... 3-3 Check
3-14 Type
Panel
760
............................... 3-19 .................................... Type
761
..................................... 3-20 Type
626
..................................... 3-22 461
. . . . . . . . . . . ..*........................... 3-25 . . . . . . .. . ..
Marginal
Tape
166
Dimensions
Check
..................
F low
.......................
................... ..........
. . .. . .. . .. .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
4-4 9-12 9-16 1
CHAPTER
1
INTRODUCTION
The Type 166 is a general-purpose
executive,
and internal
transfers
data
of data between
provide
control
output
system.
Except
for certain
cessor resides
instruction
a number
sides operating
The only
each restricted
on a stored
flags,
although
conditions
must retrieve
contain
the registers
single
instruction.
the bottom
structions
another
used for address modification
The accumulators,
16 memory
have three
locations
addresses
accumulator),
may use multiple-level
cent accumulators
cessor is capable
manipulation
indirect
of performing
of a character
Boolean
logical
and arithmetic
priority
functions,
to standard
interrupt
system
select
a full-word
shift
comparisons,
instruction
through
for memory
during
operations,
as index
actual
registers,
a memory
Thus
processing
or half-word
size.
both
transfer,
The processor
fixed-
of modification
the hardware
an external
l-1
device
also
includes
or an internal
(which
inmay be
instructions
to call
two adjathe pro-
transfer,
or the
hardware
for per-
arithmetic,
jumps,
and testing
a
occupy
instruction,
includes
and floating-point
within
All
address
a block
and
Most basic
location
a single
Be-
instruction,
actually
address modification.
With
allows
time.
for every
in a fast memory.
operands.
and a variety
which
from one
of an instruction.
end some may use a single
of variable
operations,
double
contained
double-length
(byte)
only
an accumulator,
register
addressing
for processing
forming
In addition
and are usually
and an index
of the pro-
are the same as those used for computations
15 of which
which
the state
all operands
the arithmetic
information
to the input-
to share computer
are stored at the completion
in the processor
the other
pro-
for a user mode which
and al I data and results of computations
registers
cases it may
over by the processor
area in core,
the processor
all
to an in-out
in the processor,
carried
logical,
It also controls
in many
and information
to a definite
program,
system.
to memory,
information
count,
all of the arithmetic,
and initial
held permanently
is the program
of programs,
equipment,
one for connection
information
in memory.
to the next
performs
in a PDP-6
system commands
two bus interfaces,
entirely
that
operations
and peripheral
by supplying
control
processor
transmission
memory
merely
It contains
cessor.
central
instructions.
a program-assignable
condition
can interrupt
the normal
program
facilitate
sequence;
double-precision
an executive
routine
a number
arithmetic;
timing
except
metic
register
processor
Word
has the following
protection
of various
and relocation
and al I processing
such as carry
functions,
and
that allow
memory
is done
addresses.
in parallel
in the main arith-
Information
handled
by the
characteristics:
36 bits
Format
Instruction
code, 9 bits
Accumulator
address, 4 bits
Indirect,
1 bit
Index register address, 4 bits
Memory address,
18 bits
Input-Output Instruction
code, 6 bits
Device code, 7 bits
Indirect,
1 bit
Index register address, 4 bits
Memory address, 18 bits
Number
Neaative
Number
registers
propagation
Basic Internal
conditions
SPECIFICATIONS
asynchronous,
that relocate
checking
in core to each user program.
Length Instruction
Binary
System Representation 2’s complement
Format
Fixed
Point Floating
the completely
register
Sign,
Point The time required
metic
fast serial
and in dc adders
area
OPERATING
in the Type 166 is completely
for a few extremely
that allow
and memory
to assign a specific
1.1
All
of flags
or a sequence
magnitude,
Sign, 1 bit; exponent,
fraction,
27 bits
for execution
asynchronous
1 bit;
of any particular
operation.
of shifts
instruction
The basic operations,
controlled
by the shift
l-2
varies
35 bits
8 bits;
tremendously
such as addition
counter,
because
of
in the arith-
are performed
by built-in
hardware
subroutines.
These are called
sequence
or by special
sequences
subtract,
divide,
at the level
addition
which
etc.,
of individual
or subtraction
100 nanoseconds
Similarly
additions
and subtractions
on a larger
amount
and the time
be determined
compared
from the flow
cessor must first check
memory
and retrieval
is free;
included
for memory
protection
the time required
Exact
in Chapter
and relocation
for access once
by a series of
upon the
control
functions
involved
of operands
instruction
take
execution
and then wait
the memory
of carries
depends
For each memory
4.
each require
sequence
and storage
access time.
addition
are performed
Most processor
subsequences.
Even
in the basic
upon the number
for such a major
add-
sequence.
and the parital
depends
instruction
floating
for example
and division
required
to memory
charts
is serial,
multiplication
scale,
and setup of instructions,
of time when
function
transfer,
instruction
time may vary;
which
from the main
block
from the main
the complement
propagation,
either
manipulation,
the execution
of times it must cal I various
in the retrieval
necessary
are in turn entered
subroutine,
needed.
number
such as byte
events,
but carry
whenever
times may
access,
until
is free depends
a negligible
the pro-
the addressed
upon the type of
memory.
The processor
equipment;
when
must set up all
transfers
but since a device
it requires
equipment
service,
can operate
2.5 microseconds.
of control
can signal
no processor
in parallel.
The four I/O
information
the processor
time
over the I/O
included
to and from the peripheral
by means of the priority
need be lost in waiting,
Every transfer
devices
and data
and processor
bus does,
in this manual
interrupt
have
however,
the following
system
and peripheral
require
operating
specifications.
Paper Tape Reader
400
Paper Tape Punch
63.3
Keyboard-Printer
10 8-bit
Card Reader
200
1.2
Most
DEC equipment
processor
with
accommodate
is housed
its console
up to twelve
PHYSICAL
in steel
bays with
by 5-l/4
characters
8-bit
characters
characters
800column
per second
per second
per second
cards per minute
CHARACTERISTICS
aluminum
uses four such bays bolted
19 inch
8-bit
together.
inch. panels
l-3
control
panels.
The front
lettered
The arithmetic
of each bay can
A to N from top to bottom
(skipping
G and I).
indicator
panel
panels
mounted
in modules
is mounted
behind
double
doors.
panel
console
for the standard
can hold
up to eight
the remainder
the double
required
logic
power
and power
cover
panels,
Arithmetic
Usually,
Processor
check
tape
punch
door,
Type 166
on which
at the
fan-folded
and an indi-
the control
panel
the console
table
are used for the arithmetic
for some of the in-out
plenum
a tape reader
controls
The space below
plug-
of bays 3
for removing
space above
panels.
l-4
and a paper
has an opening
equipment.
logic
up to 25 DEC system
panel.
panel
have an
standard
control
The remaining
bay is an inner
control
can hold
are the marginal
logic
by eleven
each
At the center
two of which
the control
logic,
from the front.
the punch
or other
of each
panel
the control
equipment.
mounting
may be used to hold
supplies
a metal
displays,
doors at the back
operator
containing
in-out
may be used for DECtapes,
viewed
bay just above
At the top of bay 4 behind
panel
when
is the main
of the drawer
of the processor
of the bay occupied
Each mounting
from left to right
in the left
house the bulk
the remainder
hold the console,
top (the front
cator
at the top with
numbered
and 4, which
tape).
Bays 1 and 2, which
processor;
equipment.
are mounted
Inside
the
Physical
dimensions
Arithmetic
are as follows:
Processor
Height
69-l/2
inches
Width
100 inches
Depth
60 inches
(75 inches
with
rear plenum
doors
open)
1300 pounds
Weight
Teletype
Keyboard-Printer,
Model
38-l /2
Width
20 inches
Depth
24 inches
Weight
151 pounds
Burroughs
Width
48 inches
Depth
29 inches
Weight
200 pounds
fans at the bottom
to lOOoF.
magnetic
imately
described
However,
of every
150 pounds
bay cool
in this manual
PDP-6 equipment
All
power
cables
per square
30 amperes.
together
The arithmetic
modules
by blowing
in an ambient
temperature
The floor
temperature
sensitive
should
air out between
range
equipment
be capable
them.
from 50’
such as
of supporting
approx-
foot.
ELECTRICAL
uses standard
use Hubbell
includes
is required.
1.3
All
the logic
can operate
if the installation
air conditioning
tape,
and punch
8122
50 inches
All equipment
reader
inches
Height
Intake
tape
35 KSR
Height
Card Reader,
including
line
Twist-Lok
processor,
use two I ines and two power
CHARACTERISTICS
power
at 105 to 125 vat,
connectors;
console
both
l-5
and connector
and console-mounted
The main
controls.
cable
60 cycles,
power
control
standard
single
phase.
are rated
in-out
is usually
at
equipment
a Type 829
or Type 835;
it provides
control
mounted
logic
ac to all of the power
below
are +lO and -15 volts.
voltage.
trol
Some power
drivers
for in-out
For the punch,
punch)
that allows
-15 volt
signal
the processor
is applied
trols
(usually
logic
others
volt
for the reader,
equipment.
application
controls
This last dc turnon
bus; instead
it is included
in a small
also carries
iable
supply
Current
consumption
located
of the equipment
signal
signal
marginal
check
described
console
in this manual
and
Keyboard-Printer 2.6 amperes,
Turnon surge,
140 watts
7 amperes
Card
1.5 amperes,
Turnon surge,
145 watts
7 amperes
Reader exclusively.
Pulse amplitude
- 3.5
widths
state;
transistors
are 0 to - .3 volts
almost
volts.
logic
to -3.5
level
Pulses are of either
volts
Pulses at inverter
Occasionally,
outputs
or 400;
operate
volts).
with
depending
tolerances
an input
40,
input.
voltages
may be triggered
l-6
logic
Another
con-
from a var-
levels
modules
PDP-6
upon gate
by a level
logic
an internal
uses pulse timing
requirements.
volts
or vice
depending
of 0 and - 3 vdc
include
input
to +3.0
to - 3 volts
or 25 nanoseconds
pulse.
logic
of +2.3
may be from ground
70,
on static
Most
from the -15 volt
polarity
from ground
may be 1 microsecond
and application.
and diodes
and -2.5
the negative
is 2.5
power.
on the
25 amperes,
1900 watts
Turnon surge, 40 amperes
65 watts
9 amperes
to derive
directly
is as follows:
1.85 amperes,
Turnon surge,
supply
con-
is not sent via the memory
Tape Punch (tolerances
power
turns on the power
150 watts
2.8 amperes
is solid
- 30 volts
and keyboard-
motor
1.8 amperes,
Turnon surge,
logic
to provide
(mounted
Tape Reader PDP-6
the negative
in the console.
Arithmetic
Processor, including
console-mounted
in-out logic
All
by the logic
Type 811 or 834) via the in-out
-15 volt
in the memories.
bus that
only
punch,
of punch
(usually
Still another
required
in series
a Type 823 Power Control
power
and any in-out
I ine turns on a secondary
Type 836)
power
provide
may be connected
to control
to external
bus to turn on the peripheral
both,
ac to the motors
logic
The dc voltages
panel.
One -15
ac is fed through
for the processor
provide
supplies
equipment.
(Type 811 or 834) that provides
printer.
operator
supplies
two -15 volt
In some cases,
to solenoid
the console
supplies
and -2.3
versa.
Pulse
upon module
transition
to
instead
type
of a
CHAPTER
SYSTEM
The logical
blocks
configuration
equipment
and the memory;
control
(each
connection
buses is a block
represented
have
those that
have
9 bits;
govern
the requesting
system.
The figure
for each
register
transfers’
metic
between
through
logical
extension
AR,
of signal
of data
have
memory
notation
and arithmetic
memory
operations
the operand
of AR for handling
performs
locations
as counted
sequence
by changing
words
it
in AR,
usually
the result
double-length
a program
the address
counter
in PC.
registers
floating-point
but all
registers
interrupt
control
pulses
of signal
names,
buffer
between
all data
MB.
All
processor
transfers
and peripheral
with
the system
in via AR and a register
of memory
part
a passive
handle
These are arith-
may communicate
MB takes
appearing
which
role
in all data
transfers,
by holding
in AR.
MQ serves
but in
an operand
primarily
which
as an
operands.
by executing
by the program
Data
have 8; 7-bit
operations.
transfers
information
plays
the name
the priority
registers
and memory
MB,
via MB.
them
both
For an explanation
full-size
the operator
for sending
with
the
4.
MQ,
At the console,
among
handle
the processor,
and
Between
in size.
through
and arithmetic
through
transfers
is labeled
breaks
block.
is a set of three
are made
required).
that
Large
both data
and relocation
lines within
logical
with
2-l.
to the input-output
buses,
lines
Registers
protection
in Chapter
all
to these
considerably
18.
sequence
register
switches
vary
in Figure
the processor
Each block
the corresponding
processor
via AR.
connect
all registers,
blocks.
of program
are performed
for displaying
The processor
control
beside
and memory
a register
with
showing
addresses
166 is shown
of physical
1The registers
multiplier-quotient
are made
is combined
that
are written
processor
indicators
only
Type
connections
the number
does not show the control
and in which
equipment
of bits.
and granting
of the arithmetic
register
with
the register
handle
those
to the discussion
The heart
shows all
of the processor
and the number
36 bits,
Processor
the buses that
the figure
by I ines connecting
exponents
refer
represent
is labeled
diagram
of the register
FUNCTION
of the Arithmetic
at the top and bottom
2
instructions
PC, although
To gain
2-l
access
retrieved
from consecutive
the program
to memory
may change
for retrieval
memory
its own
or storage,
the processor
requests
address
register
system
receives
word
addresses
further
the actual
which
from memory
for the execution
registers
arithmetic,
of basic
results
Besides
the registers
the processor
contains
two registers
for memory
all
instructions
directly
compared
with
defines
outside
area by adding
The priority
processor
which
All
to memory
the contents
a constant
interrupt
to interrupt
sequence
interrupt
When
restricted
are written
allows
are allowed
for memory
register
to the program
register
storage
FE.
of preliminary
peripheral
devices
sequence.
on a priority
The first
register
allows
the program
to turn
chronizes
break
requests
to internal
processor
access,
PR.
timing
2-2
channels
in core,
the address
The number
and certain
in MA
conditions
on and off;
and assigns the break
any
the assigned
in MA.
internal
interrupt
is
in this register
it from addressing
by three
of pro-
but these are not
RLR to the address
basis as governed
mode,
a number
to one within
and certain
contains
is in executive
addresses
changed
register
The first
area
There are seven
individual
and its instructions,
In user mode,
and prevents
is then
in the relocation
program
operations,
by the repetition
the processor
to a specific
protection
The address
contained
operations
in floating-
system.
using the lower
In requests
available
performed
of the program
each program
the normal
breaks
for whatever
for temporary
to the program.
area.
system
execution
and a priority
of the memory
its assigned
MQ,
of the exponent
are available
programs
address,
of the operation.
and relocation.
from MA.
the size of the block
location
FE is used only
system
protection
time with
and sometimes
of any operation
the regular
an executive
are illegal.
supplied
registers.
to govern
register.
such as the calculation
the count
a
IR which
operand
SC and the floating-exponent
into
and al I memory
grams share processor
instructions
enter
is decoded
in MB is the memory
counter
I ing the remainder
that
register
by the shift
and it also controls
SC is control
and which
the
When
In some of the more complicated
computations
main
half
MB,
on the console.
passes to the instruction
of an index
to AR,
in that
of the instruction.
are aided
steps in the three
while
The right
the bus from memory
to the operator
register
and accumulators,
iI; AR by the contents
SC is used for subsidiary
point
registers
half
over
link
switch
its left
of the instruction.
are brought
these full-size
also serves as a control
of index
may be modified
an address
via MA from the address
retrieval
are necessary
and supplies
at MB as an instruction,
execution
The operands
cycle
This register
MA.
is retrieved
controls
a memory
to the
channels
control
through
registers.
the second
to the highest
syn-
priority
channel
that
ruption
by lower
priority
particular
vices
memory
is entirely
channel
taining
channels.
location
under
or give
a channel
has been recognized;
a device
control;
itse If.
of flags
that
information
information
Timing
with
is initiated
operator
processor
struction.
which
a lower
the point
directly
is supplied
transfer
subroutine
memory
access.
and provides
levels
in turn
16 locations
locations.
Their
control,
contained
but only
address
tion
but they
in memory
particular
calls
differ
specifies
contained
All
no indexing.
half
which
and relocation
to perform
When
for each
hardware
of higher
rank.
need
sequence
in-
Thus
calling
not be at
calls
arithmetic
the
subroutines-
stops upon
the restart
the necessary
associated
sequence.
is repeated
the main
Processor
for events
built-in
from it (although
transfer,
chains.
each sequence
sequences;
are determined
16 locations
Since
the main
sequences-
as accumulators,
1 to 17 may be addressed
in the right
may also
the block
and obtain
PROGRAMMING
from the remainder
in a fast memory.
locations
return
others
function
functions
into
timing
or by any sequence
in a block
2.1
The first
entry
of other
of nested
upon
pulse
that supplies
by the main sequence
For example,
which
conthe flags
protection
by asynchronous
by the main sequence
and restarts
of departure).
interface
the processor
supply memory
key cycle
uses a hierarchy
using many
sequence
or
may assign
the sequence;
this interface,
to de-
to a single
the program
has an I/O
to interrupt
Through
is supplied
at the console
timing
operates
ranked
conditions
DATA switches
in the processor
Th e main sequence
the processor
to which
in a
of channels
devices
inter-
system.
intervention
can be called
may assign several
the processor
further
the instruction
The assignment
One of the devices
by means of a special
is running,
and prevents
by performing
channel.
the program
by the program.
to the executive
for all operations
operation
each
internal
in from the console
holds the break
is executed
For this purpose
allow
may be sensed and controlled
bring
with
no assignment.
is the processor
a number
A break
associated
program
the third
entirely
of the memory
registers,
as index
system
registers
memory
register
only
2-3
because
addresses
is actually
or ordinary
by the processor
under
in that
may be used as accumulators
ordinary
of an index
index
program
they are usually
or ordinary
a zero
are 18 bits,
memory
index
only
used for address
memory,
register
the informa-
modification.
In systems
that
include
hold a readin
loader)
initiated
from the console;
only
it again
becomes
programmed
be wary
with
inaccessible
operators,
contained
convenience
4-l
the Type
point
left
and floating
to right.
floating
bits
point
l-35
166 number
bits
l-8
represent
Number
the assumed
position
point
to facilitate
i.e.,
changing
is inconvenient
for all
is completely
in PDP-6
familiar
Programming
available
to the program,
registers.
instructions.
of handling
36-bit
the sign,
word;
For
The remainder
format,
and flags.
numbers
in two formats,
represent
interpreted
or as an integer
with
the binary
in multiplication
0 to 35 from
point
with
and division
point,
the binary
to the right
hardware
In
In fixed
fraction
on the processor
the fixed-point
fixed
1 for negative.
a fraction.
as a full
has no effect
However,
bits are numbered
0 for positive,
bits 9-35
of a number
is usually
for a machine
If x is an n-digit
is precisely
binary
equivalent
to ones and al I ones to zeros.
2-4
formed
so hardware
is (2” - 1) - x or equivalently
from all ones)
all zeros
should
of bit 35.
and a program
does include
because
may
special
these opera-
numbers.
the negative
its l’s complement
programmer
and control
instruction
is usually
hand1 ing of integers
arithmetic,
from 2n - 1 (i.e.,
use the full
of the point
make use of double-length
This notation
is capable
convention.
this area,
System
an exponent,
which
area can be
40 and 41 are used for
the reader
flags,
codes
system,
0 represents
sign and magnitude
by l’s and 2’s complements.
and
bit
magnitude,
any consistent
In ordinary
sign.
Both formats
normally
from outside
system-a
in detail
locations,
and octal
the hardware
numbers,
represent
between
provisions
tions
point.
In all
point,
Of course,
adopt
computations
locations
in terms of elements
memory
a
For arithmetic
are described
lists the mnemonic
describes
taken
interrupt
assume that
the instructions
on accumulators,
in the reading
has been
In all systems
(which
purposes.
all of which
describes
effect
Table
of this section
an instruction
in this manual
instructions,
That manual
by their
and once
for other
16 core locations
operations
operations-
42 to 57 are used by the priority
descriptions
(K-06).
the first
processor
to the program.
locations
the processor
i.e.,
for normal
of using these
The logic
it replaces
a fast memory,
number,
merely
arithmetic
by changing
represents
its 2’s complement
(2” - x) - 1.
to performing
Therefore,
Subtracting
the logical
the
negatives
is 2n - x
a number
complement,
to form the l’s complement,
the processor
complement-usually
uses the logical
to form the 2’s complement
In l’s complement
zeros
instead
possible
fact
notation,
changes
adding
read a negative
to the zeros
ment
number
ones may be discarded
at the right;
form because
the rightmost
numbers .
in normal
as long as only
it still
166,
In a positive
binary
complement
sidered
one of the positive
than
the-magnitude
from 02~~
of the magnitude
of the largest
a 27-bit
For a positive
fraction.
are now interpreted
as an integral
exponent
by the binary
represented
in exactly
below),
in excess
but since
fraction
it has the l’s complement
128 code,
an actual
point:
exponent
is 0 and bits
positive
including
l-35
represent
magnitude
of the word
contains
positive
as containing
and floating
Since
number
0 is conis one less
thus have a range
an 8-bit
exponent
but the contents
of bits
exponents
l-8
from -128
of bits
are interpreted
to +127 are
zero and negatives
containing
and
all
are
zeros,
a
thus has 1 for its sign and the 2’s complement
a 1 unless the entire
code
x is represented
2-5
in 2’s comple-
fixed
number.
zero by a word
must contain
of the exponent
may be
if a portion
for both
Floating-point
of 0 to 255.
The negative
every
negatives
and the contents
i.e.,
In a
is now a l’s complement.
is 0, as before;
code,
the same way as fixed
by the 2’s complement.
of the fraction,
fraction
zeros
remains
However
A
end in 0.
fraction,
the number
of the largest
word
significance
characteristics.
is 1 and the remainder
the sign
128 (2008)
equivalents
one can
Fixed-point
integers
- 35
is -1 to 1 - 2
.
a computer
number,
notation,
number.
the range
as a binary
in excess
represented
negative
negative
interprets
only
the sign
the magnitude
to 235 - 1; for fractions,
hardware
the sign bit
of the corresponding
numbers,
The floating-point
9-35
number,
bit and in
and negative
In a negative
part of the fraction
is not
1 and attaching
possesses significance.
In a negative,
the 2’s
positive
is used to represent
fixed-point
fashion.
both
to the
the final
has the following
are discarded,
the remaining
the 2’s complement
system
numbers
zeros
interpretation
at least
to the rightmost
at the left.
has a 1 which
1 is discarded,
in the Type
even
changes
significance
Thus in 2’s complement
significance
All
as the complement-and
by attaching
this simple
complement
A 2’s complement
-1.
number
notation,
propagates.
by attaching
ones represents
integer,
discarded
one to the logical
to the left of it.
all
negative
For 2’s complement
bits as far as the carry
to merely
and adds one to the result.
one can read a negative
of the ones.
because
number
it complements
referred
in bits
l-8.
in a positive
number
Since
number
is 0 (see
the exponent
by x + 128,
is
in
a negative
number
by 127 - x.
representations
because
tion
the exponent
that
factor
scales
in standard
The program,
the hardware
compensates
without
2’s complement
however,
affecting
need
not concern
automatically
.
the fraction,
form but produces
itself
For example,
the hardware
the correct
with
these
for the instruc-
interprets
l’s complement
the scale
result
for the
exponent.
In al I floating-point
and always
normalizes
if the magnitude
is thus that
being
equal.
required
Floating-point
and an exponent
bit
0 and all
changes
range
zeros
it to -l/2
correct
result
fraction
with
operations
result.
for the special
thus have a fractional
of -128
to +127.
if the program
point,
high-order
part
part
assignment
1.
The test for
4000000008,
bits 9 and 0 are
- 27
from l/2 to l-2
part
-1 (i.e.,
but the hardware
The hardware
is not normalized
require
that discarding
in correct
the programmer
to 2’s complement
but the input-output
that
multiplication
instructions
additional
because
a 1 in
always
may not give
or that
may request
the
has a zero
form
in floating-point
double-length
results.
part of a double-length
form only
rounding,
precautions
these have
the low-order
2’s complement
b
All
in which
fractional
to be normalized
contain
in magnitude
the signed
appropriately.
notation
fractional
must remember
In floating
that
an operand
of 2’s complement
the high-order
-l/2,
the test for normalization
the exponent
supplies
and less than
from bit 9 or bits 9-35
range
are normalized
exponent.
and fixed-point
The programmer
satisfies
Note
operands
are considered
to l/2
case of the fraction
numbers
nonzero
numbers
than or equal
the sign bit differs
in bits 9-35)
a nonzero
assumes that all
Floating-point
is greater
either
and adjusts
The characteristics
leaves
a nonzero
of the fraction
normalization
the latter
the hardware
operations,
which
if the low-order
automatically
negative
part
is null.
restores
the
if it is negative.
Instruction
and programmed
Format
operators
use a basic
format
as fol lows:
O-8
Instruction
9-12
Accumulator
13
Indirect
14-17
X
Index
18-35
Y
Memory
2-6
code
address
bit
register
address
address
with
bit
Bits O-8 determine
each address
which
the first
On some occasions,
for example
of I, X,
Y to produce
address
is indirect
even when
I is 0.
structions;
(designated
instead
X (zero
X specifies
word.
another
by three
word.
or control
ones in bits O-2) have
10-12
Instruction
13
I
Indirect
14-17
X
Index
18-35
Y
Memory
device
I, X,
and the priority
bits
system
lo-12
a word
is
instructions
address.
bit assignment:
code
code
bit
register
address
address
specify
are considered
E, which
until
if I is
one of eight
devices.
is used as an address
IOT
in-
As in the
in some cases,
in others.
operator
in the program,
is designated
manner
register
half,
by three
the processor
in the usual
in the right
128,
interrupt
and Y are used to calculate
information
word
out of a possible
in exactly
of a memory
the following
to
if I is 1, this
address
out for all
instead
Device
are added
is processed
continues
and Y is carried
information
on the values
address;
the effective
The process
I, X,
an accumulator,
no indexing)
3-9
an I/O
depends
The new word
X and Y are used to determine
registers.
of addressing
is used as the effective
another
using
and index
E of an instruction
111
tents of the instruction
is usually
purposes
o-2
A programmed
address
i.e.,
Bits 9-l 2 and 14- 17
serve as accumulators
address
register
This calculation
the processor
format,
instruction
of index
E is to be used as an operand
Bits 3-9 address
appears
The effective
If I is 0, this address
as above,
for the instruction.
which
and is used to retrieve
instructions
as control
locations
they are used to retrieve
in which
basic
are executed
are used for control
flags.
an address.
0; otherwise,
IOT
bits 9-12
The contents
the same manner
found
16 memory
to address
and Y.
operations
calculates
in bits O-2.
an effective
but it does no further
in the left
half
and then executes
a JSR to an appropriate
zeros
of location
the instruction
subroutine).
2-7
Whenever
address
decoding;
such an operator
from bits
instead
it stores
40 and the calculated
contained
13-35
in location
of the
the con-
effective
41 (which
c
The processor
contains
set automatically,
flags
that allow
Some flags
I/O
e.g.,
a priority
rupt system
AR CRYO,
primarily
usually
specific
by iump
by IOT
does so on the channel
AR CRY1 These flags
be both
flag
listed
to the processor
in the processor
as being
provided
whereas,
set and cleared.
but most are contained
are set by carries
ENABLE able
to cause
the priority
of instructions.
flag
PDL OV
inter-
ENABLE
flag
is set when
is set and triggers
instruction
enable
flag
in a variety
an incorrect
of the processor
the program
Setting
interrupt
to perform
a
if the enable
sequence
PC CHG
is changed
causes a priority
has been set by the program.
a priority
interrupt
has gone outside
is set and triggers
control.
flag has been
2-8
a priority
to a memory
fl ag is set every
power
and in
when
a pushdown
of the core area assigned
I ist.
fai Is to respond
the main
in AR.
set by the program.
The flag
The clock
operations
OV causes a priority
if the enable
system
CLOCK
or failure
interrupt
This flag
arithmetic
a loss of information,
by a skip or iump instruction.
to the pushdown
bits
has overflowed.
It indicates
Setting
has been
or pullout
EXIST MEM for double-precision
of a computation,
The PC change
ENABLE
that
from the corresponding
flag may be set by arithmetic
computation.
PC CHG
primarily
a result
The overflow
result
CLOCK
be set by the program;
can always
Any
assigned
Flags that are
is active.
AROV NON
operations
instructions.
correcting
PC CHG
cannot
instructions
They are useful
AROV
Flags
that may be sensed by the program.
conditions,
to enable
and are governed
interrupt
of flags
by error
the program
are governed
interface
a number
Program
sixtieth
interrupt
when
the memory
request.
of a second
It causes a priority
set by the program.
by a signal
interrupt
if the
from
As a flag,
USER tive
the sole function
routine
whether
priority
interrupt
priority
interrupts)
(instructions
The execution
UUO
or the trapping
control
to the program.
service
a block
control
automatically
of the interrupt,
Some subroutine-calling
bits”
in the left
subroutine,
iump
the program
in the miscellaneous
ulation
instructions
necessary
location.
increments
receives
load or deposit
the
and upon
must be restarted,
the program
flags,
the bits to their
overflow,
of its
interrupt.
to the location
or to the location
from a priority
a character
require
interrupt.
two main
pointer;
the second
operates
on the byte.
occurs
between
the program
not reincrement
the two parts,
bit ensures
the pointer.
2-9
The first
may determine
the stored
original
PC change,
them.
will
either
the IOT.
outside
from the
states.
user,
Included
and a control
The four byte manipsequences
part
for their
fetches
If the program
and,
if
jumps to
bit 4 is set in the PC store
whether
that
as “miscellaneous
In returning
count.
between
the return,
after
a priority
to in the logic
can occur
Then in the subroutine,
is to
USER stays set and
to use the address
interrupt
that
it transfers
to address a location
is referred
restores
case for returning
for an interrupt
was interrupted;
which
that
and a priority
a subroutine
that
bits are the two carry
is used in a special
execution,
store what
may use a jump that
bit that
of a user pro-
to the user program
PC may point
on user
of an interrupt
causing
a
USER.
the restrictions
is no overflow,
tried
and any
this instruction.
instructions
half of the location
which
clears
the operation
in core sets this flag
of the instruction
following
reverts
are a JRST
or following
must set USER when
by a user program
At the time
a PI cycle
If the sole purpose
all
instruction
the computer,
instruction
to restrict
IOT and there
area
or halt
by a
must service
a user program
USER implements
routine
either
of an illegal
during
of an illegal
the executive
An attempt
routine
of a JSR during
Thus in order
restricted
(the executive
an interrupt
flip-flop,
to the execu-
was interrupted,
or by the trapping
IOT).
programs.
OP or UUO
to dismiss
As a control
ILLEG
a user program
that are illegal
that attempts
gram,
of USER is to indicate
a character
the interrupted
operation
instruction,
2.2
This section
is devoted
an instruction
entry
into
sharing
primarily
and sequences
with
control
level
over
the processor
output
complete
contact
Operation;
in particular
upon
associated
flip-flop
with
RUN-the
rent main
sequence.
most keys that
key functions
I iminary
switches;
Control
is exercised
through
or gates
that
that
which
controls
system
are control
levels
specific
processor
specific
with
inputs
that
allow
the
events.
or initiate
sequences
for events
associated
with
the way
is described
in which
associated
may provide
events
of all keys and switches
the console
Normal
keys consists
processor
the processor
events
data
The keys
although
the
the key action.
in detail
the keys affect
or by the
The
in Chapter
processor
such as transferring
but for those
functions
that
instruction
program,
the initiating
sequence,
3,
operation,
the main
another.
and a
sequence
sequence
Whenever
to
RUN
ceases at the end of the cur-
the computer
keys trigger
the key cycle
information
chain
of each main
after
operation
affect
time
by triggering
the completion
of course,
only
make use of the main
one
of a key cycle
is initiated
allows
executes
cannot;
primarily
operation
The stop keys can,
initiate
that
elements
two types of logical
to govern
trigger
here only
from the console
operations,
the entire
Console
1 state of this flip-flop
the next so that
either
executes
sequence.
RUN.
is cleared
main sequence
the control
and the executive
from the switches
the computer
the main
and setting
trigger
switches
we are concerned
The logic
but it also treats
of a key may also be used as a gate
effect
control
Inputs
for use by the processor
are momentary
the processor
time by user programs.
the keys and switches.
or addresses
in which
from the console
-a
Operator
SEQUENCE
to the manner
the program,
the main sequence
of processor
MAIN
while
the key cycle.
performs
in from the console
do not use the main sequence,
it is running,
For those
the necessary
data
but
pre-
and address
the key cycle
controls
operation.
The operator
INSTRUCTION
may place
the
CONTINUE
sequence.
The INSTRUCTION
by clearing
RUN.
processor
keys.
The processor
in normal
operation
For these functions,
STOPkey
the key cycle
halts the processor
may also be stopped
2-10
by means of the START,
sets RUNand
at the end of the current
at the end of any memory
READ IN,
triggers
and
the main
main sequence
access
by means
of the MEMORY
sequence.
through
STOPkey,
which
In this case,
the MEMORY
may also deposit
the contents
functions,
a single
ing functions,
the processor
CONTI
information
examine
of that
to execute
instruction,
or deposit
dressing
them
functions
cannot
function
the processor
information
can be repeated
this by having
location
while
inserted
contained
Each such examine
unless
or deposit
the processor
the console
retrigger
itself
The EXECUTE key causes
allow
memory
requires
For this
so the processor
the operator
locations
a key cycle
to
without
ad-
and these
is stopped.
has a REPEAT switch.
at a rate determined
For the remain-
but does not set RUN,
of consecutive
or
two console
in the DATAswitches.
There are also two keys that
into a sequence
the key cycle
For these
RUN must be 0.
the main sequence
The operator
two main sequences.
i.e.,
the word
return.
by the ADDRESS switches
is running.
between
be running,
triggers
purposes,
may be resumed
addressed
be performed
For maintenance
operation
location
is merely
ly .
and normal
to the waiting
in the memory
is complete.
individual
“running”
subroutine
a memory subroutine
as an instruction
the instruction
examine
is still
from the memory
simulate
cannot
the key cycle
stops when
the return
NUE key which
key cycle
the processor
the processor
disables
by a pair
through
When
this switch
of speed controls.
a delay
whose
is on,
any key
The logic
interval
enables
is determined
by
the speed setting.
b
Most
instructions
are executed
address,
fetch,
execute,
requests
memory
access
counter.
Upon
the effective
word
is retrieved
to retrieve
to AR.
If the instruction
accumulator
In some instructions,
by either
the right
or left
cycles
Each main
the instruction,
to produce
Execution
in 2. lb.
and the cycle
begins
the effective
an extra
half
enters
taken
specified
cycle
by the program
cycle
is indirect,
repeating
and performs
a new address
the cycle
as many
goes on to the fetch
is specified,
it is retrieved
a second
as following
accumulator.
2-11
the instruction
the address
After
must be retrieved
of the addressed
when
instruction,
the processor
operand,
0 being
word
begins
again.
If an accumulator
location
the main sequence:
If an address
address,
uses a double-length
(with
comprise
from the location
the processor
as outlined
operands.
that
sequence
an instruction
calculation
the necessary
consecutive
MQ.
to retrieve
from memory
times as is necessary
by the five
and store.
receiving
address
Instruction
word
is fetched
location
from the memory
first
cycle
and sent
from the next
17) and sent to
location
This type of operand
addressed
is also sent
to MQ.
Finally
and leaves
operand,
After
the processor
it in MB.
fetching
This last fetch
the operands,
logical,
This cycle
operand
as specified
by the effective
if E is to be used as control
sequence.
performed,
enters
the store cycle
the result
by the instruction;
address
information,
of it.
an
are entered
times a special
sequence
instructions
handles
must first
the storage
fetch
of the true operand;
A block
repeats
the execute
program
counter
instruction
only
cycle
the fetch
occurs
is inhibited
when
such
in all
the current
is usually
to a new instruction
contained
in memory
may be stored
there
are performed
itself
and returns
directly
to the instruction
instructions
once
require
cycles
once
for a single
but the final
one is bound
provides
in effect
for every
word
instruction,
occurrence.
information
two main
cycle.
necessary
sequences.
the incrementing
before
Some-
in the block.
In this way,
to be completed
that
by special
to the store cycle.
that
in
are many
return
on a pointer
or in
cycle.
above,
instructions
the count.
and usually
and execute
more than
following
AR and MQ
outlined
instruction
cycle
and operate
for the retrieval
transfer
returns
to the next
which
result,
complicated
from the execute
it points
it performs
out the instruction.
in an accumulator,
by the sequence
The more
to carry
the result,
for a double-length
then
in which
PC is changed
may be deposited
are performed
by variations
that
to deposit
The processor
most instructions
sequences
are necessary
is being
accumulators.
are performed
functions
If a iump or skip
For most instructions,
Although
or control
cycle
by one so that
in AR.
consecutive
the execute
counter
the processor
as specified
enters
the program
Finally
ever
is skipped
the processor
arithmetic,
also increments
in normal
Other
the memory
or a iump address.
whatever
both
fetches
PC points
Whenof the
to the next
any interruption
can
occur.
The actual
form of the sequence
by the instruction
eightclasses
tion
eight
according
is in the special
instructions
operator-there
a subroutine
that
code
matter).
and the operations
as decoded
from the instruction
to the configuration
IOT format
is specified.
is no further
must properly
In the other
carried
decodes
If bits O-2 are 000,
decoding
interpret
six classes
register.
of bits O-2.
and IOT control
the remaining
2-12
If these bits contain
bits
enters
of the code
entirely
The codes are divided
10-12
the instruction
and the processor
the remainder
out in it are determined
111,
to determine
is taken
a special
the instrucwhich
of
to be a programmed
sequence
(and of the instruction
six bits are decoded
into
from which
word
by the hardware,
for
primarily
upon
by the logic
the instruction
class.
such as specifying
is to interpret
or right
the operand
for example
specified,
the other
binations
level
be considered
in which
priority
interrupt
beginning
system
corresponding
retrieval
executed
service.
so that
control
is transferred
interrupted
is responsible
The executive
programs.
instruction;
to a subroutine,
but only
on a channel
for releasing
system
When
multiply
of bits are
functions
is
all six bits are
the unused
most instruction
it is possible
that
octal
codes
for some com-
of the computer
and these may
does not change
restricted
The interrupt
fashion
it executes
except
address
that
encoder
the PI cycle
cannot
data
requires
the
no further
action
is “held”
higher
upon
is discovered,
starts a new main
to MA for
rather
be interrupted.
or transfer
service,
honoring
than
the processor
the address supplied
in the PI system
so that
at the
in the location
the processor
control
than
from
The instruction
to a subroutine
the processor
is required,
the interrupt
of the
are strobed
the instruction
itself
transfer
before
of priority
channels
and if a request
to a subroutine
processor
by the requirements
For a PI cycle,
if further
the interrupt
restricts
running
groups
as no-ops;
transfer
influenced
cycle;
do an I/O
transfer
can be transferred
is also
serviced.
so that
If the data
to the interrupted
fixed-point
has no modes.
Since
ways,
is a full-word
in which
from a channel
must either
returns
trol
being
is disabled
in a PI cycle
for further
PI cycle
it in the normal
comes
PC, and the strobe
A4-1.
depending
operations,
of 16 Boolean
that
on the state
system.
and address
to the channel
instruction
in Table
example
and the executive
a special
and executes
instruction
no effect
specific
In some cases,
in different
are executed
instruction
it by entering
which
of ways
in the self mode.
instructions
of every
sequence
is listed
to have
An obvious
cases,
are not used and are executed
no mnemonic
and is performed
The way
honors
codes that
as no-ops.
or whether
In other
of execution.
for an individual
instruction
transfer
class four bits determine
the mode
in a variety
bits are used to represent
or a fraction.
into sets of bits that are decoded
of mode and
operand
single
as an integer
control
for which
They may be decoded
in a half-word
in the Boolean
There are some instruction
are divided
IR.
half
two determine
to a single
codes are those
with
Occasionally,
the left
decoded;
decoded
associated
automatically
a second
PI cycle
is executed
any other
interrupt.
If con-
the processor
the one being
held;
may again
be
the subroutine
completion.
operation
(user mode),
2-13
in order
each
to permit
program
time sharing
must operate
within
by several
the area
of
core assigned
to it; an attempt
to use an address
be set and immediately
initiates
an interrupt
PC points
the time
within
depends
was made).
The execution
used by UUOs
transfer
Besides
restricting
processor,
control
the main
of a programmed
are unrestricted
channel,
even
nets that
system
monitor
includes
user instructions,
to be run in a restricted
runs unrestricted
executive
user mode,
key
routine)
interrupts
or instruction
or gave
power
turnon,
it is not running,
(this action
implements
interrupt,
and clears
routine
mode and transfer
executive
routine
the user flag.
may be made
control
control,
a 1 in bit
Instructions
the
executed
in
registers
I/O
allow
PR and RLR,
the processor
A program
system
(assigning
core areas,
interrupting
when
attempted
that
operation.
The
entering
its time
needs of user programs,
in executive
is up),
and for
to use an illegal
a priority
clear
interrupt
instruction
enters
The return
and
RESET
the pro-
(which
normally
to service
to return
an
the processor
since
all
41 must be a JSR, which
UUOs
stores
by means of a iump which
to a user program
11).
cycle,
Similarly,
a user program
JRST (a 1 in bit
the I/O
suffices
the user flag
in location
mode,
by pressing
the user flag
Thus unless one
a PI cycle
(unrestricted)
mode
is interrupted,
2-14
to halt
in user mode.
elements
to one of its subroutines.
12).
attempt
for overall
it in executive
routine
by means of a restoring
UUOs)
operation.
a UUO.
the instruction
The executive
(JRST with
all
During
set.
system
user programs.
a user program
equipment).
must within
for overall
of several
is automatically
remains
by user programs
executed
These logic
program,
through
but if a user program
the executive
sets the user flag
UUO
the I/O
request
UUOs
and relocation
user programs
may place
memory
but the locations
was running
protection
sharing
because
to which
is unrestricted,
device.
must be responsible
up control
the user restrictions)
to the executive
are under
control
the operator
cessor runs unrestricted;
memory
time
to
System
for servicing
the processor
also clears
Executive
to the current
and UUOs,
it receives
program
for scheduling
control
when
Following
when
all
action
address
(the executive
and transferring
for servicing
taking
to permit
is responsible
an I/O
and the user flag.
mode
routine
(UUO)
a flag
(the location
the illegal
traps (as if they were
if the interrupted
the 8-bit
that
responsible
or operate
c
The executive
routine
area causes
channel
to user programs;
the user mode
dismiss an interrupt
sequence
operator
to the (unrestricted)
addresses,
of the assigned
on the processor
(40 and 41) are inaccessible
always
PI cycles
upon
outside
after
This instruction
an interrupt
restores
or
all
other
flags
to their
a user program
original
from
Each user program
2000
octal
(since
2000
an integral
multiple
its block
illegal
To assign
loads
is assigned
a block
address
address
by checking
is equal
the block
address
+ C (MA).
fast memory
(note
its assigned
block).
The user flag
that
circuits
instruction
that
i .e.,
is executed
These instructions
The arithmetic
the two 9-bit
unrelocated
location
as if it were
a UUO
tions
part of the processor
registers
and subroutines,
the special
time
chains
system
to dismiss
are trapped
SC and FE, the time
by having
41 is executed.
and thereby
that
full-size
16 core
locations
the relocation
channel
in
may
or halt
IR decoder
to
and
A user program
the
outputs
above,
UUOs
an illegal
to the executive
registers
AR,
execute
the special
connections
and a subroutine
interface
through
which
to the gating
for the three
main
registers.
2-15
to
have access
As mentioned
control
by adding
bus is equal
Thus in user mode,
returns
the
routine.
LOGIC
the three
chains
their
which
is relocated
an interrupt
is in user mode.
ARITHMETIC
includes
user instructions.
channel.
the size of the
so all programs
by enabling
the
tests for an illegal
ever uses the first
monitor
the processor
2.3
relocated,
size,
Each time
the user address
on a user program
its block
word.
is also
to one less
DATAO,
C(PR) x 2000 + 1777;
no user program
the nets that
when
of the data
of
and
size
on the processor
the executive
0 to 17 are never
a 1 in bit 9 or 10 (an attempt
line
than
the address sent out on the memory
Addresses
UUOs
from zero
uses a processor
At the same time
to it; i.e.,
and enabling
command
are unrestricted,
2000.
the restrictions
nor any IOT.
the UUO
11 x
this means
implements
not use a JRST with
processor)
+
routine
does not exceed
multiple
the block
to or greater
immediately
a user program,
JRST.
is an integral
to addresses
from bits O-7 and 18-25
during
This prevents
40 to 57 to service
equal
occurs
it.
restoring
location
is restricted
the executive
clear
for a user block);
to use an address
the address
to [C(PR)
C (RLR) x 2000
protection
that
starting
available
is set and an interrupt
is called
first
must use locations
A user program
PR and RLR, respectively,
but can never
of an incorrect
in core whose
a core area to a program,
subroutine
drive
first
if it attempts
flag
as a result
routine
of 2000.
size;
memory
block
user mode
is the lowest
operation
and can set the flag
leaving
the executive
interrupts,
than
states
Included
MB,
and MQ,
sequence
are made
instrucfrom
in the AR part of
the logic
are four flags,
are stored
AROV,
as miscellaneous
iump and cleared
between
MB and MQ.
Although
roll
Associated
can be triggered
i.e.,
only
the register
.
the first
to the left
in this manner
in order
can be triggered
hence
the pair
are the only
them.
previous
ones that
an exclusive
in AR:
and complementing
trahend
or division
in AR is then
places
point,
being
Negation
1.
for floating
so the result
with
2-16
AND,
is also a carry
if the first
carry
changes
If this carry
from
chain
by the contents
to hold
a word
of
count
chain
is used as two simultaneous
index
functions,
to AR.
others
function
according
performs
point,
can carry
The above
always
I isted
at a number
the algebraic
subtraction
or subtractions
of
in
by the
sum in AR of
negation)
is
in MB must be subtracted
by complementing
MB and AR are switched
merely
functions
of places
algorithm
means arithmetic
the number
into the left:
by combinations
to the addition
it generates
(which
half
are executed
is triggered
can be produced
additions
OR,
the carry
In subtraction,
the processor
or setting
an arithmetic
represented
of a word
with
words simultaneously,
adds 1000001
determined
There
a 0 bit.
from the right
in MB and AR),
the result;
of shifts
half
this
the carry
and adding
negated
is a sequence
of both
directly-all
OR,
or right.
a
is combined
of the complement,
the second
halves
plays
the clearing
and produces
number
and right
which
in
(swapped)
it usually
implement
it complements
1 to the
effectively
in MB and AR.
for fixed
until
and an overflow
of the words
originally
of bits left
complements
Although
can be performed
by complementing
from that
indexing
chain
functions
(the particular
the numbers
adding
of index
configuration
performed
to allow
in the carry
If following
the register
use the left
at AR17 and AR35
is no break
bit,
in MB,
that
in the register
LSB, it adds
Some instructions
and an address;
the formation
and the shifting
bits for storage
an operand
to a mask,
at any point
at the register
by holding
of gates
it complements
1 to 0, and ripples
is triggered
for a of ful I words
can also be interchanged
AR is a myriad
according
transfers
IR, or the miscellaneous
of a word
operations
with
functions,’
MB and AR,
of MB and AR can be formed
and arithmetic
OR logic
which
to the left;
there
function
bits in a word
and exclusive
The states of these flags by a JRST; they may also be sensed
between
PC,
The two halves
the AND
in AR.
of individual
function
jumps.
in logical
an operand
words may be made
MB may also receive
and in certain
passive
and PC CHG.
by a JFCL. of ful I words or half
in MB.
AR CRYl,
bits and may be restored
Transfers
a UUO
AR CRYO,
by adding.
interspersed.
AR,
then
and the subMultiplication
The third
in character
MQ
MQ,
register,
operations
serves primarily
actions
on a pair
length
operand
registers
is used occasional
where
the actual
shifted
MQ
holds
subroutine
For other
while
operations,
In floating
floating-point
instructions,
is transferred
portion
position
is inserted
in addition
and the SC shift-count
tains
instructions
information).
directly.
sequence
which
calls
logic
sequences
level,
negation,
are shifted
in.
In division,
out to AR
can be stored
in SC,
provides
are on the exponents.
in SC and then stored
Following
while
part of AR.
but
in AC.
whose gating
performed
part.
end.
and AR the remainder,
is calculated
that
are used and
in at the least significant
computations,
normalizing
in FE
the
the result,
SC is also used to calculate
increments,
are the AR subroutine
which
registers
also includes
the
and from SC the new
the time
in either
simultaneously
are shifted
even
add and subtract,
the processor
rank subroutines
2-17
group
direction),
counts
though
the execute
switches
chains
The basic
and subroutines.
and indexing
subroutine
the lower
C(E) or E, but when
and as bits are shifted
operations
operation
In multi-
in AR.
the special
instructions,
direction.
and the mul tip1 ier in
product
calculated
the exponent
For
ends of both
As bits of the multiplier
the quotient
the only
the arithmetic
For fixed
For other
scale,
in the exponent
in the pointer
both
is either
to SC in case it must be changed
from any higher
subtraction,
in either
so the quotient
is first
for a character
to the registers,
can be called
(for shift
back
of a pointer
nets for executing
rotated
the steps in the fixed-point
from SC it is inserted
position
addition,
the exponent
operands.
the opposite
are shifted
positions
but
Moreover,
dividend
MQ contains
their
and indexing.
and finally
trol
then switches
SC is used to count
exponent
double-length
bits of the double-length
bits of the quotient
purposes,
case
end to end and the double-
in AR.
half of the double-length
steps,
for control
MB holds the multiplicand
products
is a special
are joined
and the contents
of the computation,
In floating-point
addition
of partial
the low-order
At the completion
direction.
operation,
the low-order
for use by the division
the divide
arithmetic
and there
in parallel
comes from AC and the multiplier
the formation
out of MQ,
storage
of AR for handling
in either
to form a ring
performing
are shifted
the two registers
may be shifted
the multiplicand
controls
extension
of accumulators,
pl ication,
MQ
AR and MQ
as a right
may be joined
I y for temporary
subroutines,
(which
includes
for a single
calls
usually
subroutine,
only
MQ
AR con-
the AR subroutines
from the execute
and which
fixed-point
AR and/or
operand
con-
which
the SC addition
SC and shifts
cycle
and many
returns
cycle
to a special
to the store
cycle.
The sequences
call
only
divide
for character
the basic
begin
whichever
routine
which
calls
only
sequence
subroutines
by calling
routine
operations,
(including
the exponent
is appropriate,
also follows
the multiply
calculate
the floating
enters
fixed
directly
that
connects
MA,
buffer
MB,
memory
the control
to memory
logic
by triggering
pause-write
which
also supply
cessor
for the memory
must later
an address
is in executive
immediately,
address
the illegal
operation
as received
against
directly
by memory,
and bit
memory
from MA,
MA34
made,
the operator
to disable
special
request
levels
the least-significant
when
the bank.
all even
access
and readmust
If the proon the bus
in MA is compared
on the processor
and
sequence
the appropriate
main
register
gains
write,
The calling
the address
Ml,
sequence
for read,
with
sequence
and sets
of RLR and the more significant
represent
the sum of the two registers.
address
on the bus (low-order
adders).
bit of the address
In this way,
within
consecutive
in another.
using a 16K bank
In the address
A switch
(with
a single
addresses
at the memory
8K banks,
addresses
must be interleaved).
The processor
memory
and it must wait
until
subroutine
requests
the addressed
a memory
memory
accepts
2-18
cycle
PR.
channel.
bits from the relocation
in one bank,
address
to MB.
puts the relocated
high-order
this feature
sub-
sequence
register
or special
restart.
whose outputs
control
supplies
odd addresses
indicator
has entries
the outputs
35 is used as the LSB to select
are interleaved-all
cycle
the memory
a word
while
an interrupt
to a set of dc adders
multiply
use of an intermediate
to go to the end of the current
PR is being
sub-
return
is to be written,
places
is a delay
the processor
in MA is legal,
bits are supplied
which
and if information
there
the normalize
bus includes
by a read-write
the subroutine
or divide
INTERFACE
subroutine,
flag requesting
the comparison
If the address
allows
mode,
causes
MA bits are applied
memory
to MA,
and
subroutine.
A processor
be followed
but for user mode
An illegal
While
the memory
the multiply
PR and RLR, memory
subroutine.
scale
multiply
The fixed
does not make
to the memory
registers
then
sequence.
MEMORY
and floating
Floating
by entering
the divide
the processor
operations,
subroutine).
terminate
divide
into
user mode
shift
subroutine,
add-subtract
2.4
The interface
transfer,
the memory
and both
subroutine;
but instead
block
by calling
the request,
memory
which
as a subroutine,
does not occur
until
the memory
is free and this processor
acknowledgement
wait
only
wait
until
signal
until
from memory.
the memory
it receives
to fast memory,
accepts
is not acknowledged
nonexistent
memory
flag
the acknowledgement
unless
operator
the word
is set,
from the memory
an interrupt
the memory
the return
to the waiting
because
need
it must
If the request
is made
is no buffer.
to a memory
If
cycle,
the
Following
channel.
pulse to the waiting
the processor
sequence
of an
the processor
there
compared
sends a restart
To restart
receipt
cycle,
on the processor
subroutine
STOP key is on.
cycle,
location.
time
upon
but for a read
the read
a considerable
requesting
the MEMORY
than
restarts
is for a write
in its own buffer;
longer
within
signal,
must simulate
read
takes slightly
the request
sequence
If the request
the information
the write
The processor
has priority.
after a memory
by pressing
theMEMORY
stop,
the
CONTINUE
key.
If the address
in MA is the same as that
examining
or depositing
information
displayed
in the memory
indicators.
it displays
the information
of data,
On a read
conditions,
bus) to the device
system
located
of flags
control
which
allow
the processor
When
the code
decodes
cycle,
bits
internal
to check
switches
the necessary
to individual
or the operator
of the memory
the information
is
buffer
are
read,
on a write
times
the transfer
IOT
SYSTEM
transfer
and the processor
processor
itself
in bits O-2 of the instruction
command
IOT
IOT sequence
Only
DATAO,
CONO,
four
BLKI or BLKO
2-19
whose
IOT
I/O
signals
interface
priority
(also over
interrupt
contains
interrupts
the processor
Upon
that
the
a number
and which
instructions.
register,
instruction.
signals.
instructions.
that
command
can request
status with
the specific
logic
on the bus are the priority
conditions
internal
to a special
control
the bus by sending
Two of the devices
out on the bus; these are for DATAI,
correspond
MI displays
bus is the in-out
its own
to determine
the processor
and generates
units.
111 appears
lo-12
the contents
INPUT-OUTPUT
and status over
in the processor,
through
switches
to be written.
end of the I/O
initial
ADDRESS
from the console,
2.5
At the processor
in the console
reaching
IOT control
the execute
times the instruction
types of command
and STATUS,
requires
signals
of which
signals
operations
are sent
the first
on the bus only
three
after
conversion
to a DATAI
and the latter
peripheral
While
plied
two then
equipment
IOT control
over
is generating
the selected
Among
assignment;
the device
CON0
system
itself
and PIH,
go to the priority
to control
register
each
the request
.
The PI0
chain,
The PIH flip-flop
generates
system,
a third
detects
and
that
the program
strobes
(a CON0
signal
in a particular
a new main
memory
provided
numbered
from an encoder
the channel
the instruction
This instruction
channel
number
is doubled
in location
should
a request
is sup-
sent
to
are supplied
over
is a priority
and when-
signal
except
instruction
which
and added
with
to the
PI
the PI
that
to 40.
PI system
outputs
2-20
is off),
by performing
are connected
subroutine
The processor
If a PIR is on
enters
are set,
MA receives
to MA
the address
in such a way that
n, the processor
executes
two for each
or a block
a PI
the instruction
PIR flip-flops
42 to 57,
status,
and synchronizes
the processor
(if several
flip-flops
in a PI cycle,
is on.
the instruction,
uses locations
control
are on.
cycle,
channel
Thus for channel
a JSR to an appropriate
has priority.
By checking
channels
and address
from
PIR flip-flops
the processor
and which
the channel
To retrieve
that
in a PI cycle.
PIR,
synchronizes
the remaining
places
the request
PIO,
by one flip-flop
There are also three
if the channel
with
registers,
for the channel
the corresponding
honors
7-bit
The PIR flip-flop
performed
is active
The encoder
40 + 2n (the
be either
are
is no assignment);
is governed
signal
IOT
even
has priority).
in the PI system.
the
IR bits 3-9
to a device
three
on or off.
another
that
associated
contains
channel.
it,
of every
sequence
location
affect
signals
Every device
channel
request
the system
can set the PIR for a channel
and starts
the lowest
from any PI line
in
from the device
by sending
and in conjunction
from a block
whether
and
conditions
may supply
channel.
from
code;
is supplied
1 to 7 (zero
which
A given
activates
the PI lines at the beginning
a request
cycle
can determine
code
assigned
or status
an interrupt
on the selected
overflow
conditions
command
Data or initial
from
system
sequence
one that
that
that CON0
an internal
holds a break
for the interrupt
data
turns the channel
main
bring
PI assignment.
channels.
flip-flop
the device
with
to its assigned
interrupt
the seven
to the processor
and a priority
device;
at least one
CONS0
the STATUS
can respond.
it requests
on the bus I ine corresponding
The PI lines
in the device
assigns a channel
system
can receive
signals,
conditions
service,
and
way.
device
the initial
requires
generate
the command
a gate
CONSZ,
three
the same
the bus to the selected
the bus to AR.
CONI,
tests; all
in exactly
but only
from AR over
ever
perform
the bus to enable
ail devices
interrupt
or DATAO.
IOT
channel).
to handle
‘I
a data
transfer.
mediately
tion
If it is a BLKI or BLKO
to the interrupted
in the interrupted
into a second
program
program
PI cycle
BLKO,
or JSR; other
consequences
subroutine,
of the priority
priority.
so that
all
lower
a BLT may require
following
each
source
word
processed
and destination
The processor
rupted
then
the program
as well
a new main
time,
a request
in the accumulator
a BLKI,
is a iump to a
part
of higher
the channel
the break
so as
occurred.
lines are also strobed
is discovered,
the current
and the partial
as if to restart
should
This disables
dismiss
on which
goes
unfortunate
by a channel
the PI request
Whenever
sequence
have
If there
only
should
as the channel
execution
are stored
would
which
be either
for the channel.
can be interrupted
in the block.
addresses
begins
routine
any instruc-
the block
block
transfer,
is terminated.
but is inter-
instead.
The I/O
interface
flags
associated
flags,
overflow
supplies
for the processor
with
it with
cessor status
or a request
channel.
DATA0
in the executive
a PI assignment,
and these AR flags
the user flag
is meaningless
to a nonexistent
the clock,
memory
overflow,
that
requests
flag
DATAI
for the four
two of the AR
the interface
it is 0 by definition
a pushdown
an interrupt
instructions
brings
flags
and
can be sensed as pro-
can cause an interrupt
may also use data
PR and RLR for a user program;
controls
user address,
automatically
except
However
system.
as status since
or PC change
The program
in 2.15
plus the user flag
The flag set by an illegal
by a CONO.
loads
discussed
can be set by the CON0
made
enabled
the flags
and PC change,
(although
Setting
contains
AR and the user flag
an IOT can be executed).
been
the PIH flip-flop
41 + 2n,
hang up the processor.
im-
the processor
should
but they usually
by setting
considerable
in location
returns
before
is overflow,
in a PI cycle
even
channels
can occur
If there
and could
of the subroutine,
priority
the processor
interrupt
the instruction
can be executed
the break
At the completion
to reenable
. Since
chain
is held
priority
An instruction
subroutine.
for the program
is no overflow,
executed).
it performs
instructions
the break
(another
is actually
in which
be a JSR to an appropriate
and there
whenever
list overflow,
on the processor
only
if it has
for the processor:
in information
from the console
data
switches.
Control
units
for other
devices
each
contain
a data
the device,
an interface
for control
‘connections
connections
to the bus.
The size of the buffer
2-21
buffer
for transfers
to the device,
depends
upon
between
and an interface
the device.
the I/O
bus and
for control
It is 36 bits
if full
words
can be transferred,
device,
the buffer
can provide
may be,
operation
and often
or selecting
Usually
supplied
all
control
For input,
flag causing
buffer
onto
output,
provide
interrupt.
with
flag
the next
transfer
Included
in this manual
a 360bit
buffer
one 8-bit
line
1-6 only
word.
The punch
handles
independent
for input,
devices
each
only
a CON0
a card
shall
be requested
numeric
the
is started
mode,
column
unit
assembles
is read,
mode,
in binary,
hole
each
8.
but only
are read.
unit
flag
gates
the
For
information.
causing
when
columns
in a column
an interrupt,
but clears
2-22
tape
the
mode,
data
character
separately
prints
one CON0
into
out.
are assembled
into
is requested
two
characters;
the card
per card because
an interrupt
In binary
into a word.
a 6-bit
l-6,
Characters
With
whether
is full.
a 360bit
In alpha-
single
is required
can specify
only
in holes
on the bus.
has
from holes
is actually
sends them back
the buffer
reader
has two modes.
a 6-bit
is translated
If an interrupt
is set.
accepts
the processor
The program
or only
six into a word.
func-
not only
The paper
The keyboard-printer
is placed
are read and three
character
are
sets a
six such characters
it punches
the program
operations
column
of
usually
In alphanumeric
the control
For output,
unless
that
control
information
devices.
in two modes.
by the operator
80 columns
an error
I/O
at a time but it still
punches
the mode
certain
of more
new
one character
can initiate
the Hollerith
for four
in binary
are not printed
column
supplies
error
to device.
units
character;
CON0
status signals
sets a flag
but it assembles
typed
all
to the device
not only
one PI assignment.
following
holes of each
control
a new
with
character
once
twelve
only
the retrieval
8 is punched,
hole 7, and always
at the keyboard
reader,
hole
a DATAI
and a
whatever
additional
from the device
with
onto
to the same control
information
may be retrieved
an 8-bit
it punches
that
clear
also perform
and initiates
register
conditions,
that are connected
responds
from buffer
from the tape;
in which
punches
typed
information
is read
a DATA0
are the control
in lines
numeric,
never
but
with
a control
instructions
from the buffer
responds
the buffer
gates
such as determining
as status and often
the data
the flag
of information
and the processor
and initiates
information
The processor
the bus but also clears
DATAI
in operation,
from several
of the buffer
For an output
For initial
the device
additional
device
characters.
and the bus includes
bits can be examined
the loading
the transfer
plcce
In most cases,
a priority
unit
device,
and may be identical.
an individual
by the device.
t ions.
overlap
must be single
for an input
the control
at least one PI assignment,
there
unit.
usually
if the transfers
by DATAO;
between
which
register,
flags
can be loaded
The interface
the bus.
status
but smaller
character
but is not
mode,
all
In alphaand
serviced
before
CHAPTER
3
OPERATION
This chapter
type,
discusses
the normal
and card reader;
of operation
ization
purposes
it is recommended
of the equipment
that
information
the reader
as presented
describes
the operator;
for normal
center
the function
those mounted
operation
in Chapter
behind
this panel
the top of bays 1 and 2 contain
Indicators
for the four
in-out
only
at the top of the right
ginal
check
controls,
which
The name used in the logic
whenever
it differs
associated
flip-flop
elements
that
information
therefore
while
discussed
For maintenance
subroutine.
single
their
drawings
purposes,
is running,
through
halts as well
inside
a shift-count.
i.e.,
or control
on the panel.
STOP key to run a program
panel
at the
The panels
are for maintenance
level
When
function
located
number
they display
may be stopped
the bay doors allow
However,
in which
at slow speed stopping
3-l
is listed
at
purposes.
behind
contains
the
the mar-
is lit,
Indicators
of main sequences
change
when
stopping
the processor
after
the operator
every
after
latches
instruction.
for logic
useful
has stopped.
every
memory
and
to stops at the
This includes
down
the
and are
AR subroutines
here is limited
of an instruction.
display
too frequently
from the console
the discussion
after
in parentheses
any indicator
is asserted.
but most indicators
at the completion
as the situation
All controls
operator
part of this panel
to
in 9.1).
states over a considerable
located
organ-
accessible
indicators.
part of the panel
bay (the lower
for a register
the processor
self-
the functional
in 9.1 .
are on the main
most of which
in terms of the information
end of a main sequence,
grammed
console
are described
the processor
with
discussion
is relatively
that are readily
most of the processor
is in the 1 state or the associated
Switches
stepping
and indicators
are on the upper
from the name engraved
retain
himself
Tele-
PANELS
and punch
indicators,
devices
cover
this chapter
the doors of the bays are described
reader,
punch,
2.
CONTROL
also contains
metal
reader,
but the detailed
Although
9.
familiarize
of the controls
of the processor,
of the console;
first
processor,
is included,
is in Chapter
3.1
This section
of the arithmetic
some maintenance
for maintenance
contained,
operation
all pro-
the INSTRUCTION
a
This panel
contains
to the operator
tinuous
ations,
and all
Indicator
all off,
and the console
contact
levers
that are of concern
The switches
supply
lock are Z-position
that
initiate
contoggles
or terminate
oper-
held on.
just completed.
is a UUO and the remaining
bits are defined
Any other
the register
is an IOT and the remaining
configuration
contains
If the left
three
by the program;
display
bits indicates
the first
the basic
lights
are
if the left
six bits of the
format,
for
code.
these four bits are usually
they are used for special
the left bit
one of the eight
lights
three
using the basic format,
but for some instructions
In an IOT instruction
bits specify
of the first
the instruction
- For instructions
address,
flags.
speed controls
while
flip-flops
- Bits O-8 of the instruction
the instruction
code.
AC (IR9-12)
lator
(IRO-8)
are on,
which
only
and control
keys and switches.
The keys are momentary
an action
the instruction
device
Panel
Registers
INSTRUCTION
three
all of the operating
but the rotary
up is 1 or on.
or produce
Operator
for most of the registers
and contains
levels
for which
indicators
Console
is the LSB of the device
purposes
code;
an accumu-
such as addressing
the remaining
three
IOT instructions.
I (IR13) - This is the indirect
bit,
and it should
always
be off when
the processor
has stopped
at the end of an instruction.
INDEX
(IR14-17)
completed.
- Contains
If the four
the address
lights
are all off,
of the last index
register
used in the instruction
there was no address modification
in the final
just
address
cycle.
MEMORY
with
(Ml)
any console
desired
location
- This 36-bit
examine
while
register
or deposit
the processor
displays
the contents
operation.
of the memory
location
associated
The I ights may also be used to display
is running.
3-2
any
PROGRAM
COUNTER
(PC) - This 18-bit
register
contains
the address
of the next
instruction
in the program.
MEMORY
ADDRESS
one greater
than
(MA)
that of the location
in slow speed operation,
access.
However,
contains
the effective
In addition
panel
containing
the register
if there
to the above
usually
which
there
18-bit
the halt
contains
either
register
indicates
instruction.
the address
an address
On an instruction
or in a subroutine,
may or may not be the address
of the last memory
are three
processor
registers
stop
used for the last memory
in the store cycle
was no storage,
address,
halt this
located
it
access,
at the top of the in-out
(c below).
Switch
Registers
DATA
(DS) - Th is register
operator
may either
struct ion.
ADDRESS
with
- 0 n a programmed
the operator
the word
may also read
by ADDRESS,
For a read request
MEMORY
Whenever
displays
a DATAI
register
the contents
a 360bit
word to the processor.
or cause the processor
DATA with
keys and switches.
specified
to supply
in memory
- By means of this 18-bit
the operating
location
deposit
The program
(MAS)
allows
may specify
the memory
the word read;
it as an in-
for the processor.
the operator
of that
to execute
The
subroutine
location
request
for use
gains access
are displayed
for a write
address
to the
by MEMORY.
the word written
is
displayed.
Control
Indicators
RUN - Lit while
triggering
the processor
the next.
When
is running
the light
in normal
goes off,
operating
the processor
mode,
with
each
main sequence
stops upon completion
of the cur-
rent instruction.
MEM
STOP (MC STOP) - If this
processor
stops after
memory
light
access
goes on at the beginning
is completed
3-5
because
of a memory
the subroutine
fails
subroutine,
the
to send a restart
pulse to the calling
the MEMORY
CONTINUE
PI ON
If RUN
sequence.
CONTINUE
restarts
(PI ACTIVE)
is also on,
If RUN
key.
the interrupt
- Indicates
is off,
the processor
other
can be restarted
only
keys may be used but only
by I ifting
MEMORY
key function.
that
interrupt
requests
can be granted
by the priority
interrupt
system.
(PI01 -7) - Th ese lights
PI ACTIVE
the lights
specify
PI REQUEST
nized.
other
the channels
(PIRl-7)
PI IN PROGRESS
being
held.
numbered
can force
the REQUEST
Several
light
that
When a PROGRESS
light
is serviced
a single
flow,
REQUEST will
PI OV,
PI CYC,
way because
formed
only
still
example
indefinitely
instruction
indication
if the channel
with
overflow,
though
the break
can go on and remain
Thus a faulty
that
the break
location
program
is being
contains
a CONO,
REQUEST on and PROGRESS
going
serviced.
off;
all
be on.
only
in the program.
3-6
PI CYC
light
is on.
the corresponding
on.
If there
be static
is over-
not yet be on and
in this case the
The lights
act in this
if the instruction
will
per-
in a PI cycle,
and PI REQ will
the processor
PC will
the PI cycle(s),
is set and cleared
However,
can hang up the processor
is that
no higher-
goes off.
on in a PI cycle
held
is on.
is on,
one whose
PROGRESS will
at the top of bay 1 will
light
for the break),
PROGRESS
is being
light
from any
breaks are currently
following
the PIH flip-flop
at the end of the first,
and PI REQ lights
PROGRESS
can interrupt
PROGRESS
so REQUEST goes off without
be on even
is not an IOT.
visual
IOT without
are required;
a given
a jump to a routine
until
below
have been synchro-
ACTIVE
is the lowest-numbered
serviced
go on again
requests
on which
but while
channel
The numerals
is not on; for a request
the channels
indicate
goes on (following
by a block
PI cycle
two PI cycles
being
on which
if the corresponding
can go on only
is actually
are on.
two sets of indicators.
if a channel
may be on simultaneously,
REQUEST goes off and cannot
within
even
- These lights
lights
PI channels
the channels
may go on; a lower-numbered
and the channel
If a break
indicate
a request
light
(PIHl-7)
which
for these and the following
- These lights
The program
source
indicate
repeat
and will
and the
be on.
For
the instruction
point
to the next
Operating
Keys
In the right
half of the operator
is two logical
The momentary
keys.
on positions
panel
is a row of eight
keys affect
throughout
and program
grammed
when
conditions
operation
the discussion
have access
use the keys properly
the special
Although
the key cycle).
it is assumed
operator
and of these,
the processor,
trigger
imposed
only
by the ADDRESS
readin
area,
retrieved
pletion
ition
for single
above
STOP (INST
of the current
It places
cycle
position
and punch,
twelve
keys (i.e.,
keys are given
is not in use,
i.e.,
below,
that both
In order
are illegal.
the operator
must be fully
to
aware
of
of the keys to the pro-
the processor
to retrieve
the RIM SBR indicator
inaccessible
from any location
INSTRUCTION
instruction
and any memory
the normally
center
are initiating
of the relation
the same as START except
lighting
is disabled,
are the
in normal
an instruction
operation
from the location
switches.
READ IN - This key is exactly
fast memory
is in use,
lever
The other
for individual
of which
in 3.3t$.
if RUN is off.
specified
the others
system
each
the reader
or not.
and no operations
discussion
is presented
RUN) an d causes the first
mode,
system
(a complete
of the system
is running
the executive
to all of memory
(lighting
the readin
that
the stable
end of the row control
considerations
levers,
of a given
and below;
the processor
special
switch
positions
two are stop keys,
the executive
START - This key functions
enter
above
The two levers at the right
and these may be used at any time whether
they
up and down
contact,
for the keys whose names are written
is off for both keys.
3-position
bottom
it also causes
the processor
to
at the top of bay 1.
In this mode
the
an address
16 core
17, the processor
Whenever
the readin
causing
This key has a catch
The turnon
17 or less is given
locations.
leaves
STOP) - Turns off RUN,
instruction.
step operation.
cal I with
that
that
an instruction
of the key triggers
to stop at the com-
it to be left
events
is
mode.
the processor
allows
access to the
that
in the on pos-
faci litate
emergency
stops (for detai I s see 3.3~).
INSTRUCTION
the processor
CONTINUE
to resume normal
(INST
CONT)
operation
- This key functions
(lighting
3-7
RUN)
beginning
only
if RUN
with
is off.
the instruction
It causes
in the
location
specified
operator
can single
also has a catch
by PROGRAM
COUNTER.
step instructions
so that
By leaving
by pressing
by leaving
both
INSTRUCTION
INSTRUCTION
keys on and using
STOP on,
CONTINUE.
the REPEAT switch,
the
The latter
key
a program
can
be run at slow speed.
MEMORY
STOP (MEM
for single
step operation.
of every
memory
access.
During
only
single
causing
and the meaning
the processor
step operation
a call
a separate
However,
MEMORY
MEMORY
CONTINUE
and it then restarts
ADDRESS always
(MEM
whatever
turns off the light).
CONT)
cal Is.
and using the REPEAT switch,
the location
was interrupted
within
to which
only
STOP on,
The latter
key also has a catch
purposes
access was made.
if the MEM
the operator
generates
the main sequence.
by the MEMORY
MEMORY
a program
for maintenance
the stop occurs
- Th’IS k ey f unctions
sequence
By leaving
step by memory
displays
cycle
The subsequent
the stop.
This key is used only
upon where
of each memory
in the fetch
during
in the on position
goes on at the beginning
to stop at the completion
for read-pause-write
cycle.
depends
it to be left
STOP light
does not hold memory
write
of the lights
that allows
the MEM
the key is on,
so the processor
then triggers
to single
While
subroutine,
a read request
restart
STOP) - This key has a catch
STOP light
is on,
STOP key (it also
can use MEMORY
so that by leaving
CONTINUE
both
can be run at slow speed from one memory
call
keys on
to the
next.
EXECUTE
(EXEC)
the instruction
While
cannot
- Th’IS k ey f unctions
contained
the key is on,
be affected
before
saving
the console,
in the DATA
the normal
if RUN
switches
program
is off.
program
a skip increments
it so that
count
it.
in the execute
is inhibited;
thus PC
counting
IO RESET - This key functions
control
registers
in the processor
nected
to the in-out
is off.
it in executive
bus.
3-8
that
It clears
skip always
mode)
when
is already
all flags,
increments
time for the skip;
jump always
in the program;
but saves the count
if RUN
(placing
it a second
A programmed
to the next instruction
only
cycle
A programmed
and may increment
a iump loads PC normally
to execute
upon completing
PC at most once.
it points
It causes the processor
and stop immediately
unless a skip or iump is executed.
PC once for the normal
the console
only
from
increments
PC
executed
from
in it.
control
flip-flops
and in most equipment
and
con-
DEPOSIT
THIS
(DEP) - Deposits
The word deposited
is displayed
the contents
the MA lights
displaying
used while
the processor
is running
DATA
NEXT
(DEP NXT)
in the location
contains
- This key functions
is displayed
If RUN
is off during
the address of the examined
if there
EXAMINE
is no chance
NEXT
(EX NXT)
the contents
ORY ADDRESS.
is off during
the deposit,
only
is off,
if RUN
than
by ADDRESS.
the processor
This key should
location.
of a program
by MEMORY.
halt occurring
It deposits
that specified
(3.3b).
the contents
by MEMORY
At the completion
be
of
ADDRESS,
of the operation
MA
location.
location.
to display
the contents
the processor
This key should
of a program
halt occurring
- Th’IS k ey f unctions
At the completion
specified
is no chance
is one greater
the operation,
of the location
in the location
of the affected
if there
THIS (EX) - C auses MEMORY
ADDRESS.
display
only
the address of the affected
EXAMINE
only
the address
whose address
and the word deposited
If RUN
by MEMORY.
stops with
DEPOSIT
of DATA
only
whose address
of the location
stops with
be used while
the MA lights
the processor
by
displaying
is running
(3.3b).
if RUN is off.
is one greater
of the operation
specified
It causes MEMORY
than
MA contains
that specified
to
by MEM-
the address of the
examined
location.
READER ON
reader
- Turns on the reader
energizes
the brake,
and triggers
a PI request
on the
c hanne I .
READER OFF - Turns off the reader
reader
motor,
releases
the brake,
and triggers
a PI request
on the
channel.
READER FEED - Feeds tape through
PUNCH
only
motor,
FEED - While
feedholes
the reader
th’ IS k ey is held on,
while
the punch
punched.
3-9
held on (provided
generates
blank
the reader
tape,
is on).
i .e ., tape with
Operating
Switches
The first
four switches
with
each
are toggles
is an indicator
POWER - This switch
and Teletype,
ment)
that
lights
applies
local
power
which
if left on,
allows
which
must be turned
at the right
while
power
and makes power
whose
located
the switch
to the processor
available
Almost
every
unit
to come on with
system power.
on and off at the processor
POWER on,
wait
a few seconds
clear
punch,
peripheral
equip-
has its own power
Exceptions
it is not called
the power
for reader,
and the punch,
console,
whenever
to allow
units
(memories,
the unit
and goes off automatically
and the control
units
are in remote.
and associated
panel,
is on.
to all external
controls
by the logic
end of the operator
include
which
for 5 sec.
to terminate
switch,
the reader,
is turned
After
and memory
on
turning
power
to
come on.
ADDRESS
STOP (ADDR
STOP) - While
is made to the location
is on,
and MEMORY
remains
on,
processor
displays
any fetch
write
DISABLE
MEMORY
cycle
call
switches.
read or written.
following
the stop.
stop occurs
whenever
At the stop the MEM
Throughout
for read-pause-write
(MEM
DISABLE)
100 psec to a request
panel,
causing
causes the processor
generates
the time that
only
The subsequent
this switch
on the processor
STOP and then
The sequence
SPEED - These switches
six overlapping
ranges.
for fine
within
initiated
is iterated
allow
restart
then
access
STOP light
the switch
a read request,
the failure
channel.
subroutine.
I/O
so the
triggers
a
MEM
of a memory
light
If the switch
The operator
to re-
on the bay 1 inis on,
such failure
can free the processor
RESET.
by an operating
at a rate determined
the operator
They include
each
is off,
for access turns on the NONEX
to hang up in the memory
REPEAT - Causes the sequence
control
- While
a PI request
INSTRUCTION
is held on.
is on, a memory
cycle.
spond within
by pressing
by the ADDRESS
the word
does not hold memory
separate
dicator
specified
this switch
key to be repeated
by the SPEED switches.
to vary the repeat
a 5-position
range.
3-10
rotary
as long as the key
interval
range
switch
from 3.4
psec to 8 set in
and a potentiometer
knob
Console
Disable
- In the lower
key clockwise
reader
disables
and punch)
right
corner
all operating
keys and switches
so no one can interfere
b
Figure
3-2 shows the indicator
main ful I -word
register
Since the results
ful primarily
for single-step
always
contains
the last word stored.
result
On bay 1 are the indicators
in 2.1~ are at the right
EXEC MODE
executive
as listed
in the text,
although
The second
indicates
light
location
change
The carry
flag.
the flip-flops
instructions
wherein
FE, several
quencing
flags
carries
stored
in AR and their
the information
for the flags
described
from the right
of the sixth
is the
the
flags are
outside
and carry
the carry
to the program.
column
operation
from the
flag,
which
of its assigned
flip-flop
and the light
states are transferred
is relevant
accumulator.
The remaining
The latter
are the AR overflow
with
(if any),
and is thus lit when
is the illegal
is trapped,
not be confused
storage,
are in many cases abbreviated
is at the bottom
EX ILL OP just below.
should
MB
column
is not in use).
to address a location
column
requires
Indicators
on the panel
user instruction
stop
in an accumulator
of the user flag
CPA ILL OP,
at an instruction
in a second
levels.
are use-
core
inhibits
is always
re-
off at
flags and the PC
flip-flops
to the flags
The remaining
above
only
them:
in those
flags are in
column.
Besides the flags,
ister
with
In the second
detect
column,
has attempted
when a UUO or an illegal
stop.
the right
in the third
not be confused
an instruction
system
PDL OV
these registers
contents
At the top of the third
from the 0 output
the three
AR, and multiplier-quotient
If the instruction
the word
the names engraved
that a user program
area and should
and their
and control
drawings.
the
those for the
Bay 2 displays
in memory,
the word stored
(or the executive
from those used in the logic
right.
contains
is driven
(except
Turning
of the processor.
register
are stored
AR contains
for flip-flops
is running
arithmetic
just performed.
MQ
switch.
Panels
operation,
end of the panel.
I’rg ht , which
routine
MB,
maintenance
upon the instruction
on the panel
the operation
of an instruction
entirely
is a key-locked
at the tops of bays 1 and 2.
buffer
depend
and for a double-length
with
Bay Indicator
panels
memory
registers:
MCI.
of the panel
the indicator
important
of the various
panel
control
processor
also includes
levels,
cycles,
shift
counter
and a multitude
special
3-11
sequences,
SC, floating-exponent
of flip-flops
that
and subroutines.
govern
regthe se-
The following
indicators
are of importance
the meaning
of a light
KEY EX SYNC,
running
If only
3.3b).
running
is on,
goes on and remains
If only
3.3b).
the sync light
is on,
goes on and remains
- If this light
a BLKI or BLKO,
Following
If CHF7
(bottom,
an interrupt
is on following
fifth
SPLIT SYNC
the start
- Indicates
it triggered
only
that
RUN
between
will
if there
incorrectly
THIS while
key function
the processor
is
has not been perincorrectly
(see
does not go on at al I, but the
key is pressed.
a PI cycle
that executes
the two parts of a character
if a character
is returning
(see
does not go on at al I, but the
is on following
be off even
the instruction
character
light
initiating
from left)
the light
has not been per-
may have been performed
the start
is
key is pressed.
the desired
some other
column
key function
presses DEPOSIT
on,
is off,
light
initiating
the operation
has occurred
a JRST,
an interrupted
lights
on until
a JSR in a PI cycle,
to restart
is off,
specified,
the processor
may have been performed
some other
both of these
If the key is pressed while
sync light
the desired
on,
the operation
on until
THIS while
presses EXAMINE
lights
RUN
(un Iess otherwise
operation
stop):
KEY DEP ST - If the operator
and it stops with
formed.
cycle,
both of these
the sync light
KEY DEP SYNC,
about
for an instruction
If the key is pressed while
sync light
CHF7
is given
in normal
KEY EX ST - If the operator
and it stops with
formed.
to the operator
from a break
operation
operation.
was interrupted.
and the processor
is
operation.
was a read-pause-write
a read request,
and the subsequent
call
restart
during
the preceding
fetch
a separate
write
triggered
cycle.
STOP SYNC
- Indicates
that the preceding
fetch
cycle
triggered
a read-pause-write
cycle.
PI OV - Indicates
that a BLKI or BLKO
performed
3-12
in a PI cycle
has overflowed.
memory
PI CYC
- This light
an instruction
goes on when
only
a BLKI or BLKO
if a second
that
that
If those two lights
either
synchronized
higher
on at the completion
(i ,e.,
of
the instruction
was
this light
is on whenever
that
was made by the program
simultaneously
the PI system
This can occur
has not yet been honored.
were already
is active
if a previous
by a BLT, or several
has just finished
servicing
are
and a request
instruction
If the system was already
waiting.
or synchronized
and the processor
PI OV and PI CYC
active,
requests
were
one of those with
priority.
A LONG
- Indicates
that
for address modification
MA = MAS
in the ADDRESS
is retrieved
no fast memory,
PIA 33, 34,
no channel
instruction
used an index
register
address.
displayed
switches.
that the main
PI CYC
RIM SBR - Goes on when
struction
of the preceding
by the MEMORY
This light
ADDRESS
is on whenever
lights
an address
is identical
stop occurs
times as well.
- Indicates
on even when
cycle
that the number
but may be on at other
EX PI SYNC
the address
or used an indirect
- Indicates
to that contained
remains
for the interrupt
PI REQ indicates
the system and some requests
a request
is required
of an instruction
are not on,
has been synchronized
activated
PI cycle
but is still
is honored,
overflowed).
PI REQ - At the completion
on.
a PI request
sequence
goes off before
the operator
just completed
the instruction
was a PI cycle.
is completed.
presses the READ IN key and remains
from a location
above
17.
The light
This light
is always
on until
on if the system
an inincludes
or if it is not in use.
35 - Indicate
the PI channel
assigned
to the processor.
If all
three
lights
are off,
has been assigned.
At the completion
of an instruction,
and the control
indicators
stop:
NRFZ,
MC WR,
discussed
NRF3,
DSF7,
SC and FE may have any configuration.
above,
MPF2,
the following
SC = 777,
3-l 3
lights
UUOFl,
Besides the flags
may be on at an instruction
EX UUO
SYNC
(always
on),
MQ36,
CRY0 V CRYI,
instruction
stop.
information,
is stopped
AR CRYO,
At a memory
AR CRY1 .
stop MC
and at least one other
awaiting
the return
is on,
the memory
left column
the console.
Refer to 9.1
None
RD will
light
will
be on if the memory
be on to indicate
from the memory
stop occurred
for further
of the remaining
subroutine.
cycle
the point
For example
in an examine
information
lights
should
be on at an
was used to retrieve
at which
a time chain
if KEY RD/WR
or deposit
operation
on the use of these
indicators
initiated
in the
at
for maintenance
purposes.
CAR0
READER
Figure
3-3
In-Out
c
Figure
3-3
(the latter
that
shows the panel
are described
are associated
with
that
in 9.1).
and Marginal
In-Out
contains
Indicator
the in-out
Check
Panel
indicators
At the top of the panel
the executive
system rather
fol lows:
3-14
Panel
than
and the marginal
are three
the in-out
8-bit
check
indicator
equipment.
controls
registers
These are as
MEMORY
(PR) - D e f ines the size of the block
10
times the number
in the block is 2
PROTECTION
The number
of locations
the register.
Each program
user attempts
access
to an octal
current
address
to an address
greater
instruction,
interrupt
location
RELOCATED
displayed
ADDRESS
row of indicators
bus.
the bus is reset following
PIA register
is stopped.
light
that
PIA (if all
PRINTER
three
PIA lights
but have duplicate
the printer
buffer
data
lights
a PI request
there
a priority
control
The address
by adding
should
assigned
bits.
The data
to it.
it automatically
always
in the I/O
be off when
shown
clears
the FLAG
by the associated
The lights
and printer.
labeled
(PTPl-8)
fer bits are numbered
- Contains
the last character
1 to 8 from right
3-15
TELE-
Both share a common
is actually
as each character
punched.
to left and correspond
PI
for the keyboard;
is being
-
REGISTER
and sta-
has a 3-bit
Whenever
specified
assignment).
buffer
lines
Each device
is made on the channel
keyboard
from MA).
and some of the control
and card reader.
is no channel
bits of a user
of the 36 data
the lights
are the buffers
eight
mitted.
DATA
Each
C(RLR) x
ten bits come directly
the contents
transfer,
devices,
is not shown because
PAPER TAPE PUNCH
of the
by ten zeros.
block
the most significant
of the PI channel
for two distinct
assignment
displays
keyboard-printer,
are off,
to the assigned
display
every
the number
goes on,
are actually
i .e.,
ADDRESS.
on the panel
punch,
in core.
in RLR followed
bus (the least significant
The remaining
contains
for any device
by ten ones,
in
If a
size.
skips the remainder
of a user block
contained
is relocated
by MEMORY
on the memory
tus bits for the reader,
that contained
at the top of bay 1 goes on causing
is the number
The bottom
the processor
in PR followed
the processor
the position
(RLA) - Th ese lights
address as it is placed
Since
than the number
(RLR) - Specifies
than for fast memory
2000 to the number
than
from zero to one less than the block
than C(PR) x 2000 + 1777,
in the block
user address other
one greater
to a user program.
channel.
RELOCATION
of the first
greater
and the CPA ILL OP light
on the processor
MEMORY
must use addresses
in core available
The buf-
to a frame
of
trans-
tape viewed
with
information
for bit
BIN
the feed
from bus lines
28-35,
with
line
edge.
The buffer
receives
the information
35 supplying
1.
(B) - While
hole 8, never
information
this
punches
28-35
any punch
is on,
hole 7, and punches
30-35.
While
operation
hole
always
6-l
the light
punches
according
is off,
to the
the information
is punched.
BUSY - indicates
FLAG
light
on bus lines
on lines
that
the punch
- Causes a PI request
goes off when
TELEPRINTER
hole near the right
the program
is in operation.
upon completion
supplies
another
of a punch
operation.
FLAG
character.
-
TTI DATA
board.
when
(Ill1
- Contains
The buffer
bit
lines 28-35
BUSY,
1.
with
is shifted
bit
questing
is transferred
to left so that
bit received
to the processor
- Th is p air of lights
BUSY goes on when
in ill
an interrupt.
the first
from the key-
ends up
over bus
1 on line 35.
FLAG)
is assembled
received
1 to 8 from right
in at the left,
The character
TTI (BUSY,
keyboard.
the last character
bits are numbered
a character
in buffer
acter
-8)
DATA,
a key is struck.
(at the left)
When
is for the
the entire
BUSY goes off and TTI goes on,
TTI goes off when
the program
retrieves
charrethe char-
acter.
BUSY,
while
TTO (BUSY,
a character
is complete,
FLAG)
is being
- In the right
transmitted
pair
to the printer.
BUSY goes off and TTO goes on,
TTO goes off when
the program
supplies
3-16
of lights,
BUSY is on
When
requesting
a new character.
transmission
an interrupt.
PAPER TAPE READER -
BUFFER (PTRO-35)
by the program.
bus lines.
the right
BIN
Characters
this
When
is off,
sensing all eight
BUSY,
FLAG
CARD
- When
information
number
of characters
questing
an interrupt.
reader
When
1.
operation
8 is punched
the previously
each
reads hole
6-l
and assembles
six
character
is brought
read characters
read operation
BUSY goes on,
in the manner
is retrieved,
FLAG
from the buffer.
motor
hole
in at
retrieves
are shifted
a single
character,
holes.
trieving
formation
hole
word.
each
to the
holes from tape are brought
each reader
in which
at the right,
to correspond
bit 35 receiving
is on,
into a 36-bit
BIN
bits are numbered
with
light
those characters
into the buffer
read from tape but no yet retrieved
of six or eight
end of the buffer,
such characters
left.
data
The 36 buffer
(B) - When
of only
- Contains
the reader
specified
goes into operation
by BIN.
When
BUSY goes off and FLAG
goes off when
FLAG
the program
is also set when
re-
the required
goes on,
retrieves
the operator
re-
the inturns the
on or off.
READER -
BUFFER (CRO-35)
to correspond
to the bus I ines.
in at the right
with
buffer
information
of one,
two,
information
retrieved
previously
as new ones come
are numbered
characters
over reader
from
signal
line
left to right
from cards are brought
lines 1, 2, 4, 8, A,
1.
The program
from a card is to be placed
or six characters.
be read per bus transfer,
the buffer
Six-bit
end of the buffer
bit 35 receiving
ifies whether
in units
- The 36 bits of this buffer
in.
3-17
are shifted
spec-
on the bus
If more than one character
read characters
B,
left
is to
in
BIN
(B) - While
each column
lower
this light
character
3 on line
1.
the reader
6-bit
a card
is read in binary
The first
is read as two characters.
half of the column
second
is on,
is the upper
If the light
converts
code,
(holes 4-9)
half
is off,
hole
(holes
character
are required
to fill
the program
gin a card cycle,
and the light
remains
fied
by the program,
trieving
the data
automatica
the buffer
a single
is full;
column
or only
three
an entire
DONE
depending
columns.
the
1, 2, 3) with
hole
mode
in which
to the Burroughs
requests
that
the reader
the entire
card
be-
is read.
of information
speci-
requesting
an interrupt.
Re-
off and clears
the buffer,
does not respond
may light
after
on whether
of the number
to the request
each
BIN
column
is cleared
before
or only
the
when
is off or on respectively,
and a full
also signals
which
buffer
contains
that the reader
of characters
six
has finished
in the buffer,
or
iam has occurred.
- Lit from the time the reader
lit at the same time.
ally
1;
the amount
goes on,
FLAG
line
the buffer.
on until
is one or two characters,
it starts another.
to begin
FLAG
card regardless
that a card
CARD
turns FLAG
is read.
contains
this light
I ly if the program
next column
until
the buffer
11, 0,
in a column
goes on when
- Each time
is from the
is in alphanumeric
BUSY - This light
FLAG
character
9 on reader
12,
reading
the Hollerith
and six columns
with
mode wherein
a card cycle,
It is possible
The program
but CARD
completes
for CARD
DONE
one card cycle
and BUSY to be
turns on BUSY to cause the reader
DONE
remains
on until
the cycle
actu-
starts.
EOF - When
on the reader
the card hopper
is empty,
turns on this light.
pushing
the END
It also turns on FLAG,
OF FILE button
requesting
an
interrupt.
ERR (CREL)
- Indicates
a validity
check
3-18
or read check
error
in the reader.
3.2
This section
reader,
describes
paper
is included
the normal
tape punch,
in their
DEC also supplies
OPERATION
OF IN-OUT
operation
of the photoelectric
keyboard-printer,
maintenance
manuals
and in the operator
for al I devices
a
Figure
Before
loading
This releases
reader
stack
a tape
vertically
is nearest
tape
so that
to inform
the program
the read head and the feed
Take three
from the front
in the left
bin is placed
Information
manual,
included
Paper Tape Reader
turn off the reader
that
with
reader,
for other
PDP-6
in a PDP-6
paper
devices
Operation.
system.
the reader
motor
of tape
an interrupt
Place
so that
the reader
the READER OFF key.
the front
mounting
in Figure
3-4.
Make
otherwise
tape
end of the tape
panel,
sure that
it will
on the
the fanfold
from the bin and slip the tape
to the folds,
3-19
by pressing
is unavailable.
the tape oriented
as shown
to correspond
Type 760
and it also requests
holes are nearer
or four folds
so it is threaded
tape
Tape Reader
tape may be inserted,
in the bin at the right
from the operator.
reader
in the reader,
the brake
channel
3-4
perforated
and card reader.
manuals
manufacturer
EQUIPMENT
i.e.,
away
into the
the part of the
not stack properly.
Once
break.
the tape
is properly
This also requests
the readin
mode
loader,
makes use of the reader
photoce
lifting
I Is.
After
loaded
lift
the READER ON
an interrupt
always
the program
signals
is located
has finished
reading
or turn the reader
faces the right
ter punching,
in a drawer
side of the drawer.
the tape moves
a slot on the front
before
to the clutch,
b
The punch
the program
turn on the reader
by sending
the READER FEED key,
to inform
k ey to start the motor
that
starting
which
the reader
the loader.
When
using
The program
moves the tape past the sensing
run out the remaining
the tape,
off so the tape
at the top of the left
Fanfold
may be slipped
tape
console
bay.
The punch
is fed from a box as shown
bin from which
the operator
of the drawer.
3-5
is on.
the
leader
by
out directly.
Tape Punch
into a storage
Figure
and energize
Paper Tape Punch Type 761
3-20
mechanism
in Figure
may remove
3-5.
Af-
it through
Toload
the punch,
first empty
top of a box of fanfold
in the center
frame
as well
at the right
Figure
tape
3-5.
open the top,
the console
PUNCH
Make
sure the tape is feeding
To remove
a length
to provide
an adequate
trailer
of tape).
Remove
length
in which
only
correspond
moval,
through
the tape
of the box has a small
the mechanism
end;
first
at the end of the tape
remove
the box from the frame,
After
loading
18 in.
PUNCH
leader
otherwise,
it will
sure that
not stack
stack over so the beginning
the tape
properly
left
hold
of leader.
FEED long enough
within
of the
the area
in the bin is stacked
as it is being
of the tape
the tape,
at the beginning
the tape from the bin and tear it off at a fold
Make
If they point
bin.
hold down
(and also
in
motion.
correctly.
in the storage
as shown
of tape
to feed approximately
properly
flap
Set the box in the
of the box),
at the wrong
tape from the bin,
feed holes are punched.
to the folds;
the bottom
length
Then tear off the
mechanism.
in the direction
long enough
and folding
of perforated
turn the tape
point
and thread
FEED key
flap;
the tape
the box was opened
direction,
the punch
the full
and thread
on the tape should
down
next
that extends
side of the punch
seal up the bottom,
box below
(the top has a single
as the flap
The arrows
in the opposite
the chad
is on top,
punched.
and label
to
After
it with
re-
both
name and date.
c
The teletypewriter
puter.
(Figure
It is actually
simu I taneously
.
3-6)
Teletype
provides
two independent
The equipment
plus start and stop control
of the unit
is a 2-position
unit
two-way
devices,
operates
characters
rotary
Keyboard-Printer
Striking
resembles
a key transmits
character
is printed
or the function
The line feed moves the carriage
return
operator
moves the carriage
must strike
typewriter
executed
only
vertically
to the left margin
both return
serially.
When
with
to the Teletype
only
and line
and printer,
operator
which
may be operated
per second,
Located
this switch
and com-
with
8-bit
at the right
front
is set to LINE,
the
system power.
that of a standard
a character
transmitted
OFF/LINE.
is on line and it goes on and off with
The keyboard
keyboard
between
at speeds up to ten characters
signals
switch,
communication
control
four rows of keys and a space bar.
unit connected
if the processor
with
a spacing
sends it back
3-21
Codes
to the printer.
of six lines to the inch.
but does not feed a line:
feed.
to the bus, but the
for the characters
to start a new line
on the lower
The
the
parts
of the key tops can be transmitted
on the upper
shift
parts (punctuation,
key when
control
key,
listed
striking
CTRL,
for some of the control
lists al I codes,
their
Because of recent
associated
striking
percent
Control
key.
the keys.
the appropriate
Codes
functions
ASCII
have no effect
assignments,
in the code,
character
key.
certain
on the printer
may be slight
sent back.
required
differences
the
down
the
for all characters
to the computer,
when
down
by holding
Codes
In such cases alternate
key positions.
characters
by holding
codes are transmitted
and the key combinations
there
for printable
sign) are transmitted
and some that are not can be transmitted
changes
with
by striking
ampersand,
the character
when
on the keyboard
acters
merely
but codes
Table
A4-2
to transmit
in the printing
characters
them.
char-
are listed
in
parentheses.
Figure
In line
with
repeat
button
mission
shift
the space bar below
REPT.
Pressing
of the corresponding
key may also be repeated
3-6
Keyboard-Printer
the keyboard
this button
code
Type 626
are four
and striking
red buttons.
any character
so long as REPT is held down.
in this manner,
but there
3-22
At the right
end is the
key causes repeated
Characters
is no repetition
that
of control
require
transthe
characters.
The red button
remaining
on the left,
two buttons,
These buttons
affect
ribbon
tabs are described
directly
are to figures
Manual
teletypewriter,
The
feed and carriage
return.
codes over the bus.
and the procedure
281 B (Technical
(RO) Teletypewriter
line
and do not transmit
All references
Bulletin
in the console
LOC CR, are the local
LF and
replacement,
below.
1 of Teletype
Receive-Only
LOC
the printer
Paper installation,
Vol.
BRK RLS, is not connected
for setting
in typing
horizontal
unit
35 Keyboard
and vertical
section
574-220-l
Send-Receive
00 in
(KSR) and
Sets).
Paper
The unit
has a sprocket
feed and uses 8-l/2
tray at the back
of the unit,
window
of the platen.
in front
the cover
release
the paper
guides
paper
button
with
offer
it up below
the sprockets,
the paper
To free
side.
the handle
form paper.
The supply
forms can be torn off against
To replace
on the right
by pushing
from the tray,
of the paper
and printed
x 11 fanfold
marked
first
remove
the platen
at the rear,
and press the local
line feed
in a
the edge of the glass
the upper
cover
old paper
for remova I, lift
the remaining
PUSH at the right
is held
of the platen.
by pressing
To insert
new
lining
up the holes at the edges
button
to draw
the paper
in under
the platen.
Ribbon
Replace
engage
whenever
the old ribbon
reels by lifting
mechanism
the empty
both
it becomes
or frayed
from the ribbon
the spring
is called
worn
guides
clips on the reel
out in Figure
4).
spring
the supply
reel,
out around
the other
clips
to secure
over the guide
guide
roller,
hook on the end of the ribbon
ribbon
and make sure that
ribbon
is seated
properly
roller,
spindles
install
through
the reversing
eyelet
and feeds correctly
too light.
side of the type block,
and pulling
Dis-
and remove
the reels off (the ribbon
the
feed
a new reel on the other
side.
Unwind
from the inside
the fresh ribbon
the two guides
onto
over the point
becomes
the old tape from one of the reels and replace
the reels.
and back
the printing
on either
Remove
reel on one side of the machine;
reel spindle
or when
the inside
of the arrow
in the hub.
3-23
onto
of
side of the type block,
of the take-up
has been wound
in operation.
on either
Push down
Wind
reel.
Engage
the
a few turns of the
the spool.
Make
sure the
Tabs
The horizontal
and vertical
slotted
wheel
surrounded
zontal
tab mechanism
tabulator
mechanisms
by a spring
is shown
on which
in detail
are mounted
in Figure
spat ing drum,
and a tab can be set by inserting
tabulator
when
pawl
lift
pliers
or equivalent,
Slide
the stop along
location.
Figure
the type
block
carriage
the spring
49 shows the vertical
line,
out in Figure
a number
The slotted
47.
is in the desired
in the desired
from use by turning
tabulator
but adjacent
direction,
mechanism.
With
against
With
B124 Card
Reader.
mation
given
Card
is similar
9 applies
and stacker
only
capacity
in the center
the following
READY
four
indicators,
Indicates
START button
Hopper
empty
Stacker
ful I
Card
iam (feed
unit
logic,
to the B122.
In Figure
that
the first
needle-nose
the spring
check
the processor
contains
is white,
here,
In both
3-7,
machines
the hopper
the operating
the other
three
has not been pushed
check)
when
VALIDITY
the pawl.
tabs
ON
3-24
button
is lit)
capacity
can control
infor-
800 cards per minute
the cards are read
is at the right,
buttons
of
the
but the maintenance
The B124 handles
one or more of the following:
(only
tension.
it into the slot at the new
it does not catch
Read check
Validity
the
apart.
to that described
of 2000 cards.
is a console
on the
Reader
in the control
and sensed photoelectrically.
at the left;
NOT
change
Its operation
in Chapter
and has a hopper
lengthwise
a trivial
The hori-
The slots in this disc al low vertical
1 in.
is a
it catches
The 8122 Card Reader handles 200 cards per minute and has a hopper and stacker
500 cards.
Each
is mounted
where
position.
it so that
tabs must be at least
-d
wheel
and reinsert
4.
of tab stops.
a tab stop in a groove
the tab stop out of the slot in the wheel
A stop may be removed
at any desired
are also called
the stacker
and indicators.
are red error
indicators.
Of
Figure
The reader
cannot
a not-ready
the above
respond
to turn power
off when
e.g.,
exciter
I amps,
cycle;
otherwise,
FEED CHECK
a card.
the FLAG
the reader;
solar
panel
motors
NOT
the reader
READY
ccl Is, photo
Type 461
READY
is lit.
is available.
power
condition
The program
This status bit
is off (the console
READY
due to a malfunction
There
amplifiers.
is continuous.
a NOT
cover
may check
is 1 on any of
is interlocked
When
error
condition
this
panel,
also supplies
requesting
light
status bit
during
the ERR light
any card
on the
is 1.
A signal
interrupt
a status bit to the program.
3-25
is on,
due to a jammed
a priority
in the read circuits,
is no read checking
stop as soon as the I ight goes on.
on the in-out
the signal
while
is also on and the reader
- Indicates
light
a NOT
read checking
The drive
Reader
not in place).
- Indicates
in-out
Card
if the reader
and also when
READ CHECK
processor
to the program
status bit to determine
conditions
3-7
card or failure
to select
to the processor
on the channel
turns on
assigned
to
VALIDITY
CHECK
indicates
light
bit
that
- This
an
light
invalid
punch
the ERR light
is on,
functions
only
combination
on the
processor
if the
VALIDITY
ON
has been
read
in alphanumeric
in-out
panel
is also
button
It then
is lit.
mode.
on and
the
switch
that
controls
reader
may
be turned
When
reader
error
this
status
is 1 .
Located
on the
reader
auxi
reader
console
contains
last
left
I iary
power
- Green
a 3-set
delay,
at the
processor
POWER
OFF
- Turns
START
- Turns
STOP
- If the
stops
when
RESET
END
the
- Turns
OF
off
With
this
main
power
switch
on,
on system
power
at
of which
light;
the
three
FILE
EOF
and
terrupt
on the
hopper.
button
the
off
the
turns
reader
the
the
control
main
processor
first
six
console.
below
the
runs
power
are
to the
on either
The
three
- P ressing
FLAG
red
this
reader
at the
console
momentary
contact,
the
motors
channel
the
signal
no other
turns
READ
when
processor
generated
supply
on the
by
turning
and,
on system
is on.
remains
on.
not-ready
condition
NOT
READY
FEED
CHECK,
exists.
light
and
the
reader
stacker.
I ights:
to the
power
auxiliary
button
button
on the
assigned
the
reader
is duplicated
when
provided
to the
check
white
lights
but
supply,
action
is illuminated
this
out
power
This
indicator
is in operation,
main
logic.
supply,
READY
card
on the
Button
the
NOT
current
The
which
console.
reader
off
on the
in the
is the
action.
ON
power
stacker
supply.
buttons,
is alternate
after
of the
or by turning
seven
POWER
side
CHECK,
the
hopper
in-out
is empty,
indicator
reader;
the
button
by the
button
can
lights
panel,
light
goes
be checked
VALIDITY
the
button
requesting
out
when
CHECK.
and
a priority
cards
are
bit
by the
as a status
turns
in-
placed
program.
VALIDITY
punch
character;
ON
- Th’ IS is an alternate-action
combination
when
read
the
switch
in alphanumeric
is on,
and
yellow
mode
invalid
is sent
punch
reader.
3-26
button
that
to the
also
is lit
reader
lights
when
control
VALIDITY
on.
An
unit
as an all-zero
CHECK
invalid
and
stopsthe
In addition
toggle
to the above
switch
hopper
under
is empty
With
READY
For operation
READY
turnon
should
be placed
plastic
weight
When
For normal
error
are on,
patible
punch
is indicated
codes and all
with
lf the reader
that
face
NOT
to prevent
jamming
mode,
every
invalid
column
it for improper
punch
READ CHECK
Usually
lit,
(note
light
this is either
check
a failure
error
attempts
in this unchecked
B122 Card
ON
is lit,
card.
A4-3
Cards
the
If any of
and the reader
a NOT
READY
push START.
Hollerith
char-
a VALIDITY
If a second
at-
lists the Hollerith
that the Burroughs
circuits
the failure
code
is incom-
3-27
the reader
a failure
part would
in a validity
part of the read circuits.
Reader.
of a lamp or solar cell
in which
is alphanumeric.
to read it result
have detected
go on together,
in this particular
if reading
on at system
To continue,
button
NOT
Place
READY,
for a valid
Table
the self-checking
of the read circuitry
However,
3 set
Punch).
is one section
for the Burroughs
to
whenever
is turned
to generate
card.
is checked
punches.
combinations
after
the operator.
stops at the end of the current
There
malfunction
the
it is not in use.
at any time
and the VALIDITY
and the reader
check
switch
toward
to stop at the end of the current
adjustment.
but several
from the processor
as the last few cards are read.
STOP may be pushed
and FEED CHECK
on a card,
RUN
when
the FEED CHECK
lit whenever
the 12 edge
READ CHECK
in a validity
stop with
and press POWER ON;
READY
If both
sulting
causes the reader
the main power
temporary.
error.
[local)
Push START to turn off NOT
used by the IBM 029 Card
stops with
switch
down with
is encountered
in the read circuitry.
read check
condition
can be started
on line,
push RESET.
to read the card fails,
character
operation
is in alphanumeric
CHECK
power
is left on with
the reader
If an invalid
tion
turn on the main
to the processor.
acter .
READY
switch
and then
and a LOCAL
is off.
in the hopper
causing
reading
tempt
card cycles
on top of the deck
is then available
condition,
(down),
and stacker
the NOT
the toggle
in remote
light
lights
Raising
is empty,
and the reader
the red check
generate
the hopper
light.
power
is full.
in the hopper
until
off line,
should
interlocks
the interlocks
or the stacker
the switch
the NOT
are also
the cover;
feed cards continuously
on.
there
a malfuncand may be
is in need of
is not detected
cause incorrect
timing
If no invalid
punches
check
it is likely
error,
For particulars
refer
as a
re-
can be found
to be a
to the manual
When
a card cycle
hopper
the card
begins,
and is pushed
The most probable
is first
into the read station
point
for a feed
contacted
where
to occur
it may iam in the feedways;
frequent
the pickup
card fails
to appear
motors
a feed check
error,
cated,
but put a duplicate
event
head cover
by lifting
moving
been
the knurled-head
the center.
off).
sliding
bolts
properly
turning
equipment
with
connected
system power
ticular
peripheral
unless a single
device
go on and off with
to their
on and off independently
to allow
permanently
use the readin
READ IN key.
initial
up.
OPERATING
console,
and in-out
unit
by
When a
light
that
goes on
has caused
upon
no FEED CHECK
a card stuck
cards,
is indiin the
remove
(an interlock
positions
the
removes
power
I head can be removed
and squeezing
Be sure when
by
them toward
replacing
the head that
engaged.
PROCEDURES
check
busses.
has been taken
however,
the memories
In general
all
and peripheral
memories
off line deliberately.
its own organization.
in some instances
Most
power
should
Whether
in-out
supplies
go on
a par-
control
units
must be turned
of the processor.
information
in the part of core that
loader,
card
for jammed
the photocel
vertical
straight
a
In order
To check
bolts are fully
is on depends
system power;
the FEED CHECK
it out horizontally
at the processor
to the memory
the rollers.
is in alphanumeric,
If necessary,
PROCESSOR
on system power
time,
the read station,
error).
and the knurled-head
3.3
After
check
turned
had been damaged
a worn or damaged
(if reading
The head can then be lifted
it is seated
to reread
it at its base and pulling
if it has not already
into the read station.
to move the card through
iam inside
either
a validity
edge
over by rollers.
in its place.
that a card should
may produce
if the trailing
the
edge of
is taken
is at the entry
in the prescribed
Do not attempt
stop.
but no cards are processed
read station
may fail
at the read station
and the drive
In the unlikely
knife
at the bottom
the feed operation
malfunction
If the card is bent,
handling,
by a knife
Read In
to be brought
is ordinarily
set the appropriate
into memory,
inaccessible
starting
This turns on the RIM SBR light
location
a readin
because
loader
is usually
kept
of the fast memory.
To
in the ADDRESS
at the top of bay 1, and while
3-28 switches
and lift
the light
is on,
the
any memory
address
from 0 to 17 provides
goes out and the processor
location
above
any other
a loader
left end between
which
mounting
mode regardless
panels
Place
the first
location
(0 is most convenient),
If the remaining
them
first
when
pressing
in the DATA
and lift
switches
and pressing
deposited,
EXAMINE
turn RIM MAINT
THIS,
check
should
do whatever
is requested
To debug
this switch
THIS.
locations,
DEPOSIT
so the operator
MEMORY
they
NEXT
switches
displays
for each.
After
at the
the loader
the
to the first
the word
in order
Although
loader
in
may deposit
may be deposited
the entire
NEXT.
switch
up holds the processor
set the ADDRESS
DEPOSIT
Operating
deposited.
by setting
all words are
by going
through
it
has been deposited,
Keys
accompanying
Every program
in the program
INSTRUCTION
each
is begun
by either
lights,
operating
program
for information
instructions;
on halts,
START or READ IN.
particularly
STOP may be latched
CONTINUE.
STOP and INSTRUCTION
By similar
may be single
effected
by using REPEAT.
The keys for the reader
0 r with
CONTINUE
program
or not.
Putting
toggle
PROGRAM
the operator
tape
On a halt
COUNTER,
and
may restart
by
CONTINUE.
using INSTRUCTION
SPEED controls.
but
doors on bay 2, on a bracket
at the console,
make note of the console
INSTRUCTION
programs,
the double
then EXAMINE
material
and so forth.
the operator
pressing
and STOP keys,
down.
should
requirements,
from any
must make use of a small
it is a good idea to check
b
The operator
using the CONTINUE
switches,
words are in consecutive
in the DATA
displayed
word
behind
taken
is retrieved
mode.
2L and 2M.
of any action
The light
of fast memory,
an instruction
the operator
of core,
is mounted
loader.
stepped
out of readin
in the bottom
to core instead
mode whenever
Read in can be single
RIM MAINT,
readin
readin
key takes the processor
To deposit
labeled
17.
leaves
access
the REPEAT switch
latched
down,
use of the MEMORY
stepped
from one memory
and punch
on and the progmm
the program
and both
call
to the next;
INSTRUCTION
CONTINUE
low-speed
at any time whether
The stop keys may also be pressed at any time,
stepped
speed can be varied
STOP and MEMORY
may be operated
3-29
on,
single
but ordinarily
by the
keys,
operation
the processor
a
can be
is running
these are used only
for
single-step
or low-speed
operation
ten keys use the key cycle
with
that
IO RESET.
on throughout
Of the initiating
program
is actually
only
running,
stops the processor
thus possible
tion
there
AMINE
lights
is running).
THIS or DEPOSIT
in the left column
key function
the halt
was not performed;
instruction.
If only
no way of knowing
are meaningless.
whether
it was executed
If EXAMINE
precautions
essor time.
While
the operator
may use EXAMINE
However,
operator
when
RUN
the processor
relocation
by the EXECUTE
PROTECTION
lights
key,
is stopped,
and protection
is relocated
to the block
specified
How-
The halt
in-
and it is
key manipulation
pair
lights
at the console
while
of SYNC
are on,
while
the
that
EX-
and START
the corresponding
was performed
was performed
prior
to
but there
is
and thus the console
RUN off,
are inhibited
lights
the SYNC
are compatible
including
panel,
by MEMORY
3-30
that
during
light
with
available
to him.
the
mode.
in an instruction
interrupt
so
operation,
the operating
size as indicated
unless the address
proc-
a key cycle
in single-step
addresses
or a priority
RELOCATION
are sharing
all of memory
instructions
than the block
also understand
user programs
THIS with
as between
at the top of the in-out
should
the processor.
and the instruc-
the key function
must be observed
must be smaller
The operator
Either
RUN is cleared
THIS is pressed with
for a key function,
occur.
stop.
cycle,
the halt or after,
THIS and DEPOSIT
supplied
the
is performed.
that
must make sure his actions
user mode any address
will
is on,
STOP is
of the execute
the key function
during
THIS or DEPOSIT
does not go out but the key function
There are also special
is on,
occur),
while
goes off) at the same time
If both
is on,
stop MEM
halt occurring.
the corresponding
panel.
light
light
stopping
holds for any wanton
check
if neither
a SYNC
without
(RUN
halt should
stop nor a memory
the time
occur
Even through
THIS have any effect
of a program
between
on the bay 1 indicator
is running.
at a memory
RUN at the beginning
THIS is operated,
as is the case
by the 0 state of RUN so
an instruction
is any chance
halt should
function
a program
CONTINUE;
two instructions
the same caution
The remaining
(unless of course a program
is neither
between
If a program
a clear
THIS and DEPOSIT
to be triggered
(of course
see c below).
is gated
while
stepping
MEMORY
by clearing
for a key cycle
is completed
processor
tiated
single
do not use these keys if there
struction
the key cycle
EXAMINE
i .e.,
of these keys inserts a key cycle
ever,
into
by pressing
keys,
if only
can have no effect
memory
can be restarted
stop considerations
some operation,
entry
key manipulation
RUN remains
on.
to initiate
For seven keys,
inadvertent
the program
(for special
In
ini-
by the MEMORY
for an illegal
address
is for fast memory,
it
(the RELOCATED
ADDRESS
is
displayed
take
the processor
to determine
what
If this light
there
instructions
from either
switch
lowed
the operator
must observe
while
a program
associated
An interrupt
interrupt
instead
is being
with
processor
priority
is waiting
when
IOT that overflowed),
subroutine
will
be skipped
the break-i
nel on which
as the program
.e.,
the interrupt
when
EXECUTE
In addition
for
illegal
EXEC MODE
can switch
from the console.
The
IO RESET, but this also clears
priority
to observing
is pressed,
the processor
is on (indicating
executed
routine.
is continued.
goes off,
and all
lower
that
goes on,
channels
the PI instruction
will
instruction
be taken
by the
and the JSR to the
the processor
and both
will
remain
continues.
CAUTION
Never under any circumstances
press more than one initiating
key
at a time because the processor will try to perform both functions
at once.
Note that in low-speed
operation
one of the continue
keys is always on, so although
EXAMINE
THIS or DEPOSIT THIS
can be used while the processor is running,
they cannot be used
in low-speed
operation.
3-31
If an
the preceding
Furthermore,
priority
of the following.
performs
from the console
PI IN PROGRESS
are al-
from the console.
This wi I I turn off PI CYC,
the program
interrupts
the user-executive
must be aware
one executed
a non-IOT
was requested
If both
The operator
including
If PI CYC
PI REQUEST
but any other
mode.
key whenever
the operator
interrupts,
to be the iump to the break
required
in this circumstance
from the console,
instruction
is on.
PI assignments.
stepped.
switches.
if EXEC MODE
two PI cycles
user restrictions.
will
at the top of bay 1
However,
mode by pressing
over any instruction
of the one in DATA
was a block
single
between
the appropriate
all
the lights
to executive
in the use of the EXECUTE
has priority
request
including
all
from the console
are legal
or protection.
the processor
by executing
equipment
be exercised
restrictions
“hold”
wil I return
may be made from user to executive
should
only
an IOT may be executed
mode to the other
most of the in-out
Care
and instructions
is also no relocation
or a UUO
executed
must observe
is on (this can happen
are legal;
and PI CYC are off,
instruction
The operator
All addresses
he can do.
is off but PI CYC
user instruction
an illegal
out of user mode.
the same interrupt),
not all
Furthermore,
at the right).
wil I
the chandisabled
c
Ordinari
iy I NSTRUCTI
Emergency
STOP is used for single
ON
but it can also be used for an emergency
this purpose
that
the turnon
temporarily
certain
can stop at one of these points
pulse generator
mal clearing
once
output
in the execute
it has been
If the processor
cycle
should
cycle.
down
BLKI,
programmer
BLKO,
correctly
over:
PC is static,
never
goes on,
lights
display
attempts
would
Both of the above
ever,
causea
that
then
single
The
sequence.
should
to the turnon
the processor
disable
the nor-
of the key so that
step operation.
Once
RUN is
without
certain
seeming
routine
light
to accomplish
anything,
do not
checks
have been
Although
nonetheless
IOT will
the processor
for the channel
as it is
it is recommended
the processor
But a condition
made,
repeats
will
that
perform
a PI
cause the processor
the instruction
to
over and
is on but the PI IN PROGRESS
on indefinitely
light
(the AC
code).
an instruction
switch
isoff),
The attempt
from a memory
that
the lack of any instruction
to address a nonexistent
but if the JSR for the break
memory
should
is not connected
retrieved
usually
attempt
to the bus
is interpreted
results
by the
in an interrupt
to go to the same memory,
go into a loop.
loops include
the complete
stop at the completion
never allow
an XCT that executes
into a loop that
only
and PI REQ at the top of bay 1 remain
to retrieve
channel,
malfunction
a one-shot
the computer.
this happens,
the IOT instruction
as a UUO.
the processor
with
until
the PI REQUEST
and PI CYC
on the processor
not interfere
instruction.
When
(and the DISABLE MEMORY
processor
apply
triggers
cycles;
For
in a loop.
the end of a main
to hang up the machine.
for any non-IOT
lf the program
Both features
or JSR be used in a PI cycle,
hang up in the PI cycle.
will
it will
Representative
for an inept
and address
its reaching
procedures,
get caught
whose output
RUN in case a hardware
hang up or be running
a DEC Technical
possible
only
latched
in the instruction
and maintenance
should
a pulse generator
if a loop prevents
IO RESET can be used to clear
clear,
call
pulses
also clears
step operation
stop if the processor
of the key triggers
inhibits
Stop
the processor
itself
of an instruction.
to finish
or if a programmer
keeps jumping
back
main sequence,
There are other
an instruction.
puts a UUO
to the instruction
3-32
so pressing
cycle
INSTRUCTION
program
If a program
in location
without
41,
ever
STOP
failures,
should
how-
include
the processor
completing
goes
a main
se-
The key thus halts
quence.
program
attempts
ory subrorftine.
STOP clears
Hardware
example
RUN,
if PI CYC
transfer,
can cause
fails
to honor
includes
IO RESET.
If th c procctssor
no chance
it will
of hanging
an interrupt
without
cannot
affect
the time
request
the memory
freeing
chain
will
access.
stop following
up a memory,
inhibit
merely
subroutine
when
If it has, hold on MEMORY
write.
3-33
For
the processor
to clear
in a block
cycle.
by clearing
For any
RUN and press-
the reset occurs,
For this situation
press INSTRUCTION
stop.
step to the fetch
to be sure the processor
IO RESET.
but INSTRUCTION
cause a loop in which
on each
the subsequent
hangs up in the mem-
cannot
If MQO refuses
the processor.
the lights
the processor
is on and the
by IO RESET.
succeeding.
returning
MEMORY
this situation,
do not free the processor
is within
STOP and then check
so that
loops that
call,
while
If DISABLE
can then be freed
wil I loop forever,
a memory
read part of a read-write
TINUE,
to set,
the request
hang up a nvmory
MEMORY
the time chain
and the machine
the processor
loop that
likely
Interrupting
cycle.
that is not on line,
any access to a memory
malfunctions
keeps trying
these in the address
it will
it is preferable
has not stopped
the processor
STOP to clear
RUN,
to press
following
STOP and press MEMORY
Once
very
the
CON-
has stopped
with
and then press
CHAPTER
DRAWING
Accompanying
charts,
both
each
logic
drawings
dashes (e . g.,
number
the sheet
number
If a drawing
to treat
CD,
wiring
master
In general,
the only
associated
flow
describe
the standard
the other
the same serial
manual
number
contains
personnel
peculiar
logic
wiring
list CL,
wiring
in the manual
drawings.
purposes
than
machine.
manuals
every
numbered
use the prints
of a given
portion
for work
to the installation.
4-l
that
type
that
on the equipment
A size).
does,
in the man-
should
use the
0, corresponding
is assigned
serial
reflect
system
because
0.
they
to
But if a
Therefore,
that
to
a different
the difference
is so modified.
of the standard
list
that are reduced
have drawing
those drawings
machine
Drawings
system are serial
BS,
are the
of each manual
use.
to
cable
are usually
of equipment
Drawings
the equipment
from standard,
for that
unit
ID,
module
at the machine
for the manual.
accompanying
as the lowest
working
number.
schematic
utilization
chapter
both
is written
diagram
piece
and their
for the PDP-6
Al though
in some way
the drawings
the figures
sheets,
letter
list WL (the last three
drawings
personnel
several
left of the drawing
list ML,
draw-
if more than one
interconnection
The maintenance
only;
dash,
by
(see next
the individual
codes are block
for a given
with
is the type
number
a revision
some typical
TD,
serial
includes
engineer,
PW, module
types of engineering
rather
should
diagram
included
in this and other
differs
timing
cable
most of the prints
unit
code;
power
by another
at the lower
by the project
is labeled
the second
specifying
If a drawing
flow
is in four parts separated
size;
code
preceded
is a type
FD,
WD,
and
production
number,
diagram
for instruction
B size and printed
tenance
signed
number
of D-size
drawing
is the drawing
letter
of sheets are written
being
drawings
for the equipment
particular
of the logic).
list MDL,
diagrams
ual are intended
serial
a section
primarily
Every
indicating
the third
sometimes
diagram
drawing
digits);
CHARTS
consisting
diagrams.
is a letter
a number,
after
flow
part
FLOW
The drawing
or a mnemonic
To the left of the number
SD,
and wiring
code.
three
and the number
system diagram
tions
(usually
is revised
the right.
however,
the first
may end with
is required
UML,
and a type
and the last is a number
drawing
each
number
AND
set of drawings,
schematics),
D-166-4-EX):
ing (the code
diagram
is a complete
(block
of the equipment
paragraph);
prints
CONVENTIONS
PDP-6
a DEC drawing
4
it describes,
have
although
main-
show any varia-
All drawings
included
also written
on the prints
ings associated
in front
in a manual
with
metic
number
The letters
Processor
Figures
memories.
Figure
are usually
prefixed
The complete
from
indicate
numbers
manual
charts
describes
drawings
computer.
a logic
every
Th ey also
or some special
module)
are not shown.
drawings
tified
indentify
cation
code
code
made
Pin designations
e.g.,
that
plugin
each
may be formed
“0”
present
not only
the Arith-
Types 461,
626,
760,
the fast and core
publications
in-out
devices
for Chapters
of every
at any module
The standard
to showing
is shown
5, 6, 7, and 8.
letter,
power
pins (A to D on
of every
logic
element,
the
Circuit
type
is always
iden-
Below
by adding
panel
the type
number
For example,
is a lo-
the location
F in bay 2 (in the lettering
it to distinguish
the pin letter
used in the
and ground
and one or two digits.
10 in mounting
element
pin that carries
location.
catalog.
logic
connector
the function
has a slash through
merely
in the
in separate
drawings
show the function
connector
numeral
reproduced
used in these drawings.
in the DEC module
one
unit
described
and the common
by type and by physical
as given
appears
DRAWINGS
level.
In addition
up of one digit,
drawings,
LOGIC
voltage
circuit
number
2FlO represents
the logic
it from
to the module
letter
on
“0”).
location
code,
2FlOH.
The frame
o'y,
every
by the type
processor
show the type of signal
signal
devices
and notation
diagrams
devices
and show both
4 and a series of logic
the conventions
are block
“M”
the manual
includes
in-out
draw-
number.
for the arithmetic
for Chapter
for four
for in-out
type
which
are
To differentiate
on the figures
for this manual,
units
legend.
These numbers
a code designating
are prefixed
by the appropriate
by chapter.
the drawing
may not be included
on drawings
logic
numbers
those of another,
4.1
The logic
above
a figure
for the memory
in a series of flow
figure
166 but also the control
system
This chapter
right,
(the code
“AP”
Type
and 761.
in the lower
one manual
of the figure
manual).
are assigned
containing
or peripheral
out device
the arithmetic
device
control
unit
pa.neIs are designated
smaller
block
the circuit
symbols,
type
number
requiring
requires
A,
only
processor
a major
a few
B, . . ., even
and the console
portion
logic
though
mounting
they
such as those representing
and location
code
of a bay,
4-2
bays 1 to 4.
is designated
panels,
inverters
as bay 1.
Each memIf an in-
it has no bay number;
may be mounted
single
are written
includes
in any position.
and capacitor-diode
near the symbol,
and the inputs
the
For the
gates,
and
outputs
are labeled
mation
are written
by connector
inside
together
in a drawing,
are then
written
side the boundary
have
by the prefix
“R. ”
of such a module
prefixed
connectors
2DE17-EB).
on both
Only
the upper
for logic
the upper
one identified
by the prefix
On the logic
diamond
.
the assertion
1 or 0, true or false.
places
depending
sertion
level,
for ground
carrying
diode
gate,
transition
edge,
i.e.,
required
the logic
and triangle
level
of the same polarity,
pulse
by open
the line
polarity
(i.e.,
Sometimes
of the logic
edge
the triangle
a leading
necessary.
4-3
triggering
edge
has a negative
amplifier
occurs
function
is shown
Occasionally
a
by a level
at the leading
immediately
showing
the direction
vdc;
or capacitor-
by a composite
and a triangle
as-
Sometimes
is triggered
is indicated
indicates
represents
to it is at -3
the output
that
in different
is at ground.
of a pulse
of the level,
but this is not
line
no
diamonds
levels
or
by open
and represent
if a function
the
is shown as a diamond,
are shown
categorically
corresponding
In these cases,
on a trailing
level
module
by a triangle
and closed
assertion
For example,
polarity
is shown
requirements
may have different
to the input
2DE17-DT,
at the rear of panel E.
polarities
voltage
connected
pins are
two rear connectors,
the S connector
input
neither
connector
Thus for a double-height
D,
upon
true when
triggered
also have
by ‘5.”
true when
the assertion
is negated).
only
The location
so pins A to D of the lower
usually
are represented
function
shows the assertion
for the input
just in-
are identified
be designated
by pulses whose
the gate;
a pulse output.
An event
showing
depend
levels
would
lines,
is considered
If the input
transition.
number
are written
connectors.
at a pin connection
requirements.
is shown
produces
infor-
appear
and type
and the front
2DE17,
the lower
is provided
is considered
level
the diamond
a diamond
polarity
when
a logic
which
input
the function
at the input.
triggering
with
the function
assertion,
line
gate
logic
two front
the power
present
that satisfies
A given
upon
with
Such modules
of signal
gating
polarity
the same module
the location
(pins on this module
“RI”
timing
Similarly,
location
pins on the rear connector
e.g.,
receives
These polarities
difference.
represent
the type
triangles.
line:
is at the rear of panel
In DEC convention,
and closed
logical
drawings,
height,
signals.
the R connector
from
and
and the pin letters
and back;
letters,
connector
are available
in 2DE,
boundary
front
letter
connector
mounted
the circuit
elements
in a dashed
are double
panel
blocks,
lines cross it.
by two panel
by the appropriate
logic
the module
Some modules
larger
If several
the signal
is given
all
may be enclosed
once within
where
Some modules
With
the block.
they
only
pins.
after
the
symbol
the opposite
of the transition
by a composite
in the in-out
diamond
equipment,
a wide
pulse
composite
is used to produce
signal
the polarity
pointing
a delay
for this is a pair
of the triggering
in the direction
LWd
NegOiwC
Ncgotive
Assertion
Pulse
on the pulse
showing
signal
PUlSe
Posilt
is shown
merely
by an arrow
Clomped
Lood
INVERTERS
ve
Negative
I
I
I
I
XVY
x~+(--$~
l--~-.E---~~~~A
A
FF(0)
FFtl)
s
FF(0'2J4-FF("
FF
T
T
E
Figure
4-1
Logic
4-4
Symbols
The
the second
w
CAPACITOR-DIODE GATES
6102
2011
poikity,
Nonstondord
Sign01
bb
Trailing
edge
Tronsi?ions
b
-----------__
the pulse
edge.
flow.
SIGNALS
I--1I
trailing
-going
Positive-going
Ground
Assertion
Any nonstandard
transition.
of signal
events
the first
of triangles,
bb
0
Level
by triggering
The upper
part of Figure
capacitor-diode
gates.
catalog.
With
connector
pin letters.
shows the signal
in Figure
The remaining
show the function
the requirement
that
to form an AND
or OR gate,
a pair
4-1.
inverter
with
labeled
a common
the blocks
output)
connection
level
gates,
both
level
by pulses
signal
and
conventions
shown).
Since
labeled
merely
gates with
the gates
all
also contains
Inputs
elements
function.
CLK,
only
except
from
X,
left
though
to right
labeled
connections,
value,
gate
(s)in
these
learning
all
assertion
gate,
at the left,
implies
function
only
once,
input
or
po-
and
of a gate
de-
a given
net
a
may be replaced
at the top,
change:
is an input
(A)
Of course,
levels
has
Because
is of opposite
number;
outputs
no logical
labels
gates are AND
of its inputs,
and all
an in-
the logic.
level
the logical
includes
but
and a
D shows a pair
to both
gates,
where-
one.
flip-flops
Some examples
bus driver
in an AND
it is shown
pulse
is shown at C.
to a gate are generally
a gate
the pulse
enter
by a pulse
then
(the in-out
The tilde
polarities
such as
as eight
(a diode
when
or an ORgate-theequivalence
may be replaced
through
and the assertion
at
Blocks are used to represent
code and a type
Since
in the usual way.
configuration
an AND
a location
as indicated
to a module,
have common
or 11 % V .I)
with
are connected
emitters,
as many
such nets invert
“Q /\I’
indicates
are labeled
circuit
PG, clock
in which
Each block
All
ator
and diode
modules
internal
as shown at B.
the output
Y and Z each
of the circuit
inputs
function
inverters
grounded
that
in which
tion
pin and internally
way consistent
in the drawing
by connections
its truth
passing
gates
is produced
are shown
affecting
its logical
input
inverters
without
as levels
other
and
codes,
show other
Thus if two single
may be inverted
in an OR gate.
shown
of AND
4-l
location
in the simplest
and may be ignored
and the tilde
upon
element
function
may be used as either
single
of Figure
for inverters
to the DEC module
numbers,
logical
pin connections
pends
of type
be shown.
logic
are always
with
to the inputs.
output
logic
collector
as many as four
verter
larity
of every
if the gate
gates are always
OR (v)
sections
the individual
the individual
an assertion
are examples
pin connection
uses capacitor-diode
no actual
in the introduction
lettered
for the appropriate
gates with
equipment
every
However
of ihverters
by a block
4-l
fully
and the symbols
drawings.
drawings
A in Figure
designations
These are described
the symbols
for the PDP-6
The logic
4-l
BD, solenoid
appear
as blocks
are delay
driver
4-5 DLY,
SD,
that
pulse
majority
contain
a mnemonic
amplifier
gate
MAJ,
abbrevia-
PA, pulse
gener-
dc adder
DCA.
Clocks,
pulse amplifiers,
coupled
pulse outputs
cuit.
is triggered,
is grounded,
(usually
generators,
during
the delay
type of symbol
rectangle,
terminals
at the positive
output
if the negative
at the negative
output
if the positive
period.
than
the 4303
convention
sented
diamond
in both
by a fifth
The principal
diamond,
advantage
any need
to invert
conditions
appear
as the input
source
nected),
one must know
both
FF(1) at negative
actually
Direct
in the example
which
grounding
ways
a direct
clear
is drawn
with
name
the signal
(i.e
.,
input
that
output
output
is asserted
is
neg-
is shown at E (the same
and the 6131
the polarities
DC Adder).
associated
is at the left and the O-out
appears
correct
of the signal
at the bottom
one of the flip-flop
In this
with
either
terminal
state
is repre-
have a separate
output
terminal,
assertion
is that
there
as an input
truth
values.
indicates
When
terminal
name and the assertion
at the l-out
those
terminal
net:
all
a flip-flop
state
of flip-flop
logical
output
is used
of the flip-flop.
to which
level.
is never
the signal
To
line
is con-
For example,
the signal
FF; at ground
assertion
terminal.
of the rectangle
at E, with
that are not gated)
is shown
at the left.
center.
collectors;
to a logic
the enabling
(the output
levels
terminal
at
are at the sides of the flip-flop:
A flip-flop
An unbuffered
the O-in
flip-flop
may also have a complement
may be set or cleared
such a function
may be represented
in various
on the logic
in either
by
of the
shown at F .
Connections
simplest
is usually
right
that
are shown at the bottom
inputs
output
to such a cir-
an indicator.
at the O-out
pulse
Delay
showing
level
the input
a flip-flop
the two states at both
originates
originates
inputs
the left.
input,
assertion
represents
Some flip-flops
to drive
the signal
the physical
Two gatable
pairs.
in the drawings
determine
this signal
twice,
the name of a signal
net,
that
the “0”
in showing
to a logic
have a logic
integrating
S and T are drawn
In normal
represented
the 4303
The symbol
of the flip-flop.
by the left
of transformer-
pulse appears
other
also represents
have a pair
When
pulse appears
delays
delays
of the block).
a positive-going
One-shot
and some one-shot
shown at the right
or a negative-going
grounded.
ative
pulse
between
flip-flops
way consistent
shown
corner
with
entering
on to the next
are shown
showing
the lower
fl ip-flop,
all
left
ways
pin connections.
corner
The clear
of the leftmost
and so on through
4-6
flip-flop,
the register.
drawings,
line
always
for an entire
then
in the
register
out of the lower
If the flip-flops
in a
counter
have count
entering
the center
see the program
shifting,
all
connected
(e.g.,
internally
are therefore
because
flip-flops
numbers.
if all
with
is made
gates,
output.
inputs
perform
which
a register
flip-flop
of the input
for this,
and a gated
gated
its inputs,
drawings.
Since
containing
flip-flops,
The flip-flop
being
available
pulse
through
pin,
are
to produce
that
the signal
each
at
pin.
of the input
through
of
the termina-
there
is also a
containing
to the AND
delay
the outputs
until
etc.,
is connected
emitter
polarity,
instances
each
NPN
signal
at that
isdelayed
is an input
is
used for inputs and out-
change
in many
1 output
i .e.,
and no attempt
are made
circuits
gates,
the block
than the duration
three
and
them have no pin
or “v,”
are made
includes
at a connector
4-7
“A”
pulse amplifiers,
MB,
and diode
and arrows
state change
race problems.
SBR, which
are
by a negative
to these flip-flops
logical
card
no pin numbers
in many cases there
is not available
more rapidly
the flip-flop
lo-
at the pin to indicate
gates
inputs
on the logic
to prevent
besides
input
but without
is inverted,
function,
input
These gates
the AR,
inverter
and do not even
circle
take place
many
pulse amplifier.
the PA output,
function
other
e.g.,
However,
bits of a register
as a small
flip-flops
the subroutine
the diamonds
to individual
through
to the many modules
module,
than
other
merely
are not shown
pulse
by logic
no logical
drawing
condition
merely
are
most transfer
instances
and the output
is gated
(e.g.,
for
a module
the flip-flop.
to the regular
level
of the left
within
shown between
or “s v.”
to left,
are connected
registers,
In many
and the connections
right
in the same way as a count
to the module:
‘%A”
from
and pin connections
6-5).
a ground
modules
containing
symbols
Figure
either
polarities
terminal
To compensate
logic
gates are similar
symbol,
in the IO-mc
elements,
input;
these
input
State changes
flop
signal
on the logic
processor
are internal
Such gates are labeled
Since
the flip-flop
In addition
to AR,
one in which
In some cases pulse
pulses.
logic
In all
gate are of the same polarity
e.g.,
to indicate
is shown
hybrid
internal
is shown
8-7).
with
connections
th e appropriate
fol lowers.
tion
the input
(refer
signal
going
at the center
if the flip-flops
on the module
rectangles
numbers
to a given
nonstandard
puts.
as small
If these
a ground
are included
shown
from different
however,
the shift
in Figure
is usually
and leaving
If flip-flops
are on the same modules
inputs
labeled
1).
register,
modules
flip-flop
shown
5-l
pulse
flip-flop
gates must be shown;
as a shift
codes or type
included
side of each
Figure
register
gates for a given’
MQ
of the right
of the shift
the count
and outputs,
counter,
the shift
cation
inputs
a flip-
gate at the PA
internal
I y to the
flip-flop
clear
whenever
input
(see the SBR at the left
a subroutine
is called
also, sets the flip-flop
gate
is the return
pulse
All
triggers
logic
right
drawings
and
lettered
of logic
ence
are laid
elements,
both clears
out with
rectangular
to the circuit
are often
in “Figure
5-6B6”
included
would
a single
in figure
mean
triggers
input
to the PA
the return
the time chain.
numbered
drawing
references.
the circuit
is used
the subroutine
of the subroutine,
the SBR and restarts
Because
that
to the PA; the other
map coordinates,
top to bottom.
coordinates
gate
At the completion
output
A to D from
An SBR (or its equivalent)
The same pulse
the input
from the subroutine.
the PA, whose
5-2).
from any time chain.
in an SBR, enabling
pulse
in Figure
located
1 to 8 from
left
to
may contain
a number
For example,
a refer-
in block
Bb of logic
draw-
ing 5-6.
4.2
All
signal
source.
eral
names
in PDP-6
Each register
drawings,
letters,
which
ginating
are mnemonics
with
associated
one drawing,
or only
appears
if not,
associated
it is merely
transfer
prefix
code
other
hand,
logic,
the readin
mode
on one of the drawings
corresponding
figures
The name of a signal
of the two registers
cause
the transfer
fore appear
registers
first
logic
an arrow
is always
to the register
shifts
name;
code
information
between
the entire
with
is associated
register.
of one to three
register
AR and its
all with
is AR SH LT.
On the
with
read
in and is shown
All prefix
codes and
4-2.
The arrow
the receiving
to another
invariably
register
the type of transfer
Numerals
signal
includes
points
and its name must therespecifies
and the register
representing
the names
to the left be-
register
8 in AR is AR8 and bits O-7 in MB are MBO-7.
4-8
ori-
of drawings
KEY RIM SBR.
The name of a transfer
but also
sev-
as part of the signal
a number
from one register
them.
associated
bit
in Figure
code
naturally
of AR to the left
is designated
it occupies
the arithmetic
require
which
whether
and its
of the name of any signal
For example
flip-flop,
of the signal
mnemonic
may appear
the contents
logic,
designation.
system,
has a single
and AR subroutines
of transfer,
acts on less than
control
the function
and at the beginning
at the left
transfers
in the signal
and the direction
if the signal
appended
with
title
subroutine
for the key
that
and each
to the name.
that
are listed
both
part of one,
logic,
AR, and the pulse
NOTATION
indicate
This source
prefixed
flag
that
logic
in the drawing
in this part of the logic.
name;
SIGNAL
not only
bits
the
involved
bits are merely
Operations
that
affect
name.
bit
only
half
of a full-word
The state of a flip-flop
8 in AR is AR8(1).
S ince
transfers
a symbol
in parentheses
transfers
all
into
of course
transfer
of zeros from register
Since
B now contains
pond
to ones in A,
larly,
the transfer
cleared
before
the transfer,
by setting
are transferred
possible
al I bits in B and then
the contents
into
B while
pulses at once
ones in A,
B -A(V).
transforms
bit
to the right
(a shift
gating
are also quite
FC(E)
restart
PSE causes memory
for subsequent
AC0 always
dressed
refers
zeros.
control
to accumulator
two sources
produces
contained
setting
clears
function
this effect
is B-A(O).
of A and B.
Simi-
OR function.
If B is
of A to B.
The same effect
If both
in AR are cleared
is necessary.
point
The signal
and
This is a iam
in time,
from A can provide
A.
would
the zeros and ones of A
at a single
into
bit
the same information
or clearing
the transfer
a given
ones and also corres-
to zeros
the outputs
The actual
contain
zeros.
occurs
that
This action
function.
pulse
originally
The pulse
have fairly
We have
PC+1 INH
causes
the word
(if the instruction
OR function
it is
the gating
that
levels
triggers
both
names:
inhibits
MQ
name,
bit
to
in B if the
the word
in the same register);
the program
pause
a second
AC2 refers
and any pair
following
in
AR COM
so far but the names of
E and then
to deposit
is 17,
correspond
SH RT shifts
to the accumulutor
AC address
4-9
a given
incrementing
in location
B that
of A and B, and is written
pulse signals
the store cycle
the same signal
bits-of
that complements
obvious
been discussing
0, but AC2 refers
can have
clears
from one bit to another
to fetch
SAC2
), which
in B the exclusive
descriptive:
storage;
by the instruction
No more than
ones into
in AR.
the transfer
the contents
such as B(0) -A(1
is a iam transfer
the word
as the clear
A and B both
the signal
is AR +(O).
that
the iam transfer
types of signals
complements
levels
no prior
gate
AR,
is a Iso indi-
B(J)“A(J).
in A is 1, produces
Most other
clears
B bits corresponding
the B outputs
is labeled
that
transferring
of two registers:
types of transfers,
i.e.,
corresponding
so that
S ince
For example
the 1 state of
of transfer
p ro d uces the inclusive
and B +A(1 ) transfer
B-A(J).
name.
in B the AND
the transfer
to ones in AR set,
to switch
There are other
MQ
B -(0)
and is written
for the transfer
transfer
A to B, B ‘A(l),
then after
the type
The pulse
produces
e .g.,
states,
but rather
that
LT or RT to the register
in parentheses,
B is as follows:
therefore
to B simultaneously
those corresponding
the signal
in bit positions
of ones from
be produced
i.e.,
in A is in the 0 state.
the 0 transfer
of pulses
the register
A to register
bit
transfer
to as a 0 transfer
ones only
and the pair
transfer
following
is not usual ly referred
by appending
by a numeral
in effect
the bits of AR,
of B if the corresponding
are indicated
is represented
cated’by
zeros
register
counter;
to wait
for a
accumulator.
the one ad-
to accumulator
must have opposite
0).
polarities
so that
polarity
symbol.
differentiated
the source
of every
Whenever
two
by adding
signal
is uniquely
logically
an extra
equivalent
letter
or number
MR CLR and MR CLR A are equivalent
pulses.
nal through
signal
signal
a bus driver,
name.
buffered
part
If the outputs
signals
The pulses
the buffered
of a flip-flop
are indicated
format:
first
the prefix
code
or number
and letter
combination
the fetch
time chain;
DST13
not always
in exactly
flow
to determine
charts
is pulse
the order
are NRT0.5,
NRTO,
valent
and together
are the first
operations
number
pulse
CHT8B
culate
follows
in a pulse
subroutine.
lines.
name
Thus the first
subroutine,
pulse
and the next
The SBRs and most control
names
in which
the ‘IT”
4-2
the next
output
signals
the following
pulse,
these
logic
conjunction
explanation
with
consult
chains
calls
through
also have
equi-
separate
In character
following
following
FMTO,
the
in normalize
indicate
by ET3.
usually
by the subroutine
INSTRUCTION
return
the
from a
the exponent
cal-
an SBR, is FMTOA.
similar
three-part
DECODING
of instructions
as the gating
The purpose
of the tree
them with
of every
the discussion
always
pulses
labels
3 in
by an “F. “
appear
gates and to correlate
three
is followed
chain,
the time
by a number
These pulses are
should
two
in the chain,
govern
the same three-
followed
But in most cases a letter
multiply
shows the decoding
in the figure
give a detailed
pulse
triggered
that
is replaced
sections.
CHT8A.
have
time chain.
cycle-the
the
numera I.
ET0 and ETOA are logically
is ET1 but this
in the floating
flip-flops
is a tree which
pulse
module,
FT3 is pulse number
the first
cycle,
sig-
at the end of the
all
“T,”
and the.reader
in the execute
but precedes
4.3
Figure
subroutine
In the execute
The next
the letter
are
for example,
name and the state
For example
associated
they
to the flip-flop
For example,
expect,
sequence.
pulse
indicates
then
the
an equivalent
“8”
and subroutines
the pulse.
one might
NRTO.1.
CHT8
cycles
the chain,
names;
produces
externally
13 in the divide
that
the proper
return
but equivalent
main
specifying
signal
the flip-flop
and
the same polarity,
by the letter
are buffered
naming
have
its name
to one of the signal
is indicated
for the various
by
signals
If one logic
by a ” B” between
in the time chains
identified
logical
levels
in the flow
function;
4-10
the instruction
charts
is to al low the reader
the instruction
of the decoding
from
codes.
in 5.3.
The
that are described
to gain
familiarity
No attempt
for this the reader
hardware
register.
should
is made
in
with
here to
use the tree
in
Any code
placed
in IR is converted
fetch,
execute,
andstorecycles
tion.
The decoding
are converted
into signals
as gates
to enable
decoder
for several
the first
output
bits.
begins
and branches
together
a single
type,
at several
the mode or action
only
and it gates
of the groups
extends
of two,
or binary-to-octal
individual
outputs
parenthetical
but the hardware
which
outputs
enables
act
a second
In others
decoding.
the figure
the line
IR bits,
These primary
the decoding
part way across
instruc-
for al I remaining
and then generates
the length
three,
of the tree,
or four bits shown
decoders.
only
where
signal
items are listed,
does not decode
names are shown
the coding
the bit
as shown pro-
configuration
into
in-
outputs.
When
IR receives
to generate
output
an instruction
one of eight
is the decoder
output
IR is clear
perform
command
t ions.
level
Between
corresponds
to prevent
code.
individual
use the basic
that
classes with
point
instructions
there
is no further
common
entries
format
and character
decoding
to three
conditions
corresponding
are
on the I/O
in the figure
are adjacent).
operations.
as these
ORed
ones.
The decoder
command
the command
the eight
composite
while
level
to
of the drawthe
IOT instrucfunctions.
At
the device.
are the decoder
outputs
for the six instruction
order,
but are instead
The configuration
001 indicates
24 codes are not used.
level
If it is not a user IOT,
1 O-1 2 into
bus to select
At the top
At the bottom
to generate
If the second
4-11
generate
instruction.
of bits
bits are decoded
in bits O-2.
of the actual
to three
the decoding
three
in the figure.
zeros
also
(these are not in numerical
decoding
the first
shown at the left
an illegal
instructions
IR bits 3-9 are placed
cycle,
the generation
Other
attempts
and causes
the top and bottom
that
which
for an IOT,
is generated
Some of these
the same time
levels
a user program
output
in the instruction
command
an instruction
when
ing is the decoder
primary
by a flip-flop
awaiting
a UUO
code
for a UUO,
is conditioned
classes
listed,
most significant
classes.
in the
the particular
In some cases the output
group
Most
only
that must occur
to execute
the three
instruction
by binary-to-quarternary
Where
with
for the latter
into
events
sequences
bits.
extends
positions.
bit configuration.
to govern
in turn act as gates for further
position;
decoded
dividual
the eight
outputs
the line
at a single
appear
in the figure
instruction
of bits are actually
for each
duces
at the left
levels
special
of the remaining
represents
are decoded
Groups
and various
more bits whose
of branches
gating
representing
decoding
For the former
a number
into
octal
digit
If bits 3-5
in the code
contain
listed
so
the floatingis 0,
111,
1, or 2,
IR6-8
are
decoded
for two unused
ing scale.
for the specific
(NR
because
is dependent
the gate
is used only
basic ‘instruction
represents
a number
a full-word
transfer
digits
determines
specifies
the necessary
the pushdown
into
level
instructions
float-
bits 4 and 5 are
condition
any
which
for round-
command
level
is called
only
IR 2Xx,
which
class with
single
IR bits.
For these
AR,
instruction
word.
by
output
as a UUO.
The last group
transfers,
decoding
enabled
which
like
the effect
of bit 6,
the outputs
of IR3-5
instructions,
and
of IR6-8
generates
the true
are two additional
a iump,
and the three
in IR 2XX
instructions,
also enables
are fixed
on the nontransfer
whether
which
make
the decoding
register
half:
that
up
of
by 101 in the first
of the destination
by bit 3 determines
4-12
fetch
For division
IOT,
there
the
and bits 7 and 8 are decoded
is specified
part
the state
of instructions
IR BOOLE
group,
Further
configurations
execute
the instruction,
is specified.
to enable
name by any configuration
for JRST,
of the 16 instructions
bit 3 determines
from
For the JP group
100 in IRO-2.
Bits 4 and 5 determine
three
to those for the Boolean
the half-word
level
of miscellaneous
that actually
IR6 determines
Second
but for multiplication
a group
of a signal
configurations
or fractions.
The next
operations,
bits.
and divide
specifies
The 01 configura-
from bits 7 and 8.
levels,
sequence.
to the six instructions
instructions
and further
of control
The decoder
respectively.
as integers
digit
of the word.
multiply-divide
for multiply
(the absence
op code).
the configuration
which
and divide,
octal
and specific
and negating
are to be treated
for the shift
wherein
for the mode,
a composite
pair
level
0 or 1 in the second
swapping
separately
These modes are equivalent
to determine
bit clears
upon
command
and store operations
if it is not executed
and subtraction
the half
fetch
store the miscellaneous
Another
ceive
generates
a further
instructions
corresponding
that
for the mode.
lR3-6
only
Either
multiply
on the multiply
of IRb-8
to an unused
levels
an entire
The logical
subroutine,
to the primary
groups.
the operands
and jump
corresponds
addition
return
instruction
and for these,
is not dependent
normalize
to fixed
are determined
decoded
the decoding
control
6, but
that control
as 01-)
of IR6 act as gates directly
command
the
the levels
whether
6 is actually
enable
instructions
bits 7 and 8 are decoded
of 2 and 3 correspond
and store operations
bit
bit
instruction
for which
of bits 3 and 4 (shown
which
upon
by
the single
and
bits 7 and 8 for the mode.
class corresponds
of small
of bits 5 and 6 generate
net that
operations,
instructions.
The second
tion
character
the floating-point
instruction,
ROUND)
floating-point
octal
the five
A 1 in bit 3 indicates
decoded
ing
codes,
three
shall
re-
a 1 in either
half
shall
then be
A 1 in bit 6 causes
set to all ones.
destination
register
receives
7 and 8 are decoded
The remaining
tions
the half
word
compare
an accumulator
AC or C(E)
ACCP
type,
instructions
is compared
is compared
against
MEMAC
command
AC for a jump or memory
the masked
bits.
shown;
for the logical
level.
by bits 6-8.
because
figures
the arithmetic
processor
that
when
gether
intermediate
actual
clear
both
the subroutine
Each flow
insignificant
pulses
halves
is shown
by breaks
against
and the four common
show the flow
of AR).
If an event
three
generates
the comparison
tests
the action
on
8 swaps the mask
as
by bits 6 and 7, for the arithmein the term for bit
otherwise
8 because
no instruction
levels
in-out
devices.
operations
that
These figures
in a manner
that
is from the logic
(for example
is prefixed
can be executed
ARLT -(O)
show every
is equivalent
drawings
event,
to the actual
unless
ET1 is shown
italicized).
clearing
and ARRT +(O),
by
which
by CFAC,
the time
pulse
is routed
shown along
a vertical
line.
Except
AR,
tovia
gating.
of time
such as the delay
in the line.
the other
the
by these instructions.
of all
in turn triggers
to the register
specifies
the skip or jump condition
appears
charts
implicitly
which
in which
any of which
whether
group
CHARTS
(the terminology
AR +(O),
group
C(E);
and a 1 in bit
instructions;
of operations
only
instruc-
the ACCP
bits 3 and 4 determine
or MEMAC
FLOW
is based on a sequence
intervals,
group,
is used only
are flow
pulses are shown
interface
chart
the
Bits
compare
00 in lR3-4
instructions,
is determined
for ACCP
generated
in this chapter
ly it triggers
i .e.,
the mask is C(E),
the condition
The level
in the hardware
class,
of IR5 determines
is not used by the ACBM
and in so far as possible,
Certain
so that
register.
class includes
in the two classes determine
the test level
The remaining
comparison,
The state
4.4
and timing
of the source
C(E) or E, and the MEMAC
In the ACBM
bits
comparison
this port of the condition
gating
the transfer
are for the arithmetic
the types of MEMAC
for a skip.
The remaining
the test.
need appear
half
For the arithmetic
a direct
A 1 in bit 5 specifies
before
tic comparison
before
The former
either
zero.
of bits 3 and 4 specify
the composite
the opposite
(ACBM).
against
and a 1 in bit 5 indicates
configurations
from
011 and 110,
two IRO-2 configurations,
either
to be swapped
for the mode.
and the logical
in which
the operand
pulses
across a pulse amplifier
Pulses always
4-13
appear
or inverter,
in ellipses
time
and events
for
between
in rectangles.
A pair
of single
horizontal
is I isted
the delay
by double
lines
time,
with
(numbers
an arrow
along
to occur.
several
vertical
the left
the events
associated
lines
through
in Figure
associated
. require
branch
with
only
with
must be satisfied
from a horizontal
the pulse
line,
below
in an ellipse
line
the conditions
that
the arrow
indicates
In a rectangle,
written
to continue
shown
the lower
A flow
listed
for the event
for flow
A break
sequence.
the pulse.
in order
the lines
the subroutine,
terminates
with
between
the flow.
the calling
that
must be satisfied
address,
shows the main
and are shown,
figures
Those instructions
and at the left
4-13
that
in 4-8;
in Figures
right)
for the cycle,
in Figure
that
a con-
to the right
along
the line.
are written
instructions,
to 4-10.
the sequence
other
above
the
is shown
at
for each
IOTs,
goes on independently
to special
instruction
e.g.,
are shown
an IOT
4-14
shown
require
take
isrequired
of processor
may call
place
outside
of the operands.
4-l
4-6,
4-7,
sequences
SC subroutines
1 and 4-12.
execute
cycle
of the processor
at the beginning
operations.
the main
in Figure
the basic
the entire
chart
4-8.
by special
in Figures
flow
from
the fetching
that are executed
for the
sequences
in Figure
in tables
entry
AR CRY0 at the
can be called
following
subroutines
that
clearing
and at the right
sequences
operations
charts
exits
cycle
than
The flow
to provide
the execute
some of which
of these
use the key cycle
sequence.
in columns
and deposit,
events;
of instructions
arithmetic
In-out
in,
and AR subroutines
These special
instructions,
such as examine
by any instruction,
by the execute
are shown
possible
all
4-3
must be made,
of events
operations,
show all
in Figure
show the execution
and the special
4-14;
a sequence
including
memory
respectively,
IOT sequence.
operations
show the main
and store cycles
shows the IOT
as the special
require
4-4 and 4-5
are timed
processor
such as start and read
The basic
4-8
into
Some console
that are not produced
sequence
The remaining
pulses.
others,
fetch,
of the cycle.
Figure
that
Figure
beginning
4-8,
Key functions
time chain
operations
(Figure
entry
the key cycle;
instruction,
are shown
initial
the key time
sequence.
and all
which
4-3.
to the main
wise
ends with
to continue
term identifies
continues
a line
a delay;
lines.
The key cycle,
shown
the flow
on a line
indicates
to restart
references);
written
vertical
the upper
are figure
to the left of a colon
A condition
call;
that
line
must be asserted
by the subroutine
indicates
thjs path
written
When
returned
a vertical
that
a subroutine
in parentheses
the flow
dition
or the signal
indicates
term names the pulse
terminates
lines breaking
or the end,
as well
are
but other-
For every
action,
the initial
by the
bits
Figures
instruction,
registers,
hardware;
the decoding
codes,
further
of the logic
E may mean
an address
either
The states of the processor
the effective
address
and
in a priority
interrupt
gate,
cycle
Since
the complete
whose
events
are listed
timing
lines
does not use the second
tions
of the logic
half
generates
that are performed
possible
can easily
events
ing the tables
described
instruction)
here
the fetch
and
the PC inhibit
the processor
from the console).
is
For all
in-
In al I cases,
registers
and
the modes for fixed
multiply
and
modes even
though
(in the following
in Figure
pulses are shown
the call
and special
the time
4-5,
(i . e . , those
those
in tables.
of an AR subroutine;
instructions
In a table
the subroutine
ET6 to ET9 are omitted
CYCLE
instruction
chain
when
entry
is at the
the instruction
time
4-7,
pulses
it is assumed
sequence
is explained
levels
it is impossible
cycle.
sequence
and 4-8.
FLOW
and gating
of the execute
how the specific
4-6,
is defined
EXECUTE
by the execute
in Figures
cycle
The pulses from
in the description
determine
or return
(e.g.,
contains
of the cycle.
subroutine,
that
MA always
at the end of the sequence.
indicate
4.5
tion
from the context.
the fina I gates
by the execute
pulse at the right.
cycle,
cycle,
executed
flags),
or its contents,
at ET0 whenever
situation
in the
registers,
is evident
cycle;
of the
to it,
for the execute
entirely
vertical
the return
control
gates are those that control
is being
as performed
is given
an accumulator
the fetch
is some special
by the execute
The action
locations,
PC is incremented
or the instruction
is shown
instruction
individually.
are timed
double
main
there
in terms of the instruction
are not decoded
Every
that
the
to the meanings
the meaning
following
The initial
decoding
in italics.
memory
location;
decoding,
exactly
AC may mean either
are shown
unless
The
is given
or the addressed
the store cycle)
gates are I isted
left,
gates.
final
explanation
be understood
that are executed
that control
for ET3,
and
does not correspond
is not shown.
is not shown as an initial
divide
list the complete
drawings:
registers
It should
cycles.
structions
and 4-13
sense (i . e . , in terms of accumulators,
but in the notation
execute
to 4-10
and the initial
whenever
in the instruction
programming
4-6
of events
for it.
with
the descrip-
However,
for instruc-
to consider
the multitude
For most such instructions
produces
the desired
sequences
that
with
.
4-15
the reader
is familiar
the reader
result
A few of the less obvious
of
by inspect-
are,
however,
the action
of each
’
In a half-word
the fete h cycle
AR and a word
which
transfer
(Figure
depend
upon
left)
in MB,
in AR,
so ET0 switches
half
ET1 swaps the two halves
is to perform
any operation
ET4 jams the specified
the other
half
by setting
either
the memory
result
in location
thus any mode
include
is in both
it,
E.
subroutine
requiring
transfer,
is called
at ET3.
for the bidirectional
transfer
with
limited
the possible
the word
let
US
word.
-.which
transfer
of the logical
to be used as the mask is in MB,
refer
to the latter
ET0 completes
necessary
. ET1 then
same time
it adjusts
AR corresponding
ET4 then moves
not been handled
as the data
the construction
produces
the data
word
the test word
and
it would
for MOVS,
function
4-16
and
Exceptions
to be moved
by ET1 in MB;
AR negate
be necessary,
but the
requires
are quite
in AR.
a
straightforward
the mask as the test
if this is
and at the
by complementing
However,
and these correspond
of MB,
AR to MB,
At this point
cycle,
For convenience
the two halves
or transferring
lost.
cycle
so for this instruction
of it with
zeros from
to MB.
the
At the end of the fetch
and set actions
the mask has been
mask,
4-6
to be tested
OR function)
word
the word
(no instruction
ACBM.
by transferring
on
in MB and AR at ETO.
or MOVM-the
in Figure
group,
for the complement
must be a subset of the ones in the original
Then
AR to MB for
the swap is made
of the mask by swapping
seem that
AR.
at ETlO.
so that
instructions
and the AND
to AR and the data
to the opposite
the action
from
from MB to AR would
and the word
to ones in MB (the exclusive
be in
the store cyc le to deposit
MOVN
instructions
and
If the instruction
in MB.
is necessary
for other
the test word
of the source
is transferred
is in MB only
compare
word,
word
in
mode and transfers
words are already
for either
a transfer
The other
the source
of AR and completes
are to be swapped,
is required
to one direction).
exception
only
is the source
the AR to MB transfer
transfer
By ET4 the result
an accumulator
ET1 also clears
require
the correct
may happen
Of course
that
words after
is in AR at the end of the execute
includes
whatever
Then if the halves
is to be negated
that
the result
in which
ET0 performs
half
those modes
in E usually
such as EXCH
of these
requires
At ET1 0 the result
i .e.,
places
of the source
the appropriate
if required.
storage
MB and AR are switched.
gate
into
which
half of the destination,
In most instructions
MB and AR.
if the word
word
or self mode,
instructions
In a full-word
half
always
is to be from one half
on the unused
and destination
MB and AR for the memory
If the transfer
then
cycle
of the instruction
MB to AR for the self mode.
of the destination,
of the source
and the mode specifies
The execution
MB and the destination
the positions
i .e . , the fetch
the mode;
from memory
the destination.
4-6,
bits of
ones from MB to AR.
the clear
action
has
any ones now in AR
exactly
to all
the ones
within
the masked
time
pulses clear
again
to restore
the adjusted
sequent
word
word
in AC.
4-7),
the current
program
PC,
9 and
programs.
one greater
is transferred
the second
since
address
than
of other
changed
half
according
listed
from
The store cycle
cycle
performs
the iump address
If the program
does continue,
the processor
stops,
of the location
anything.
and may be used for error
PC displays
that
contained
4-17
of AR,
and
for subbut
deposits
is
the data
a series of operations
and after
the processor
and complementing
is not necessary,
from
MB to MA.
three
the original.
of the execute
PC to MB,
next
it is available
in the table
instructions.
the
to the contents
AR at the same time so that
transfer
action
zeros to MB,
does not deposit
10 transfer
that
transferring
the store cycle
but the JRST can halt
When
into
For the clear
in MB.
AR,
The bidirectional
it has not been
seems to be pointless,
pointless,
word
At ET9 the test is made
of the requirements
in AC unless
pulses
in the data
the test word.
because
In JRST (Figure
positions
these bits by complementing
data
storage
available
bit
the iump address
the JRST.
that
Pulses 5 and 6 transfer
has been
transferred
these operations
halts
to
are
in maintenance
and MA displays
an address
CHAPTER
SEQUENCE
MAIN
This chapter
the main
cribed
describes
control
in detail
struction
here:
register;
calculation
execute
cycle
of IOT
in Chapter
over
test conditions
operations
necessary
of the result.
The
events
chapters.
The many arith-
transfers;
between
affect
register;
and timing
the arithmetic
and data
transfers
that
it from the in-
and storage
in other
in which
four are des-
and decoding
operations,
6 with
and control
cycles,
it from the instruction
are described
instructions
the console
the processor;
to trigger
control
specific
Figure
registers;
Chapter
Chapter
to produce
7
8 includes
the processor
the program
required
sequence
and inputare discussed
them are described
in
whereas
lower
right
provide
the
CONTROL
continuous
control
keys are momentary
of events
for the various
levels
contact
operations
is shown
that gate
switches
that
certain
operations
allow
the operator
The hardware
or to stop the processor.
console
turns on computer
of Figure
power
inadvertently,
CONSOLE
in Figures
5-l
that
provides
and 5-2
(flow
4-3).
the operator
of master
switches
sequences
and timing
When
clear
5-l
pulses.
the flags
and the processor
power
at the console,
comes on in the 1 state,
These pulses
and they also trigger
MR START clears
system
of basic
the way
6.
In general,
chart,
maior
of the operands;
address
5.1
within
from memory
and memory
or logical
and explains
Of the five
subroutine
but any arithmetic
Chapter
instructions
The various
equipment.
retrieval
are described
inputs
and decoding
to the extent
of individual
the memory
the decoding
here,
from memory
only
subroutines
to console
of an instruction
address;
is discussed
and data
response
CONTROL
on instructions.
retrieval
of the effective
describes
output
operate
calculation
for the execution
metic
the processor
elements
5
the master
and the in-out
l/O
interface;
clear
system
turning
Integrating
on a clock
that
RUN so the processor
clear
and the master
including
MR CLR clears
5-l
the 4303
all
flip-flops
the major
control
provides
cannot
start
Delay
a string
begin
(Figure
5-2,
in the priority
registers
in the
operations
right).
interrupt
and flip-flops
intheprocessorproperincludingali
every
new operating
sequence,
memory
continue
pulse).
The master
wishes
to clear
several
special
formation
start
flip-flops
5-l
Several
example,
running,
clears
Since
all
stead.
four
flip-flops
Then,
the start
flip-flops
th is purpose,
flip-flop
and the processor
the key cycle
the signal
chain.
KTOA triggers
cycle
triggers
the following
two gates
POSIT while
of the figure
This chain
that
the processor
to trigger
and
must carry
in-
gates
the appropriate
furthermore
memory
to begin
5-2
normally
is set in-
in these operations;
sequences.
left
the processor
flip-flop
if the operator
start flip-flop
the power
of Figure
set
to enter
has been
set,
through
the
clear
5-2
selects
allows
the
RUN (0) so that
EXAMI
There are,
NE or DE-
the final
from
period).
to start
is not running.
goes directly
functions
sequence.
by the condition
if the processor
For
has been
KEY MANUAL
during
by two pairs
is set at the begin-
flip-flop
a new main
the level
continue
is
of RUN (1) with
if neither
KTOA and KTl
condition:
the processor
two main
either
in the upper
of pulses only
if
KTOA,
flip-flop
functions
net is disabled
between
only
sync flip-flop
between
However,
keys generates
the RUN
while
chain,
For
flip-flop.
for the events
sequence,
console
the processor
from the net in C5 causes
sequence.
and nets that
of the RUN
start
the AND
a pulse generator
is running,
they
from the keys but rather
of the operation
is broken
bypass
than
specifically
The flags
to two or more
the appropriate
provide
(the entire
triplet
KTl;
a state
the corresponding
the signal
at the end of the main
level
common
in the key time
If at the end of a main
is to continue,
of this
mode.
may be performed
or deposit
from the net in C3 causes the processor
The turnon
a store
with
flip-flops
the insertion
states.
net in the top center
however,
functions
A pulse
is running,
Pushing any key other than the twoSTOP
key time
events
two of the nets at the left generate
of the start
the operator
from the keys and switches,
not by levels
right).
The sync
control
and when
by MR START because
and deposit
but for examine
cycle.
other
(IT0 or any equivalent
in the executive
to control
are governed
if the processor
ning of the execute
key
examine
(upper
flip-flops,
clear
the input from the EXECUTE key to affect
these two operations
of sync and start
only
inputs
functions
of the nets AND
it is not in operation.
operation
to another.
shows the logic
a net in A3 allows
console
the beginningof
of any new instruction
by the power
are cleared
of composite
of every
the processor
from one main sequence
a number
operations.
only
system or place
control
half of Figure
generate
and at the initiation
is generated
the I/O
The masterclearalsooccursat
at the beginning
i.e.,
(see below)
over
The left
SBRflip-flops.
pulse
KTOA to KTl
in
because
it is assumed
previously
stopped
the processor
continue
somewhere
is the only
triggers
the MC restart
at KTl .
For read
in,
sets the readin
mode
memory
is operating
replace
is exactly
the 16 flip-flop
equivalent
in the readin
to start;
is taken
than read
in,
the CONTINUE
the appropriate
of Figure
address
into
loading
MA,
deposit
next,
increment
level
triggers
another
read
that
(upper
operations,
start,
This pulse places
cycle.
instruction
Either
in the program.
of a store cycle
by clearing
that
next
into
the processor
by
51 Dl).
associated
with
in the center
next,
an
instead
the computer,
it from the DATAswitches.
for the processor
is inhibited
MA and transfer
and deposit
send data
of
deposit,
Also shown
in the key
loads the DATAswitches
and the assertion
read in,
the processor
and instruction
into
of the DATAI
cycle
so that
the operator
RUN at ETO.
cannot
STRUCTION
but the logic
the processor
or the program
The executive
stop the processor.
gate is bypassed
5-3
continue
in operation
As long as RUN remains
a JRST; a user program
STOP key,
Examine
clear
operations
PA (see 8.3).
setup
right).
a new
the DATAI
the IOT has selected
the instruction
triggers
AR and load
which
the transfer
the various
operations
on drawings
PC) but most are shown
all
permanently
console
net is in Figure
are shown
and deposit
ADDRESS switches.
clear
through
involving
in, examine,
The three
it.
and execute,
CPA indicates
cycle
Start,
it from the console
AR.
and starting
by the key time pulses
in
mode whenever
but the clear
(the clear
of
read
stored
For
= 0).
operation,
at the bottom
operating
17 ( I, MA18-31
for normal
(such as operations
5-2.
is the gate
KEY GO
the flip-flop
produced
function
portion
Following
beyond
to normal
When
respects,
program
return.
the master
left.
core registers
In all other
has
Memory
at the lower
may keep a loading
keysso that READ IN can be single stepped
6
A few of the functions
drawing
clears
unused
switches
operator
subroutine
completion.
shown
of the fast memory.
and the processor
the
KTl does not generate
flip-flop
thus the operator
that
the memory
for the subroutine
the normally
mode,
from any location
KTl
in which
subroutine
registers
area of memory,
an instruction
other
in readin
is l-but
by inhibiting
waiting
continue
the processor
cycle
operation
an SBR is legitimately
KTl
.e +, RUN
is “running”-i
it at the end of a memory
Th,is is why memory
clear:
that
set,
by setting
all generate
RUN
the completion
performs
of every
one instruction
may stop the computer
program
The operator
clears
clears
by a pulse generator
(Figure
store
after
at the end
it by a 1 in bit
it by pressing
5-2)
10 of
the IN-
that is also connected
to the key.
The action
this ensures
that
through
RUN will
the PG is slow
be cleared
even
compared
to the processor
if some malfunction
should
time
chains,
interrupt
but
the normal
procedure.
The other
console
functions
do not place
fers AR to MB at KT3 and enters
would
normally
be in MB after
the processor
the instruction
retrieval
cycle
in normal
operation.
at the point
from memory
at which
of this single
instruction.
In the four examine
KT3 requests
read or write
as required
and sets KEY RE/WR
deposit
information
in memory,
memory
subroutine,
the MC restart
The upper
right
portion
If the REPEAT switch
held on.
operator
of Figure
generates
period
then
To use the memory
is set.
To repeat
retriggers
repeat
start,
function,
instruction
SV
Since
STOPkey
deposit
to repeat
operations,
may be repeated
normal
KT4 to trigger
retrigger
KT3 triggers
the read/write
return
from store
KEY GO.
the instruction
cycle
All
cycles
but the execute
groups
of instructions,
fetch,
and
both
the
in the main
cycle
and
perform
the start
only
only
PROCESSOR
the add
time
subroutine;
subroutines.
5-4
change
the operator
when
which
examine
is already
the
stop
each instruction,
need
not use the
and
or deposit
interrupts
start
is
must hold on
for the four examine
the appropriate
at
key
the memory
the operator
Furthermore,
RUN,
the
flip-flop
causes
1, but it does
CYCLES
instruction,
operations
the memory
state
mode.
flip-flops.
and these four are described
store can call
memory
cycle,
of the
be running
if one of these operations
to instruction
sequence:
in,
To
Cl).
the SBR.
the 4303
every
Similarly,
KT4.
is running:
5.2
There are five
triggers
and clear
completion
must already
or read
KT4.
86,
as long as any initiating
the processor,
This pulse does not affect
cycle
5-2
STOP key; then at the completionof
does not start
the processor
chain
operations,
KT4 for the repeat
left):
KT4 is generated
continue,
it; in this case,
while
transition
execute
(upper
the processor
then
key and the INSTRUCTION
KT4.
delay
(Figure
clearing
generate
so the processor
and deposit
Upon
return
that
the key time
both the initiating
triggers
the read/write
a repeat
presses the STOP key for memory;
fl ip-flop
AR to MB.
5-2 shows the gates
KT4 triggers
is on,
the end of the delay
KEY WR also transfers
trans-
an instruction
but it does not set RUN,
stops at the completion
a memory
Execute
that
address,
are common
in detail
whereas
fetch,
to all
in this section.
the
address
execute,
and store.
instructions
or to
Instruction,
cycle
can call
The execute
specific
performs
operations
special
here
cycle
necessary
instruction
to timing,
and the entry
and return
in the fetch,
execute,
condition
either
general
within
standard
but is limited
primarily
to the
instructions,
including
entry
of individual
the description
functions,
of the execute
the calling
cycle
of the simple
into
included
AR subroutines,
sequences.
cycles,
of subroutines
the gating
levels
are OR functions
instruction
an instruction
outputs
control
for special
may be an entire
operations
For this reason,
and store
and the calling
control
for the execution
sequences.
is limited
pulses
some general
from the instruction
of instruction
class or a single
or in an instruction
(4.3)
of time
An input
or it may be a single
The reader
and only
the sequence
conditions.
instruction,
class.
decoders
that govern
is assumed
special
mode
fami I iar with
conditions
the
are discussed
here.
-a
The lower
half
from memory
of Figure
(flow
to interrupt
triggering
ITO.
synced
cycle
by key
retrieve
a slight
provided
master
sets IFlA,
the processor
places
the memory
in a normal
processor
Furthermore,
IOT
controls
operation
clear,
is not already
which
is already
in a Pi cycle,
a request,
the sequence
continues
instead
the processor
in a Pi cycle
by setting
Pi CYC,
subroutine
sequence,
i.e.,
is in a PI cycle,
if PI OV
is completed),
and supplies
Pi CYC(O),
however,
the sequence
a memory
th e address
the appropriate
is 1 (this can occur
MA is incremented
only
address
the instruction
address
will
strobes
in the second
subsequently
produces
which
consecutive
that
no reif
triggers
and then triggers
address
interrupt
to IT1 directly.
ITl,
the
which
retrieval.
comes from the program
PI channel
register,
the priority
to IATO,
for instruction
by 1 at the same time
5-5
starts
that
continues
by
has been
if the PIR strobe
in a Pi cycle.
cycle
or deposit
the memory
subroutine
(8.2k)
or causes examine
a new instruction
of an instruction
the SBR for the memory
PI SYNC
begins
clears
of instructions
the processor
and no examine
cycle
the master
the retrieval
starts
KEY GO
in the store
IT0 also generates
does produce
clear,
pulse
IT0 generates
delay
that
operations,
is in normal
the final
or if the processor
the strobe
block
timing,
chain
Wh en the operator
4-4).
processor
If the processor
an instruction.
system
calls
Figure
normal
of the next one.
and after
quest
5-3 shows the time
chart,
or deposit
instruction
counter;
is transferred
PI cycle
the channel
if the
into
when
MA.
a
address
is
transferred
in,
so the processor
When
the channel.
transfers
been
the instruction
the instruction
from a location
in read
above
17,
program,
T2 starts
UUO
ITlA
also clears
ly by triggering
instruction,
in location
IT1 A.
operation
restart
associated
triggers
ITlA,
If the instruction
flip-flop
with
which
was retrieved
in case the processor
has
retrieval
to ITlA
execute
by setting
41; the memory
After
so that
triggers
situations.
restart
ITlA
after
IFlA
then
of the operand
the operand
If a UUO
and making
continues
in the fetch
is executed
the contents
appears
in the
a read request
the chain
cycle
auto-
of the execute
as an instruction.
of the DATAswItches
Similarly,
have been
to MB via AR.
The calculation
the upper
of the effective
half
of Figure
cycle
5-3
by triggering
in a character
(flow
ATO.
portion
register
Address
for an instruction
chart,Figure
However,
address
4-4).
for the operand
word
to IR, and clears
sequence,
handled
as specified
in preparation
ITlA
by CHT9
has already
shown
in
starts
the
for the second
the pointer
by the pointer.
from MB to AR,
MA
by the logic
is also triggered
the processor
of the instruction
address
is governed
In a normal
the cycle
in this case,
the effective
the address
and the index
address
operation:
must now calculate
transfers
IR.
mode
for several
execution
b
part
location
the memory
from MB into
late
a new instruction
XCT TO returns
the console
address
in MB,
the readin
may also be entered
the instruction
transferred
is available
in the second
in.
cycle
matical
the instruction
code and AC address
The instruction
to retrieve
performs
transfers
AT0
the indirect
for subsequent
and
bit
memory
access.
AT0 also generates
processor
being
cycle
.)
index
in a PI cycle,
the operator
(IFlA
However,
re t urns the processor
is already
provided
(8.2H
If the instruction
register
address
strobes
the priority
If the strobe
to the instruction
the sequence
that
the return
specifies
cycle.
continues
modification
to MA,
register
is to be performed,
makes
a memory
read
5-6
system
any request,
If there
the address
cycle
cycle
(IR14-17
request,
AT2,
sets
generates
by triggering
AT1
IOOpsec
than the instruction
= 0), AT1
and
the
or if the pro-
the preceding
rather
AT1 triggers
provided
PI SYNC
is no request
STOP k ey within
is to the address
no index
interrupt
discovers
has not pressed the INSTRUCTION
0 guarantees
if address
which
in a PI cycle.
is not al ready
IATO which
cessor
PI SYNC
jumps directly
which
A LONG.
transfers
to AT4.
the
The return
from
memory
triggers
the index
AT3,
register
half
continues
index
address
of AR.
ger ATO,
restarting
contents
cycle
address
return
clears
the cycle
to MA and makes another
clears
allows
of
trans-
which
(lR13 is l),
from MB back
contents
the indirect
the memory
bit and
restart
to trig-
cycle.
address,
the processor
for the instruction
MA,
MQ,
is contained
to the last word
goes on from AT4
and ARLT are all
in the right
retrieved
halves
from memory,
to the fetch
clear;
cycle.
the effective
of both
provided
MB and AR.
the final
The
address
did not index.
Figure
5-4 shows the logic
for the execution
structions
of the control
or specific
OP,
not used.
shall
included
All
apply
codes:
that
There are a few instructions
either
of a second
ulator.
The three
The cycle
fetches
levels
AC2
keeps
the final
for any double
address
chart,
4-4).
Figure
after
The bottom
these situations
word
shift
POP and POPJ both
for the pushdown
list.
5-7
by half
are shown
operation
pull
individual
whether
for
the fourth
is
is XCT;
instruction
situations
require
of the already
point
of the word
(5.3).
the retrieval
retrieved
in the center
or
is asserted
accum-
of the figure.
division,
out the word addressed
Fetching
in-
CH INC OP and
IR 254-7
and for fixed
shows
the net in the
and indicate
the third
the accumulator,
addressed
inputs,
The level
are standard
retrieving
groups,
operations
two are jumps;
INH
two
necessary
part of the figure
an accumulator,
it is retrieved.
FAC
after
instruction
do not require
the first
of the operands
The lower
In all
part of character
or of a word
that govern
dividend.
from memory
function.
generate
which,
accumulator
uses a double-length
for that
be incremented
inputs
the retrieval
for the cycle.
to the first
instruction
other
(flow
Fetch
modes which
an inhibit
both
not the pointer
the four
controls
levels
instruction
left generates
CH CL INC
that
of an instruction
the generation
which
address
The last action
--c
lower
the
on to AT4,
AT5 also sets A LONG,
calculation,
of MBLT are equal
the cycle
an indirect
the calculated
a direct
of address
calculated
specifies
to add
The subroutine
to MB and moves
of IR, and sets AFO.
specifies
At the completion
address
from AR back
the address
the add subroutine
by the instruction.
the new address.
portions
If the instruction
specified
transfers
to retrieve
register
and requests
If the instruction
to AT5 which
read request
sets AF3A
to the address
fers the calculated
the left
which
which
by ACRT,
addressed
by ACLT
is required
by JRA and BLT:
the former
AC in E and saved
E and PC in AC;
location
by ACRT.
addressed
Two levels
PSE.
govern
The first
the retrieval
can later
For the first
it is not to be incremented;
be written
while
back
in.
and thus requires
should
first
all
operand;
execution
time
that
address
calculation
IOT:
after
data
than other
proper
fetch
to FT5.
the pointer
and requests
by BLT T6.
the sequence
read.
In a block
operations
FTlA
bypassing
destination
AC,
are performed
FTI,
because
addresses,
only
each
which
all
SBR flip-flops
so that
cycle
and stored,
FTO performs
pointer
requires
restart
the instruction
for the first
must fetch
transfer.
AC,
All
of these
is required.
into
If the
cycle
but continues
the AC address
cycle;
into
for the
the
goes directly
from IR to MA
is also produced
directly
but the store and
The subroutine
contains
The
FTO for a block
the sequence
which
in-
greater
the fetch
operations
which
The
is 0 and the entry
triggers
by a fetch
situations,
the fetch time chain,
deferring
FTlA,
indexed
the memory.
is also an entry
BLT subroutine.
5-8
to release
triggers
is retrieved
by the special
significantly
transfers
the pause
do not use E as an
that
require
which
is to
instruction
scale.
no accumulator,
if
FC(E) and IR FP.
that provide
no outside
the pointer
floating
IOTTOA
information
and controlled
requires
at al I, A LONG
There
goes to FTl,
IRMD
no further
is immediate.
word
read
The second
is automatically
operations
except
or deferring
The memory
transfer,
deposit
to FC(E):
in E; however,
indexed
(8.1).
inputs
instructions
If the instruction
a memory
index
and
follows
a pointer
at AT4 when
no indexing
the entry
fetching
FC(E) retrieves
a character
and they request
cycle
has been
sequence.
To fetch
part,
.
if an incremented
and division
are the delaysand
requires
that
operations,
in the
FC(E) and FC(E)
automatically
in the store
is required
of two
floating
instructions
otherwise
instruction
(usually
stored
storage
address,
inputs to both nets are al I standard
store the result
is from the address
FTO is delayed;
note
all
In the upper half of the figure
entry
pause
multiplication
includes
have modes
the
for subsequent
thus pauses after
location
The remaining
fixed-point
structions
normal
subroutine
in the second
take special
the second
so it can rewrite
An IOT BLK also retrieves
the pause.
but the reader
represents
whereas
a word
from a JSA which
to the effective
part of character
Similarly,
a load does not.
to retrieve
the memory
into the same memory
by the same level).
AC as the return
according
the memory
request:
be written
the latter
of a word
reads and releases
makes a read/write
to restore
returns
the initial
to
source
The sequence
from FTlA
AC operations
are necessary.
is in AR and E in MB.
MB and AR.
left half,
and the operation
half of AC,
quired,
read for either
type of extra
routine
to FT4A,
extra
word
fetched
from
FTlA
then
triggers
return
words were
addressed
fetched,
although
by the left
and if there
If there
case it contains
MQ
MB contains
cycle
is clear
the extra
E with
(the latter
unless
fetching
Figure
4-5.
compl icated
The lower
sequence.
sequence
Figure
the processor
the simpler
ones,
the pulses
instructions
trigger
of the figure
Two are inhibit
contains
results
the
directly
read or
which
results
AC and C(E)
also fetched
clear
the word
the left
half
clear;
or in the same state
if no fetch
AC operation
if both
operations
was required,
were
in which
Execute
performs
5-5 shows the logic
Only
portion
sub-
word.
the operands,
of the instruction.
MQ
a memory
E with
the left either
an additional
The memory
FT6A,
if the cycle
only
the memory
access.
AC contains
case occurs
.Id
After
requires
E; and AR and MB contain
was no AC fetch,
is re-
E from MB to MA and
by triggering
are swapped
E.
FT5, which
is not used for memory
MA contains
was no C(E) fetch,
at al I).
the cycle
the selected
triggers
so that
FT5 transfers
is in the
accumulator
to save
MB and MQ
the instruction
completes
MA with
If a second
AC
MA and switches
and if the address
loads
FT4A also triggers
the AC halves
half.
as at the end of the address
performed
E.
clears
and skips to FT4 which
are required.
address
of the cycle,
MA;
additional
MB and AR so that
FTlA
FT3, which
upon whether
then
from FT5 if the effective
clears
and switches
contains
whether
between
FT4 also sends MB to MQ
AC operations
The memory
upon
operations,
FTlA
MB and AR,
clears&H,
and MB again
a switch
and goes on to FT4.
AC fetch.
FT6 or FT7 depending
At the completion
by AC,
It also triggers
switches
which
if no additional
read/write.
directly
AC fetch
switch,
adds 1 to MA,
returns
are no extra
in MB.
makes the MB-AR
FTIA
include
a word addressed
swaps the halves
by it depend
All sequences
If there
To fetch
performed
for the execute
are actually
appropriate
is made from the subroutine
that
break
necessary
time chain,
executed
for the execution
the flow
by the ET pulses;
chart
is
for the more
subroutines.
shows the generation
levels
the operations
of three
the chain
usually-but
5-9
levels
for subroutines;
not always,
that
control
reentry
the execute
into the main
at ET10 (XCT and UUO,
for
example,
both
return
directly
to the instruction
FSB start at ET4 and thus inhibit
inhibit
ET4 although
ET5.
this does not mean
(including
executive
instructions)
but which
require
inhibits
time
fixed-point
whose
that
that
it triggers
continue
subtract
at ET3 and enters
ET3 and switch
logical
most instructions
E LONG
In the execute
cycle
operations
and the flags.
which
flow
data
the sequencing
logic
the
The
chart,
which
instr-uction
will
involving
and
by the ET pulses
AR SBR which
triggers
both
inhibits:
the floating
IOTs
ET4 to
add subroutine
index
the pointer
at
counter.
to and return
individual
complete
of the
These instructions
gen-
to ETlO.
conditions
and operations
occur
almost
instruction,
actually
and
execute
at pulses 0,
refer
cycle
are
PC, MA,
exclusively
of the execute
refer
are listed
involving
on AR and MB that
from subroutines,
registers,
half
of skipping
for a specific
description
in the first
to the appro-
discusses
only
the more general
to the appropriate
section
of the
chapters.
cycle,
trigger.
be taken
instructions
are required
the final
pulse
a delay
two 0 pulses are logically
they
operations
The following
entry
for which
instructions
and transfer
events
and also triggers
events
transmission
then
by ET pulses occur
the program
events
and other
flow chart.
the execute
many
of
generate
block
ET5 to go to ET6 instead
the only
logical
following
triggered
of specific
transmission,
For events
simultaneously
ETl.
causes
of the cycle,
in this and
To begin
is also a group
the level
return
which
at ET4; both
In fact,
the SBR at the left at the same
at ET3 and enters
ET6 to ET9 affect
independent
The many
instruction
operations
using
1, and 4; to determine
operations.
subroutine
add subroutine
and transfer
(right)
the Boolean,
ET3 to trigger
instructions
by subroutine
are triggered
all generate
for
to an IOT subroutine.
chain;
priate
the negate
the floating
all
general
several
There
and some of the data
operations
IOTs and
are made at ET3.
to ET3.
The subroutine
subroutine.
AR SBR includes
Almost
erate
and logical
for ull
execution
entries
continues
AR SBR causes
an appropriate
requires
chain
These instructions
for a pause:
the chain.
floating
transfer
requiring
the subroutine
add and subtract
an AR subroutine.
ET4 but only
The subroutines
All otherinstructions
most of them are at ET0 but the execute
instructions
cycle).
Usually
from the fetch
for a subsequent
equivalent
5-l
ETI;
but two pulse
ET0 increments
from the next memory
cycle
location
0
FT6A,
triggers
ET3 follows
automatically
lines are required
the program
in sequence.
counter
ET0 and ETOA
because
so that
The only
from
of
the next
circumstances
that
inhibit
PC+1 are those
sequence
is to be performed.
synchronizes
cycle
bit
10).
interrupt
system
three
restoration
ET3 starts
both
fixed
at ET3 in order
ET4 follows
from ET3 only
AR SBR, ET3 triggers
ART3,
clears
this SBR and triggers
the FSB subroutine.
the in-out
transfer
time
pulse
IOTT
Most
computational
by having
the remaining
control
operations
most instruction
most instructions
store cycle
those
could
be performed);
routine),
routine
for most instructions
fixed-point
if the block
return
(all of these except
multiplication
skip the second
in the cycle
(which
scale
5-l 1
return,
is an entry
to
except
for
but at its completion
regulate
the chain
the flags
cycle
continues
the necessary
by the store cycle
program
(6.22,
8.3).
are produced
in AR,
ET10 sets up MB and triggers
in the execute
division
are made
also returns
is complete.
The subroutine
immediately
is asserted,
is made at ET10 for character
floating
that generate
half of the execute
ET 7-9 perform
for fixed-point
operations.
ET5.
if E LONG
executed
and
cycle.
ET5 follows
at ET9 or ETlO.
The return
and all shift
the IOT subroutine,
are to be deposited
subroutine
and division,
to ET5 unless there
by triggering
a 1 in
for the priority
For the instructions
pause,
interruption.
two pulses
(JRST with
and sets ET4 AR PSE.
instructions
AR and MB either
by subroutine.
instructions
cycle
without
that
is no inhibit.
in turn continues
However,
the final
results
switch
not only
pulses
executed
division
point
(5.4);
to ETlO.
UUO,
the cycle,
ET0 provides
to the instruction
ET4 triggers
transmission
instruction
multiplication
FSC,
from ET3 without
to the execute
ET5 go directly
all
if there
for these
instructions:
and data
for BLT,
in normal
from store
hold and dismiss operations
and floating
ET4, which
sequence
and entry into user mode.
to return
instruction
for use during
the normal
for the halt
AR subroutine
If ET4 follows
returns
through
Since
the appropriate
the next
flip-flops
may interrupt
RUN
the subroutines
before
the AR carry
of flags,
XCT also stops the chain
immediately
again
pulses also handle
operations,
addition;
occur
which
and clears
(5. l),
execute
(8.2b),
for character
floating
operations
cycle
The first
ET0 will
ET0 also clears
those console
to instruction
entry
in which
via
cycle
but also for many of
is at ET9 (provided
operations,
all
from the normalize
NRT6),
the
and the block
the
floatingreturn
transfer
sub-
--e Store
lnformation
cycle
resulting
(logic,
controlled
Figure
by four
requests
structions:
that
thos’e which
a fetch;
so much
execution
the fetch
cycle
address
ory mode
addressed
they
stores
the result
that
in both memory
the block
before
continued
after
in a second
structions
following
completion,
accumulator.
that store
in memory),
a memory
completion
This event
the low-order
occurs
halt,
having
require
pause
have
(which
if AC0
is
BLT LAST inhibits
generate
interrupt
the block
SAC2
shifts,
that
that
the word
is inhibited
in AC so that
operations
in
in the mem-
If a priority
for all double-length
in
by instructions
zero store
transfer.
instructions
and fixed-point
in it without
The input
gate
types of in-
or by test instructions
are stored
and shift
that
instructions
word against
of a block
levels
is generated
is
restart
the read and
but AC storage
addresses
Some arithmetic
than
transmission
for no AC selection).
the current
the break.
and data
chain
E; and those which
SAC INH
and an accumulator,
IR9-12
than
time
by three
information
other
by the store
in the write
and three
the read rather
only
compare
gates
SC(E) is generated
execution.
by computational
Instructions
in the cycle
during
which
E and deposit
only
in memory
of the store
execution;
logic.
location
requested
(the net in C6 decodes
AC storage
cycle,
and pause before
clear
is deposited
The sequencing
store C(E) in a location
that
mode which
may be indexed)
4-5).
by the store
merely
no accumulator,
to store.
Figure
used a fetch
those which
time
of an instruction
FC(E)PSE from the fetch
to free the memory
(that
no result
flow chart,
and are generated
required
that
5-6;
levels:
for any instruction
write
from the execution
stops
may be
to store MQ
floating-point
in-
have a double-length
result.
To generate
a write
a read/write
restart
memory
subroutine
address
has replaced
to be storage
lR9-12,
which
for SC(E),
for SC(E) PSE.
the
return
E during
to generate
is necessary
ST3.
If there
cycle),
ST3 clears
AC,
AC storage
transfers
ST6A which
to guarantee
that
MQ
sets SF7,
the
return
whereas,
it triggers
is no storage
ET10 triggers
request.
according
ST3 directly.
is necessary.
to MB, andcalls
The memory
the SBR for the memory
from the previous
5-l
2
restart
In this case,
another
write.
of the
to E (or whatever
If there
into
is also
it from
triggers
ST5A
ST6 increments
MA
ST6 is also delayed
subroutine
subroutine
ST2 to provide
the completion
MA and ST5 loads the AC address
AR to MB, and makes the write
second
STl;
time pulse sets SF3, andat
the execute
goes on to ST6 if a second
the
ET10 triggers
Either
triggers
in an accumulator,
transfers
to address
slightly
request
cannot
call.
trigger
This delay
both
Th e return
ST5A and ST7.
from this storage
from ST3 if there
is no AC storage
ST.7 is the return
time
for a character
for the divide
operation
not on a character
that
but only
protected
.as no-ops.
to ST7.
to a new instruction
case,
it returns
If RUN
cycle
code,
formation
which
a block
indexed.
cycle,
calculation.
Although
the lower
right
specified
by IRlO-12.
entire
IRO-12
index
portion
register
transfers
there
indicates
which
ET4,
program
operates
those that
codes (except
attempts
the UUOs)
to address
a
and the sequence
Otherwise,
examine
5-8.
from MB,
selection
ST7 returns
or deposit,
provides
For the fetch
in which
address
cycle
cycles,
of every
main
df every
IR13- 17 from MB.
sets lR12,
after
the pointer
IR13 controls
register
in-
the repetition
to be used in the
that
cycle,
cycle
IRl4-17=0,
decodes
supplied
registers.
performs
is shown
is supplied
in
by
the instruction
by IR3-9;
the bus
5-7.
control
In every
(or instruction
IR.
MR CLR clears
instruction
and device
AT0 transfers
If the calculated
5-l 3
instruction
bit
Although
TOA directly
the AC address
to the code
sequence.
address
gate,
control
lines are at the top of Figure
shows the pulse signals
5-7).
and the address
and IOT
according
the instruction
15 of them can be used as index
selection
and store
is selected
data
of an index
only
register
pulse
the indirect
the address
receives
from MB (Figure
the IOT time
calculation,
code and AC address
from MB; at the beginning
register
into the corresponding
IRO-2 are all ones,
A device
into
instruction
addresses
of the appropriate
at the beginning
address
IR only
no index
of the figure
the instruction
register
codes inhibit
and
CONTROL
are 16 accumulators,
instructions,
for the in-out
register
address
and IR14-17
of Figure
For IOT
The lower
an instruction
on the CPA channel
has requested
the 18-bit
instruction
The generation
lR9-12.
drivers
IOT
in IR14-17
no indexing.
into
For effective
of the address
A 0 address
AC storage.
not be performed,
stops at this point.
INSTRUCTION
and AC and index
may be transferred
has been
is requested
the operator
to be performed,
bit,
changes
FP/CH
directly
to the key cycle.
instruction
indirect
(i .e.,
if at any time a user
is 0, the processor
unless
all
is no second
ST7; thus all unused
interrupt
5.3
For each
Since
also follows
could
the first part
ET3 to trigger
a priority
ST7 which
if the division
after
Furthermore,
area of memory,
jumps directly
subroutine
terminates
cause
triggers
or from ST5A if there
on the pointer).
are not used for instructions
are interpreted
at all,
then
address
cycle,
the
ITlA
codes for an IOT)
into
an indirect
bit and
is indirect,
AT5 clears
IR14-17
in preparation
character
operation
effective
address
ation
for loading
acter
time
The next
for the character
jogic
in many
additional
operations;
and those
that
All
5-8
Thus CHT8A
pulse
When
the first
cycle
to calculate
clears
IR13-17
in the first
part of a
the
in prepar-
part of the char-
represent
is shown
outputs
represent
5-8 shows the primary
decoding
multiply
and divide
instructions
hierarchy,
without
although
have
the appropriate
group
both
Outputs
integral
classes,
and
decoding
instructions,
to unique
at several
from the groups
Figure
the
instructions
floating-point
functions
are,
are minor;
the standard
correspond
is
executes
both
into maior
modes that
prefix.
There
that actually
and for all
IR.
the decoding
differences
represent
representing
the prefix
of IRO-8 to control
modes.
pairs whose
the hardware
and divide
command
5-8 outputs,
5-9 and 5- 10 have
and instruction
instruction
with
decoding
of the processor,
outputs
for all single
in the decoding
instructions
the IR multiply
for fixed-point
of the Figure
to 5-l 0 show the main
In this section
which
for these
Figure
levels
decoding
Figures
lines
the floating
round.
command
Figures
cases to individual
decoding
fractional
levels
repeats.
to the address
by the final
instructions.
For example,
instruction.
codes.
is triggered
drawings,
a few command
and final
returns
from the pointer.
which
of individual
down
however,
into
the processor
the cycle
chain.
the execution
trivial
at AT0 when
is completed,
at ATO,
three
carried
for reloading
9-bit
different
decoded
in
5-l 0 also shows the timing
for
SCT and UUO.
The binary-to-octal
tion
decoding
IRO-2.
class,
and 2,
the eight
operations,
condition
produces
input
exactly
by outputs
IR FP/CH
011 in IR3-5
the command
of the eight
P is grounded
specified
gate
other
codes
so that
decoders
codes of the form
levels
for FSC and the five
classes
the decoder
no further
are decoded
are not used.
13X) gates
character
on.
All
further
arithmetic
IR FP/CH
the lower
operations.
codes in
Outputs
control
5-9 and 5-10.
by
In the
decoding.
in IOT control.
in this figure;
in Figures
in instruc-
is specified
is always
for floating-point
100 to 131 which
(i ,e.,
the first stage
instruction
shown
the instructions
performs
and require
by IRlO-12
5-14
5-8
primary
3, 4, 5, and 6 is shown
includes
and instruction
left of Figure
the same operations
instructions
and IR 2Xx,
classes represented
level
which
gating
class produce
IR FP/CH
command
in the upper
by determining
The decoder
the UUO
IOT
decoder
in the
The primary
and character
ANDed
left decoder,
with
which
At the right,
the
the
1
primary
level
by IR3(1) re p resents
gated
and 5 are further
decoded
Bit 6 does not appear
The top center
representing
represent
group.
to determine
is gated
instructions
two of the move
At the left,
by IR 2XX
(the two types of arithmetic
upper
right
IR 25X is decoded
a gate
not required
for these codes.
divide,
level
IR MO (Figure
gates.
representing
5-8,
Al I modes but the immediate
uses a double-length
result
in memory;
do store
in AC,
dividend
whereas
a second
the
AC storage
half of the double-length
product
Note
that
outputs
IR UUO
of the decoder
A and IR IOT A in the upper
puts do not drive
plied
the command
to the executive
logic
lines
(5.5)
executive
logic;
lines for the other
of which
executed
ecutive
is enabled
as a UUO.
logic
in testing
by the appropriate
The gate
C(E).
storage
just below
each
logic);
at the
code.
which
a combined
Only
and
command
fetch
and store
fractional
division
a 1 in bit 7 store
the
For all modes
in division
is
that
and for the low-
multiplication.
The command
have
output
a suffix
right.
instructions.
“A:”
level
for UUO
when
these are
These decoder
Instead,
two cases whether
two instructions
decoder
for the
multiply
in AC.
for the remainder
in the latter
as a UUO.
each
inhibits
for the corresponding
or must be executed
1 outputs
level
the appropriate
IR JRST A in the upper
to determine
each
and storage,
also generates
produces
they are apthe instruction
is generated
are driven
out-
by the
by the gates
the instruction
in C4,
is not being
ORs the 1 states of IR9 and IRlO for use by the ex-
a JRST.
5-15
4
plus two unused
for fixed-point
at the top of the figure
left,
levels,
plus one unused
The two modes with
in fractional
is allowed
the command
two outputs
mode
is required
command
the command
AC fetch
bits
subroutine.
The 0 and
instructions
to inhibit
AC2.
FSC:
the mode.
in 84 for use by the overflow
decoding
memory
than
instructions
(01 in bits 7 and 8) fetch
order
three
to generate
of these outputs
and fetches
only
four modes.
miscellaneous
Further
return
into eight
the six shift
generates
both
center).
into
IR 254-7
by IR 2XX
IR3-5
with
are ORed
the signal
gated
the condition
shift
into seven
generates
the decoder
decoded
other
bits 7 and 8 to determine
to convert
and are ORed
IR SH is further
instructions
at the normalize
or two instructions
codes
Although
rounding
instructions
Just below,
floating-point
the instruction,
here but controls
decoder
eight
all
ACCP
V MEMAC,
For the ACBM
do nothing
mediate
upper
ACBM
group
clear,
which
(upper
uses E.
the other
or subtract
1 before
testing.
MEMAC;
memory
or an accumulator.
the state
the test is made
The logic
nets at top center
the condition
be it 0, C(E),
or E.
The upper
parison
employs
an AND
zeros.
In an arithmetic
and the standard.
but since
is smaller.
cription,
the test word
transfer,
swap is made
for MOVS
represented
is determined
8 that
functions
either
test,
types generates
E
or add
the main
the test word
shall
come
a comparison
with
memory
from
(direct);
is subtracted
from the test word,
condition
at the left:
the logical
or not the masked
equality
the subtrahend
groups,
the standard,
com-
bits are all
of the test word
is the exclusive
is true when
three
of gates
and MEMAC:
AR = 0 represents
the inequality
This function
6.2d
for ACCP
for all
is less than
test is whether
the function
representing
by the pair
the test word
only
and the only
the overflow
logic,
merely
and
OR of the AR sign
is greater
it is true when
than
is automatically
false
(for a complete
des-
function
when
AR0 is 1, i.e.,
when
so the entire
is true
0.
or when
the four standard
modes
are decoded
(bits 5, 6 = 01); and the word
moving
by the condition
the magnitude
IRb(0)
while
V ARO(1)
the
the test word
5-9)
For a full-word
negative
function
the standard
is less than
FWT (Figure
gate
condition.
see the flag
ACCP
of AC against
test the skip or jump condition
AR is 0; bit
comparison,
In MEMAC,
im-
E (immediate).
The function
bit and the overflow
whether
a 1 in bit 5 specifies
The condition
that
both
0 and either
three
as against
bits:
The net in the
includes
comparison
in the latter
of bit 5 determines
in the figure
and ACBM.
on the masked
masking.
in the class that
instruction
against
before
C(E) or AC against
In ACCP,
otherwise
minuend;
Any
for the action
C(E) for the mask direct,
do an arithmetic
types compare
level
bit 7 selects
IR5(1) selects
set.
of the instructions
three
MEMAC,
bits 3 and 4 are decoded
A 1 in bit 8 swaps the AC halves
control
ACCP,
,
bits 3 and 4 for instructions
one fourth
or C(E);
5-9)
right),
complement,
left decodes
MEMAC:
(Figure
the word
in MOVN
5-l 6
from bits 7 and 8; a left-right
is negated
is negative,
or MOVM.
either
both
when
moving
situations
the
being
HWT
(Figure
5-9)
For a half-word
specifies
transfer,
whether
the standard
the half
word shall
and a 1 in bit 6 specifies
that
the left
into
left.
and 5 are both
by loading
that
levels
0, there
a half
be transferred
the source
half of the source
The other
modes are decoded
control
( i.e.,
if the instruction
the appropriate
functions.
if instruction
BOOLE,
5- 10)
AS (Figure
BOOLE
a decoder
and AS have
tions
by name,
bits,
for a specific
may require
JP (Figure
Bits 6-8
of bit
function,
and number,
and lists the basic
instruction.
the OR function
of AS,
addition
by the
HWT
The lower
LT SET
gate
per-
level
levels
is merely
is required.
together,
by three
gated
decoders,
at the left
produce
gates
To decode
for
one
lists the 16 opera-
for each of the four possible
taken
is performed
of the basic
is 1.
the command
The table
1 state.
which,
Each operation
equal
to the left generate
to binary-to-octal
shows the result
functions
its bits be made
of the two instruction
or subtraction
5, and 6 are applied
3, the other
is set to all ones
net generates
word
be all ones.
left.
decoding
whether
bits 4,
from one to three
pairs
the required
of the execute
time
of
result
pulses and
functions.
5-l 0)
of the iump and pushdown
controlling
sidiary
operations,
by the 0 state
operand
For further
of bit 6 to determine
the 16 Boolean
gated
the same modes,
half
The gates
half
If bits 4
is constructed
if it should
the other
the upper
of the right
for the transfer
for bits 7 and 8.
by the states
MB18
or the right
the word
half
it be set or that
is negative.
is made so
half of the destination.
the other
to the right,
of the destination;
the transfer
is 1, AR is cleared;
that
half
before
half
half of the destination
on IR4(1)
requires
and that
bit 5 is 0 or the sign bit
function
bit
however,
For a transfer
forms an equivalent
Since
clear;
half
the right
and complementing
half
to the sign of the transferred
be swapped
on the other
If either
If bit 4 is 0, the other
complemented)
into
the operation
into one half
is left
into the left or right
shall
is transferred
is no action.
word
word
from bits 7 and 8; a 0 or 1 in bit 3
transfers
levels-one
the pushdown
between
that
and pullout
group
are decoded
into eight
MB and AR at the end of the execute
representsal
instructions.
I JP instructions
except
For PC control,
5-l 7
individual
cycle,
JSP, and another
JP JMP represents
instructions.
there
that
For
are two subrepresents
the six instructions
that
iump,
JSR,
all
i.e.,
except
JSP) a Iso g enerate
but it stores
E instead
XCT,
(Figure
UUO
JP FLAG
ET3 to trigger
a point
beyond
the memory
instruction
write
effective
UUO
class,
to deposit
the execute
the trapped
instruction
triggers
the processor
40.
and sets IFlA
return
PROGRAM
is retrieved
program
counter
(Figure
At the beginning
stepped
one position
program
controls
Jump
satisfaction
in only
nected
5-l
so that
1).
instructions
its own sequence
is implemented
replaced
in MB
For all codes
address 40 into
cycle
MA and the
triggers
a memory
by the calculated
logic.
MA,
and
The memory
so the processor
from MA so any input
of every
location
performs
execute
addressed
cycle,
return
the
from consecutive
in the normal
memory
program
by loading
PC one extra
control
into
PC.
must be preceded
is
The
instructions
condition
is
at the end of an execute
sometimes
An address
by a clear.
so a pulse at the PC+1 input
Skip
location,
ADDRESS switchesor
18-bit
locations.
if a specified
position
to any chosen
a new address
from the console
sequence
by the
the counter
by means of skip and iump instructions.
via MA and the transfer
configuration
from the memory
by advancing
transfer
of a condition,
in a carry
cycle.
at
CONTROL
are taken
to skip one instruction
instructions
must be made
the operand
UUO Tl to index
cycle
cycle
41.
in the program
cycle.
portion
in the instruction
Each instruction
the skip
transfers
triggers
of the instruction
5.4
satisfied;
executes
to UUO TO, which
its address
The memory
then
then
is equivalent
with
to the instruction
by the instruction
MA and MBLT,
The last event
the remainder
in location
cause the processor
PC
bits (JSA also saves
the processor
it had been retrieved
instruction,
in location
returns
so that
clears
T2 makes a read request
automatically
PC (PUSHJ,
that save
bits).
which
subroutine
into MBLT.
address
STOR to save the miscellaneous
XCTTO,
, just as though
code
Three of the instructions
5-l 0)
causes
in the UUO
POP.
of the miscellaneous
IR XCT
as an instruction
PUSH and
upon
can be transferred
a jump address from
The flip-flops
MB
are con-
to PC35 adds 1 to the contents
of the counter.
Figure
5-12
shows the control
logic
for the counter:
three
control
pulses are produced
upper half; t.he lower half shows the ge nera tion of the gates that control
5-18 counting,
in the
skipping,
Every program
and jumping.
KTl
clears
mented
tion
PC and KT3 loadsthe
at the beginning
counting
parts,
the second
on the pointer
(C3).
except
XCT,
between
instructions,
executed
For changes
(MQO
iump
jump when
the condition
the add-l
tions
that
instructions
location
The skip conditions
in AR,
There
if the indexing
computer
is another
performs
the next
PC SET \/
count
level
did not produce
instruction
(other
operations
and has no second
pairs and
the normal
the processor
each
sequence
not yet
has
throughout
a block
word.
trans-
When
the
at BLTT5A.
is asserted
The
JFCL when
An extra
begins
for a block
the PC change
5-l 9
flag
all
is
instruc-
at ET9 on two
the storage
by PC+1 ENABLE.
the appropriate
compare
0 or an accumulator
condition
instruction
against
or
either
IOT that does not use the PI system:
into ARO,
sequence
occurs
beyond
for any logical
against
skip),
count
when
and
flag
compare
and is represented
test instructions
a carry
the addressed
one place
is for skipping
block
ET7 to clear
for any conditional
and those arithmeitc
sign,
in normal
than an IOT
PC+1 for setting
which
include
memory
skip
two main
The net for PC SET has as input
the subroutine
compare
during
PC SET causes
sequence,
of the test condition
conditional
of the pointer
any iump or skip occurs
level
that
require
instruc-
from the console.
the two IOT status
instructions
the next
from the subroutine
ET9 to count.
extra
before
interrupts
to process
the test is satisfied.
and the satisfaction
those arithmetic
E or C(E).
include
other
program
of instruction
is inhibited
directly
an enable
jumps so that
Any
a PI cycle
cycle
Conditions
when
inhibit
the pointer
in it because
AR has the appropriate
subroutine
of PC or AC.
appears
and
use an accumulator
unconditional
execution
out of normal
is satisfied.
jumps when
involve
to the fetch
PC+1 (ET9) causes
unconditional
1,
location
which
generally
only
in which
PC is incre-
so PC is not incremented
Counting
executed
in,
counting,
occur
operations
Since
PC is counted
will
that affects
cycle.
to an instruction
whereas
cycle,
instruction.
For normal
cycle
Character
IOT BLT all
returns
= 0),
in the program
ET8 to load,
execute
must be inhibited
addressed
the BLT subroutine
also applies
The circumstances
instruction
execute
the count
is complete
cycle.
the address
block
in the second
the currently
fer because
inhibit
anda
start or read
into it.
another
with
operation
switches
execute
in the single
UUO,
occurs
the console
is to be performed.
beginning
counting
block
of every
sequence
with
ADDRESS
at ET0 are those in which
in normal
part
begins
only
IOTTOA
if the block
the OR gate
(6.2e).
counts
PC (the
is complete).
at the right
generates
If
the
5.5
The executive
logic
by a number
assigned
allows
of programs.
to it by loading
user mode,
interruptions,
memory
or to perform
are discussed
by CPA,
i.e.,
med clear
changed
with
when
a DATA0
for these registers
by the program.
are also cleared
only
ma in sequence
a level
there
output
from
sync remains
beginning
clear
set until
of every
pose of this flip-flop
that
IR is clear
To set up a specific
DATAO.
It then
cycle
a pair
to prevent
jumps
the
to the location
control
of the
in a PI cycle
(such as
type of interrupt),
routine.
Other
the prothan for
to use a protected
causes
area
the processor
of
to go the
on the processor
as a UUO
channel;
(a I I UUOs
protection
the
are unrestricted
the DATA0
appears
clear
in Figure
5-13
it remains
set as long as PI CYC
cleared
sequence.
at the end of the main
the generation
provide
of the UUO
deliberately
(A3,
B5)
from one
synchroniza-
for EX PI SYNC
is 1 even
PI CYC
EX UUO
until
functions
the set function
After
unprogram-
flip-flop
control
since
main
The only
operation
must maintain
flip-flops
at top center
states must remain
and the illegal
registers
and set pulses are gated
in the program.
their
they
and relocation
The pulse amplifiers
(7. I&
of PI instructions.
and then
The user program
However,
of the next
in the instruction
program,
three
flip-flop,
between
is merely
user
logic
start because
clear.
in the
routine).
the user flag
the beginning
address
instruction
start because
The remaining
the PI cycle
may be a master
interrupt
for the processor
the master
by
a priority
for PR and RLR when
by the master
tion and are cleared
action
for the memory
address
Similarly,
to another.
The former
except
is the master
some other
in core
the processor
is under
unti I it attempts
to the executive
logic
(which
and memory
and the area
program.
to the executive
the il legal
the memory
and set pulses
in a PI cycle
has control
of processor
placing
to the selected
returning
and triggers
to perform
control
registers,
but if a JSR is performed
instruction.
sequence
return
IOT
the sharing
a user program
IOT or for servicing
control
an illegal
the processor
the clear
appropriate
of a block
5-l 3 shows the executive
provide
time
to a location
main
but automatically
which
and relocation
the user program
end of the current
Figure
selects
the user mode with
priority
causes
routine
unrestricted);
the completion
latter
The executive
and is hence
following
leaves
to control
by a block
routine
cessor
routine
temporarily
executive
LOGIC
the executive
the protection
and jumping
may be interrupted
EXECUTIVE
the
is set at the
sequence.
command
though
is cleared,
SYNC
is
level
The purduring
the
cycle.
executive
routine
for the program
5-20
loads PR and RLR with
with
a processor
a JRST that also sets the executive
mode sync flip-flop
JRST,
time
(83).
or by restoring
the flags
were
Th e setting
the flags
executive
(a 1 in bit
Instructions
stored.
in bit 5, but the restoring
either
11) provided
that
by programming
store the miscellaneous
sequence
The processor
in which
does not
bits with
at the
PC store EX USER
Instead,
the executive
at this time,
the sync is set:
was running
directly.
leave
12 of the
a 1 in bit
that a user program
JRST does not act on the user flip-flop
mode sync if MB5 is 1.
end of the main
may be done
it sets the
mode
the transition
until
the
of the sync back
to 0 sets EX USER.
The addresses
in the user program
and relocated
to the area assigned
that
inhibits
both
The net also
to all
inhibits
programs
ipso facto
ses that
relocation
occur
the minimum
in a PI cycle
because
inhibit
is necessary
calls
right
monitor
IOT,
UUO
to generate
drives
the corresponding
command
terrupt
is in user mode,
or halt
Any
this thus provides
the executive
UUO
regardless
EX IR UUO
and at ET1 it sets EX ILL OP.
JSR in location
41.
flip-flop.
Just
in case
by all
block
is cieared
if the instruction
The 1 state
IOT
that
level.
a JRST that
(a block
of this flip-flop
the user flag
does not overflow
IOTs.
5-21
the relocation
routine,
outputs
The JRST or IOT decoder
is not executed
attempts
the
IOT
output
as a UUO.
in a PI cycle
(after
is not part
the UUO
When
with
and return
interrupt
of the
control
to
40 and 41,
the inhibit
at ET8 the illegal
in-
sync is set);
it must use addresses
should
for
to dismiss a priority
then continues
and
for the addresses
the IR decoder
can communicate
since
of addres-
(82).
EX IR UUO
relocation
only
to the executive
line
inhibits
Again
are
of the executive
a iump
command
a user program
or relocation
control
is 0.
are available
no protection
by receiving
of mode enables
locations
these addresses
are under
a level
if the user flag
are necessary
the user flag
user IOT
generates
inhibits
the UUO
replaces
right
these
is running.
require
they are legal
here because
executed
user instructions
At ET7 the JSR clears
a block
is also
but both
should
and replaces
a means by which
routine.
addresses,
EX IR UUO
the processor
user program).
There
if a user program
only
whether
asserted
so that
unnecessary
also stores and clears
JRST,
the system
and
even
If the interrupt
the routine
The nets in the upper
size).
is always
addresses
the instructions
for the PI channel
by the instructions.
the inhibit
is really
block
PR to determine
The net in the lower
of fast memory
inhibit
and must be unrestricted
JSR that
to the program.
the relocation
routine
given
against
and protection;
(the protection
less than
are checked
into the
operation
the JSR,
EX ILL OP
The illegal
that
operation
is inserted
between
flip-flop
is also used to inhibit
two main
sequences
EX ILL OP is set by ST7 at the same time
read/write
while
that
relocation
the processor
the key cycle
return.
5-22
during
an examine
is running.
is triggered
or deposit
For this purpose
and cleared
by the
CHAPTER
6
LOGIC
ARITHMETIC
The first
half of this chapter
full-word
registers,
fixed-point
logical
word
numbers
reg isters,
portions
ister
on computer
there
the
are
two
pointer
gating,
(e.g.,
the flag
half
and arithmetic
conditions
9-bit
interface
logic
connection).
individual
register
The three
operation
cycle
the reader
full-word
is, MBi,
AR;,
registers,
arithmetic
and MQi
refer
subroutine
registers
specifically
time
time
pulse,
discussion
with
with
and all
have
the generating
(6.5).
time
of the generating
either
pulses
of the appropriate
are contained
are all on the same module
connected
(computer
trigger
a given
In the following
conditions
instructions
To determine
directly
the
Lines from this
CFAC
from the subroutines.
sequence.
at each
all must trigger
the prefix
of those
of data
are therefore
interface
of its
SC).
that occur
chains
for
the reg-
the execution
pulses
one or two subroutine
6-l
is a discussion
the events
in a subroutine
in the main
time
register
control
the different
logic
floating-exponent
The test discusses
for the execution
events
to,the
that
cycle.
perform
only
only
by a subroutine
should
chains
and
the full-
of steps required
the SC subroutines
AR,
the significance
is given
each
transfers
the size and position
with
to the register
and for other
triggered
they
for
associated
Many
data
Besides
used
hardware
from
OR gates
When
directly
of the arithmetic
interface,
register.
through
with
Three
and half-word
All
the number
and also describes
of pulses
are
and counting
the time
chain
by the functions
discussion
of any event
in a given
numbers.
such as calculating
of the execute
a number
are supplied
in the execute
outside
instances,
are labeled
they
describes
on full-word
FE that
Included
and AR subroutines
of this chapter
floating-arithmetic
event,
logic
control
operations
and any other
in an arithmetic
to the register
computations
calculations.
in these registers.
SC and
operations.
logic,
for the pulses
same operation
registers
subsidiary
instructions
In many
step.
are used for computations
are also performed
in character
its control
used for arithmetic
parts of floating-point
words
and floating-arithmetic
The second
that
and MB,
and for various
of
fixed-
MQ,
the registers
and the fractional
operations
calculations
input
AR,
describes
or through
for an
performed
the significance
the subroutine
subroutine.
in the same set of double-height
(it also contains
modules,
the ith bit of the
memory
indicator
is controlled
left
half
register
as a pair
in mounting
Ml,
of half
panels
J of the same bay (e.g.,
are in panel
locations
pair
amplifiers
of pulse
merely
as blocks
gates
output
fers,
drives
but since
all
tween
corresponding
Figures
in locations
gates
in two
All
logic
transfers.
the registers
the actual
logic
All
inputs
to
drawings,
half
of all
to them
by a
these are shown
with
Each PA
for ordinary
register
bit are labeled
and pin connections
input
the registers.
in the same set of modules,
internally
registers
modules
every
H and
half
amplifiers
with
for the
in panels
drawings,
pulse
register
the first
are supplied
associated
to 18 register
are contained
bits are made
pulses
labeled;
and is connected
iam
control
On the register
of the control
Each 360bit
The flip-flops
15.
14 and
logic).
for the right
6- 1 and 6-2).
the pin connections
9 for
name;
and is shown
5 to 12 and 16 to 24.
18 input
in the memory
D and E of bay 2, the second
in the drawings
but to only
is described
registers
see MB,
with
are shown
which
0 or 1 transby signal
connections
are listed
only
be-
for external
signals.
6.1
Figures
6-l
and 6-2
show the left and right
fers to and from memory
one of the operands
direct
clear
MEMORY
are made
(which
receives
the register
include
six sets of internal
at the connector
so that
transfers
of either
zeros
into
right
the left.
half
memory
Clear
For various
bus (7.2)
inputs
The external
are made
at the top in Figure
bits O-8 that
parallel
two of which
set or clear
into
the program
Transfers
pulse set inputs
but these are used only
Besides
the memory
l-8;
inputs
the clear
bus inputs.
whereas
than
gates
for bits
l-8,
6-2
third
stores
gates.
The two halves
the right
and the right
may be stored
of information
into
in the
MB from the
of the figures.
l-8.
from the memory
there
The gates are controlled
the
are also available
shown at the bottom
those
it holds
and set inputs.
AR or MQ.
into
trans-
has a
from external
counter
for bits
other
clear
inputs
pulses
MB from either
in MB LT.
via single-bit
bits
single-bit
All
here because
and gatable
but the gatable
instructions,
register
for the single-bit
6-4.
pulse)
buffer.
Each MB flip-flop
the left may be iam transferred
executive
are also available,
gates
gates,
memory
is discussed
instructions.
can be made with
i.e.,
of MB; the instruction
register
clear
or ones may be made
of MB may also be swapped;
of the full-word
and logical
The MB modules
Transfers
halves
via MB, butthe
in most arithmetic
input
BUFFER
bus are shown
are also set gates
by three
the miscellaneous
transfer
bits
for
pulses,
in MBO-5.
The generating
logic
set and clear
functions
register
for these transfer
occur
include
fol lowing
The latter
storing
is saved so that
Saving
allows
between
the computer
top section
through
various
to the appropriate
but
return
routine
CHF7,
is set at the end of the first
to return
properly
control
to the second
part
The
part of the
Storage
jumps.
to their
bits also include
can return
6-3.
subroutine).
of the subroutine-calling
The miscellaneous
which
of Figure
the exponent
the executive
of Figure
6-3
OR nets whose
inputs
in the center
section
main sequence
supplied
shows the logic
function
are always
half
the single-bit
of MB leaving
(D2,
be cleared
(upper
B7).
CHF7
These bits
original
and EX USER.
to a user program
part
if there
by re-
in a character
is a priority
before
from
generate
the level
MB PC ST0
ET6 (Ab,
86).
but the restoring
PC (A8).
All
There
instruction
left and right
half
opera-
interrupt
gates
halves
JSA,
PAS are triggered
(6.5)
address
in the right
levels
for the execute
ET6 via the diode
of MB are swapped
time
a signal
from memory
For a UUO,
half,
the UUO
occur
to MB from AR or MQ
by the
pulses are
jumps.
(5.3).
No prior
at ET0 (07)
pl acing
the
These iump instructions
PC into
bits along
PC at ET6 but is not included
net in D6.
only
clears
MB must also
c I ears MB at ET5 (Bl) and transfers
transfers
control
these
and the ET3 loads IR into
subroutine
in various
since
ET1 clears
iump JRST also save the miscellaneous
that
or from the trans-
to these gates are supplied
for transfers
via the bus.
(C3) which
interface
The
section.
arrive
PC that
these
MB transfers.
clear
is required
E in the left
half
it at
with
in MBPC STO;
because
the
and leaving
the
clear.
The two diode
conditions
is one iump,
the gating
pulse also triggers
the transfers
gates;
inputs
in from memory,
inputs
the effective
the register
Timing
is not required
pulse
all of the regular
from the subroutine
chains;
For transfers
governs
drive
in the bottom
left)
The transfer
that
of the figure.
and subroutine
iam transfers.
MB before
that
come either
by the OR nets shown
The clear
right
to nullify
can be used by a subroutine
shows the pulse amplifiers
fer gates
this
right
the two.
The remainder
MBLT
(refer
at ET6 in several
the interruption.
the flags.
tion,
left
bits occurs
in the upper
operations
by the MB sign bit
the four AR flags which
states
is shown
in floating-point
and are conditioned
of the miscellaneous
pulses
nets in D7 provide
are standard
instruction
six conditions
for the left-right
modes and a fourth,
6-3
JSA,
swap of MB.
is described
above.
Three of these
For the
other
two,
CON0
makes the swap so that
BLT does it to restore
the address
word
in the location
time
pulses at B2 to trigger
whenever
specified
the processor
includes
BLT,
The logic
which
the transfer
must fetch
then
ing from top to bottom.
Almost
transfer
05) to AND
with
the mask;
The 0 transfer
transfer:
portion
in AR are also ones.
gether:
they
iam transfer
are also applied
AR to MB,
to AR control
(6.2~)
The double
transfer
always
does it (03)
if there
is no fetch
wise
erated
subroutine
in Figure
is actually
(6.62);
6-3
are not immediately
The single
at AT3A
the result
console
transfer
to move
the calculated
uses the transfer
only
standard
instruction
the transfer
situations
portion
of the draw-
and ones simultaneously,
In the ACBM
is inverted
through
deposit
trigger
the transfer
but
group,
a 0
the diode
net in
again
if the masked
to produce
an actual
of the character
of zeros
and ones to-
from MB to AR at the same time.
the transfer
cycle
word
addressed
switch
transfers
address
back
the contents
Cb).
to 4.5
modification
but the latter
and divide
the transfer
to
as any other
events
in the address
in order
execution
cycle
to store
from the
can be sent to MB only
subroutines
ET0 or ETlO:
is complex
gen-
be required
the transfer
or instruction
of the DATA switches
of the multiply
by levels
(also see below).
to MB; ST5 triggers
6-4
would
other-
in the block
In a few instances,
hardware
Any deposit
points
times gated
of these cases as well
refer
half of AC,
at three
are at execute
may be made at either
(D5),
by either
is required
but additional
in the flowcharts,
interface)
to move AC to AR and E to MB; FTlA
D8; ET9 and ETlO,
AR; AR also goes to MB at the beginning
cycle,
pair at ET1 .
to trigger
in an accumulator.
because
address
center
(83).
from AR to MB (B5) f o II ows index register
of an instruction
In the execute
pulses
For an explanation
obvious
level
swap
(one from the subroutine
one direction
one.
alone
cycle
(82)
but two of the signals
the remaining
in only
the superfluous
control
The MB-AR
ET4,
the entire
execute
at FTlA
The fetch
all ones and all bits outside
in the fetch
(83).
the appropriate
the original
is also used in a character
of an additional
(ETO, C2;
necessary
eliminate
that
occurs
FT3 makes the transfer
transfer
three
gate
bus, and
to store the data
then at ET6 zeros are transferred
of MB contains
The other
in order
(5.2~).
are of zeros
zeros are transferred
bits are to be cleared.
the character
by ACLT
command
of the I/O
The swap is also triggered
swap to restore
the transfers
made at ET1 (the group
the data word
3.
from AR to MB occupies
all
halves
These two levels
PAS in A2,
the second
cases in which
is always
half.
over both
configuration
a word addressed
requires
transfers
are several
to its original
by the right
controls
there
that
pair
E is available
(6.8_b,
the former
and requires
via
_c).
involves
some comment.
In most instructions,
transfer
the result
from AR to MB occurs
to move the result
ly for AC storage).
a write
or restarting
for the store
fer gating
at ST5 (the MB-AR
However,
a read/write,
cycle
unless a transfer
inhibit
represent
situations
in which
2-way
transfer.
In EXCH,
the switch
acter
is inserted
in the iump and pushdown
already
by
the
switch
right
logic
instead
Figure
configuration
4-7 left).
the result
of MB and AR is made at ETlO.
is available
and POPJ,
The remaining
hardware
would
is that
of both
transfer
is triggered
by two signals
for a switch
of MB and MQ.
include
FT4A to return
to storing
a second
fer subroutine
(6.6~1).
(C 1) to move
to MB the word
fetched
6.2
Figures
6-5
and 6-6
AR flip-flop
and set inputs,
other
clear
cycle,
input
pulse.
instructions
at ET9
result
is
results
represented
ET9, so a second
the address
are unnecessary
from AC
in POP
them).
(Figure
6-3,
accumulator
that
upper
transfer,
trigger
fetch
addressed
which
the other
the transfer
operation,
at the beginning
right)
(B5)
and ST6 prior
of the block
trans-
of the JP instructions
by ha If of AC.
REGISTER
halves
of the full-word
(which
receives
inputs,
one of which
6-5
by a
the char-
transfers
before
it is used at ET0 in three
The AR modules
\.
placed
MB control
from a location
there
instructions,
one for a single
also occurs
ARITHMETIC
and two complement
a negative-going
within
a second
show the left and right
has a direct
from MQ
the
deposit,
for all
is made so that
to eliminate
the trans-
the ET9 transfer
four
(the transfers
interface,
The transfer
In the execute
switch
moved
JSR, whose
and JRA,
correctly
ones and zeros
from the subroutine
accumulator.
except
In the other
PUSHJ
by requesting
generates
use the Z-way
cycle.
be required
The conditions
inhibited
JSA,
This double
E to MB following
is also
instructions
is already
auto-
generating
in a character
In JSP,
to MA at ET10 in PUSH and
but extra
The conditions
instructions
for all
occurs
in E, either
in MB or is being
The transfer
is made
is made specifically
direction
The net that
is in 04.
these
the
from AR to MB at ET1 0 in prepara-
is already
for the store
level JP A tR6(0),
is to be stored
is made at ET0 (C2);
in MB.
the switch
in the opposite
is asserted.
the result
word
group:
in MB (flowchart,
in the appropriate
inhibit
in an accumulator,
at ET9 in ACBM
is transferred
the net for the inhibit
into the data
At ET9,
the transfer
the result
is in C7;
ET10 (C6).
switch
if the result
level.
and
in AR; and if it is to be stored
from MB to AR because
matical
tion
appears
include
the register
accepts
arithmetic
clear
register.
pulse),
gatable
a positive-going
ten sets of internal
gates,
Each
clear
pulse,
but the
the
gatable
0 and 1 inputs
single-bit
pulses
The AR outputs
are also available
from external
AR flip-flops,
within
through
the in-out
bus,
test nets and in many
drivers
shown
in the lower
at the connectors
through
in the left of Figure
corresponding
the four gates).
and various
other
lower
net decodes
bit 9 is 1 and bits
signal
ized
fraction
even
though
Assertion
contains
outputs
that
is necessary
for normalizing
algorithm,
the AR subroutines,
register
gating
are shown
set bits
and the flag
for single-bit
and 6-6.
The only
in the lower
1-8;
the lower
pulse as the row above)
The bottom
pulse
inputs
part of Figure
pair
are buffered
by the
that bit
ANDed
condition,
gate
gates as shown
indicates
that
9 is not included
the
among
in the two nets in C3:
the
net for the condition
that
represented
in floating-point
in bits
AND
by assertion
operations.
of the
The floating-
10 to 35) is considered
normal-
by the clear
pulse for the register.
left shifting;
gating
levels
are shown
6-4.
for a given
at the bottom
the addition
pair
at the lower
drawings,
of transfer
left are triggered
from SC l-8
to ARl-8
Figures
DATAswitches.
The next
of the two AR drawings,
used are for bits O-8 and the gates
The upper
iam transfers
bus and the console
describes
AR Gating
presently
in the register
this section
logic,
inputs
(the two gates
provide
two sets of gates
into AR from the l/O
AND
is 0, the upper
and control,
a
6-5
of the
of all AR bits are also available
(note
1, and zeros
in other
9 is the same as the sign bit.
to the arithmetic
Figures
bit
buffer
such as in the prograrn
to form large
are further
The latter
(AR bits 0 and 9 both
gates
zeros
gates
The outputs
so these outputs
from a single
every
to the shift
purposes,
externally
all
of the memory
in the processor.
The 0 outputs
of the output
stage decoder
In addition
The external
places
that are joined
10 to 35 are al I zeros.
bit
can be made with
gating
for connection
subroutines,
6-5.
AR for the condition
-l/2
transfers
to the input
for control
of the arithmetic
of the register
AR = FP HALF,
point
the processor
diodes
The first
modules
connectors
left of Figure
6-l 0.
portion
the 6205
the module
sign bit AR0 are used throughout
control
so that
gates.
are connected
and are also available
at the connector
6-6 pulses merely
or
by the same transfer
6-5 and 6-6,
gates
to ARO-5.
provide
Both of these transfers
1 outputs
clear
and from SC3-8
two rows are iam transfer
bit are the 0 and
for these
1 transfers
are preceded
for right
of the adjacent
bits.
and
Since
at the register
extremities
special
for the left shift
inputs
for these special
listed
shift
the different
showing
the shift
the connections
inputs
types of shifts
Among
represent
of conditions,
groups
required
which
condition
that
does not apply
level
arithmetic
is asserted
a division
during
The three
shift
bo determine
the state
input
of AR1 unless
make
MQ35
rotation.
cleared
the source
The gates
so that AR0 is unaffected
tation,
from MQl
shift,
that
by any right
The net at the right
combined
AR35
provides
in any double
rotation,
shift
shift
length
or division
is automatically
shift
shift;
cleared
input
floating
is
division
which
function
so
follows
(C4),
instruction
performed,
which
rotation
right.
shift,
The gate
case AR0
The upper
two gates
and AR35 the source
the 1 input
at the lower
so that
left
both
or a right
and from MQO
at the lower
left arithmetic
right
or logical
on a single
AR0 is automatically
disables
or division,
inputs
arithmetic
register
in a combined
disables
shift,
levels
AR0 receives
in which
to AR35 from AR0 in a single
arithmetic
in a single
function
The flip-flop
subroutine,
AR is shifted
in multiplication
shift.
shift
it is also
In left shifting,
is being
the gate
left
is 0 (D4).
as individual
on the AR extremities.
of the net disable
load or a logical
but
composite
over
in
that
The arithmetic
composite
as well
AR0 whenever
right
places
functions
operation,
return
diagrams
shift.
for AR0 on a combined
at the lower
type.
in control
nets
and block
composite
NRF2
is another
functions
of arithmetic
net controls
of data
in a character
shift.
logical
shift
occur
Another
provided
Just above
or a combined
some type
The center
subroutines.
are
At the left are
at the appropriate
shift
in the normalize
subroutines.
6-7.
they
the same shift
but is necessary
shifting
of any given
at which
there
The generating
of Figure
nets are several
require
nets use these composite
the effect
is unaffected.
affect
sets at ARO.
by the corresponding
division
the type of shift,
are also drawn
by any type of division
cannot
al I floating-point
pulses
and floating-add
to fixed
upon
portion
to the shift
all of which
return
is asserted
the control
inputs
(84) is required
in the normalize
SHC DIV,
the time
These diagrams
the level
combined
in the upper
with
configurations.
depending
at AR35 and for both
are shown
the flow charts.
of AR and MQ
gates
vary
the
rological
1 input
so
or a character
deposit.
Above
MB.
the shift
The bottom
gates are three
two rows supply
of MB and AR when
third
rows of gates
set is connected
used separately,
that
1 and 0 transfers
but provide
to the AR complement
inputs
6-7
use the outputs
that
provide
a iam transfer
of the corresponding
the OR and AND
when
and is conditioned
pulsed
bits
in
functions
together.
by ones in MB.
The
Pulsing
this set of gates
produces
in AR the exclusive
the MB gates
provides
al! AR bits.
The top two sets of gates generate
flip-flop
a simple
OR of MB and AR.
to the left of the module
the gates on the AR8 module
complements
are internal
ripple
carry
a carry
is no control
the pulse AR+-1
gate.
Tl,
which
register
in this manner
automatically
18-bit
enters
function.
the partial
the arithmetic
contents
is carried
directly
triggers
have been
carry
carry
output
the level
functions,
function,
a
i.e.,
starts at AR35 with
and the lower
of the register,
This second
The chain
AR18 and AR17:
may be pulsed
carry
input
to AR34.
on to AR33.
between
because
The chain
to the
For example,
is a serial
1 to the contents
the ripple
the full-register
out
the upper
complements
continues
independently
carry
carry in turn corn-
the carry
through
the
out of AR18
in order
complements
contents
into that
addition)
to index
partial
therefore
into
function
a partial
two
addition,
for addition.
then a carry
of MB and AR (AR c MB(V)).
has been
formed,
gates to change
the number
the full-register
the exclusive
in AR represents
OR into
the sum of the
of AR.
bit.
sum.
OR function)
But if there
addition,
of two numbers
is a carry
For each bit where
the next more significant
If after
first
OR function
set of carry
state of a flip-flop,
1 and the carry
carry-initiating
in two stages,
sum *(the exclusive
is no carry
is initiated
carry,
adding
are applied
but the carry
related
when
of the partial
of the arithmetic
sum.
the ripple
complements
the pulse.
inputs,
the the AR35 complement
At the end of the operation,
sense the prior
of the partial
set,
is the exclusive
the partial
sum is the opposite
ripple
only
of MB and the previous
sum if there
as level
both
but the latter
sum (the result
bit,
generates
gates simultaneously.
for a break
addition
sum.
For any given
cannot
to all
gates provides
pulse
that
both of which
above
.
operation
carry-initiating
initiate
AR17,
The partial
the gate
is a 1, carries
except
set of carry
This arithmetic
correct
bit
words simultaneously
The upper
pulses,
these gates
the gates saves pin connections
and if AR35 is 1, it also triggers
if that
carry
The lower
is applied
occurs
pulsing
i .e.,
The two sets of gates provide
initiate.
which
plementsAR34;and
After
of placing
pulse applied
This pulse,
AR35;
containing
to the module).
and
function,
use AR8 and MB8 outputs
AR7 (this method
inputs
there
complement
The next row of gates
it instead
bit.
both summands
However,
ARi
the next more significant
6-8
since
senses the corresponding
AR; is 0 and MBi
complements
for that
1.
bit,
is 1, both
Anytime
a bit
but this carry
is actually
bit,
the
the partial
are 1, the carry
the processor
configuration
bits must originally
is complemented,
is inhibited
if the
a
bit
was complemented
goes not only
gate.
from 0 to 1.
to the complement
Thus,
a carry
it terminates
when
of two binary
input
initiated
a 0 bit
numbers
addition,
and B be positive
binary
bit of the partial
is a carry,
bit,
fractions
the operation
the first section
satisfies
B the contents
whose
of MB,
but also to its lower
up the register
does produce
PS the partial
sum of A and B.
sum is less than
until
the correct
sum
of Si.
Since
there
sum produced
For convenience,
1, i.e .,
to a bit of the sum Si if there
of the two carry
starts
there
let A
is no overflow.
is no carry
can be no carry
in
If there
into Si.
into the
A
least significant
can be no carry
The second
bit of the partial
of the partial
two ones.
Because
sum until
This bit
the partial
section
is carried
of 0 and
to the least
is 1 or if it is 0 resulting
and the next
l),
a 0 bit
carry
partial
addition
carry
However,
carry
is generated;
all
further
i.e.,
from the partial
the partial
addition
PS into sections
of two zeros,
Proceed
with
into
is 0 resulting
al I bits
a carry,
from the right
Psi-,
of a partial
bits are correct
a.ddition
of two ones,
6-9
bit
addition
of
the first
of two zeros,
0 that
results
If the 0 that
that
out
addition
up the register
there must be a carry
of two ones is the condition
is no carry
from the partial
addition
Since
are correct.
propagates
up to the next
up to the end of the section.
there
and a 1 from
is 1 (resulting
carry
sum.
it must be correct.
from the partial
is not correct
i-l
The ripple
partial
each more significant
in the first section
If PS
PS i 2.
sum,
addition
which
initiate.
the entire
bit of the partial
If this 0 is the result
of two ones,
results
Psi,
therefore,
it by the carry
is encountered.
further
the bit
sum in Psi generates
is a ripple
significant
sum is also correct.
reaching
divide
in this way through
from the partial
is also correct;
into
there
Proceed
as PSI.
input
functions,
PS
and ends at the first bit Psi that satisfies the conditions
35
section starts with Psi , and extends to the next bit that
with
the same conditions
If this bit
bit.
gate
Algorithm
and S the arithmetic
sum Psi is equal
psi = 0, A; = Bi = 1.
ripple
the upper
PS35 = S35.
so that
until
bit
of two ones ripples
That this algorithm
Addition
of AR,
Psi is the complement
To understand
there
through
below.
contents
AR by the partial
addition
is complemented.
-b
Let A be the original
produced
of the next more significant
by the partial
is proved
a carry
At each stage,
no
from the
terminates
into
the
the next
ends the section
and the
carry
initiate
begins
ments
all
result
S is the correct
incorrect
The preceding
positive
a new ripple
bits of the partial
shows that
Before
some further
facts
Both carry
are applied
more significant
Carries
of the carry
comple-
operation,
the
algorithm
works
case of two
for the special
for the remaining
cases,
including
negative
addition,
the partial
i.e.,
to the sign bit ARO,
which
sum of two minus
is treated
as though
signs
it were a
bit of AR.
bit conditions
bers are added,
the carry
be understood:
in the partial
(0).
The sign
At the completion
the algorithm
should
(ones) is a plus sign
next
sum.
the addition
proving
The sign bits are included
functions
Consequently,
in the next section.
sum of A and B.
example
numbers.
operands,
carry
both
carry
or if there
functions:
is a carry
into
and out of the sign bit
that
the binary
there
is a carry
out of AR0 if two negative
out of AR1 and the sign of the partial
(i.e.,
carries
num-
sum is minus.
out of AR1 and ARO) are used to detect
overflow.
Assume
bers are 3%bit,
point
fixed-point
[xl
where
is therefore
+.
this number
is represented
of a number
is produced
puter
representation
is no negative
the largest
The four
is to the left
fractions.
the brackets
by the state
by changing
of the number
0; the magnitude
negative
number
cases of addition
of the most significant
The computer
enclose
the number
contained
In 2’s complement
of ARO.
is therefore
1 - 0 overflows,
is -1,
representation
the sign and subtracting
-x
of two positive
-. cl changing
represented
35bit
fractions
+ ('Y)
x + (-Y)l
Y Fx
x + (-)h
Y >x
6-10
i.e.,
xl
. With
positive
in ARl-35.
number
from
to plus.
CO1.
x
the negative
1.
this representation,
-.
num-
The sign of
arithmetic,
the sign back
are:
all
of the positive
the magnitude
by the configuration
X+Y
(4
bit,
The comthere
Furthermore,
Since
the 2’s complement
second
format
a representation
case and y may be 1 in the fourth
the contents
of AR after
addition
the sign.
a negative
it is apparent
processor
answer,
case.
represent
out of AR1 changes
none
allows
that
In the first
the number
Consequently,
the overflow
by checking
the sign bit
from ARO:
The contents
of AR then represent
that
into
of two negative
the sign bit would
bit,
and
its absence
the capacity
numbers
of the register.
is a carry
there
results
in
The
from AR1 but
11
numbers,
changes
41
-xl
-4
- yl
+.61
+ 1 -x
the partial
addition
and all carries
except
representation
in the presence
- yl
the sign and the complete
41
is the computer
If (x + y) > 1, the carry
of two positive
carries:
above,
be:
If (x + y) < 1, the AR1 carry
which
is discussed
the number:
-.cx+ythe addition
which
+. Cx + yl .
the sum has exceeded
x or y may be : in the
either
case,
if the addition
detects
In case two,
for -1,
-x
is:
- yl
of -6< + y).
of a carry
result
If )x + y) > 1, there
from the sign bit
is no carry
indicates
into the sign
overflow.
AR then
contains:
+. Cl - (x + y -I)1
In case three,
the addition
of x and -y,
and all carries
except
into
that
where
y is less than or equal
the sign bit would
to x,
the partial
addition
be:
+.Cxl
41
- VI
41+x-yl
Since
.
y <x,
it follows
complete
result
the result
cannot
an AR1 carry,
ducing
that
is +. Cx -yl
exceed
(1 + x - y) > 1.
.
Since
the larger
the minus sign resulting
Hence
the AR1 carry
the signs of the operands
operand
and there
from the partial
an AR0 carry.
6-11
changes
are different,
can be no overflow.
addition
allows
the sign and the
the magnitude
Although
it to ripple
there
through
of
is
pro-
In case four,
carry
the addition
function
of x and -y with
y greater
than x,
the partial
addition
and the
are:
+.Cxl
Because
y > x,
it follows
and no overflow.
i.e.,
that
(1 +x
The above
result
-.Cl
- yl
41
+ x - yl
Hence
- y) < 1.
is the 2’s complement
are no carries
representation
from AR1 or AR0
of the number
x - y,
'(Y - 4.
Addition
is also used in fixed-point
in MB.
The subtraction
adding
could
-x to y and taking
ment
the word
in AR,
word,
which
is produced
subtraction
be performed
the negative
then
by exchanging
l’s complement
from all ones,
i.e.,
with
by taking
x in AR,
the 2’s complement
complement
the subtrahend
negative
however
the result
The complement
in AR.
for ones,
in which the sign is changed
and the magnitude
-35
1-2
. The complement
of x is thus:
from
-35
y
of x,
It is much simpler
all ones for zeros and zeros
1 -x-2
adding
the minuend
of the result.
add and again
the arithmetic
to compleof a
is equivalent
to
is subtracted
;
y to 2r x yields:
1 -x+y-2
which
there
-35
equals:
1 - (x - y) - 2 -35
which
that
even
is the 1’s complement
is, by an AR1 carry
for operations
2’s complement
of x - y.
without
involving
(i.e.,
of -1 to the complement
when
Overflow
an AR0 carry
-1 because
subtracting
the
drive
6-8
of whose
inputs
gates
versa.
l’s complement
Overflow
is properly
-35
is 2
more negative
carries
occur
indicated
than
the
in the addition
of 0).
shows the generating
the register
or vice
in the same way as in addition;
-1 from 0, the proper
c
Figure
is indicated
logic
AR Control
for the AR control
are in the top section;
come either
these
from the subroutine
6-12
pulses.
The pulse amplifiers
PAS are triggered
interface
(6.5)
through
that
OR nets most
or from the transfer
gates
in
the left
center
section.
and subroutine
Timing
chains,
of events
gates
right.
necessary
lists at each
time
the instructions
for each
the result;
complement
of memory
1 transfer.
All
gate
are not immediately
The pulse
amplifiers
the desired
block
transfer
the key
PAS in B7.
require
first
two pulses
IOT
All
divide,
half
half
half,
is positive
triggers
action
and the instruction
the entire
word.
is the first
pulse
OR as a
6-8
the functions
are cleared
To leave
6-8.
in the address
that
the
nets in Figure
of Figure
cycle
is to extend
at the
(D2),
half of the
into AR
is to clear
it; however,
through
that
functions
transfer
if the instruction
the
Subroutines
the other
the subsequent
from
through
may also occur
affects
is set by complementing
and the
by a signal
is triggered
The clear
transfer
is no further
half
places
at ET0 for four of the Boolean
IOTT
the other
14, which
in 4.5.
is cleared
halves
4-8)
sequence
instructions;
corner
and multiply.
(D6) and in any half-word
there
(Figure
use the OR
and compare
left
the
of memory
by the nets in B3 and C3.
it is required
instructions,
to gate
are no complement
diode
from the DATA switches
add,
by the
uses the exclusive
described
both
is generated
cycle:
For an HWT,
a negative
transfer
BOOLE
The other
in the upper
operations,
there
and then
IOT,
the left
floating
For input
or the transfer
or to extend
input
in the execute
from the bus (88).
gate
AR clear
location.
half,
only
For console
include
at ET1 by any input
other
half,
exclusively
the complement
straightforward.
AR are shown
are supplied
The flow chart
Because
from the flowchartsare
main sequence
and also lists the specific
AR first
transmission,
and the subsequent
The other
the clear
destination
clear
in the right
(5.1)
event,
with
clears
are quite
pulses
instructions.
functions.
the AND
for the data
subroutine.
logic
time
the same is true for the converse.
obvious
that
address
require
functions
necessary
each
16 Boolean
in an accumulator,
other
the events
that
that
require
by the various
nets are used almost
of the Boolean
that
of the
are supplied
for the execute
Six of these diode
a.11 functions
and complement
levels
for the execution
necessary
for MB,
to these gates
and the gating
OR nets at the lower
AR events
inputs
the
to set,
the appropriate
in Bl.
other
subroutine
only
complements
interface;
another
if the subroutine
negate
provide
subroutines
affect
is to subtract
trigger
the complement
One
to the PA gates
in the add-subtract
Corresponding
(d below).
the complement
input
through
at ET0 or ET4 for Boolean
6-13
time
the top gate
functions,
time
comes from the
chain-this
pulses
in C2.
(A2)
pulse occurs
for the index
The gates
below
and
that
and at ET5 and ET7 for the ACBM
group
in case the masked
of the carry
function
bits must be cleared
in an AR subroutine
The four
PAS in A3 and A4 are triggered
transfers
from MB into either
jam transfer.
The top two
any such transfers
with
MB control
instruction
half word
of the I/O
bus.
All
directional
transfers.
other
pulses
Transfers
sequences
(6.6b),
(D4) as well
of the other
Boolean
84 in the figure.
various
data
the first
is required
This function
to provide
through
the pulse amplifier
for the left and right
The control
pulses
shifts,
are shown at the right
reader
calculate
should
refer
in Figure
complements
pulse
are triggered
AR gates
6-9.
to the description
and floating
supplied
add subroutines,
(D5),
part
are located
(6.7g),
6-14
bits in an
in four
83 and
at ET0 in
operations
in
when
ET1 is gated
at
bits in an ACBM,
provides
(BOOLE
6 and 11).
by AR AS Tl in the add-subtract
subroutine
in the chain
initiates
PAS in the upper
from the subroutine
that are external
AR bits
and load
(6.6b).
OR in XOR and EQV
of the subroutines
one-
between
and in character
the masked
To understand
from
on both halves
3) and an OR function
of MB and AR (As) are triggered
The remaining
which
for the special
levels
(04) and at ET6 for the
multiplication
instructions
of the second
The next
in B6.
functions
of the
of the selected
E is available
for the jam transfer
are also triggered
addition.
portion
in both the deposit
in SETM (BOOLE
14) an d an exclusive
OR pulse amplifiers
the partial
so that
gating
is shown
(CS) is used to set the masked
in fixed-point
and IOT
B4 by the level
(BOOLE
logic
and transfer
in 82 with
(B4) are required
The 1 transfer
The gates
OR function
The exclusive
trigger
a 1 transfer
The PAS for the exclusive
in SETCM
the gates
of MB and AR; for
of the address
cycle,
iam
for a full-word
the generating
transfer
1, and
the PAS in A3 and A4 are for full-word,
part and in the load sequence
a 1 transfer
0,
that
compare
D5.
to provide
in a CON0
(D8).
This transfer
from
include
at the end
has been set.
also occurs
instructions.
transmission,
interface,
of the address
of zeros alone
as to provide
flip-flop
interchange
at ET1 in four of the Boolean
IOT status test instructions
complements
Al I four must be triggered
the subroutine
by ET4 through
transfer
control
for a simultaneous
jam transfers
gate
combinations
of AR.
into ARRT at the beginning
The left
ACBM
in several
provide
through
in an HWT triggered
character
if the complement
halves
Half-word
the nets in C7.
two
inputs
not made
(6.1).
word
or both
The bottom
at ET&
the carry
right
of Figure
in which
1-8 are cleared
6-8
provide
interface.
to the arithmetic
the significance
function
register
of these transfers,
they occur.
or set according
modules
the
In the exponent
to whether
the sign bit
is 0 or 1 in order
to nullify
the exponent
part of the register.
from SC1 -8 into AR occurs
in the normalize
return
the exponent
a similar
of SC3-8
character
in the result;
operation
to insert
transfer
the new position
-d
Figure
6-9
routines;
shows the logic
the flowchart
Figure
6-9
chains.
are the nets that
fixed-point
ward
for these
The add gate
against
memory.
and the instructions
indexing
in any MEMAC
of either
instruction
iump
instructions,
and to index
AR-1
is asserted
for the MEMAC
erates
in the pullout
the level
the chain
LTRT,
at AR17 as well.
for operations
last four are included
the level
generated
that
subtrahend
transfer
before
The AR subroutines
join
for the return
and negation;
ment AR.
The double
in a block
cycle
Subtracting
1 is done
indexing
occurs
the subtract
compare
at ET3.
AR-1
TO, which
gate
by instructions
requiring
AR+1
or block
the test word
is
IOT.
Similarly,
and to decrement
the
1 nets is a net that gen-
the carry
chain
at AR35
to enter
in the two add-l-to-both
or pullout
lower
above,
jumps and
instruction
right
(these
corner
described
(this
up-
in the two add-l-to-both
calling
subtraction
time
for both
independently.
instruction
in the
of
an accumulator
ET3 for an AR subroutine.
levels
right
sub-
the subroutine
to pause after
generates
AR SBR is
and also for negation
last case is for negation
of the
subroutine).
time
chains,
The chain
both
by complementing,
then adding
into
Th e net
and negation
by complementing,
AR+-1
addition,
IOT or in any pushdown
sequence.
negation
triggers
and control
the add 1 and subtract
two separate
indexing
In the lower
AR or its two halves
JPA IR6(0)).
to the interrupted
downward
to trigger
decrement
add and subtract
4-8.
are generated
that
the floating-add
are actually
of Figure
causes any entry
and for a floating
entering
part of a
incremented.
and fixed-point
in any pushdown
Between
the execute
to insert
in the first
has been
arithmetically
1 levels
instructions
by any of the four subroutine
in a full-word
gates
that
the pointer
in the level
causes
right
the entire
which
on the pointer
occurs
that adds 1 to the test word,
instructions.
AR+-1
index
for fixed-point
The add 1 and subtract
or downward
pointer
the level
only
subroutines
AR Subroutines
the negate,
provide
to ARO-5
if the pointer
is in the upper
is asserted
subtraction
asserted
governing
and floating-scale
The jam transfer
1.
All
6-15
with
multiple
in the upper
left
entries,
handles
require
a preliminary
adding
1, and complementing
subroutines
complements
each
in the execute
pulse
cycle
that
indexing
to compleagain;
are triggered
AR and also sets the complement
control
flip-flop
(C5).
Th e complement
routine
interface
(6.5)
pulse
as well
either
TO pulse,
there
triggering
AR+-1
Tl which
carries
pulse
character
both
is also triggered
operations
halves
generate
Of course,
a carry
Just to the right
traction.
tion
LTRT),
ment
control
the partial
routine
addition,
and after
add pulse
AR AS Tl .
and also when
the chain
There are three
AR17CRY
(lower
initiated,
All
left)
all
further
is enabled
until
half
carries
all
If the complement
traction)
the completion
control
appropriate
flip-flop
carries
die out:
2F5Y
carry,
overlap
then
has been
set,
the return.
in the time
chain
because
(i.e.,
the subroutine
the carry
ART3
that
i.e.,
has called
6-16
triggering
return
any carry
speed
function
AR,
control
the AR subroutine.
is
can come only
and the OR gate
the carry
However
complements
through-
is a vast OR
completion
is not performing
ART3.
the complement
point
pulses
for any bit
the subroutine
completion
clears
a carry
half,
off the transistor
initiating
Once
the partial
carry.
Tl in the right
of the carry
goes negative
of AR is not required
triggers
these carry
or sub-
After
register
in Bl cutting
triggers
cycle
at any required
from all AR bits.
are from the ripple
for subtracinterface,
cycle.
the full
carries
to the OR gate
outputs
only
and sub-
to function,
in the address
triggers
into AR17.
for addition
for any execute
initiates
that
AR AS TO sets the comple-
These are AR+-1
ORed with
the carry
pulse
de lay triggers
gers the next pulse
pin 2F5Y.
Successive
carries
register
and
out of AR18.
is necessary
at this pulse
in AR.
pulses are applied
chain
is complete.
pulse which
carries
to carry
is a carry
for the complement
begins
an index
AR,
instructions
but also from the subroutine
sufficient
and ARAS T2 which
receives
bit.
adding
there
the block
The chain
initiate
three
that
a delay
whenever
return,
For indexing
as in those
time
before
This
normalize
is also gated
is a separate
to function
of the register.
into AR35
cycle,
whether
to the next
by grounding
from a contiguous
ment
that
IN in the left
just to the right
pulse.
continues
pulses
out the register.
gate
to determine
FWT.
incrementing.
as well
complements
in the execute
flip-flop,
addition
which
in the chain,
or the appropriate
transfer,
cycle
transfer
carries
chain
from the sub-
complement
from block
automatically
and negate
not only
transfer
pulses
in a block
by a signal
1 to the contents
for execute
the same pulse that
pulse
and is triggered
and in a block
by time
into AR17 occurs
The first
the register
into AR35 adding
(this occurs
of the index
subtraction
to allow
as by the input
of AR together
AR+-1
is a delay
directly
as well
may be triggered
as by ET3 in a floating
Fo,ilowing
latter
for negation
a sub-
if the compleand after
flip-flop
an
and trig-
-e
The jump-addressable
Although
flags
some AR flag
ferentiates
and associated
control
cleared
directly
by the program.
cleared
initially
by the master
from one main
three
instructions,
which
change
if a 1 is programmed
flag
with
bits 9-12
make
the jump.
stores
them according
The flag
clear
The remaining
whether
vided
from
execute
cycle
presence
to the first
have occurred.
in process
indicating
of flip-flops
in the
of -1;
being
signal
addition
only
flag.
from the subroutine
interface
bit
or a 0 in a negative
the level
level
gates
6-17
sensing
the flags
of CHF7
the program
All
of the other
AR OVSET
(the exclusive
address.
and EX USER.
may determine
flag
other
pro-
gates are
of every
by the
(as is shown
is asserted
in
when
the
OR of the two
instruction
that
flags,
to
and re-
is indicated
index
group-
the test word-
and if overflow
in C6 set the overflow
shift
them
cases is determined
overflow
instructions
the PC
as the direct
is the exclusive
on the attempt
in an arithmetic
in E5).
The last
clears
at the beginning
to the corresponding
number
all
or in the MEMAC
MEMAC
by
JFCL selects
after
in most fixed-point
the absence
or subtraction
(6.5);
is exercised
the flags.
Since
are
states must re-
(8.3),
flags
so that
are cleared
the overflow
The remaining
and on the loss of a significant
number
with
flip-flops
their
from memory
is restoring
which
for those
1 flags
32 is 1.
clears
dif-
that
iump or skip sets the PC change
in b above),
i . e.,
relevant
if bit
out of AR0 and AR1 .
algorithm
the states of the carry
sets the overflow
right,
carry
the restoration
Overflow
in conjunction
In fixed-point
condition
in a positive
erated
lower
and then set by carries
flip-flops.
Any
overflow.
flag
the flags
is not a JRST that
conditions
interface
taken
for setting
events
I/O
indirectly,
conditions
have oppositestates;
flow
must be addressed
6-10.
for the processor.
the selected
gates
two fl ip-flops
occurred,
and clears
&and
over the flags
in the processor
word
of Figure
can be sensed or
because
and the CON0
here also handle
include
clear
control
generated
of the addition
ET10 transfers
Program
flags
carry
the master
four bits of the word
of one of these carries
the latter
than
half
the four AR flags
overflow,
and set pulses
the discussion
carry
only
in bit 29 or the overflow
The JRST, which
the instruction
the pair
the many
of the instruction
or not certain
for arithmetic
rather
in the right
the user flag and the flip-flop
operation,
a 1 in IRl 1, JFCL,
instruction,
flags
also affect
to the next.
JRST with
are shown
The PC change,
start
sequence
governs
logic
functions
the two parts of a character
main
AR Flags
flag
has
on an over-
by an FWT to form the negative
to the left,
OR input
i.e.,
if a 1 is lost
for this gate
is gen-
The top nets at the far right
subroutines:
SCO.
in Figure
the exclusive
The remaining
6-10
provide
OR of AR0 and MBO,
right
(5.3).
The lower
net ANDs
and this output
is exclusive
ORed with
the lower
is automatically
instructions
gate
is 1 or 0.
word
In this case,
is negative
false
since
i.e.,
and the output
tracting
S from the test word
in the following
Hence,
standard:
a standard,
signs and overflow
the function
register
.
register,
gates,
Each MQ
and gatable
but the gatable
by single-bit
The upper
pulses
T<O,
T<S:
- if
s OV,+ifOV
T<O,
TX:
+and
OV specifies
are iam transfer
outputs
gates
of the adjacent
bits.
upon
the type of shift,
there
shift
gates
shown
at MQl
in the lower
as AR0
whether
group,
a test word
is made
configurations
the test
by sub-
of T and S result
- if OV
Q OV
the relation
and right
between
the test word
and the
and set inputs.
provide
and left
Since
of Figure
modules
include
the clear
inputs
levels
so that
The generating
At the left
6-18
transfers
The lower
for a given
gates
two rows
1
bit are the 0 and
at MQ35,
nets for the special
are the different
can be made
for MQO).
at the ends of the register
for the left shift
pulse for the
four sets of internal
these are used only
gating
the connections
6-7.
receives
multiplier-quotient
of zeros or ones from MB,
shifting;
are special
which
at the connector
(at present,
transfers
of the full-word,
input,
The MQ
are also available
gates
REGISTER
halves
clear
and both sets at MQO.
portion
specifies
of
for T > S.
has a direct
for right
the output
2, OV
MULTIPLIER-QUOTIENT
from external
two sets of gates
The four possible
Q MEMAC,
is true or false
The comparison
s OV,
inputs
with
In the ACCP
E or C(E).
+ if
show the left
clear
0.
T > 0, T > S:
flip-flop
gate
of AR0 and
in arithmetic
In a MEMAC,
0, the function
- and
AROWAR
and 6-12
T.
net.
T 2 0, T < S:
6.3
6-11
either
condition
arithmetic
conditions:
it is true for T < S, false
Figures
is with
function
conditions
of the upper
less or not less than
against
the standard
the overflow
AR0 in the upper
from AC is compared
for use in various
test for the inequality
the comparison
or positive,
levels
and the complementary
nets at the lower
compare
control
vary depending
the right
shift
types of shift
inputs
are
with
the
time
pulses at which
they occur
diagrams
also appear
the shift
nets are two composite
require
at the appropriate
the same shift
type.
the corresponding
shift
add subroutines.
Another
division
NRF2
provided
is necessary
The four shift
input
to determine
case AR0 is the source.
the input.
to MQl
shifted
the shift
MQ35
constant
to receive
single
additional
the left
in Figure
of the register
only
allow
through
shift
is being
MQ
is shifted
performed
right.
AR35 provides
directly
shift.
the 0 input
combined
rotation
below
so that ones are always
deposit
shifted.
pulse
otherwise
The two gates
are shifted
but AR35 must enter
from AR35
in the shifting),
for any left
is not itself
the single-bit
MQO
circumstances,
and in the character
MQ
(C4),
multiplication
is skipped
zeros
levels
MQO.
inputs,
in a combined
logical
There
sequence.
In the first
floating
The pair of gates
leaving
is a
at
the remainder
unaffected.
the register
This bit
of MQ35
(6.8b).
grounds
similarly
MQO when
For use in multiplication,
receives
gate
shifting
subroutines.
shifting
to be transferred
(MQO
affect
but
or by the final
of AR0 in a division
AR is shifted
entry
other
division
instruction
In left
shift
AR0 to MQ35
operation;
shift,
that affects
6-13
shift
net connects
The left
In all
to fixed
as individual
MQO whenever
information
arithmetic
to MQ35.
at DSTlOA,
777.
by any type of
cannot
arithmetic
by
and floating-
arithmetic
extremities.
arithmetic
the complement
in any double-lengtharithmetic
shift
as well
net controls
causes
part of character
gate
al I floating-point
on the MQ
return
does not apply
level
to
(84) is required
is asserted
the control
inputs
all of which
combined
in the normalize
functions
contains
right
shift,
division
shift
to the right
The final
.
inputs
in the first
follows
The next
counter
in any double-length
but causes
so that
These
the level
of conditions,
of AR and MQ
condition
MQO by any double-length
into MQl
groups
unless some type of double-length
The next gate
MQO shifts
provide
of MQl
into
when
which
of any given
in which
i.e.,
division
configurations,
Among
is SHC DIV which
nets use these composite
the state
shift,
shift
The flip-flop
subroutine,
the shift
in the flow charts.
represent
function
floating
receives
showing
but it is also required
composite
over
the effect
AR0 is shifted
that
The arithmetic
is 0 (D4).
return
diagrams
places
functions
operation,
in control
in the normalize
and block
the state
For the multiply
35 and 36 are equal.
subroutine,
Another
MB0 for use by the divide
actually
on any right
shift
(6.8~).
6-19
bit MQ36
but is of significance
the net at the right
net in C4 supplies
subroutine
has an additional
supplies
the exclusive
a level
OR function
(Figure
6-13,
right).
only
in multiplication
indicating
when
of MQ35
and
bits
At the top of the figure
at the master
clear
The remaining
deposit
character
interface
are the pulse amplifiers
and the shift
transfer
transfers
sequence
(6.641).
occur
word
into
in the multiply
In addition
T-bit
to the three
registers
The shift
counter
in the figure
only
for storage
is calculated
in SC and stored
on the fractions.
a character
Since
computations
its flip-flops,
1 transfers
temporary
a carry
chain;
and two sets of transfer
in the
The
in 84.
FT4A transfers
The remaining
logic
also
steps in arithmetic
in Figure
and all associated
multiplication
storage
in SC,
transfers
includes
6-14.
Each module
gating.
of shift
two
operations.
FE is used
and division,
the number
the exponent
steps in the operation
for the position
portion
is considerable
gating
the SC flip-flops
and carry
in Figure
logic.
flip-flop
also has a carry
of the pointer
in
the next
so that
input
is used only
top one provides
functions
6-14
a simple
which
to gatable
input
output.
to the flip-flop
collectors.
that
the transfers,
clear.
complement
function
below.
clear,
implement
complement,
andset
These are connected
to SC8 adds 1 to the contents
for the register
are described
so it includes
with
only
a
These provide
SC Gating
are the gates
and a carry
a pulse at the SC+1
connected
for storage
associated
to FE3-8.
In addition
input
there
but FE is used only
gates
from SC and from MBO-5
addition,
carry
register
SC counts
a
clear
operation;
the arithmetic
are shown
In floating
are performed
including
clear
Below
of ones occurs
operation.
actual
direct
FE also provides
(6.5).
from the subroutine
E to MB.
and counting
from each
in FE while
only
c).
register
results.
interface
I isted at the gate
AC fetch
registers,
computations
of intermediate
pulses
is cleared
SHIFT COUNTING
arithmetic
one flip-flop
MQ
Transfer
on a signal
it returns
(6.&,
and the floating-exponent
includes
that
ARITHMETIC
for use in auxiliary
occurs
is to be a second
subroutines
full-word
the register.
from the subroutine
and at the four time
MQ at the same time
6.4
only
The jam transfer
if there
and divide
control
of zeros and ones from MB.
MB and MQ,
at FT4 saves E in MQ
this additional
PAS are triggered
PAS provide
that switches
that
There are three
and the other
The remaining
6-20
partial
inputs,
from one flip-flop
of the counter.
sets of complement
two provide
gates
each
are connected
The
gates:
the partial
to the
to
the
add and
1 inputs.
The top gate
plement
6203
provides
transfer
module)
gates
to place
until
that
inputs
provided
gates
depending
varies
the data
level
levels
that
the top set of AND
menting
it.
the other
bottom
MB bit
For this function,
the first
sets of AND
the data
data
levels
two sets enable
input
to SC from ARO-8
must be added
used in the arithmetic
OR of the contents
that
three
from MB64
numbers
the partial
in AR in that
are for indexing
register
of SC with
no ripple
is used.
and are not associated
propagate
stead,
as soon as the partial
chain
the carry
pulse.
carry
from one bit
determines
The conditions
for a carry
for the partial
The nets that
gate
receives
bit of a source
into SC3-8,
are automatically
generate
For example,
with
SC clear,
by compleFor
by ones in the source
the first
three
add
an enabling
register.
i.e.,
register:
bits negated;
and the pointer
a bit
a series
bits,
with
the
The carry
connections
inputs,
the carry
for SC differs
from one flip-flop
the full-register
of level
in SC the exclusive
then
function
is complemented
operations,
the same algorithm
add pulse produces
carry
from
and all bits are adjusted
in AR.
right
pulse
from
to the next
function;
by the carry
transitions
are the same as those
6-21
in character
essentially
by the data
sum.
when
for all
each AND
but also
and MBO-8.
The carry
sum is formed,
the carries
with
in any way with
to the next
used.
are asserted
represented
the arithmetic
of information
addition
asserted.
the partial
sum to produce
carries
the carry
the number
for partial
levels
is performed
First,
at the complement
SC bit
operations
The addition
(6.2b).
incre-
a set of level
to set the corresponding
1 to SC3-8
in floating-point
in SC.
for
it is then
the upper
OR) gates
SC is being
of MB04
add pulse
input
the exponent
to individual
and division,
chain,
are used not only
from a single
set enables
To calculate
adjusts
gates,
(exclusive
together;
the complement
the partial
a carry
The source
ORed
nets and an input
places
a com-
pulses are applied
of steps to be counted;
in which
gates
causes
three
the second
gates
add
add gates
the operation
to all
control
provides
net (not part of the
In multiplication
the lower
or set first.
are sets of four AND
is a diode
gate
the operation.
to the partial
The partial
upon
is common
a 0 in a given
of the number
SC is cleared
The middle
in the counter.
terminating
inputs
to the SC flip-flops.
for transfers
but instead
are two networks,
the data
FE to SC.
The last gate
inputs,
number
all ones,
from
SC.
the complement
of the figure
supply
into
no level
a specific
it contains
At the bottom
gates
receives
SC receives
mented
1 transfer
from MB1 8, 28-35
which
in order
example,
an ordinary
no
pulse.
to left
lnacross
simultaneously
There
is no carry
by
into
the least
that
significant
bit
is indicated
two carry
both
(D8) and a carry
by a 1 in the data
out conditions,
summand
changes
propagated
complements
SC8 is disabled
when
and a 0 in the partial
sum.
upon a carry
or if the partial
through
those bits that
and so on through
only
one dependent
bits are ones,
have
out occurs
the register.
defining
carries;
Since
there
cluding
functions
logic
are triggered
governing
FE, which
master
(Bb),
for floating
by execute
transferred
to SC (B2).
The complement
transfer
floating
The only
scale.
occurs
upper
left
and its partial
other
cases,
are quite
in.
bits,
are
out
if
After
the level
the carry
pulse
level
for SC7,
the gating
the LSB, the carry
function
time
In all
gate
for
chains
in-
the master
add function
only
is triggered
(B3).
only
portion
the information
All
in the final
three
sections
of the pointer
6-22
govern
are ungated
or
SC for
although
Read the appropriate
of this chapter)
through
through
to determine
the net in the
the nets in the top center,
right.
it is followed
The source
operation
and they are triggered
the net in the upper
OR is used for transfers.
subroutine
is subsequently
functions
SC is cleared
in which
on the
is the complement
by sign conditions.
complemented
through
other
these pulses
subroutine.
clear),
cycle
The
governing
calculate
subroutineinstructions,
are gated
in the SC add subroutine
the exclusive
cases,
In most instances,
in a given
it is cleared
the position
and
a subroutine.
The conditions
from the execute
and arithmetic
the complement
SC event
simple:
into
interface
SC (C8) is made at ET0 in a shift
into
triggered
chains.
to entry
6-15.
or may receive
time
the subroutine
from SC in the exponent
(84).
28-35
(all are included
includes
is used for addition
all
trigger
of each
(which
other
in the data
description
the significance
(B7),
prior
in Figure
at ET1 in FSC if AR is positive
from the special
many of those that
subroutine
is a carry
from the subroutine
through
pulses only
is shown
operation
of MB18,
or calculating
by pulses
directly
an exponent
or division
part of a character
shifting
into
storage,
and may receive
multiplication
which
can be no carry
there
SC Control
time
for temporary
in the first
pulse,
for all
supplies
There are no connections
the SC and FE functions
is used only
clear
the carries
bits,
there
is a carry
the SC8 carry
of SC and FE are triggered
the SC subroutines.
SC functions
For any bit,
in.
condition
(B8).
b
The various
For the other
sum is 1 and there
the chain
receives
two ones are added-a
This last function
by the carry
of information
(B3);
in
for the data
levels
to the partial
Figure
6-16.
input
add gates
A flip-flop
for each
subroutine;
transfer
instead
in the logic
or partial
the enable
cal Is for the SC addition.
enable
function
for the appropriate
addition.
level
in 06 indicates
negative
6-15
that
in the upper
enables
There are no flip-flops
is derived
the first
is ANDed
complemented,
from a flip-flop
al I ones, the next
count
a leading
so SC8B remains
three
right
of
the required
associated
with
the SC add
in the main subroutine
by 1 through
with
the nets shown
that
below
asserted
There are two subroutines
on exponents
of steps required
through
the
in an operation
right
Listed
of Figure
levels
interrupted
governing
character
SAT1 then
the carry
addition,
chain
control
triggers
chain,
of shift,
the partial
SAT2.1
triggers
of the
in C4.
or divide
and count
When
subroutine
is ORed with
SCO-7
triggers
the -0
are
the PA
configuration,
an add subroutine
subroutine
the intermediate
in Figure
6-16
result
that
counts
are the entry
to which
the number
at each step.
and the flow charts
subroutine
for use in cal-
are in the lower
conditions,
the subroutine
for add lists the entry,
The logic
the con-
returns
the source
in the
enabled
for each call .
left
,although
add,
The termination
counter,
and the pulses
and the return
flip-fIopCHF1
is all ones.
for
disappears.
the shift
the flowchart
for add is in the upper
SCO-7
has
The PA output
the shift-count
Similarly,
decodes
that a shift-count
multiply
and shifts
with
a l’s
indicating
the pulse amplifier
and a shift
at the left
the type
sequences.
for the partial
The time
4-8.
SC contains
The
SC Subroutines
with
and pointers,
is shown
which
the PA output
associated
for these subroutines
to -0
SC8B.
even after
from the SC outputs.
The net in Dl
f or a signal
in theshift-count,
edge at output
derived
bits are all ones and hence
SC8(1)
by a pulse
pulse
signals
to 63 in magnitude.
c
culations
control
i . e . , SC has counted
may also be indicated
to produce
are several
less than or equal
all ones and its output
trol
levels
subroutine
SC may also be incremented
left of Figure
compl’ement
count
by the enabling
levels.
In the lower
been
is determined
in Figure
The first
this is of relevance
and after
the carry.
6-16.
a delay
sufficient
SAT3 then
6-23
returns
only
pulse always
in character
for all
level
clears
operations.
transitions
to the interrupted
the
through
sequence.
The shift-count
subroutine
All
add subroutine.
is used only
other
shifting
arithmetic
subroutines.
Entry
operation
but provides
a delay
the condition
that
SC and triggers
into
by SCTl
is complete,
the delay
output
the same event
the processor
duce
includes
the number
example,
triggers
SCTl
lower
if bit
accumulator,
other
which
For a shift
0, right
left of both
addition
subroutine
DST14A,
alone.
level
gates,
AR and MQ
the logic
shifts
both
AR and MQ,
are supplied
in the deposit
requires
time
a right
chains
pulses
at the end of the subroutine
moves
shifting
in case there
both
registers
right
MQ
in Figure
the shift
empty.
so following
the divide
(FDTl)
both
both
flip-flops.
registers
at the register
6-24
right
sequence.
is both
of AR alone
to the right
the final
to supplement
extremities
subword
gates
for
part of a
Floating
pulses
registers
from the
left at
and one left shifts
at MST2, but a final
In floating
pulse
is
part by a shift
set of gates allows
shift
The
of a single
The first
in the second
to the left.
subroutine,
6-17.
The level
with
shifts
For
18 of the instruction
in the load
division
both
to re-
registers.
in calculations
is possible;
The effects
shifts
from the subroutines
may request
being
shifts
subroutines,
has been overflow
overflow
the norma I ize return.
right
right
in the various
return
process
the count
via SCT2.
The normalize
normalizing
shifts
When
to the right.
the regular
sequence
the output
and count.
if bit
The upper
alone
and then
instruction
left
is followed
The regular
process
by
increments
on SAT1 in the shift-count
control
this
produce
no
(indicated
SCTl
the nets at the left
the latter
registers.
performs
incomplete,
for the arithmetic
the program
or an AR shift
shifts.
the multiplication
logic
by subroutine
of both
divide
though
left shift;
sequence
to trigger
but two other
Similarly
an MQ
shift
signals
are shifted
even
requires
collects
is for shifting
that
operation
times
through
Note
led shifts
different
to the control
includes
operation,
that
are triggered
sequence
floating-
INTERFACE
at many
18 is 1 .
SC-control
character
applied
of AR or MQ
set of nets,
routine.
SUBROUTINE
interface
is still
the
from the
-0
all ones),
for a new shift
to the interrupted
required
’ at SCTO, which
does not contain
again
and
by pulses
If SC does not contain
If the counting
a subroutine
of signals
all shifts
shift.
(6.5).
is often
directly
sequence
shift
returns
shift operations,
by SC is produced
the first
6.5
Because
operations,
the shift-count
before
the appropriate
triggered
counted
SC8 is not 1 or SCO-7
either
of the delay
in character
MQ
shift
begins
by
the fractions,
division,
a 2-bit
in the floating-divide
the single
shift
for all of these shifts
that
begins
are controlled
by the special
ters
(6.22,
shift
6.3).
in Figure
6-7 and
The remaining
for
particularly
control
add
subroutine,
division,
all
handled
the
net
are
clear
triggers
interface
at
with
the
MQ,
pulse
the switch
of MB and
right
include
some are connected
of Figure
logic
pulses
by levels,
subroutine
made
the
are
entry
directly
to
AR negate
routed
or
through
the
to the AR subtract
AR,
and overflow,
directly
to the
handles
but overflow
overflow
most pulses
register
for
in an arithmetic
sub-
gating.
multiplication,
shift
operation
is
(6.2~).
and
main
to drive
of Figure
6-17
are gated
are
trigger
or the AR complement
of every
amplifiers
that
time
ions from
figure,
form
charts.
inputs
Al I connect
pulses
diagram
subroutine
the pulse
which
flag
in the flow
of the
for the regis-
in block
that collect
functions,
right
shown
place
top
subroutines
the gating
control
flip-flops
sequence.
additional
6-21,
For this
clear
a third
in the
with
purpose,
lines.
prefix
subroutine
Two
the master
of these
DS is in the
with
upper
6-26.
types of data
charts
for all
word without
at the
with
are
overflow.
SBR flip-flops
beginning
in the lower
Three
than a word
the
all
6.6
three
from one area
listed
operations,
case,
several
of Figure
upper
all shifts
for gates
detect
All
but
floating-point
cleared
MP are
nets that
to MB,
in the
one special
logic
right
of MQ
for
In some cases,
of MB and
by a net included
for
gating.
For the other
and described
at the appropriate
functions
switch
through
the
for
6-7
are mostly
for the registers.
the transfer
and
6-17
right
than
the
For example,
prefix
in Figure
interface.
routed
Except
is shown
shift
to the register
logic
subroutine
are
each
other
the
in Figure
configurations
in the upper
chains,
routine,
shown
The exact
nets
transmission
time
inputs
transmission
types are’in
in memory
to the left or right.
SUBROUTINE
instructions
Figure
to another.
and can insert
affecting
DATA
a character
the rest of it.
There are several
4-9.
switch
iNSTRUCTIONS
to subroutines
The block
transfer
The character
operations
into a word
in memory
Shift
operations
shift
configurations
6-25
move
for their
execution.
moves an entire
handle
or retrieve
single
characters
a character
the bits of a word
differentiated
block
mainly
or pair
Flow
of words
smaller
from
a
of words
by the effects
of the shift
on the register
rather
than
data
power
of 2.
The last group
extremities.
transmission;
the arithmetic
-a
A flow chartof
is in Figure
the block
6-18.
the instruction
a word
from
provide
source
S.
S and D, and returns
the effective
The first
C(S).
fetch
cycle
and destination
address
halves,
The subroutine
cycle
retrieves
in Figure
the word
by a
respectively,
4-9 and the time chain
of the accumulator
S and D.
The first
then stores
the word
to retrieve
and store a second
addresses.
AC,
The entire
swaps its halves
of the execute
execute
cycle,
C(S).
The first
ET1 then
clears
MA and swaps the MB halves
(S, D) in MQ
to multiplying
operations
Transfer
addresses
contains
subroutine
as logical
in location
sequence
addressed
by
cycle
retrieves
fetch
D, increments
word
both
according
is iterated
to the
until
D equals
E.
At the beginning
the first
is equivalent
is at the right
and destination
to the fetch
source
Block
instruction
The left and right
location
incremented
transfer
shift
may be viewed
pulse
and make
AR contains
pulse switches
BLT TO (Figure
6-18,
C(S) available
so that
S is available
(D,S),
MB contains
MB and AR to save
so ET3 can transfer
upper
to memory
left)
and fetches
(0, E), and MQ
E and bring
D to MA.
which
from MB.
to MA,
(D,S)
to MB.
ET3 also triggers
switches
MB and MQ
It also requests
to save
a memory
write
to store C(S) in D .
Upon
receipt
of the memory
are now in both
and
D.
BLTT2
Following
the BLT time chain
The next
registers.
(S, D) in AR.
from
return,
clears
pulse
then switches
ARLT and the next
the AR subroutine,
D-E to MB and the two addresses
tion result
bringing
AR,
incrementing
both
E to MB,
Upon
addresses.
to MB and
retrieval
of an accumulator,
so the processor
addresses
in MB as though
they had just been
following
table
the
shows the contents
a subroutine
called
fetch
the return
addresses
lowing
reenters
and triggers
of AR,
cycle
MB,
pulse calls
retrieved
and MQ
6-26
(S, D) to MB.
pulse moves
that
from AC.
following
just following
using
of
pulse
the
the incremented
For convenience,
each
halves
moves the new
This is the point
procedure
E
the subtrac-
adds 1 to both
saves E in AR,
the entire
E is now in MB
and returns
the subroutine
BLTT6
the addresses
to subtract
The next
to AR.
repeats
to MB so that
the subroutine
E in MQ
at FTl A.
by the pulse).
MQ
MB and AR so that
BLT T3A places
BLT T4 then moves
to MQ,
transfers
the fol-
in the sequence
(or
AR
D,s
INITIAL
ET0
ET1
BLT TO
BLT TOA
BLT Tl
BLT T2
BLT T3
BLT T3A
BLT T4
BLT T5
BLT T5A
BLT Tb
Since
E is initially
cycle
following
sign
is positive.
MQO
(D4,
program
the block
a block
strobing
BLTDONE
usual
in the store
the priority
manner).
are still
ones.
sibly
to repeat
have
been
addresses
cycle
main
though
the final
from AC,
and begins
are five
sequences
instructions
for execution:
Since
where
are stored
on to BLT T6.
the processor
it had previously
Character
provision
is generated,
returns
the level
terminates
is negated
block
transfer,
there
in place
After
in the
addresses
(D6),
to the instruction
by the PI request.
for
cycle
all
osten-
requests
fetches
the new
require
two main
left off.
group,
four of which
and if necessary
6-27
increments
is
of the
Operations
operation
fetches
There
instruction.
includes
in the accumulator
to the interrupted
in the character
part
BLTLAST
the
throughout
at BLT T6, so the incremented
but it is interrupted
returns
the first
If a PI request
switch
to ETlO.
cycle,
-b
There
MB-AR
addresses
the store
the program
the subroutine
BLT T4.
and BLT T5A tests
at ET1 is inhibited
of going
the
is 0 so the
is 0 at this time,
goes on to the next
sequences,
until
the result
to MQ,
If MQO
to ET1 0 instead
at every
to E; then
the result
counting
is negative
MQO may not be 0 (if it is, the subroutine
the same instruction
serviced,
D-E
D-E
it equal
and the processor
and the current
Following
E
D+l
is complete.
program
returns
system
This prevents
inhibit
of D makes
(the normal
in AR and BLT T5A goes directly
no store-AC
original
interrupt
even
S/D
of the address subtraction
the block
may use many
is asserted
E
at BLT T4 and BLT T5 move
whether
D
S,D
S/D
the indexing
and the subroutine
transfer
C(S)
c(s)=S,
D, the result
is incremented
are no operations
Since
in which
88) to determine
transfer)
S,D
S+l,D+l
Ex,
The transfers
counter
D,S
C(S)
C(S)
S,k-==2~
D
than
MQ
E
EV
E
E
greater
that
MB
the pointer,
the
second
handles
character
shown
the character
operations
in Figures
main
control
fetch
cycle
tion;
the address
the I, X,
levels
deposit
P in the word
instructions
increment
the pointer
The maior
part.
flip-flops
The first
a PI request
during
is ANDed
the program
flag
to the address
CH INC OP,
upon
which
part
executes
a block
CHF7
routine,
the JSR saves CHF7
point
a priority
remains
with
whose
only
by the master
clear,
and clears
6-28
may occur.
However
it so that
for the fact
that
that
and
that
is asserted
This level
the first
part
interrupt
returning
to the
was lost).
of CHF7
by the master
part,
levels
6- 19A2).
the state
at the end of the first
set for the return.
the flags
the pointer
part.
CH INC
part after
and
in the first
and a priority
and is cleared
interrupt
pulse
indicates
the first
to fetch
the pointer
command
(Figure
is incremented
fetches
Two other
the second
The level
assertion
fetch
the
sequence
compensates
the pointer
repeating
main sequence
it is set by CHT9
at which
IOT,
is repeated
are cleared
to the second
When
cycle
increments
must not reincrement
flip-flops,
(6.2~).
that
to generate
(the first
the second
of
in the load or de-
are set by the final
the two parts.
If the pointer
from the first
clear
between
part,
P in C(E)*
from the instruction
the two parts,
merely
and increments
skipping
by the
of size S from position
The deposit
it at position
from
as the number
in the second
fetches
of which
the pointer.
sequence
most control
remain
CHF7(0)
ly increment
interrupted
both
the program
is defined
its position
a character
the program,
part are derived
distinguishes
the character
into AC.
merely
The first
of the operand
part and use this new pointer
to continue
part of any instruction
with
must actual
cycle
CHFS and CHF7,
can interrupt
justified
end of AC and inserts
for the first
flip-flop
the first
occurs,
levels
retrieves
The last instruction
to the instruction
control
two control
follows.
address
the load sequence
the
from the instruc-
Two of the instructions
in the word.
in the first
calculated
P specifies
is
instructions,
of the pointer,
address
the operand,
its size;
E and loads it right
from the right
then returns
Within
for all
for the two parts
I ists the different
the effective
The load sequence
sequence.
that
part calculates
part and then one enters
of S bits
sequence
and the logic
to the effective
of the character
in location
4-9
and the configuration
S specifies
a character
posit
execution,
of the pointer.
to the right
of Figure
according
of the pointer:
in the first
the
their
in the second
and Y, portions
the pointer
half
The flowchart
pointer.
The top of the flow chart
the pointer
cycle
by the incremented
the left
and 6-20.
governing
fetches
bits remaining
other
occupies
6-19
P and S portions
designated
Unlike
(D3) must
start
via the
the sequence
returns
If an interrupt
if there
merely
is a iump to a sub-
it may be used by the break
When
routine.
the routine
is complete,
clear
and restores
its original
when
the program
repeats
CH INC
to assert
instructions
part.
The first
fetches
pointer,
but CHINC
sequently
part,
PC+1 is inhibited
Th’ IS I evel
from
OP requests
Since
a fetch
there
ET0 triggers
the subroutine
starts
(upper
the zeros of MBO-5
(i . e. % ,P) into
first
pulse
enables
as data
SC .
-P+S-1
P + 1, the result
completion,
to index
character
go to the next
The chain
struction.
the MB6-1
this time
which
SC so that
interpreted
again
data
sets CHF2
inputs
than
which
36 cannot
position
the new
which
to the next
point
the partial
6-29
addition
enabling
until
upon
the return
i.e.,
if S >
location
SC and calls
location.
Upon
P-S,
CHT3A,
into
a loop.
must
36 -S.
for any nonincrementing
merely
transfers
of
Actually
Thus if the pointer
CHF2(1)
the
the position
location.
than
to
of the position
following
put the processor
at CHT7
then
into SC and returns
in the next
call:
the
CHF2(1)
the complement
results.
it
loads -P-l
clears
P is 100 -S rather
is no subroutine
pulse
character;
it now contains
character
is the starting
but there
to SC so that
36,
otherwise
so that
If SC0 is 1 at the junction
an S larger
is no pointer
must go on to the next
of S generates
or the first
If there
is not cleared
of 0 size)
SC so that
instruction,
more time.
to CHT4,
for a character
mod 64 so the correct
to CHT6,
for another
Y of the pointer
complements
than
CHFl
the
may sub-
to AR and sets CHFl,
add a little
continues
the addition
and S is larger
continues
CHT6
l(1)
into
location
then
-P-l
in the same location
loads -229
is then
(i.e.,
portion
for the new location.
(B3),
left
pointer
add at the next
sign and the instruction
the address
SC add again;
skips to CHTS
The result
bits
sequence
to rewrite
6-1984);
add in the SC subroutine
are not enough
memory
part.
(Figure
SC add.
partial
part of the two
for each
the first
Then
causes
by either
allows
count
the pointer
the partial
the CHT2
is cleared
at CHT6
and calls
for the partial
loads -37
of the pointer
CHT4A
sets CHF2
via the flag
the flags.
in the first
the incremented
uses only
transfers
to SC so that
to give
If there
CHF7
one program
chain
Thus if SC0 is 0, the chain
CHT4A
to call
time
CHF7
it restores
CH 2, INCOP
which
pulse
in SC has a positive
an AR subroutine
the next
then
MB6-11
.
for the character.
chain
inputs
CHT3
the ones from
portion
The first
in the SC add chain
SC contains
CHT3
left).
E:
must be only
incrementing,
that
is also asserted
and pause so that
but the IBP (CAO),
clears
CH INC OP and instead
Finally,
location
by all
at CHTl
inhibits
the pointer.
the pointer
be deposited.
CHF7(1)
(C5).
do not increment
in the second
JRST again
from MB4 at the same time
the first
CH ‘L INC OP
that
part
state
the restoring
inenables
S into
it.
For
CH s INC
tions
OP,
already
the chain
mentioned
because
specifically
for CH INC
from SC3-8
into ARO-5
then
it.
(dropping
The return
from MB04
required
by the instruction,
cycle.
count
(C2) which
shifts
clears
SC and IR13-17,
in the address
cycle
following
the next
execute
request
at the beginning
MQ containing
load
word
is then
triggered
AR.
the character
CHF7
in both
transfers
Thus MB contains
it other
which
than
returns
include
in the chain
P in SC,
and calls
AR P places.
contains
in tne
character
position
6-30
CHT8A
of the pointer
that
is a PI
start
of the pointer,
and
and zeros elsewhere.
FC(E) as there
(A2).
wil I be
LCTO moves the
the shift-count
this,
subroutine.
LCTOA trans-
part containing
the deposit
moves AR and MQ
completion,
the mask to MB,
all ones.
the shift-
Both sequences
Following
and ET0 enters
that
whereas
calls
the desired
to ETlO.
Upon subroutine
the mask,
to ST7 for
the return,
left
DCTl
contains
then
which
the data
transfers
contains
zeros
(Ad).
loading
the character
The pair
the ones from MB to MQ,
MQ
sequence
P places
AR contains
and the ones in the mask are in the same position.
by the return
position
gates
and pause,
a shift-count
operation
returns.
address
at the right
of AR except
and returns
a fetch
registers.
all
then
pulse
shifting
AR thus clearing
request
position
the first
by right
P in SC and calls
in the appropriate
AR clearing
justified
instructions
in at the right
plements
right
The initial
complements
is the only
in case there
6-20.
to the effective
to
P from FE to SC, sets Cl-IF5
the sequence
at the top in Figure
E.
in E, and ET0 triggers
The pulse also clears
DCTO complements
pulses
AR contains
cycle
the I and X portions
and sets CHF7
up of ones in the last S places
from the mask into
The two deposit
to which
according
to AR and the mask to MB,
character.
zeros
retrieved
part,
CHT7
the new P
Upon
transfers
it
transfers
than an IBP, CHT8B
for receiving
events
SC.
memory
and CHF2,
ones in at MQ35.
the second
cycle
and clears
the pointer
other
Then CHT9
part are shown
instructions,
storage
The character
fers zeros
made
loading
select
CHF6
opera-
by transferring
here and the sequence
operation
part.
of the address
the word
a word
no subsequent
will
for the second
MB containing
For the two
cycle
the pointer
the read/write
If incrementing
in preparation
the first
both
terminates
S places
the latter
so that
The two chains
left
restarts
clears
For any character
MQ
CHT8
S in SC.
the subroutine
the new P into
and CHT7
in MB; additional
SC mod 64 is transferred)
which
which
OP uses the CHT6
from the old pointer
inserts
means
to MB after
to FE and complements
instruction
CHT6
CHT8B
CH INC
available
SCO-2
triggers
a new
data
S is still
OP are that
moves the new pointer
deposit
with
then skips to CHT8B.
word
of
and comother
than
from the mask to
the complement
of the
in
At the same time,
character.
to MB.
The next
and DCT3 then
ferring
zeros
the character
cycle
CHF7
specifies
no character
is processed.
36,
If both
from position
part of Figure
6-20
the character
word
by transof MB.
restarts
This
the waiting
is at most the entire
P and S are less than
P or the right
the right
the level
(86) w h’IC h causes
SHAC2
The direction
of the shift
of places
portion
word.
36 but P + S > 36,
36 - P bits of the character
For
a character
are deposited
AC.
ing is considered
by bit
cycle,
ET0 transfers
to be positive
SC is already
and contains
a positive
to trigger
SHTO (B5),
structions
and the first
the correct
connections
to the registers
shift
inputs
and described
control
with
shifts
the AR and MQ
show the configurations
for all
twelve
word
(0 left,
into SC.
it is assumed
of shifts
the number
generate
accumulator.
1 right),
and the
(6.2~1,
6.3).
types of shift.
6-31
Block
chain
MBl8(1)
interface
extremities
left shift-
if bit
counts
is
gates
ET1
for all
in-
SC now
SC up to all
(6.5),
below
is 0,
if MB18
of MB18.
are shown
diagrams
con-
18 is 1,
so that
to the state
the subroutine
Since
Thus MB18(1)
which
according
MQ
however
the subroutine
the shift-count,
shift,
Thus if MB18
number;
SC on the condition
through
that
desired.
of shifts.
Then ET3 starts
at the register
gating
instructions
and store a second
of a positive
left or right
are made
actions
and the flowchart
and for a combined
negative,
also calls
AR and MQ
the shift
to fetch
AC;
of the number
SHTl
combined
of MB1 8, 28-35
shifting
complements
complement.
shift
that
AR contains
one less than
pulse SHTl
count
sequence
operations
18 of the instruction
adds one to SC.
ones and at each
The three
the complement
number
which
4-9.
the shift
by bits 28 to 35.
and right
the 2’s complement
1, SC contains
governing
the complement
bits 28 to 35 contain
correct
Operations
the main
is specified
of the execute
a second
of Figure
is specified
to be shifted
At the beginning
Shift
shows the logic
for them occupies
contains
of the character,
into the all ones portion
store cycle
back
P.
The lower
tains
in the data
The subsequent
than
-c
number
position
is moved
in E.
a size greater
of size 36 - P is loaded
in position
word
ones outside
bits are ones)
to ETlO.
position
it contains
the appropriate
(all other
the data
ones in the character
AR so that
into
and returns
to deposit
word with
complements
from the character
If the program
P > 36,
pulse again
inserts
pulse also clears
memory
the data
andthe
in Figure
The
special
6-7
the flowchart
Since
an arithmetic
is included
shift
multiplies
in case significant
arithmetic
shift,
the overflow
a 0 in a negative
number
truns to the main
sequence
fixed-point
structions
describes
The return
ARITHMETIC
multiply
Fixed
cycle
to a special
add and subtract
the arithmetic
from ET0 and is described
either
of the two fixed-multiply
chain
C(E) or E itself
whereas
in the former
double-length
MPTO (Figure
6-21,
and sets MPF2
waits
until
(6.2).
with
Fixed
integer
Both instructions
upper
left).
the desired
enter
the special
are negative.
to MPTOA.
If both
It also calls
operands
+1 overflows
the representation
stored
For integral
integer
half
generating
and the result
the fractiona.
accumulator
multiplication,
in the low-order
is not clear.
the standard
transfer
is negative,
for all
MPTOA
half
MPT2 then
and store
only
for -1.
MPTOA
is complete
return
into the
bits
to MB and sets the overflow
transfers
the result
following
6-32
and the result
if -1 is multiplied
to MPTl,
to AR so that
the return
half
fraction,
of the
35 steps
subroutine
(6.8b)
by -1,
the high-order
returns
half
transfers
NRT6,
half
is
is stored.
the resulting
if the high-order
the sequence
to ET10 via
in AR.
to ET10 via
no accumulator
flag
whose
is being
the low-order
which
and
is also neg-
multiplication
In the store cycle,
the chain
use AC and
in SC to count
the multiply
wherein
6-21
at ET0 by triggering
If integral
mode
Figure
multiplication
sequence
complements
but the memory
4-8;
is in the low-order
from MQ
functions
directly
cycle
case is a double-length
and the sequence
subroutine.
continues
the execute
enters
are negative
This can occur
process
in the normalize
in a second
an
part of Figure
This pulse sets the appropriate
answer
pulse
may or may not call
and fractional
that
flag.
the final
is in the left
it is assumed
MPTOA sets the overflow
At this point,
in-
in 6.85
in the latter
if both operands
(IRb(0))
subroutine
Both integral
ative,
performed
Each of these
within
divide
but the product
MST6 returns
re-
Multiply
instructions
for them.
performed
Fixed
that
which
as operands,
product.
which
instructions.
sequence
are both
register
2
time
SHTlA
or
INSTRUCTIONS
and the floating-point
divide
shows the special
triggers
number,
at ETlO.
with
A flow chart
from the shift-count
condition
or double-left
out of AR1 in a positive
is set if a 1 is shifted
and are described
subroutine
In a single-
flag
(6.2~).
fixed
subroutine.
of 2, an overflow
shift.
goes from the execute
arithmetic
by powers
bits are lost in a positive
6.7
This section
numbers
can make
NRT6.
use of
b
This instruction
affecting
allows
the program
the fractional
contained
part.
in 2’s complement
struction
occupies
of Figure
The first
The number
notation
Scale
the exponent
by 2’ where
in AC is multiplied
address.
as the sign,
the left quarter
of a fl oating-point
of Figure
4-10,
as positive
is 0 or 1 . The flowchart
18,
and the time
chain
without
y is the number
i s interpreted
This number
bit
number
is shown
or
for the in-
in the lower
d-19.
pulse
two pulses
plements
to change
in bits 28 to 35 of the effective
negative
right
Floating
in the execute
then
adjust
cycle
transfers
SC according
SC; if negative,
of MB18,
to the sign of the number
ET3 adds one to SC by triggering
FSTO, which
calls
the SC add subroutine.
the ARO-8(l)
data
inputs
to the exponent
the complement
to SC.
During
The return
pulse
in AR:
FSTl .
28-35
to SC.
if positive,
In either
ET1 com-
case,
the subroutine,
the 1 state
FSTOA transfers
the new exponent
part of AR; and if the signs of AR and SC are different,
The next
ET3 triggers
of FSFl enables
from SCl-8
it sets the overflow
flag.
To see that
overflow
exponents
the above
sequence
or underflow,
consider
produces
the various
notation.
2, x,
i.e.,
255 - x.
otherwise
the 2’s complement,
exponent
in mind
by the numbers
factor
in MB.
On the other
i .e.,
256 - y.
that
values,
Thus if AR is positive,
hand
if MB is positive,
At each
step,
and properly
detects
the floating-point
0 to 255 and that
Let x and y be the absolute
part of AR and the scale
otherwise
the correct
cases keeping
from - 128 to +127 are represented
in E is in 2’s complement
exponent
of events
the scale
respectively,
ARl-8
fat tor
of the
contains
MB28035
C (SC) is a function
contains
MB+
ET0
-[255
- yl
ET1
ET3
SC
ADD
AR-,
MB+
AR+,
MB-
AR-,
MB-
-[255
- yl
+cy - 11
+Ey
- 11
+[yl
-[255
- yl
-[256
- yl
+cy
- 11
+Cyl
-[256
- yl
-c256
- yl
+Cyl
+cx + yl
-[255
- (x + y)]
+cx - yl
6-33
-c255
y;
of the signs
of AR and MB as follows:
AR+,
x;
- (x - y)]
Hence
with
no overflow
per representation
flow)or
or underflow,
SC and AR have
of the new exponent.
in the last two x - y < 0 (underflow),
-c
Both of these
instructions
special
sequence
(Figure
the subtrahend
subtracted
the center
is then
in AR,
has now been
ET4 triggers
replaced
the floating
transfer
the MBO-8(l)
data
the signs are the same.
and shortly
to SC.
by its complement,
the difference
values
tations,
AR,
between
signs.
in the upper
For floating
the operands
FAT0 complements
to SC so that
case,
the partial
addition
the complement
the
to be
be added
and
FAFl
and sets FAF2
the result
of the addition
unless
of the numbers
there
It also sets FAFl
at FAT1 produces
that
of AR.
(A3) to enable
at least
a 1
if
FAT1 also triggers
the ARO-8(l)
one exponent
data
is represented
in SC is a l’s complement
is overflow.
in AR and MB.
ones.
of the MB sign and exponent
the sign of SC is opposite
clears
the exponents
SC to all
negative
of
Let x and y be the abklute
The possible
signs,
exponent
represen-
are as follows:
ARO-8
SC Before
SC After
DC255 - y + xl
Result
+cxl
-[255 - yl
AR+,
MB-
+ Cxl
-[255 - yl
1
-[255 - y + XIJ
AR-,
MB-
-[255 - xl
+[yl
AR-,
MB+
-[255 - xl
.
+Cyl
if the MB exponent
and AR because
the number
may instead
MB+
the addition.
ET0 triggers
6-22;
MB and AR so that
Since
AR+,
Hence,
half of Figure
add,
ET0 switches
subroutine.
the signs of AR and SC are different,
of the exponents
MB signs
4-10.
the negate
but transfers
FATlB
and hence
and results
shown
subtract,
by its negative,
inputs
In either
after,
Since
but for floating
are the same,
if the signs are different,
SC add,
opposite
255 (over-
x + y >
add sequence.
If the signs of the operands
enabling
of Figure
and ET3 calls
two columns
Add-Subtract
add time chain
portion
6-22Al);
if in the first
AR and SC have
Floating
use the floating
the flow chart occupies
inputs
However,
the pro-
the same sign and SC contains
is greater
If the AR exponent
the number
with
than
is greater,
the smaller
y 1 x:
signs #
y < x:
signs = -[255 + y - xl
y >x:
signs # -[255 + y - xl
y Lx:
signs = the AR exponent,
the AR and SC signs differ
the signs are the same and
exponent
6-34 is the one that
FATlA
is shifted.
switches
after
MB
If the exponents
are equal,
place.
the signs may or may not be the same but it matters
Since
is negative
the result
in SC is a l’s complement,
, and in this case FATlA
produced
a positive
exponents
(since
notation);
in this case FATlA
in preparation
ensures
the smaller
(6.2~1,
6.3),
in AR and MQ
triggers
which
sets FAFl
complements
portion
transfers
are still
exponent
follows
value
MB to it.
These two simple
if overflow
between
has
the
and FAT3 complements
it
sequences
and the logic
from
inputs.
triggers
pulse
FAT7
subroutine.
the sign
has been
of magnitude,
The return
the
FAT5A
changes
receives
in the chain
clears
right
clears
SC to all
the MB sign and exponent
If AR was cleared
FAT1 0 which
by loading
is no shifting.
Thus SC always
The next
FAT5
to the registers
in order
Then
nor the
are required,
the number
loads SC with
of SC.
(a condition
the fraction
inputs
After
FAT6 if there
AR add.
return
shift
the MB bits
data
the state
The return
pulse
Floating
do I ittle
more
multiplication
is shown
in each
in SC the complement
and enters
arithmetic
add at FAT8
FAT9 calls
neither
than 64 shifts
subroutine.
of the exponent.
and
can affect
match
directly
upon
than 63 places
a positive
then
at FAT6,
nullifies
the addition
those control
via
NRT6
the
flip-flops
that
is directly
to
of the result.
at ET0 and the first
divide)
if it
in l’s complement
MSB are of no significance
correctly
the normalize
of floating-point
FPT4 places
However
on numbers
if fewer
the MBO-8(l)
-d
4-10
H owever
and the partial
set and enters
execution
takes
on it is necessary
the difference
more
the addition
the correct
its bits
to enable
of MB,
ET1 0 for storage
Figure
must be shifted
AR (A8).
depending
sign and the absolute
merely
(A6).
adds one to SC,
and cal Is the shift-count
ones if MB is negative,
exponent
was performed
FAT2 which
to generate
so that
FAT5A
SC and again
or their
addition
bits to the left of the fraction
sets FAF3(B4)
extremities
to FAT4
action
in SC is one less than
triggers
part so FAT6 clears
into ARl-8,
return
the number
a 2’s complement
with
that all
shifted
jumps directly
by at least one 0 in SCO-2),
low-order
no further
the transfer
for the shift-count.
If the number
represented
result,
not whether
the appropriate
Multiply
and Divide
than
the three
call
and division.
in the lower
calls
half
the exponent
of the number
subroutine.
subroutines
The flowcharts
6-22.
calculate
subroutine.
The return
6-35 Both chains
at MST7
in
are triggered
The return
(27 for multiply,
from multiply
for the
are at the right
of Figure
of steps required
necessary
from
30 for
triggers
FMTOB,
which
mal ize shift
transfers
gates,
the calculated
exponent
and enters normalize
from
FE to SC,
NRT6 returns
return.
sets NRF2
directly
to set up the nor-
to ET10 for storage
of
the result .
The divide
equal
subroutine
to half
first
the dividend,
to ST7-the
only
the division
is executed,
from
tests that
the sequence
normalized
number
DST21A
can be performed.
sets the overflow
that
returns
fails
to satisfy
to FDTOB,
subroutine.
floating
divide,
possible
overflow,
time
pulse,
enters
This subroutine
by doing
the other
FDTl,
normalize
30 steps,
which
return
for rounding.
shifts
and NRT6
the simple
by more than
with
a subroutine
fixed
and floating
calculates
multiplication,
floating-point
normalize
that
instructions
the result
of their
except
a
Floating
operations
multiply
call
on the fractions.
and the logic
drawing
and divide
for the time
generate
OR and equivalence
tinction
between
whereas
in division
several
lf
exponent
the normalwhereas
bits,
one for
includes
for the rounding
an extra
bit.
It then
of the result.
and floating
The multiply
subroutine
scale
subroutines
call
by both
that
division
subroutine
fixed
both
is used by both
and floating
the normalize
are called
return
division.
subroutine
to
computations.
Exponent
a subroutine
The flowchart
chain
is shown
levels
necessary
Calculate
to calculate
for exponent
in Figure
the exponent
calculate
6-23.
for execution
signs and FMFl,
multiplication
and division.
In multiplication
6-36
beginning
is at the left
in Figure
of the subroutine.
of the operand
of the divisor
before
The nets at the right
functions
the exponent
quotient
sequence
multiplication
the exponent.
arithmetic
two extra
are four arithmetic
Floating
floating
DST13
SUBROUTINES
there
the divide
the calculated
one bit overflow
instruction
or
is a zero divisor.
to ET10 for storage
ARITHMETIC
from
but does not enter
to compensate
directly
operation.
gates
generates
right
AR and SC subroutines,
one arithmetic
begin
returns
transfers
for only
The divide
AR and MQ
6.8
Besides
deliberately
is less than
and jumps directly
this condition
shift
can compensate
If the divisor
flag
which
FE to SC and sets NRF2 to set up the normalize
ize return
All
division
is subtracted
in the logic
These are exclusive
the last term providing
the exponents
from that
4-11
a dis-
are added,
of the dividend.
Since
FMFl
is the SBR for the return
plication
but 0 in division;
therefore,
opposite
of those for division.
The first
time
upper
left).
in either
The first
complements
occurs
pulse
d a t a inputs
action
(upper
next
other
pulse
OR of ARO,
calls
by FPF2(1).
two,
consider
then
at FPTlA
another
After
is positive;
excess-l
in division
sequence
is included
the same,
bits
FPTl B complements
FMFl
the exponent
FPT4 returns
is set,
Finally
so the complement
holds
net for SC.
The
Then FPT3 transfers
of both
inputs
special
SC is again
the calculated
sequence.
occurs
if AR0 is 0;
complemented,
if MB is negative.
otherwise
On the other
if AR is negative;
and indexing
for the
MB and AR by loading
thus at FPTl the complement
if AR0 and MB0 are the same,
The
condition
as the SC data
to the interrupted
at FPTl occurs
complements
for two of the four cases;
SC.
pulse
the
it adds one to SC.
MBO-8(l)
portions
at FPTl 8, SC is complemented
The next
FPTlA
in the complement
is correct
(Figure6-23,
the complement
if the appropriate
using
the result
and nullifies
1 to 8.
this time
chain
SC.
At the return
only
the
FPTl also enables
otherwise
if the signs of AR and MB are not equal,
occurs
otherwise.
at FPTlA
Finally,
hand,
com-
FPTl B
SC if MB is positive.
To see that
and MB.
this addition,
multiplication.
is 0 for division,
complements
is generated
SC addition,
SC,
sign into
it is indexed.
plementing
which
128 into
in division.
is false;
time
of FMFl , i .e.,
the SC add subroutine.
for the complement
to FE, clears
First,
from the state
it is 1 in multi-
are exactly
the floating-point
sets SC1 thus loading
or negative
calculation,
for multiplication
triggers
MBO, and FMFl
by FPT2,
MB0 and FMFl
the appropriate
FMFl
pulse
to SC and calls
the gating
then
exponent
or divide
in multiplication
is triggered
right);
enabled
multiply
SC if the sign of AR is different
SC if the exclusive
latter
from the exponent
the sign functions
floating-point
if AR is positive
ARO-8(l)
to multiplication
these operations
Since
excess-128
but if negative,
28 code,
the correct
code
is used,
operates
tents of SC1 -8 as a positive
result,
let x and y be the true exponents
the exponent
portion
it is 255 - (x + 128) = 127 - x.
the sum of the exponents
the difference
of events
give
must be increased
in SC as follows
must be reduced
of AR is x + 128 if the number
Since
number):
6-37
the result
must also be in
by 128 for multiplication;
by the same factor.
(the table
of AR
For multiplication,
whereas,
the above
items show the sign of SC and the con-
AR+,
MB+
AR+,
MB-
AR-,
FPTl
-c127l
-Cl271
+c1281
SC ADD
+rx
+cx - 13
-c255
FPTlA
+1x1
-c256
- x3
+Cxl
SC ADD
+[128
-cl27
- x - yl
+[128
+[128
+ x + yl
- 13
+ x + yl
FPTl B
For every
the result
case,
positive
form),
ponent
remains
in positive
return
subroutine
checks
the sequence
unless
in SC is the correct
there
of events
is overflow,
exponent
- xl
+ x + yl
-[255
- xl
-[256
- xl
-cl27
- x - yl
for the product
subroutine,
and puts the exponent
(but expressed
result
and the subsequent
into
correct
form.
For division,
MB+
AR+,
MB-
AR-,
MB+
AR-,
+c 1281
-11273
SC ADD
- [xl
4x3
+[254
- xl
+[254
FPTlA
+[255
- xl
-IX
+c255
- xl
-Cl
SC ADD
-cl27
- x + yl
+[128
-cl27
- x + yl
+[128
FPTl B
+[128
+ x - yl
+[128
+ x - yl
the correct
result
+x1
+ x - yl
in positive
b
A single
subroutine
types differ
only
routine
flow chart
chain.
A pulse
ber of steps into
in multiply
For fixed
handles
point,
occupies
portion
the subroutine
point,
Either
triggers
time
the entering
MST1
(upper
left),
point,
4-l
the subroutine.
is triggered
is FMTOA,
which
point
sequence
are ORed
chain
pulse
fixed
of Figure
or floating-multiply
the two SBR flip-flops
-Cl273
- xl
+x1
+ x - yl
Multiply
35 for fixed
SC, sets an SBR and calls
MB-
form.
for both
of steps-
the center
in the fixed-
for floating
pulse
multiplication
in the number
shifting,
The ex-
normalize
+[1281
gives
in
(SC0 = 1).
FPTl
again
x + yl
is:
AR+,
which
MB-
+[1281
by a negative
the multiply
for overflow
AR-,
+[128+
as indicated
form during
MB+
which
moves
6-38
and floating
point;
27 for floating
point.
1; Figure
6-24
follows
which
in Figure
is equivalent
the exponent
the multiplier
of the num-
the AR and MQ
by the net at the right
by MPTO,
The sub-
shows the time
loads the complement
To control
the two
extremities
6-24.
to ETO;
calculation.
from MB to MQ
and the
multipl
icand
continue
to either
and 36 of MQ,
right
MST2,
step,
the bit MQ35
there
is a transition
no arithmetic
return
from
MST3A,
which
AR subroutine
is called
or not.
It then
the sequence
been
returns
shifted
into MQ35,
At the 3-way
i.e.,
MSB and MQ35,
the sign.
left).
whose
branches
count
is complete,
shifts
the low-order
of the high-order
to the 3-way
the equality
is not complete,
(lower
in a pair
of multiplier
following
direction,
MST4 calls
Thus MST2 appears
to check
rather
which
than on
calls
is
If
the AR
AR subtract.
AR,
the next
when-
MST1 , there
in every
SC and shifts
and MQ36
goes to MST2.
goes to MST3,
decision
branch
SC does not contain
If these
If they
half
777.
Either
loop whether
MQ
right
bit pair
which
of the product
in MQ
MST6 then
in AR.
from
any
one place.
(which
that
has just
MQ36
the step count
receives
leaves
the loop,
to the 3-way
decision,
call
MST3A
AR subroutines.
to MSTS.
to the right,
provides
shift,
MST2
necessarily
jumps directly
condition
In the final
MST2 returns
are not equal,
the return
has the additional
two bits are equal,
are now open -those
half
decision
bits,
the chain
increments
On
are performed
and in this case the chain
goes to MST2.
is 0.
36).
decision,
MST5
versa
At the 3-way
bits 35
bit of the multiplier
operations
may
of AR and MQ
and MQ36
Arithmetic
in the opposite
This pulse
between
of SC and the shifting
step.
1 to 0 in the bit pair,
For a transition
triggers
1 or 0.
the sequence
the relationship
the next more significant
if the two bits are equal
is a transition
upon
Form MSTl,
the LSB of the multiplier
1 to 0 or vice
bit being
action
add subroutine.
contains
contains
from
thereafter.
the incrementing
held on the previous
the basis of a particular
there
MQ35
MQ35
shortly
or MST4 depending
step includes
Initially,
each successive
ever
MST3,
but every
one place.
contains
AR is cleared
from AR to MB.
the return
jumping
only
Since
This pulse
and makes
the multiplier
two of
the step
clears
SC,
its sign equal
to the appropriate
to
to that
instruction
sequence.
The multiplication
mul tipl ier,
duct
into
MQ
initially
sum was right
AR and MQ
at MQ35,
order
shifted.
0, the sequence
Initially,
as the multiplier
is available
sum in AR is one binary
partial
is as follows:
and AR is clear.
are shifted
the multiplier
sequence
shifts
are connected
is shifted
and the effect
of magnitude
MB contains
greater
out.
calling
6-39
the low-order
At each step,
of the multiplicand
than
Thus MB can be combined
without
so that
the multiplicand,
in the preceding
directly
an AR subroutine
with
until
MQ
the
bits of the pro-
the current
bit of
in MB on the partial
step because
AR.
Since
a 1 is shifted
the
MQ36
into
is
MB35.
At this transition,
is clear.
which
the sequence
The shifting
time
the sequence
The process
1, adding
then
continues
at every
high-order
continues
until
in this way,
transition
To see that
the next
subtracting
from
the multiplicand
transition
(which
Thus,
there
and to place
this procedure
results
AR contains
is an additional
the low-order
in a correct
half
right
fraction
product,
will
at every
The low-order
product.
from AR,
be from
to the previous
the multiplicand
At the end,
1 to 0.
half of the double-length
from AR0 to MQO
to subtract
goes to MST3 to add the multiplicand
of the mul tip1 ier in MQ35.
sign
jumps to MST4
transition
of MQ
sum.
from 0 to
with
to move
magnitude
the positive
at
sign and the
is in MQO-34
in the MQ
consider
1 to 0),
partial
the correct
shift
which
the sign
the correct
positions.
binary
integer:
100111011
876543210
(The decimal
tions.)
digits
below
This number
the binary
is obviously
digits
equal
are the powers
an n-bit
equivalently
k places.
string
100000000
111000
11
k+n
k
k
-2 ,or
rightmost
bit corresponds
to 2 is equal to 2
k
0
2n - 2 is a string of n ones and the 2 shifts the string left
of ones whose
2k(2n-
2’);
i .e.,
Thus:
=:
100000000
=
=
p+
c
In this last representation,
0 to 1 (in the direction
the opposite
number.
alternately
power
of increasing
transi Con.
is 0 for a positive
this manner,
each
The largest
29- 28+ 26- 23+ 22- 2O
of 2 that
is subtracted
significance),
whereas
term
corresponds
The multiplication
subtracting
sum in the order-of-magnitude
29- 28
20
=
100111011
partial
to the bit posi-
to:
+
+
Now
of 2 corresponding
algorithm
the multiplicand
positions
6-40
corresponds
each
that
to the transition
in PDP-6
from the partial
corresponding
to a transition
is added
corresponds
to the sign bit,
interprets
to
which
the multiplier
sum and adding
to the transitions.
from
in
it to the
If a multiplier
of the same magnitude
were
negative,
it would
have
the form:
1011000101
-876543210
in which
the extra
wherein
opposite
bit at the left
to opposite
transitions.
multiplier:
this time
to the sign bit,
which
--c
The time
chain
for the divide
Figure
4-12
is the flow
Either
pulse
loads SC with
point,
36 for fixed-point-through
by IR DIV
generates
by ET0 or FDTOA,
there
tinction,
the fixed-point
the state
of IR6 (Bl).
The first
and calls
floating-point
division
with
fractional
order
Since
the significant
the dividend
jumps
,
entry
half
dividend.
division,
the fetch
drawings,
point,
of the number
six entries,
is further
cycle
of the dividend
position,
brings
upon
that
is triggered
To make
the sequence
jumps to DSTIO
AC to AR,
moves the divisor
for computations.
6-41
negative,
This is also the entry
is fetched
for
for integral
just as does
and it is used for the low-
DST2 then switches
half
to
operations.
was originally
dividend
dis-
according
or floating-point
uses a double-length
the high-order
only
the latter
of levels
one accumulator
and clears
ET0 gated
the dividend
of integers.
from AR to MB.
for floating-
the sign of the dividend
into a pair
for integral
DSTl
and 6-26;
For this purpose,
or fractional.
left)
6-25
the subroutine
decoded
division
Figures
bits.
negation,
for division
but only
magnitude
at FDTOA in floating-point.
depending
is integral
Following
Integral
of greatest
of steps required-30
Although
(D6) t o remember
to DSTl
may thus use exactly
Divide
is at DSTO (upper
subroutine.
in low-order
to DSTlO
level
to:
is now 1.
6-25Al).
division
pulse sets DSF7
a positive
the subtraction
pulse gates at individual
command
but continues
fixed-point
half.
the complement
the fixed
the AR negate
The algorithm
is at ET0 in fixed
are nevertheless
dividend,
subroutine
Entry
is now equivalent
2O
is on two logic
DS DIV TO (Figure
in AR and upon whether
For a negative
subroutine
chart.
The number
z3- z2+ $-
for a negative
by the transition
the sign.
- z9+ z8.. p+
signs correspond
the same sequence
is detected
represents
in AR.
from MB to MQ
MB and MQ,
The sequence
placing
then
and
The only
enters
other entry
at DST3 (Ab).
already
positive.
negative
into
double
the LSB addition).
negate
and adding
add one as required).
all
The computational
at the right
point
or fractional
discussed
fixed
above.
Entry
which
‘L DSDIVI,
original
6-25.
point.
is direct
is made at the subroutine
which
right
dividend
shifts
MQ,
return.
moving
This action
the dividend
closing
of AR0 into
closes
by 2.
the hole
MQ35
the division
the divisor
subtract.
Since
magnitude
of the divisor
goes instead
complements
which
the subroutine
it follows
into
in both
the
700bit
AR0 and AR1 and
is to compare
Thus,
is less than
with
the result
or equal
to that
6-42
is triggered
triggers
AR
7 which
also
through
the net
dividend
in floating
sequences
by
AR negate,
DSTlOA
magnitude
entry
(lower
in AR2035
of the dividend
DSTll
left)
brings
and
but it also
which
left shifts
the complement
is of no significance.
to determine
whether
or DST12 depending
AR add;
of the computation
of the number
the
MQO, so the double-length
the dividend
pulse calls
is neces-
it and then
it is conditioned
but this
is either
The former
or positive.
to DST6,
The shift
connections,
pulse
half
and DST9 calls
goes to DSTlOB,
the same.
the divisor
the next
is positive,
the two halves
the sequence
shift
by complementing
this reverses
and if DST9 calls
DSTlO
on
AR.
DSTOA,
half
the magnitude
9:
for a positive
point;
division,
division
depending
from one of the preliminary
floating
between
is now in
to complement
the LSB of the high-order
of the division
is negative
the dividend
begins
(i .e.,
and
was al I ones before
positions,
at DSTlO,
For a floating
For fixed
can be performed.
whether
begins
up the hole
The next step in the process
half
but merely
represents
but leaving
because
original
half
into the high-order
goes on to DST8,
from DST2 or DST7; from
case
now has the sign bit
MQO-35.
divides
AR,
to their
Otherwise,
is negative
is formed
(the complement
the sequence
positions
This pulse
in this
is null
of the high-order
part of the subroutine
in Figure
A carry
or is
a double-length
branches
number
ET0
in length
the dividend
th e sequence
(B3),
the sequence
all words
wherein
MB and AR so the low-order
half
If AR is not clear,
words to their
because
the LSB.
of the low-order
returning
to change
of a double-length
one into
fraction,
one word
DST3 is necessary
the return
Thus if AR is clear,
interchanges,
is either
DST3 sets DSF7
After
to form the 2’s complement
returns
with
The 2’s complement
word
fixed-point
the dividend
DST4 then switches
sary if the 2’s complement
preceding
entries,
form.
AR negate.
AR is clear.
is for a negative
starting
positive
MB and MQ.
the entire
DSTlO
For all other
and DSTS calls
whether
than
The sequence
dividend
interchanges
AR,
earlier
the latter,
is also positive
in AR.
upon
AR
if the
There are actually
three
different
AR is clear
conditions
and the result
icance
in it,
a fixed
fraction,
matical
cannot
the divisor
fraction,
having
divided
the test is that
occur
as the result
for this.
tinues
than
the sequence
The next
one subtracts
dividend
one place
not overflow,
and
a 1 is entered
the overflow,
into
step.
add the divisor
the PDP-6
the result
positive.
ever going
back
The following
of the sign
dividend,
operations
produces
rotation
from the AR subroutine,
in progress,
which
sets
and DSTllA
the
cancon-
In division
the dividend,
again
continues
to shift
out.
the
In binary
shifts
before
first
does
is positive
To compensate
going
and then
and add putting
generates
The
If the subtraction
a 0 is entered.
This procedure
shifts
the sign of the result
the dividend
instead
on paper,
or not at all at each step.
the divisor,
into
then
subtracts
bit of the quotient.
is overflow,
back
division.
and
once
algorithm
result
result,
the division
except
of the result
the
cannot
If AR0 is 1, the overflow
the actual
either
than
correspond
a negative
SC and triggers
to a combined
case that
to the
for
next
adds the divisor
zeros
into the quotient
the same quotient
without
a step.
processor
test subtraction
increments
becomes
auto-
the only
to DST13,
cycle.
right
return
but this number
For
is allowed.
(the preceding
the return
it goes into
a single
If there
until
fail
continues
to the right)
is larger
It then
again
of times
to generate
on in the new position.
also
of signif-
no overflow
are normalized,
After
performs
the dividend
back
integer,
6-2687).
the quotient.
However
a fixed
but the normalize
type of division
(or the divisor
if the dividend
one could
subtraction
(Figure
goes into
the divisor
i .e.,
of -1 could
the sequence
and
the dividend
fractions
operation).
the number
to the left
the divisor
thus subtracts
(a dividend
the loop that
out the divisor
computations,
loop
comprise
from half
to the end of the store
to DST14A
few pulses
from the dividend
all floating
in the particular
allowed
For
does not overflow.
If it is positive,
jumps directly
if the divisor
35
than 2 -1 which
be one bit overflow
of any floating-point
flag and
of division,
be greater
subtracted
Since
types
has anything
is subtracted
of a 0 divisor
DSTl 1A tests the result.
not be greater
is actually
three
for a 0 divisor;
possibly
it by 2), so theremay
fails
for the
here
only
the divisor
ly compensates
overflow
tested
is positive
the quotient
For a floating
shift
being
that
to the procedure
the sequence
shift
MQ35
of AR,
receives
a 0 quotient
bit.
6-43
Each
enters
MQ
to the left.
loads
If the initial
This shift
of ARO.
if the divisor
loop
above.
the loop at DST14A,
the complement
is the next bit of the quotient:
produces
outlined
one
which
is equivalent
The complement
does not go into
bit of the quotient
the
into
MQ35,
in.
and the low-order
Following
determine
for a 0,
left)
half of the dividend
DST14A,
what
action
to take
it is added.
because
the loop checks
The gate
the divisor
or DSTl5
or DSTl5
sets DSFS (I ower
of the loop
The first
bit
loaded
into MQ35
point.
divisor
the dividend.
magnitude
than
fraction
because
puted
to allow
before
shift
the delayed
the loop.
DSTl4B
operations
the last quotient
DST16 right
remainder
(C4).
so either
bit
shifts
should
the divisor
Either
30 times
enters
NT14
to the begin-
the sign bit to
the loop only
generate
if the
the sign and 35
requires
and an additional
if
for floating.
but rather
iterations
30 steps for the
quotient
in the loop
in the subroutine
and place
in MQ,
AR.
if DSF7
originally
negative,
all
remainder
them
the first
follows
DST14A.
When
upon
DST19
(A6)
bit
is com-
slightly
have
that
off one place
been
DST17A
then
jumps to DST19A
cal Is the AR negate
The setting
the return
c
6-44
Again
to the left.
(I ower
subroutine.
the signs of
Therefore
operands,
jumps directly
the
to DST17A
from the dividend,
this addition
checks
prevents
in the loop places
on positive
the sequence
in (84).
adjust
shift
too much has been subtracted
back
to prevent
performed
this pulse generates
jumps out to DST16.
remainder,
The final
subtraction
signal
and it instead
position.
the remainder
the MB sign.
der has the same sign as the dividend.
left)
the correct
If it is already,
indicates
of the SC completion
(upper
in correct
operations
is 0, the sequence
is delayed
and shift,
generate
but it leaves
Since
depending
dividend:
subtract
the assertion
DST17 or DST18 adds the divisor
right)
division,
upper
not at the end of the loop but in the middle.
but rather
SC to 777,
also be positive.
A negative
AR subroutine,
(lower
6-26,
goes back
Floating-point
The test for completion
from continuing
and remainder,
is made
and subtract,
and increments
The remaining
quotient
which
to
is subtracted;
the functions.
return
the sequence
may be one bit overflow
of the process
Thus each step is not shift
the final
and MB0 (Figure
part of the quotient
quotient.
in MQ35
a 1, the divisor
reverses
is shifted
running.
The test for termination
occurring
or integral
there
bit
The 36 fixed-point
bit
is 1, DST14 subtracts
for fixed
It must be 0 because
bits of the fractional
27-bit
36 times
is not actually
the left of the binary
if MQ35
the AR subroutine
iterates
quotient
has received
A 0 quotient
to gate
The loop
generated
OR of MQ35
sign.
adds it if negative.
(A7).
is larger
If the quotient
is the exclusive
left)
out from MQ as the quotient
the previously
may have either
positive,
ning
next.
is shifted
may call
either
the sign of the original
left);
but if the dividend
Thus at the end,
of the SBR for the return
from the previous
was
the remain-
from AR negate
subroutine
from getting
through
in
both
SBR.
the opposite
presently
direction.
in AR with
the quotient
net
ative
left.
for storage
FDTOB for floating
correct
refer
As an example
obtain
DST20
with
in MB.
the exclusive
the quotient
and
The reader
then
switches
and MQO,
subroutine
operates,
consider
and a divisor
sign for
returns
that
by
is already
to MQ
the
in correct
should
where
be negit is
to ET9 for fixed
the remainder
the remainder
in its present
(&p,
remainder
the result
case,
divisor
the proper
the result
note at this point
be stored
the
is generated
the remainder
but in the floating
return
and
the
which
The subroutine
cannot
of +. 100100
MB,
then determines
moves
should
instruction;
which
to
If the signs are different,
of the way this algorithm
a dividend
SC
MQ
signs are the same (A5),
accumulator.
to the normalize
c I ears
OR of DSF7
in a second
quotient
from
The sequence
DST2lA
division.
quotient
(A6)
AR negate.
for a 290bit
particulars,
fractions
Next
one for a fixed-point
is correct
the
jumps to DST2lA.
and DST21 calls
available
moves
If the operand
the sequence
and
then
the quotient
by checking
in the lower
form
DSTl9A
For
form.
division,
is the
in MQ9-35
further
6-46).
a division
of +. 101,
of 3-bit
By paper
fixed-point
computation,
we
this way:
,111
lOl)loo.loo
10 1
10 00
1 01
110
101
-i
Assuming
the computer
and
MB has 0.101.
MQ
= 1 .OOl .
registers
Before
The sequence
to be four bits
starting
in length,
the division,
MQ
must shift
has four steps as follows:
0.100
-0.101
1 1.001
1 +
1.111
1 .OOl
1.111
I 0.010
+o. 101
2+ 0.100
1 .ooo
-0.101
6-45
AR contains
0.010
0.101
left
0.100,
to close
MQ
has 0.100,
the hole,
giving
3 c
4
The quotient
is in MQ
floating-point
at the right,
instructions
cal I ing a subroutine
fraction
is l/2
malize
return
in Figure
Entry
operate
Return
on the fractional
9) is opposite
-l/2
in AR at the left.
Normalize
the result.
(bit
flow chart
1 ,011
0.111
parts of the operands
A floating-point
in state
to the sign bit
has the same magnitude
occupies
the right
half
number
of Figure
the normalize
add sequence
(upper
inputs
return
left).
chain
is immediate
The first
at the AR and MQ
pulse
from
in the chain,
extremities
FATlO,
is in positive
right
AR,
any overflow
that
shifts
MQ
to accommodate
putations.
Since
equivalent
to multiplying
the answer
the gating
level
the register
subroutine
.
shift
is equivalent
to dividing
by 2, the result
has already
been
as the AND
function
is a 0 result,
right,
form,
The nor-
chain
is shown
The next
produces
a 0 result
NRT. 1 jumps directly
pulse
clears
to NRT6,
which
is now in negative
form)
and enters
the normalizing
loop
sets NRF2 and after
at the 0 test.
MQl
a delay
it cannot
that
is unnecessary
allows
overflow.
6-46
is
generates
all of AR
part of
in the
SC
(SO
(As).
in the multiply
in SC to settle
for the 0 test in this case,
pulse
complements
The last pulse
the exponent
com-
tests for a 0 result.
the final
goes to NRTl,
because
and
the exponent
the exponent
the chain
6.3).
6.8~)
The test can include
result,
shift
(6.2~
of the figure
For a nonzero
skips the right
shift
enables
in the fractional
the net in the center
.
in the floating
see 6.7g,
by 2 and indexing
of AR = 0 and MQl(0)
that
arithmetic
may occurred
is unchanged.
shifted
on the fractions
If there
(84).
the exponent
chain
a right
any operation
FMTOB,
of the
sets NRF2 (CS),which
for a double-length
in SC (which
Multiply
as +1/2).
the last pulse
NRTOS,
adds one to the exponent
because
normalized
or if the magnitude
1, and the time
NRTO then
Since
is considered
representation
4-l
end by
6-27.
into
the shift
that
(the fraction
0.001
0.011
0.001
the remainder
to normalize
if the MSB of the fraction
0.101
1 .OOl
+
-
-d
All
0.011
0.110
-0.101
sequence,
(C3) enters
but its inclusion
merely
the
allows
attainment
result
would
otherwise
for a possible
rounding
of a significant
the divide
vanish.
overflow
(5 above).
bit,
pulse
the regular
there
because
the pulse
occurs
slightly
the total
return.
down.
in the zero test because
sequence
triggers
FDTl
Even though
MQ2
contains
there
an extra
to allow
by the return
from
extra
enters
FE back
right
shift
at the beginning
are two shifts,
only
from
to SC.
of AR,MQ;
of the chain
and NRTO is ample
quotient
the
one to compensate
generated
exponent
Divide
for which
bit generated
the required
between
shifts,
quotient
the calculated
delay
operands
must be two right
of the extra
then
in normalize
to settle
unnormalized
in the divide
FDTl,
so that
shift-count
included
certain
sets NRF2 and transfers
right .shift
preliminary
the other
in the sequence,
but is delayed
with
For divide,
FDTOB,
subroutine,
The final
result
to allow
MQl
bit generated
the
need be
only
for
rounding.
In the normalizing
(the gating
AR,
levels
6.2),
NRTl
decreasing
a delay
until
whose
either
that
NRT3
triggers
output
NRT2.
retriggers
the normalizing
may have
complements
into
that
the round
is asserted
part of the fraction
subroutine,
exponent
so theassertion
positive
shift
NRT3 sets the overflow
counted
when
from
negative
the exponent
the result
.
l/2,
flag.
time
NRT2 goes
This does not necessarily
exponents-the
was calculated
if the result
The loop continues
at which
into positive
representation
in SC thus
NRT2 also enters
is not yet normalized.
has magnitude
nets for
exponent
of AR,MQ
l/2
before
multiplication
of the exponent,
is also negative.
overflow
or
it is already
However,
in
if AR0 is 0,
SC.
the subroutine
but the gate
or the fraction
occurred
left
if the number
the loop uses the negative
form for insertion
generates
by the net in C2 and the decoding
an arithmetic
NRT2
loop
is not of magnitude
This pulse adds one to the negative
and triggers
At this point,
order
respectively
If SC is now positive,
Since
proper
are generated
AR9 and AR0 differ
or underflow
division.
if AR9 and AR0 are the same and the fraction
its magnitude,
on to NRT3.
mean
loop,
again
which
cal Is the subroutine
which
returns
must determine
gate
only
is in C3 and C4.
if a rounding
is 1.
for the initial
that
right
any rounding
The program
action
The rounding
of NR ROUND
to the beginning
whether
first
specifies
is necessary,
sequence
causes
shift.
requires
i .e.,
Then
NRT3.1
The completion
of the subroutine
(C2).
is required.
rounding
the repetition
continues
triggers
Thus the entire
The net
by a 1 in IR6,
if the MSB of the low-
NRT3 to complement
adds one to AR.
6-47
action
of the entire
SC,
making
the chain
NRTSA
routine
the
to NRTS,
(lower
is repeated
right)
in
case the rounding
also sets NRF3
(03)
automatically
form.
to NRT4,
then
both
negative,
is a l’s complement
and places
than
of a positive
the magnitude
of a negative
a 0 can be null
the low-order
half
caution
bits and leaves
part
MQ
still
contains
part of the result,
extra
quotient
in correct
going
Adding
order
NRT3.1,
it
is required.
and in proper
floating-
the round
is null
part
of the
on a 1 in MQl
is that
form.
The answer,
and a l’s complement
of a 1 in MQl
The program
if
is one
increases
but decreases
MSB is not significant.
low-order
of
the magnitude
MSB is significant,
if the entire
is < 1/2LSB
part
should
Of course,
is null,
always
in which
round
unless
to be used.
division.
in MQ9-35.
and MQl
l-35
two quotient
bits and append
then
one because
a 2’s complement.
concerning
the program
reaches
NRTSA
to ET10 to store the result.
2’s complement
part
ones).
pass if no rounding
is >1/2LSB
the low-order
bits are lost in the shifts.
order
the given
is already
part
but only
again
from O- if the bottom
away
the lower
when
number,
the remainder
remainder
when
result
is necessary
true sign of the remainder,
ization,
result
is actually
returns
the low-order
was all
is now complete
for conditioning
the result
unless
in a negative
case the high-order
i.e.,
a 2’s complement.
the magnitude
icant
NRT6 which
The reason
the chain
it goes on the first
but if the bottom
by 1 LSB .
the action
in magnitude
if the fraction
from SC to AR so the result
it is ignored,
rounds
only
Then when
net.
used here is in magnitude,
is increased
A further
can occur
to which
This pulse also triggers
the top part
greater
(which
the round
the exponent
The rounding
top part
disabling
continues
NRT4 transfers
point
has overflowed
The divide
Following
contain
the two right
a truncated
If there
bits,
them at the left
only
reconstruct
the true
6-48
order
In order
two
the
least signif-
after
normal-
to use the low-
remainder
quotient
29 quotient
MQO contains
in the division
one.
end of a lower
remainder.
shifts,
computes
remainder-the
was overflow
otherwise
must either
subroutine
or save the
calculated
from
CHAPTER
7
MEMORY
In a PDP-6
system,
arithmetic
the core memories
processor
a fast flip-flop
operation
by a memory
memory
to processor
requests
at the processor
memory,
provide
pulse
appropriate
places
cessor,
by the
the time
of memory.
required
address
a core memory,
acknowledges
and continues
In addition
with
included
no buffer,
the clear
registers.
in the description
system
any one of 262,144
register.
The actual
appears
locations
address
much shorter
must wait
time
until
by triggering
control
from the memory
depends
the type
upon
the memory
less time
than
cycle.
a write.
is available
need wait
stores
of data.
to the pro-
the data
the memory
to
and available
than
slightly
access
Memory
data
the processor
access
the protection
address
MEMORY
to a processor
merely
only
the
only
the data
and the
until
the
in its own buffer
cycle.
of the memory
7.1
The memory
is usually
for controlling
These govern
is free
respond
only
request
for a response
or receive
at which
and write
logic
the memory
and
The internal
and receipt
of the processor.
must wait
for writing
that
to memory
to transmit
the processor
the request,
elements
access
bank,
describes
the transmission
soa read requires
automatically;
to the standard
the user mode
section
Once
this time
For reading
the word
bits.
by the processor
contains
memory
the logic
to the
and the way they
This chapter
may request
control
an 8K or l6K
timing,
manual.
bus:
connected
in any core bank.
their
and control
or a subroutine
The fast memory
rewrites
in a separate
units
may contain
functions,
addresses,
For a core memory,
memxy
control
are separate
16 locations
on the bus and the processor
high-order
from
the bottom
in the memory
signal
A core memory
end of the memory
cycle
operations
addressed
their
the necessary
in a main
a request
bus.
are described
hardware
A time
and fast memories
may replace
of these memories,
LOGIC
to memory,
this chapter
and relocation
of areas
and are
LOGIC
as one homogeneous
an 18-bit
unit:
the processor
address from
put on the bus is the sum of C(MA)
7-l
in core
logic.
ADDRESS
by providing
also describes
may address
the memory
and C(RLR).
address
The bus control
portion
of each
memory
contains
in,
memory
four
a 16K or 8K bank),
If the bottom
nal is required;
decodes
of a core bank
this signal
or five
and a given
is replaced
is generated
7-l
shows
must always
counter,
index
the
be preceded
or the console
registers,
The transfer
to MA35
gates
by a clear,
address
that
and fifth
processor
is fetching
operations
a double-length
the second
bits from
result.
is in the normal
To address
bus with
MA;
those for the relocated
bits,
which
select
bank
the operator
locations
over
selection
sig-
of addresses
into MA,
which
the program
so that
accumulator;
cannot
situations
that
between
go into MA31
occur
location
input
however,
if the
for double-length
use a double-length
addresses
(b below).
at the MA+1
is broken,
such actions
that
circuits
a pulse
chain
out of MA32
of accumulators,
set bit 30 and bits 32-35.
in the MA control
The carry
instructions
buffer,
of short addresses
configuration
In all other
a single
memory
negative.
the relocation
bits,
bank,
Bits 26-35
register
RLR.
RLA,
are with
a memory,
must be supplied
bus drivers
and all
the bus in both
and to select
to select
addresses
i.e.
control
forms;
a location
between
are interleaved;
an 8K bank,
wired
an additional
may directly
are included
such an instruction
ones asserted
the sum with
memory
arithmetic
within
from
are supplied
to the address
operand
or produce
17 as an accumulator,
increment
MA,
the second
bits 21-35
are supplied
address
order.
a location
shows the required
pulses
A carry
a second
0.
only
the memory
For the transfer
of the register.
When
Transfers
may be made from
the right.
AC is in location
register.
in a carry
or storing
and certain
address
the pulses
adds 1 to the contents
responds
a given
MA Register
individual
produce
memory
upon whether
by the processor.
switches.
are connected
the fourth
memory
memory
and PI channels,
The MA flip-flops
shift
18-bit
bits (depending
by a fast memory,
-a
Figure
address
that
within
address
are supplied
Bus drivers
connections
are supplied
a bank.
A switch
, al I odd addresses
because
7-2
both
at each
above
bus.
all
bits are required
relocated
Figure
16K memory
bit 21,
even
7-2
Bits 21 and 35
as bits to select
If bit 35 replaces
are in one bank,
five
bits are shown
assertion.
to the memory
is, they
21-25
The high-order
states at ground
the bits for the two uses.
must be interleaved
7-5.
the
bits
by MA,
for the direct
RLR in Figure
in both
directly
over
allows
the memory
in another.
to select
a
With
the bank.
At the upper left in Figure 7-2 are the bus connections
processor.
At the right
means that
the address
selection
signals
(fast memory
is a net that
for the bus since
addresses
flip-flop.
This mode allows
readin
output
Additional
is also
the operator
is used by readin
mode
control
to a flip-flop
compares
the MA
gates
a level
when
and three
bit with
in Figure
7-l).
The outputs
in MA
indicator
transfer
decoding.
of the readin
in the area of core that
when
which
in core
extra
to the program.
to determine
mode
is
The ungated
the program
logic
7-3
requires
shows the circuits
a pair
second
of pulses:
triggers
the transfer
Figure
pulses,
leaves
the
in figure
address
the transfer
triggers
usually
logic
number
load accumulator
The address
fer in from
and IT1,
transfers
loads
from
net that
are shown
7-2,
in the switches.
PA through
left)
below
the
to assert
This signal
register
switches.
the gates
Every
is used
transfer
left;
TWOof
addresses
into
from
At the beginning
the instruction,
7-3
MA32-35
the key logic
of every
unless
that signal
40 + 2n.
from
clears
instruction
the processor
is
transfer
A UUO
address
The other
and
sets of
the appropriate
cycle,
PAS
loads
sets MA30
MA prior
the
the register.
The other
right.
of a PI channel
the address
with
because
gates.
in the lower
producing
A signal
it to retrieve
MA.
the net in the upper
switches
to the register
The transfer
into MA32034,
into
to the gates shown
the address
directly
MA 30.
are as follows:
PC into
(Figure
a logic
one of the PAS at the top of the figure.
MA bits through
and index
the address
(these
of addresses
the clear
through
and applied
MA by setting
loads the channel
to the address
contains
MA Control
control
the first
7-3 set individual
40 into
address switch
those for MBRT and PC are applied
by the key
MA module
(7.2).
7-3 shows no pulse for the transfer
generated
console
is identical
that
the transfer,
each
of these nets are ANDed
-b
Figure
gates,
the corresponding
the address
by the memory
gates
require
by the 0 state
inaccessible
of the
the fast memory
16 locations
fast memories
to start a program
section
a condition
generates
the bottom
conditioned
and is ordinarily
for all zeros,
output
replaces
control
area.
In addition
input
a fast memory
the fast memory
by the fast memory
18-31
The decoder
are not relocated).
that selects
decoder
MA bits
in MA is 17 or less.
The signal
replaced
decodes
for the memory
IR bits.
to any transIT0 clears
MA
is in a PI cycle,
in
which
case IT1 loads the PI channel
cycle.
If the instruction
and AT3 clears
to AT0 after
the new address
and FTlA
subsequently
address
MA transfers
in the execute
clear
subsequently
is left
deposit
at FT4A.
two make
location
Finally,
For UUO,
code
This special
so that
in the pushdown
in location
transfer
the third
in the execute
store
cycle
into MA
instructions,
this instruction
list
in preparation
instructions,
(ET9,
wil I deposit
uses it to display
will
in the pushdown
cycle
POPJ,
subroutine
two
Three
C(E) and
UUO,
for POPJ because
moves C(E) to a new location.
the following
list;
the UUO
BLT loads a new address
it late
FT3 transfers
instructions.
of the top location
the pro-
MBRT to fetch
For the other
is required
by the contents
via MA).
transfers
returns
an accumu-
of the accumulator;
so that
40.
IR 14- 17
is complete,
into MA to fetch
for particular
ET3 sets MA30
in from
in MBRT and the cycle
IR9-12
half
for the address
the address
calculation
FT5 again
only
c I ear MA and load
the transfer
by either
are required
subsequently
and JRST,
transfers
cycle
specified
which
FTl
ends.
to PC must be made
the subroutine
the address
in MA as the cycle
the instruction
jumps to the location
PUSHJ,
if addressed
MA at ETl.
MBRT goes to MA at ET3.
(transfers
clears
follows
the effective
and BLT all
in which
in preparation
AT5 transfers
When
cycle,
MA
AT2 transfers
register,
is indirect,
is retrieved.
to the fetch
in MBRT and the clear
an index
If the address
it again.
cessor continues
lator
specifies
AT0 clears
address.
ETlO).
for
PUSH,
The first
C(E) or PC in the top
the current
instruction
location
in
case the JRST is a halt.
At the beginning
in MA.
of the store
If storage
cycle,
the appropriate
of an accumulator
address
is also required,
for the deposit
ST3 clears
of C(E) is already
MA and ST5 loads
it from
IR9-12.
In the upper
is triggered
by UUO
only
right
of Figure
by a signal
Tl to switch
for the deposit
ing by FTlA
to fetch
a block
that
IOT
ing the second
ferred
into
7-3
from
from
of MQ
the key logic
location
instruction
AC,
the address
examine
and by ST6 which
accumulator.
in the pair
Note
that
for a Pl channel
Since
the channel
sets MA35.
7-4
next
pulse
of the pointer
this latter
event
and that
address
contained
is generated
The two gated
and by IT1 if the indexing
the PI system.
MA at the same time.
increments
for the operations
40 to 41,
in a second
a second
is using
is a net that
occurs
the channel
always
in MA.
and deposit
The PA
next,
by the store
inputs
allow
cycle
count-
has overflowed
only
when
address
ends in 0, MA+1
perform-
is transmerely
in
c
Figures
7-4 and 7-5
user mode.
eight
show the two registers
The bits in both
bits in a memory
the processor,
selection
register
The executive
routine
bits,
this discussion
registers
anything
i.e.,
words;
setting
the first
different
any address
in which
to the actual
Every
time
a user program
chain
of majority
a 0 from
output
diagram
gates
is a subtraction
comparison
is 2, OK
(upper
right),
is 1 and the PR bit
is 0 or if there
when
as a multiple
is a borrow
< C(PR)
memory
reloads
MA,
18-25
of the address
7-4.
Each gate
bits
PR bit and a carry
is asserted
whenever
left).
of MA from
the
access
input
at least
The carry
conditions
stages,
from the previous
is made
and each address
with
a 1 signal
gate
PR by the
from an MA
are asserted
to indicate
and there
is a borrow
out only
the output
is asserted
whenever
7-5
x 2000.
in the chain.
At the beginning
MA
must
The
(a block
is real I y a borrow-the
are labeled
stage and either
to MAI&25.
are compared
here
are fulfilled.
defines
+ C(RLR)
two of the inputs
2000
of
is C(MA)
receives
mentioned
from 0 to
a block
RLR is added
the previous
PR and the outputs
in is disabled
At all other
in from
the two
in RLR, however,
since
in
of MA may have
2000 + 1777,
x
numbers
C( PR) and
any address
The number
of 2000
(all
with
PR represents
to which
the borrow
is 0.
words.
if C(MA)
is in the lower
comparison
chain
of 4000
the remainder
A clear
user
eight
the same multiple;
MA may contain
is clear.
2000
is compared
address
the corresponding
of the gate
MA18-25
at the top of Figure
of the gate
Since
to a given
to the most significant
do not represent
to PR.
by the CPA
10818-25.
assigned
of octal
in MA
for
loads the protection
RLR from
correspond
An address
by a DATA0
the gating
The DATA0
multiples
if PR is clear,
is legal
EX because
register
for the
to the most significant
the registers
of the block
are actually
block
into
logic.
registers
contents
and relocation
to correspond
the prefix
mode
both
a block
in the assigned
be relocated
18-25
the relocation
functions.
to all ones,
in a user program
carry
Since
but identical
An address
bit,
bus,
represent
PR25 represents
protection
the size and location
al I zeros
address
have
the executive
if MA is less than or equal
from
1777,
they
are octal),
only
with
provide
is transferred
and set inputs
PR and RLR.
have entirely
it is legal
Information
determines
the numbers
that
Registers
are numbered
0 to 7 of the I/O
by loading
address
address.
is included
PR from’bits
program
registers
but the clear
level
User Mode
that
a
of the
if the MA bit
MA is 1 and PR
is 1 or PR is 0.
NO actual
difference
is produced
transitions
across the chain
indicates
that
MA
same polarity,
right
AND
these
two
At the same time
against
to the assigned
to MA18-25.
inputs:
a bit of MA,
work
ORed
an odd number
to generate
an enable
if no relocation
enable
level
are disabled
of the inputs
level
is desired,
is applied
(upper
the RLA outputs
The circuit,
negation
a settling
7.2
Transmission
and receipt
pulse
ampl if iers,
cycle,
the input
over
the bus,
each with
AND
memory
PAS that
correspond
generates
a level
gated
through
of data
uses exclusive
the carry
gates
control
required
for level
are enabled
to ones in MB.
that enables
state,
DATA
pulse
To receive
AND
MB bits (6.1).
7-6
the other
a carry
to the
a 1 output
division
net-
The RLR input
mode
control)
are no carries.
to the first
adder
transitions
is
so that
This
in the chain
the sum of MA and RLR appears
at
across the chain.
LOGIC
and output
to al I input
information
gates;
less
are ones.
pulses
from
bus are controlled
(Figure
by the 1 states of MB bits.
a transfer
all output
to set the appropriate
input
has
the next
uses a voltage
end of the memory
at both
left,
from
executive
inputs
because
of dc adders
at the lower
to MA and there
The carry
MEMORY
applies
diagram
circuit
MA changes
gates
(7.8)
to MA to
OR nets to generate
from
is equivalent
at the processor
AND
in block
of the inhibit
interval
at the
control
of 2000
out by a chain
one a bit of the sum,
to pin H of all adders.
Each time
sent to memory
of RLR are added
two or more of the inputs
the sum output
right).
after
(the
asserted
The nets in the lower
bit of RLR, and the carry
are ones;
whenever
when
starts at a multiple
is carried
shown
The sum circuit
a 1 output
block
The addition
the corresponding
stage.
address.
PR, the contents
It has two sets of outputs,
more significant
with
7-5.
for level
out at the left end
the last gate,
the signals
taken
protected.
Every
block.
is the time
A borrow
a legal
REL so that
is compared
three
whenever
EX INH
MA
RLR in Figure
next
with%
is being
above
state.
or not MA contains
the memory
shown
adder.
changes
when
RLR is added
significant
MA
for the comparison
PR; and the two outputsof
whether
that
the address
the 8-bit
than
levels
only
required
each time
is larger
indicate
can be asserted
relocate
and the time
7-6).
To transmit
For a write
data
gates
and triggers
a read,
memory
that arrive
by 86
pulses
those
control
over the bus are then
Figure
7-7 shows 36 MI flip-flops
of a memory
location.
MB connections
memory
restart
the memory
the condition
of a write
have
operator
examines
examine
and deposit,
which
are included
request
clears
or deposits
(flow
gate
Figure
and read/write
consider
4-3).
-the
appropriate
type
for the access
is written
the specific
general
request
struction
that
inputs
pointer
condition
that
that
suffices
the
for
next and deposit
next,
CONTROL
governs
requests
may request
available
only
for memory
three
access
types of memory
for operations
cycle
pulse
through
with
generate
is supplied
pulses
7-9.
RD,
that
supply
the gates,
required;
in normal
by the processor
action:
mode,
pulse.
that
read,
which
restart
or a block
IOT
to an earlier
for
by the subroutine;
include
the store
the request
levels
A read request
sets MC
and the read/write
any specific
a read
write,
we shall
store
it is supplied
a
For any in-
but there
(86).
sequence.
that
also triggers
MB (B5).
by a subroutine
in the main
whereas,
request
The reason
an output
request,
the subsequent
for the
7-8.
generates
clears
the read/write
is performed
point
subroutine
Each gate
requires
FT7 triggers
the
the memory
at the top in Figure
however,
type
and pause,
directly
trigger
the triggering
and either
operations
instructions
MC
access
fetch
and returns
of Figure
and clears
(A!$,
requires
the restart
and a few subroutines
along
to the net that
The request
left
that
type of access
in character
and-pause
cycles
of memory
triggers
cases,
the word
of any location
for examine
includes
first .
the main
store
or write
restart
MI displays
address
and the
the address for a
The write
the contents
is necessary
MEMORY
The processor
last being
Pulses from
three
it.
so that
The equal
modules,
the transfer.
7-8 and 7-9 show the logic
chart,
also display
but an additional
7.3
Figures
memory
register
the contents
the read restart
and loads MB into
into.
to display
Whenever
address switches,
for a nonexistent
information
use MC RSTl to trigger
to the modules.
Ml
The indicators
indicators
on the arithmetic
in the console
subroutine
been written.
a set of console
gates are internal
is the same as that
from
would
drive
The flip-flops
to the input
access
that
are
Indexing
which
of a
skips the
In these special
by ST2 for all fetch-
cycle.
to the bus by setting
RD and clears
request
sets both.
7-7
MC
up the flip-flops
WR, a write
A request
in the upper
request
for any type
sets MC
of cycle
WR
clears
MC
STOP and sets MC
to the latter
the system
MC
flip-flop;
instead
is in executive
RQ; however,
necessary
valid
address,
main
Tne bus levels
that
from
the outputs
from
MC
function
in a response
from
the bus into
STOPswitch
a cycl e and specify
request
memory
memory.)
MC
subroutine
7-8.
When
the addressed
memory
which
clears
acknowledges
MC
RQ.
to memory,
transfers
from
the memory
subroutine
the processor
In this case,
the return
is delayed.
MC
must wait
from
the cycle
of the current
on the channel
through
request
a possible
which
level
that
bus drivers
is generated
to prevent
request
would
gates
mal-
not result
data
pulses
STOP key or if the ADDRESS
the main
MC
and the processor
to the waiting
by the circuits
request
pulse
(delayed)
half
of Figure
This pulse
the acknowledging
MB onto
for the read restart
sequence
though
by pressing
KTl.
7-8
the restart
to trigger
pulse so that
the subroutine
RUN
ADDR
ACK,
also sends a write
memory
the read nor the write
stops even
MC
a pulse
pulse
restart
MC
For read or the read portion
from
a preliminary
RD and supplies
neither
pulse
(C6).
it returns
triggers
the bus, and triggers
sequence
triggers
in the lower
to the processor,
of an address.
memory
the MC restart,
RS TOat
that
address,
available
to the waiting
the subroutine,
MC
a
the PR maximum
interrupt
are derived
the bus enable
is controlled
access,
data from
RS Tl clears
the return
a priority
a memory
the selected
receipt
been set during
trigger
than
out the
has supplied
to skip the remainder
has pressed the MEMORY
becomes
For write
back
read/write,
to carry
(D4).
of the memory
that
is allowed
This is done
generating
lf the operator
etion
left)
(Note
RD also supplies
Comp
(lower
from
and MA now contains
sets t) e stop flip-flop
If
the PA in C7 to set
is greater
read or write
is also specified.
control
MB (7.2).
ison
directly
of the figure.
if the user program
and triggers
flip-flops.
if a read or write
from
Then
the processor
right
triggers
delay
is set; but if the address
(C6) causes
is not applied
in the lower
delay
(7. ld.
pulse
(8.3).
of the three
in processor
lines
a longer
direct1 y to ST7 (5.2~)
request
RQ only
request
of the right
operations
address pulse
to the processor
the two delay
is in user mode,
flip-flop
by jumping
the general
the output
and relocation
the illegal
assigned
mode,
the request
sequence
although
it enters
if the system
protection
address,
RQ,
restart
is not clear.
the MEMORY
from
of
.
the MC restart.
the subroutine
return.
RSTl
return
If MC
STOP has
memory
can trigger
The operator
CONTINUE
key,
may then
which
triggers
For a read/write
cycle:
MC
of which
ADDR
clears
7-8,
restarts
the memory
transfers
lower
data
The other
Thus the processor,
shown
every
request
pulses
keep
in the two memory
7-9
pulse.
arriving
for 100 psec,
is an integrating
address
For write,
normal
MC
shorter
than
returns
pulse
completion
pulses
a read
pulses,
signal
alone
duplicates
the write
restart
to the memory,
both
at the same time
to memory
(the pulse
that
is inhibited
interface
If the console
clears
MC
RQ by simulating
MC
ADDR
for any other
cycle
ACK
(MC
that
if there
within
in the
it
1 state
there
by
be no request
set at this time
the 4303
state
is a memory
a priority
indicating
change
stop).
interrupt
lOOpsec,
triggers
This pulse sets
on the assump-
there isnomemory
DISABLE switch
is off,
pulse
with
the error pulse
acknowledgement
the subroutine
an additional
In the
as long as triggering
But should
the address
also triggers
situations.
is placed
granted,
MEMORY
RD(l)),
special
RQ is still
to trigger
to the bus.
which
period.
has not been
does not respond
the simulated
manner;
I/O
handle
in the 1 state
the delay
memory
from
completion
pulse
is generated
to
memory.
in the
the
supply
restart.
logic
compensate
is associated
for memory
has pressed the MEMORY
the equal
need
has access
and if MC
to the Ostate,
for access
connected
The remaining
that
already
Type 4303
at intervals
in the processor
a restart
delay
continuously
if the addressed
generates
as for
by the processor
by triggering
drawings
remains
the nonexistent-memory
f lip-flop
control
The delay
the delay
the last request
that
request
cycle
which
its own subroutine
supplied
same
the completion
the write
pulse
in a write
is the
generates
part,
restart
part
over the bus from MB.
left of Figure
that
in the first
For the second
The read/write
and provides
circuits
tion
RD.
acknowledgement
left).
lower
an error
MC
bus.
of the address
(Figure
by the memory
c I ears MC RQ and the read restart
on the memory
the action
that
the response
ACK
RS Tl
MC
remains
cycle,
address
requests
prevents
flip-flops
the two parts of a read/write
AT4 sets the split/cycle
in the main
sequence
a fetch-and-pause
of the sync f I ip-f lop prevents
the read/write
of synchronizing
STOP key or the ADDRESS STOPswitch
are for read only:
The 1 state
a pair
stops between
condition),
to set it earlier
with
restart
pulse
from
because
all
request
FT7 from
triggering
7-9
(Figure
7-9,
cycle.
If the operator
ison (which
would
synchronizing
flip-flop.
instruction
and address
can be made
triggering
the write
only
the read/write
restart
right)
al low a stop on
There
is no
memory
in the fetch
request
for memory.
cycle.
pulse
Instead,
and
separate
left
read and write
center)
switch
to prevent
input
purposes.
request
restart
the processor
restart
to memory
are triggered
the processor
to the sync flip-flop
for maintenance
the read/write
requests
from memory
set gate
so that
that
some operation
it may finish
in the event
allows
In case the processor
pulse sets another
with
by FT7 and the read/write
flip-flop,
other
it stops.
the operator
might
stop while
its cycle,
location.
7-10
memory
writing
There
hanging
(Figure
the split
onto
the same word
KTT triggers
back
cycle
memory,
If the operator
continue,
7-8,
is an extra
to override
the stop sync.
than
restart
should
the write
into the addressed
CHAPTER
8
INPUT/OUTPUT
The PDP-6
input-output
arithmetic
bus,
processor.
the priority
structions
ment,
system
The processor
interrupt
to control
this chapter
photoelectric
reader.
control
units
system,
the processor
describes
paper
Other
includes
tape
tion
8-l
8-2.
and the bus drivers
control
unit
each
bit
in lR3-9.
for a particular
that
appears
The cable
drivers
which
device
transfer
reset.
signal
required
As an example,
the IOT
processor
in-out
inequip-
devices:
and card
the associated
The 36 cable
lines
input
input
to IOT
to the drivers;
made
available
other
than
consider
i .e.,
governs
through
the drivers
the driver
levels
The transfer
and reset
sequence,
when
they
handle
at input
levels
Every
lines,
device
one from
the selection
the appropriate
signal
code
number
from
input
IOT
left
resistors
control
for 2.5
gating,
followed
in the upper
E (the
both
bus by an input
to the AR input
sent to the device,
transmission
the bus by supplying
on the external
L goes negative
8-l
lines
of the instruction
5-7.
14 IOS
from AR onto
for bit 0 shown
AR f I ip-f lop modules).
bits 3-9
determines
only
output
placed
level
In an output
connections
any signal
command
for the bus data
Figure
7 of the
of informa-
word.
bus are transceivers,
control
drivers
come from
from
commands
of an instruction
IOT
and times the transfer
on the IR drawing,
receives
by a negative
to L and M.
to the above
IOT
CONTROL
selection
1 in AR0 is represented
tively,
that allows
by connecting
instructions
bus.
of these
responds
for the I/O
is automatically
of the
the I/O
keyboard-printer,
merely
TRANSFER
are shown
code portion
and reset levels
sections
including
for the processor
Teletype
to the system
device
net which
into and out of the computer.
transfer
control
In addition
punch,
via the I/O
The configuration
in the device
transfer
for four of the more common
tape
decodes
for them
a diode
device,
units
I N-OUT
The I/O
register
contains
as a device.
and three
bus.
into and out of the computer
in Figure
interface
may be added
shows the logic
are shown
and an I/O
paper
8.1
Figure
are in-out
itself
reader,
equipment
elements
the control
equipment
to the I/O
the peripheral
no
by the driver
of Figure
are mounted
are connected,
psec,
with
transferring
8-2.
A
on the
respecthe
input
at E to outputs
second
is ground.
external
F, and H:
J merely
in the various
for use in l/O
control
signal
brings
discharges
inpyt
status registers
the control
is connected
for 2.5
net shown
tion.
The IOT
chain
starts
pointer
word
control
develop
time chain
back
into
always
MA,
and triggers
depending
whether
the block
is complete.
O-to-l
still
transition
within
the second
pulse
from the initial
terminating
pulse
upon
following
the fall
setup
is IOT
triggers
a previous
in the first
delay,
reset
IOT T2,
T3, and a final
the block
level
setup delay
With
at H, which
is applied
to the
If two
itself
a pair
whose
instruction,
cycle
to write
into
the PI system
IOTs occur
terminating
data
skip and
and
GO.
The
the system
is not
too close
the delay.
of delays:
the indexed
its associated
out the required
provided
the
generates
ET4 sets IOT
triggers
the
one instruc-
is using
delay
in
to more than
subroutine
a block,
shown
The four
instruction
transfer
setup
IOT.
to the
instruction.
For a block
It also carries
within
triggers
8-2
common
from the memory
the initial
control/
for the IOT class,
part of a read/write
instruction
level
by the logic
the specific
left).
the block
be no con-
on the bus.
a negative
the code
functions
for the data.
whether
a data
of this flip-flop
until
cycle
will
no dc load)
assertion
are generated
at ET4 (upper
This action
reset to the bus drivers.
to determine
Th e return
the reset
of the device
status or data
IRO-3 contains
the second
(7.3).
including
the reset period
waits
begins
the fetch
operations
ones at ground
for incoming
control
polarities
and in the I/O
there
gates with
at F produces
sets lR12 to convert
overflow
IOT,
IRlO-12
that
diode
by the 2-psec
When
restarts
memory
clears
In any nonblock
places
and output
to ground,
that
the
assertion
system
returns
the outputs
(through
a ground
4-13).
at both
interrupt
level
registers
on the bus (F) for 2 psec.
since
the bus and devices
levels
bus signals
the
F drives
panel.
to the bus to ensure
The gate
left decodes
at IOT TO, which
IOT TOA which
instruction,
gating.
Figure
at the lower
OR gates at the right
merely
is negative;
of the control
the transfer
are connected
psec and is followed
8- 1 (fl ow chart,
Figure
that
and third
in-out
in the priority
connected
L and M off,
and pulses that
provide
For input,
device
to the AR input
control
The levels
buffers
at both
inputs
a hard negative
operation.
an addressed
signals
placing
gates
I/O
and input
same bus lines,
device
M to ground,
a subsequent
of the first
on the console
the computer-
At the same time
the capacitor-diode
with
an indicator
F and H together
within
of the processor.
level
to the capacitor-diode
devices.
operations
the assertion
drives
bus and is connected
buffers
flict
J,
a restart
pulse
together,
The terminating
delay
is IOT
whose
T3A.
The level
that
outputs
places
initial
information
to final
bus through
ister
of the initial
transition).
the I/O
cable
During
drivers;
to the bus in the device
the appropriate
device
selection
clear;
the restart
AR is cleared
T3.
the capacitor-diode
time
chain
initiation
of IOT
In addition
IOT
operations
to the timing
right).
Whenever
turning
on all peripheral
T3A triggers
logic,
computer
Figure
power
8-1 also shows a pair
is turned
equipment.
clear
and when
are included
in MR START,
see 5.1).
channels
arranged
to the processor
channel
controls
priority
request
effective
address
transfer.
struction
cur while
of every
that
allows
is not complete,
chain.
under
delay
enough
cycle
level
allows
the
ahead
of the
instructior
by
ET% When al I
at
output
The processor
prevents
40 + 2n where
Any
the
leaves
signals
to pin C of I/O
the device
can also generate
(upper
cable
control
(both
3,
units
conditions
this reset by means of a
in the processor
to be interrupted
control.
I/O interface.
Moreover,
cycle,
requests
by a signal
assigned
on any channel.
until
the program
The processor
and honors
made
after
by entering
n is the channel
If the break
the PI cycle
8-3
instruction
and dismisses
immediately
for requests
the highest
has completed
instruction
except
and executing
No further
is a block
the break
and
may turn any
checks
the processor
a PI cycle
number.
on any one of
I/O devices
to the
the end of the current
a request
is in a PI cycle.
the processor
control
the reset from the console
and address
must wait
honors
of general
is applied
The priorities
program
a break
instruction
calculation
the computer
T2 and T3
the bus is accomplished
at pin B clears
the flags
the program
has been made.
in location
or status reg-
PRIORITY INTERRUPT
in a priority
are completely
triggers
The program
that
on or off and may request
at the beginning
block
system
-15 volts
The reset signal
8.2
seven
on,
the operator
19 of the same CON0
interrupt
whose
AR to the
For any input
the execute
the reset delay
setup
the
for 2 psec and resets the bus.
on the power
The priority
to reenter
buffer
in the device
in from
during
IOT pulses
and set.
by ETO; the transfer
grounded
the data
The initial
clear
gate
connects
instructions,
gates
between
well
a 2.5psec
instruction
connects
For the two output
enough
to the IOT
are complete,
an output
and set pulses for the device.
allows
to produce
T2 keeps the gate
instruction
This pulse also causes the computer
transfers
1 in bit
an input
IR to enable
delay
IOT
are ORed
this period,
control.
clear
from
prior
setup delays
on the bus (the pulse
setup
trigger
IOT
and final
interruptions
IOT
the
in a
the incan oc-
and the block
automatically.
If the break
instruction
in the break
pair,
the PI cycle
be a JSR to a break
priority
is not a block
or the processor
terminates
goes on to the second
at the end of the non-IOT
This routine
routine.
and the program
request,
IOT
may then
must dismiss
be interrupted
the channel
with
instruction
instruction,
which
at any time
must
by a higher
a JRST at the end of the
routine.
The processor
I/O
the program
register:
assignment
register
binary-to-octal
When
interface
device
assigns a priority
control
whose
requires
I ine corresponding
a column
ting
in the priority
of three
flip-flops,
of each fl ip-flop
sequence:
channel
are the logic
chain
PIOi,
represents
on,
gates through
Priority
PIRi,
made,
which
flops
by rows (for the generation
system,
Since
at the left.
the individual
the control
break
held.
gram selects
or clearing
this channel
P104.
of IOC3.
At specific
generating
PIR STB.
break
on it.
and setting
channels
a break
during
This signal
the associated
signals
by a 1 in CON0
times
The program,
chain
PI request
its
lines.
grounding
Each channel
i is the channel
process
Between
the
of level
control
state
its operations,
let us consider
4, a device
may bypass
PIR flip-flop
directly
8-4
flip-flops
IOB
(1)).
the
by the
in the flip-
control
channel
4.
over the
of CONO.
The pro-
on or off by setting
the PI4 line,
the request
is on and a device
the PI0
(PIR -
strobes
between
(lOB29-35)
must ground
the processor
sets PIR4 if the channel
however,
changes
by ones in bits 29-35
in the
and PIR flip-flops
is activated
For program
by
The set-
channel
or the program;
bit 32 and turns the channel
on channel
number.
for a given
gates which
see ,b below).
is identical,
is controlled
the rows of PI0
by a device
at the left
1 to 7 are selected
for all
To request
into
are appl ied to a gated
on the decoder,
8-3.
where
are requested
of these pulses,
channels
sequence
other
in Figure
in the interruption
breaks
All
PI ACTIVE
number
to the seven
by gating
and PIHi,
PIR and PIH rows is the priority-determining
input
a channel
PI assignment
Chain
are shown
a stage
request
a break
a 3-bit
in the register.
a
The 21 flip-flops
contain
of the register
1 to 7 are connected
it requests
to the number
each
by loading
The outputs
outputs
service,
units
to a device
(Omeans no selection).
decoder
a device
and all
pin V
lines by
has requested
by selecting
a channel
a
’
Several
PIR flip-flops
priority
request
may be set simultaneously,
(i .e.,
the PI REQ outputs
by the chain
enables
the highest
interrupt
If the request
2NllR.
AND
gate
disabling
PIH
disabling
both
0 state,
have
the current
break.
held.
which
clears
is 1.
returning
The enabling
Thus,
a lower
priority
levels
priority
always
break,
would
have
caused
dismisses
the current
break
or if there
is none,
b
Figure
8-4
and which
break.
shows the circuits
governs
When
through
the sequence
an IOT
with
program,
gates
device
which
of operations
code
input
input
2NllS,
is in progress.
PI control
priority
generates
a break
PIH(0) c
up to and including
that
because
of the break
priority
being
the first
require
to be satisfied
is of highest
channel
is currently
in the stages to the left
to the main
AND
it also holds PIR4 in the
the break
an interruption
the
PI control
negates
on a higher
is bound
at
gate
S of the lower
has been started,
on which
which
manner:
of PIR4 satisfies
of this flip-flop
from the left,
for the clear
and so on to each
AND
while
nor
and an
PIH4 is 0, satisfying
so a request
be 0, but this condition
PIR flip-flop
the system
PIH flip-flops
2 is enabled
4 is enabled
Furthermore,
for the channel
requested
are all 0, stage
on the same channel
to the left,
is made
4 in the following
the break
The 1 state
to the interrupted
all
if stage
but negates
After
output
is neither
The 1 state
of the chain.
the PIH flip-flop
the PIH and PIR flip-flops
any higher
sets PIH4.
no effect
It does this by clearing
one that
both
when
channels
PI REQ4,
to the right.
request
however,
To dismiss a break
output
one of
The 1 state of PI ACTIVE
on channel
4,
the highest
of a request
If a break
and 2N13R.
and the remainder
any further
three
only
by asserting
2, stage 3 is enabled,
held on channel
at 2N12S
which
is set),
Similarly,
is honored
for the first
the request
at the left.
on channel
no break
+-PI CH RQ,
that
honors
The selection
the second.
a request
the rest of the chain
These actions,
PI OK(l),
nor held
a ground
asserting
preventing
can interrupt
of the chain
flip-flops
PI REQ4
PIR flip-flop
the PIR and PIH flip-flops.
stage enables
is currently
gate
generates
stage
requested
and producing
upper
between
priority
and hold
If there
lR,S
gates
For example,
stage.
numbered
at the top of the figure.
1, the first
is neither
successive
2Nl
shown
of level
held on channel
for the lowest
but the PI system
setting
in progress.
and returns
to
program.
PI Control
the program
controls
in the priority
004 appears
8-5
the priority
chain
in the program,
when
interrupt
a device
the AND
gate
system,
requests
in 86
a
enables
the selection
gates
PI ACTIVE
8-5,
upper
level
and the PI0
flip-flops
CON0
bit 23 gates
right).
ing PI RESET (84).
erates
other
CON0
This pulse
pulses which
triggers
the selected
The remaining
tion,
logic
level
cycles,
from
initial
Figures
pulses
in both
cycle.
The PIR strobe
quested
a break.
request
PI CYC
(C6).
encoded
are listed
and 4-5).
I ights
channel
When
and encode
triggers
located
Th e p rocessor
then
returns
retrieves
from
number
(A5) which
channels
line,
to the instruction
cycle,
the instruction
The
request
a device
by
has reoneandonly
PI RQ if any
a level
in a
and
is not in a PI
PI RQ allows
the processor
execu-
the inverted
for an interrupt
8-4 generate
(A3).
the instruction
the processor
into binary.
places
memory
bits 25 and 26 turn
theprioritychainasserts
left of Figure
three
of the figure).
over which
in
by bits 24-28.
the requesting,
(right
check
p rovided
and gen-
The other
a request
at 2L20
cycles
by generat-
set pulse
specified
with
grounds
in Figure
directly,
in the flow charts for
PIRflip-flopsareset,
IATO
control
system
on the selected
in any on channel
the channel
IOT
The following
operations
associated
PIR STB (B5),
PIR flip-flop
3).
a break
and address
t o g enerate
number,
the entire
bit 27 turns it off.
any device
an indicator
the instruction
sets the
from
by ones in bits 29-35:
bit 24 requests
The nets in the lower
is honored,
PI SYNC (5.22)
selected
(most events
Assoonasoneormore
PI REQ level.
(C7);
operations
PI SYNC (B3), which
generating
one
4-4
(Al,
the various
controls
PIR input gating
the
time
of a break
pulse to clear
PI ACTIVE
(A8);
8-4
level
bus (the bus gates are shown
PIH flip-flops
performs
on channels
in Figure
and dismissal
execute
SET, which
on and off
the status
PI ACTIVE, clears the PI0 flip-flops
the PIR and
operations
channels
the I/O
the clear
PI system by setting
bits perform
In CONI,
onto
clears
clear
PI CON0
Bit 28 turns on the
control
PI system.
for the
a delayed
PI cycle
by setting
and using the binarycontained
in location
40 + 2n
(see 7. lb).
Since
IOT
the most common
that
takes
of the pointer
to the data
erated
the place
instruction.
(upper
left) .
IOT
If the block
In the execute
dismiss
(PI OV(l)),
for an I/O
of a whole
word overflows,
ET1 immediately
complete
interrupt
it; then
th e b reak
device
subroutine,
TOA sets
is one that
let us consider
this type first.
both a hold
ET0 holds the break
ET10 ends the PI cycle
is not held,
executes
PI OV when the processor
is not complete,
cycle,
merely
and after
8-6
completing
block
If the indexing
switches
from
the block
and a restore
level
are gen-
by setting
by clearing
a single
PIH, only to have
PI CYC.
the data
If the block
instruction,
the
is
processor
tine).
performs
the instruction
The sequence
not been an IOT.
The routine
of events
The break
must then
in location
41 + 2n (which
is now the same as it would
is held
terminate
must be a JSR to the break
have
at ETO; ET10 dismisses
with
the appropriate
been
had the first
the PI cycle
restore
instruction
and clears
instruction
rou-
PI OV.
to dismiss
the break
(B2).
When
the program
cessing
of every
cessor instead
performs
word
to the instruction
greater
than
interrupted
those
If a request
block
cycle
the remainder
last used.
to finish
However,
system of flags
actions
data
may also be triggered
processor
IR3-9,
in the same manner
the diode
command
switches
logic,
to request
from
into AR (this
Figure
as any other
5-l);
IOT
controt.
transfer
from
the bus (7.12).
The condition
flops
shown
8-5
in the AR logic
(6.2e).
on the bus; CPA STATUS
tions
out so that
external
lines
chart
and the CON0
(Figure
4-13).
actions
In addition
been
control
section
to check
is primarily
instruction
selects
when
the device
generates
the level
CPA gates
gated
clear
bits associated
to the enable
8-7
flip-flops
and relocation
controt
bits;
in
the various
data
the key
registers
and overflow
flags
to information
bus lines are used for condi-
some fl ip-f lops are set only
them.
with
the
and sense the flip-
according
Extra
Certain
of the console
and the PC change
the bus.
gates
is shown with
protection
the flip-flops
individual
SET can only
CPA which
the contents
by CPA,
(5.5)
SET regulates
onto
code 000 appears
bus and the gate
a
its own status and per-
An IOT
8-5
is
honored.
the interface.
loads the memory
and status
have
cycle
system.
the flip-flops
and CPA CON0
addressesone
interrupt
the set pu Ise may set or clear
conditions
initial
the priority
plus the user mode flag
gates
and then
through
commands,
CPA CON0
(6.6a),
CONTROL
the processor
For DATAI,
DATA0
the pro-
the instruction
all requests
and its own IOT
does not use the I/O
a processor
in Figure
I/O
the pro-
is no IATO;
as a new BLT with
until
device:
in Figure
T4 during
it were finished
the block
breaks
through
there
is waiting,
allows
sequence
net at the left
signals
that
at BLT
a request
processor
flip-flops
mits processor
transfers
since
PROCESSOR
the arithmetic
and enable
as though
does not restart
8.3
between
is discovered,
the incomplete
and the processor
The interface
PIR STB is generated
transfer,
in the block.
terminates
returns
a block
A complete
by
list of the bus
them
is included
and flags,
CPA
in the IOT
includes
a PI
flow-
assignment
register
PIA which
decoder
to request
an interrupt
The first
two flip-flops
to use a protected
access
to memory
Either
drives
flip-flop
allow
flag
generator
the flag
the PC change
overflow
computer
a pulse
is on,
triggers
or overflow
that
pushdown,
flag
gates a switch
underflow
peripheral
between
device
causing
device
attached
to the processor
to both
control
I/O
control
transmission
The data
tion of the device
pair
A filament
it is set.
transformer
The other
to request
100 psec
of flip-flops
60 times per second.
provide
in the power
If the enable
two enable
an interrupt.
flip-flops
There
out of AR0 in a pushdown
AR CRYO(l)
at-
requests
within
Both types of instructions
unit
signals
connections
includes
is also an
or pullout
are represented
represents
overflow
by
for
to the processor
and which
includes
bus,
for both
lines.
with
via the in-out
the following
lines:
8-8
acts as an interface
control
buffer
(up to a maximum
The control
unit
whose
transfers
and a control
section
A control
unit
unit
for a high-speed
of data
to and from
section.
The data
buffer
of 36) and is connected
handles
receipt
and
and the device.
to its device
the appropriate
bus,
that
but an automatic
the processor
from a control
unit
processor.
bus for direct
a data
bus data
LOGIC
of the arithmetic
to the device
and are described
connected
section
to the memory
and the I/O
of control
and control
The next
must have a control
via the in-out
a number of bits appropriate
the device
flag
INTERFACE
to PDP-6
and the IOT
The basic
contains
set.
is a carry
a break.
the PIA
a user program
the processor
a response
time.
of MB and AR at ETlO.
may also be connected
memory.
when
time
gate
for pullout.
the device
is connected
every
whenever
to elicit
to real
if there
8.4
Every
fails
in AR control
list:
ET10 sets PDL OV
the level
operations
conditions
by the register.
one,
that sets the clock
for the pushdown
instruction,
the right
which
flag
the left one is set when
an interrupt
causes a break
Various
addressed
errors:
an address
flip-flop
a means of synchronizing
control
indicate
area of memory;
but specifies
error
from 10833-35.
on the PI line
at the left
tempts
(7.3).
is loaded
equipment.
configuration
depend
upon the organiza-
All
is shown
control
units
in Figure
are
7-10,
1 Power
On
Line
It is connected
power
to the
control
ment
when
1 Reset
for
the
line
is at -15
remote
each
device
ters and data
buffers
when
computer
power
tion,
Lines,
with
device
control
registers
input,
the status registers
circuit
places
priority
channels
14 In-Out
from the outputs
struction.
is connected
Lines,
to only
then
responds
output,
other
is
presses the I/O
may also generate
a reset.
data and control
the lines
informa-
connect
AR to the
capacitor-diode
are connected
gates;
for
to AR through
Type
or equiv-
requests
a ground
which
on the appropriate
on one of seven
I ine.
- These seven pairs of lines are derived
contains
the device
code
for both ones and zeros.
determines
those
an interrupt
in an IOT
A device
one from each pair.
the selection
IOT commands
that
incontrol
The configura-
code for the device,
are accompanied
which
by the ap-
code.
6 Command
a set:
the operator
all
regis-
The line
must be made by a 4657
seven of the lines,
of these connections
propriate
buffers
the control
to the bus.
through
(connection
is at ground
tion
to only
buffers
lOS3-9
of IR3-9,
Assertion
attached
- A device
by placing
Selection
equip-
no dc load on the bus).
PI l-7
Lines,
is on.
in the
peripheral
pulses to clear
For output,
and data
alent
switch
on all
the program
and data
Bus Drivers
7 PI Request
negative
at ground.
Diode-Gate
power
on.
goes on or when
4657
that
turns
- These lines transfer
ones asserted
computer
local/remote
normally
console;
IOBO-35
whenever
of the
of all equipment
reset key on the processor
36 Data
and
is turned
computer
volts
terminal
- This line supplies
Line
pulsed
- This
Lines - These lines provide
two negative
one pair
levels
for input.
loads conditions
loads the data
buffer.
two pairs
from
The two
of negative
E,oth pulse pairs
include
the bus into
the control
input
gate
the bus.
8-9
levels
pulses for
a clear
register,
and
the
status and data onto
Every
lap
control
unit
may
even
and
program
checking
are
and
flip-flops
Some
devices
have
additional
instructions
but
cannot,
registers
These
appropriate
punch
elements
register
flags
because
in-out
it
systems
as in the
kind.
tape
Every
the
busy
can
as full
whether
data
contains
the
be checked
same
is actually
two
such
as magnetic
reader,
and
has
control
a PIA
register,
flags,
word
b y a single
of
counts
status
a number
two
a command
bits
control
for
are
and
that
governs
or alphanumeric.
fl ip-f
lops
and
information
two
scale
are
the
in complexity,
and
The
in large
processor
error
same
not
associated
other
in
with
conditions.
on a larger
A maximum
necessary,
elements
by an
flip-flop
register
by a DATAO.
if more
basic
BUSY
Even
only
status
distinguished
busy
to the
have
bits;
are
output.
differ
be supplied
instruction;
other
of status
18 control
but
has
registers
it may
The
in binary
connections
status
but
must
the
control
and
and
Teletype
input,
the
tape,
a maximum
and
the
the
As an example,
control
tape
by
flip-flops,
units
by the
directly.
8-6.
control
I y over-
be governed
elements.
an additional
the
usually
be sensed
Figure
two
usual
I y be sensed
program
basic
control
from
whereas
devices-one
the
several
has
is to be read
bits;
and
in most
reader
can
reader,
PIA
names
same
tape
can
by the
the
register
tape
which
registers
usual
unit
be affected
include
can
control
signals
paper
these
fl ip-flops
the
status
the
same
i .e.,
provide
addresses
the
The
flip-flop,
CON0
for
al though
control
within
devices
prefix.
device
all
assignment
have
equipment
mode,
all
register
interrupt
registers,
in general,
for
control/status
priority
data
is,
status
a 3-bit
the
status
all
the
FLAG.
and
That
control/status
consider
control
be identical.
as status,
by CONO.
The
includes
scale
such
of 36 bits
additional
device
can
codes
must
be used.
Selection
of a device
between
the
At
and
reader
the
processor
is strongly
left
device
transfer
and
the
of
in Figure
selection.
conditions
transfer
functions
bus while
IOT
control
condition
and
status
and
the
timing
and
the
peripheral
advised
8-6
the
Every
while
pulses
commands;
IOT
the
before
units
to the
is connected
in and
out,
control
are
gates
AR onto
only
commands.
8-10
conditions,
and
described
in detail
in 8.1
processor
status
into
initial
any
to the
and
information
however,
of data,
investigating
connections
device
data
transfers
control
to study
are
out,
of all
six
in.
the
AR at the
a bidirectional
of the
for
peripheral
PI requests,
command
The
pulses
bus;
the
lines
levels
that
gate
processor.
All
device
uses
commands,
govern
the
output
clear
input
onto
devices
both
(which
equipment).
IOT
provide
status
types
the
require
of data
the
Although
al I devices
unit,
the commands
lower
left
define
when
Every
the device
gate
In the normal
in triggering
sequence
control
unit.
culated
for
for other
information
the CONO:
(Figure
upon
all
is supplied
the device
provide
conditions-in
to the same bus lines
register.
The outputs
for the various
are applied
to a gated
decoder,
requesting
within
a ground
a break
to governing
only
once.
information,
each
When
so that
DATA0
a control
bits as necesaddress
cal-
the configuration
of the input-output
but it need
not only
unit
initial
assigned
of the figure
Outputs
which
is generated
are applied,
provide
of the three
level
control
however,
are connected
contained
The 0 decoder
levels
PIA bits,
at pin P enables
to the number
to the device.
in gen-
are sent to the con-
I to 7 of this decoder
A group
corresponding
outputs
conditions
The outputs
system.
level,
the
in PIA,
output
i .e.,
is not
to no PI assignment.
information
an entire
CON0
unit.
decoder.
interrupt
gate
in the right
the control
on the channel
In addition
tions
the
the second
control
assignment;
the status
The AND
bits
on the output
SO it corresponds
functions
con-
the IC pulses within
bus by the effective
with
the equivalent
binary-to-octal
connected,
trol
over which
I ines of the priority
placing
ANDed
instructions.
of individual
operations
to the request
the initial
4- 14).
by any of the three
trol
provides
in the flowchart
the
devices.
and status flip-flops;
the priority
and is listed
to IOT commands
for all
first
IOS
the reset bypasses
PIA and sets up the other
The 1 states of the status bits are separately
eral,
responds
that
to the seven
pulses generates
over the in-out
always
then
registers
the control
into
wired
Note
on a control
by the net in the
net,
the program
of command
number
bits 33-35
bits depends
operations
channel
unit
the control
any effect
is generated
such a diode
The control
clears
to have
that
in the instruction.
pair
usually
I ines,
level
for any device,
whose
pulse
loads the assigned
The control
code.
of operation
The first
contains
IC CLR and clears
by means of a CONO,
sary.
control
code appears
ditions
pulse
in by a selection
selection
the appropriate
selection
to the six command
must be gated
of the figure.
I ines that
only
are connected
transfers,
block
of data
must assign
not necessarily
loads the buffer
has completed
the data
commands
can be processed
a PI number
set BUSY.
after
and provide
A common
8-11
of data
from
giving
procedure
buffer
certain
con-
the initial
the necessary
but also sets BUSY causing
the transfer
also perform
data
for output
the device
to device,
condi-
mode
is that
to operate.
its completion
dears BUSY and sets FLAG.
signal
interrupt.
FLAG,
Th e p rocessor
and again
CON0
to make
the control
device
gates
next
to clear
onto
word.
CON0
clears
to clear
BUSY,
of the DATAI
preventing
Small
scale
Teletype
these
in-out
devices
four devices;
lications.
The remaining
for the standard
and control
drawing
buffer
units
devices.
connections
or drawings
with
its connections
the first
contains
a data
reader
motor
provide
a
data
from
a single
PIA, BUSY,
to
mode flip-flop
is on.
Since
PI assignment,
tape,
8-bit
There
the reader
clear
FLAG,
character
1 in 10835.
hole
8 is punched
Binary
from
tape
mode
and assembles
is made available
describes
equipment
for the
an immediate
tape
reader
the control
are described
are in four groups
and punch,
units
in separate
shows the control/status
connections
for
of two or three
I/O bus as described
in 8.4.
pub-
each
register
The other
to the device,
and the data
I/O bus.
and the
register
is also an extra
is an input
device,
for the tape
to the desired
for initial
reads holes
six such
mode.
it available
characters
conditions
those
over bits O-5 of the bus with
8-12
hole
that
the
must
the first
mode
(B=O) reads
of the bus with
characters
word.
8-6)
CON0
to retrieve
bits 28-35
a 36-bit
(Figure
indicates
Alphanumeric
over
1-6 of only
into
reader
status bit which
set BUSY to cause the device
and makes
(B=l)
are paper
drawing
FLAG, the control
B.
to
Paper Tape Reader
and set up B according
hole
ter encountered
and
with
unit
that
word.
PDP-6
show the control
a
In addition
via the
the device
Then the DATAI
EQUIPMENT
This section
group,
to both
the last DATAI
used with
drawings
in each group
the buffer
of an extra
8 logic
to the processor
clears
BUSY
of the transfer
in preparation
peripheral
In each
setting
level
for other
Chapter
must include
the completion
clears
must provide
the control
IN-OUT
STANDARD
and card reader.
control
conditions
an
new data,
the program
for an interrupt.
must follow
most commonly
keyboard-printer,
provides
requesting
and sets BUSY causing
the retrieval
8.5
which
from the device;
FLAG
the program
PIA decoder
in the block,
BUSY and sets FLAG
The turnoff
To end a block,
DATA0
the initial
information
the
enables
the last word
the bus also clears
more data.
action
another
For input,
retrieve
then
with
Following
FLAG.
unit
to buffer
the buffer
retrieve
responds
sets BUSY.
an extra
from
then
The latter
in which
The first
1 on IOB5.
charac-
Figures
8-7
and 8-8 show the 36-bit
Registers.
A single
bit after
shift
it; output
example,
hole
from
right,
Figure
bit 35 (the presence
In alphanumeric
mode,
422 1 Registers
at all.
a single
are counted
Every strobe
sets the right
strobed
The sixth
to the left
8-hole
into
hole
hole
reads hole
2 into
the first
the 4221
strobe
in parallel
4221
Register
left
sets SR36 indicating
shifts
that
those ones that
that
bits 28 and
are not used
the entire
holes
left
in a new one.
of Figure
have already
36-bit
into
the previously
it reads
in the upper
etc.
bits of the
Registers
strobe
at the same time
Shift
into
29,
1 into
bit 34,
loads the six data
and each subsequent
sixth
17, 23,
the least significant
character,
Shift
For
11,
to load holes 8 and 7 directly
bit SR6 and also shifts
strobe
level),
module.
bits 5,
by the feed
by a negative
mode,
in an extra
a single
containing
generated
6-Bit
bit from 0 to 5 and every
read into
six holes are loaded
bits of the register,
The characters
one buffer
part of the buffer
is indicated
But in binary
one place
is made up of six Type 4221
is always
The strobe
the other
read character
in.
position
B(0) causes the strobe
that
significant
which
contains
that
8-7).
. Thus in reading
registers
the least
hole
with
of a hole
29 at the same time
module
a single
1 is associated
and 35 (upper
as shift
register
buffer,
word
8-7.
been
has been
assembled.
Retrieval
Figure
of information
8-8.
generates
When
a pulse
inadvertently.
the operator
that
O-to-l
acter
counter
placing
clears
BUSY to ensure
the tape
tape feed
switch
generators
-one
through
pulse
whose
(The operator
the feed
on the negative
termination
occurs.)
return.
generates
so that
hole
command
8-13
the brake
the first
and the trailing
the buffer.
left),
by means of the console
is generated
pulse
and the char-
(lower
is connected
pulse
If BUSY is 1, the leading
loads
the buffer
this action
edge
8-606
pulse must then set BUSY,
to clear
signal
the motor
in the program,
and releases
hole
ON
does not go into operation
appears
8-8C4)
of
MOTOR
in Figure
a leading
that
the level
a pulse generator
is encountered
the strobe
left
when
may duplicate
The feed
in the lower
to cause an interrupt
The second
the clutch
shown
the console,
the reader
through
PTR CLR (Figure
an inverter-
when
from
for the reader
register.
also engages
but no reading
transition-to-ground
a CON0
generates
in motion.
that
is also produced
When
BUSY(l)
by the logic
pulse also sets FLAG
the control
transition
SR.
is controlled
turns on the reader
clear
goes off.
pulse
whose
delay
clears
This start
the motor
command
.second
tape
and the same action
goes on,
when
from
edge
triggers
to two pulse
on the
generates
a
a 400-psec
This is timed
to occur
when
feed
the holes are centered
hole
strobes
sets FLAG
clutch
all
eight
and clears
and engages
BUSY(l)
to prevent
DATA1
gates
generating
the brake,
stopping
the tape feed
onto
every
if hole
of the shift
processor
registers
feed
hole
edge
mode flip-flop
binary
mode;
FLAG.
edge
the latter
clears
every
pulse then
releases
the
is gated
the processor
The termination
again
mode,
edge pulse
When
transition
pulse
to set FLAG
B (Figure
unlike
(B=O) punches
1.
Binary
according
by
responds,
of DATAI
the buffer
than
turnon
to allow
sets
and SR by
sets up B according
an entire
the clear
for every
character
supplied
DATA0
by the instruction;
BUSY and sets FLAG
to request
unlike
wear,
Because
mode,
and
is in alphanumeric
or
with
is a wait
I0835
circumstances
character
the cycle
8-14
is complete,
by gating
holes
6-l
the program
after
goes off whenever
the
must turn on the motor,
CON0
through
per
controlling
of 1 second
the motor
the program
character
Alphanumeric
the reader,
and sets BUSY to trigger
interrupt
by the
FLAG,
format.
and may set FLAG
the first
when
a priority
BUSY,
just one 8-bit
of the bus,
and there
in normal
including
FLAG
Also
motor
to the desired
which
mode.
punching
mode punches
To reduce
However,
clears
of the word
PIA register,
whether
by 10830-35.
speed.
bits
a 1 into SR36,
Retrieval
is in the character
for 5 seconds.
block
significant
hole 8, skips hole 7, and punches
turns on the punch
to reach
a 3-bit
by bits 28-35
punches
supplied
may vary.
and shift
BUSY.
B determines
supplied
always
conditions
to handle
8-9).
the character
the motor
into the least
a
Punch
bits as the reader:
modes
the punch
assignment,
Paper Tape
between
the operator
pulse generates
are the same as for alphanumeric
difference
(B=l)
l-6
the buffer
and clear
either
does not call
the initial
fill
however,
mode
but the terminating
loads holes
the reader,
to the characters
rather
the delay
Six strobes
of the reader
and the only
wishes
(The trailing
FLAG.)
The strobe
has th e same control
a data
program
The trailing
the PIA decoder,
the tape.
triggers
and sets SR6.
and restart
The punch
hole
enables
and the flip-flop
In alphanumeric
bits 28-35.
the bus and clears
b
mode
buffer
from setting
8 is punched.
the trailing
DATA0
into
the former
the reader
mode,
only
allows
holes
to the photocells.
PTR CLR.
In binary
strobe
data
respect
BUSY:
the buffer
BUSY to restart,
with
supplies
a PI
if the programmer
the PI system.
the punch
cycle
a done pulse
on the PIA decoder.
Then
for the
clears
Figure
8-10
circuits
shows the data buffer
that
operator
govern
feeds
Delay
the motor
tape from
period.
the console
SCR Driver
driver
The 1 state
(Al)
cannot
go on when
off level
from a second
generate
READY.
the two signals
motor
power
delay
delay
is delayed
the tape feed
from
is triggered
in the upper
mechanism.
A reluctance
pickup
provides
by READY,
triggers
a 5rnsec
output,
gated
BUSY(l),
gates
the data
the end of the punch
clears
hole
left synchronize
buffer
interval,
to generate
delay
driver
tape
Note
directly,
leader:
provided
the tape feed
but does not generate
the ready
contents
of the buffer.
The data
mode f I ip-f lop contra
In binary,
B( 1) provides
PTP7 clear
regardless
the buffer.
determined
The delay
to enable
the drivers
the motor
level,
by the contents
outputs
with
the
BUSY(l)
to
SOthe assertion
indicate
of
that
in the ready
clear
output,
the
signal
Diode
for the punch
terminating
feed
This allows
level
after
the gates
Gates
and punching
bits.
whose
with
solenoids.
At
pulse,
key operates
DONE,
the feed
the operator
the appropriate
punching
in the lower
to hold
and set pulses
buffer
and drive
ANDed
feed holes without
through
the 4113
of the corresponding
8-15
level
the tape
the speed
float,
with
a pulse generator
is up to speed.
format
of the act ion of the DATA0
the 4113
from
so it punches
through
is also ANDed
of the motor
and the delay
key enables
the punch
an interrupt.
delay.
the input
to the
so that
Both signals
to the period
release
The gate
of the first,
a sync mark through
s the character
a hard ground
in alphanumeric,
solely
that
GO.
the
the Type 823
the key logic
is off.
than
by enabling
1 state
Integrating
shorter
but the busy condition
punching
sets BUSY or the
is in turn ANDed
and causing
the solenoids
BUSY and sets FLAG.
solenoid
1 outputs
which
if the motor
the flag
The circuits
from
and timing
the 4303
the final
by the turnon
may proceed,
setting
motor
The delay
SPEED,
GO),
at intervals
after
enable
on.
1 second
is up to speed and punching
prevents
is turned
to generate
The second
by GO
on for 5 seconds
drivers,
the program
generates
turns on the punch
clear
solenoid
Whenever
of which
by the power
computer
punch
set as long as it is triggered
of this delay
however,
gates,
cycle.
(either
and holds the motor
is inhibited,
associated
and punching
in D6 is set and remains
delay
with
the
left.
PTP8 set and
on the remainder
of holes 7 and 8 is
of
c
The Teletype
device
is actually
Signal
code.
mon to both
tively.
two separate
names
devices,
Keyboard-Printer
and distinct
in the logic
drawings
TTI and TTO for signals
In addition
to PIA,
the control
register
to control
the devices
separately,
the first
clearing
and setting
of the other
control
the IOB reset does clear
the control
changes
clears
bits are handled
and sets TTO
when
by the data
in the transmitter
TTO FLAG;
is set,
clearing
DATAI
then
interrupt.
For input,
strikes
During
Setting
a prolonged
idle
the CON0
also clear
should
DONE
the entire
TTI FLAG.
TTI FLAG.
keyboard
either
interval,
character
from flag
clear
sets TTO
transition
has been
of TTI
clear
state
BUSY and
TTO
TTI DONE
with
setting
up PIA following
TTI FLAG
to prevent
readin
of a character
a
to request
to prevent
When
an
interrupts
an idle
that
BUSY
ACTIVE
received,
manipulation.
bits
operation,
clears
by the program
be left
only
In regular
gates on the PIA decoder
PIA should
clears
by CON0
in the transmitter
The response
flag
directly
the
period,
may have
been
accidently.
Data transmission
over
When
TTI BUSY and setting
clears
of TTO
TTI BUSY is set by the O-to-I
a key.
due to inadvertent
typed
setting
pair
derived
the DATA0
com-
respec-
to allow
to PIA).
and signals
and
two pairs of control
In order
bits are handled
For output,
and printer,
in the CON0
bits in addition
PI channel
TTY for elements
includes
F LAG.
pulse
instructions
and receiver.
the subsequent
FLAG.
the operator
the control
prefixes:
8-11)
and TTI
TTI BUSY,
a common
to the keyboard
(Figure
program
(of course
FLAG,
unique
TTO
both
TTO
with
use three
flip-flops,
PIA;
BUSY,
devices
bus lines
(10828)
between
28-35.
is always
1.
the processor
IOB35
corresponds
Between
is in the form
of 1 l-unit
one complete
character
requires
(space),
followed
a start
impulse
marks-and
transmission
the control
characters
which
exactly
and the Teletype
to the first
unit
is terminated
character
100 msec.
8-16
is in 8-bit
data
bits
characters
bit and the eighth
serially
Character
by a stop impulse
tinuously.
unit
and the keyboard-printer,
are presented
by the eight
control
data
bit
transmission
at 110 bits per second,
transmission
in order-with
(2 marks).
always
begins
ones represented
An idle
line
SO
by
marks con-
with
At the right
in Figure
pair
of clocks
input
provides
center
.
register)
(Figure
always
8-12,
upper
module
buffer
is left
transmission
cycle
applied
ENABLE(l)
sampling
level
in two modules,
the keyboard
changes.
Almost
Receiver
buffer
with
associated
control
(the output
buffer
is actually
no initial
reset,
so the program
data
included
generate
a
speed clock
for
data
all
Teletype
an 8-bit
that
The higher
a 4706
receives
character
clear
Clocks
after
near the
of the remaining
and a 4707
circuits
within
Teletype
and flags.
a IO-bit
separate
shift
clears
OUT
2 and 3 then set and clear
1 clears
ENABLE,
character
left
one unit,
The seven
succeeding
shifts
+2,
placing
shifts,
at clocks
immediately
the eighth
in A6 is satisfied,
enabling
ACTIVE
and shifts
left
impulse
to the printer.
data
by loading
in a 1 count,
holds
OUT
on to keep
LINE
. . .,
bit.
clearing
contain
clear
gate.
The shift
42
marking.
8-17
to inhibit
which
clears
the first
enables
line.
shift
pulse.
and out to the printer.
a 1 followed
10 000 000,
at clock
OUT
further
with
the rest of the character
with
and setting
by a
and moves the entire
LINE
17, move
enabled
ACTIVE(l)
generates
in OUT
TTOl-8
disables
a
into the
(0) on the printer
to TT08,
15,
the
triggers
ANDed
sets it.
impulse
When
and sets DONE,
the line
clock
the register
the register
a DATA0
The 4 count
transition
bit
they also fill
ACTIVE(O)
timer
clear
character
5, 7,
the ACTIVE
again,
a start
was in ENABLE
the first
one bit at a time;
placing
transmission,
holds at 4 until
input.
so the next
whose
the 1 that
out to the printer
after
LINE,
every
should
and then loads the character
that
the clock
for ACTIVE
After
When
DONE
is a 4-counter
from
or the operator
turnon.
character.
it also clears
The stop timer
the set gate
power
for the next
BUSY,
to a terminal
conditions
computer
in readiness
by setting
2, and the transition
Shift
during
of data.
chain
half)
and sets ENABLE.
1 count
t
this allows
ambiguity
registers
send a rubout
buffer
and receipt
resolution:
is included
and a countdown
.
The transmitter
data
time
bit to prevent
are shift
oscillator
the transmission
Each includes
Both buffers
TTO
greater
in the figure
Transmitter
are a crystal
to regulate
of each
logic
8-12
shifts,
the AND
19 then
LINE
by zeros
clears
to feed
enables
gate
a stop
the stop
BUSY and sets FLAG.
It also
The next
character
cycle
asserts the 4 count:
clock,
ACTIVE
clock
until
rate,
of the output
timing
apply
DATA0
chart
DATA0
to first-character
TTI (Figure
8-12,
conditions
the AND
+ 8, clears
buffer.
LAST
pulse.
UNIT,
buffer
onto
but enables
the next
gate
shift,
The AND
unit
clock
first
shifts
gate
clears
buffer
if not,
ACTIVE(l)
for
and for max-
and right
shown
the 4 count
22
the next
sections
for relatively
Levels
one-shot,
late
at the left
would
BUSY;
ACTIVE,
set input.
timing
enables
also
be up already.
the ACTIVE
gate;
and loads the start
impulse
and enabling
character
cycle
when
TTll
gates the
inhibits
the one-shot
within
the cycle
input
to the AND
the upper
begins
into
The DONE
the DATAI
are generated
generates
When
and LAST UNIT.
LAST UNIT(l)
clears
in the
by +8
responds,
impulse
through
flip-flops
asserted
the program
t8
start
8; the transition
sets all
4 count
other
set input
bits and move the 0 left.
no more shifts
inhibiting
t
SET, which
DONE
character;
The negative
1, enables
and DONE.
The next
chart.
and sets DONE
when
FLAG
the previous
so each
5, clears
the buffer
ACTIVE
contains
by clock
fills
a start
impulse
but
satis-
to this gate.
in 07 connected
5; otherwise
that
in the character
and clears
clears
input
except
read
clear
by momentary
shift
at clock
the lower
fies the lower
interval.
and generates
the shift
both
for the ACTIVE
The left
conditions
rate
which
produced
the bus and clears
4 count
rate;
by the printer;
this interval.
end of the input
asserts SPACE,
enables
The first
sets FLAG
the data
sets BUSY,
the 0, the last shift
transition
cycle,
ACTIVE(l),
TT18 as a 0; successive
contains
at maximum
the flip-flop
printing
or does so before
as required
within
the maximum
at the left
LAST UNIT(O)
a shift
appear
Clock
again.
Thus the stop is held on the line
(minimum)
respectively,
within
distributor
in 08.
SET,
is enabled
half)
are as shown
gate
show,
of an input
from the keyboard
units
set gate
set ENABLE
continues
DATA
or slow-speed
lower
At the beginning
has already
following
should
arrival
the .4CTIVE
23 and printing
or two character
imum printing
until
DATA0
the clock
periods
and normal
begin
if the new
is set at clock
does not occur
four
cannot
noise pulses
QTTI
ACTIVE
SPACE
to the upper
at the data
satisfies
ACTIVE
input.
the
gate
to reset the device.
8-18
clear
input
The start
(the
buffer
prevents
impulse
activation
must prevail
was set at clock
of the
through
1) so the
d
In addition
START
to
PIA
instead
of the
and
an auxiliary
and
the
a card
from
is also
available
CHECK,
CRL,
operation,
tion
CREL,
card
hopper
PG
is also
Both
modes
determined
ters,
but the
type
taken
CRXL
from
read
assembles
six
to a 6-bit
six
the
reader
ment,
set
START,
a card
in binary
START
no more
FLAG
and
1, 2,
strobes:
second
8,
the
reads
the
In alphanumeric
into
of this
signal,
the
other
rn d icates
check
the
four
that
l
the
3.2d).
The
computer
&bit
characters.
B,
reads
upper
device,
for
as the
which
DONE,
signals,
reader
FEED
is not
(for
ready
a full
signal
than
ALL,
is an
input
and
set up B according
because
causes
six
the
the
reader
columns
a II owing
every
at
first
a time.
column
to the
column
to read
initial
explanathat
FLAG.
word.
Although
The
data
half
(holes
(holes
12,
11,
the
by a single
least
however,
conditions
CON0
lines
The
charac-
(B=l)
4-9)
are
designated
reader
bit.
with
1,
2,
hole
the
mode
therefore
requires
six
Each
9 cor-
3) with
converts
This
reads
12 bits
significant
0,
strobe.
mode,
6-bit
one
lower
mode,
six
mode
the
half
from
Binary
CR1 L is the
desired
contains
an entire
To
retrieve
read
to set
8-19
for
indicates
in 88 to set
and
(Hollerith)
Either
as soon
CARD
EOF
words
into
word.
checking,
occurs.
columns
a single
status
reader
generator
three
read
MISSED,
status
card
in the
varies.
is then
DATA
CYCLE,
reader
error
pulse
contains
is cleared
negation
columns
which
for
The
of
A,
first
available
START
8-13)
*flop
CARD
operation,
number
4,
Since
36-bit
as two
are
flip
1) and
error
assembles
an error
START
or read
standard
(Figure
of START(
CRL
check
reader
OR
triggers
the
B,
as are
reader
card
hole
12 bits
strobes
for
characters.
Since
ting
to card
and
code
columns
23-26).
B assemble
two
(27)
its assertion
values
the
reader.
check
the
signals.
is the
bit
it is read
to CR 1 L .
in a column
the
a feed
column,
to CRlL;
corresponding
and
column
requires
status
from
information
the
but
a validity
by
X has
of these
(bits
whenever
the
All
as a status
is empty
of
flip-flop
status
EOF
for
mode
busy
refer
in a single
responding
signal
and
triggered
where
column
the
conditions,
register
additional
indicates
the
are
four
Reader
a data
ALL.
separately
of reader
12 bits
FLAG
CCL
control
BUSY,
cycle,
the
CREL
all
the
usual
provides
starts
is derived
FLAG,
flag,
reader
reader
and
Card
mode.
Usually
information
card
even
a single
FLAG,
must
about
provide
the
the
card
though
the
column
at a time,
which
otherwise
program
a PI assignprogram
begins
format.
can
retrieve
CON0
is set for
Set-
sets
every
six
3
characters.
FLAG(l)
response
card
by
the
cycle
the
buffer
may
a new
CON0
Figures
8-14
of a reader.
contain
and
8-14,
strobe
generated
CR2L
place
The
characters
are
counted
in.
sets
the
The
sixth
line
into
of
the
to the
left
bit
bit
strobe
which
has
80 columns).
which
is made
the
after
the
is set,
there
FLAG
The
when
FLAG
that
sets
DATAI
is cleared
program
card
are
even
still
six
though
program
SR6
sets
34,
for
etc.
und
4221
and
the
Shift
also
SR36
The
at
shifts
indicating
from
into
a single
bits
5,
must
first
the
provide
same
that
time
in the
left
those
that
the
module.
For
the
six
shifts
left
have
36-bit
sixth
example,
and
into
35
bit
35
data
the
it reads
that
entire
29,
CRlL
upper
ones
23,
loads
strobe
6-Bit
every
reads
strobe
4221
0 to 5 and
17,
subsequent
Register
Type
11,
a character
each
in parallel
up of six
bit
containing
register
in an extra
right
entire
read
The
one
the
is always
buffer
character
and
enough
a buffer
of the
bits
quickly
contains
part
read
strobed
module
that
significant
strobe
buffer,
with
the
Every
36-bit
data
into
START,
of the
a single
right).
affect
informing
(a card
manner,
card.
register
negative),
least
is set,
word
usual
respond
from
upper
(a 1 is asserted
not
in the
not
Completion
the
shift
does
MISSED
next
show
Each
CR1 L is associated
DATA
the
8-15
output
does
a complete
t.o read
but
program
in search
not
interrupt
FLAG
and
it;
(Figure
clears
If the
Registers.
after
a priority
is cleared
characters
bit
program
begins.
buffer
Shift
requests
bits
previously
in a new
one.
of Figure
already
8-14.
been
word
has
been
in the
lower
left
assembled.
Retrieval
Figure
the
of
information
8-15.
same
The
time
causing
the
CARD
CYCLE
mode,
CBIL
code
directly
that
reader
a card
CON0
pulse
it clears
which
to the
data
pulse
to the
check
in alphanumeric
acter,
the
data
check
causing
lines
button
if
I ines.
control
card.
entire
the
to translate
indicates
that
unit,
which
responds
by
only.
cleared
on the
reader,
If the
column
starts
data
the
busy
column
the
are
read;
it stops
and
must
hole
is ready
asserting
so al I zeros
8-20
reader
from
does
character
is set,
each
signals
and
START
to assert
reader
shown
buffer
When
however,
logic
When
continues
reader
B is 1,
the
register.
but
the
by the
The
mode
are
clears
control
START
character;
is controlled
an entire
clears
is negated
to a 6-bit
the
to process
strobe
validity
first
from
a level
not
contain
and
if the
be reset
counter
SCCL
the
from
CCL
For
the
are
by sending
a valid
operator
manually.
at
(02)
asserts
alphanumeric
12-bit
positions
that
(C4)
is asserted
card,
status.
of
Hollerith
applied
a column
causes
a validity
Hollerith
has
pressed
The
CSP
charthe
from
the
reader
also
buffer
and
This
signal
the
triggers
counts
of the
from
characters
also
no effect
half
pulse
the
words
are
strobe
to set
FLAG.
turnoff
Each
of
pulse
FLAG
is still
buffer
and
negated,
1,
sets
six
assembled,
also
that
the
MISSED.
CARD
to prepare
not
been
the
sets
to put
and
strobes
for
six
pulse
the
lf this
sixth
the
bus,
next
while
clears
from
the
the
DATA
triggers
and
character.
terminates
GONE
CCL
is 1.
the
onto
for
DATA
again
termin-
ALL
allows
20 psec.
the
terminating
buffer
delay.
and
reader
buffer
is finished,
FLAG
for
then
retrieved,
card
CBHL
if FLAG
the
the
asserts
delay
FLAG
gates
the
six
which
a 2.2-msec
when
which
The
SR30
into
half,
thus
sets
DATAI
clear
has
Finally
DONE,
sets
triggers
data
are
and
the
lower
three.
buffer
strobe
the
of the
or only
character
which
it causes
There
responds,
triggers
delay
strobe.
the
a delay
in place
in the
program
level
indicating
generating
lines
fifth
loads
in binary
columns
the
the
20-psec
DATA
data
that
triggers
but
of a column
gating
the
also
a second
reads
When
the
from
triggers
unit
being
a strobe
PA output
on the
presence
If full
to generate
in alphanumeric,
delay
the
Dl
The
column
the
whether
indicates
the
PA in
it in SR.
has
upper
ating
the
the
reader
is
GONE
delay.
The
logic
also
program
gives
which
PA
may
that
strobe
to
inspect
read
that
used
information
groups
that
allows
a CON0
during
the
card
change
pair
on
feature
a gate
the
is usually
usually
part
includes
triggered
rereads
the
contained
first
of a full
word
to reread
three.
as soon
as the
the
column
with
either
third
column
If a CON0
present
column
strobe.
the
ALL
column.
then
or
to read
set
pulse
delay
The
same
The
clear
FLAG
during
a card
is finished.
8-21
for
opposite
what
program
The
so that
cycle
mode
usual
and
the
twice.
initial
triggers
generates
program
final
sets START,
This
to read
the
may
same
or
feature
in a card,
the
first
also
78 columns
the
the
a strobe
mode.
I y starts
reread
If the
conditions,
termination
thus
or the
ALL
column
the
CON0
in alphanumeric.
card
any
whose
to determine
of a binary
given
one
a short
first
in binary
the
triggers
in either
It may
program
cycle,
FLAG
in the
column.
the
also
by
in conjunction
the
of
mode,
the
next
card
is
based
in binary
column
as
use this
are
card
read
will
in
be
CHAPTER
9
MAINTENANCE
This chapter
reader,
ories
discusses
punch,
level.
Circuit
procedures
in the following
Teletype
as well
Tape Reader
Model
Teletype
Bulletin
Vols 1 and 2
281B:
Model
35 Send-Receive
Teletype
(KSR)
1187D:
B122 Card
section
indicators
maintenance
in this manual,
plus
maintenance
schedules
corrective
maintenance
includes
of a diagnostic
the performance
commercial
and exercise
of the various
brands
Model
Technical
discusses
and
discusses
Parts,
Reader
of the chapter
those controls
maintenance
logic
specific
lubrication
devices
are included
3500
Speed Tape Punch
section
for the in-out
main-
manuals:
preventive
exe lusive
maintenance
with
at the system
Circuits;
tape
nor its mem-
preventive
is discussed
in PDP-6
High
Bulletin
the processor
for the exhaustive
are described
as corrective
processor,
must be used in conjunction
2158:
described
gested
neither
Bulletin
and describes
tion
Except
for the arithmetic
the maintenance
and repair
Perforated
Burroughs
ment
Since
herein
manual.
equipment,
manufacturer’s
Digitronics
The second
in-out
troubleshooting
and adjustment
The first
the information
in the memory
for the basic
maintenance
and card reader.
in isolation,
information
procedures
and corrective
keyboard-printer
can operate
tenance
preventive
Manual
operation
troubleshooting
and
are given
includes
are listed
for purposes
endorsement.
9-l
below;
of normal
The third
of marginal
Special
for maintenance
check
section
includes
Finally,
of the construc-
and test equipment
except
of specification
system operation.
procedures.
and a description
tools
purposes
a list of those for the equip-
memories.
procedures
loops.
Set
(B122.51)
not used in the course
programs
Set (KSR),
Teletypewriter
of the equipment
and a description
procedures
Teletypewriter
35 Send-Receive
the fast and core
program
Set (BRPE)
required
for DEC equipment,
only,
sug-
and do not constitute
for
Triplett
Multimeter
Dual-channel
Tektronix
oscilloscope
layed
System module
System
l-inch
gauge
width
Feeler
580 series,
sweep
trigger
DEC Type
1960
DEC Type
18467
cleaning
Digitronics
kit
Any quality
gauges
set,
scale
Chatillon
O-20 pound
spring
scale
Chati I Ion 719-20
Tape punch
maintenance
kit
lubricants
lubricants
Bulletin
tools;
lubricants
Cotton
swabs
Cleaning
f Iuids
Test cables
Super Fi lter
and probes
Kote
(aerosol)
with
lists all special
discretion
Teletype
KS7470
oi I; Mobi lgrease
Teletype
KS7471
grease
without
Burroughs
cloth
Q-tips
or equivalent
DuPont
Freon
Low-capacity
add KS7470
and S64960-2
oi Is;
or equivalent
TF; denatured
probes
alligator
clips;
Research
Products
Wisconsin
#2
and -39 greases
Cheese
9-2
punch
S 15821-26
S 1582 l-32
cloths
mils
11248
order
(installations
Lint-free
de-
719-10
Teletype
punch
Card reader
with
260
faci Ii ties
1-25
spring
KSR-33
preferably
Model
MS-133
O-10 pound
Punch
Simpson
DEC Type 0001
gauge
Tape reader
630-NA;
DEC Type 1954
extender
modu le pu I ler
Paper tape
Model
alcohol
for the osci I loscope;
etc.
Corp.,
Madison,
oil)
Also
have standard
wrenches.
hand
The card reader
and a pair
of 18-inch
also be available.
transport
additional
Phillips
a drift
pliers.
that
include
9.1
OPERATION
operation
controls,
checking,
power
primarily
bays; all
their
The main
power
switches
console
viewed
plugged
in,
Switching
control,
from
to LOCAL
at the lower
usually
pair
Type 829 which
that
on the in-out
has an additional
also supplies
Turning
on the main
Located
in the upper
ac for the motors
a power
by the main
power
control
control.
(Figure
have
that
behind
and explains
There are
for ac line and for
doors at the rear of the
the exterior
of bay 4 (the
on is registered
enable
directly
to the power
delay
shown
in the lower
right
the main
of Figure
clock;
5-l
ac to the fans and the power
door
punch,
and Teletype.
controls
and indicators
is a secondary
it goes on whenever
Also at the top of bay 3 is a panel
outlets.
9-3
power
This control
identical
the power
from
indicator
control
is a
This type of
so in a system
is not present.
supplies.
control
is usually
to those
containing
time
is
switch
is controlled
is not used.
clear
ac line
toggle
by an elapsed
that
doors.
left bay of the
power
In some processors
output
double
the external
is in REMOTE,
clear
is in REMOTE,
controls
is on whenever
for a delayed
supplies
the tape
to the operator.
and a LOCAL/OFF/REMOTE
3-3).
part of the bay 3 plenum
both
directly
the switch
has been
switch
control
in the reader,
Type 811;
this secondary
panel
equipment,
on the plenum
is at the bottom
breakers,
power
consult
should
Controls
outward,
when
in-out
available
are mounted
face
turns on power;
time
and basic
They include
It has a red light
using the 829 the integrating
otherwise
supplies
of ac circuit
etc.
for the logic.
Power
a Type 835,
the rear).
The total
left
power
hammer,
for the bay exteriors,
tape equipment,
are regularly
switches
and indicators
a ganged
the console.
control
and all
a plastic-headed
necessities.
for maintenance.
and maintenance
controls
magnetic
rod,
set of Allen
FOR MAINTENANCE
that
a
Most
cleansers
of the processor
and indicators
and a complete
a brass drift
Standard
housekeeping
normal
screwdrivers
punch,
for additional
3 discusses
marginal
requires
water-pump
the use of the controls
many
including
At installations
manual
Chapter
tools
that
a Type 834,
on the 835.
supplies
supplies
When
are turned
six ac convenience
on
.
As explained
in 3.2,
The ac line
through
to the punch
which
be bypassed
box.
power
is controlled
the logic
turns the punch
toggle
can go on only
the reader
buttons
a -1.5 vdc
turnon
may be turned
on the reader
tude
knob
(a similar
mounting
meter
modules)
pins A to D are connected
marginal
checking,
panel
there
in a panel,
module
receives
contains
no pulse amplifiers.
bussed to permit
(in the processor
remaining
the right
bus.
the logic
power
system power
the I/O
motor)
may
end of the chad
on its main
switch
in the same way
If system
by the POWER ON
power
is off,
and POWER OFF
down,
all
the modules
switch
to + 10 MC and pushing
directly
but all
the polarity
of a pair
panel
volt
lines.
power
B pins.
in the panel
All
lines,
the magni-
+lOA
and +l OB; one is
types
1609,
receive
the fixed
1607,
-15
switches.
fixed
toggle
only
in a mounting
are module
the normal
submodular
D pins are grounded.
marginal
up the top or middle
check
4606,
The C pin
if the panel
panel
are sep-
voltage
to them
6603,
6609);
When
all
voltages.
switch
three
Turning
applies
switches
the output
of the
supply
to the + 10A or + 10B bus respectively
on the panel.
Turning
polarity
switch
to -15
MC and pushing
switch
the marginal
9-4
applies
are
the polarity
power
toggle
the
volts.
variable
up the bottom
the
double-height
To allow
of negative
receive
output;
indicates
the C pins are bussed together
toggle
may be
of the in-
of the supply
application
are three
output
at the bottom
containing
The C pins of the pulse amplifiers
always
floating
on the supply).
and ground
+I0
to all
whose
of the console
panel
to the power
independent
Supply
and the dc voltmeter
the lower
independent
logic
Controls
controls
is mounted
volts,
in the panel
At the left end of each
switch
the other
-15
Check
amplitude,
the pulse amplifiers
modules
through
are on the front
(except
are two
on every
arately
on the punch
purposes
behind
has turned
is a Type 734 Power
voltage
logic
A pins
Marginal
The 3-position
In every
bussed to all
is supplied
door
the output
of the output
located
Then it turns on with
Its controls
3-3).
controls
directly
by the operator.
console.
from 0 to 20 volts.
(Figure
switch
on and off independently
At the top of the bay 4 plenum
out panel
is controlled
For maintenance
if the operator
signal
-b
varied
motors
on and off.
on the left side of the stacker.
as the 834:
large
and Teletype
by a Type 823 ( mounted
by means of an ON/OFF
The card reader
located
to the reader
the
check
voltage
to the C pins of the pulse amplifiers
applies
normal
While
voltage
marginal
checking
from one polarity
all
unselected
are left on.
only
to all
to the other
lines
(i.e.,
However,
At the completion
check
of marginal
switches
switches,
one for the eight
sole shelf
in the upper
voltages
the CODE
mation
HOLE
procedures
code
holes,
corner
supply
switch
allows
the other
panel
the normal
switch
application
should
voltages
panel
position
to
switches
are provided
off the toggle
turn off all
switches.
three
mar-
amplifiers
4K.
fixed
in the tape
hole,
When
to the right
for the feed
of marginal
(also
hole
voltage
are located
both
+lO volts.
reader.
below
switches
Turning
labeled
Two
the con-
are in the +lOV
the polarity
switch
+lO MC) applies
photodiode
output.
to the amplifiers
the
Similarly
for the infor-
holes.
Mounted
on brackets
allow
between
the technician
shooting
the logic.
Chapter
3 because
The RIM MAINT
Figure
5-2.
cannot
be cleared
stays
in the readin
the readin
above
switch
for turning
for the feed
Maintenance
that
polarity
to the photo
to the amplifier
fixed
switching
panel.
of mounting
receive
correct
OFF
switches.
off when
if the individual
the technician
mounting
the FEED HOLE
of the variable
even
not be used as a substitute
check
all amplifiers
applies
and the center-off
on every
right
switch
switch
of the toggle
need not be turned
polarity)
may also be applied
to 3-10 MC and pushing
output
the polarity
this interlock
check
(left),
because
the polarity
of the setting
switches
those of opposite
Marginal
position
the toggle
and should
toggle
lines regardless
a panel,
as a convenience
ginal
power
Turning
in the panel.
lM22,
can be repeated
23.
to alter
All
of these
switch
switches
is mounted
the switch
no matter
mode
Also
While
even
location
the chain
5-2
is on,
down.
a readin
2M1,2,
One
loader
in the bottom
does not include
9-5
the repeat
KT4.
delay,
left of
so that
it
The processor
may be run that
is the REPEAT BYPASS switch
in
of core.
in the lower
retrieval.
checkerboard
switches
was mentioned
of the RIM SBR flip-flop
is used for instruction
KTOA triggers
toggle
as an aid in trouble-
switch
and it is shown
the 0 output
and a memory
on Figure
this switch
when
depositing
side are five
of the processor
are off when
on grounds
what
on the wiring
operation
just above
indefinitely,
shown
panels
the normal
it must be used when
Turning
area.
the mounting
Switches
which
thus
includes
is mounted
so the key cycle
Two of the switches
shift-count
subroutines.
is ART3 MAINT,
return
left
With
the carry
is instead
by using
6-16.
in the normal
in the upper
prevents
the return
a shift-count
in Figure
interruptions
Shown
which
pulse ART3;
through
provide
simulated
on,
The last switch
may be used for troubleshooting
CYCLE
OVERRIDE,
if the MEMORY
flip-flop.
step is triggered
shown at the right
subroutine
makes only
shooting
procedures
accomplishes
Other
than
special
the power
maintenance
has switches
or the latter
reader
cover
the hopper
is on,
check
the set gate
controls
the
step
and shown at the
the next
step in
ful I, and these may be operated
until
the hopper
request,
16.
Ordinarily
cycle
sync
the memory
is undergoing
parts of a cycle.
troublethe memThe override
to the flip-flop.
in a and b above,
NOT
manually
LOCAL
switch,
1 N15,
AT4 sets the split
or Teletype.
generate
This is SPLIT
But in troubleshooting
mentioned
punch,
that
above
that
a stop.
the read and write
and stacker
cards continuously
19
generating
from the processor.
so a processor
by disabling
toggle
2C7,8
a fetch-and-pause
during
for the reader,
is a local/remote
to feed
generate
to memory;
and marginal
lH18,
may single
can trigger
7-9 and mounted
STOP switch
to stop it between
switches
inside
empty
the reader
the memory
the memory
this objective
above
above
from
A technician
SCTO nor SCTl
in Figure
should
a read request
does not hold
ory it may be desirable
switch
cycle
and mounted
and
by KT2.
STOP key or the ADDRESS
Then if the fetch
in the arithmetic
in an AR subroutine
is mounted
neither
instead
6-9
by KT2.
which
the subroutine;
of events
of Figure
completion
SCT MAINT,
this switch
each
right
flow
RUN.
The card
READY
when
there
are no
reader,
however,
the former
is
for maintenance.
Under
Raising
(local)
is empty,
this switch
and then
stop with
the
causes
FEED CHECK
on.
Besides
top
the switches
there
are many
of bay 1 most of the indicators
flip-flops
requests
displayed
and levels.
have
been
maintenance
which
The PI REQUEST
synchronized,
by a set of lights
mounted
indicators.
display
lights
the states of all
on the console
but the signals
in front
This category
arriving
of module
the PI1 line.
9-6
SBRs and many
indicate
at the logic
connector
includes
2L20.
at the
control
those channels
over
the I/O
on which
bus are
The top light
is for
d
By using
the STOP and CONTINUE
program
from one instruction
single
In either
manually
ically
by latching
call
on the CONTINUE
key,
call,
STOP light
discussed
that
finer
steps.
processor
results
on bay
plied
to AR and MQ,
1.
To observe
should
the necessary
because
there
To produce
MEMORY
CONTINUE;
from the key causes
switches
memory
subroutine.
automat-
and setting
the
a memory
must be on for the SBR that
displayed
by the indicators
by following
with
pulse
the flow
charts
any initiating
switch
key can
settings
are
index,
at which
or negation
the stop occurred
of the shift
step in it.
by pressing
After
MEMORY
the lights
the subroutine
pulse,
The
for the arithmetic
and the effect
of shift
The attendant
but triggers
pulses ap-
to the shift-count
an ART3 or an SCT stop,
CONTINUE.
so the
by one of the SBR
then stops prior
either
in even
is performed.
is indicated
counter
The processor
can be operated
from the AR subroutines;
can then be seen by observing
every
the
key cycle
no other
sup-
operations
stop.
restart
after
this causes
the delay
if MEMORY
MEMORY
every
every
termination
can be left on together,
step in a shift-count;
may be done
stops following
the processor
the return
subtraction,
pulse for simulating
an automatic
restart
and the required
in c above,
inhibits
turn on SCT MAINT.
is no memory
the processor
associated
delay,
keys for
can be performed
of the information
the function
the operation
be restarted
stepping
can be determined
discussed
an addition,
and also following
processor
plies
switches
time
and each
may
5.
on bay 2, and the point
subroutine
REPEAT,
of the subroutine
lights
panels
on ART3 MAINT
stops every
immediate
registers
Turning
step a
the technician
on the REPEAT switch,
Each time
KT4 set the repeat
at the end of Chapter
By using the maintenance
turning
The meaning
Using
all require
or the single
on,
and at the top of bay 1 a light
return.
proceeds.
may single
for maintenance
be latched
interval.
and the bay indicator
as the processor
be repeated;
time
is on,
the subroutine
the operator
to the next by using the STOP and CONTINUE
key;
to the desired
on the console
Similarly,
the CONTINUE
SPEED controls
is awaiting
keys for instructions,
case the STOP key should
by pressing
the MEM
Step Operation
to the next.
step from one memory
memory.
Single
stop,
turn on REPEAT BYPASS and latch
KTOA to retrigger
to retrigger
so the processor
the key cycle.
stops after
STOP is left on too,
CONTINUE
supplies
9-7
the repeat
every
and the level
The ART3 and SCT
AR subroutine
the processor
the restart
delay,
on
for all
and every
wi II also stop after
three
every
types of stop.
While
the processor
is single
charts
and compare
the information
in the lights.
The point
The indicators
display
stops within
of an instruction.
struction,
light
given
at which
a great
an instruction
deal
may sometimes
stepping
be on.
ventive
(maintenance
maintenance,
sists of program
a section
and a third
The first
quired
describing
section
tapes,
loading
specifies
that
and tells
the operator
program
and margin
descriptions
appropriate.
furnishes
the operator
information
another
need
with
is stopped
only
1
at
at the end
of an in-
AR and memory
to the flow
stops,
the
charts.
of the PDP-6
for check-out,
Each MAINDEC
manuals
have
suggesting
use when
pre-
package
the same format:
applications
procedures
con-
an abstract;
of the programs;
levels
that apply
including
octal
explains
the MAINDEC
to each
what
program.
listings;
the program
or modifying
are applicable
MAlNDECs
and gives
to the basic
marginal
section
to the
suggests various
checking.
section
charts
is testing
hardware
for
as to the cause of the error,
The third
flow
instructions
are indicated
The second
with
It lists the re-
It specifies
contains
are included
and in what
detailed
where
manner,
the program.
for PDP-6).
9-8
detailed
how errors
the program.
and symbolic
to aid in updating
list of all
switches,
a MAINDEC.
providesinformation
or restart
for using
running
part specifies
or typeouts),
how to repeat
MAI NDECs
for the current
cycle
on bay
of the processor
off at the completion
malfunctions.
. All
The final
halts
Each description
The following
library
information;
the programs.
(e . g . , programmed
the panels
manual
by the lights
the workings
self-testing
equipment
as displayed
PROGRAMS
the usage of the console
operator
including
permit
of the processor
the processor
refer
in the flow
the programs.
is all
and starting
applications
programs
tapes and a reference
operator
always
the operations
is indicated
I is always
MAINTENANCE
or diagnosing
containing
when
an address
For particulars
DEC)
the state
about
light
through
9.2
MAINDEC
can provide
the indirect
follow
has stopped
more information
than they
single
should
by them with
the processor
For example,
but when
the technician
stepping,
(consult
the DEC program
and
l
Test
Instruction
Part
Part
Part
Part
Part
Micro
MAINDEC
Test
1
2
3
4
5
601-l 601-2 601-3 601-4 601-5 Checkerboard Memory
Clock
Address
602 Test 603 Test Memory
604 Speed
Test Memory Retention
Power Failure Memory
605 after 606 Over lap 607 Power Failure
Test 608 Reader
Binary
Test 610 Reader
Alpha
Test 611 Punch Test Memory
612 Data
Teleprinter
Test 613 Test 614 Memory
Checkerboard Low 64 x 4K Hi 4x 4K 16x 16K 16 x 16K Interleave Protect
Card
and Relocate
662- 1 622-2 622-3 622-4 Test 623
Reader
Test 641
Fast Memory
Test 662
9.3
This section
discusses
procedures,
and lists recommended
equipment.
Preventive
system and periodically
preventive
PREVENTIVE
maintenance
maintenance
during
MAINTENANCE
schedules
and use of marginal
procedures
for the arithmetic
consists
of tasks performed
its operating
life
9-9
to ensure
that
processor
prior
check
during
and the basic
to initial
it is in satisfactory
PM
in-out
operation
operating
of the
condition.
Faithf u I performance
progressive
deterioration
mechanical
checks,
borderline
circuit
of specific
elements
of these tasks forestalls
and correcting
including
minor
cleaning
conditions
damage
and inspection;
or intermittent
such as power
possible
failures
supplies,
failure
by discovering
at an early
stage.
The
marginal
checks,
which
to make
in-out
future
tasks
circuits,
drivers,
of
aggravate
them easy to detect;
interface
consists
and checks
and sense
elements.
a
Preventive
mended
maintenance
intervals
ules.
for PM checks
interval
of this type
days every
Marginal
nominal
which
maintenance.
future
the total
shift.
period
necessitate
sched-
malfunctions,
large-
Each user should
set up
should
over the longest
be assigned
an appropriately
system
Recom-
as calendar
PM task evenly
Without
such preventive
PM,
biased
to per-
designed
unavailability
Accurate
components
replacement,
for two or three
log.
or when
no marginal
margins,
By plotting
above
in locating
scheduled
in locating
exist,
at which
obtained
and expected
provides
by the
preventive
components
bias voltages
or
the source
and the margins
observable
capabili-
are detected
during
are also useful
0
margins
or under-biasing
be replaced
transistors.
9-l
specified
over a long period
These plots
such as deteriorating
within
helpful
is easily
acquired
to test the functional
indication
the specified
deterioration
information
replacement.
by over-
can then
beyond
programs
biased
visual
in the maintenance
progressive
preventive
about
or other
components
are then
voltages
brought
a printout
Marginal
diagnostic
operating
Failures
are recorded
scheduled
the MAINDEC
module
provides
voltages
fail
intermittent
with
After
are predictable.
ning
utilizes
levels.
the malfunction.
circuits
would
as well
be staggered.
a specific
for that
time
schedules.
month.
ties of the system
operating
PM program
shift,
to strict
and to minimize
should
distributes
operating
the PM function
checking
program,
that
operating
operations,
at long intervals
In every
according
on elapsed
normal
installation
of the scheduled
and Marains
be performed
are based
occur
recommended.
program
below
that
for his entire
formance
should
in scheduling
PM procedures
a schedule
each
procedures
For convenience
scale
Schedules
during
failure
dates
a basis for planmarginal
or
of
Raising
the operating
overcome
voltage
by the previous
voltage
below
fiers)
runaway).
increases
l-10 margins
supply
the line
For every
the failure
MAINDEC.
DEC supplies
charts
for +lOA,
-+lOB, and -15
on the supply;
for normal
time of the voltage
When
equipment
too narrow),
At each
operation,
region
troubleshooting
chart,
a
the abscissa
check-out,
Daily
Operator
1.
two points
(nine
a particular
switch.
by abnormal
margin
procedures
(9.4)
be performed
the voltage
pairs of
as read
below
level
shows the change
in
operates
properly.
the region
to diagnose
number
being
the abnormality.
in the maintenance
apply
Arithmetic
only
Processor
to the arithmetic
PM
processor;
procedures
for the in-
Maintenance
Log al I error
each
is
in -c below.
Run all five
on
which
(e.g.,
the page
charts
the appro-
level
are provided
volt
can result.
running
is the margin
levels
The -15
page has three
of the logic
is induced
The
voltage
while
each
negative
from the power
check
Thus a chart
section
for entering
has a separate
of logic
for
to pulse ampli-
maintenance
are plotted:
should
only
to the logic
spaces
is too low.
(to check
are -7 and -8 volts.
The ordinate
is the time
is done
or damage
the
and thus provides
the marginal
section
checks.
Lowering
comes directly
form for such plots;
are provided
fai I.
must be
is explained.
in this section
are given
volts
maior
and that which
-b
out equipment
standard
marginal
spaces
such dysfunction
The procedures
modules
keep preventive
for each
over which
malfunction
At the top of each
log where
margins
(this
margins
bias that
conditions
Each panel
level
-18
the user should
priate
too high
supply
the -15
are plotted
for the date).
volt
3-5 and +15 volts;
which
chart
temperature
comes through
in the PDP-6
transistors
high
to pin C for logic
than
cutoff
bias and noise rejection,
pulse amplitude.
be made more negative
system
from the meter
cutoff
low-gain
to pulse amplifiers
are normally
must never
the transistor
therefore
the -15
the output
the line
increases
and simulates
or lowering
or decreases
whereas
transistor
transistors
Raising
+I0 volts
transistor;
reduces
bus to pulse amplifiers;
supply,
driving
+lO volts
a test for high-leakage
thermal
above
parts of the Instruction
ha Its,
noting
the cause
Test (MAINDEC
if known.
9-l 1
601) without
margins.
2.
Check
air flows
3.
that all
freely
Replace
cooling
through
The remaining
procedures
components
such as indicators,
by trained
RUN
PART
3
WITHOUT
MC
RUN
PART
WITtiOUT
fuses,
personnel
*
FIX
TROUBLE
USING
PART
3
HALT
TROUBLE
__I
2
MC
RUN
PART
WlTti
MC
PART
5 MAY
BE
HELPFULL
IN
DETERMINING
EXACT
CAUSE
OF FAILURE
3
4
MC
RUN
PART
5
WITHOUT
MC I
RUN
WlT!i
PART
FULL
etc;
only.
1
HUN
PART
NITHOUT
cooling
in the log.
are to be performed
FIX
TROUBLE
and that
the filters.
any noncritical
note any replacement
fans of the system are running
RUN
4
MC
WITH
PART
FULL
5
MC
PERFORMAfuCE
Figure
9-l
Processor
Marginal
9-l 2
Check
Flow
*
4
FIX
TROUBLE
4
I
1
Weekly
1.
Check
the operator
the machine,
and take
2.
noted
If trouble
shooting
methods,
program,
contact
by use of moderate
logic,
do so.
any provisional
voltages
diagnostic
adopted,
down
in
if necessary.
who made
by normal
the note;
on certain
to make an appropriate
measures
have occurred
trouble-
using his
If the system can be kept opera-
the trouble.
margin
which
be reproduced
the operator
Do not fail
that
measures
in the log cannot
tional
authority
any malfunctions
corrective
try to reproduce
cribing
Every
log; note
small
entry
and notify
time wi II be required
sections
of
in the log des-
the scheduling
to rectify
the trouble.
1000 Hours
1.
Run all five
using
tive
the flow
parts of the Instruction
diagram
maintenance
levels,
voltage
note all
Change
tire
system
a.
b.
c.
the two thumb
in the maintenance
margins,
on the preven-
at abnormal
margin
log and cross reference
at the bottom
of every
bay in the en-
procedure:
screws holding
the fan and filter
Take the filter
out of the housing
housing
of the bay.
Remove
install
the results
In case of failure
the air filters
using the following
the floor
and plotting
601) with
by page number.
and clean
Loosen
9-l)
charts.
circumstances
the log to the chart
2.
(Figure
Test (MAINDEC
the housing.
a clean
Replace
one.
the housing
the two thumb
and
containing
screws.
9-l 3
the clean
filter
and tighten
to
d.
Clean
water
filter
in a direction
and lint
e.
the dirty
maining
hot,
opposite
is removed
Stand
moisture
to evaporate.
the filter
product
The spray serves both
.
with
which
gauge
under
tape equipment
is supplied
the correct
with
the system;
Wh en examining
be exact-the
to variations
To ensure
that
tape
Model
accumulated
error
feedhole.
sure that
rately
with
re-
15 minutes.
Kote
or an equivalent
medium
dust and
lint
and as
during
the
PM
for the tape
reader,
Procedures
them.
punch,
keyboard-
for al I four devices
PM intervals.
punched
use it for al I paper
error
will
tape.
A DEC standard
tape measurements.
by the processor
in 6 inches.
of every
on the gauge
exceed
paper
A paper
will
tolerance
punch
in the system
are within
tolerance.
adjustments
9-14
with
to inner
the naked
the tolerance.
tape
tape with
be readable
hole
is about
should
edge:
eye,
readers
this dimension
spacing
It is much easier
readers
must be within
one eighth
be checked
has a wide
in general
on mechanical
to read a wide
it must be
The reader
but mechanical
longitudinal
The 5 mil
the reader
from feedhole
hole spacing,
35 or the Flexowriter,
to try to jockey
distance
the tape
in longitudinal
the base dimensions
than
to allow
is sufficiently
capturing
procedures
associated
visible
punched
The output
as a dirt
Equipment
is the lateral
smallest
tolerance
all dust
is shown on the next page.
.392 f
the Teletype
In-Out
accurately
dimension
must
in about
wash out trapped
the recommended
The most important
inch.
When
water
Super Filter
maintenance
requires
specifications
.002
hot tap
flushing.
and DEC logic
together
aeroso
helps
preventive
card reader,
The paper
If the flush
f . Spray
includes
with
shake out excess moisture.
c
are grouped
to that of air flow.
the fi I ter shou Id dry camp etely
next reverse
printer,
it thoroughly
the fi I ter on one end for 10 to 15 minutes
a detergent
This section
by flushing
every
to punch
tolerance
such as
k5 mi Is
the diameter
once
do not.
of the
day to en-
the tape accu-
of tape dimensions.
The punch
is within
can be adjusted
7 mils of the nominal
wi I I punch
(993
to produce
properly
.
accurate
1 inch.
If possible,
lateral
Once
make
spacing
on any given
it is so adjusted,
adjustments
tape whose
any tape of 1 f
whi le punching
.007
the narrowest
inches
tape
inch).
The following
procedures
Oai ly Operator
Tape Reader
Using
2.
Digitronics
bearings,
check
of the tape
3.
Remove
photodiodes
4.
Check
top surface
610,
is laterally
error
the exciter
clean;
the read head,
read head
halts,
noting
lamp cover
replace
if there
springs
margins.
to ride
is designed
the cause
and check
the bulb
the lamp cover
611) without
positioned
the photoelectric
Log all
clean
tape guides,
and brake.
the tape
guide;
that
kit MS-133,
tests (MAINDECs
that
this position.
cleaning
capstan,
Run the reader
tests,
that
along
During
the
the inner
edge
to accept
tape
in
if known.
the lens is clear
and the
is any sign of yellowing.
are adjusted
so as to just touch
the
of the tape.
Run the punch
noting
2.
equipment.
-
roller
1.
for the in-out
Maintenance
1.
Tape Punch
are recommended
the cause
Using
612) without
margins.
Log all
error
halts,
if known.
the DEC standard
to the following
a.
test (MAINDEC
standards
Feed hole
to inside
tape
gauge,
(see Figure
edge:
check
that
9-2).
.392
9-15
f
.002
inch.
the punch
output
width
conforms
b.
&I5 mils accumulated
c.
Width:
IDIRECTION
0F
1 f
TAPE
.007
longitudinal
error
in 6 inches.
inch.
MOTION
IA
00
00
0. . . 00
..
0.0
0.0.
71
00
0.0
0.0.
0 ..:.
0
00
0
. . . . . . . . . . .
l e.0..
0.0
0.00..
0.0
00
0.0
00
l o.0 -7
mooooooooooooooooooooooeoeeeeeeeeoeeeoeeeeeeeeoeeeeeeeeeoeeeeeeeeoeeeee
EDGE
Figure
3.
Check
for “fuzzy”
9-2
holes.
NEAR
OPERATOR
Paper Tape Dimensions
This indicates
a misadjusted
or worn
out die
block.
4.
Empty
the chad
new box of tape
5.
Clean
or other
box should
also be emptied
every
time a
is insta I led).
the punch
solvents
the light
Teleprinter
box (the chad
by blowing
dust off the die block.
near the feed pawl
lubricating
or die block
since
Do not use alcohol
such solvents
remove
film.
1.
Inspect
the platen
has been
and clean
the platen
needs cleaning
run without
only
and paper
if typing
paper).
9-l 6
guides
as necessary
(in general,
has run off the page or the printer
t
1.000
5.007
in
2,
Remove
replace
3.
and other
the ribbon
Reader
noting
fouling
material
from the ribbon
guides
and
if necessary.
Run the Teleprinter
halts,
Card
lint
Test (MAINDEC
614) without
margins.
Log all
error
the cause if known.
-
I.
Remove
the exciter
and the hopper
area
lamp assembly.
with
a soft bristle
Clean
the solar
cells,
the feed
head,
brush.
CAUTION
Other
agent for the solar cells.
the potting
in the assembly.
Use only Freon as a cleaning
cleaning
fluids may damage
2.
Run the Card
unusual
wear
Reader
Test (MAINDEC
on the test deck.
641) without
margins.
Log all malfunctions
with
Watch
probable
for
cause
if known.
Every
160 Hours (Monthly)
Tape Punch
1.
Remove
procedure
grease
outlined
the general
ions.
Make
but do not apply
contact
between
and perform
Bulletin
the armatures
2158.
the complete
lubrication
Be sure that
and magnet
pole
no oil or
faces or between
points.
Inspect
connect
from the console
in 5 of Teletype
accumulates
contact
2.
the punch
points
condition
direction
(clockwise
elements.
Check
moving
sure nuts and screws that
sufficient
meet
of all
torque
squarely.
as viewed
for freedom
to disturb
Rotate
lock
of movement.
9-l 7
the adiustments
the adjustment.
the main
from the front)
parts and tightness
shaft slowly
and activate
of wiring
are tight,
See that
all
in the normal
all
movable
3.
Run the Punch Test (MAINDEC
on the PM voltage
chart;
the log to the chart
Every
612) with
log abnormal
by page
margins.
failure
Plot the failure
margins
points
and cross reference
number.
330 Hours
Tape Reader
-
1.
Carefully
perform
the daily
of the tape as it proceeds
against
tape,
2.
the inner
edge
Carefully
check
in the accurate
and thread
through
is well
(with
the tape
all
feedhole
The diodes
diode.
holes punched,
centers
of those holes.
correct
it by shimming
3.
Check
the exciter
4.
Check
the pinch
energized.
5.
With
engage
which
dirt
8.5 f
to capstan
clearance
may be limiting
.l
travel
as if reading
tape.
The correct
the roller.
with
manual.
roller
adjust
Severe
just barely
a slight
If the roller
it,
directly
iitter
according
indicates
as follows:
9-l 8
the
the
is apparent,
excessive
clutch
of the clutch
deis
solenoid.
the READER FEED key to
clutch
setting
the highest
sensation
does not contact
the clearance
under
if the clearance
to engage
jittering
over
guides.
with
is TO to 12 mils;
the full
the holes
or brake.
or if skew
gap clearance
the clutch
causing
with
9-2.
volts.
it on and lift
against
be tested
voltage:
turn
capstan,
tronics
is incorrect
the read head or the tape
bulb
the pinch
in Figure
the clutch
the feedhole
in the reader,
rotating
tinuously
center
paper
Turn on the reader
but not through
no tape
allows
tolerances
removed).
it travels
punched
for holes 1 and 8 must lie directly
either
The proper
insufficient,
still
If this alignment
roller
to the position
sure that
of read head photodiodes
the guides
Using a line with
and making
the dimensional
lamp cover
through
attention
Use an accurately
guides.
within
the alignment
tape
particular
the reader,
of the tape
one which
i.e.,
PM paying
is that
point
in the finger
the capstan,
to Section
capstan
on the
when
held
or runs con4-13
runout,
of the Digiwhich
should
a.
Turn the reader
slides,
off,
and remove
pull
it from the console
the drive
belt
from both
on its extension
capstan
and motor
pulley.
b.
Turn on the reader
Using
I-
capstan
Stan,
and 2-mil
feeler
and pinch
turning
and lift
roller
READER FEED to engage
gauges
check
for various
it by hand.
the clearance
angular
If runout
the clutch.
between
positions
is excessive,
of the cap-
the capstan
must
be replaced.
c.
6.
Turn the reader
Using
a spring
activated
pinch
the procedure
7.
Check
tape
tension
roller
a fine
rubber
dust to collect
8.
Check
end.
brake
insert
armature;
file
4-15
to the capstan
around
tape
while
on the clutch
use a spring
3-l/2
to 7 pounds.
the force
scale
necessary
If adjustment
the area
skew;
hooked
the tape with
to unseat
is necessary
the
use
manual.
where
the edges of the
they may be removed
the reader
is running.
by ap-
Do not allow
block.
using a short piece
the free end of the tape
to move
that
step 2 of the Digitronics
can cause
tension
quired
Teleprinter
check
on the capstan
Such ridges
plying
scale,
the belt.
is from 3 to 4 pounds.
in Section
for ridges
ride.
off and replace
of paper
between
into
the brake
tape with
the brake
solenoid
the loop to measure
engaged.
a loop
The force
in one
and its
the tension
re-
must be from
1.
Lift
screws,
2.
the cover
and check
retaining
clips,
Check
the selector
is no lubricant
or other
everywhere
for effects
of vibration:
loose nuts,
etc.
magnet
coils
for signs of overheating.
fouling
material
9-l 9
under
the armature.
Make
sure there
If necessary,
insert
a piece
lubricant.
Card
Manual
Reader
of bond paper
Make
- Sections
B112.51
1.
sure no lint
and figures
the pole and armature
to soak up any
is left.
referenced
below
are in Burroughs
Card
Reader
Technical
.
Check
exciter
The procedure
of all
between
lamp brilliancy
requires
a deck
ones in twelve
according
to 3.16;
of cards punched
columns
followed
step and step 2 must be performed
by all
whenever
adjust
with
if necessary.
a repetitive
pattern
zeros in the next five.
photo
amplifiers
This
are changed
in the reader.
2.
Using
the same test deck,
pulse with
respect
3.
operation
Check
(performance
4.
Check
Check
2.3),
to the read pulse
of the strobe-8
can be checked
response
(the procedure
5.
check
of card-detect
requires
performance
using a deck
only
a deck
the leading
for all
twelve
counter
solar
cell
of the strobe
rows (Section
3.17).
to Section
3.18
the counter).
CD1 according
of cards having
a 4 punch
for valid
by punching
timing
according
by adjusting
of the translator
prepared
edge
to Section
in column
80).
codes
(Section
Hollerith
each valid
code
circuits
(Section
3.19
in alternate
col-
umns of a card.
6.
Test performance
50-card
deck
punches
(all
7.
Using
surfaces
in which
invalid
Burroughs
(Figure
and ‘the feed-slide
(Figure
4.5-1,
of the validity
column
40 of each
combinations
S64960-2
3.4-1,
check
card contains
are listed
oil,
right),
fork/actuator-arm
lubricate
the feed-knife
pivot
top right).
9-20
2.4),
one of the invalid
at the bottom
of Table
the feed-sIide/gib
pivot
(Figure
post bearing
using a
A4-3).
bearing
3.4-1,
surfaces
C),
8.
Run the Card
failure
points
reference
Every
Reader
Test (MAINDEC
on the PM voltage
the log to the chart
641) with
chart;
margins.
log abnormal
by page
Plot the
margins
and cross
number.
1000 Hours
Tape Reader
1.
Perform
the inner
the daily
and 330-hour
edge of the tape
2.
Check
3.
Using
all power
lines of ones and zeros,
margins
applied
at top speed
unless
the tape being
in Figure
4.
9-2,
Observe
reader
dual -channe
5.
Apply
amplifier
(beneath
Tests (MAINDECs
against
signal
the inner
at pin
the processor
margin
while
the code
The trailing
of the code
holes by 300 to 500 psec; code
amplifier
adjustment
6.
Using
per second
it satisfies
that exhibits
with
code
this trailing
extreme
potentiometer
MAINDEC
of the feedhole
changes
should
edge
output
should
hole
containing
with
run the test tape at all
hole
margins
the
input
of a
for a width
of 1 msec.
and adjust
the read
signals
lead the trailing
width
timing
610,
should
moderate
with
edge
be approximately
requirement.
A read
rotation
a less sensitive
of the
card.
speeds up to 400 characters
from 3 to 17 volts
9-21
guides.
hole and feedhole
in gain with
be replaced
the tolerances
one vertical
hole amplifiers,
the scope.
1 .8 msec when
edge
both
within
18M in the panel
with
Run the
no adjustments
of the tape
the feedhole
to the code
observing
edge
console)
Adjust
well
611) with
logic.
Make
dimensions
alternate
610,
control
per second).
has lateral
I osci I loscope.
a +9 volt
along
lamp voltage.
test tape with
and reader
(400 characters
read
the exciter
punched
run the Reader
and travels
cards
including
of accurately
the feedhole
logic
voltages
to the read amplifiers
reader
Tape must travel
guides.
supply
the same length
PM schedules.
and feedhole
margins
Amplifiers
from 5 to 15 volts.
these margins.
clutch
Error halts
and brake
by poorly
be touched
with
the margin
log the prior
the log to the chart
up as necessary
a splice
be disregarded
Plot
are required,
cross reference
Tape Punch
occurring
can usually
made splices.
adjustments
should
on the test tape
since
levels
between
these are generally
on the PM voltage
and post adjustment
by page
to obtain
margin
caused
chart;
if
levels
and
number.
-
1.
Check
the Teletype
Maintenance
Kit for parts which
may require
periodic
replacement.
2.
Run the Punch Test (MAINDEC
on the PM voltage
log to the chart
Teleprinter
by page
log abnormal
failure
margins.
Plot the failure
margins
points
and cross reference
the
number.
1 . Clean
2.
the distributor
Perform
Teletype
3.
Bulletin
Tape Reader
lubrication
1 (there
swab,
procedure
as prescribed
are four applicable
sections;
by
see
of contents).
test (MAINDEC
on the PM voltage
erence
2000
table
Freon and a cotton
teleprinter
281 B, Volume
Run the teleprinter
points
with
the complete
the Bulletin
Every
chart;
612) with
chart;
the log to the chart
614) with
log abnormal
by page
margins.
failure
margins
Plot the failure
and cross ref-
number.
Hours
-
1.
Check
2.
Inspect
all
all
electrical
connections
for electrical
moving
parts for wear.
9-22
and mechanical
security.
Card
Manual
Reader
- Sections
B122.51;
1.
and figures
part numbers
Check
a.
referenced
specify
the following
b.
feed
tensions
Exciter
(Section
side plate
c.
Top and bottom
d.
Feed-knife
e.
Clutch
collar
2.
h.
Reluctance-pickup
Clutch-reset
With
S64960-2
pivot
3.
(Figure
Using
the feed
4.
breaker
Using
3.5-l
blade
clearance
and front
strobe
output
card
contact-arm
4.5-l),
S15821-32
grease,
trip-
trip-arm/clutch-
(Section
and slide
to left
circuit
duration;
breaker
the feed-roll
pivots
the clutch
4.5-l).
9-23
timing
4.4-l),
tip
(Section
roll
(Figures
the clutch
actuator
the feed
and the circuit
repack
pickup
arm pivots
(Figure
lubricate
3.7).
3.8).
), and the stacker-switch
cams (Figure
3.3).
3.4).
actuated
guide,
pulse
(Section
lubricate
grease,
3.2).
3.5).
arm position
Sl5821-39
(Section
clearance;
spot
(Section
(Section
disengaged
(Section
and feed-test
oil,
clearance
clearance
trip-arm
light
3.6).
and orientation
i.
Technical
pivot
clearance;
block
clearance;
card deck
Stacker-stop-actuator
the circuit
throat
overlap
(Section
and feed-roller
plate
to insulation
core
ridge
g.
protrusion
clearance
to read-bed
to actuated
Gap between
gib clearance
Reader
lubricants.
to card-column-80
latching
Card
3.1).
hopper
arm to rear solenoid
f.
roller
lamp bracket
registration;
collar
Burroughs
are in Burroughs
adjustments:
Top and bottom
arm spring
below
shaft
shaft
breaker
housing
(Figure
3.9).
4.3-l
trip-arm
3.7-l).
gears (Figure
cams (Figure
and spring
,2),
4.3-3),
4.4-l).
(Section
5.
Using
S15821-26
6.
Check
lubricate
the following
ing noise under
Section
oil,
rotation;
a.
Feed-rol
ler shaft
b.
Cam-fol
lower
c.
Pulley
bearings
d.
Clutch
shaft
e.
Card-feed
PDP-6
is constructed
during
the
first
of
year
period
approaching
system
malfunctioning
manifest.
Diagnosis
with
tion
and flow
charts
solid
on logical
and manuals,
the contents
system
frustration.
thinking,
the
possibility
all
a broad
is complete,
sense,
staff
should
its documentation
This section
common
of failure
The maintenance
and
it outlines
diagnosis
instead
portrayed.
allowing
remote.
the
instead
and
contains
plan
no fault
of attack
proper
remedial
secure
knowledge
-
for
action
is
of the
procedure.
the prints;
are generally
modules,
with
guarantees
step-by-step
right)
state
is exceedingly
When
section
MAINTENANCE
familiarity
are cross-referenced
in the lower
with
reliable,
installation
depends
to the DEC prints
Familiarity
of
bearings
CORRECTIVE
hardware.
the logic
number
using the procedures
bear-
assembly)
shaft
remedies;
mnemonic
drawings
bearings
by excessive
bearings
specific
to memorize
Logic
as evidenced
bearings
in ignorance
Do not attempt
drawings
worn
(at the clutch
total
and an organized
with
replace
bearings.
rol I bearings
highly
to acquire
isolating
system,
for wear
actuator-arm
after
the system
classification
bearings
motor
4.
9.4
use this
the drive
concentrate
When
sufficient
there
system
logic
reference
to the manual
recourse
on associating
avoids
tion.
9-24
number
(it appears
time
manuals
wasted
troubleshooting.
with
difficulty.
for the in-out
in futile
number
the logic
during
in cases of extreme
are manufacturer‘s
of these manuals
understood,
documentation
by section
to the text
is well
the drawing
searches
the figure
In addidevices.
for informa-
When
confronting
a malfunction
the following
in the machine,
plan
of attack
should
be
employed:
Initial
investigation:
2.
Preliminary
3.
Console
check:
marginal
particular
section
4.
troubleshooting:
within
use pertinent
check
Remedial
6.
Validation
7.
Log report:
procedures,
module,
make
ensure
a complete
sis is expected
to suggest
a remedy
such situations
are treated
in b.
Before
commencing
Ascertain
fault
all
and all
conditions
whether
the diagnostic
troubleshooting
Investigation
within
information
symptoms
the present
evident
by console
fault
that
proper
record
(step 5),
The final
physical
programs,
symptoms.
maintenance
the problem
by isolating
modules
of diagnosis,
includes
within
a
the malfunction
or a similar
the first
and validation.
four steps above.
may require
attendant
The diagnoprocedures;
in c .
Troubleshooting
to explain
is discussed
concerning
how faults
in PDP-6
explore
every
any unusual
the fault
indicators,
is restored.
remedy,
two steps are discussed
procedures,
when
system function
but the remedy
procedure
troubleshooting
possible
reflected
problem.
or control.
in a below,
a
Initial
obvious
to localize
the diagnosis
supply,
of remedy:
is discussed
modules;
diagnostic
on the
action.
which
details
presents
etc.,
complete
Troubleshooting,
This section
information
of the logic.
a particular
5.
all available
see if the malfunction
troubleshooting:
controls,
Logic
gather
occurred,
etc.
Search
one has occurred
9-25
may be isolated
Circuits.
possible
function
source
of information.
of the machine
such as the type
the maintenance
before
to individual
or whether
of program
prior
to the
in progress,
log to determine
any cyclic
history
of
related
malfunction
the PM voltage
check.
exists,
charts
to determine
for any steadily
If a deteriorating
diagnosis
module
may be simplified.
he can make a diagnosis.
ploring
every
available
with
logic
cables,
the condition
connectors,
of all
filters
is useful
for cable
and module
or faulty
circuit
or three
modules
modules;
malfunction
Examine
marginal
to the present
can gather,
trouble,
the more
first
ex-
time.
often
Intermittents
discloses
(Section
a clogged
troubles
provide
filter
than
with
voltages.
ones.
Except
joints
to within
to start checking
otherwise
of a simple
the
considerable
power
two
arbitrary
Nevertheless,
require
Check
This preliminary
certainty
must be used.
the discovery
troubleshooting
of power
are due to cold-soldered
is isolated
large
the temperature
to fail.
it is poor strategy
than
proper
for intermittent
failures
would
security
may allow
semiconductors
which
If a very
supply
diagnosfailure
procedures.
ina
a small
(with
to relatively
supplies
procedures
are more annoying
the location
caused
and electrical
the malfunction
troubleshooting
time-consuming
the physical
most intermittent
investigation,
within
the MAlNDECs
vestigation.
under
of malfunction.
malfunctions
by the initial
In many cases the initial
MAINDEC
regions
symptoms
marginal
Unless
Troubleshoot
pinpoint
to cause
connections,
Few things
complex,
of air;
components.
check
tic work.
flow
for catastrophic
more sophisticated
preliminary
formed
corrected.
the system without
just wastes
Be sure that power
for free
more often
inspect
etc.
check
itself
to troubleshoot
usually
were
related
the technician
for physical
is inoperative,
a bay to rise sufficiently
Console
voltage
seemingly
information
of information
a check
within
after
operating
failures
Attempting
source
begins
of system
sources,
produces
past conditions
Check
Troubleshooting
portion
narrowing
The more
rapidly
Preliminary
how similar
investigation
Troubleshooting
section
logic,
consistent
of machine
marginal
by weakened
Intermittent
an appropriate
of a malfunction.
or without
9.2),
discloses
checking,
components
malfunctions
selected
connections,
and
line
is usually
9-26
checking
derived
are substantially
with
from
localizes
a
by use of
of the malfunction).
be aggravated
by use of marginal
however,
accompanied
on the nature
always
on the basis of information
but does not in
from the console
depending
can almost
of attack,
and thus transan appropriate
the initial
more difficult
in-
to locate.
If the malfunction
does not show up in the first
which
the trouble
was initially
faults
frequently
the entirely
first.
give
solid
Faulty
observed,
indications
state
ground
to those caused
is inherently
connections
margins,
perform
using the same user program.
similar
processor
run without
between
periphery
In-out
by processor
more reliable,
check
the operation
equipment
malfunctions.
Since
the peripheral
and processor
in
are common
equipment
sources
of
trouble.
If a malfunction
detected
charts.
Console
run with
show up at narrower
the computer;
through
among
the errors.
malfunctions
intersect
procedures
display
at a common
Troubleshooting
Logic
troubleshooting
has been
troubleshooting
technique
to reproduce
by repeating
the program
useful
to try aggravation
In general
a diagnostic
form some operation
by having
design
that
performed
check,
do
or those made
a pattern
be necessary
produce;
on the PM vol-
the trouble.
discovering
techniques
halt.
on a small
has been
the malfunction
separate
error
con-
of consistency
to discover
it,
diagnoses
a diagnostic
string
it
all
must
is
executed
loop and toggle
that
usually
is encountered.
parts of
A common
at times it may
occurred,
fault
e.g.,
it may be
run.
causes
correctly,
it in from the console,
9-27
first
For an intermittent
is executed
a malfunction
though
the failure
loop is being
a malfunc-
the source.
loops,
correctly;
after
The two main
to identify
which
of instructions
If the operation
runs until
under
at the time.
while
of the logic
identified.
and then
conditions
is a small
that
section
is the use of diagnostic
was running
and checks
his own diagnostic
toward
be
in loading
of marginal
malfunctions,
may sometimes
the source
the exact
the computer
application
catastrophic
they
by differences
in the last few plots
to diagnose
be directed
malfunctions
loop
the computer
in this manner
work
are to reproduce
be necessary
listings
in the errors
but before
for reproducing
during
it can generally
point.
is detail
detected
the error
some ingenuity
fault
caused
listed
for locating
consistency
to a user program,
those
halt
should
Although
unique
Malfunctions
than
discovers
use of margins,
Logic
margins.
use the error
troubleshooting
sistent
conditions
margins
If the MAINDEC
not restart
tion
by loading
by a MAINDEC
conditions
tage
is caused
the computer
the error
is indicated
the program
The technician
but it is usually
to per-
starts over;
may
easier
to modify
the maintenance
MAINDEC
more than
ten instructions.
routines
seldom
an error
by using JRST 4 with
Any routine
halt
with
is intended
involves
either
checking
to twist
are designed
the factory,
usually
appears
modules.
modules
with
Three common
Substitution
Whenever
bits.
rather
Regardless
location
-
place
Panel
may be used to detect
Using
than
has not moved,
ule in a specific
indicators
module
substituting
a’ spare,
location,
the trouble
of the outcome
it is a desirable
in a shift-count.
after
than within
suspect
implement.
the source and correct
and signal
a malfunction
e.g.,
it.
tracing.
is thereby
swap counter
cured.
or
is in the ei<changed
to be elsewhere,
of the swap the good
maintenance
leaving
soldered
by tapping
the trouble
is likely
practice
probably
module
in
should
to keep each
mod-
in the system.
malfunctions
by following
REPEAT or REPEAT BYPASS and the SPEED controls,
speed by pausing
located
indicators,
to see whether
before
Poorly
connections
such harmless
panel
to
shows up; this type of fault
step is to identify
observing
be impervious
systems are tested
or cable
not hesitate
in the system
to locate.
or other
the next
should
should
occasionally
panel
moves to the new
feeds the module,
to its original
PDP-6
by
As long as reasonable
All connections
of this type are occasionally
a suspect
If the malfunction
that
the
The tech-
detection
personnel
or sockets
Although
of a screwdriver
swap modules
the logic
cables,
in mounting
toappear
replacing
If the malfunction
on
following
ones.
component
maintenance
connection
are substitution,
module.
be returned
soldered
can be reproduced,
is simply
the processor
of the next routine.
above).
and issometimesverydifficult
handle
techniques
possible,
so plugs,
malfunctions
the plastic
the malfunction
register
a poorly
hidden
diagnostic
the instruction
(weak
plugs or modules.
or flexing.
as an intermittent
Well
loaction
described
damage,
cables,
of pulling
are more likely
halts
to catastrophic
or vibration
troubleshooting
reliability;
nevertheless,
connections
Once
amount
to the first
malfunctions
voltages
permanent
at connections,
for excellent
any reasonable
check
inflicting
of small
Each routine
loop by replacing
intermittent
is part of console
and probe
pointing
entirely
of the routine.
fo convert
marginal
is used to avoid
601 consists
into a diagnostic
a iump to the beginning
marginal
care
the address
may be converted
Aggravation
nique
containing
program.
each
A complete
instruction,
discussion
memory
of single
9-28
access,
machine
a program
AR subroutine,
step operation
state
changes.
loop can be run at slow
or even
is presented
every
in 9.15
step
Repetitive
memory
examine
ting
or deposit
pulse.
All pulses
on the logic
logic
halt
for it.)
when
the skip with
so an effort
located
that
should
memory
ions.
location
validation
thus that
It is difficult
be made to change
When
that
a iump to itself,
contains
has been
to ensure
the malfunction
that
b
Once
a malfunctioning
stitution,
as intensive
submodular
for repair
module
or replacement;
given
in PDP-6
pared
to replace
has been
system scheduling
troubleshooting.
Circuits.
the old:
It is expected
those who wish
When
faults
replacing
loop,
that
the exercise
loop keep
should
gen-
an appropriate
are shown
the source
loop should
into an exercise
using signal
not
loop,
tracing,
ones which
it simple
by starting
or by repeating
synchronize
indicating
into catastrophic
can be
and use a minimum
the processor
at a
key functions.
corrected,
or component
cured
on the repeti-
pin locations
intermittents
and is presumably
the module
all
loop
loop can be obtained
isolated
was actually
a diagnostic
an exercise
a simple
pins;
on the scope,
intermittent
For example,
by set-
instruction
for selecting
by a mnemonic
to pinpoint
constructing
information
helpful
output
is prefixed
(to change
A single
in an exercise
are very
at module
name
key.
time pulses or to a pulse
charts
may be viewed
occurs
a iump).
the malfunction
during
events
an error
far more easily.
of instruct
signal
an
may be repeated
Complete
running
sequence
are available
by repeating
in 5.1.
the machine
(The flow
and every
In order
the machine
replace
Once
and levels
instruction
the EXECUTE
paragraph
to one of the main
drawings,
A single
START or READ IN.
With
pulse or event.
using any instructions
REPEAT with
in the final
a scope.
sweep
the suspect
by using
is given
requires
the oscilloscope
erate
and using
can be repeated
tracing
without
from the console.
switches
of key functions
Signal
can be produced
operation
it in the DATA
in memory
tion
access
replaced
be particularly
was reaIly.at
careful
fault,
and
by the replacement.
Repair
located,
repair
requirements
should
preclude
that defective
to undertake
a module,
in some cases adjustments
must be made or broken.
9-29
be made
immediately
by sub-
use of the processor
to aid in
modules
module
make
will
repair
be returned
may refer
to DEC
to procedures
sure the new one is properly
must be made
or internal
connections
pre-
Internal
Most
Connections
inverter,
jumpering
shipped
diode,
to connect
with
any given
all
modules
have
jumpers
to select
jumpers
the type
loads connected;
jumpers
for other
the delay
of module.
to the module
as they appear
on the UML
these codes are explained
upon
the type
with
in
cutters).
Some
wire
decoders,
and some delay
lines require
etc.,
must be cut or soldered
jumpers
see Appendix
and the way
have
selection
in depends
1) give
may be used.
are
for insertion
some flip-flops,
of module
in the circuit
module
(e.g.,
lists (UML,
in which
for internal
These modules
collectors.
jumpers
module
for modules
depend
pins,
Whether
have provision
a replacement
for example
duration.
locations
inverter
must be disconnected
The utilization
in all
modules
to prepare
purposes;
the connections
configurations
are used;
loads at the output
the unused
of the tap to choose
upon
clamped
clamped
location
and decoder
capacitor-diode,
the jumper
The jumper
in which
codes
the jumpers
manual.
De lays
Most delay
are,
modules
however,
three
these modules
contain
types of adjustable
is replaced,
The 1304 and 4301
distributed-constant
the new module
may be adjusted
Set up an exercise
2.
delays,
pin J of the module
that cannot
be adjusted.
1304,
4301,
and 4303.
Whenever
must be adjusted
repeatedly
to observe
(-3
lines
to give
the correct
There
one of
time
interval.
as follows:
loop that
Set up an oscilloscope
delay
volts
during
triggers
the duration
the delay
the delay.
of the level
interval,
output
ground
at
other-
wise).
3.
Set the scope sweep
centimeter
sweep
The output
is adjusted
trimpot
The 4303
to observe
accessible
has flip-flop
the negative
that
to the calibrated
displays
to the required
through
type outputs.
output,
the entire
a hole
position,
and select
a per-
duration
of the level
output.
duration
by means of a screwdriver
in the rear of the module
Use the above
method
or at pin U to observe
9-30
frame.
but connect
the ground
output.
the scope at pin W
The delays
for
power
clear
ment at all;
The 4303
motor
the delay
period
in the repeat
one of five
varies
and punch
external
logic
charge
Tape Reader
.
When
any reader
hour PM checkout
required
Card
card adjustment
(the smallest
for the selected
circuit
should
not exceed
by means of the speed controls:
or none at all
current
memory
may not need adjust-
card
having
the selector
is internal);
chooses
the potentiometer
capacitor.
a trimpot
subordinate
100 psec.
adjustment,
This action
to it).
but also serves as a validation
perform
not only
procedure
the entire
provides
lOOO-
for the
for the repair.
Reader
Replacing
any photoamplifier
the exciter
3.16
involves
an adjustment
assembly;
package
lamp brilliance
Sections
and 3.17
of the card reader
requires
calibration
procedures
procedures
replacement
to ensure
affected
correction
of the fault
by the replacement.
most applicable
is made
diagnostic
to that
(MAINDEC)
devised
to ensure
tenance
task be performed
detection
reveal
of the fault.
available,
proper
of faults
a failure
not normally
that
operation.
normally
mechanism,
If the entire
during
preventive
manual
should
tests should
be followed
by
operational
that
elsewhere,
that
can be performed
while
for the whole
9-31
PM interval.
levels
of the PM procedure
If repair
maintenance,
by the just-corrected
extant
be performed
or signal
occurred.
the entire
system component.
masked
that
as part of the re-
adjustments
the fault
suggested
still
part
performance
It is strongly
PM procedure
it need not be scheduled
requires
or an alternate
been
perhaps
up final
in which
for the malfunctioning
may have
of any mechanical
in the system,
be run,
should
of
Log Entry
and to trim
checked
of
3.
and
of the system
readjustment
using the procedures
procedure
4 in the reader
component
Validation
portion
in an area
program
Validation
condition
complete
Replacement
of the adjustment
Section
of any electrical
requires
pulse coincidence,
of Section
from
reader
manual.
performance
-c
Following
in the card
and of the strobe
the replacement
appropriate
ment
a nonexistent
isadjusted
(and all checks
so the replacement
are not critical,
for detecting
capacitors
the available
replacing
turnoff
the appropriate
test should
be
preventive
main-
This action
ensures
malfunction
is likely
or replace-
and may
to cause
the equipment
recurrence
is down and
Corrective
maintenance
maintenance
detection,
Suggest
log.
Include
the component
improvements
diagnostic
activities
procedures
nation
of the log will
time
at fault,
indicating
by recording
symptoms
a real
they are recorded
given
they should
part of the initial
everything.
9-32 nevertheless
investigation
in future
and detailed
important.
in
the method
be helpful
A complete
dog is particularly
in detail
by the fault,
that might
if indicated.
and obvious,
be a maior
until
and any comments
used to locate
may seem insignificant
down
all data
in PM procedures
details
Reduce
are not complete
of fault
diagnosis.
write-up
Although
be included
for a future
the
of
some
since exami-
malfunction.
APPENDIX
1
ENGINEERING
Reduced
copies
explains
the drawing
ponents
of engineering
numbers
in a PDP-6
and flow
charts,
which
are many other
given
system component,
ing the size letter;
fied;
drawings
drawing
drawing
which
by title,
for the entire
lists the module
in Appendix
The 166 MDL
lists first
tion about
representing
by logical
For example,
14 to 23.
the plug-in
occupying
(flip-flops,
function,
a pulse amplifier
by the output
serial
drawing
speci-
drawings
are
number.
with
number.
list ML;
Each MDL
letter,
no individual
draw-
lists all drawings
and number
in this instance
for all system components
that make up the processor
circuits
as the type
of sheets.
The
the system module
(this drawing
is dis-
2).
code for the module
to the individual
gate,
requirements
by “6”
follow-
these are also A size and identified
revision
system is a module
there are ten, numbered
and jumper
code,
For a
component
and individual
the drawing
the SD, FDs, and BSs that accompany
the modules
25 sections
identified
by the code,
serial
However,
are D size unless otherwise
system is an A-6
and drawing
schematics
in maintenance.
of that
4
for all com-
the equipment.
for reference
mentioned
Chapter
used in the block
system are identified
code that follows
number,
drawings
has the type number
to the entire
for the entire
type number
cussed further
into
used primarily
It I ists the MDLs for al I system components;
other
of which
engineering
and conventions
all drawings
or mnemonic
2 of this manual.
and maintaining
number
that apply
list (MDL)
by the equipment
list SML,
identify
in each case is identified
for the system component
only
drawing
discussion
in Volume
the notation
drawings
every
by the number
ing number.
only
engineering
the type of drawing
The master
and type codes that
are the basis for learning
In the following
specified
are included
system and details
there
number.
drawings
DRAWINGS
is shown
Each UML
locations.
it.
this manual.
in the utilization
shows three
Above
each
Each location
inverters)
using the same signal
names that
is labeled
the output
of the net in which
it is used.
Al -1
mounting
location
is further
pulse amplifiers,
by naming
Detailed
module
lists UML,
panels,
each divided
is the type
partitioned
in the module.
appear
pulse;
informa-
according
Circuits
on the block
an inverter
number
are
schematics.
or diode
Of
the various
memory
cable
diagrams,
busses is included
associated
with
is CONS,
on the console.
switches
and the connections
power
on but disrupts
NO
Note
CBL-2
on the console
and CBL-3
and its many branches.
onto
show all
of logic
levels
the 60-cycle
console
disabling
relationship
the switch
and
is closely
keys and
from the keys and
signal
switch
to the normal
case for physical
for the
holds system
Note
the keys and switches.
levels
from the logic
panels.
also that
position
the
of
identification
CBL-1
to indicators
to module
connector
number
of cable
pins and identify
and switch
shows the locations
the four bays; CH shows the configuration
There are also a large
made from cables
cable
molded
CD that
to all operating
including
bear no invariant
and on the bay indicator
plugs and iacks throughout
tions
control
that enables
the labels
Another
on the in-out
ions.
of drawings
registers
power
signals
shows the connections
of the key-locked
contacts
these are merely
of connect
A pair
on switch
7-10).
shows the generation
how the on position
and NC labels
the switch;
which
Figure
to the main power
the console
shows the logical
(IOMB,
This drawing
switches
flag.
the one that
in the manual
the logic
clock
CD,
of all
of the main cable
lists CL that
the signals
harness
show the connec-
carried
on the various
I ines .
All connections
WD.
made among
Each drawing
the module
shows three
of the complexity
of the wiring
ings,
for example
one showing
puts (there
are also other
Power wiring
controls
one were
all ac connections
drawing
plenum
mounted
mounting
50ACPW
and is identified
in the processor,
the grounds
are shown
each
and pulses,
the other
ACPW and DCPW.
of the rear plenum
right
the mounting
is substituted).
through
may use during
the termina
I strips.
panels
letters.
diagrams
Because
is shown in two draw-
the levels
and flip-flops
controls
out-
circuit
maintenance.
All wiring
is color
switches
have three
right
positions
+lO red,
Al -2
-15
blue,
line
including
ground
i .e.,
ACPW
with
the
to a display
an override
from the supplies
black.
shows
50 cycles,
is associated
in the high-voltage
DCPW shows all of the dc wiring
coded
side.
using 240 volts,
in the lower
of power
from the front,
from the wiring
and fans (for machines
The interlock
The interlock
Each shows the location
doors viewed
panels
doors in bays 3 and 4 and may be used for example
technician
by the panel
set of three
on the inside
from the power
in the console.
in a series of wiring
combinations).
supplies
looking
pins
panels
is shown in the PW drawings,
and power
as though
connector
As shown
the
to
in
the lower
color
left,
all
terminal
code as the wiring;
the terminals
to them use the standard
a power
connector
in the right
mounting
horizontally
block
voltages
for each
are the connections
This bus carries
the -1%volt
connections
from
processor
units
included
cable
Burroughs
turnon
the controls
H-l 182627
H-l
.
block
designations
on the marginal-check
H-l
1900107,
components,
all
inputs
to the drawing
between
are numbered
signal
name,
be included
giving
All
input
signals
the bottom
between
the destination
boxes are eight
the pin connections
the top and bottom
of the signal
of input
units,
lines;
horizontal
UML,
WD,
rows.
Output
at the
there
control
and various
other
are a number
of
drawings
1877446,
H-l
and
logic;
1877453,
the others
and give
and part
all
are shown
of which
point
out on a rectangular
at the left,
information
of two wires
coordinate
all outputs
rows are identified
and row.
are computer-
pin numbers
at an intersection
by page
supply
the in-out
two rows of information,
its source
shows the
sys-
at the right.
by a letter
and a num-
the top row giving
Supplementary
is identified
data
and
wide.
in all
The first
two positions
but the bottom
Al-3
row,
in the same way,
are used exclusively
the final
the
may
by page and row.
positions
lines,
a “0”
power
about
and connectors,
column
MCLT,
These include
flow
is laid
by at least
row indicating
character
show signal
at the site and
manual.
for the reader
in the input
are identified
H-l
bus.
are at the right.
For the card reader
The information
and all
equipment
diagram,
has its own
1900115,
by dashed
and the marginal-check
information
reader
and negative
In the upper
to the variable
meter
device
plug-in
are indicated
tem,
All
H-l
These schematics
connection.
ber.
each
are lists of equations
a common
The columns
time
in the card
represents
with
to the elapsed
horizontai
at one end of every
identically).
A wiring
bay is
left and right.
the positive
to other
panel
not included
The last three
Wires
checking
MDL.
182640,
of electrical
panel
for the memories.
However,
carry
connected
for each
The smaller
located
coded
control
in the appropriate
schematics.
by rectangles.
are color
such as the PWs, also present
schematics
to H-l
1877461
printed
drawings,
and
and wires
for marginal
signal
Connections
as listed
logic
terminals
(the wires
voltages
of representations
are shown at the lower
vertical
use the same
but the wires
up the sides of the bays.
bay are actually
check
in this manual.
drawings
halfway
are different
the pair
and wiring
to the marginal-check
rear of the same bay.
Many
layout
and yellow
the variable
also carries
on the 778 Supply
about
for marginal
on the 728 and 734 Supplies
The strip between
whose
panel .’ The green
variable
right
coding.
bracket,
These are mounted
strips
strips and the terminals
two positions
for
are
used for pin connections
and the bottom
system
row gives
in the form
5 and that
socket.
tion
AAB5L6,
which
symbol
unit,
appears
can be used to find
in Table
The majority
2.5-l.
and are wired
to form
;
stick
into
panel
designation
switch,
are diode
sticks
the part
stick,
the locaa plug-
its location
are not described,
or
in Burroughs
be deduced,
of the part can be found
which
6 of the
If the box represents
or diode
unit
row B, posi-
are given
cannot
the part.
and description
A,
row L, column
some of the part designations
the
of a plug-in
of the words describing
with
3
4
also
in Chapter
but are all
in the drawings
diode
gates:
or B follows
by NC).
the remaining
the circuit
5
6.
identical
6
l-l
V
the top,
the D.
required
rows may contain
is used in.
by 0 followed
indicates
are sent uncut,
for any given
other
For a diode
information.
stick,
1 and 6 and the gates associated
Al -4
J
W
by a letter
or bottom
center,
A number
Replacements
the configurations
at positions
2
C
R
is designated
is indicated
of the logic
resistors
letters
of the part
1
“,
two or three
to conform
nections,
plugs
A,
explains
7
the box if a T, C,
(no cut
the others)
’
PIN
The location
is in rack
the initial
manual
designation,
as follows:
0
A diode
parts.
box is a part
reader
the unit
low-speed
A schematic
units
electrical
than
of each
of the card
and thus identify
amplifier,
of the plug-in
CUT
is usually
the meaning
such as a photo
2.2
means that
such as K for relay;
and wherever
designation
gable
of all
its key pin (the one larger
some standard
2.5,
Section
the locations
The part designation
Section
At the top center
lines.
the location.
used to designate
is given
tion
of output
part
or number.
of the stick
the position
and the technician
location.
It may be cut
is represented
by
must cut them
In addition
Row 2 often
them:
L
Y
of the cut or cuts made
rows 3 and 6 give
with
K
x
to pin con-
indicates
information
an R in position
the part
about
the
3 indicates
that
the resistor
used in the gate;
Information
is tied
A or 0
contained
box representing
to -12
in position
in other
a relay,
volts;
NO
a numeral
5 or 6 indicates
rows depends
or NC
in position
4 indicates
the use of the gate as logical
upon the element
in row 5 indicates
Al-5
the number
normally
represented;
of diodes
AND
for example
open or normally
closed.
or OR.
in a
APPENDIX
2
SPARES
For a large-scale
than
system such as PDP-6,
the cost of maintaining
the quantities
a fully
of all modules,
memories,
systems may differ
considerably
vice
user with
supplies
quantity
Field
each
and number
Service
stock
that
control
in quantity
a list geared
also supplies
moderate
stock
and power
units)
miscellaneous
Quantity
to his particular
for every
so DEC Field
needed
in-out
supply,
the total
and power
for repair
Ser-
control.
of DEC mod-
devices.
It is further
and keyboard-printer,
and
toggle
6ATl
Micro
Switch
1575-L
Arrow
Hart
Rotron
Mfg.
Co.
Rotron
Mfg.
Co.
Rotron
fan
53E168
2
Rotron
filter
34-x1
DPDT
Vendor
Switchcraft
2
fan
individual
Telever Switch
16006 Cat. No. S-302
Reworked
per DEC
510
drawing
MA-C-01
Lockout
Howard
However,
This list gives
power
tape punch,
1
1
module,
spares for the various
Subminiature
switch SPDT
lamp
system.
components
5
Indicator
in PDP-6.
system components
Part Number
key
10
used in all
list SML 1ists
items for the system.
for bat-handle
switch
far more expensive
The system module
and type of system components,
Item
Switch
is generally
controls
available
spares lists of electrical
and mechanical
downtime
of spares.
the user keep a spare tape reader,
the following
1
in-out
supplies
of spares recommended
ules and lists of electrical
recommended
adequate
power
( i.e . , processors,
even
Type CFG
431
MC4806390
Transistor
12-80-l
Howard
A2-1
5
Inc.
Electric
Industries
APPENDIX
3
GLOSSARY
It is not intended
the flow
gives
charts
that
when
the meanings
and the four
use of this glossary
following
of all
in-out
the meanings
for logical
functions
each prefix
code
applies.
code
be substituted
of events
codes and all
Only
and their
signal
these are listed
and all
below
inputs
are listed
to the logic
because
quite
No generating
conditions
A (5-3) Address
AC Accumulator.
AC0 Accumulator
whose
AC2 Accumulator
following
of the figures
to anyone
are given
flags
are discussed
the numbers
all
obvious
The processor
from the console
in parentheses
names for the processor
are usually
charts.
4 or for using
This glossary
names are included
meanings
in the flow
Chapter
drawings.
terms used in the signal
a few complete
terms,
for reading
in the logic
of the terms and has read 4.2.
because
in 2.12,
With
prefix
of standard
who knows
and described
any sequence
devices.
names are composites
shall
are I isted
in 3.la.
to which
cycle.
address
is 0.
the one addressed
by an instruction.
AC BM (5-9) Accumulator
compare
bit modify;
instructions,
AC as specified
(5-9) Accumulator
metic
compare
AC with
A3-1
either
which
test bits of
by a mask (either
C(E)) and may modify
ACCP
the logical
compare,
the masked
i .e.,
instructions
E or C(E).
E or
bits.
those ariththat compare
the
ACCP
ET AL TEST
ACCP
ACCP
ETC COND
condition
ETC COND is the skip or iump
as specified
ACBM,
ACCP,
by bits 7 and 8 in
or MEMAC.
of the instruction code
the skip or iump
specifies
is to be made on the
of the condition
specified
by bits 7 and 8, the condition
is exclusive
ACCP
ORed with
ET AL TEST,
sensed by the program
ACK
Acknowledge,
ADDR
Address.
A LONG
Flip-flop
AOBJP
Add one to both and jump
AOBJN
Add one to both and
logic,
AR COM
CONT
register
special
AR complement
beginning
plemented
menting
are
of an address.
if positive.
subroutines,
flip-flop;
of subtraction
that
control
and flags.
set at the
or decrementing
result
must be com-
the addition
or incre-
used.
AR CRY COMP
AR carry
complete.
AR CRY0
Flip-flop
set by any carry
A3-2
logic.
and associated
control
following
is
iump if negative.
inputs,
in AR to indicate
which
any operations
in the calculation
Arithmetic
IR6 to
control
set whenever
performed
10) whether
or absence
generate
5, 6, 7, 8, 9,
bit 6
presence
signal
AR (6-4,
Since
out of ARO.
AR CRY1
Flip-flop
AR = FP HALF
Level
set by any carry
asserted
when
AR as a floating-point
tude
AR OV
SET
out of AR1 .
the fractional
number
part
of
is of magni-
l/2.
Condition
that
determines
overflow
in AS
or MEMAC.
Level
AR SBR
that
causes
the execute
cycle
to pause
at ET4 for an AR subroutine.
AS (5-l 0)
Add-subtract
e
ASH
Arithmetic
shift.
ASHC
Arithmetic
shift
B
Binary;
BLK
Block.
BLKI
Block
in.
BLKO
Block
out.
BLT (6-18)
Block
transfer.
BLT DONE
Level
that
terminates
permanently
because
buffered
or temporarily
BLT LAST
Inhibits
combined.
.
(5-10)
Boolean
A3-3
the block
to handle
AC storage
is complete.
BOOLE
a block
instructions.
when
transfer
is complete
an interrupt.
block
either
transfer
Mode
BOTH
in which
result
is deposited
in both
AC and memory.
CA0
Character
add one (= IBP).
CBHL
Leve I to the card reader
the upper
output
half
causing
of a binary
it to place
column
on the
lines.
Contents
of b
Contents
of location
specified
by effective
address .
CFAC
Computer
(6-17)
floating-arithmetic
(subroutine
CH (6-19,
20)
interface).
As a prefix,
character
manipulation);
CHG
Change.
CH INC
These three
CH INC
CH %INC
OP
OP
levels
asserted
during
struction
that
pointer.
exclusive
struction
the first
calls
between
A3-4
CH INC
is
part of any in-
two
levels
part
CH INC
of the pointer;
the two parts.
OP causes
because
OP
the in-
it or the first
character
following
of a
CH %lNC
either
does not require
the
are mutu-
the first
incrementing
repeated
part
for incrementing
within
of an incrementing
being
(byte
the first
operation.
operation.
incrementing
inhibits
control
The other
character
operations
also channel.
in a character
ally
connection
operation
a priority
part
is
interrupt
CL
Clear.
CLK
Clock.
CLR
Clear,
CMC
Core
memory
signals
control;
from memory
prefix
(core
for control
or fast) over
the bus.
COM
Complement.
COMP
Complete
CONI
Conditions
in.
CON0
Conditions
out b
CONS0
Conditions
in and skip if one.
CONSZ
Conditions
in and skip if zero.
CONT
Control;
CPA (8-5)
Processor
face
a
continue.
I/O
interface.
at the other
control;
through
control
This is the inter-
end of the bus from
it the processor,
and the bus,
controls
via
itself
IOT
IOT
as a
device.
CR (8-13,
CRE L
14,
15)
Card
Signal
reader.
from the card reader
a validity
CRL
Signal
or read check
A3-5
indicates
error.
from the card reader
it is not ready
that
for operation.
that
indicates
CRY
Carry.
CYC
Cyclel
DATAI
Data
in.
DATA0
Data
out.
DC (6-20)
Deposit
DCA
DC adder.
DEP
Deposit
DIR
Direct,
DIV
Divide.
DN
Do nothing.
DPC
Deposit
DPCI
Index
DS (6-25,
E (5-5)
26)
character.
l
C(E) rather
i .e.,
character
pointer
Divide
than E.
(= DPB).
and deposit
character
(= IDPB).
subroutine.
As a prefix,
execute
cycle;
also effective
processor
to use second
address.
E LONG
Level
half
that
of execute
EOF
End of file.
EX (5-13)
As a prefix,
EXCH
Exchange
A3-6
causes
cycle.
executive
0
mode;
also examine.
EXEC
Execute,
F (5-4)
As a prefix,
FA (6-22)
Floating
add.
FAD
Floating
add.
FC (C (AC LT))
Fetch
fetch
the contents
by the number
Fetch
FC(C(ACRT))
the contents
ocat ion addressed
of the
oca t ion addressed
in ACRT.
FD (6-22)
Floating
divide.
FDV
Floating
divide,
Floating
exponent.
FM (6-22)
Floating
multiply.
FMC
Fast memory
FMP
Floating
FP (6-23)
As a prefix,
15)
of the
also flip-flop.
in AC LT.
by the number
FE (6-14,
cycle;
control,
multiply.
floating-point
late subroutine;
exponent
also floating-point
calcuinstruc-
tions.
FP/CH
IR decoder
structions
output
and character
FS (6-l 9)
Floating
scale.
FSC
Floating
scale.
A3-7
for the floating-point
operations.
in-
FSB
Floating
FWT (5-9)
Fu I I -word
HWT (5-9)
Ha If-word
transfer.
I (5-3)
Instruction
cycle.
ILL
Illegal
ILLEG
Illegal0
INC
Increment
INH
Inhibit.
INST
Instruct ion e
INT
Interrupt
IO
In-Out.
IOB (801,2)
In-out
line
subtract.
transfer,
l
b
a
bus; IOBi
(5-7)
In-out
select.
IOT
(8-T)
In-out
transfer.
IR decoder
UUO
IR (5-7,
8)
output
for IOT
(replaced
by a
in user mode).
Instruction
register
and associated
nets.
JFCL
Jump
JP (5-10)
Jump and pushdown.
A3-a
. . ., 35) is data
i on the bus.
10s
IOT A
(i = 0,
on flag
and clear.
decoding
JRA
Jump and restore
JRST
Jump
JRST A IR decoder
accumulator.
and restore.
UUO
output
for JRST (replaced
in user mode
if a halt or PI dismiss).
JSA Jump and save accumulator.
JSP Jump and save program
JSR Jump to subroutine.
K (5-2) Key cycle
KEY (5-1,
2) KEY MANUAL by a
counter.
l
Key. Level
generated
when
any initiating
key is pressed. LC (6-20) Load character. LDC Load character
LDCI Increment
LSB Least significant
LSH Logical
shift. LSHC Logical
shift
LT Left MA
MAI
(7-1,
(7-2)
2, 3)
(= LDP). pointer
and load character
bit. combined
l
Memory
address V
Memory
address
A34
L
interface.
(= ILDP). MAJ
Majority
gate,
MARK
Teletype
signal
MAS
Address
switch.
MA SW
Address
switch.
MB (6-1, 2, 3, 4; 7-6)
Memory
buffer
special
inputs,
representing
a 1.
and associated
and data
control
interface
logic,
with
mem-
ory bus.
MC (7-8, 9)
Memory
MD
Multiply-divide.
MEM
Memory;
control
0
as a mode,
result
is stored
only
in E.
MEMAC
(5-10) Memory
and accumulator
test instructions;
for a jump,
AC,
modification
AC against
these test
or test C(E) against
Memory
(7-7) MISC
zero for a skip,
MOVN,
MOV,
M
S
(6-7,
bits.
Move
negative
or magnitude.
Move
or move and swap.
Multiply.
MP (6-21) MQ
C(E).
indicators.
Miscellaneous
BITS zero
and may or may not increment
and may or may not increment
MI
and
11,12,
13) Multiplier
control
A3-10
quotient
logic
register
and special
and associated
inputs.
Extra
MQ36
MR (5-1,
MQ
bit for use in multiply.
Master.
2)
Pulse that prepares
MR CLR
main
sequence
Pulse that
MR START
(
turnon
or console
clears
or when
entire
Multiply
MSB
Most significant
MUL
Multiply.
MULT
Multiply.
NEGATE
Form the arithmetic
NR (6-27)
Normalize
NXT
Next.
OP
Operation.
ov
Overflow.
PC (5-l 1, 12)
Program
PDL OV
Pushdown
4)
function.
computer
at power
subroutine.
bit.
2’s complement.
return.
counter
and control.
list overflow.
Priority
interrupt.
PI A
Priority
interrupt
PICH
PI channel
A3-11
for each
IO RESET is pressed.
MS (6-24)
PI (8-3,
processor
assignment.
address.
PIH
PI hold.
PI0
PI on
PIR
PI request
POP
Pullout.
POPJ
Pullout
PR (7-4)
Protection
PSE
Pause.
l
and jump.
e
PTP (8-9,
10)
Paper tape
punch e
PTR (8-6,
7, 8)
Paper tape
reader.
PUSH
Pushdown
a
PUSHJ
Pushdown
and jump.
PWR
Power.
PWR CLR
Pulses that clear
RD
Read.
REL
Relocation
REM
Remainder;
low-order
Request.
RIM
Readin
RLA (7-5)
Relocation
A3-12
at power
turnon.
*
floating-point
half
REQ
computer
of result
mode.
adder.
mode that
in AC2.
stores
RLR (7-5)
Relocation
ROT
Rotate.
ROTC
Rotate
Combined.
RPT
Repeat
l
RQ
Request a
RS
Restart,
RST
Restore
RT
Right.
RUN
.
l
Run,
(5-l)
s (5-6)
Store cycle
SBR
Subroutine;
SC (6-14,
register
15,
16)
l
also a mnemonic
card
1260.
Shift
counter
SEL
Select 6
SH (6-20)
Shift.
SH AC2
Double-length
SHC (6-7)
Shift
SPACE
Teletype
SR
Shift
ST
Start.
A3-13
,
shift
l
connection.
signal
register.
for 0.
for subroutine
STATUS Any
IOT
i.e.,
instruction
CONI,
STB
Strobe
SW (5-l)
Switch.
SWAP
Interchange
that examines
CONS0
status,
or CONSZ.
l
the left and right
halves
of
a word.
SUB
Subtract
T
Time. TST
Test. .
TTI (8-11,
12)
Teletype
input . TTO (8-l
1, 12)
Teletype
output. TTY (8-l
1, 12)
Teletype. uuo
(5-l 0) Programmed
UUO
is performed
or when
UUO
A
WR
XCT
2xx
IR decoder
(unused
when
it replaces
output
op code);
a
one is programmed
an illegal
user instruction.
for UUO. Write, (5-10)
Execute. Level
code
25X
operator
Level
code
A3-14
indicating
beginning
indicating
beginning
that
with
that
with
IR contains
an octa I 2.
IR contains
25.
an octal
APPENDIX
INSTRUCTION
Octal
Mnemonic
000
uuo
,0;7
100
131
132
133
134
135
136
137
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
FSC
IBP
I LDB
LDB
IDPB
DPB
FAD
FADL
FADM
FADB
FADR
FADRL
FADRM
FADRB
FSB
FSBL
FSBM
FSBB
FSBR
FSBRL
FSBRM
FSBRB
FMP
FMPL
FMPM
FMPB
FMPR
FMPRL
FMPRM
FMPRB
FDV
FDVL
4
CODES
Octal
Mnemonic
Octal
172
173
174
175
176
177
200
201
202
203
204
205
206
207
210
21 1
212
213
214
215
216
217
220
221
222
223
224
225
226
227
230
231
232
233
234
235
236
237
240
241
FDVM
FDVB
FDVR
FDVRL
FDVRM
FDVRB
MOVE
MOVE I
MOVEM
MOVES
MOVS
MOVSI
MOVSM
MOVSS
MOVN
MOVNI
MOVNM
MOVNS
MOVM
MOVMI
MOVMM
MOVMS
IMUL
IMULI
IMULM
IMULB
MUL
MULI
MULM
MULB
IDIV
IDIVI
IDIVM
IDIVB
DIV
DIVI
DIVM
DIVB
ASH
ROT
242
243
244
245
246
247
250
251
252
253
254
255
256
257
260
261
262
263
264
265
266
267
270
271
272
273
274
275
276
277
300
301
302
303
304
305
306
307
310
311
A4-1
Mnemonic
LSH
ASHC
ROTC
LSHC
EXCH
BLT
AOBJP
AOBJN
JRST
JFCL
XCT
PUSHJ
PUSH
POP
POPJ
JSR
JSP
JSA
JRA
ADD
ADDI
ADDM
ADDB
SUB
SUBI
SUBM
SUBB
CAI
GAIL
CAIE
CAKE
CAIA
CAIGE
CAIN
CAIG
CAM
CAML
Octal
Mnemonic
Octal
*Mnemonic
Octal
312
313
314
315
316
317
320
321
322
323
324
325
326
327
330
331
332
333
334
335
336
337
340
341
342
343
344
345
346
347
350
351
352
353
354
355
356
357
360
361
362
363
364
365
366
CAME
CAMLE
CAMA
CAMGE
CAMN
CAMG
JUMP
JdMPL
JUMPE
J UMPLE
JUMPA
JUMPGE
JUMPN
JUMPG
SKIP
SKIPL
SKIPE
SKIPLE
SKIPA
SKIPGE
SKIPN
SKIPG
AOJ
A03 L
AOJE
AOJ LE
AOJA
AOJGE
AOJN
AOJG
AOS
AOSL
AOSE
AOSLE
AOSA
AOSGE
AOSN
AOSG
SOJ
SOJL
SOJE
SOJ LE
SOJA
SOJ GE
SOJN
367
370
371
372
373
374
375
376
377
400
401
402
403
404
405
406
407
410
411
412
413
414
415
416
417
420
421
422
423
424
425
426
427
430
431
432
433
434
435
436
437
440
SOJ G
SOS
SOSL
SOSE
SOSLE
SOSA
SOSGE
SOSN
SOSG
SETZ
444
445
446
447
450
451
452
453
454
455
456
457
460
461
462
463
464
465
466
467
470
471
472
473
474
475
476
477
500
501
502
503
504
505
506
507
510
511
512
513
514
515
516
517
520
*
SETZI
SE TZM
SETZB
AND
ANDI
ANDM
ANDB
ANDCA
ANDCAI
ANDCAM
AN DCAB
SETM
SE TMI
SE TMM
SETMB
AN DCM
ANDCMI
ANDCMM
ANDCMB
SETA
SETAI
SE TAM
SETAB
XOR
XORI
XORM
XORB
IOR
IORI
IORM
IORB
ANDCB
441
ANDCBI
442
443
ANDCBM
ANDCBB
A4-2 Mnemonic
EQV
EQVI
EQVM
EQVB
SETCA
SETCAI
SETCAM
SETCAB
ORCA
ORCAI
ORCAM
ORCAB
SETCM
SETCMI
SE TCMM
SETCMB
ORCM
ORCMI
ORCMM
ORCMB
ORCB
ORCBI
ORCBM
ORCBB
SET0
SET01
SETOM
SETOB
HLL
HLLI
HLLM
HLLS
HRL
HRLI
HRLM
HRLS
HLLZ
HLLZI
HLLZM
HLLZS
HRLZ
HRLZI
HRLZM
HRLZS
HLLO
Octal
Mnemonic
Octal
521
522
523
524
525
526
527
530
531
532
533
534
535
536
537
540
541
542
543
544
545
546
547
550
551
552
553
554
555
556
557
560
561
562
563
564
565
566
567
570
HILL01
HILLOM
HILLOS
HIRLO
HIRLOI
HIRLOM
HIRLOS
HILLE
HILLEI
H LLEM
HILLES
HIRLE
HiRLEI
H RLEM
HIRLES
H RR
H RRI
H RRM
HIRRS
HILR
H LRI
H LRM
H LRS
H RRZ
H RRZI
H RRZM
H RRZS
H LRZ
H LRZI
H LRZM
H LRZS
H RR0
H RROI
H RROM
H RROS
H LRO
H LROI
H LRiIM
Hi LROS
H RRE
571
572
573
574
575
576
577
600
601
602
603
604
605
606
607
610
611
612
613
614
615
616
617
620
621
622
623
624
625
626
627
630
631
632
633
634
635
636
637
640
Mnemonic
HRREI
HRREM
HRRES
H LRE
HLREI
H LREM
HLRES
TRN
TLN
*TRNE
TLNE
TRNA
TLNA
TRNN
TLNN
TDN
TSN
TDNE
TSNE
TDNA
TSNA
TDNN
TSNN
TRZ
TLZ
TRZE
TLZE
TRZA
TLZA
TRZN
TLZN
TDZ
TSZ
TDZE
TSZE
TDZA
TSZA
TDZN
TSZN
TRC
A4-3 Octal
641
642
643
644
645
646
647
650
651
652
653
654
655
656
657
660
661
662
663
664
665
666
667
670
671
672
673
674
675
676
677
7-00
7-04
7-10
7-14
7-20
7-24
7-30
7-34
Mnemonic
TLC
TRCE
TLCE
TRCA
TLCA
TRCN
TLCN
TDC
TSC
TDCE
TSCE
TDCA
TSCA
TDCN
TSCN
TRO
TLO
TROE
TLOE
TROA
TLOA
TRON
TLON
TDO
TSO
TDOE
TSOE
TDOA
TSOA
TDON
TSON
BLKI
DATAI
BLKO
DATA0
CON0
CONI
CONSZ
CONS0
APPENDIX
TELETYPE
The 8-bit
Model
only
codes are listed
35.
seven
Alternate
An
below.
characters
information
bits.
are listed
The eighth
are set up so that
the eighth
2008 greater
the corresponding
Octal
Code
than
ASCII
Character
asterisk
bit
5
CODE
indicates
in parentheses.
a code
that
The characters
bit may be used for parity,
is a mark,
has no effect
ASCII
actually
but currently
and thus the codes generated
on the
contain
all
machines
from the keyboard
are
codes.
Key
Remarks
Combination
200
NULL
SHIFT CTRL P
Null.
201"
SOM
CTRL A
Start
202*
EOA
CTRL B
End of address.
203*
EOM
CTRL C
End of message.
204
EOT
CTRL EOT
End of transmission;
machines.
205
WRU
CTRL WRU
“Who
is
.
l
of message.
.,
are you?”
Triggers
” at remote station.
206*
RU
CTRL RU
“Are
207
BELL
CTRL BELL
Rings the bell.
210*
FE
CTRL H
Format
211
HT
CTRL TAB
Horizontal
212
LF
LINE
Line feed.
213
V TAB
CTRL VT
Vertica
214
FF
CTRL FORM
Form feed.
215
CR
RETURN
Carriage
216*
so
CTRL N
Shift
out.
217*
SI
CTRL 0
Shift
in.
220*
DC0
CTRL P
Device control
I inc escape.
FEED
As-1
shuts off TWX
you..
“Here
.?”
effector.
tab.
I tab.
return.
reserved
for data
Octal
Code
ASCII
Character
221.
DC1
CTRL Q
Turns reader
on. 222*
DC2
CTRL TAPE
Turns punch
on. 223
DC3
CTRL XOFF
Turns reader
off. 224*
DC4
CTRL &&&
Turns punt h off. 225*
’ ERR
CTRL U
Error . Key
Remarks
Combination
226*
SYNC
CTRL V,
Synchronous
227*
LEM
CTRL W
Logica I end of media. 230*
so
CTRL X
Separator,
information. 231*
Sl
CTRL Y
Separator,
data
232”
s2
CTRL Z
Separator,
words. 233*
s3
SHIFT CTRL
K
Separator,
groups. 234*
s4
SHIFT CTRL L
Separator,
records. 235”
s5
SHIFT CTRL M
Separator,
files. 236’
S6
SHIFT CTRL N
Separator,
misce I laneous. 237*
s7
SHIFT CTRL 0
Separator,
misce I laneous
240
Space
Space
bar
241
B
.
SHIFT
!
”
242
II
SHIFT
243
#
SHIFT #
SHIFT $
252
$
%
&
‘(9
(
)
*
253
+
SHIFT +
244
245
246
247
250
251
254
SHIFT %
SHIFT
&
SHIFT
‘(I)
SHIFT
(
SHIFT )
SHIFT *
I
255
256
A5-2
idle. delimiter. .
Octal
Code
ASCII
Character
Key
Combination
/
260
/
B
261
1
1
262
2
2
257
263
'3
0
Zero,
3
264
4
4
265
5
5
266
6
6
267
7
7
270
8
8
271
9
9
272
:
:
273
I
I
274
<
SHIFT <
275
300
301
A
A
302
B
B
303
C
C
304
D
D
305
E
E
306
F
F
307
G
G
310
H
H
311
I
I
312
J
J
313
K
K
314
L
L
277
*
SHIFT =
>
?
‘w
276
Remarks
SHIFT
>
SHIFT
?
SHIFT
‘A (@)
A593
prints
with
a slash
Octal
Code
ASCII Character Key
Remarks
Combination
315
M
M
316
N
N
317
0
0
320
P
P
321
‘Q
Q
322
R
R
323
S
S
324
T
T
325
U
U
326
V
V
327
W
W
330
X
X
331
Y
Y
332
Z
Z
333
1
SHIFT
K
334
- 0
SHIFT
L
335
1
SHIFT M
336
SHIFT
337
SHIFT
a
n(t)
(+)
Lower case letters; codes cannot
be generated
from keyboard
and
should not be used in programs
for reasons of compatability.
340-373*
374*
375”
376*
Acknowledge;
code cannot be generated from keyboard
and should
not be used in programs for reasons
of compatabi
I ity.
ACK
01
ALT MODE
May be used for any desired
purpose.
control
Escape; code cannot be generated
from keyboard
and should not be
used in programs for reasons of
compatability.
ESC
AS-4
Octal
Code
ASCII
Character
377*
DEL
Key
Combination
Remarks
RUB OUT
Delete
REPT
Causes any other key that is struck
to repeat continuously
until REPT
is released.
LOC
LF
Local
line
feed.
LOC CR
Loca I carriage
BRK RLS’
Not
A5-5
connected.
return.
APPENDIX
CARD
6-bit
Code
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
Character
1
2
3
4
5
6
7
8
9
0
=[#I
’ [@I
Space
/
S
T
U
V
W
X
Y
Z
i VI
OO
6
READER
Column
Punch
CODE
6-bit
Code
Any invalid
1
2
3
4
5
6
7
8
9
0
83
84
85
86
87
None
01
02
03
04
05
06
07
08
09
082
083
084
085
086
087
40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67 70 71 72 73 74
75
76
77
A6-1 Character
J
K
L
M
N
0
P
Q
R
$
*
+ [a1
A
I3
C
D
E
F
G
H
I
i m
Column
Punch
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1
2
3
4
5
6
7
8
9
0
8
8
8
8
8
3
4
5
6
7
1
2
3
4
5
6
7
8
9
0
8
8
8
8
8
3
4
5
6
7
Invalid Punch Combinations
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
11
11
11
11
11
11
11
11
11
Q
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
12
12
12
12
12
12
12
12
12
23
24
25
26
27
2 8"
29
34
12
13
14
15
16
17
18
19
*except 2 8 0
A692 $3 5
36
37
39
45
46
47
49
56
57
59
67
69
79
89
11 12
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