Техническое описание

Техническое описание
March 6th 2011
SOM
TDM-3730 SYSTEM ON MODULE
TDM-3730 HARDWARE MANUAL rev A | March 6 2012, TechNexion
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
TDM-3730
TDM-3730 System on Module
Hardware Manual
Rev A
2
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
1 Contents
2
Revision ........................................................................................................................................... 5
3
Care and Maintenance ..................................................................................................................... 6
4
5
3.1
General .................................................................................................................................... 6
3.2
Regulatory Information ............................................................................................................ 6
Description ...................................................................................................................................... 9
4.1
Block Diagram TDM-3730 System on Module ......................................................................... 10
4.2
Functional Block Diagram CPU................................................................................................ 11
System Components ...................................................................................................................... 12
5.1
CPU: DM-3730 ....................................................................................................................... 12
5.1.1
5.2
6
PMIC: TPS-65930 .................................................................................................................... 15
5.2.1
TPS-65930 – Introduction ............................................................................................... 15
5.2.2
TPS-65930: Features ....................................................................................................... 15
5.3
Memory ................................................................................................................................. 16
5.4
NAND Flash ............................................................................................................................ 17
5.5
Network: SMSC LAN9220 ....................................................................................................... 18
5.6
USB PHY ................................................................................................................................. 19
5.7
WiFi Module .......................................................................................................................... 19
5.7.1
WiFi Signals Description.................................................................................................. 19
5.7.2
I-PEX Connector.............................................................................................................. 20
How to use the Multiplex Mode ..................................................................................................... 21
6.1
7
Multiplexing in u-boot ............................................................................................................ 21
TDM-3730 Module Pin Description ................................................................................................ 23
7.1.1
8
DM-3730 Digital Media Processor Features .................................................................... 12
Definitions ...................................................................................................................... 38
Signal Description .......................................................................................................................... 39
8.1
External Memory Interfaces – GPMC Signals Description........................................................ 39
8.2
Video Interfaces –CAM Signals description ............................................................................. 40
8.3
Video Interfaces – DSS Signals Description ............................................................................. 42
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8.4
Video Interfaces – TV Signals Description ............................................................................... 43
8.5
Serial Communication Interfaces – I2C Signals Description ...................................................... 44
8.6
Serial Communication Interfaces – McBSP LP Signals Description ........................................... 44
8.7
Serial Communication Interfaces – McSPI Signals Description................................................. 45
8.8
Serial Communication Interfaces – UARTs Signals Description ................................................ 46
8.9
Serial Communication Interfaces – USB Signals Description .................................................... 47
8.10
Removable Media Interfaces – MMC/ SDIO Signals ................................................................ 47
8.11
General Purpose IOs Signals Description ................................................................................ 48
8.12
Test Interfaces – JTAG Signals Description .............................................................................. 49
8.13
Power Supplies Signals description ......................................................................................... 51
8.14
System and Miscellaneous Signals Description ....................................................................... 51
8.15
Touch Interupt Signal Description........................................................................................... 52
8.16
Serial Communcication Interfaces – HDQ/ 1-Wire Signals Description .................................... 52
8.17
PWM Signals Description........................................................................................................ 52
8.18
ADC Signals Description.......................................................................................................... 52
8.19
Analog Audio Signals Description ........................................................................................... 53
8.20
Keypad Signals Description ..................................................................................................... 54
8.21
Ethernet Signals Description................................................................................................... 55
8.22
LED Signals Description .......................................................................................................... 55
8.23
Pull-up or Pull-down Signals Description................................................................................. 56
8.24
Boot Option ........................................................................................................................... 56
9
Electrical Characteristics ................................................................................................................ 57
10
Environmental Specifications ..................................................................................................... 58
11
Mechanical Dimensions ............................................................................................................. 59
11.1
12
TDM-3730 System on Module Dimensions ............................................................................. 59
Module Connection ................................................................................................................... 60
12.1
Module Connector DDR2 SO-DIMM ....................................................................................... 60
12.2
Nut to Fix TDM-3730 Module to the Baseboard ..................................................................... 61
13
Disclaimer .................................................................................................................................. 62
14
Warranty ................................................................................................................................... 63
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TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
15
Contact Information................................................................................................................... 64
2 Revision
Revision
0.90
A
A-01
A-02
Date
21/06/2011
05/07/2011
11/08/2011
06/03/2012
Description
Preliminary version
First public version
Change in Wifi signals description
Add Chapter about multiplexing in Software
5
Created by
TechNexion
TechNexion
TechNexion
TechNexion
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
3 Care and Maintenance
3.1 General
Your device is a product of superior design and craftsmanship and should be treated with care.
The following suggestions will help you.
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Keep the device dry. Precipitation, humidity, and all types of liquids or moisture can
contain minerals that will corrode electronic circuits. If your device does get wet, allow it
to dry completely.
Do not use or store the device in dusty, dirty areas. Its moving parts and electronic
components can be damaged.
Do not store the device in hot areas. High temperatures can shorten the life of electronic
devices, damage batteries, and warp or melt certain plastics.
Do not store the device in cold areas. When the device returns to its normal temperature,
moisture can form inside the device and damage electronic circuit boards.
Do not attempt to open the device.
Do not drop, knock, or shake the device. Rough handling can break internal circuit
boards and fine mechanics.
Do not use harsh chemicals, cleaning solvents, or strong detergents to clean the device.
Do not paint the device. Paint can clog the moving parts and prevent proper operation.
Unauthorized modifications or attachments could damage the device and may violate
regulations governing radio devices.
These suggestions apply equally to your device, battery, charger, or any enhancement. If any
device is not working properly, take it to the nearest authorized service facility for service.
3.2 Regulatory Information
Disposal of Waste Equipment by Users in Private Household in the European Union
This symbol on the product or on its packaging indicates that this product must
not be disposed of with your other household waste. Instead, it is your
responsibility to dispose of your waste equipment by handing it over to a
designated collection point for the recycling of waste electrical and electronic
equipment. The separate collection and recycling of your waste equipment at the
time of disposal will help to conserve natural resources and ensure that it is
recycled in a manner that protects human health and the environment. For more information
about where you can drop off your waste equipment for recycling, please contact your local city
office, your household waste disposal service or the shop where you purchased the product.
We hereby declare that the product is in compliance with the essential
requirements and other relevant provisions of European Directive 1999/5/EC
(radio equipment and telecommunications terminal equipment Directive).
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Federal Communications Commission (FCC) Unintentional emitter per
FCC Part 15
This device has been tested and found to comply with the limits for a Class B
digital device, pursuant to Part 15 of the FCC rules. These limits are designed
to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instructions, may cause harmful interference to radio
or television reception. However, there is no guarantee that interference will not occur in a
particular installation. If this equipment does cause interference to radio and television reception,
which can be determined by turning the equipment off and on, the user is encouraged to try to
correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna
■ Increase the separation between the equipment and receiver
■ Connect the equipment to an outlet on a different circuit from that to which the receiver is
connected
■ Consult the dealer or an experienced radio/TV technician for help.
WARNING! To reduce the possibility of heat-related injuries or of overheating
the computer, do not place the computer directly on your lap or obstruct the
computer air vents. Use the computer only on a hard, flat surface. Do not allow
another hard surface, such as an adjoining optional printer, or a soft surface,
such as pillows or rugs or clothing, to block airflow. Also, do not allow the AC
adapter to contact the skin or a soft surface, such as pillows or rugs or clothing, during operation.
The computer and the AC adapter comply with the user-accessible surface temperature limits
defined by the International Standard for Safety of Information Technology Equipment (IEC
60950).
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4 Description
The TDM-3730 Is a highly integrated System on Module (SOM) containing the TI ARM Cortex
A8 DaVinci DM3730 processor, PMIC, Wireless LAN, USB PHY, LAN Controller, Memory and
NAND Flash.
The high-performance, digital media processors are based on the enhanced device architecture
and are integrated on advanced 45-nm process technology. This architecture is designed to
provide best in class ARM and Graphics performance while delivering low power consumption.
This balance of performance and power allow the device to support the following example
applications:
• Portable Data Terminals
• Navigation
• Auto Infotainment
• Gaming
• Medical Imaging
• Home Automation
• Human Interface
• Industrial Control
• Test and Measurement
• Single board Computers
The device can support numerous HLOS and RTOS solutions including Linux, Android and
Windows Embedded CE by TechNexion and/ or third parties.
One can always check our website ( www.technexion.com ) for additional product detail
information, mechanical design files, software programming guides, source code software and
custom baseboard creation guideline.
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4.1 Block Diagram TDM-3730 System on Module
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4.2 Functional Block Diagram CPU
The functional block diagram of the DM3730 Digital Media Processor is shown below.
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5 System Components
5.1 CPU: DM-3730
5.1.1 DM-3730 Digital Media Processor Features
Texas Instruments (TI) DM3730 Digital Media Processor
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Compatible with OMAP™ 3 Architecture
ARM® Microprocessor (MPU) Subsystem
o Up to 1-GHz ARM® Cortex™-A8 Core Also supports 300, 600, and 800-MHz
operation
o NEON™ SIMD Coprocessor
High Performance Image, Video, Audio (IVA2.2TM) Accelerator Subsystem
o Up to 800-MHz TMS320C64x+TM DSP Core Also supports 260, 520, and 660MHz operation
o Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
o Video Hardware Accelerators
POWERVR SGX™ Graphics Accelerator
o Tile Based Architecture Delivering up to 20 MPoly/sec
o Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel
and Vertex Shader Functionality
o Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
o Fine Grained Task Switching, Load Balancing, and Power Management
o Programmable High Quality Image Anti-Aliasing
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core
o Eight Highly Independent Functional Units
o Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit,
Arithmetic per Clock Cycle
o Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
o Load-Store Architecture With Non-Aligned Support
o 64 32-Bit General-Purpose Registers
o Instruction Packing Reduces Code Size
o All Instructions Conditional
o Additional C64x+TM Enhancements
 Protected Mode Operation
 Expectations Support for Error Detection and Program Redirection
 Hardware Support for Modulo Loop Operation
C64x+TM L1/L2 Memory Architecture
o 32K-Byte L1P Program RAM/Cache (Direct Mapped)
o 80K-Byte L1D Data RAM/Cache (2-Way Set- Associative)
o 64K-Byte L2 Unified Mapped RAM/Cache (4- Way Set-Associative)
o 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
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C64x+TM Instruction Set Features
o Byte-Addressable (8-/16-/32-/64-Bit Data)
o 8-Bit Overflow Protection
o Bit-Field Extract, Set, Clear
o Normalization, Saturation, Bit-Counting
o Compact 16-Bit Instructions
o Additional Instructions to Support Complex Multiplies
1.8-V I/O and 3.0-V (MMC1 only), 0.9-V to 1.2-V Adaptive Processor CoreVoltage
0.9-V to 1.1-V Adaptive Core Logic Voltage
Note: These are default Operating Performance Point (OPP) voltages and could be
optimized to lower values using SmartReflex AVS.
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Serial Communication
o Multichannel Buffered Serial Ports (McBSPs)
 512 Byte Transmit/Receive Buffer (McBSP3)
 5K-Byte Transmit/Receive Buffer (McBSP2)
 SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix
Operations
 Direct Interface to I2S and PCM Device and T Buses
 128 Channel Transmit/Receive Mode
o Master/Slave Multichannel Serial Port Interface (McSPI) Ports
o High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI
Interface)
o High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem
 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
o One HDQ/1-Wire Interface
o UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR]
Modes)
o Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
Camera Image Signal Processing (ISP)
o CCD and CMOS Imager Interface
o Memory Data Input
o BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface
o Glueless Interface to Common Video Decoders
o Resize Engine
 Resize Images From 1/4x to 4x
 Separate Horizontal/Vertical Control
System Direct Memory Access (SDMA) Controller (32 Logical Channels With
Configurable Priority)
Comprehensive Power, Reset, and Clock Management
o SmartReflexTM Technology
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o Dynamic Voltage and Frequency Scaling (DVFS)
ARM® Cortex™-A8 Core
o ARMv7 Architecture
 TrustZone®
 Thumb®-2
 MMU Enhancements
o In-Order, Dual-Issue, Superscalar Microprocessor Core
o NEON Multimedia Architecture
o Over 2x Performance of ARMv6 SIMD
o Supports Both Integer and Floating Point SIMD
o Jazelle® RCT Execution Environment Architecture
o Dynamic Branch Prediction with Branch Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
o Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
ARM Cortex-A8 Memory Architecture:
o 32K-Byte Instruction Cache (4-Way Set-Associative)
o 32K-Byte Data Cache (4-Way Set-Associative)
o 256K-Byte L2 Cache
32K-Byte ROM
64K-Byte Shared SRAM
Endianess:
o ARM Instructions - Little Endian
o ARM Data – Configurable
o DSP Instructions/Data - Little Endian
Removable Media Interfaces:
o Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)
Test Interfaces
o IEEE-1149.1 (JTAG) Boundary-Scan Compatible
o Embedded Trace Macro Interface (ETM)
o Serial Data Transport Interface (SDTI
Up to 125 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
45-nm CMOS Technology
CPU Package:
o 423-pin s-PBGA package (CUS Suffix), .65mm Ball Pitch
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5.2 PMIC: TPS-65930
5.2.1 TPS-65930 – Introduction
The TPS65930 devices are power-management ICs for OMAP™ and other mobile applications.
The devices include power-management, a universal serial bus (USB) high-speed (HS)
transceiver, light -emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time
clock (RTC), and embedded power control (EPC). In addition, the TPS65930 includes a full
audio codec with two digital-to-analog converters (DACs) and two ADCs to implement dual
voice channels, and a stereo downlink channel that can play all standard audio sample rates
through a multiple format inter-integrated sound (I2S™)/time division multiplexing (TDM)
interface.
These optimized devices support the power and peripheral requirements of the OMAP
application processors. The power portion of the devices contains three buck converters, two
controllable by a dedicated SmartReflex™ class-3 interface, multiple low dropout (LDO)
regulators, an EPC to manage the power sequencing requirements of OMAP, and an RTC and
backup module. The RTC can be powered by a backup battery when the main supply is not
present, and the devices include a coin-cell charger to recharge the backup battery as needed.
The USB module provides a HS 2.0 OTG transceiver suitable for direct connection to the OMAP
UTMI+ low pin interface (ULPI), with an integrated charge pump and full support for the carkit
CEA-936A specification. An ADC is provided for monitoring signals, such as supply voltage,
entering the device, and two additional external ADC inputs are provided for system use.
The devices provide driver circuitry to power two LED circuits that can illuminate a panel or
provide user indicators. The drivers also provide pulse width modulation (PWM) circuits to
control the illumination levels of the LEDs. A keypad interface implements a built-in scanning
algorithm to decode hardware-based key presses and reduce software use, with multiple
additional general-purpose input/output devices (GPIOs) that can be used as interrupts when
configured as inputs.
5.2.2 TPS-65930: Features
The TPS65930 devices offer the following features:
 Audio:
o Differential input main microphones
o Mono auxiliary input
o External predrivers for class D (stereo)
o Automatic level control (ALC)
o Digital and analog mixing
o 16-bit linear audio stereo DAC (96, 48, 44.1, and 32 kHz and derivatives)
o 16-bit linear audio stereo ADC (48, 44.1, and 32 kHz and derivatives)
 USB:
o USB 2.0 on-the-go (OTG)-compliant HS transceivers
o 12-bit universal transceiver macro interface ULPI
o USB power supply (5-V charge pump for VBUS)
 Additional Features:
o Keypad Interface (up to 6 × 6)
 Backup battery charger
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5.3 Memory
The TDM-3730 has a dual channel 32 bit External Memory Interfaces (EMI) controller.
Each 32 bit wide channel is connected 16 bit wide to two Hynix H5MS1G62AFR MOBILE DDR
SDRAM Chips SDRAM_nCS0 and SDRAM_nCS1 signals are used to select them.
The standard configuration is organized as 1Gbit (4Bank x 16M x 16bits). Therefore given 4
chips are used a total of 4Gbit or 512MB of memory is available.
Features:
 Mobile DDR SDRAM
o Double data rate architecture: two data transfer per clock cycle
 Mobile DDR SDRAM INTERFACE
o x16 bus width
o Multiplexed Address (Row address and Column address)
 SUPPLY VOLTAGE
o 1.8V device: VDD and VDDQ = 1.7V to 1.95V
 MEMORY CELL ARRAY
o 1Gbit (x16 device) = 4Bank x 16Mb x 16 I/O
 DATA STROBE
o x16 device: LDQS and UDQS
o Bidirectional, data strobe (DQS) is transmitted and received with data, to be used
in capturing data at the receiver
o Data and data mask referenced to both edges of DQS
 LOW POWER FEATURES
o PASR (Partial Array Self Refresh)
o AUTO TCSR (Temperature Compensated Self Refresh)
o DS (Drive Strength)
 INPUT CLOCK
o Differential clock inputs (CK, CK)
 Data MASK
o LDM and UDM: Input mask signals for write data
o DM masks write data-in at the both rising and falling edges of the data strobe
 MODE and EXTENDED MODE REGISTER SET and STATUS REGISTER READ
o Keep to the JEDEC Standard regulation (Low Power DDR SDRAM)
 CAS LATENCY
o Programmable CAS latency 2 or 3 supported
 BURST LENGTH
o Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
 AUTO PRECHARGE
o Option for each burst access
 AUTO REFRESH AND SELF REFRESH MODE
 CLOCK STOP MODE
o Keep to the JEDEC Standard regulation
 INITIALIZING THE MOBILE DDR SDRAM
o Occurring at device power up or interruption of device power
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5.4 NAND Flash
NAND on the TDM-3730 is populated as Micron MT29F4G16ABBDAH4D and connected 16 bit
wide to the DM3730 GPMC bus.
The default TDM-3730 supports the chip which provides 512MB of addressable space.
The GPMC_nCS0 signal is used for it’s selection.
Features:
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Open NAND Flash Interface (ONFI) 1.0-compliant
Single-level cell (SLC) technology
Organization
o Page size x8: 2112 bytes (2048 + 64 bytes)
o Page size x16: 1056 words (1024 + 32 words)
o Block size: 64 pages (128K + 4K bytes)
o Plane size: 2 planes x 2048 blocks per plane
o Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks
Asynchronous I/O performance
o tRC/tWC: 20ns (3.3V), 25ns (1.8V)
Array performance
o Read page: 25μs
o Program page: 200μs (TYP: 1.8V, 3.3V)
o Erase block: 700μs (TYP)
Command set: ONFI NAND Flash Protocol
Operation status byte provides software method for detecting
o Operation completion
o Pass/fail condition
o Write-protect status
Ready/Busy# (R/B#) signal provides a hardware method of detecting operation
completion
WP# signal: Write protect entire device
First block (block address 00h) is valid when shipped from factory with ECC. For
minimum required ECC, see Error Management.
Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000
RESET (FFh) required as first command after poweron
Alternate method of device initialization (Nand_Init) after power up (contact factory)
Internal data move operations supported within the plane from which data is read
Quality and reliability
o Data retention: 10 years
o Endurance: 100,000 PROGRAM/ERASE cycles
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5.5 Network: SMSC LAN9220
The LAN9220 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded
applications where performance, flexibility, ease of integration and system cost control are
required. The LAN9220 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and
supports HP Auto-MDIX. The variable voltage I/O signals of the LAN9220 accommodate lower
voltage I/O signaling without the need for voltage level shifters.
Qualified Magnetics – Magnetics listed under this heading have been tested in order to verify
proper operation with the specific device listed with it.
Suggested magnetic – Magnetics listed under this heading have not been tested in order to
verify proper operation with the specific device listed with it. This category of magnetic has been
evaluated by the contents of the vendor supplied datasheet and legacy performance only.
Vendor
Part Number
Qualified Magnetics
UDE
RT7-115A1K1A
Pulse
H1102
Halo
TG110-RP55N5
Halo
HFJ11-RP26E- L12RL
Delta
RJSE1R5310A
Pulse
HX1188
Halo
TG110-RPE5N5
Halo
HFJ11-RPE26E-L12RL
TDK
TLA-6T717W
Delta
LFE8505T
Suggested Magnetics
Pulse
J0011D01B
Midcom
000-7219-35
Bothhand
TS6121C
Bothhand
LU1S041X-43
Midcom
000-7090-37R
Midcom
MIC66211-5171T- LF3
Elec & Eltek
820-M0323R
18
Package
Temp
Integrated RJ45
16-pin SOIC
16-pin SOIC
Integrated RJ45
Integrated RJ45
16-pin SOIC
16-pin SOIC
Integrated RJ45
Integrated RJ45
16-pin SOIC
0° - +70° C
0° - +70° C
0° - +70° C
0° - +70° C
0° - +70° C
-40° - +85° C
-40° - +85° C
-40° - +85° C
-40° - +85° C
-40° - +85° C
Integrated RJ45
Cardbus
16-pin SOIC
Integrated RJ45
16-pin SOIC
Integrated RJ45
16-pin SOIC
0° - +70° C
0° - +70° C
0° - +70° C
0° - +70° C
-40° - +85° C
-40° - +85° C
-40° - +85° C
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
5.6 USB PHY
The SMSC USB3320 is a Hi-Speed USB 2.0 transceiver that provides a configurable physical
layer (PHY) solution and is an excellent macth for a wide variety of products. USB3320 uses the
industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB Transceiver to the link.
ULPI uses a method of in-band signalling and status byte transfers between the link and
transceiver to facilitate a USB session with only 12 pins.
5.7 WiFi Module
The Marvell® 88W8686 is a low-power highly-integrated IEEE 802.11g/b MAC/Baseband/RF
WLAN system-on-chip (SoC), designed to support IEEE 802.11g payload data rates of 6, 9, 12,
18, 24, 36, 48, and 54 Mbps, as well as 802.11b data rates of 1, 2, 5.5, and 11 Mbps.
General features:
 Ultra low-power dissipation
 Single-chip integration of 802.11g/b wireless RF and baseband, MAC, CPU, memory,
and host interfaces
 Integrates all RF to baseband transmit and receive operations, with support for external
PAs
 Fully integrated frequency synthesizers with optimized phase noise performance for
OFDM applications
 Integrated direct conversion WLAN RF radio
 Supports 19.2, 20, 24, 26, 38.4, and 40 MHz oscillator clock sources
 Software backward compatible with 88W8385 and 88W8015 devices
5.7.1 WiFi Signals Description
SIGNAL NAME
DESCRIPTION
MMC2_CLK
Clock
MMC2_CMD
Command
MMC2_d0
4 bit data
MMC2_d1
4 bit data
MMC2_d2
4 bit data
MMC2_d3
4 bit data
GPIO54
Reserved
GPIO 157
Wifi enable – power on
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5.7.2
I-PEX Connector
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6 How to use the Multiplex Mode
The function of the pins on the module can be changed by adjusting the multiplex mode (mux).
6.1 Multiplexing in u-boot (Linux)
Multiplexing can be done in u-boot in the tdm3730.h file
(Use the file in this directory: board/technexion/tdm3730/tdm3730.h)
Example of what it might look like:
MUX_VAL(CP(ETK_D2),
(IEN|PTD|EN|M4))
The last part “M4” is the multiplex mode and you can change that according the table in the Chapter 7.
The line of code is build up as follows:


Pin #
The name of the variable is the function in Mode 0; ETK_D2
The current Multiplex mode is M4, which means that currently this pin is GPIO_16
Ball #
Pin Name
mode V
type
description
SPI Enable 0, polarity
MCSPI3 CS0
1
IO
configured by software
etk_d2
0
O
ETK data 2
84
AC7
GPIO_16
4
1.8
IO
General-purpose IO 16
USB data. Used as VP in 4Mm1_txdat
5
IO
pin VP_VM mode
Hw_dbg4
7
O
Debug signal 4
Table 1: Example of pin 84 on the TDM-3730 module and the different functions for each multiplex
mode (see Chapter 7)
After this you will need to recompile:
Uboot#
Uboot#
Uboot#
make distclean
make tdm3730_config
make tdm3730
This will create the u-boot.bin
6.2 Multiplexing in Windows Embedded Compact 7
Change the following file:
C:\WINCE700\platform\TN_TDM_3730\SRC\INC\bsp_padcfg.h
21
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Change code :
#define GPIO_PADS_37XX \
PAD_ENTRY(ETK_D4, INPUT_DISABLED | MUXMODE(4))
Then recompile
22
/* GPIO 18 */ \
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
7 TDM-3730 Module Pin Description
Pin #
1
2
3
4
Ball #
X
X
X
X
Pin Name
VBUS_5V
DC_5V
GND
DC_5V
5
X
PreDriv.RIGHT
6
X
DC_5V
7
X
PreDriv.LEFT
8
X
DC_5V
9
X
MIC_BIAS_G
10
X
DC_5V
11
X
MIC_MAIN_P
12
X
DC_5V
13
X
PWR_ON
14
15
16
17
18
19
20
21
22
AA10
X
X
X
X
X
X
X
X
SYS_nRESPWRON
HOST nOC
RESETB
SYSEN
LEDA
GND
MMC1 CD
HSUSB ID
LCD PWM
23
X
MIC MAIN M
24
X
AUXR
25
X
MIC BIAS
26
27
28
29
30
31
X
X
X
X
X
X
CHRG STATE
VIO 1V8
DVI_nDISABLE
VIO 1V8
LCD ENBKL
VIO 1V8
32
X
HSUSB DN
33
X
VIO 1V8
mode
0
23
V
5
5
GND
5
type
I
I
GND
I
description
Power
5V
Power
5V
Predriver output right P for
O
external class-D amplifier
5
I
5V
Predriver output left P for
O
external class-D amplifier
5
I
5V
Dedicated ground for
GND GND
microphones
5
I
5V
2.5/
I
Main microphone left input (P)
2.75
5
I
5V
Input; detect a control
4.2
I
command to start or stop the
system
1.8
I
Power On Reset
1.8
IO
HOST nOC
USB PHY
1.8
OD
System enable output
4.2
D
User definable LED Indicator
GND GND Power
1.8
IO
Card Detection1
4.2
IO
USB ID
1.8
IO
LCD Backlight on/off
2.5/
Main microphone left input
I
2.75
(M)
2.5/
I
Auxiliary audio input right
2.75
2.5/
Pwr Analog microphone bias 1
2.75
1.5
IO
Battery type
1.8
O
Power
1.8
IO
DVI/ Backlight control
1.8
O
Power
1.8
IO
LCD Backlight Control
1.8
O
Power
USB data N/USB carkit
4.2
transmit data
1.8
O
Power
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
Pin Name
34
X
HSUSB DP
35
X
IDM0
36
X
ADCIN2
37
38
39
X
X
X
IDP0
CAM IO
VMMC1
MCSPI1 SIMO
MMC2_dat5
GPIO_172
Safe_mode
MCSPI1 CLK
MMC2_dat4
GPIO_171
Safe_mode
KPD.C4
MCSPI1 SOMI
Mmc2_dat6
GPIO_173
Safe_mode
KPD.C3
40
R4
41
T5
42
X
43
T4
44
X
45
T6
46
X
47
V4
48
X
49
V5
50
X
51
W4
52
X
mode
V
type
4.2
IO
2.5/
2.75
4.2
4.2
0
1
4
7
0
1
4
7
1.8
1.8
1.8
0
1
4
7
1.8
1.8
mcspi1_cs0
0
Mmc2_dat7
GPIO_174
Safe_mode
KPD.C2
1
4
7
mcbsp3_fsx
0
Uart2_rx
GPIO_143
Safe_mode
KPD.C1
Mcbsp3_dr
Uart2_rts
GPIO_141
Safe mode
KPD.C0
MCBSP3 CLKX
UArt 2_TX
GPIO_142
Safe mode
KPD.R4
1
4
7
IOA
description
USB data P/USB carkit
receive data
USB PHY 3320C
I
General –purpose ADC Input
IOA
O
IO
IO
IO
USB PHY 3320C
VBAT.RIGHT - VAUX2.OUT
Power
Slave data in, master data out
MMC/SD Card Data bit 5
General-purpose IO 172
IO
IO
IO
SPI Clock
MMC/SD Card Data bit 4
General-purpose IO 171
D
IO
IO
IO
Keypad column 4
Slave data out, master data in
MMC/SD Card Data bit 6
General-purpose IO 173
D
Keypad column 3
SPI Enable 0, polarity
configured by software
MMC/SD Card Data bit 7
General-purpose IO 174
IO
1.8
IO
IO
1.8
D
1.8
I
IO
Keypad column 2
Combined frame
synchronization
UART2 Receive data
General-purpose IO 143
1.8
D
I
O
IO
Keypad column 1
Received serial data
UART2 request to send
General-purpose IO 141
D
IO
O
IO
Keypad column 0
Combined serial clock
UART2_transmit data
General-purpose IO 142
I
Keypad row 4
IO
0
1
4
7
1.8
1.8
0
1
4
7
1.8
1.8
24
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
53
V6
54
X
55
T21
56
X
57
mode
0
1
4
7
Mmc2_dir_dat3
1
X
59
R20
60
X
61
V19
62
X
63
V20
AA1
V
type
IO
I
IO
description
Transmitted serial data
UART2_CTS
General-purpose IO 140
I
IO
IO
Keypad row 3
Combined serial Clock
General-purpose IO 117
I
I
O
IO
Keypad row 2
Boot configuration mode bit 5
Direction control for DAT4,
DAT5, DAT6, and DAT7
signals case an external
transceiver used
LCD Pixel Data bit 22
General-purpose IO 7
I
IO
IO
Keypad row 1
Transmitted serial data
General-purpose IO 119
1.8
I
IO
IO
Keypad row 0
Received serial data
General-purpose IO 118
1.8
I
IO
Keypad row 5
Combined frame
synchronization
General-purpose IO 116
IO
IO
I
IO
IO
General-purpose IO 139
MMC/ SD Card Data bit 7
MMC/ SD Input Clock
MMC/ SD Card Data bit 3
Transmit enable
1.8
1.8
0
4
7
1.8
1.8
0
O
AB16
58
64
Pin Name
MCBSP3_DX
UART2_CTS
GPIO_140
Safe mode
KPD.R3
MCBSP2_CLKX
GPIO_117
Safe_mode
KPD.R2
Sys_boot 5
1.8
Dss_data22
GPIO_7
Safe_mode
KPD.R1
Mcbsp2_dx
GPIO_119
Safe mode
KPD.R0
Mcbsp2_dr
GPIO_118
Safe mode
KPD.R5
3
4
7
Mcbsp2_fsx
0
GPIO_116
Safe mode
LCD PON
Mmc2_dat7
Mmc2_clkin
Mmc3_dat3
Mm3_rxdm
Safe mode
1.8
0
4
7
1.8
1.8
0
4
7
IO
1.8
4
7
4
0
1
3
6
7
1.8
25
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
65
66
67
68
69
Ball #
AA2
Pin Name
LCD_INI
Mmc2_dat5
mode
4
0
Mmc2_dir_dat1
1
AC1
AD2
70
X
71
Y7
type
IO
IO
Cam_global_reset
2
Mmc3_dat1
3
IO
Mm3_rxdp
6
IO
Safe mode
LCD_envdd
Mmc2_dat6
7
4
0
IO
IO
Mmc2_dir_cmd
1
O
O
1.8
Y2
AB2
V
IO
1.8
Cam_shutter
2
O
Mmc3_dat2
Safe mode
TS nPEN IRQ
Mmc2_dat4
3
7
4
0
IO
Mmc2_dir_dat0
1
Mmc3_dat0
3
IO
Safe mode
GPIO_12
etk_clk
mcbsp5_ clkx
mmc3_clk
7
4
0
1
2
IO
O
IO
O
mm1_rxdp
5
hw_dbg0
GPIO_19
etk_d5
7
4
0
mcbsp5_fsx
1
mmc3_dat1
hw_dbg7
GND
Sys_clkout1
GPIO_10
Safe_mode
2
7
IO
IO
1.8
O
description
General-purpose IO 137
MMC/SD card data bit 5
Direction control for DAT1
and DAT3 signals case an
external transceiver used
Global reset is used strobe
synchronization
MMC/SD Card Data bit 1
Vplus receive data (not used
in 3- or 4-pin configurations)
General-purpose IO 138
MMC/SD Card Data bit 6
Direction control for CMD
signal case an external
transceiver is used
Mechanical shutter control
signal
MMC/SD Card Data bit 2
General-purpose IO 136
MMC/SD Card Data bit 4
Direction control for DAT2
signal case an external
transceiver used
MMC/SD Card Data bit 0 /
SPI Serial Input
General-purpose IO 12
ETK trace clock
Combined serial clock
1.8
MMC/SD Output Clock
Vplus receive data (not used
IO
in 3- or 4-pin configurations)
O
Debug signal 0
IO
General-purpose IO 19
O
ETK data 5
Combined frame
1.8
IO
synchronization
IO
MMC/SD Card Data bit 1
O
Debug signal 7
GND GND Ground
O
Configurable output clock1
1.8
IO
General-purpose IO 10
0
4
7
26
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
72
AD3
73
AC12
74
75
76
77
AC5
AC13
AC14
AD6
78
AC15
79
X
80
AC6
Pin Name
GPIO_13
etk_ctl
mmc3_cmd
hw_dbg1
mode
4
0
2
7
I2C3_sda
0
V
1.8
type
IO
O
IO
O
IOD
1.8
GPIO_185
Safe mode
GPIO_18
Etk_d4
Mcbsp5_dr
4
7
4
0
1
Mmc3_dat0
2
IO
Hw_dbg6
7
O
I2C3 SCL
0
OD
GPIO_184
safemode
4
7
I2C2 SDA
0
GPIO_183
Safe_mode
4
7
MCSPI3 SIMO
1
IO
Etk_d0
Mmc3_dat4
GPIO_14
0
2
4
O
IO
IO
Mm1_rxcv
5
IO
Hw_dbg2
7
O
I2C2 SCL
0
OD
GPIO_168
Safe_mode
GND
MCSPI3 SOMI
Etk_d1
GPIO_15
4
7
Mm1_txse0
5
Hw_dbg3
7
1.8
1.8
IO
IO
O
I
IO
IOD
1.8
1.8
1.8
IO
IO
GND GND
IO
O
IO
1.8
IO
1
0
4
O
27
description
General-purpose IO 13
ETK trace ctl
MMC/SD command signal
Debug signal 1
I2C Serial Bidirectional Data.
Output is open drain.
General-purpose IO 185
General-purpose IO 18
ETK data 4
Received serial data
MMC/SD Card Data bit 0 /
SPI Serial Input
Debug signal 6
I2C Master Serial clock.
Output is open drain
General-purpose IO 184
I2C Serial Bidirectional Data.
Output is open drain.
General-purpose IO 183
Slave data in, master data out
IO
ATK data 0
MMC/SD Card Data bit 4
General-purpose IO 14
Differential receiver signal
input (not used in 3-pin mode)
Debug signal 2
I2C Master Serial clock.
Output is open drain
General-purpose IO 168
Ground
Slave data out, master data in
ETK data 1
General-purpose IO 15
Single-ended zero. Used as
VM in 4-pin VP_VM mode.
Debug signal 3
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
81
AD9
82
AD8
83
AB24
84
AC7
85
AA23
86
AC2
87
W6
88
89
90
91
Pin Name
mode
V
1.8
AO
1.8
I
IO
description
SPI Enable 1, polarity
configured by software
ETK data 7
MMC/SD Card Data bit 7
General-purpose IO 21
Transmit enable
Debug signal 9
SPI Clock
ETK data 3
MMC/SD Card Data bit 3
General-purpose IO 17
Debug signal 5
TV analog output Composite:
cvideo1_out
SPI Enable 0, polarity
configured by software
ETK data 2
General-purpose IO 16
USB data. Used as VP in 4pin VP_VM mode
Debug signal 4
TV analog output S-VIDEO:
cvideo2_out
UART1 Clear To Send
General-purpose IO 150
MCSPI3_CS1
1
O
etk_d7
mmc3_dat7
GPIO_21
mm1_txen_n
hw_dbg9
MCSPI3 CLK
Etk_d3
Mmc3_dat3
GPIO_17
Hw_dbg5
0
2
4
5
7
1
0
2
4
7
O
IO
IO
IO
O
IO
O
IO
IO
O
TV SVIDEO Y
0
MCSPI3 CS0
1
etk_d2
GPIO_16
0
4
Mm1_txdat
5
IO
Hw_dbg4
7
O
TV SVIDEO C
0
UART1 CTS
GPIO_150
Safe_mode
UART1 RTS
GPIO_149
Safe_mode
Mmc1_WP
Etk_d9
Mmc3_dat5
0
4
7
0
4
7
4
0
2
1.8
O
IO
UART1 Request To Send
General-purpose IO 149
IO
O
IO
General-purpose IO 23
ETK data 9
MMC/SD Card Data bit 5
Vminus receive data (not
used in 3- or 4-pin
configurations)
Debug signal 11
UART1 Transmit data
General-purpose IO 148
1.8
1.8
1.8
type
AO
IO
1.8
AD5
O
IO
1.8
Mm1_rxdm
5
IO
Hw_dbg11
UART1 TX
GPIO_148
Safe_mode
GPIO_20
Etk_d6
7
0
4
7
4
0
O
O
IO
AC8
Mcbsp5_dx
1
2
7
X
Mmc3_dat2
Hw_dbg8
KPD.C5
W7
1.8
IO
O
28
1.8
O
1.8
IO
O
D
General-purpose IO 20
ETK data 6
Transmitted serial data O
AF13
MMC/SD Card Data bit 2
Debug signal 8
Keypad column 5
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
92
V7
93
N23
94
M20
95
M23
96
M21
97
98
99
100
M22
K22
L23
J21
101
J22
102
AC22
103
H23
Pin Name
UART1 RX
Mcbsp1_clkr
Mcspi4_clk
GPIO_151
Safe mode
MMC1 DAT3
GPIO125 (2)
Safe mode
MMC1 DAT2
GPIO_124 (2)
Safe mode
MMC1 CLK0
GPIO_120 (2)
Safe mode
MMC1 DAT1
GPIO_123 (2)
Safe mode
mode
0
2
3
4
7
0
4
7
0
4
7
0
4
7
0
4
7
MMC1 DAT0
0
GPIO_122 (2)
Safe_mode
DSS D21
4
7
0
Mcspi3_cs0
2
Dss_data3
GPIO_91
Safe_mode
MMC1 CMD
GPIO_121 (2)
Safe_mode
3
4
7
0
4
7
DSS ACBIAS
0
GPIO_69
Safe_mode
DSS D16
GPIO_86
Safe_mode
DSS D10
GPIO_80
Safe_mode
Dss_data19
mcspi3_simo
dss_data1
GPIO_89
safe_mode
4
7
0
4
7
0
4
7
0
2
3
4
7
V
1.8
1.8/
3.3
1.8/
3.3
1.8/
3.3
1.8/
3.3
1.8/
3.3
type
I
IO
IO
IO
description
UART1 Receive data
Receive Clock
SPI Clock
General-purpose IO 151
IO
IO
MMC/SD Card Data bit 3
General-purpose IO 125
IO
IO
MMC/SD Card Data bit 2
General-purpose IO 124
O
IO
MMC/SD Output Clock
General-purpose IO 120
IO
IO
MMC/SD Card Data bit 1
General-purpose IO 123
IO
IO
O
IO
IO
LCD Pixel Data bit 21
SPI Enable 0, polarity
configured by software
LCD Pixel Data bit 3
General-purpose IO 91
IO
IO
MMC/SD command signal
General-purpose IO 121
IO
1.8
1.8/
3.3
IO
AC bias control (STN) or pixel
data enable (TFT) output
General-purpose IO 69
1.8
IO
IO
LCD Pixel Data bit 16
General-purpose IO 86
1.8
IO
IO
LCD Pixel Data bit 10
General-purpose IO 80
IO
IO
IO
IO
LCD Pixel Data bit 19
Slave data in, master data out
LCD Pixel Data bit 1
General-purpose IO 89
O
1.8
1.8
29
MMC/SD Card Data bit 0/ SPI
Serial Input
General-purpose IO 122
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
104
AC23
105
106
107
108
109
110
111
G24
AD21
G23
AB22
G22
AC21
F23
112
AC19
113
F22
114
AD20
Pin Name
Dss_data11
GPIO_81
Safe mode
Dss_data18
mcspi3_clk
dss_data0
GPIO_88
safe_mode
Dss_data4
mode
0
4
7
0
2
3
4
7
0
Uart3_rx_irrx
2
GPIO_74
Safe mode
Dss_data17
GPIO_87
Safe mode
Dss_data12
GPIO_82
Safe mode
Dss_pclk
GPIO_66
Hw_dbg12
Safe mode
Dss_data5
Uart3_tx_irtx
GPIO_75
Safe mode
Dss_data9
Uart3_tx_irtx
GPIO_79
Hw_dbg17
Safe mode
Dss_data0
Uart1_cts
GPIO_70
Safe mode
Dss_vsync
GPIO_68
Safe mode
Dss_data2
GPIO_72
Safe mode
4
7
0
4
7
0
4
7
0
4
5
7
0
2
4
7
0
2
4
5
7
0
2
4
7
0
4
7
0
4
7
V
type
IO
IO
description
LCD Pixel Data bit 11
General-purpose IO 81
IO
IO
IO
IO
LCD Pixel Data bit 18
SPI Clock
LCD Pixel Data bit 0
General-purpose IO 88
IO
IO
LCD Pixel data bit 4
UART3 Receive data, IR and
Remote RX
General-purpose IO 74
1.8
IO
IO
LCD Pixel data bit 17
General-purpose IO 87
1.8
IO
IO
LCD Pixel data bit 12
General-purpose IO 82
O
IO
O
LCD Pixel Clock
General-purpose IO 66
Debug signal 12
IO
O
IO
LCD Pixel data bit 5
UART3 Transmit data, IR TX
General-purpose IO 75
IO
O
IO
O
LCD Pixel data bit 8
UART3 Transmit data, IR TX
General-purpose IO 79
Debug signal 17
IO
I
IO
LCD Pixel Data bit 0
UART1 Clear To Send
General-purpose IO 70
1.8
O
IO
LCD Vertical Synchronization
General-purpose IO 68
1.8
IO
IO
LCD Pixel Data bit 2
General-purpose IO 72
1.8
1.8
1.8
1.8
1.8
1.8
1.8
30
I
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
115
E24
116
117
118
119
120
AC20
E23
AB19
D24
Y22
121
D23
122
W22
123
E22
124
W21
125
X
Pin Name
Dss_data8
Uart3_rx_irrx
GPIO_78
Hw_dbg16
Safe Mode
Dss_data3
GPIO_73
Safe mode
Dss_data7
Uart1_rx
GPIO_77
Hw_dbg15
Safe_mode
Dss-d1
Uart1_rts
GPIO_71
Safe_mode
Dss_data6
Uart1_rx
GPIO76
Hw_dbg14
Safe mode
Dss_data13
GPIO_83
Safe mode
Dss_data20
Mcspi3_somi
Dss_data3
GPIO_91
Safe mode
Dss_data14
GPIO_84
Safe_mode
mode
0
2
4
5
7
0
4
7
0
2
4
5
7
0
2
4
7
0
2
4
5
7
0
4
7
0
2
3
4
7
0
4
7
Dss_hsync
0
GPIO_67
Hw_dbg13
Safe_mode
Dss_data23
Dss_data5
GPIO_93
Safe_mode
GND
4
5
7
0
3
4
7
V
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
type
IO
I
IO
O
description
LCD Pixel Data bit 8
UART3 Transmit data, IR TX
General-purpose IO 78
Debug signal 16
IO
IO
LCD Pixel Data bit 3
General-purpose IO 73
IO
I
IO
O
LCD Pixel Data bit 7
UART1 Receive data
General-purpose IO 77
Debug signal 15
IO
O
IO
LCD Pixel Data bit 11
UART1 Request To Send
General-purpose IO 71
IO
I
IO
O
LCD Pixel Data bit 6
UART1 Receive data
General-purpose IO 76
Debug signal 14
IO
IO
LCD Pixel Data bit 13
General-purpose IO 83
O
IO
IO
IO
LCD Pixel Data bit 20
Slave data out, master data in
LCD Pixel Data bit 3
General-purpose IO 91
IO
IO
LCD Pixel Data bit 14
General-purpose IO 84
IO
O
LCD Horizontal
Synchronization
General-purpose IO 67
Debug signal 13
O
IO
IO
LCD Pixel Data bit 23
LCD Pixel Data bit 5
General-purpose IO 93
O
1.8
1.8
GND GND Ground
31
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
126
V21
127
128
C23
V22
129
B24
130
X
131
B23
132
133
134
135
AB18
Pin Name
Dss_data22
mode
0
Mcspi3_cs1
2
A23
IO
IO
description
LCD Pixel Data bit 22
SPI Enable 1, polarity
configured by software
LCD Pixel Data bit 4
General-purpose IO 92
type
O
1.8
O
IO
UART3 Transmit data, IR TX
General-purpose IO 166
1.8
IO
IO
LCD Pixel Data bit 15
General-purpose IO 85
O
1.8
Dss_data4
GPIO_92
Safe_mode
UART3 TX
GPIO_166
Safe_mode
Dss_data15
GPIO_85
Safe_mode
3
4
7
0
4
7
0
4
7
UART3_RX_IRRX
0
GPIO_165
Safe_mode
GND
4
7
UART3_RTS_SD
0
GPIO_164
Safe mode
4
7
Cam_d0
0
GPIO_99 (1)
Safe mode
4
7
HDQ_SIO
0
IOD
Sys_altclk
1
I
I
1.8
IO
UART3 Receive data, IR and
Remote RX
General-purpose IO 165
GND GND Ground
UART3 Request To Send, IR
O
enable
1.8
IO
General-purpose IO 164
I
1.8
A24
AC18
V
I
1.8
i2c2_sccbe
2
OD
i2c3_sccbe
3
OD
GPIO_170
Safe_mode
4
7
IO
Cam_d1
0
I
GPIO-100 (1)
Safe mode
4
7
UART3 CTS
0
GPIO_163
Safe_mode
4
7
1.8
I
IO
1.8
32
IO
Camera digital image data bit
0
General-purpose IO 99
Bidirectional HDQ 1-Wire
control and data Interface.
Output is open drain.
Alternate clock source
selectable for GPTIMERs
(maximum 54 MHz), USB (48
MHz), or NTSC/PAL (54
MHz)
Serial Camera Control Bus
Enable
Serial Camera Control Bus
Enable
General-purpose IO 170
Camera digital image data bit
1
General-purpose IO 100
UART3 Clear To Send
(input), Remote TX (output)
General-purpose IO 163
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
136
137
138
139
140
141
Ball #
L24
G21
K24
J20
K23
F21
142
J23
143
C22
144
145
H24
A22
Pin Name
mode
Cam_d6
0
GPIO_105 (1)
Safe_mode
4
7
Cam_d11
0
GPIO_110
Hw_dbg9
Safe_mode
4
5
7
Cam_d7
0
GPIO_106 (1)
Safe_mode
Cam_strobe
GPIO_126
Hw_dbg11
Safe_mode
4
7
0
4
5
7
CAM D9
0
GPIO_108 (1)
Safe_mode
4
7
CAM D10
0
GPIO_109
Hw_dbg8
Safe_mode
4
5
7
Cam_d8
0
GPIO_107 (1)
Safe_mode
Cam xclkb
GPIO_111
Safe_mode
Cam_fld
4
7
0
4
7
0
Cam_global_reset
2
GPIO_98
Hw_dbg3
Safe_mode
4
5
7
Cam_hs
0
GPIO_94
Hw_dbg0
Safe_mode
4
5
7
V
type
I
1.8
I
I
1.8
IO
O
1.8
I
O
IO
O
Flash strobe control signal
General-purpose IO 126
Debug signal 11
I
1.8
I
I
1.8
IO
O
1.8
O
IO
Camera clock output b
General-purpose IO 111
IO
Camera fiel identification
Global reset is used strobe
synchronization
General-purpose IO 98
Debug signal 3
IO
O
IO
1.8
33
Camera digital image data bit
10
General-purpose IO 109
Debug signal 8
I
IO
1.8
Camera digital image data bit
9
General-purpose IO 108
Camera digital image data bit
8
General-purpose IO 107
I
1.8
Camera digital image data bit
11
General-purpose IO 110
Debug signal 9
Camera digital image data bit
7
General-purpose IO 106
I
1.8
description
Camera digital image data bit
6
General-purpose IO 105
IO
O
Camera horizontal
synchronization
General-purpose IO 94
Debug signal 0
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
146
J19
147
B22
148
149
150
151
152
G19
F18
G20
B21
F19
153
E18
154
R2
155
T2
Pin Name
Cam_pclk
GPIO_97
Hw_dbg2
Safe_mode
Cam_xclka
GPIO_96
Safe_mode
mode
0
4
5
7
0
4
7
Cam_d2
0
GPIO_102
Hw_dbg5
Safe_mode
Cam_wen
4
5
7
0
Cam_shutter
2
GPIO_167
Hw_dbg10
Safe_mode
4
5
7
Cam_d4
0
GPIO_103
Hw_dbg6
Safe_mode
4
5
7
Cam_d5
0
GPIO_104
Hw_dbg7
Safe_mode
4
5
7
Cam_d3
0
GPIO_102
Hw_dbg5
Safe_mode
4
5
7
Cam_vs
0
GPIO_95
Hw_dbg1
Safe_mode
GPMC_d8 (3)
GPIO_44
Safe_mode
GPMC_d9 (3)
GPIO_45
Safe_mode
4
5
7
0
4
7
0
4
7
V
1.8
1.8
type
I
IO
O
description
Camera pixel clock
General-purpose IO 97
Debug signal 2
O
IO
Camera clock output a
General-purpose IO 96
I
1.8
IO
O
I
O
1.8
IO
O
I
1.8
IO
O
I
1.8
IO
O
I
1.8
IO
O
Camera write enable
Mechanical shutter control
signal
General-purpose IO 167
Debug signal 10
Camera digital image data bit
4
General-purpose IO 103
Debug signal 6
Camera digital image data bit
5
General-purpose IO 104
Debug signal 7
Camera digital image data bit
3
General-purpose IO 102
Debug signal 5
IO
O
Camera vertical
synchronization
General-purpose IO 95
Debug signal 1
1.8
IO
IO
GPMC data bit 8
General-purpose IO 44
1.8
IO
IO
GPMC data bit 8
General-purpose IO 45
IO
1.8
34
Camera digital image data bit
2
General-purpose IO 102
Debug signal 5
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
156
V2
157
U1
158
U2
159
T3
160
161
M3
P2
162
V1
163
164
P1
R1
165
W2
166
R3
167
168
169
170
171
172
173
174
X
X
M2
N2
M1
F2
G3
L2
175
J2
176
K3
177
X
Pin Name
GPMC_d15 (3)
GPIO_51
Safe_mode
GPMC_d10 (3)
GPIO_46
Safe_mode
GPMC_d13 (3)
GPIO_49
Safe_mode
GPMC_d12 (3)
GPIO_48
Safe_mode
GPMC_d4 (3)
GPMC_d6
GPMC_d14 (3)
GPIO_50
Safe_mode
GPMC_d5 (3)
GPMC_d7 (3)
GPMC_clk
GPIO_59
Safe_mode
GPMC_d11 (3)
GPIO_47
Safe_mode
GND
GND
GPMC_d2 (3)
GPMC_d3 (3)
GPMC_d1 (3)
GPMC_noe
GPMC_nwe
GPMC_d0 (3)
GPMC_a6 (4)
GPIO_39
Safe_mode
GPMC_a2 (4)
GPIO_35
Safe_mode
GND
mode
0
4
7
0
4
7
0
4
7
0
4
7
0
0
0
4
7
0
0
0
4
7
0
4
7
V
1.8
type
IO
IO
description
GPMC data bit 15
General-purpose IO 51
1.8
IO
IO
GPMC data bit 10
General-purpose IO 46
1.8
IO
IO
GPMC data bit 13
General-purpose IO 49
1.8
IO
IO
GPMC data bit 12
General-purpose IO 48
IO
IO
IO
IO
GPMC data bit 4
GPMC data bit 6
GPMC data bit 14
General-purpose IO 50
1.8
IO
IO
O
IO
GPMC data bit 5
GPMC data bit 7
GPMC clock
General-purpose IO 59
1.8
IO
IO
GPMC data bit 11
General-purpose IO 47
1.8
GND
GND
IO
IO
IO
O
O
IO
O
IO
Ground
Ground
GPMC data bit 2
GPMC data bit 3
GPMC data bit 1
Output enable
Write enable
GPMC data bit 0
GPMC output address bit 6
General-purpose IO 39
1.8
O
IO
GPMC output address bit 2
General-purpose IO 35
1.8
1.8
1.8
1.8
1.8
GND
GND
1.8
1.8
1.8
1.8
1.8
1.8
0
0
0
0
0
0
0
4
7
0
4
7
GND GND Ground
35
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
Ball #
178
G2
179
J1
180
X
181
K5
182
F1
183
J3
184
G4
185
K2
186
J4
187
K4
188
189
H2
H1
Pin Name
GPMC_a10 (4)
mode
0
Sys_ndmareq3
1
GPIO_43
Safe mode
GPMC_a7 (4)
GPIO_40
Safe_mode
GND
4
7
0
4
7
GPMC_nbe0_cle
0
GPIO_60
Safe_mode
4
7
GPMC_nadv_ale
0
GPMC_a5 (4)
GPIO_38
Safe_mode
GPMC_ncs7
0
4
7
0
GPMC_io_dir
1
Mcbsp4_fsx
2
Gpt_8_pwm_evt
GPIO_58
Safe_mode
GPMC_a3 (4)
GPIO_36
Safe_mode
GPMC_a4 (4)
GPIO_37
Safe_mode
GPMC_a1 (4)
GPIO_34
Safe_mode
GPMC_a9
3
4
7
0
4
7
0
4
7
0
4
7
0
Sys_ndmareq2
1
GPIO_42
Safe_mode
GPMC_a8
GPIO_41
Safe_mode
4
7
0
4
7
V
1.8
1.8
type
O
IO
description
GPMC output address bit 10
External A request 3 (system
expansion). Level (active low)
or edge (falling) selectable.
General-purpose IO 43
O
IO
GPMC output address bit 7
General-purpose IO 40
I
GND GND Ground
Lower Byte Enable. Also used
O
for Command Latch Enable
1.8
IO
General-purpose IO 60
1.8
O
1.8
O
IO
O
IO
IO
GPMC chip select bit 7
GPMC IO direction control for
use with external transceivers
Combined frame
synchronization
PWM or event for GP timer 8
General-purpose IO 58
1.8
O
IO
GPMC output address bit 3
General-purpose IO 36
1.8
O
IO
GPMC output address bit 4
General-purpose IO 37
1.8
O
IO
GPMC output address bit 1
General-purpose IO 34
O
IO
GPMC output address bit 9
External A request 2 (system
expansion). Level (active low)
or edge (falling) selectable.
General-purpose IO 42
O
IO
GPMC output address bit 8
General-purpose IO 41
O
1.8
1.8
1.8
36
Address Valid or Address
Latch Enable
GPMC output address bit 5
General-purpose IO 38
IO
I
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
Pin #
190
191
Ball #
mode
0
Sys_ndmareq1
1
Uart4_rx
GPIO_65
Safe_mode
2
4
7
X
F4
193
X
F3
V
type
I
I
C2
192
194
Pin Name
GPMC_wait3
1.8
I
O
Ether_txn
AO
GPMC_ncs4
0
O
Sys_ndmareq1
1
I
Mcbsp4_clkx
Gpt_9_pwm_evt
GPIO_55
Safe_mode
2
3
4
7
1.8
Ether_txp
IO
IO
IO
AO
GPMC_nxs6
0
O
Sys_ndmareq3
1
I
Mcbsp4_dx
2
Gpt_11_pwm_evt
3
IO
GPIO_57
Safe_mode
4
7
IO
195
X
Ether_rxn
196
X
LANLED_spd
197
X
Ether_rxp
198
X
LANLED_link
199
200
X
X
GND
GND
1.8
IO
description
External indication of wait
External A request 1 (system
expansion). Level (active low)
or edge (falling) selectable.
UART4 Receive data
General-purpose IO 65
LAN9220: transmit negative
output
GPMC Chip Select bit 4
External A request 1 (system
expansion). Level (active low)
or edge (falling) selectable.
Combined serial clock
PWM or event for GP timer 9
General-purpose IO 55
LAN9220: transmit positive
output
GPMC chip select bit 6
External A request 3 (system
expansion). Level (active low)
or edge (falling) selectable.
Transmitted serial data
PWM or event for GP timer
11
General-purpose IO 57
LAN9220: receive negative
input
LAN9220: LED1 speed
VO
indicator
LAN9220: receive postive
AI
input
LAN9220: LED2 link and
VOD
activity indicator
GND GND Ground
GND GND Ground
AI
37
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
7.1.1
Definitions
X=Pin on other chip than DM-3730
(1) This GPIO is only an input (and not an output).
(2) The usage of this GPIO is strongly restricted. For more information, see the GeneralPurpose Interface chapter of the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(3) The usage of local bus signals are resticted
(4) The local bus address signals can be used as GPIO only if the ethernet PHY is not
assembled
1. MODE: Multiplexing mode number.
 Mode 0 is the primary mode; this means that when mode 0 is set, the function
mapped on the pin corresponds to the name of the pin. There is always a
function mapped on the primary mode. Notice that primary mode is not
necessarily the default mode.
Note: The default mode is the mode at the release of the reset; also see the
RESET REL. MODE column.
 Modes 1 to 7 are possible modes for alternate functions. On each pin, some
modes are effectively used for alternate functions, while some modes are not
used and do not correspond to a functional configuration.
2. TYPE: Signal direction
 I = Input
 O = Output
 I/O = Input/output
 D = Open drain
 DS = Differential
 A = Analog
 PWR = Power
 GND = Ground
Note: In the safe mode, the buffer is configured in high-impedance.
38
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
8 Signal Description
8.1 External Memory Interfaces – GPMC Signals Description
The General Purpose Memory Controller (GPMC) is used to interface external memory devices:
such as NOR Flash, NAND Flash, Pseudo SRAM, SRAM or Field programmable Gate Array
(FPGA)
SIGNAL NAME
GPMC ALE
DESCRIPTION
TYPE
Address Valid or Address Latch Enable
O
Lower Byte Enable. Also used for Command
GPMC CLE
O
Latch Enable
GPMC D0
GPMC data bit 0
IO
GPMC D1
GPMC data bit 1
IO
GPMC D2
GPMC data bit 2
IO
GPMC D3
GPMC data bit 3
IO
GPMC D4
GPMC data bit 4
IO
GPMC D5
GPMC data bit 5
IO
GPMC D6
GPMC data bit 6
IO
GPMC D7
GPMC data bit 7
IO
GPMC D8
GPMC data bit 8
IO
GPMC D9
GPMC data bit 9
IO
GPMC D10
GPMC data bit 10
IO
GPMC D11
GPMC data bit 11
IO
GPMC D12
GPMC data bit 12
IO
GPMC D13
GPMC data bit 13
IO
GPMC D14
GPMC data bit 14
IO
GPMC D15
GPMC data bit 15
IO
GPMC nOE
Output Enable
O
GPMC nWE
Write Enable
O
GPMC A1
GPMC output address bit 1
O
GPMC A2
GPMC output address bit 2
O
GPMC A3
GPMC output address bit 3
O
GPMC A4
GPMC output address bit 4
O
GPMC A5
GPMC output address bit 5
O
GPMC A6
GPMC output address bit 6
O
GPMC A7
GPMC output address bit 7
O
GPMC A8
GPMC output address bit 8
O
GPMC A9
GPMC output address bit 9
O
GPMC A10
GPMC output address bit 10
O
GPMC CLK
GPMC Clock
O
GPMC nCS4
GPMC Chip Select bit 4
O
GPMC nCS6
GPMC Chip Select bit 6
O
GPMC nCS7
GPMC Chip Select bit 7
O
GPMC WAIT3
External indication of wait
I
Note 1: GPMC nCS0 is connected to NAND IC on TDM-3730.
Note 2: GPMC nCS5 is connected to SMSC LAN9220 IC on TDM-3730.
39
PIN TDM-3730
182
181
174
171
169
170
160
163
161
164
154
155
157
166
159
158
162
156
172
173
187
176
185
186
183
175
179
189
188
178
165
192
194
184
190
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
8.2 Video Interfaces –CAM Signals description
SIGNAL NAME
Cam_hs
Cam_vs
Cam_xclka
Cam_xclkb
Cam_d0
Cam_d1
Cam_d2
Cam_d3
Cam_d4
Cam_d5
Cam_d6
Cam_d7
Cam_d8
Cam_d9
Cam_d10
Cam_d11
Cam_fld
Cam_pclk
Cam_wen
Cam_strobe
Cam_IO
DESCRIPTION
Camera Horizontal Synchronization
Camera Vertical Synchronization
Camera Clock Output a
Camera Clock Output b
Camera digital image data bit 0
Camera digital image data bit 1
Camera digital image data bit 2
Camera digital image data bit 3
Camera digital image data bit 4
Camera digital image data bit 5
Camera digital image data bit 6
Camera digital image data bit 7
Camera digital image data bit 8
Camera digital image data bit 9
Camera digital image data bit 10
Camera digital image data bit 11
Camera field identification
Camera pixel clock
Camera Write Enable
Flash strobe control signal
VBAT.RIGHT - VAUX2.OUT
TYPE
IO
IO
O
O
I
I
I
I
I
I
I
I
I
I
I
I
IO
I
I
O
PIN TDM-3730
145
153
147
143
132
134
148
152
150
151
136
138
142
140
141
137
144
146
149
139
38
The camera ISP can support the following features:
 Image sensor:
o Interface with various image sensors:
 R, G, B primary colors
 Ye, Cy, Mg, G complementary colors
o Support for electronic rolling shutter (ERS) and global-release reset shutters
 CSI1/CCP2B serial interface: The CSI1/CCP2B receiver is compatible with the SMIA
CCP2 specification and the MIPI CSI1 specification.
 Two MIPI CSI2 serial interfaces: The camera ISP implements two MIPI CSI2 serial
interface receivers (CSI2A and CSI2C). The CSI2 receivers enables data transfer at up
to 2Gbps. It is based on the MIPI CSI2 Specification 1.0.
 Parallel interface: The camera parallel interface (CPI) supports two modes:
o SYNC mode: In this mode, the image-sensor module provides horizontal and
vertical synchronization signals to the parallel interface, along with the pixel clock.
This mode works with 8-, 10-, 11-, and 12-bit data (if using CCDC inside the
Video processing hardware above 10 bit data must be internally converted to 10
bit by the Bridge lane shifter). SYNC mode supports progressive and interlaced
image-sensor modules.
o ITU mode: In this mode, the image-sensor module provides an ITU-R BT 656compatible data stream. The horizontal and vertical synchronization signals are
not provided to the interface. Instead, the data stream embeds start-of-active
40
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion









video (SAV) and end-of-active video (EAV) synchronization code. This mode
works in 8- and 10-bit configurations
Video processing hardware: The Video processing hardware removes the need for
expensive camera modules to perform processing functions. It consists of parts: front
end and back end:
o Video processing front end (VPFE)
o Video processing back end (VPBE)
Statistic collection modules (SCM): The host CPU uses statistics to adjust various
parameters for processing image data.
Central-resource shared buffer logic (SBL): Buffers and schedules memory accesses
requested by camera ISP modules
Circular buffer: Prevents storage of full image frames in memory when data must be
post-processed and/or preprocessed by software
Memory management unit (MMU): Manages virtual-to-physical address translation for
external addresses and solves the memory-fragmentation issue. Enables the camera
driver to dynamically allocate and de-allocate memory; the MMU handles memory
fragmentation.
Clock generator: Generates two independent clocks that can be used by two external
image sensors
Timing control:
o Generation clocks passed to the clock generator
o Generation of signals for strobe flash, mechanical shutter, and global reset.
Support for red-eye removal.
Open core protocol (OCP) compliant:
o One 64-bit master interface connected to L3
o One 32-bit slave interface connected to L4
Parallel Camera Interface (CPI)
o Video and Graphics Digitizer 1.8-V Mode: input maximum frequency 148.5
MHz supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion
bridge enabled
o 12-Bit SYNC Normal Progressive Mode: input maximum frequency 75 MHz
supported by the ISP module.
o 8-Bit SYNC Packed Progressive Mode: input maximum frequency 130 MHz
supported by the ISP module.
o 12-Bit SYNC Normal Interlaced Mode: input maximum frequency 75 MHz
supported by the ISP module
o 8-Bit SYNC Packed Interlaced Mode: input maximum frequency 130 MHz
supported by the ISP module.
o ITU Mode: input maximum frequency 75 MHz supported by the ISP module
41
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
8.3 Video Interfaces – DSS Signals Description
The Display Subsystem can support


Color and monochrome displays up to 2048 x 2048 x 24-bpp resolution
256 x 24-bit entries palette in red, green, blue (RGB)
SIGNAL NAME
Dss_pclk
Dss_hsync
Dss_vsync
Dss_acbias
Dss_data0
Dss_data1
Dss_data2
Dss_data3
Dss_data4
Dss_data5
Dss_data6
Dss_data7
Dss_data8
Dss_data9
Dss_data10
Dss_data11
Dss_data12
Dss_data13
Dss_data14
Dss_data15
Dss_data16
Dss_data17
Dss_data18
Dss_data19
Dss_data20
Dss_data21
Dss_data22
Dss_data23
LCD_PON
LCD_ENVDD
LCD ENBKL
LCD PWM
DESCRIPTION
LCD Pixel Clock
LCD Horizontal Synchronization
LCD Vertical Synchronization
AC bias control (STN) or pixel data enable
(TFT) output
LCD Pixel Data bit 0
LCD Pixel Data bit 1
LCD Pixel Data bit 2
LCD Pixel Data bit 3
LCD Pixel data bit 4
LCD Pixel Data bit 5
LCD Pixel Data bit 6
LCD Pixel Data bit 7
LCD Pixel Data bit 8
LCD Pixel Data bit 9
LCD Pixel Data bit 10
LCD Pixel Data bit 11
LCD Pixel Data bit 12
LCD Pixel Data bit 13
LCD Pixel Data bit 14
LCD Pixel Data bit 15
LCD Pixel Data bit 16
LCD Pixel Data bit 17
LCD Pixel Data bit 18
LCD Pixel Data bit 19
LCD Pixel Data bit 20
LCD Pixel Data bit 21
LCD Pixel Data bit 22
LCD Pixel Data bit 23
LCD Enable
LCD Voltage On
LCD Backlight Control
LCD Backlight on/off
42
TYPE
O
O
O
PIN TDM-3730
109
123
113
O
100
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
IO
IO
IO
112
118
114
116
106
110
119
117
115
111
102
104
108
120
122
128
101
107
105
103
121
98
126
124
64
66
30
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The TDM-3730 can easily be connected to a 18 or 24 bit TTL panel by following the following table.
DSS_D
Dss_data0
Dss_data1
Dss_data2
Dss_data3
Dss_data4
Dss_data5
Dss_data6
Dss_data7
Dss_data8
Dss_data9
Dss_data10
Dss_data11
Dss_data12
Dss_data13
Dss_data14
Dss_data15
Dss_data16
Dss_data17
Dss_data18
Dss_data19
Dss_data20
Dss_data21
Dss_data22
Dss_data23
24 bit
B0
B1
B2
B3
B4
B5
B6
B7
B0
G1
G2
G3
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
18 bit
B0
B1
B2
B3
B4
B5
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
8.4 Video Interfaces – TV Signals Description
The video encoder converts RGB video signals to conform to the NTSC/PAL standard analog
video. The video encoder includes an integrated synchronization signal generator and two
single channel video digital-to-analog converters (DACs) with video amplifiers, data manager,
luma stage, chroma stage, modulator, and a control interface.
The output data to the TV set are the analog composite data from the video DAC stage. The
following video standards are supported:



NTSC-J, M
PAL-B, D, G, H, I
PAL-M
SIGNAL NAME
Cvideo1_out
Cvideo2_out
DESCRIPTION
TV analog output Composite: cvideo1_out
TV analog output S-VIDEO: cvideo2_out
43
TYPE
AO
AO
PIN TDM-3730
83
85
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
8.5 Serial Communication Interfaces – I2C Signals Description
The device contains multimaster high-speed (HS) inter-integrated circuit (I2C) ™ controllers),
each of which provides an interface between a local host (LH), such as the microprocessor unit
(MPU) subsystem, and any I2C-bus-compatible device that connects through the I2C serial bus.
External components attached to the I2C bus can serially transmit and receive up to 8 bits of
data to and from the LH device through the 2-wire I2C interface.
Each HS I2C controller can be configured to act like a slave or master I2C-compatible device.
INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)
SIGNAL NAME
I2C2_SCL
DESCRIPTION
I2C Master Serial clock. Output is open drain
I2C Serial Bidirectional Data. Output is open
I2C2_SDA
drain.
Note: These signals have a 4.7kΩ pull up resistor to 1.8 V
TYPE
OD
PIN TDM-3730
78
IOD
76
TYPE
OD
PIN TDM-3730
75
IOD
73
INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)
SIGNAL NAME
I2C3_SCL
DESCRIPTION
I2C Master Serial clock. Output is open drain
I2C Serial Bidirectional Data. Output is open
I2C3_SDA
drain.
Note: These signals have a 4.7kΩ pull up resistor to 1.8 V
8.6 Serial Communication Interfaces – McBSP LP Signals Description
The multichannel buffered serial port (McBSP) provides a full-duplex direct serial interface
between the device and other devices in a system such as other application chips (digital base
band), audio and voice codec, etc. Because of its high level of versatility, it can accommodate to
a wide range of peripherals and clocked frame oriented protocols.
MULTICHANNEL BUFFERED SERIALPORT (McBSP LP 2)
SIGNAL NAME
Mcbsp2_dr
Mcbsp2_dx
Mcbsp2_clkx
Mcbsp2_fsx
DESCRIPTION
Received serial data
Transmitted serial data
Combined serial clock
Combined frame synchronization
TYPE
I
O
IO
IO
PIN TDM-3730
61
59
55
63
TYPE
I
O
IO
IO
PIN TDM-3730
49
53
51
47
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3)
SIGNAL NAME
Mcbsp3_dr
Mcbsp3_dx
Mcbsp3_clkx
Mcbsp3_fsx
DESCRIPTION
Received serial data
Transmitted serial data
Combined serial clock
Combined frame synchronization
44
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8.7 Serial Communication Interfaces – McSPI Signals Description
The multichannel serial port interface (McSPI) is a master/slave synchronous serial bus. The
McSPI modules differ as follows: SPI1 supports up to four peripherals, SPI3 supports up to two
peripherals
The McSPI instances include the following main features:
 Serial clock with programmable frequency, polarity, and phase for each channel
 Wide selection of SPI word lengths ranging from 4 bits to 32 bits
 Up to four master channels or single channel in slave mode
 Master multichannel mode:
o Full duplex/half duplex
o Transmit-only/receive-only/transmit-and-receive modes
o Flexible I/O port controls per channel
o Two direct memory access (DMA) requests (read/write) per channel
 Single interrupt line for multiple interrupt source events
 Power management through wake-up capabilities
 Enable the addition of a programmable start-bit for SPI transfer per channel (start-bit
mode)
 Support start-bit write command
 Support start-bit pause and break sequence
 64 bytes built-in FIFO available for a single channel
 Force CS mode for continuous transfers
MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)
SIGNAL NAME
Mcspi1_clk
Mcspi1_simo
Mcspi1_somi
Mcspi1_cs0
DESCRIPTION
SPI Clock
Slave data in, master data out
Slave data out, master data in
SPI Enable 0, polarity configured by software
TYPE
IO
IO
IO
IO
PIN TDM-3730
41
40
43
45
TYPE
IO
IO
IO
IO
O
PIN TDM-3730
82
77
80
84
81
MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)
SIGNAL NAME
Mcspi3_clk
Mcspi3_simo
Mcspi3_somi
Mcspi3_cs0
Mcspi3_cs1
DESCRIPTION
SPI Clock
Slave data in, master data out
Slave data out, master data in
SPI Enable 0, polarity configured by software
SPI Enable 1, polarity configured by software
45
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8.8 Serial Communication Interfaces – UARTs Signals Description
The module contains two universal asynchronous receiver/transmitter (UART) devices
controlled by the microprocessor unit (MPU):


UART1 is pinned out for use as UART devices only.
UART3, which adds infrared communication support, is pinned out for use as a UART,
infrared data association (IrDA), or consumer infrared (CIR) device, and can be
programmed to any available operating mode.
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)
SIGNAL NAME
Uart1_cts
Uart1_rts
Uart1_rx
Uart1_tx
DESCRIPTION
UART1 Clear To Send
UART1 Request To Send
UART1 Receive data
UART1 Transmit data
TYPE
I
O
I
O
PIN TDM-3730
86
87
92
89
TYPE
I
O
I
O
PIN TDM-3730
53
49
47
51
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)
Multiplex option instead of McBSP3 Signals
SIGNAL NAME
Uart2_cts
Uart2_rts
Uart2_rx
Uart2_tx
DESCRIPTION
UART2 Clear To Send
UART2 Request To Send
UART2 Receive data
UART2 Transmit data
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA
SIGNAL NAME
Uart3_cts_rctx
Uart3_rts_sd
Uart3_rx_irrx
Uart3_tx_irtx
DESCRIPTION
UART3 Clear To Send (input), Remote TX
(output)
UART3 Request To Send, IR enable
UART3 Receive data, IR and Remote RX
UART3 Transmit data, IR TX
46
TYPE
PIN TDM-3730
IO
135
O
I
O
131
129
127
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March 6 2012, TechNexion
8.9 Serial Communication Interfaces – USB Signals Description
The USB Host is connected to the SMSC USB3320
The USB3320 is a highly integrated full featured Hi-Speed USB 2.0 transceiver based on
MCSC’s proven ULPI interface. The USB3320 provides an extremely flexible solution in a
convenient 5 x 5 mm QFN package. It supports a wide variety of different reference clock
frequencies with one single part, as well as accepting clocking from crystal/resonators and the
ULPI 60 MHz Clock-In mode. As with previous generations of SMSC's USB transceivers, the
USB3320 integrates a USB switch and both ESD and VBUS over-voltage protection devices.
Note1: USB 1.1 devices can be connected to the USB 2.0 host port only through a USB 2.0 hub.
Note2: Single USB 1.1 devices can be connected directly to the USB OTG port. This port should
however during boot up always be kept in OTG mode.
Note3: It’s not advisable to connect a hub to the USB OTG port.
Note4: ESD decoupling circuits are advised on all USB devices and ports.
USB Host
SIGNAL NAME
IDM0
IDP0
RESETB
DESCRIPTION
D – pin of the USB cable
D + pin of the USB cable
When low, the part is suspended with all ULPI
outputs tri-stated. When high, the USB3320
will operate as a normal ULPI device
TYPE
IO A
IOA
PIN TDM-3730
35
37
16
The USB OTG is connected to the TPS65930 USB Transceiver
The TPS65930 device includes a USB OTG transceiver that supports USB 480 Mbps HS, 12
Mbps full-speed (FS), and USB 1.5 Mbps low-speed (LS) through a 4-pin ULPI.
The device has a USB OTG transceiver that allows system implementation that complies with
the following specifications:
 Universal Serial Bus 2.0 Specification
 On-The-Go Supplement to the USB 2.0 Specification
 UTMI+ Low Pin Interface Specification
USB OTG
SIGNAL NAME
DESCRIPTION
HSUSB_DN
USB data N/USB carkit transmit data
HSUSB_DP
USB data P/USB carkit receive data
HSUSB_ID
USB ID
VBUS_5V0
Power
Note: It is advised to use USB OTG only for USB OTG
47
TYPE
IO
IO
IO
PWR
PIN TDM-3730
32
34
21
1
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8.10 Removable Media Interfaces – MMC/ SDIO Signals
The multimedia card high-speed/SD/SD I/O (MMC/SD/SDIO) host controller provides an
interface between a local host (LH) such as a microprocessor unit (MPU) or digital signal
processor (DSP) and either MMC, SD memory cards, or SDIO cards and handles
MMC/SD/SDIO transactions with minimal LH intervention.
The application interface manages transaction semantics. The MMC/SD/SDIO host controller
deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic
redundancy checks (CRC), start/end bit, and checking for syntactical correctness.
The application interface can send every MMC/SD/SDIO command and either poll for the status
of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to
warn of end of operation.
The application interface can read card responses or flag registers. It can also mask individual
interrupt sources. All these operations can be performed by reading and writing control registers.
The MMC/SD/SDIO host controller also supports two DMA channels.
SIGNAL NAME
MMC1 CD
MMC1 CLK0
MMC1 CMD
MMC1 DAT0
MMC1 DAT1
MMC1 DAT2
MMC1 DAT3
MMC1 WP
VMMC1
DESCRIPTION
Card Detection1
MMC/SD Output Clock
MMC/SD command signal
MMC/SD Card Data bit 0 / SPI Serial Input
MMC/SD Card Data bit 1
MMC/SD Card Data bit 2
MMC/SD Card Data bit 3
MMC Write Protect
Power 1V8/ 3V3
TYPE
IO
O
IO
IO
IO
IO
IO
IO
O
PIN TDM-3730
20
95
99
97
96
94
93
88
39
8.11 General Purpose IOs Signals Description
By using Multiplexing a maximum of 125 pins on the module can be turned into GPIOs. By
default the following GPIOs are already acting as GPIO as first function and do not need any
software configuration.
SIGNAL NAME
GPIO 12
GPIO 13
GPIO 18
GPIO 19
GPIO 20
GPIO_137
DESCRIPTION
General-purpose IO 12
General-purpose IO 13
General-purpose IO 18
General-purpose IO 19
General-purpose IO 20
General-purpose IO 137
TYPE
IO
IO
IO
IO
IO
IO
PIN TDM-3730
68
72
74
69
90
65
TYPE
IO
IO
PIN TDM-3730
28
15
GPIOs Signals Description
SIGNAL NAME
DVI_nDISABLE
HOST nOC
DESCRIPTION
DVI/ Backlight control
HOST nOC
48
TDM-3730 HARDWARE MANUAL rev A
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8.12 Test Interfaces – JTAG Signals Description
The target debug interface of the device uses the five standard IEEE 1149.1 (JTAG) signals
(nTRST, TCK, TMS, TDI, and TDO), a return clock (RTCK) to meet the clocking requirements of
the ARM968 processor, and two instrumentations pins (EMU0, EMU1).
Schematic of the JTAG signals
49
TDM-3730 HARDWARE MANUAL rev A
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See Photo for the location of the solder pads. Solder at the orange pads
SIGNAL NAME
Jtag_ntrst
Jtag_tck
Jtag_rtck
Jtag_tms_tmsc
Jtag_tdi
Jtag_tfo
Jtag_emu0
Jtag_emu1
DESCRIPTION
Test reset
Test Clock
ARM Clock emulation
Test Mode Select
Test Data Input
Test data Output
Test emulation 0
Test emulation 1
TYPE
I
I
O
IO
I
O
IO
IO
50
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8.13 Power Supplies Signals description
Power Supply Signals
SIGNAL NAME
DESCRIPTION
TYPE PIN TDM-3730
DC 5V
Power 5V
I
2
DC 5V
Power 5V
I
4
DC 5V
Power 5V
I
6
DC 5V
Power 5V
I
8
DC 5V
Power 5V
I
10
DC 5V
Power 5V
I
12
VBUS_5V
Power 5V
I
1
VIO_1V8
Power 1V8
O
27
VIO_1V8
Power 1V8
O
29
VIO_1V8
Power 1V8
O
31
VIO_1V8
Power 1V8
O
33
VMMC1
Power 1V8/ 3V3
O
39
Note1: All input 5V signals should be connected to the main 5V input power circuit. There is an
acceptable tollerance of +/-5%.
Note2: The output 3V3 signals current is limited and therefore it’s advisable to generate 3V3
voltage on the baseboard for optimal operation.
Ground Signals
SIGNAL NAME
DESCRIPTION
TYPE PIN TDM-3730
GND
Power Ground
GND 3
GND
Power Ground
GND 19
GND
Power Ground
GND 79
GND
Power Ground
GND 125
GND
Power Ground
GND 167
GND
Power Ground
GND 177
GND
Power Ground
GND 199
GND
Power Ground
GND 70
GND
Power Ground
GND 130
GND
Power Ground
GND 168
GND
Power Ground
GND 180
GND
Power Ground
GND 200
Note 1: All GND pins must be connected and should not remain not connected .
Note 2: On a custom baseboard. Please connect GND signals to the mounting pose/nuts which
are used to lock the module to the baseboard.
8.14 System and Miscellaneous Signals Description
SIGNAL NAME
DESCRIPTION
TYPE PIN TDM-3730
SYS_CLKOUT1
Configurable Output Clock 1
O
71
SYS_nRESPWRON Power On Reset
I
14
SYSEN
System enable output
D
17
SYS_nRESPWRON will reset the module when pulled low, it will reset DM-3730, TPS65930,
LAN controller, USB PHYand WiFi simultaneously.
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8.15 Touch Interupt Signal Description
SIGNAL NAME
TS_nPEN_IRQ
DESCRIPTION
Touch Interrupt
TYPE
IO
PIN TDM-3730
67
8.16 Serial Communcication Interfaces – HDQ/ 1-Wire Signals Description
The HDQ/1-Wire module implements the hardware protocol of the master functions of the
Benchmarq HDQ and the Dallas Semiconductor 1-Wire® protocols. These protocols use a
single wire for communication between the master (HDQ/1-Wire controller) and the slaves
(HDQ/1-Wire external compliant devices).
SIGNAL NAME
Hdq_SIO
DESCRIPTION
Bidirectional HDQ 1-Wire control and data
Interface. Output is open drain.
TYPE
PIN TDM-3730
IOD
133
TYPE
PIN TDM-3730
I
13
8.17 PWM Signals Description
SIGNAL NAME
PWR_ON
DESCRIPTION
Input; detect a control command to start or
stop the system
PWM Option on the TPS65930 instead of DVI_nDISABLE & LCD ENBKL
SIGNAL NAME
DESCRIPTION
TYPE
PWM1
Pulse width driver
O
PWM0
Pulse width driver 0
O
PIN TDM-3730
28
30
8.18 ADC Signals Description
SIGNAL NAME
ADCIN2
CHRG STATE
DESCRIPTION
General –purpose ADC Input
Battery type
52
TYPE
I
IO
PIN TDM-3730
36
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TDM-3730 HARDWARE MANUAL rev A
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8.19 Analog Audio Signals Description
ANA.MIC Signals Description
SIGNAL NAME
Mic_main_M
Mic_main_P
DESCRIPTION
Main microphone left input (M)
Main microphone left input (P)
TYPE
I
I
PIN TDM-3730
23
11
TYPE
PWR
GND
PIN TDM-3730
25
9
TYPE
PIN TDM-3730
O
7
O
5
TYPE
I
PIN TDM-3730
24
VMIC BIAS Signals Description
SIGNAL NAME
MIC_BIAS
MICBIAS_G
DESCRIPTION
Analog microphone bias 1
Dedicated ground for microphones
Headset Signals description
SIGNAL NAME
PreDriv.LEFT
PreDriv.RIGHT
DESCRIPTION
Predriver output left P for external class-D
amplifier
Predriver output right P for external class-D
amplifier
AUX input Signals Description
SIGNAL NAME
AUXR
DESCRIPTION
Auxiliary audio input right
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8.20 Keypad Signals Description
The TDM-3730 supports a keypad interface up to a matrix of 6 x 6
When a key button of the keyboard matrix is pressed, the corresponding row and column lines
are shorted together. To allow key press detection, all input pins (KBR) are pulled up to VCC
and all output pins (KBC) are driven to a low level.
Any action on a button generates an interrupt to the sequencer.
The decoding sequence is written to allow detection of simultaneous press actions on several
key buttons.
The keyboard interface can be used with a smaller keyboard area than 6 × 6. To use a 3 × 3
keyboard, KBR(4) and KBR(5) must be tied high to prevent any scanning process distribution.
SIGNAL NAME
KPD.C0
KPD.C1
KPD.C2
KPD.C3
KPD.C4
KPD.C5
KPD.R0
KPD.R1
KPD.R2
KPD.R3
KPD.R4
KPD.R5
DESCRIPTION
Keypad column 0
Keypad column 1
Keypad column 2
Keypad column 3
Keypad column 4
Keypad column 5
Keypad row 0
Keypad row 1
Keypad row 2
Keypad row 3
Keypad row 4
Keypad row 5
TYPE
D
D
D
D
D
D
I
I
I
I
I
I
54
PIN TDM-3730
50
48
46
44
42
91
60
58
56
54
52
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8.21 Ethernet Signals Description
TDM-3730 contains a SMSC LAN9220 Single chip Ethernet controller with the following
features:










Fully compliant with IEEE 802.3/802.3u standards
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and Half-duplex support
Full-duplex flow control
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
SIGNAL NAME
ETHER_RXN
ETHER_RXP
ETHER_TXN
ETHER_TXP
LANLED_LINK
LANLED_SPD
DESCRIPTION
Receive Negative Input (normal)
Receive Positive Input (normal)
Transmit Negative Output (normal)
Transmit Positive Output (normal)
Link and Activity Indicator
Speed Indicator
TYPE
AI
AI
AO
AO
O
D
PIN TDM-3730
195
197
191
193
198
196
TYPE
D
PIN TDM-3730
18
8.22 LED Signals Description
SIGNAL NAME
LEDA
DESCRIPTION
User definable LED Indicator
The TDM-3730 System on Module contains 5 onboard LEDs with following functions:
LED NAME
LED1
LED2
LED3
LED4
LED5
DESCRIPTION
Power ON
Power: System works
WiFi: Active
LAN: Active
Power ON
55
TDM-3730 HARDWARE MANUAL rev A
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8.23 Pull-up or Pull-down Signals Description
Pin #
73
75
76
78
Signal Name
I2C3_sda
GPIO_185
Safe mode
I2C3 SCL
GPIO_184
safemode
I2C2 SDA
GPIO_183
Safe_mode
I2C2 SCL
GPIO_168
Safe_mode
Mode
0
4
7
0
4
7
0
4
7
0
4
7
Voltage
Resistor
Pull up/down
1.8
4.7kΩ
Up
1.8
4.7kΩ
Up
1.8
4.7kΩ
Up
1.8
4.7kΩ
Up
8.24 Boot Option
SIGNAL NAME
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
DESCRIPTION
1
1
1
1
0
Boot configuration mode bit 5
1
56
TYPE
PIN TDM-3730
I
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9 Electrical Characteristics
PARAMETER
MMC Interface 3.0-V Mode
High-level input voltage
VIH
Low-level input voltage
VIL
High-level output voltage with 100-μA sink
VOH
current IOH
Low-level output voltage with 100-μA source
VOL
current at vdds_mmc1 minimum
MIN
PARAMETER
GPIO 1.8-V Mode
High-level input voltage
VIH
Low-level input voltage
VIL
High-level output voltage with 100-μA sink
VOH
current IOH
Low-level output voltage with 100-μA source
VOL
current at vdds_mmc1 minimum
MIN
PARAMETER
Recommended Operating Conditions
Supply voltage for 1.8-V I/O macros
Vdds
Vdds_mem Supply voltage for memory buffers
1.8-V mode
Vdds_mmc1 Supply voltage
range for mmc1
3.0-V mode
dual voltage IOs
Supply voltage
1.8-V mode
Vdds_x
range for x dual
3.0-V mode
voltage IOs
Analog supply voltage for Video DAC
Vdda_dac
The Supply Voltage to the module is 5V ±5%
57
NOM
MAX
UNIT
3.3
0.75
V
V
V
0.375
V
MAX
UNIT
1.26
-0.3
1.44
2.1
0.36
2.1
V
V
V
-0.3
0.4
V
1.875
-0.3
2.25
NOM
MIN
NOM
MAX
UNIT
1.71
1.71
1.71
2.70
1.91
1.91
1.91
3.60
V
V
V
1.71
2.70
1.8
1.8
1.8
3.00 to
3.30
1.8
3.00
1.91
3.60
V
1.71
1.8
1.91
V
TDM-3730 HARDWARE MANUAL rev A
March 6 2012, TechNexion
10 Environmental Specifications
Temperature
Humidity
Dimensions
MTBF
Weight
Shock
Vibration
Commercial: 0° to 70° C
Extended: -20° to 70° C (no WiFi)
Industrial: -40° to 85° C (no WiFi)
10-90%
67.6x 50x 3.4 mm (2⅝x 2x ¼ inch)
>100,000 hours
12 grams
50G / 25ms
20G / 0-600 Hz
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11 Mechanical Dimensions
11.1 TDM-3730 System on Module Dimensions
Dimensions in mm
Note: 2D (DXF) and 3D(STEP) files are available for download at the Technexion website.
(Service and support/ Downloads/ ARM CPU Modules/ TDM-3730)
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12 Module Connection
12.1 Module Connector DDR2 SO-DIMM
To mount the TDM-3730 module on the baseboard it isrecommended to use a connector with
the following specifications:



DDR II SO-DIMM 200pin SMT
Standard
height 6.5 mm
For example Foxconn AS0A426-N6SN-4F or Tyco 5-1746530-4
If you have difficulty purchasing these parts please contact [email protected], for
assistance.
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12.2 Nut to Fix TDM-3730 Module to the Baseboard
Note 1: Always design the above mounting nut/pose on your custom baseboard and fasten the
TDM-3730 to ensure a solid connection and counter vibration prone applications.
Note 2: On a custom baseboard always connect the mounting nut/pose to the baseboard
general system GND section.
If you have difficulty purchasing these parts please contact [email protected], for
assistance.
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13 Disclaimer
TechNexion reserve the right to make corrections, modifications, enhancements, improvements, and
other changes to its products and services at any time and to discontinue any product or service without
notice. Customers should obtain the latest relevant information before placing orders and should verify
that such information is current and complete. All products are sold subject to TechNexion terms and
conditions of sale supplied at the time of order acknowledgment.
TechNexion warrants performance of its hardware products to the specifications applicable at the time of
sale in accordance with TechNexion’s standard warranty. Testing and other quality control techniques are
used to the extent TechNexion deems necessary to support this warranty. Except where mandated by
government requirements, testing of all parameters of each product is not necessarily performed.
TechNexion assumes no liability for applications assistance or customer product design. Customers are
responsible for their products and applications using TechNexion components. To minimize the risks
associated with customer products and applications, customers should provide adequate design and
operating safeguards.
TechNexion does not warrant or represent that any license, either express or implied, is granted under
any TechNexion patent right, copyright, mask work right, or other TechNexion intellectual property right
relating to any combination, machine, or process in which TechNexion products or services are used.
Information published by TechNexion regarding third-party products or services does not constitute a
license from TechNexion to use such products or services or a warranty or endorsement thereof. Use of
such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TechNexion under the patents or other intellectual property of
TechNexion.
TechNexion products are not authorized for use in safety-critical applications (such as life support) where
a failure of the TechNexion product would reasonably be expected to cause severe personal injury or
death, unless officers of the parties have executed an agreement specifically governing such use. Buyers
represent that they have all necessary expertise in the safety and regulatory ramifications of their
applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and
safety-related requirements concerning their products and any use of TechNexion products in such
safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TechNexion. Further, Buyers must fully indemnify TechNexion and its representatives against
any damages arising out of the use of TechNexion products in such safety-critical applications.
TechNexion products are neither designed nor intended for use in military/aerospace applications or
environments unless the TechNexion products are specifically designated by TechNexion as militarygrade or "enhanced plastic." Only products designated by TechNexion as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TechNexion products which
TechNexion has not designated as military-grade is solely at the Buyer's risk, and that they are solely
responsible for compliance with all legal and regulatory requirements in connection with such use.
TechNexion products are neither designed nor intended for use in automotive applications or
environments unless the specific TechNexion products are designated by TechNexion as compliant with
ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TechNexion will not be responsible for any failure to meet such
requirements.
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14 Warranty
TechNexion hardware products are warranted against defects in materials and workmanship. If
TechNexion receives notice of such defects during the warranty period, TechNexion shall, at its
option, either repair or replace hardware products that prove to be defective.
1. Warranty Period
The warranty period shall commence on the invoice date. For TechNexion equipment
the standard warranty period shall be two-year parts and labor.
2.
Warranty Coverage
2.1 This warranty does not apply to any Products that have been repaired or altered by
other than TechNexion authorized service person or, which have been subjected to
misuse, abuse, accident, or improper installation. TechNexion assumes no liability as a
consequence of such events under the terms of this warranty.
2.2 This warranty does not cover the damage due to the shipping of the Products and
external causes, including accident, abuse, misuse or problems with electrical power,
usage not in accordance with product instruction, and problems caused by use of parts
and components not supplied by TechNexion upon request.
2.3 This warranty does not cover any items that are in one or more of the following
categories:
a. Software and/or device drivers,
b. External devices,
c. Accessories or parts added to Products after the Products shipped from TechNexion
and, Accessories, or parts that are not assembled in TechNexion facilities.
d. All warranty is voided if the TechNexion warranty label or serial number is removed,
illegible, or missing
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15 Contact Information
TechNexion Headquarters:
Address:
17F-1, No. 16, Jian Ba Road,
Chung Ho City, 23511, Taipei, Taiwan
E-mail:
[email protected]
Website:
www.technexion.com
Telephone:
+886-2-8227 3585
Fax:
+886-2-8227 3590
64
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