Renesas | Renasas Single-Chip Microcomputer SH7086 | A/D Conversion in Single-cycle Scan Mode

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APPLICATION NOTE
SH7080 Group
A/D Conversion in Single-cycle Scan Mode
Introduction
This application note describes the single-cycle scan mode of A/D conversion. It is intended as reference material to
help in the design of user software.
Target Device
SH7086
Contents
1.
Specification...................................................................................................................................... 2
2.
Applicable Conditions ....................................................................................................................... 3
3.
Description of Modules Used ............................................................................................................ 4
4.
Principles of Operation...................................................................................................................... 7
5.
Description of Software................................................................................................................... 10
6.
Flowchart......................................................................................................................................... 15
7.
Documents for Reference (Note) .................................................................................................... 17
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
1.
Specification
In this sample application, the A/D converter for the SH7086 performs A/D conversion in single-cycle scan mode.
Three rounds of A/D conversion proceed on analog input channels 0 to 3 (AN0 to AN3). Converted data are stored in
the on-chip RAM. An overview of the operation is shown in figure 1.
On-chip RAM (24 bytes)
First round
of converted
data
ADDR0 data
2 bytes
ADDR1 data
2 bytes
ADDR2 data
2 bytes
ADDR3 data
ADDR0 data
A/D data registers 0 to 3
(ADDR0 to ADDR3)
Second round
of converted
data
ADDR1 data
ADDR2 data
ADDR3 data
Each holds 2 bytes.
ADDR0 data
Third round
of converted
data
ADDR1 data
ADDR2 data
ADDR3 data
Figure 1 Overview of A/D Conversion
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January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
2.
Applicable Conditions
The applicable conditions for this sample application are shown in table 1.
Table 1
Applicable Conditions
Item
Setting
Device
Operating frequency
SH7086 (R5F70865)
Internal clock: Iφ = 80 MHz
Bus clock: Bφ = 40 MHz
Peripheral clock: Pφ = 40 MHz
MTU2 clock: MPφ = 40 MHz
MTU2S clock: MIφ = 80 MHz
Single-chip mode
Renesas Technology products:
High-performance Embedded Workshop Version 4.03.00.001 (integrated
development environment)
SuperH RISC engine Standard Toolchain (V.9.1.1.0)
SuperH RISC engine C/C++ Compiler (V.9.01.01)
High-performance Embedded Workshop default settings:
[ -cpu=sh2 -object="$(CONFIGDIR)\$(FILELEAF).obj" -debug -gbr=auto chgincpath -errorpath -global_volatile=0 -opt_range=all -infinite_loop=0 del_vacant_loop=0 -struct_alloc=1 -nologo ]
Operating mode
Development environment
C compiler options
REJ06B0699-0100/Rev.1.00
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
3.
Description of Modules Used
In this sample application, A/D converter channels 0 to 3 are used for A/D conversion.
The functions of the SH7080 group A/D converter are outlined in table 2.
Table 2
A/D Converter Function Overview
Item
Overview
Resolution
Input channels
10 bits
Interrupt source
Others
•
•
•
•
•
•
•
•
•
8 channels (2 independent A/D conversion modules on chip) for the SH7083/84/85
16 channels (3 independent A/D conversion modules on chip) for the SH7086
Conversion time
2.0 µs per channel (when Pφ = 25 MHz)
Operation mode
Single mode: A/D conversion on one channel
Continuous scan mode: A/D conversion repeated on up to 4 channels for the
SH7083/84/85 or up to 8 channels for the SH7086
• 1-cycle scan mode: A/D conversion repeated on up to 4 channels for the
SH7083/84/85 or up to 8 channels for the SH7086
Data register
Results of A/D conversion are stored in 16-bit data registers corresponding to the
respective input channels.
A/D conversion start • Operation of the A/D control register (ADCR) by software
method
• A/D converter start trigger from the multi-function timer pulse unit 2 (MTU2) or 2S
(MTU2S) can be selected.
• External trigger signal
A/D conversion end interrupt request (ADI)
Sample & hold functions are provided.
Module standby mode can be set.
DMAC/DTC can be started by an interrupt.
REJ06B0699-0100/Rev.1.00
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
A block diagram of the A/D converter is shown in figure 2.
AVss
Internal data bus
Pφ
+
ANm
Bus interface
ADDRn
ADCSR
converter
ADTSR
10-bit D/A
ADCR
AVref
ADDRm
AVcc
Sequential comparison register
Module data bus
Multiplexer
Pφ/2
Comparator
Control circuit
Pφ/3
Sample &
hold circuit
Pφ/4
ANn
ADI interrupt signal
Conversion trigger from MTU2/MTU2S
ADTRG
[Legend]
AVcc
AVref
AVss
ANm to ANn
ADCR
ADCSR
ADTSR
ADDRm/n
: Power supply pin or reference voltage in the analog portion
: Reference voltage for A/D conversion
: Ground or reference voltage in the analog portion
: Analog input pins
: A/D control register
: A/D control/status register
: A/D trigger select register
: A/D data register m/n
Note: The register number corresponds to the channel number of modules.
(m/n = 0 to 7 for the SH7083/84/85 and 0 to 15 for the SH7086)
Figure 2 A/D Converter Block Diagram (One Module)
REJ06B0699-0100/Rev.1.00
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
• The A/D data registers (ADDRm and ADDRn) are 16-bit read-only registers which hold the results of conversion
on the corresponding analog input channels. Converted data are stored in bits 15 to 6 of ADDR. The 6 lower bits are
always 0.
• The A/D control register (ADCR) controls the start of A/D conversion.
• The A/D control/status register (ADCSR) controls A/D conversion and sets the A/D conversion time.
• The A/D trigger select register (ADTSR) enables an external trigger to start A/D conversion.
Note: For details on the operational specifications, refer to the section on A/D converter (ADC) in the SH7080 Group
Hardware Manual.
REJ06B0699-0100/Rev.1.00
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
4.
Principles of Operation
In this sample application, A/D conversion is performed three times in single-cycle scan mode on each of analog input
channels 0 to 3 (AN0 to AN3). Converted data are stored in the on-chip RAM on completion of each round of
conversion on all channels. Figure 3 is a timing diagram of operations in this sample application.
In single-cycle mode, A/D conversion starts when the ADST bit is set to 1. On completion of conversion for the
specified number of channels, the ADST bit is automatically cleared and the ADF bit is automatically set to 1. In this
sample application, three rounds of A/D conversion are performed. The ADF bit is cleared on completion of A/D
conversion. Then ADST bit is set to1 and the remaining two rounds of A/D conversion are performed.
First round of
A/D conversion
Second round of
A/D conversion
Third round of
A/D conversion
ADST
A/D converter
Standby
A/D conversion
Standby
A/D conversion
Standby
A/D conversion
Standby
ADF
Figure 3 Operational Timing for A/D Conversion
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
A more detailed view of the timing is given in figure 4. Processing at the numbered points is described in table 3.
Firstly, the mode, channel, clock, etc., are selected with ADCSR_0 and ADCR_0 ((1) in figure 4).
Then, the ADST bit in ADCR_0 is set to 1 to start A/D conversion (figure 4, (2) and (3)). At the end of each round of
A/D conversion on all the channels (0 to 3), the converted data are stored in bits 15 to 6 of the corresponding register
from ADDR0 to ADDR3 (figure 4, (4)). The ADF bit is set to 1 after conversion on all channels has been completed
(figure 4, (5)). Also, the ADST bit is cleared to 0 (figure 4, (6)). In single-cycle scan mode, A/D conversion is
performed only once on each specified channel (in this sample application, A/D conversion is performed once on each
of the channels AN0 to AN3). After that, the ADF flag of ADCSR_0 is cleared to 0 (figure 4, (7)) and data from all the
four registers are stored in the on-chip RAM (figure 4, (8)).
Steps (2) to (8) shown in figure 3 are repeated twice (figure 4, (9) and (10)).
ADST
A/D
converter
Standby
A/D conversion
Standby
ADF
A/Dconverted
data (AN0)
ADDR0
A/Dconverted
data (AN1)
ADDR1
A/Dconverted
data (AN2)
ADDR2
ADDR3
A/Dconverted
data (AN3)
A/Dconverted
data (AN2)
A/Dconverted
data (AN3)
(1)
(2)
(3)
(4)
(5) (7)
(6)
(8)
Third round of A/D conversion
A/Dconverted
data (AN1)
Second round of A/D conversion
A/Dconverted
data (AN0)
On-chip RAM
(9)
(10)
Figure 4 Details on the Timing of A/D Conversion
REJ06B0699-0100/Rev.1.00
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
Table 3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Processing
Software processing
ADCSR_0 and ADCR_0 are used to select
the mode, channel, clock, etc.
Setting the ADST bit of ADCR_0 to 1.




Clearing the ADF bit of ADCSR_0 to 0.
Storing data from the registers ADDR0 to
ADDR3 in the RAM.
Repeating steps (2) to (8) (to perform A/D
conversion a second time).
Repeating steps (2) to (8) (to perform A/D
conversion a third time).
REJ06B0699-0100/Rev.1.00
Hardware processing

Starting A/D conversion on input channel AN0.
Sampling the analog inputs and performing conversion.
After conversion storing converted data in registers
from ADDR0 to ADDR3.
Setting the ADF bit of ADCSR_0 to 1.
Clearing the ADST bit to 0.


Repeating steps (2) to (8) (to perform A/D conversion a
second time).
Repeats steps (2) to (8) (to perform A/D conversion a
third time).
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
5.
Description of Software
5.1
List of Functions
The functions of this sample application are listed below.
Table 4
List of Functions
Function Name
Description
main()
Initializes A/D converter module 0 and calls the A/D conversion routine.
ad_conv()
Starts A/D conversion and stores the results of conversion in the on-chip RAM.
5.2
Variables Used
The variables used in this sample application are listed below.
Table 5
List of Variables
Variable/Label Name
Description
Unsigned short Ad_data[AD][CH] Array (2 bytes) for storing A/D-converted data.
AD indicates the number of rounds of A/D conversion, i.e.
3 in this sample application.
CH indicates the number of channels, i.e. 4 in this sample
application.
Unsigned char ad_count
A/D conversion counter
Unsigned char ch_count
A/D conversion channel number counter
5.3
Referring
function
ad_conv()
ad_conv()
ad_conv()
Section Assignment
Section assignment for this sample application is as follows.
Table 6
Section Assignment
Address
H'00000000
Section Name
DVECTTBL, DINTTBL,
PIntPRG
H'00000800
H'00001000
PResetPRG
P, C$BSEC, C$DEC, D
H'FFFF4000
B, R
H'FFFFBC00
S
REJ06B0699-0100/Rev.1.00
Description
DVECTTBL: Exception vector table
DINTTBL: Interrupt vector table
PIntPRG: Interrupt program
Reset program
P: Program area
C$BSEC: Stores an address for B section initialization.
C$DEC: Stores an address for D section initialization.
D: Stores data.
B: uninitialized data area
R: initialized data
Stack area
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
5.4
Register Settings
The registers used in this sample application are described below. The settings below are the values used in this sample
application and differ from the initial values.
5.4.1
(1)
Clock Oscillator (CPG) Settings
Frequency Control Register (FPQCR)
Function: Specifies the division ratios for the frequency output by the PLL circuit.
Set value: H'0241
Bit
15
14 to 12
Bit Name

IFC[2:0]
Set Value
0
000
11 to 9
BFC[2:0]
001
8 to 6
PFC[2:0]
001
5 to 3
MIFC[2:0]
000
2 to 0
MPFC[2:0]
001
REJ06B0699-0100/Rev.1.00
Description
Reserved
Frequency division ratio of the internal clock (Iφ) frequency
000: × 1 (Iφ = 80 MHz for an input clock frequency of 10 MHz)
Frequency division ratio of the bus clock (Bφ) frequency
001: × 1/2 (Bφ = 40 MHz for an input clock frequency of 10 MHz)
Frequency division ratio of the peripheral clock (Pφ) frequency
001: × 1/2 (Pφ = 40 MHz for an input clock frequency of 10 MHz)
Frequency division ratio of the MTU2S clock (MIφ) frequency
000: × 1 (MIφ = 80 MHz for an input clock frequency of 10 MHz)
Frequency division ratio of the MTU2 clock (MPφ) frequency
001: × 1/2 (MPφ = 40 MHz for an input clock frequency of 10 MHz)
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
5.4.2
(1)
Low Power Mode Settings
Standby Control Register 4 (STBCR4)
Function: Controls the operation of individual modules in low-power-consumption mode.
Set value: H'FE
Bit
7
Bit Name
MSTP23
Set Value
1
6
MSTP22
1
5
MSTP21
1
4, 3

All 1
2
MSTP18
1
1
MSTP17
1
0
MSTP16
0
REJ06B0699-0100/Rev.1.00
Description
Module stop bit 23.
When set to 1, stops the clock supply to the MTU2S. When set to 0,
makes the MTU2S operate.
Module stop bit 22.
When set to 1, stops the clock supply to the MTU2. When set to 0, makes
the MTU2 operate.
Module stop bit 21.
When set to 1, stops the clock supply to the CMT. When set to 0, makes
the CMT operate.
Reserved
Module stop bit 18.
When set to 1, stops the clock supply to the AD_2. When set to 0, makes
the AD_2 operate.
Module stop bit 17.
When set to 1, stops the clock supply to the AD_1. When set to 0, makes
the AD_1 operate.
Module stop bit 16.
When set to 1, stops the clock supply to the AD_0. When set to 0, makes
the AD_0 operate.
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A/D Conversion in Single-cycle Scan Mode
5.4.3
(1)
A/D Conversion Settings
A/D Control/Status Register _0 (ADCSR_0)
Function: Controls A/D conversion and sets A/D conversion time.
Set value: H'0013
Bit
15
Bit Name
ADF
Set Value
0
Description
A/D end flag
A status flag which indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion on all channels is completed in scan mode.
[Clearing conditions]
• When 0 is written after reading it as 1.
• When DMAC/DTC is activated by an ADI interrupt and ADDR is
read.
14
ADIE
0
13, 12
11

TRGE
All 0
0
A/D interrupt (ADI) enable
When set to 1, generation of an ADI interrupt by ADF is enabled.
Reserved
10
9

CONADF
0
0
8
STC
0
State control
Sets A/D conversion time (50 states for this sample application).
7, 6
CKSL[1:0]
00
5, 4
ADM[1:0]
01
3
ADCS
0
2 to 0
CH[2:0]
011
Clock select bits 1 and 0
Set A/D conversion time (Pφ/4 for this sample application).
A/D mode bits 1 and 0
Select A/D conversion mode (4-channel scan mode for this sample
application).
A/D continuous scan (single-cycle scan mode for this sample
application)
Channel select bits 2 to 0
Select analog input channels for A/D conversion (channels AN0 to
AN3 for this sample application).
REJ06B0699-0100/Rev.1.00
Trigger enable
When TRGE = 0, the A/D conversion trigger is disabled.
Reserved
ADF control
Controls ADF operation in 2-channel scan mode.
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A/D Conversion in Single-cycle Scan Mode
(2)
A/D Control Register _0 (ADCR_0)
Function: Controls the start of A/D conversion.
Set value: H'0000
Bit
Bit Name
Set Value
Description
15, 14
13

ADST
All 0
0
12 to 0

All 0
Reserved
A/D start.
When cleared to 0, the A/D conversion is stopped and the A/D
converter enter the idle state.
When set to 1, A/D conversion is started.
Cleared automatically in single mode upon completion of A/D
conversion on the selected channel.
Reserved
(3)
A/D Trigger Select Register _0 (ADTSR_0)
Function: Enables an external trigger for the start of A/D conversion.
Set value: H'0000 (initial value)
This sample application does not use an external trigger. Thus, this register is not set and its initial values are used as-is.
Bit
15 to 12
Bit Name
Initial Value
TRG11S[3:0] 0000
11 to 8
TRG01S[3:0] 0000
7 to 4
TRG1S[3:0]
0000
3 to 0
TRG0S[3:0]
0000
REJ06B0699-0100/Rev.1.00
Description
A/D Trigger 1 Group 1 Select 3 to 0.
Select an external trigger, MTU2 trigger or MTU2S trigger to start
A/D conversion for group 1 when A/D module 1 is in 2-channel
scan mode.
A/D Trigger 0 Group 1 Select 3 to 0.
Select an external trigger, MTU2 trigger or MTU2S trigger to start
A/D conversion for group 1 when A/D module 0 is in 2-channel
scan mode.
A/D Trigger 1 Select 3 to 0.
Select an external trigger, MTU2 trigger or MTU2S trigger to start
A/D conversion for A/D module 1.
A/D Trigger 0 Select 3 to 0.
Select an external trigger, MTU2 trigger or MTU2S trigger to start
A/D conversion for A/D module 1.
January 2008
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SH7080 Group
A/D Conversion in Single-cycle Scan Mode
6.
Flowchart
A flowchart for this sample application is shown below.
6.1
Main Routine
main ()
Initialize A/D
conversion counter
Initialize A/C
conversion
channel numbers
Set the frequency
control register
(FRQCR)
Internal clock: 80 MHz
Bus clock: 40 MHz
Peripheral clock: 40 MHz
MTU2S clock: 80 MHz
MTU2 clock: 40 MHz
Set the standby
control register 4
(STBGR4)
Set MSTP16 of STBCR4 to 0.
[Function]
Supplying clocks to A/D_0.
Set the A/D
Control/Status
Register 0
(ADCSR_0)
Set the A/D
Control/Status
Register 0 (ADCR_0)
ad_conv ()
- Clear the A/D end flag (ADF) to 0.
[Function]
Clearing the A/D end flag.
- Clear the A/D interrupt enable bit (ADIE) to 0.
[Function]
Disabling ADI interrupt.
- Clear the trigger enable bit (TRGE) to 0.
[Function]
Disabling trigger for starting A/D conversion.
- Clear the state control bit (STC) to 0.
[Function]
Setting A/D conversion time to 50 states.
- Set the clock select bits (CKSL) to 00.
[Function]
Setting A/D conversion time to Pφ/4.
- Set the A/D mode bits (ADM) to 01.
[Function]
Setting A/D conversion mode to 4-channel scan mode.
- Clear the A/D continuous scan bit (ADCS) to 0.
[Function]
Setting single-cycle scan mode.
- Set channel select bits (CH) to 011.
[Function]
Setting channels to AN0-AN3.
Clear the A/D start bit (ADST) to 0.
Perform A/D conversion and store the result to the RAM.
ad_conv ()
ad_conv ()
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A/D Conversion in Single-cycle Scan Mode
6.2
A/D Conversion Routine
ad_conv ()
Set ADST of ADCR_0 to 1.
[Function]
Starting A/D conversion.
Start A/D conversion.
Is A/D
conversion
ended?
No
Repeat loop until ADF of ADCSR_0 is set to 1.
[Function]
Remaining in standby mode until A/D conversion
is ended.
Yes
Clear ADF bit.
Store AD data (AN0)
in RAM.
Increment channel
number counter.
Store AD data (AN1)
in RAM.
Increment channel
number counter.
Store AD data (AN2)
in RAM.
Increment channel
number counter.
Store AD data (AN3)
in RAM.
Clear ADF bit of ADCSR_0 to 0.
Store A/D-converted data (in ADDR0) in
RAM (Ad_data).
Increment channel number counter
(ch_count).
Store A/D-converted data (in ADDR1) in
RAM (Ad_data).
Increment channel number counter
(ch_count).
Store A/D-converted data (in ADDR2) in
RAM (Ad_data).
Increment channel number counter
(ch_count).
Store A/D-converted data (in ADDR3) in
RAM (Ad_data).
Clear channel
number counter.
Clear channel number counter (ch_count)
for next round of A/D conversion.
Increment A/D
conversion counter.
Increment conversion counter (ad_count)
for three rounds of A/D conversion.
End
REJ06B0699-0100/Rev.1.00
January 2008
Page 16 of 19
SH7080 Group
A/D Conversion in Single-cycle Scan Mode
7.
Documents for Reference (Note)
• Software Manual
SH-1/SH-2/SH-DSP Software Manual
The most up-to-date version of this document is available on the Renesas Technology Website.
• Hardware Manual
SH7080 Group Hardware Manual
The most up-to-date version of this document is available on the Renesas Technology Website.
REJ06B0699-0100/Rev.1.00
January 2008
Page 17 of 19
SH7080 Group
A/D Conversion in Single-cycle Scan Mode
Website and Support
Renesas Technology Website
http://www.renesas.com/
Inquiries
http://www.renesas.com/inquiry
csc@renesas.com
Revision Record
Rev.
1.00
Date
Jan.18.08
REJ06B0699-0100/Rev.1.00
Description
Page
Summary
—
First edition issued
January 2008
Page 18 of 19
SH7080 Group
A/D Conversion in Single-cycle Scan Mode
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
This document is provided for reference purposes only so that Renesas customers may select the appropriate
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 2008. Renesas Technology Corp., All rights reserved.
REJ06B0699-0100/Rev.1.00
January 2008
Page 19 of 19
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