BBSRM latest
BeagleBoard System
Reference Manual
REF: BB_SRM
Revision C4
C4
BeagleBoard
System Reference Manual
Rev C4
Revision 0.0
December 15, 2009
Page 1 of 180
REF: BB_SRM
BeagleBoard System
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Revision C4
THIS DOCUMENT
This work is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported
License. To view a copy of this license, visit http://creativecommons.org/licenses/bysa/3.0/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San
Francisco, California, 94105, USA.
All derivative works are to be attributed to Gerald Coley of BeagleBoard.org.
For more information, see http://creativecommons.org/license/resultsone?license_code=by-sa
For any questions, concerns, or issues submit them to [email protected]
BEAGLEBOARD DESIGN
These design materials referred to in this document are *NOT SUPPORTED* and DO
NOT constitute a reference design. Only “community” support is allowed via resources
at BeagleBoard.org/discuss.
THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT
PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN
WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE
THE DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND
PERFORMANCE OF THE DESIGN MATERIALS IS WITH YOU. SHOULD THE
DESIGN MATERIALS PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
NECESSARY SERVICING, REPAIR OR CORRECTION.
We mean it; these design materials may be totally unsuitable for any purposes.
Page 2 of 180
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BeagleBoard.org provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR
EVALUATION PURPOSES ONLY and is not considered by BeagleBoard.org to be a finished end-product
fit for general consumer use. Persons handling the product(s) must have electronics training and observe
good engineering practice standards. As such, the goods being provided are not intended to be complete in
terms of required design-, marketing-, and/or manufacturing-related protective considerations, including
product safety and environmental measures typically found in end products that incorporate such
semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the
European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other
related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may
be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS
THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER
WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies BeagleBoard.org from all claims arising from the handling or use of the goods. Due to the open
construction of the product, it is the user’s responsibility to take any and all appropriate precautions with
regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE
LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
BeagleBoard.org currently deals with a variety of customers for products, and therefore our arrangement
with the user is not exclusive. BeagleBoard.org assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or services described
herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide
prior to handling the product. This notice contains important safety information about temperatures and
voltages. For additional information on BeagleBoard.org environmental and/or safety programs, please
contact visit BeagleBoard.org.
No license is granted under any patent right or other intellectual property right of BeagleBoard.org covering
or relating to any machine, process, or combination in which such BeagleBoard.org products or services
might be or are used.
Mailing Address:
BeagleBoard.org
675 North Glenville #195
Richardson, TX 75081
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WARRANTY: The BeagleBoard is warranted against defects in materials and workmanship for a
period of 90 days from purchase. This warranty does not cover any problems occurring as a result
of improper use, modifications, exposure to water, excessive voltages, abuse, or accidents. All
boards will be returned via standard mail if an issue is found. If no issue is found or express return
is needed, the customer will pay all shipping costs.
Before returning the board, please visit BeagleBoard.org/support
Please refer to sections 12 and 13 of this document for the board checkout procedures and
troubleshooting guides.
To return a defective board, please request an RMA at http://beagleboard.org/support/rma .
Page 4 of 180
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Revision C4
Table of Contents
FIGURES .......................................................................................................................................................9
TABLES .......................................................................................................................................................11
1.0
INTRODUCTION.........................................................................................................................13
2.0
CHANGE HISTORY....................................................................................................................14
2.1
2.2
3.0
3.1
4.0
4.1
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
6.0
6.1
6.2
6.3
7.0
7.1
7.2
7.3
7.4
7.5
7.6
7.7
CHANGE HISTORY .......................................................................................................................14
REVISION C3 VS. C4 ...................................................................................................................14
DEFINITIONS AND REFERENCES.........................................................................................15
DEFINITIONS ...............................................................................................................................15
BEAGLEBOARD OVERVIEW ..................................................................................................15
BEAGLEBOARD USAGE SCENARIOS ............................................................................................15
BEAGLEBOARD SPECIFICATION .........................................................................................17
BEAGLEBOARD FEATURES..........................................................................................................17
OMAP PROCESSOR.....................................................................................................................18
MEMORY.....................................................................................................................................18
POWER MANAGEMENT................................................................................................................18
HS USB 2.0 OTG PORT ..............................................................................................................19
HS USB 2.0 HOST PORT .............................................................................................................19
STEREO AUDIO OUTPUT CONNECTOR .........................................................................................20
STEREO AUDIO IN CONNECTOR ..................................................................................................20
S-VIDEO CONNECTOR .................................................................................................................20
DVI-D CONNECTOR....................................................................................................................20
LCD HEADER .............................................................................................................................20
SD/MMC 6 IN 1 CONNECTOR .....................................................................................................21
RESET BUTTON ...........................................................................................................................21
USER/BOOT BUTTON ..................................................................................................................21
INDICATORS ................................................................................................................................22
POWER CONNECTOR ...................................................................................................................22
JTAG CONNECTOR .....................................................................................................................23
RS232 HEADER ..........................................................................................................................23
EXPANSION HEADER ...................................................................................................................23
BEAGLEBOARD MECHANICAL SPECIFICATIONS ..........................................................................23
ELECTRICAL SPECIFICATIONS .....................................................................................................24
PRODUCT CONTENTS..............................................................................................................26
BEAGLEBOARD IN THE BOX REV C4 ..........................................................................................26
SOFTWARE ON THE BEAGLEBOARD ............................................................................................27
REPAIR ........................................................................................................................................27
BEAGLEBOARD HOOKUP.......................................................................................................28
CONNECTING USB OTG.............................................................................................................28
CONNECTING USB HOST ............................................................................................................29
CONNECTING OPTIONAL POWER .................................................................................................30
CONNECTING JTAG....................................................................................................................31
CONNECTING SERIAL CABLE ......................................................................................................32
CONNECTING S-VIDEO................................................................................................................33
CONNECTING DVI-D CABLE.......................................................................................................34
Page 5 of 180
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7.8
7.9
7.10
7.11
7.12
7.13
8.0
BeagleBoard System
Reference Manual
Revision C4
CONNECTING STEREO OUT CABLE..............................................................................................35
CONNECTING STEREO IN CABLE .................................................................................................36
INDICATOR LOCATIONS...............................................................................................................37
BUTTON LOCATIONS ...................................................................................................................38
SD/MMC CONNECTION ..............................................................................................................39
LCD CONNECTION ......................................................................................................................40
BEAGLEBOARD SYSTEM ARCHITECTURE AND DESIGN .............................................41
8.1
SYSTEM BLOCK DIAGRAM ..........................................................................................................41
8.2
INPUT POWER..............................................................................................................................44
8.2.1
USB DC Source .....................................................................................................................45
8.2.2
Wall Supply Source ...............................................................................................................45
8.2.3
DC Source Control................................................................................................................45
8.2.4
3.3V Supply............................................................................................................................46
8.2.5
Meter Current Measurement .................................................................................................46
8.2.6
Processor Current Measurement...........................................................................................46
8.3
POWER CONDITIONING ...............................................................................................................47
8.4
TPS65950 RESET AND POWER MANAGEMENT ...........................................................................48
8.4.1
Main Core Voltages...............................................................................................................49
8.4.2
Main DC Input.......................................................................................................................49
8.4.3
OMAP3530 I2C Control........................................................................................................49
8.4.4
VIO_1V8................................................................................................................................49
8.4.5
Main Core Voltages Smart Reflex .........................................................................................51
8.4.6
VOCORE_1V3.......................................................................................................................51
8.4.7
VDD2.....................................................................................................................................51
8.5
PERIPHERAL VOLTAGES ..............................................................................................................52
8.5.1
VDD_PLL2............................................................................................................................52
8.5.2
VDD_PLL1............................................................................................................................52
8.5.3
VDAC_1V8 ............................................................................................................................54
8.5.4
VDD_SIM ..............................................................................................................................54
8.5.5
VMMC1 .................................................................................................................................54
8.5.6
VAUX2...................................................................................................................................54
8.5.7
Boot Configuration................................................................................................................54
8.5.8
RTC Backup Battery..............................................................................................................55
8.5.9
Power Sequencing .................................................................................................................56
8.5.10
Reset Signals.....................................................................................................................57
8.5.11
mSecure Signal .................................................................................................................58
8.6
OMAP3530 PROCESSOR .............................................................................................................59
8.6.1
Overview................................................................................................................................59
8.6.2
SDRAM Bus...........................................................................................................................60
8.6.3
GPMC Bus.............................................................................................................................60
8.6.4
DSS Bus .................................................................................................................................61
8.6.5
McBSP2.................................................................................................................................61
8.6.6
McBSP1.................................................................................................................................61
8.6.7
McBSP3.................................................................................................................................62
8.6.8
Pin Muxing ............................................................................................................................62
8.6.9
GPIO Mapping ......................................................................................................................64
8.6.10
Interrupt Mapping ............................................................................................................64
8.7
POP MEMORY DEVICE ...............................................................................................................65
8.8
SYSTEM CLOCKS .........................................................................................................................65
8.8.1
32KHz Clock .........................................................................................................................65
8.8.2
26MHz Clock.........................................................................................................................66
8.8.3
McBSP_CLKS .......................................................................................................................66
8.9
USB OTG PORT..........................................................................................................................67
8.9.1
USB OTG Overview ..............................................................................................................67
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8.9.2
USB OTG Design ..................................................................................................................68
8.9.3
OTG ULPI Interface..............................................................................................................68
8.9.4
OTG Charge Pump................................................................................................................69
8.9.5
OTG USB Connector.............................................................................................................70
8.9.6
OTG USB Protection.............................................................................................................70
8.10
USB HOST PORT .........................................................................................................................70
8.10.1
Host USB OMAP3 Interface.............................................................................................71
8.10.2
Host USB PHY..................................................................................................................71
8.10.3
Host USB Connector ........................................................................................................72
8.10.4
Host USB Power Control..................................................................................................73
8.11
SD/MMC....................................................................................................................................73
8.11.1
MMC Power .....................................................................................................................75
8.11.2
OMAP3530 Interface........................................................................................................76
8.11.3
Card Detect ......................................................................................................................78
8.11.4
Write Protect.....................................................................................................................78
8.11.5
8 Bit Mode ........................................................................................................................78
8.11.6
Booting From SD/MMC Cards.........................................................................................78
8.12
AUDIO INTERFACE ......................................................................................................................79
8.12.1
OMAP3530 Audio Interface .............................................................................................79
8.12.2
TPS65950 Audio Interface................................................................................................80
8.12.3
Audio Output Jack ............................................................................................................80
8.12.4
Audio Input Jack...............................................................................................................80
8.13
DVI-D INTERFACE ......................................................................................................................80
8.13.1
OMAP3530 LCD Interface ...............................................................................................81
8.13.2
OMAP3530 LCD Power ...................................................................................................82
8.13.3
TFP410 Framer................................................................................................................83
8.13.4
TFP410 Power..................................................................................................................84
8.13.5
TFP410 Control Pins........................................................................................................84
8.13.6
DVI-D Connector .............................................................................................................85
8.14
LCD EXPANSION HEADERS ........................................................................................................87
8.15
S-VIDEO......................................................................................................................................89
8.16
RS232 PORT ...............................................................................................................................90
8.16.1
OMAP3530 Interface........................................................................................................90
8.16.2
OMAP3530 Level Translator ...........................................................................................90
8.16.3
RS232 Transceiver............................................................................................................90
8.16.4
Connector .........................................................................................................................91
8.17
INDICATORS ................................................................................................................................91
8.17.1
Power Indicator................................................................................................................92
8.17.2
PMU Status Indicator.......................................................................................................92
8.17.3
User Indicators .................................................................................................................93
8.18
JTAG..........................................................................................................................................93
8.18.1
OMAP3530 Interface........................................................................................................93
8.18.2
Connector .........................................................................................................................94
8.19
EXPANSION HEADER ...................................................................................................................94
8.19.1
OMAP3530 Interface........................................................................................................95
8.19.2
Expansion Signals.............................................................................................................96
8.19.3
Power................................................................................................................................98
8.19.4
Reset .................................................................................................................................98
8.19.5
Power Control ..................................................................................................................98
8.20
ADDITIONAL EXPANSION HEADER ..............................................................................................98
9.0
9.1
9.2
9.3
CONNECTOR PINOUTS AND CABLES ...............................................................................100
POWER CONNECTOR .................................................................................................................100
USB OTG.................................................................................................................................101
S-VIDEO....................................................................................................................................102
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Reference Manual
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9.4
DVI-D ......................................................................................................................................103
9.5
LCD..........................................................................................................................................105
9.5.1
Connector Pinout ................................................................................................................105
9.5.2
Connector Suppliers ............................................................................................................106
9.5.3
Dimensions ..........................................................................................................................107
9.5.4
Mounting Scenarios.............................................................................................................108
9.6
AUDIO CONNECTIONS ...............................................................................................................110
9.7
AUDIO OUT ...............................................................................................................................111
9.8
JTAG........................................................................................................................................112
9.9
RS232.......................................................................................................................................114
9.10
EXPANSION ...............................................................................................................................115
9.11
BATTERY INSTALLATION ..........................................................................................................116
9.11.1
Battery ............................................................................................................................116
9.11.2
Battery Installation .........................................................................................................116
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
11.0
BEAGLEBOARD ACCESSORIES ..........................................................................................118
DC POWER SUPPLY ...................................................................................................................119
SERIAL RIBBON CABLE .............................................................................................................120
USB HUBS ................................................................................................................................121
DVI CABLES .............................................................................................................................121
DVI-D MONITORS ....................................................................................................................122
SD/MMC CARDS ......................................................................................................................122
USB TO ETHERNET ...................................................................................................................123
USB TO WIFI ............................................................................................................................123
USB TO BLUETOOTH ................................................................................................................124
EXPANSION CARD DESIGN ........................................................................................................125
MECHANICAL INFORMATION............................................................................................126
11.1
BEAGLEBOARD DIMENSIONS ....................................................................................................126
11.2
BEAGLEBOARD EXPANSION CARD DESIGN INFORMATION .......................................................127
11.2.1
Mounting Method ...........................................................................................................127
11.2.2
Expansion EEPROM ......................................................................................................127
12.0
BOARD VERIFICATION .........................................................................................................129
12.1
EQUIPMENT ...............................................................................................................................129
12.2
OUT OF THE BOX.......................................................................................................................130
12.3
SD CARD CONFIGURATION .......................................................................................................131
12.4
SETUP .......................................................................................................................................132
12.5
FACTORY BOOT VERIFICATION .................................................................................................132
12.6
BOARD SD BOOT ......................................................................................................................133
12.7
FACTORY BOOT REINSTALL ......................................................................................................134
12.8
BOOTING THE KERNEL ..............................................................................................................136
12.9
UBOOT TESTS ...........................................................................................................................142
12.9.1
EDID Test .......................................................................................................................142
12.9.2
LED Test .........................................................................................................................142
12.9.3
DVI-D Test......................................................................................................................143
12.10 KERNEL BASED TESTS ..............................................................................................................143
12.10.1
DVI-D Test......................................................................................................................143
12.10.2
S-Video Test....................................................................................................................143
12.10.3
Audio Test.......................................................................................................................144
13.0
TROUBLESHOOTING .............................................................................................................148
13.1
ACCESS POINTS .........................................................................................................................148
13.1.1
Voltage Points.................................................................................................................148
13.1.2
Signal Access Points.......................................................................................................150
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13.2
TROUBLESHOOTING GUIDE .......................................................................................................151
13.3
SERIAL PORT ISSUES .................................................................................................................152
13.3.1
First Step ........................................................................................................................153
13.3.2
Second Step.....................................................................................................................154
13.3.3
Third Step .......................................................................................................................155
13.3.4
Fourth Step .....................................................................................................................155
14.0
KNOWN ISSUES........................................................................................................................157
15.0
PCB COMPONENT LOCATIONS ..........................................................................................158
16.0
SCHEMATICS............................................................................................................................160
17.0
BILLS OF MATERIAL .............................................................................................................171
18.0
PCB INFORMATION................................................................................................................172
Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
BeagleBoard Usage Scenarios ...................................................................... 16
USB Y-Cable ................................................................................................ 19
The Rev C4 Box............................................................................................ 26
Rev C4 Box Contents.................................................................................... 27
USB OTG Connection .................................................................................. 28
USB Host Connection................................................................................... 29
DC Power Connection .................................................................................. 30
BeagleBoard JTAG Connection ................................................................... 31
BeagleBoard Serial Cable Connection.......................................................... 32
BeagleBoard S-Video Connection............................................................ 33
BeagleBoard DVI-D Connection.............................................................. 34
BeagleBoard Audio Out Cable Connection.............................................. 35
BeagleBoard Audio In Cable Connection................................................. 36
BeagleBoard Indicator Locations ............................................................. 37
BeagleBoard Button Location................................................................... 38
BeagleBoard SD/MMC Location ............................................................. 39
BeagleBoard LCD Header Location......................................................... 40
BeagleBoard High Level Block Diagram ................................................. 41
BeagleBoard Top Side Components......................................................... 42
BeagleBoard Backside Components......................................................... 43
Input Power Section.................................................................................. 44
Processor Current Measurement ............................................................... 47
Power Conditioning .................................................................................. 48
Main Power Rails...................................................................................... 50
Peripheral Voltages................................................................................... 53
Power Sequencing..................................................................................... 56
Reset Circuitry .......................................................................................... 57
OMAP3530 Block Diagram ..................................................................... 59
McBSP2 Interface..................................................................................... 61
McBSP1 Interface..................................................................................... 62
Page 9 of 180
REF: BB_SRM
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
BeagleBoard System
Reference Manual
Revision C4
McBSP3 Interface..................................................................................... 62
POP Memory ............................................................................................ 65
System Clocks........................................................................................... 65
USB OTG Design ..................................................................................... 68
USB Host Design...................................................................................... 71
Example of an SDIO Card ....................................................................... 74
RS-MMC and Card ................................................................................... 75
SD/MMC Interface ................................................................................... 77
Audio Circuitry ......................................................................................... 79
DVI-D Interface ........................................................................................ 81
S-Video Interface ...................................................................................... 89
RS232 Interface Design ............................................................................ 90
RS232 Cable ............................................................................................. 91
Indicator Design........................................................................................ 92
JTAG Interface.......................................................................................... 93
Expansion Header ..................................................................................... 94
Power Connector..................................................................................... 100
USB OTG Connector.............................................................................. 101
OTG Host Shorting Pads ........................................................................ 101
S-Video Connector.................................................................................. 102
DVI-D Connector.................................................................................... 103
DVI-D Cable........................................................................................... 104
Top Mount LCD Adapter........................................................................ 107
Top Mount LCD Adapter........................................................................ 108
Bottom Mount LCD Adapter .................................................................. 109
Audio In Plug.......................................................................................... 110
Audio In Plug.......................................................................................... 110
Audio Out Plug ....................................................................................... 111
Audio In Plug.......................................................................................... 111
JTAG Connector Pinout.......................................................................... 112
JTAG 14 to 20 Pin Adapter .................................................................... 113
JTAG Connector Pinout.......................................................................... 113
RS232 Header ......................................................................................... 114
RS232 Flat Cable .................................................................................... 114
Expansion Sockets .................................................................................. 115
Optional Battery...................................................................................... 116
Optional Battery Location....................................................................... 117
DC Power Supply ................................................................................... 119
RS232 Cable ........................................................................................... 120
RS232 Cable Wiring ............................................................................... 120
HDMI to DVI-D Cable .......................................................................... 122
USB to Ethernet Adapters....................................................................... 123
USB to WiFi ........................................................................................... 124
USB to Bluetooth.................................................................................... 125
BeagleBoard Dimension Drawing .......................................................... 126
BeagleBoard Bottom Stacked Daughter Card ....................................... 127
Page 10 of 180
REF: BB_SRM
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
BeagleBoard System
Reference Manual
Revision C4
BeagleBoard Expansion Board EEPROM Schematic ............................ 128
BeagleBoard Voltage Access Points....................................................... 149
BeagleBoard Signal Access Points ......................................................... 151
BeagleBoard Serial Cable Orientation.................................................... 153
DB9 Male Connector .............................................................................. 154
DB9 Null Modem Cable ......................................................................... 154
Serial Cable Loopback............................................................................ 155
BeagleBoard Top Side Components....................................................... 158
BeagleBoard Bottom Side Components ................................................. 159
Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Change History ............................................................................................. 14
BeagleBoard Features ................................................................................... 17
BeagleBoard Electrical Specification Rev C4 .............................................. 24
OMAP3530 Pin Muxing Settings ................................................................. 63
OMAP3530 GPIO Pins................................................................................. 64
OMAP3530 Interrupt Pins ............................................................................ 64
OMAP3530 ULPI Interface.......................................................................... 68
OMAP3530 ULPI Interface.......................................................................... 69
USB OTG Charge Pump Pins....................................................................... 70
USB Host Port OMAP Signals ..................................................................... 71
SD/MMC OMAP Signals ............................................................................. 78
OMAP3530 Audio Signals ........................................................................... 79
OMAP3530 Audio Signals ........................................................................... 80
OMAP3530 LCD Signals ............................................................................. 82
TFP410 Interface Signals.............................................................................. 83
J4 LCD Signals ............................................................................................. 87
J5 LCD Signals ............................................................................................. 88
S-Video Interface Signals ............................................................................. 89
JTAG Signals ................................................................................................ 94
Expansion Connector Signals ....................................................................... 96
Expansion Connector Signal Groups ............................................................ 97
J4 GPIO Signals............................................................................................ 99
J5 GPIO Signals............................................................................................ 99
DVI-D to HDMI Cable ............................................................................... 103
J4 LCD Signals ........................................................................................... 105
J5 LCD Signals ........................................................................................... 106
J4 and J5 Connector Sources ...................................................................... 106
Connector Dimensions................................................................................ 107
JTAG Signals .............................................................................................. 112
DC Power Supply Specifications................................................................ 119
DC Power Supplies ..................................................................................... 119
Cable Pinout................................................................................................ 121
USB Hubs Tested........................................................................................ 121
DVI-D Monitors Tested.............................................................................. 122
Page 11 of 180
REF: BB_SRM
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
BeagleBoard System
Reference Manual
Revision C4
SD/MMC Cards Tested............................................................................... 122
USB to Ethernet Adapters........................................................................... 123
USB to WiFi Adapters ................................................................................ 124
USB to Bluetooth Adapters ........................................................................ 125
Voltages ...................................................................................................... 150
Troubleshooting .......................................................................................... 152
Known Issues .............................................................................................. 157
Page 12 of 180
REF: BB_SRM
1.0
BeagleBoard System
Reference Manual
Revision C4
Introduction
This document is the System Reference Manual for the BeagleBoard, a low cost
OMAP3530 based board supported through BeagleBoard.org. This document provides
detailed information on the overall design and usage of the BeagleBoard from the system
level perspective. It is not intended to provide detailed documentation of the OMAP3530
processor or any other component used on the board. It is expected that the user will refer
to the appropriate documents for these devices to access detailed information.
The key sections in this document are:
Section 2.0– Change History
Provides tracking for the changes made to the System Reference Manual.
Section 3.0– Definitions and References
This section provides definitions for commonly used terms and acronyms.
Section 4.0– Overview
This is a high level overview of the BeagleBoard.
Section 5.0– Specification
Provided here are the features and electrical specifications of the BeagleBoard.
Section 6.0-Product Contents
Describes what the BeagleBoard package looks like and what is included in the
box.
Section 7.0– Hookup
Covered here is how to connect the various cables to the BeagleBoard.
Section 8.0– System Architecture and Design
This section provides information on the overall architecture and design of the
BeagleBoard. This is a very detailed section that goes into the design of each
circuit on the board.
Section 9.0– Connector Pinouts and Cables
The section describes each connector and cable used in the system. This will
allow the user to create cables, purchase cables, or to perform debugging as
needed.
Section 10.0– BeagleBoard Accessories
Covered in this section are a few of the accessories that may be used with
BeagleBoard. This is not an exhaustive list, but does provide an idea of the types
of cables and accessories that can be supported and how to find them. It also
provides a definition of what they need to be. It does not guarantee that these
devices will work on all OS implementations.
Section 11.0 – Mechanical
Information is provided here on the dimensions of the BeagleBoard.
Section 12.0 – Board Verification
A description is provided on how to setup the board and using the verification
process and SW to verify that the board is functional.
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Section 13.0 – Troubleshooting
Here is where you can find tips on troubleshooting the setup of the BeagleBoard.
Section 14.0- Known Issues
This section describes the known issues with the current revision of the
BeagleBoard and any workarounds that may be possible.
Section 15.0- BeagleBoard Components
This section provides information on the top and bottom side silkscreen of the
BeagleBoard showing the location of the components.
Section 16.0- BeagleBoard Schematics
These are the schematics for the BeagleBoard and information on where to get the
PDF and OrCAD files..
Section 17.0- Bill Of Material
This section describes where to get the latest Bill of Material for the BeagleBoard.
Section 18.0- BeagleBoard PCB Information
This section describes where to get the PCB file information for the BeagleBoard.
2.0
Change History
2.1
Change History
Table 1 tracks the changes made for each revision of this document.
Table 1.
Rev
C4
2.2
Change History
Changes
Initial release.
Date
By
12/15/2009
GC
Revision C3 vs. C4
There are three key changes on the Rev C4 board versus the Rev C3 version.
o Use of the OMAP3530DCBB72 device which is the 720MHZ version of the
OMAP3530.
o An updated version of the UBoot software. The following changes will affect the
user experience:
o The Beagle splash screen has been replaced with an orange only screen at
boot up.
o Turning on VAUX2 for the EHCI fix
o A more advanced fix for the EHCI noise issue on Rev C3 board. This involves a
change in the power circuitry for the 1.8V rail supplied to the EHCI PHY
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interface. The power is now derived from the VAUX2 on the TPS65950 through a
filter circuit.
3.0
Definitions and References
3.1
Definitions
SD- Secure Digital
SDIO- Secure Digital Input Output
MMC- Multimedia Card
MDDR- Mobile Dual Data Rate
SDRAM- Synchronous Dual Access Memory
OMAP3530- The CortexA8 based System on a Chip from Texas Instruments.
4.0
BeagleBoard Overview
The BeagleBoard is an OMAP3530 platform designed specifically to address the Open
Source Community. It has been equipped with a minimum set of features to allow the
user to experience the power of the OMAP3530 and is not intended as a full development
platform as many of the features and interfaces supplied by the OMAP3530 are not
accessible from the BeagleBoard. By utilizing standard interfaces, the BeagleBoard is
highly extensible to add many features and interfaces. It is not intended for use in end
products. All of the design information is freely available and can be used as the basis for
a product. BeagleBoards will not be sold for use in any product as this hampers the
ability to get the boards to as many community members as possible and to grow the
community.
4.1
BeagleBoard Usage Scenarios
The Figure 1 provides an example of a few of the various usage scenarios for the
BeagleBoard.
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USB
WiFi
GP
BT
Revision C4
beagle>
Batter
SD
4GB
Figure 1.
BeagleBoard Usage Scenarios
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5.0
Revision C4
BeagleBoard Specification
This section covers the specifications of the BeagleBoard and provides a high level
description of the major components and interfaces that make up the BeagleBoard.
5.1
BeagleBoard Features
Table 2 provides a list of the BeagleBoard’s features.
Table 2.
Processor
POP Memory
PMIC TPS65950
Debug Support
PCB
Indicators
HS USB 2.0 OTG
Port
HS USB Host Port
Audio Connectors
SD/MMC Connector
User Interface
Video
Power Connector
Expansion
Connector
(Not Populated)
2 LCD Connectors
BeagleBoard Features
Feature
OMAP3530DCBB72 720MHz
Micron
2Gb NAND (256MB)
2Gb MDDR SDRAM (256MB)
Power Regulators
Audio CODEC
Reset
USB OTG PHY
14-pin JTAG
GPIO Pins
UART
LEDs
6
layers
3.1” x 3.0” (78.74 x 76.2mm)
Power
2-User Controllable
PMU
Mini AB USB connector
TPS65950 I/F
MiniAB
Single USB HS Port
Up to 500ma Power
3.5mm
3.5mm
L+R out
L+R Stereo In
6 in 1 SD/MMC/SDIO
4/8 bit support, Dual voltage
1-User defined button
Reset Button
DVI-D
S-Video
USB Power
DC Power
Power (5V & 1.8V)
UART
McBSP
McSPI
I2C
GPIO
MMC
PWM
Access to all of the LCD
3.3V, 5V, 1.8V
control signals plus I2C
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The following sections provide more detail on each feature and sections of the
BeagleBoard.
5.2
OMAP Processor
The BeagleBoard uses the OMAP3530DCBB72 720MHZ version and comes in a .4mm
pitch POP package. POP (Package on Package) is a technique where the memory, NAND
and SDRAM, are mounted on top of the OMAP3530. For this reason, when looking at
the BeagleBoard, you will not find an actual part labeled OMAP3530.
5.3
Memory
The Micron POP memory is used on the Rev C4 BeagleBoard and is mounted on top of
the processor as mentioned. The key function of the POP memory is to provide:
o 2Gb NAND x 16 (256MB)
o 2Gb MDDR SDRAM x32 (256MB @ 166MHz)
No other memory devices are on the BeagleBoard. It is possible however, that additional
memory can be added to BeagleBoard by:
o Installing a SD or MMC in the SD/MMC slot
o Use the USB OTG port and a powered USB hub to drive a USB Thumb drive or
hard drive.
o Install a thumbdrive into the EHCI USB port
Support for this is dependent upon driver support in the OS.
5.4
Power Management
The TPS65950 is used on the Rev C4 to provide power to the BeagleBoard with the
exception of the 3.3V regulator which is used to provide power to the DVI-D encoder and
RS232 driver. In addition to the power the TPS65950 also provides:
o
o
o
o
o
Stereo Audio Out
Stereo Audio in
Power on reset
USB OTG PHY
Status LED
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5.5
Revision C4
HS USB 2.0 OTG Port
The USB OTG port can be used as the primary power source and communication link for
the BeagleBoard and derives power from the PC over the USB cable. The client port is
limited in most cases to 500mA by the PC. A single PC USB port is sufficient to power
the BeagleBoard. If additional devices are connected to the expansion bus and the 5V rail
is used to power them or if a high powered USB device is connected to the EHCI port,
then the power required could exceed that supplied by a USB port or Hub.
It is possible to take this to 1A by using a Y cable if additional power is needed for either
the USB host port or an expansion card. Figure 2 shows and example of the Y-Cable for
the USB.
Figure 2.
USB Y-Cable
The BeagleBoard requires a single minAB to USB A cable or as mentioned a Y-Cable
can be used if needed.
There is an option to provide external power to the BeagleBoard using a 5V DC supply
and is discussed later in this section.
5.6
HS USB 2.0 Host Port
On the Rev C4 board a single USB HS only Host port is provided via a USB Type A
connector. It provides power on/off control and up to 500mA of current at 5V.
The HS USB Port is HS only. In order to support a FS/LS device, a HUB must be used.
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5.7
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Stereo Audio Output Connector
A 3.5mm standard stereo output audio jack is provided to access the stereo output of the
onboard audio CODEC. The Audio CODEC is provided by the TPS65950.
5.8
Stereo Audio In Connector
A 3.5mm standard stereo audio input jack is provided to access the stereo output of the
onboard audio CODEC.
5.9
S-Video Connector
A 4 pin DIN connector is provided to access the S-Video output of the BeagleBoard. This
is a separate output from the OMAP processor and can contain different video output data
from what is found on the DVI-D output if the software is configured to do it.
It will support NTSC or PAL format output to a standard TV. The default is NTSC, but
can be changed via the Software.
5.10
DVI-D Connector
The BeagleBoard can drive a LCD panel equipped with a DVI-D digital input. This is
the standard LCD panel interface of the OMAP3530 and will support 24b color output.
DDC2B (Display Data Channel) or EDID (Enhanced Display ID) support over I2C is
provided in order to allow for the identification of the LCD monitor type and the required
settings.
The BeagleBoard is equipped with a DVI-D interface that uses an HDMI connector that
was selected for its small size. It does not support the full HDMI interface and is used to
provide the DVI-D interface portion only. The user must use a HDMI to DVI-D cable or
adapter to connect to a LCD monitor. This cable or adapter is not provided with the
BeagleBoard. A standard HDMI cable can be used when connecting to a monitor with an
HDMI connector.
DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE
BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY
AND THEN POWER ON THE BEAGLEBOARD.
5.11
LCD Header
A pair of 1.27mm pitch 2x10 headers are provided to gain access to the LCD signals.
This allows for the creation of LCD boards that will allow adapters to be made to provide
the level translation to support different LCD panels.
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Revision C4
SD/MMC 6 in 1 Connector
A 6 in 1 SD/MMC connector is provided as a means for expansion and can support such
devices as:
o
o
o
o
o
o
o
o
o
o
WiFi Cards
Camera
Bluetooth Cards
GPS Modules
SD Memory Cards
MMC Memory Cards
SDIO Cards
MMCMobile cards
RS-MMC Cards
miniSD Cards
It supports the MMC4.0 (MMC+) standard and can boot from MMC or SD cards. It will
support both 4 and 8 bit cards. It will also support most SDHC cards as well.
5.13
Reset Button
When pressed and released, causes a power on reset of the BeagleBoard.
5.14
User/Boot Button
A button is provided on the BeagleBoard to provide two functions:
•
•
Force a change in the boot sequence of the OMAP3530.
Used as an application button that can be used by SW as needed.
When used in conjunction with the RESET button, it will force a change to the order in
which boot sources are checked as viable boot sources.
If the button is pressed while the RESET button is released, the sequence becomes:
o
o
o
o
USB
UART
MMC1
NAND
Even though the NAND may have a program in it, if a card is placed in the MMC slot, it
will try to boot from it first. If it is not there, it will boot from NAND.
There is also the option to have a serial download application that will program the
NAND if connected to the serial or USB ports. In this scenario the internal ROM will
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stop on either the serial or USB port and start the download process from there. It does
require an application to be run on the host PC in order to perform this function.
If the user button is not pressed at reset, the sequence in which the internal ROM looks
for viable boot sources is as follows:
o
o
o
o
NAND
USB
UART3
MMC1
In this case, NAND overrides every option and will always boot from NAND if there is
data in the NAND. If the NAND is empty, then the other sources are available to be used
based on the boot order.
To force a boot from the SD/MMC card, the reset button must be pushed and the reset
button pushed and reelased.
5.15
Indicators
There are three green LEDs on the BeagleBoard that can be controlled by the user.
o One on the TPS65950 that is programmed via the I2C interface
o Two on the OMAP3530 Processor controlled via GPIO pins
There is a fourth LED on the BeagleBoard that provides an indication that power is
supplied to the board and is not controlled via software.
5.16
Power Connector
Power will be supplied via the USB OTG connector and if a need arises for additional
power, such as when a board is added to the expansion connectors, a larger wall supply
5V can be plugged into the optional power jack. When the wall supply is plugged in, it
will remove the power path from the USB connector and will be the power source for the
whole board. The power supply is not provided with the BeagleBoard.
When using the USB OTG port in the host mode, the DC supply must be connected as
the USB port will be used to provide limited power to the hub at a maximum of 100mA,
so a hub must be powered. The 100mA is not impacted by having a higher amperage
supply plugged into the DC power jack. The 100mA is a function of the OTG port itself.
WARNING:
DO NOT PLUG IN ANYTHING BUT
CONNECTOR OR THE BOARD WILL BE DAMAGED!
5V
TO THE DC
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Make sure the DC supply is regulated and a clean supply.
5.17
JTAG Connector
A 14 pin JTAG header is provided on the BeagleBoard to facilitate the SW development
and debugging of the board by using various JTAG emulators. The interface is at 1.8V on
all signals. Only 1.8V Levels are supported. DO NOT expose the JTAG header to
3.3V.
5.18
RS232 Header
Support for RS232 via UART3 is provided by a 10 pin header on the BeagleBoard for
access to an onboard RS232 transceiver. It does require an IDC to DB9 flat cable, which
is not provided, to access the serial port.
5.19
Expansion Header
An option for a single 28 pin header is provided on the board to allow for the connection
of various expansion cards that could be developed by the users or other sources. Due to
multiplexing, different signals can be provided on each pin. This header is not populated
on the BeagleBoard so that based on the usage scenario it can be populated as needed.
5.20
BeagleBoard Mechanical Specifications
Size:
3.0” x 3.1”
Max height:
TBM
Layers:
6
PCB thickness:
.062”
RoHS Compliant: Yes
Weight:
TBW
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5.21
Revision C4
Electrical Specifications
Table 3 is the electrical specification of the external interfaces to the Rev C4
BeagleBoard.
Table 3.
BeagleBoard Electrical Specification Rev C4
Specification
Min
Typ
Max
Unit
5
350
5
350
5
1
1.8
5.2
1.85
30
5.2
V
mA
V
mA
V
A
V
mA
V
480
12.5
1.5
Mb/S
Mb/S
Mb/S
480
Mb/S
5.4
-5.5
+/-60
V
V
mA
Kbit/S
Power
Input Voltage USB
Current USB
Input Voltage DC
Current DC
Expansion Voltage (5V)
Current (Depends on source current available)
Expansion Voltage (1.8V)
Current
USB Host (Same as the DC supplied by the power plug or USB 5V)
Current (Depends on what the DC source can supply over
what the board requires)
USB OTG
High Speed Mode
Full Speed Mode
Low Speed Mode
USB Host
High Speed Mode
RS232
Transmit
High Level Output Voltage
Low Level output voltage
Output impedance
Maximum data rate
Receive
High level Input Voltage
Lo Level Input Voltage
Input resistance
JTAG
Realview ICE Tool
XDS560
XDS510
Lauterbach(tm)
SD/MMC
Voltage Mode 1.8V
Voltage Mode 3.0V
Current
Clock
DVI-D
Pixel Clock Frequency
High level output voltage
Swing output voltage
Maximum resolution
4.8
4.8
1.75
4.8
5
Varies
5
-5
+/-35
5.2
5.2
250
-2.7
3
1.71
2.7
-3.2
5
1.8
3.0
V
.4
7
Kohms
30
30
30
30
MHz
MHz
MHz
MHz
1.89
V
V
mA
MHz
220
48
25
65
3.3
400
600
1024
x 768
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MHz
V
mVp-p
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S-Video
Full scale output voltage (75ohm load)
Offset voltage
Output Impedance
Audio In
Peak-to-peak single-ended input voltage (0 dBFs)
Total harmonic distortion (sine wave @ 1.02 kHz @ -1 dBFs)
Total harmonic distortion (sine wave @ 1.02 kHz) 2
0 Hz to 20 kHz, A-weighted audio, Gain = 0 dB
Audio Out
Load Impedance @100 pF
Maximum Output Power (At 0.53 Vrms differential output voltage
and load impedance = 16 Ohms)
Peak-to-Peak output voltage
Total Harmonic Distortion @ 0 dBFs
Idle channel noise (20Hz to 20KHz)
.7
67.5
14
.88
50
75
1
82.5
V
mV
Ohms
-80
-85
1.5
-75
-78
Vpp
dB
dB
16
17.56
-80
-90
ohms
mW
1.5
-75
-85
Page 25 of 180
Vpp
dB
dB
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6.0
Revision C4
Product Contents
Under this section is a description of what comes in the box when the BeagleBoard is
purchased.
6.1
BeagleBoard In the Box Rev C4
The final packaged Rev C4 product will contain the following:
o 1 Box
o 1 BeagleBoard in an ESD Bag
NO CABLES ARE PROVIDED WITH THE BEAGLEBOARD.
Figure 3.
The Rev C4 Box
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Figure 4.
6.2
Revision C4
Rev C4 Box Contents
Software on the BeagleBoard
The board ships with U-Boot and X-Loader flashed onto the BeagleBoard.
6.3
Repair
If you feel the board is in need of repair, follow the RMA Request process found at
http://beagleboard.org/support/rma
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7.0
Revision C4
BeagleBoard Hookup
This section provides an overview of all of the connectors on the BeagleBoard and how
they should be used.
7.1
Connecting USB OTG
The USB OTG port connects to the PC host and uses a miniAB cable through which
power is provided to the BeagleBoard. If desired, the BeagleBoard may also be
connected to a self powered USB hub. Figure 5 shows where the cable is connected to
the BeagleBoard.
If the OTG Port is to be used as a Host, the ID pin must be grounded. This means that
you must have a 5 pin cable connected to the OTG port on the BeagleBoard and you must
use a USB powered HUB. There is also an option to ground the ID on the board and is
discussed later.
C4
Figure 5.
USB OTG Connection
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7.2
Revision C4
Connecting USB Host
The Rev C4 Beagle is equipped with a USB Host only connector and can be used to
support USB based devices. In order to connect multiple devices a Hub is required. The
hub can be powered or un-powered if the total current on the devices connected to the
hub do not exceed the available power from the DC power supply that is used. If the
board is powered from the OTG connector, then the power available from this port is
extremely limited and will not be able to provide sufficient power to run most USB
devices. It may be possible to run a USB keyboard or mouse, but that is about all it will
have the power to supply. The USB Host port is HS only and does not support LS or FS
devices without a hub.
Figure 6 below shows the location of the USB Host connector.
C4
Figure 6.
USB Host Connection
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7.3
Revision C4
Connecting Optional Power
An optional DC supply can be used to power the BeagleBoard by plugging it into the
power jack of the BeagleBoard. The power supply is not provided with the BeagleBoard,
but can be obtained from various sources. You need to make sure the supply is a
regulated 5V supply. Figure 7 shows where to insert the power supply into the power
jack.
C4
Figure 7.
DC Power Connection
The power supply must have a 2.1mm I.D x 5.5mm O.D. x 9.5mm and can be either
straight or right angle. Connecting anything other than 5V will result in damage to the
board. If you are using the USB OTG port in the OTG or host mode, you must have an
external DC supply powering the BeagleBoard.
It is highly recommended that on the Rev C4 version of the board that an external power
supply or double USB cable be used if the USB Host is to be used. Most USB supplies
will not be able to supply the required current over a single USB port.
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7.4
Revision C4
Connecting JTAG
A JTAG emulator can be used for advanced debugging by connecting it to the JTAG
header on the BeagleBoard. Only the 14pin version of the JTAG is supported and if a
20pin version is needed, you will to contact your emulator supplier for the appropriate
adapter. Figure 8 shows the connection of the JTAG cable to the BeagleBoard.
C4
Figure 8.
BeagleBoard JTAG Connection
DO NOT expose the JTAG header to 3.3V. It supports 1.8V only.
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7.5
Revision C4
Connecting Serial Cable
In order to access the serial port of the BeagleBoard a flat cable is required to connect to
a PC. The adapter will not plug directly into the PC and will require an external Female
to Female twisted cable (Null Modem) in order to connect it to the PC. The ribbon cable
is not supplied with the BeagleBoard but can be obtained from numerous sources. Figure
9 shows where the ribbon cable is to be installed.
C4
Figure 9.
BeagleBoard Serial Cable Connection
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7.6
Revision C4
Connecting S-Video
An S-Video cable can be connected to the BeagleBoard and from there is can be
connected to a TV or monitor that supports an S-Video input. This cable is not supplied
with the BeagleBoard. Figure 10 shows the connector for the S-Video cable.
C4
Figure 10. BeagleBoard S-Video Connection
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7.7
Revision C4
Connecting DVI-D Cable
In order to connect the DVI-D output to a monitor, a HDMI to DVI-D cable is required.
This cable is not supplied with BeagleBoard but can be obtained through numerous
sources. Figure 11 shows the proper connection point for the cable.
C4
Figure 11. BeagleBoard DVI-D Connection
DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE
BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY
AND THEN POWER ON THE BEAGLEBOARD.
Only the digital portion of HDMI is supported on the
BeagleBoard.
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7.8
Revision C4
Connecting Stereo Out Cable
An external Audio output device, such as external stereo powered speakers, can be
connected to the BeagleBoard via a 3.5mm jack. The audio cables are not provided with
BeagleBoard, but can be obtained from just about anywhere. Figure 12 shows how the
cable connected to the stereo out jack.
C4
Figure 12. BeagleBoard Audio Out Cable Connection
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7.9
Revision C4
Connecting Stereo In Cable
External Audio input devices, such as a powered microphone or the audio output of a PC
or MP3 player, can be connected to the via a 3.5mm jack. The audio cables are not
provided with BeagleBoard, but can be obtained from just about any source. Figure 13
shows how the cable is connected to the stereo input jack.
C4
Figure 13. BeagleBoard Audio In Cable Connection
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7.10
Revision C4
Indicator Locations
There are four green indicators on the BeagleBoard. One of them, POWER, indicates
that the main supply is active. The other three can be controlled by the software. Figure
14 shows the location of each indicator.
C4
Figure 14. BeagleBoard Indicator Locations
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7.11
Revision C4
Button Locations
There are two buttons on the BeagleBoard; the RESET button when pressed will force a
board reset and the USER button which can be used by the SW for user interaction. If the
user holds the USER button down while pressing and releasing the RESET button, the
BeagleBoard will enter the ROM boot loader mode allowing it to boot from other sources
than the onboard NAND. Figure 15 shows the location of the buttons.
C4
Figure 15. BeagleBoard Button Location
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7.12
Revision C4
SD/MMC Connection
The SD/MMC connector can be used for Memory or SDIO type cards. This is a full size
connector and will support various cards. Whether a particular card is supported or not, is
dependent on the available software drivers. Figure 16 shows the location of the
SD/MMC connector.
C4
Figure 16. BeagleBoard SD/MMC Location
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7.13
Revision C4
LCD Connection
There are two headers provided to allow access to the LCD signals on the BeagleBoard.
These headers are 2x10 headers with a spacing of .05 (1.27mm) pitch. How these
connectors are used is determined by the design of the adapter board. Figure 17 shows
the location of the LCD headers on the Beagle.
C4
Figure 17. BeagleBoard LCD Header Location
Page 40 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
8.0
Revision C4
BeagleBoard System Architecture and Design
This section provides a high level description of the design of the BeagleBoard and its
overall architecture.
8.1
System Block Diagram
Figure 18 is the high level block diagram of the BeagleBoard. If you will notice, the
block diagram is configured to match the component placement of the BeagleBoard.
DVI-D
SVideo
Stereo
Out
Stereo
In
REG
LCD
TFP410
SW
OTG
EXPANSION
TPS65950
OMAP
3530
w/POP
mSecure
DC
LVL
USER
USB HOST
RS232
JTAG
RESET
SD/MMC
Figure 18. BeagleBoard High Level Block Diagram
Figure 19 shows the location of the components as shown in the block diagram.
Page 41 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Revision C4
C4
Figure 19. BeagleBoard Top Side Components
There are no key components on the back of the BeagleBoard, but Figure 20 has been
provided for completeness.
Page 42 of 180
REF: BB_SRM
BeagleBoard System
Reference Manual
Revision C4
Figure 20. BeagleBoard Backside Components
This remainder of this section describes in detail the architecture and design of the
BeagleBoard.
You will notice certain things in this section.
o The schematic has been created for each section showing only the pertinent
components and their connections.
o The pin names differ from the actual schematic. For ease of reading, the names
have been truncated to only show the specific functions of that pin as used in the
design.
Page 43 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
8.2
Revision C4
Input Power
There are two possible sources of the 5V required by the BeagleBoard. It can come from
the USB OTG port connected to a PC, powered USB HUB, or a 5V DC supply. The USB
supply is sufficient to power the BeagleBoard. However, depending on the load needed
by the expansion port on BeagleBoard, additional power may be required. This is where
the DC supply comes in to play.
WARNING:
5V
DO NOT PLUG IN ANYTHING BUT
CONNECTOR OR THE BOARD WILL BE DAMAGED!
TO THE DC
It should also be noted that if an OTG configuration is used, for example tying two
BeagleBoards together via a UBS OTG cable, both of the BeagleBoards must be powered
by the DC supply. If the OTG port is used as a Host port, then the DC supply must also
be used.
Figure 21 is the design of the power input section.
6
G3
1
2
3
4
5
VB
DD+
ID
G1
USB_CLIENT
G5
PGB0010603MR
D3
G4
C129
0.1uF
10V
G2
7
VBUS_5V0
U1
LDO_PLDN
LDO_OUT
6
USB_5V
LDO_EN
ADJ
LDO_PG
R5 TP4
3
2
TESTPT1
10K,0603,DNI
PJ-002A
SW_PLDN
USB_PWR_EN
5
SW_EN
GND
2
3
1
SW_OUT
SW_OUT
SW_PG
9
8
13
12
MAIN_DC
DC_5V
J2
14
1
2
R6
1
JUMPER,DNI
0.1,0805
TPS2141
C1
7
J1
SW_IN
SW_IN
11
*
LDO_IN
P1
10
+
4
8
9
VBAT
C128 +
0.1uF
10V
10UF
Figure 21. Input Power Section
Page 44 of 180
REF: BB_SRM
8.2.1
BeagleBoard System
Reference Manual
Revision C4
USB DC Source
The USB specification requires that the current consumed prior to enumeration be limited
to 100mA @ 5V (500mW). The 5V DC from the USB is routed through the TPS2141
switch to insure that this requirement is met as uncharged capacitors on the BeagleBoard
can exhibit a large current drain during start up that could exceed this requirement. The
TPS2141 is a USB 2.0 Specification-compatible IC containing a dual-current limiting
power switch and an adjustable low dropout regulator (LDO). Both the switch and LDO
limit inrush current by controlling the turn on slew rate. The dual-current-limiting feature
of the switch allows USB peripherals to utilize high-value capacitance at the output of the
switch, while keeping the inrush current low.
During turn on, the switch limits the current delivered to the capacitive load to less than
100 mA. When the output voltage from the switch reaches about 93% of the input
voltage, the switch current limit increases to 800mA (minimum), at which point higher
current loads can be turned on. The higher current limit provides short circuit protection
while allowing the peripheral to draw maximum current from the USB bus.
When in the USB powered mode and no DC supply is connected, the TPS2141 is
enabled, allowing the power to be supplied to the board from the OTG port through the
integrated switch inside the TPS2141.
8.2.2
Wall Supply Source
A wall supply can be used to provide power to the board. A regulated 5V DC supply of at
least 500mA is required. It needs to have a 2.1mm plug with a center hot configuration.
WARNING:
DO NOT PLUG IN ANYTHING BUT
CONNECTOR OR THE BOARD WILL BE DAMAGED!
5V
TO THE DC
In the event that a higher DC load is required due to the addition of a Daughtercard a
higher current supply can be used. The maximum current should not exceed 2A.
8.2.3
DC Source Control
Unlike when powering from the USB OTG port, in the case of the DC voltage, the
current limiting is not required. As long as the DC supply is not connected, the switch for
the USB is enabled. When the DC supply is plugged in, the switch is disabled because the
ground is removed from pin 5 of the TPS2141. This insures that the 5V from the USB is
not connected by disabling the internal FET. In the case where there is no USB plugged
in, there is no 5V available to be routed so the removal of the pullup in pin 5 has no
affect.
Page 45 of 180
REF: BB_SRM
BeagleBoard System
Reference Manual
Revision C4
When in the DC mode of operation, the USB OTG can be used in the Host or Client
modes. The TPS65950 will be responsible for handling the supply of the VBUS_5V0 rail
in the OTG or Host modes. As this is limited to 100mA, a powered hub must be used to
support peripherals on the OTG port.
8.2.4
3.3V Supply
The TPS2141 has an integrated 3.3V LDO which is being used to supply the 3.3V as
required on the BeagleBoard for the DVI-D interface and the UART. The input to the
LDO is supplied by the main DC_5V. This insures that the power to the LDO can be
supplied by either the USB or the DC wall supply and that the current measurement
includes the 3.3V supply.
8.2.5
Meter Current Measurement
Jumper J2 is a header that allows for the voltage drop across the resistor to be measured
using a meter, providing a way to measure the current consumption of the BeagleBoard
from the main voltage rails, either USB or DC. The resistor, R6, is a .1 ohm resistor
across which the voltage is measured. The reading you get is .1mV per mA of current.
8.2.6
Processor Current Measurement
The resistor across J2 can also be used to measure the current of the board by reading the
voltage drop across R6 from software. There are two pairs of resistors provided on the
TPS65950 that measure the voltage on either side of R6. This is done via the I2C control
bus to the TPS65950 from the OMAP3530 processor. These values along with resistance
of R6, are used to calculate the current consumption of the board. Figure 22 is the
schematic of the measurement circuitry.
The maximum value that can be input to the ADC inputs is based on the setting of the
VINTANA2.OUT voltage rail which defaults to 2.5V. In order to prevent the voltage
levels from exceeding this value a pair of resistors of 12K and 10K is used to scale the
voltage down.
Page 46 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Revision C4
Figure 22. Processor Current Measurement
This results in a value that is 46% of the actual value. So, for a maximum value of 5.25V,
the voltage read would be 2.415V which keeps it below the 2.5V pint.
The voltage drop across R6 will be small as the value of the resistor is 0.1 ohms. For
every 100 mA of current a voltage of the .01V will be detected. In order to determine the
actual power, the input voltage and the voltage drop must be measured.
8.3
Power Conditioning
This circuitry regulates the DC input to a nominal 4.2VDC level. This is required in order
to meet the maximum DC voltage level as specified by the TPS65950 Power
Management device which is 4.7V. Using 4.2V gives us some margin and meets the
nominal 4.2V rating of the TPS65950.
Figure 23 is the power conditioning section of the BeagleBoard.
Page 47 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
VBAT
EN
NC1
GND
FB
TPS73701
1
6
7
3
VBAT_FB
4.2V
*
OUT
NC2
NC3
POWER
R7
R8
56.2K,0603
+
22.6K,0603
10UF
0.1uF
10V
C2
C3
0.1uF
10V
D5
D5_RES
C109
GRN
5
2
4
IN
*
U2
8
Revision C4
R9
330,0603
0.125W
Figure 23. Power Conditioning
The TPS65950 provides the main power rails to the board and has a maximum limit of
4.7V on its VBAT input and a nominal of 4.2V. U2, the TPS73701, is used to convert the
DC_5V, which can come from a DC wall supply or the USB, to 4.2V to meet this
requirement. The TPS737701 is a linear low-dropout (LDO) voltage regulator and is
thermal shutdown and current limit protected. It has the ability to deliver 1A of current,
although this is far and above the requirements of the board. By adjusting the values of
R7 and R8, the actual voltage can be adjusted if needed. The LED D5 is an indication
that the 4.2V is present.
8.4
TPS65950 Reset and Power Management
The TPS65950 supplies several key functions on the BeagleBoard. This section covers a
portion of those functions centered on the power and reset functions. Included in this
section is:
o
o
o
o
o
Main Core Voltages
Peripheral Voltages
Power Sequencing
Reset
Current measurement via SW
The other functions are covered in other sections in this document and are grouped by
their overall board functions. The explanation of the various regulators found on the
TPS65950 is based upon how they are used in the board design and are not intended to
reflect the overall capability of the TPS65950 device. Please refer to the TPS65950
documents for a full explanation of the device operation.
Page 48 of 180
REF: BB_SRM
8.4.1
BeagleBoard System
Reference Manual
Revision C4
Main Core Voltages
The TPS65950 supplies the three main voltage rails for the OMAP3530 processor and
the board:
o
o
o
VOCORE_1V3 (1.2V, adjustable)
VDD2
(1.3V)
VIO_1V8
(1.8V)
The VOCORE_1V3 defaults to 1.2V at power up, but can be adjusted by software to the
1.3V level. Figure 24 is the interfacing of the TPS65950 to the system as it provides the
three main rails.
8.4.2
Main DC Input
The main supply to the TPS65950 for the main rails is the VBAT rail which is a nominal
4.2V. Each rail has a filter cap of 10uF connected to each of the three inputs. A .1uF cap
is also provided for high frequency noise filtering.
8.4.3
OMAP3530 I2C Control
The various components in the TPS65950 are controlled from the OMAP3530 via the
I2C interface. I2C_0 is used to control the TPS65950 device.
8.4.4
VIO_1V8
The VIO_1V8 rail is generated by the TPS65950 VIO regulator. The VIO output is a
stepdown converter with a choice of two output voltage settings: 1.8 V or 1.85 V. The
voltage is set by configuring the VSEL bit (VIO_VSEL[0]). When the VSEL bit is set to
0, the output voltage is 1.8 V, and when it is set to 1, the output voltage is 1.85 V.
When the TPS65950 resets, the default value of this LDO is 1.80 V; the OMAP3530
must write 1 to the VSEL field to change the output to 1.85 V. The default for the
BeagleBoard is 1.8V. This regulator output is used to supply power to the system
memories and I/O ports. It is one of the first power supplies to be switched on in the
power-up sequence. VIO does not support the SmartReflex voltage control schemes.
VIO can be put into sleep or off mode by configuring the SLEEP_STATE and
OFF_STATE fields of the VIO_REMAP register.
Page 49 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Revision C4
U5B
Power control
8
A10
REGEN
REGEN
VBAT
F8
D6
4
I2C4_SCL
4
I2C4_SDA
4
nSLEEP
B14
C4
P7
G9
VMODE1(VDD1)
VMODE2(VDD2)/I2C.SR.SCL
N.C.
N.C./I2C.SR.SDA
nSLEEP1
nSLEEP2
VBAT
CP.CAPP
C108
C72
2.2uF,0603
10V
4.7uf ,CER,0402
CP.CAPM
VBAT
L1 TESTPT1
1
T2_VDD1.L
1uH,2A
C77
C76
0.1uF
10V
10uF,CER,JMK,0805
T6
R6
E13
2
C78
R7
T7
D14
E14
E15
TP7
VOCORE_1V3
IO_1P8
C14
D15
D16
10uF,CER,JMK,0805
B15
C15
C16
CP.IN
CP.CAPP
USB CP
CP.CAPM
CP.GND
VDD1.IN
VDD1.IN
VDD1.IN
VDD1
VDD1.OUT
VDD1.L
VDD1.L
VDD1.L
VDD1.GND
VDD1.GND
VDD1.GND
VBAT
VDD2
TP12
R13
P14
VDD2
TESTPT1
L2
1
N13
2
T2_VDD2.L
1uH
C84
C83
C85
0.1uF
10V
10uF,CER,JMK,0805
TP14
T14
R15
10uF,CER,JMK,0805
N3
1uH,2A
VDD2.L
VDD2.L
VDD2.GND
VDD2.GND
VIO
P3
R4
L3
1
VDD2.FB
VBAT
TESTPT1
VIO_1V8
T13
R14
VDD2.IN
VDD2.IN
2
C99
C97
0.1uF
10V
10uF,CER,JMK,0805
T2_VIO.L
C95
10uF,CER,JMK,0805
R3
T4
R2
T3
VIO.IN
VIO.IN
VIO.OUT
VIO.L
VIO.L
VIO.GND
VIO.GND
Figure 24. Main Power Rails
Page 50 of 180
REF: BB_SRM
8.4.5
BeagleBoard System
Reference Manual
Revision C4
Main Core Voltages Smart Reflex
VDD1 and VDD2 regulators on the TPS65950 provide SmartReflex-compliant voltage
management. The SmartReflex controller in the OMAP3530 interfaces with the
TPS65950 counterpart through the use of a dedicated I2C bus. The OMAP3530
computes the required voltage and informs the TPS65950 using the SmartReflex I2C
interface.
SmartReflex control of the VDD1 and VDD2 regulators can be enabled by setting the
SMARTREFLEX_ENABLE bit (DCDC_GLOBAL_CFG[3]) to 1. To perform VDD1
voltage control through the SmartReflex interface, the TPS65950 provides the
VDD1_SR_CONTROL register. The MODE field of the VDD1_SR_CONTROL register
can be set to 0 to put VDD1 in an ACTIVE state; setting the field to 1 moves VDD1 to a
SLEEP state. VDD1 output voltage can be programmed by setting the VSEL field of the
VDD1_SR_ CONTROL register. The VDD1 output voltage is given by VSEL*12.5 mV
+ 600 mV.
8.4.6
VOCORE_1V3
The VOCORE_1V3 rail is supplied by the VDD1 regulator of the TPS65950. The
VDD1 regulator is a 1.1A stepdown power converter with configurable output voltage
between 0.6 V and 1.45 V in steps of 12.5 mV. This regulator is used to power the
OMAP3530 core.
The OMAP3530 can request the TPS65950 to scale the VDD1 output voltage to reduce
power consumption. The default output voltage at power-up depends on the boot mode
settings, which in the case of the BeagleBoard is 1.2V. The output voltage of the VDD1
regulator can be scaled by software or hardware by setting the ENABLE_VMODE bit
(VDD1_VMODE_CFG[0]). In each of these modes, the output voltage ramp can be
single-step or multiple-step, depending on the value of the STEP_REG field of the
VDD1_STEP[4:0] register. The VOCORE_1V3 rail should be set to 1.3V after boot up.
Apart from these modes, the VDD1 output voltage can also be controlled by the
OMAP3530 through the SmartReflex I2C interface between the OMAP3530 and the
TPS65950. The default voltage scaling method selected at reset is a software-controlled
mode. Regardless of the mode used, VDD1 can be configured to the same output voltage
in sleep mode as in active mode by programming the DCDC_SLP bit of the
VDD1_VMODE_CFG[2] register to 0. When the DCDC_SLP bit is 1, the sleep mode
output voltage of VDD1 equals the floor voltage that corresponds to the VFLOOR field
(VDD1_VFLOOR[6:0]).
8.4.7
VDD2
The VDD2 voltage rail is generated by the TPS65950 using the VDD2 regulator. The
VDD2 regulator is a stepdown converter with a configurable output voltage of between
Page 51 of 180
REF: BB_SRM
BeagleBoard System
Reference Manual
Revision C4
0.6 V and 1.45 V and is used to power the OMAP3530 core. VDD2 differs from VDD1
in its current load capabilities with an output current rating of 600 mA in active mode.
The VDD2 provides different voltage regulation schemes. When VDD2 is controlled by
the VMODE2 signal or with the SmartReflex interface, the range of output voltage is 0.6
V to 1.45 V. The use of the VMODE2 signal and the VDD2_VMODE_CFG,
VDD2_STEP, VDD2_FLOOR, and VDD2_ROOF registers is similar to the use of the
corresponding signals and registers for VDD1. VDD2 shares the same SmartReflex I2C
bus to provide voltage regulation. The VDD2_SR_CONTROL register is provided for
controlling the VDD2 output voltage in SmartReflex mode.
When the VDD2 is used in software-control mode, the VSEL (VDD2_
DEDICATED[4:0]) field can be programmed to provide output voltages of between 0.6
V and 1.45 V. The output voltage for a given value of the VSEL field is given by
VSEL*12.5 mV + 600 mV. If the VSEL field is programmed so that the output voltage
computes to more than 1.45 V, the TPS65950 sets the VDD2 output voltage to 1.5 V.
8.5
Peripheral Voltages
There are six additional voltages used by the system that are generated by the TPS65950.
These are:
o
o
o
o
o
o
VDD_PLL2
VDD_PLL1
VDAC_1V8
VDD_SIM
VMMC1
VAUX2
Figure 25 shows the peripheral voltages supplied by the TPS65950.
8.5.1
VDD_PLL2
This programmable LDO is used to power the OMAP3530 PLL circuitry. The VPLL2
LDO can be configured through the I2C interface to provide output voltage levels of 1.0
V, 1.2 V, 1.3 V, or 1.8 V, based on the value of the VSEL field
(VPLLI_DEDICATED[3:0]). On the board this rail is used to power DVI output for pins
DSS_DATA(0:5), DSS_DATA(10:15) and DSS_DATA(22:23). The VPLL2 must be set
to 1.8V for proper operation of the DVI-D interface.
8.5.2
VDD_PLL1
The VPLL1 programmable LDO regulator is low-noise, linear regulator used for the
OMAP3530 PLL supply. The VDD_PLL1 rail is initialized to 1.8V.
Page 52 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
U5B
FBGA209_15-74_280x280
VAC
BCI
ICTLAC1
ICTLAC2
ICTLUSB1
ICTLUSB2
VPRECH
PCHGAC
PCHGUSB
VCCS
VBATS
VBAT
BCIAUTO
Backup battery
IO Level
BKBAT
IO.1P8
Revision C4
N5
N7
P2
P6
P1
N2
T2_VPRECH
C71
N4
N6
P5
P4
R5
VBAT
1uF,CER
N1
M14
C8
VIO_1V8
VIO_1P8
C73
10V
0.1uF
IO_1P8
VBAT.RIGHT
VBAT.RIGHT
VBAT.LEFT
VBAT.LEFT
D11
D12
D9
D10
C75
C74
1uF,CER
1uF,CER
VBAT
VMMC2.IN
VMMC1.IN
VAUX4.IN
VBAT.USB
VDAC.IN
VAUX12S
VPLLA3R
VINT
A3
C1
B2
R9
K1
L1
H15
K15
C79
C80
C81
C82
TP8
1uF,CER 1uF,CER 1uF,CER 1uF,CER
TP9
TP10
TP11
TESTPT1 TESTPT1
TESTPT1
TESTPT1
VPLL2
VPLL1
VDAC.OUT
VSIM
VMMC2.OUT
VMMC1.OUT
VAUX4.OUT
VAUX3.OUT
VAUX2.OUT
VAUX1.OUT
J15
H14
L2
K2
A4
C2
B3
G16
M3
M2
VDD_PLL2
VDD_PLL1
VDAC_1V8
VDD_SIM
VMMC1
TP13
C86
C87
C88
1uF,CER
2.2uF,CER 1uF,CER
C89
C90
1uF,CER
1uF,CER
TESTPT1
VDD_EHCI
VINTUSB1P8
VINTUSB1P5
VUSB.3P1
VINTDIG
VRTC
VINTANA2.OUT
VINTANA2.OUT
VINTANA1.OUT
P10
P8
P9
L16
K16
B6
J2
H3
VINTUSB1P8 C91
VINTUSB1P5
VUSB.3P1
VINTDIG
VRTC
VINTANA2.OUT
VINTANA1.OUT
1uF,CER
10V
C92 1uF,CER
C93
C100
1uF,CER
C94 1uF,CER
C96
1uF,CER
C98 1uF,CER
1uF,CER
Figure 25. Peripheral Voltages
Page 53 of 180
REF: BB_SRM
8.5.3
BeagleBoard System
Reference Manual
Revision C4
VDAC_1V8
The VDAC programmable LDO regulator is a high-PSRR, low-noise, linear regulator
that powers the OMAP3530 dual-video DAC. It is controllable with registers via I2C and
can be powered down if needed. The VDAC LDO can be configured to provide 1.2V, 1.3
V, or 1.8 V in on power mode, based on the value of the VSEL field
(VDAC_DEDICATED[3:0]). The VDAC_1V8 rail should be set to 1.8V for the
BeagleBoard.
8.5.4
VDD_SIM
This voltage regulator is a programmable, low dropout, linear voltage regulator supplying
the bottom 4 bits of the 8 bit SD/MMC card slot. The VSEL field
(VSIM_DEDICATED[3:0]) can be programmed to provide output voltage of 1.0 V, 1.2
V, 1.3 V, 1.8 V, 2.8 V, or 3.0 V and can deliver up to 50mA. The default output voltage
of this LDO as directed by the TPS65950 boot pins is 1.8V.
8.5.5
VMMC1
The VMMC1 LDO regulator is a programmable linear voltage converter that powers the
MMC1 slot and includes a discharge resistor and overcurrent protection (short-circuit).
This LDO regulator can also be turned off automatically when the MMC card extraction
is detected. The VMMC1 LDO is powered from the main VBAT rail. The VMMC1 rail
defaults to 3.0V as directed by the TPS65950 boot pins and will deliver up to 220mA. It
can be set to 3.0V in the event 3V cards are being used.
8.5.6
VAUX2
The VAUX2 LDO regulator is a programmable linear voltage converter that powers the
1.8V I/O rail of the USB PHY and includes a discharge resistor and overcurrent
protection (short-circuit). The VAUX2 LDO is powered from the main VBAT rail. The
VMMC1 rail defaults to 3.0V as directed by the TPS65950 boot pins and will deliver up
to 220mA. The voltage rail is labeled VDD_EHCI on the schematic.
8.5.7
Boot Configuration
The boot configuration pins on the TPS65950 determine the power sequence of the
device. For the OMAP3530 support, the boot pin configuration is fixed at:
o BOOT0 tied to VBAT
o BOOT1 tied to Ground.
Page 54 of 180
REF: BB_SRM
8.5.8
BeagleBoard System
Reference Manual
Revision C4
RTC Backup Battery
An optional battery to backup the Real Time Clock that is in the TPS65950. The board
does not come equipped with the battery. The battery can be purchased from DigiKey or
other component suppliers. When the battery is not installed, R66 must be installed. You
must make sure that prior to installing the battery that R66 is removed.
Refer to section 9.11 for information on the battery selection and installation.
Page 55 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
8.5.9
Revision C4
Power Sequencing
Based on the boot configuration pins, the TPS65950 knows the type of OMAP processor
that it needs to support, in this case the OMAP3530. The voltages are ramped in a
sequence that is compatible with the OMAP3530 processor. Figure 26 is the sequence in
which the power rails, clocks, and reset signal come up.
Figure 26. Power Sequencing
Page 56 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Revision C4
8.5.10 Reset Signals
The BeagleBoard uses three distinct reset circuits:
o Warm Reset
o Cold Reset
o User Reset
Figure 27 shows the connections for the Reset interfaces.
U5A
T
P
S
6
5
9
5
0
OMAP3530_ES3.0
U3B
R47
J3
4.7K
VIO_1V8
AH25
AF24
2
4
6
8
10
12
14
16
18
20
22
24
26
28
SYS_nRESPWRON
SYS_nRESWARM/GPIO_30
VBAT
IO_1P8
nRESPWRON
nRESWARM
VBAT
PWRON
A13
B13
nRESPWRON
nRESWARM
A11
PWRON
4.7K
OMAP3
VIO_1V8
R45
VIO_1V8
C8
nRESET
R53
DNI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
S2
0.1uF
5
1
U4A
R37
10K
4
2
3
1
6
B3F-1000
SN74LVC2G07DCKR
2
Figure 27. Reset Circuitry
8.5.10.1
Warm Reset
The warm reset is generated by the OMAP3530 processor on power up. The
nRESWARM signal is a bidirectional reset. When an internal reset occurs,
nRESWARM goes low and resets all the peripherals and the TPS65950. The TPS65950
can be configured to perform a warm reset of the device to bring it into a known defined
state by detecting a request for a warm reset on the NRESWARM pin. The minimum
duration of the pulse on the nRESWARM pin should be two 32-kHz clock cycles. The
nRESWARM output is open-drain; consequently, an external pullup resistor is required.
There is no way for the user to generate a warm reset on the BeagleBoard.
8.5.10.2
Cold Reset
On power up as shown in Figure 27, the TPS65950 generates nRESPWRON, power on
reset. The signal from the TPS65950 is an output only and is not an open drain signal.
By running the signal through a buffer, SN74LVC2G07, the signal becomes open drain,
which requires a pullup on the signal. This will allow the nRESPWRON signal to be
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Revision C4
pulled low, by pressing the reset switch S2, to force a reset to the OMAP3530 processor
and to any device on the expansion card that require a reset.
It also allows for the reset signal to be pulled low or held low for an extended time by
circuitry on the expansion card if needed.
8.5.10.3
User Reset
The USER RESET button can be used to request a Warm Reset from the processor. After
initialization, this pin becomes an input to the processor. By pushing the Reset button, an
interrupt is generated into the OMAP3530 processor. The software that is run as a result
of this can then do whatever housekeeping is required and then send the processor into a
reset mode.
8.5.10.4
PWRON
You will notice another signal on the TPS65950 called PWRON. This signal is
referenced in the TPS65950 documentation. In the BeagleBoard design it is not used but
it is pulled high to insure the desired operation is maintained.
8.5.11 mSecure Signal
This signal provides for protection of the RTC registers in the TPS65950 be disabling
that function via a control signal form the OMAP3530 processor.
For more information on the operation on the signal, please refer to the OMAP3530
Technical Reference Manual.
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8.6
Revision C4
OMAP3530 Processor
The heart of BeagleBoard is the OMAP3530 processor. Figure 28 is a high level block
diagram of the OMAP3530.
Figure 28. OMAP3530 Block Diagram
8.6.1
Overview
The OMAP3530 high-performance, multimedia application device is based on the
enhanced OMAP™ 3 architecture and is integrated on TI's advanced 65-nm process
technology. The OMAP3530 architecture is configured with different sets of features in
different tier devices. Some features are not available in the lower-tier devices. For more
information, refer to the OMAP3530 Technical Reference Manual (TRM).The
architecture is designed to provide best-in-class video, image, and graphics processing
sufficient to various applications.
The OMAP3530 supports high-level operating systems (OSs), such as:
o Windows CE
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o
o
o
o
BeagleBoard System
Reference Manual
Revision C4
Linux
QNX
Symbian
Others
This OMAP3530 device includes state-of-the-art power-management techniques required
for high-performance low power products. The OMAP3530 supports the following
functions and interfaces on the BeagleBoard:
o Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8™
microprocessor
o POP Memory interface
o 2Gb MDDR (256Mbytes)
o 2Gb NAND Flash (256Mbytes)
o 24 Bit RGB Display interface (DSS)
o SD/MMC interface
o USB OTG interface
o NTSC/PAL/S-Video output
o Power management
o Serial interface
o I2C interface
o I2S Audio interface (McBSP2)
o Expansion McBSP1
o JTAG debugging interface
8.6.2
SDRAM Bus
The SDRAM bus is not accessible on the BeagleBoard. Its connectivity is limited to the
POP memory access on the top of the OMAP3530 and therefore is only accessible by the
SDRAM memory.
The base address for the DDR SDRAM in the POP device is 0x8000 0000.
8.6.3
GPMC Bus
The GPMC bus is not accessible on the BeagleBoard. Its connectivity is limited to the
POP memory access on the top of the OMAP3530 and therefore is only accessible by the
NAND memory.
The memory on the GPMC bus is NAND and therefore will support the classical NAND
interface. The address of the memory space is programmable.
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8.6.4
BeagleBoard System
Reference Manual
Revision C4
DSS Bus
The display subsystem provides the logic to display a video frame from the memory
frame buffer in SDRAM onto a liquid-crystal display (LCD) display via the DVI-D
interface or to a standalone LCD panel via the LCD interface connectors. The logic levels
of the LCD expansion connectors are 1.8V so it will require buffering of the signals to
drive most LCD panels. The DSS is configured to a maximum of 24 bits, but can be used
in lower bit modes if needed.
8.6.5
McBSP2
The multi-channel buffered serial port (McBSP) McBSP2 provides a full-duplex direct
serial interface between the OMAP3530 and the audio CODEC in the TPS65950 using
the I2S format. Only four signals are supported on the McBSP2 port. Figure 29 is a
depiction of McBSP2.
Figure 29. McBSP2 Interface
8.6.6
McBSP1
McBSP1 provides a full-duplex direct serial interface between the OMAP3530 and the
expansion interface. There are 6 signals supported on McBSP1, unlike the 4 signals on
the other ports. Figure 30 is a diagram of McBSP1.
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Revision C4
Figure 30. McBSP1 Interface
8.6.7
McBSP3
McBSP3 provides a full-duplex direct serial interface between the OMAP3530 and the
expansion interface. Figure 31 is a diagram of McBSP3.
Figure 31. McBSP3 Interface
8.6.8
Pin Muxing
On the OMAP3530, the majority of pins have multiple configurations that the pin can be
set to. In essence, the pin can become different signals depending on how they are set in
the software. In order for the BeagleBoard to operate, the pins used must be set to the
correct signal. In some cases, the default signal is the correct signal. Each pin can have a
maximum of 8 options on the pin. This is called the pin mode and is indicated by a three
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Revision C4
bit value (0:3). In the case of the signals going to the expansion connector, the settings
required for those pins depends on how they are to be used. For an explanation of the
options, please refer to the Expansion Header section. Each pin can be set to a different
mode independent of the other pins on the connector.
Table 4 is a list of all of the signals used on the OMAP3530 for the BeagleBoard and the
required mode setting for each pin. Where the default setting is needed, it will be
indicated. The USER notation under mode indicates that this is an expansion signal and
can be set at the discretion of the user. A FIXED indicates that there is only one function
for that signal and that it cannot be changed,
Table 4.
OMAP3530 Pin Muxing Settings
Signal
Mode
DSS
MMC1
MMC2
UART3
GPMC
UART1
I2C1
I2C2
I2C3
I2C4
JTAG
TV_OUT
SYS_nRESPWRON
SYS_nRESWARM
SYS_nIRQ
SYS_OFF
SYS_CLKOUT
SYS_CLKOUT2
SYS_CLKREQ
SYS_XTALIN
GPIO_149
GPIO_150
McBSP1
McBSP2
McBSP3
GPIO_171
GPIO_172
Default
Default
User
Default
Default
Default
Default
Default
Default
Default
FIXED
Default
Default
Default
Default
Default
Default
Default
Default
FIXED
4
4
Default
User
Default
4
4
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8.6.9
Revision C4
GPIO Mapping
There are a number of GPIO pins from the OMAP3530 that are used on the BeagleBoard
design. Table 5 shows which of these GPIO pins are used in the design and whether they
are inputs or outputs. While GPIO pins can be used as interrupts, the table only covers the
GPIO pin mode. If it is an interrupt, then it is covered in the interrupt section.
Table 5.
OMAP
PIN
AA9
W8
AG9
J25
AE21
OMAP3530 GPIO Pins
INT/GPIO
I/O
Signal
USAGE
GPIO_149
GPIO_150
GPIO_23
GPIO_170
GPIO_7
O
O
I
O
I
LED_GPIO149
LED_GPIO149
MMC1_WP
DVI_PUP
SYSBOOT_5
Controls User LED0
Controls User LED1
SD/MMC card slot Write protect
Controls the DVI-D interface. A Hi = DVI-D enabled.
Used to put the device in the boot mode or as a user button
input
Other signals, such as those that connect to the expansion connector, may also be set as a
GPIO pin. For information on those, refer to the Expansion Connector section.
8.6.10 Interrupt Mapping
There are a small number of pins on the OMAP3530 that act as interrupt. Some of these
interrupts are connected to the TPS65950 and their status is reflected through the main
TPS65950 interrupt. Table 6 lists the interrupts.
Table 6.
TPS65950
Pin
P12
OMAP
PIN
AF26
AH8
OMAP3530 Interrupt Pins
INT/GPIO
USAGE
SYS_nIRQ
GPIO_29
GPIO0
Interrupt from the TPS65950
SD Write protect lead. Can be polled or set to an interrupt.
MMC1 card detect input. Goes to the OMAP3530 over the
SYS_nIRQ pin.
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8.7
Revision C4
POP Memory Device
The OMAP3530 uses what is called POP (Package-on-Package) memory. The memory is
a MCP (Multi Chip Package) that contains both the Mobile DDR SDRAM and the
NAND Flash. Figure 32 shows the POP Memory concept.
Figure 32. POP Memory
The Memory device mounts on top of the OMAP3530 device. The configuration used on
the board is a 2Gb NAND Flash plus 2Gb MDDR SDRAM device from Micron.
8.8
System Clocks
There are three clocks needed for the operation of the BeagleBoard, 32KHz, 26MHz and
McBSP_CLKS. Figure 33 shows the components that make up the System Clocks.
Figure 33. System Clocks
8.8.1
32KHz Clock
The 32KHz clock is needed for the TPS65950 and the OMAP3530 and is provided by
the TPS65950 via the external 32KHz crystal, Y2. The TPS65950 has a separate output
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Revision C4
from the crystal to drive the OMAP3530 that buffers the resulting 32-kHz signal and
provides it as 32KCLKOUT, which is provided to the OMAP3530 on ball AE25. The
default mode of the 32KCLKOUT signal is active, but it can be disabled if desired under
SW control.
The 32.768-kHz clock drives the RTC embedded in the TPS65950. The RTC is not
enabled by default; the host processor must set the correct date and time to enable the
RTC.
8.8.2
26MHz Clock
This section describes the 26MHz clock section of the BeagleBoard.
8.8.2.1
26MHz Source
The BeagleBoard is designed to support two suppliers of the 26MHz oscillator. The
26MHz clock is provided by an onboard oscillator, Y1. The TPS65950 receives the
external HFCLKIN signal on ball A14 and uses it to synchronize or generate the clocks
required to operate the TPS65950 subsystems. The TPS65950 must have this clock in
order to function to the point where it can power up the BeagleBoard. This is the reason
the 26MHz clock is routed through the TPS65950.
8.8.2.2
TPS65950 Setup
When the TPS65950 enters an active state, the OMAP3530 must immediately indicate
the HFCLKIN frequency (26 MHz) by setting the HFCLK_FREQ bit field (bits [1:0]) in
the CFG_BOOT register of the TPS65950. HFCLK_FREQ has a default of being not
programmed, and in that condition, the USB subsection does not work. The three DCDC
switching supplies (VIO, VDD1, and VDD2) operate from their free-running 3-MHz
(RC) oscillators, and the PWR registers are accessed at a default 1.5-M byte.
HFCLK_FREQ must be set by the OMAP3530 during the initial power-up sequence. On
the BeagleBoard, this is done by the internal boot ROM on startup.
8.8.2.3
OMAP3530 26MHz
The 26MHz clock for the OMAP3530 is provided by the TPS65950 on ball R12 through
R38, a 33 ohm resistor is providing to minimize any reflections on the clock line. The
clock signal enters via ball AE17 on the OMAP3530.
8.8.3
McBSP_CLKS
An additional clock is also provided by the TPS65950 called McBSP_CLKS. This clock
is provided to the OMAP3530 in order to insure synchronization of the I2S interface
between the OMAP3530 and the TPS65950.
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8.9
BeagleBoard System
Reference Manual
Revision C4
USB OTG Port
The BeagleBoard has a USB OTG (On-the-Go) port. It can be used as an OTG port,
Client port, or Host port. The main use is as a client port, as that is the mode that will
supply the power needed to power the BeagleBoard.
NOTE: In order to use the OTG in the Host mode, the
BeagleBoard must be powered from the DC supply.
8.9.1
USB OTG Overview
USB OTG is a supplement to the USB 2.0 specification. The standard USB uses a
master/slave architecture, a USB host acting as a master and a USB peripheral acting as a
slave. Only the USB host can schedule the configuration and data transfers over the link.
The USB peripherals cannot initiate data transfers, they only respond to instructions
given by a host.
USB OTG works differently in that gadgets don't need to be pure peripherals because
they can sometimes act as hosts. An example might be connecting a USB keyboard or
printer to BeagleBoard or a USB printer that knows how to grab documents from certain
peripherals and print them. The USB OTG compatible devices are able to initiate the
session, control the connection and exchange Host/Peripheral roles between each other.
The USB OTG supplement does not prevent the use of a hub, but it describes role
swapping only in the case of a one-to-one connection where two OTG devices are
directly connected. If a standard hub is used, the supplement notes that using it will lead
to losing USB OTG role-swap capabilities making one device as the Default-Host and the
other as the Default-Peripheral until the hub is disconnected.
The combination of the OMAP3530 and the TPS65950 allows the BeagleBoard to work
as an OTG device if desired. The primary mode of operation however, is intended to be a
client mode in order to pull power from the USB host which is typically a PC. As the Rev
B does not have a Host USB port, this port will be used as a Host port in many
applications.
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8.9.2
Revision C4
USB OTG Design
Figure 34 is the design of the USB OTG port on the BeagleBoard.
DATA0/UART4.TXD
DATA1/UART4.RXD
DATA2/UART4.RTSI
DATA3/UART4.CTSO/GPIO.12
DATA4/GPIO.14
DATA5/GPIO.3
DATA6/GPIO.4
DATA7/GPIO.5
PGB0010603MR
D1
D2
T2_VBUS
0,0603
R8
PGB0010603MR
D3
6
G3
G2
VB
DD+
ID
G1
G4
USB_CLIENT_ID
USB_CLIENT
D4
PGB0010603MR
P1
PGB0010603MR
J6
JUMPER,DNI
VBUS_5V0
R43
1
2
3
4
5
8
T11
T10
R11
9
UCLK
DN/UART3.TXD
STP/GPIO.9 DP/UART3.RXD
DIR/GPIO.10
ID
NXT/GPIO.11
1
K14
K13
J14
J13
G14
G13
F14
F13
USB0HS_DAT0
USB0HS_DAT1
USB0HS_DAT2
USB0HS_DAT3
USB0HS_DAT4
USB0HS_DAT5
USB0HS_DAT6
USB0HS_DAT7
U5A
+
4
4
4
4
4
4
4
4
L15
L14
L13
M13
USB0HS_CLK
USB0HS_STP
USB0HS_DIR
USB0HS_NXT
2
4
4
4
4
G5
7
VBUS_5V0
C129
0.1uF
10V
VBUS
C127
TWL4030
TPS65950
10V
4.7uf ,CER,0402
Figure 34. USB OTG Design
8.9.3
OTG ULPI Interface
ULPI is an interface standard for high-speed USB 2.0 systems. It defines an interface
between USB link controller (OMAP3530) and the TPS65950 that drives the actual bus.
ULPI stands for UTMI+ low pin interface and is designed specifically to reduce the pin
count of discrete high-speed USB PHYs. Pin count reductions minimize the cost and
footprint of the PHY chip on the PCB and reduce the number of pins dedicated to USB
for the link controller.
.
Unlike full- and low-speed USB systems, which utilize serial interfaces, high-speed
requires a parallel interface between the controller and PHY in order to run the bus at
480Mbps. This leads to a corresponding increase in complexity and pin count. The ULPI
used on the BeagleBoard keeps this down to only 12 signals because it combines just
three control signals, plus clock, with an 8-bit bi-directional data bus. This bus is also
used for the USB packet transmission and for accessing register data in the ULPI PHY.
8.9.3.1
OMAP3530 Interface
The controller for the ULPI interface is the OMAP3530. It provides all of the required
signals to drive the interface. Table 7 describes the signals from the OMAP3530 that are
used for the USB OTG interface.
Table 7.
Signal
hsusb0_clk
OMAP3530 ULPI Interface
Description
Dedicated for external transceiver 60-MHz clock input from PHY
Type
Ball
I
T28
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hsusb0_stp
hsusb0_dir
hsusb0_nxt
hsusb0_data0
hsusb0_data1
hsusb0_data2
hsusb0_data3
hsusb0_data4
hsusb0_data5
hsusb0_data6
hsusb0_data7
8.9.3.2
Revision C4
Dedicated for external transceiver Stop signal
Dedicated for external transceiver Data direction control from PHY
Dedicated for external transceiver Next signal from PHY
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
Transceiver Bidirectional data bus
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T25
R28
T26
T27
U28
U27
U26
U25
V28
V27
V26
TPS65950 Interface
The TPS65950 USB interfaces to the OMAP3 over the ULPI interface. Table 8 is a list
of the signals used on the TPS65950 for the ULPI interface.
Table 8.
Signal
UCLK
STP
DIR
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
8.9.4
OMAP3530 ULPI Interface
Description
High speed USB clock
High speed USB stop
High speed USB dir
High speed USB direction
High speed USB Data bit 0
High speed USB Data bit 0
High speed USB Data bit 0
High speed USB Data bit 0
High speed USB Data bit 0
High speed USB Data bit 0
High speed USB Data bit 0
High speed USB Data bit 0
Type
Ball
I/O
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L15
L14
L13
M1
K14
K13
J14
J13
G14
G13
F14
F13
OTG Charge Pump
When the TPS65950 acts as an A-device, the USB charge pump is used to provide 4.8
V/100 mA to the VBUS pin. When the TPS65950 acts as a B-device, the USB charge
pump is in high impedance. If used in the OTG mode as an A-device, the BeagleBoard
will need to be powered from the DC supply. If acting as a B-device, there will not be a
voltage source on the USB OTG port to drive the BeagleBoard. Table 9 describes the
charge pump pins.
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Table 9.
Signal
CP.IN
CP.CAPP
CP.CAPM
CP.GND
Revision C4
USB OTG Charge Pump Pins
Description
The charge pump input voltage. Connected to VBAT.
The charge pump flying capacitor plus.
The charge pump flying capacitor minus.
The charge pump ground.
Type
Ball
Power
O
O
GND
R7
L14
T6
R6
The charge pump is powered by the VBAT voltage rail. The charge pump generates a
4.8-V (nominal) power supply voltage to the VBUS pin. The input voltage range is 2.7 V
to 4.5 V so the 4.2V VBAT is within this range. The charge pump operating frequency is
1 MHz. The charge pump integrates a short-circuit current limitation at 450 mA.
8.9.5
OTG USB Connector
The OTG USB interface is accessed through the miniAB USB connector. If you want to
use the OTG port as a USB Host, pin 4 of the connector must be grounded. The Rev C4
version of Beagle provides jumper pad, J6 that allows for a small piece of solder to be
placed on the pads to perform this function. It should be noted that with the USB Host
port on the Rev C4 Beagle, the need to convert the OTG port to a host mode is greatly
diminished.
8.9.6
OTG USB Protection
Each lead on the USB port has ESD protection. In order for the interface to meet the USB
2.0 Specification Eye Diagram, these protection devices must be low capacitance.
8.10
USB Host Port
The Rev C4 is equipped with a High Speed USB Host interface connected to the ULPI
port 2 on the OMAP3530. It uses a SMSC PHY as the physical interface and provides
power control to the USB connector. This port is a High Speed only port and will not
support low speed or full speed devices plugged directly into the connector. Figure 35 is
the design of the USB Host port.
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Revision C4
VBAT
DC_5V
R49
TP20
U6
2
3
4
1
10K
VDD1.8
R69
0,0603
6 nEN_USB_PWR
IN OUT
IN OUT
EN OUT
GND OC
PAD
8
7
6
5
9
TESTPT1
HOST_nOC
6
TPS2061 (DGN)
USB HOST INTERFACE
U7
A3
A4
B5
A5
B4
C5
C4
D5
D4
E5
E4
D3
4 USB2HS_STP
4 USB2HS_DIR
4 USB2HS_NXT
4
4
4
4
4
4
4
4
USB2HS_DAT0
USB2HS_DAT1
USB2HS_DAT2
USB2HS_DAT3
USB2HS_DAT4
USB2HS_DAT5
USB2HS_DAT6
USB2HS_DAT7
B2
A2
4 USB2HS_nRST
4 USB2HS_CLK
STP
DIR
NXT
CLKOUT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
RESETB
REFCLK
VBUS
DM
DP
ID
RBIAS
VDD3.3
VDD1.8
VBAT
GND
C2
D1
E1
B1
A1
USB33_VBUS
USB33_ID
USB33_RBIAS
R50
Power Control
10K,0603
R51
R52
P7
USB-A Conn. - 87520-xx1xx
0
8.064k
D2
B3
+ C101
100uf , 6.3V
16V
USB33_VDD3.3
C103
VDD1.8
C105
C104
C1
C3
0.1uF
10V
22uF,CER,0805
0.1uF
10V
C102
10V
4.7uf ,CER,0402
R111
1 VBUS
2 D3 D+
4 GND
SHIELD
SHIELD
5
6
Host Connector
R67
USB3322 (CSP)
HOST_VBUS
HOST_DHOST_D+
1
2
30MHZ_50mA
VDD_EHCI
R68
VIO_1V8
10K
VBAT
0,0603,DNI
C107
0.1uF
10V
C106
10V
4.7uf ,CER,0402
Figure 35. USB Host Design
8.10.1 Host USB OMAP3 Interface
The interface to the OMAP3 is the HSUSB2 interface. The signals used on this interface
are contained in Table 10.
Table 10.
Signal
Hsusb2_clk
Hsusb2_stp
Hsusb2_dir
Hsusb2_nxt
Hsusb2_data0
Hsusb2_data1
Hsusb2_data2
Hsusb2_data3
Hsusb2_data4
Hsusb2_data5
Hsusb2_data6
Hsusb2_data7
Gpio_147
USB Host Port OMAP Signals
Description
External transceiver 60-MHz clock output to PHY
External transceiver Stop signal
Transceiver data direction control from PHY
Next signal from PHY
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Bidirectional data bus signal for 12-pin ULPI operation
Enable/reset line to the USB PHY.
Input/Output
O
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
The husb2_clk signal is an output only and is used to support a HS USB PHY that
supports an input clock mode. The SMSC PHY device supports this mode and is used on
the Beagle.
8.10.2 Host USB PHY
The PHY used in the design is a USB3322/26 series device from SMSC. The USB3322 is
a highly integrated Hi-Speed USB2.0 Transceiver (PHY) that meets all of the electrical
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requirements to be used as a Hi-Speed USB Host, Device, or an On-the-Go (OTG)
transceiver. In this design, only the host mode of operation is being supported. The
USB3322 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the
USB PHY to the OMAP3. ULPI uses a method of in-band signaling and status byte
transfers between the Link and PHY to facilitate a USB session with only 12 pins.
In order to interface to the OMAP3530, the device must be used in the 60MHz clock
mode. This is done by tying the CLKOUT signal on the USB PHY to VIO_1V8. On Rev
C4, a zero ohm series resistor was added. This is not required, but was added as a “just in
case” option if the CLKOUT signal was a source of noise in the PHY. It was proven not
to be the case. The clock for the PHY is derived from the 60MHz signal generated by the
OMAP3530. All of the signals and their functions align with the descriptions found in
the OMAP3530 interface section.
The USB3322 device requires two voltages, the VIO_1V8 rail to power the I/O rails and
the VBAT, which needs to be between 3.1V and 5.1V, to power the rest of the device. On
the board the VBAT is a regulated 4.2V DC. The 3.3V rail for the device is generated
internally and requires a filter and bypass cap to be connected externally. Unlike the Rev
C3 version, the Rev C4 version derives its 1.8V from the VAUX2 rail supplied by the
TPS65950 PMIC. It also uses a ferrite bead, R67, to provide additional filtering for noise.
This is the fix for the EHCI noise issue. There is an option to connect the 1.8V rail to the
VIO_1V8 rail, but that has not been populated in the Rev C4 design.
The RBIAS block in the PHY consists of an internal bandgap reference circuit used for
generating the driver current and the biasing of the analog circuits. This block requires an
external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to ground. The
nominal voltage at RBIAS is 0.8V and therefore the resistor will dissipate approximately
80µW of power.
The USB3322 can detect ID grounded and ID floating to determine if an A or B cable
has been inserted. The A plug will ground the ID pin while the B plug will float the ID
pin. As we are not using this device to support the OTG protocol but instead as a host
device, we ground the ID pin to force it into a Host mode at all times. The ID signal is
not present on the USB connector.
The USB3322 transceiver fully integrates all of the USB termination resistors on both DP
and DM. This includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω
high speed termination resistors. These resistors require no tuning or trimming.
8.10.3 Host USB Connector
The USB connector used is a Type A receptacle and provides connections for four
signals, DP, DM, VBUS, and Ground. This is the same connector you will see on the
back of a USB hub. You will notice that there are no external ESD devices on the
connector. The ESD protection is integrated into the USB PHY.
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8.10.4 Host USB Power Control
Power is provided through the USB Host connector to power devices that are plugged
into the USB host connector. This power can be controlled by the OMAP3530 via the
TPS2061 power switch.
The TPS2061 power-distribution switch is intended for applications where heavy
capacitive loads and short-circuits are likely to be encountered. This device incorporates
a 70-mW N-channel MOSFET power switch. Gate drive is provided by an internal
charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The switch is controlled by the TPS65950 using the
LED.A signal. The OMAP3530 uses the I2C interface to activate the signal in the
TPS65950.
The amount of available current to be supplied depends on the remaining current
available when in USB mode or the DC supply. The switch will not be able to supply
more current than is available from the DC source being used.
The TPS2061 also provides an overcurrent indicator and protection circuit. When the
output load exceeds the current-limit threshold or a short is present, the device limits the
output current to a safe level by switching into a constant-current mode, pulling the
overcurrent (OC) logic output low. This is read by the TPS65950 via the CD2 pin. The
CD2 pin can be set to generate an interrupt to the OMAP3530 to alert it of this condition.
When continuous heavy overloads and short-circuits increase the power dissipation in the
switch, causing the junction temperature to rise, a thermal protection circuit shuts off the
switch to prevent damage. Recovery from a thermal shutdown is automatic once the
device has cooled sufficiently. Internal circuitry ensures that the switch remains off until
valid input voltage is present. This power-distribution switch is designed to set current
limit at 1.5 A typically. As mentioned, the amount of current available depends on the
current source.
8.11
SD/MMC
The board provides an SD/MMC interface. Its primary use is for proving the boot source
for SW but it can be used for other things such as cameras and Wireless LAN cards.
Typical users prefer to use the USB port for these functions and as such, the SD card
function is the primary us of this connector.
The connector supports 7 different types of cards.
o SD- Secure Digital (SD) is a flash memory card format developed by Matsushita,
SanDisk and Toshiba for use in portable devices. As of 2007, SD card capacities
range from 8 MB to 16 GB. Several companies have announced SD cards with 32
GB. Cards with 4-32 GB are considered high-capacity. The format has proven to
be very popular. However, compatibility issues between older devices and the
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newer 4 GB and larger cards and the SDHC format have caused considerable
confusion for some users. SD card have a write protect tab to prevent the data
from being overwritten. SD supports 1-bit SD, 4-bit SD, and SPI modes.
o miniSD- Has the same features as the SD with the exceptions that it is in a
smaller size and the support for 4-bit mode is optional amongst suppliers.
o SDIO - SDIO stands for Secure Digital Input Output. SD slots can actually be
used for more than flash memory cards. Devices that support SDIO can use small
devices designed for the SD form factor, like GPS receivers, Wi-Fi or Bluetooth
adapters, modems, Ethernet adapters, barcode readers, IrDA adapters, FM radio
tuners, TV tuners, RFID readers, digital cameras, or other mass storage media
such as hard drives. SDIO cards are fully compatible with SD Memory Card host
controller (including mechanical, electrical, power, signaling and software). When
an SDIO card is inserted into a non SDIO-aware host, it will cause no physical
damage or disruption to device or host controller. It should be noted that SPI bus
topology is mandatory for SDIO, unlike SD Memory and most of the SD Memory
commands are not supported in SDIO. Figure 36 is an example of a SDIO
camera card.
Figure 36. Example of an SDIO Card
o MMC- The Multi Media Card (MMC) is a flash memory card standard. Unveiled
in 1997 by Siemens AG and SanDisk, it is based on Toshiba's NAND-based flash
memory, and is therefore much smaller than earlier systems based on Intel NORbased memory such as CompactFlash. MMC is about the size of a postage stamp:
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24 mm x 32 mm x 1.4 mm. MMC originally used a 1-bit serial interface, but
newer versions of the specification allow transfers of 4 at a time. MMCs are
currently available in sizes up to and including 4 GB an 8 GB models.
o MMCplus- The version 4.x of the MMC standard, introduced in 2005, brought in
two very significant changes to compete against SD cards. These were support for
running at higher speeds (26MHz, 52MHz) than the original MMC (20MHz) or
SD (25MHz, 50MHz). Version 4.x cards are fully backward compatible with
existing readers but require updated hardware/software to use their new
capabilities; even though the 4 bit wide bus and high-speed modes of operation
are deliberately electrically compatible with SD, the initialization protocol is
different, so firmware/software updates are required to allow these features to be
enabled when the card is used in an SD reader.
o MMCmobile – Is basically the same as MMCplus except that it supports 8 bit
data mode.
o RS-MMC –This alternate form factor is known as Reduced-Size
MultiMediaCard, or RS-MMC, and was introduced in 2004. This form factor is a
smaller form factor, of about half the size: 24 mm × 18 mm × 1.4 mm. RS-MMCs
are simply smaller MMCs. RS-MMCs are currently available in sizes up to and
including 4 GB. Nokia used to use RS-MMC in the Nokia 770 Internet Tablet.
Figure 37 is a side by side comparison of the RS-MMC and MMC card.
Figure 37. RS-MMC and Card
Figure 38 is the SD/MMC interface design on the BeagleBoard.
8.11.1 MMC Power
The SD/MMC connector is supplied power from the TPS65950 using the VMMC1 rail.
The default setting on this rail is 3.0V as set by the Boot ROM and under SW control, can
be set to 1.80V for use with 1.8V cards. The maximum current this rail can provide is
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220mA as determined by the TPS65950 regulator. Maximum current can be limited by
the overall current available from the USB interface of the PC.
8.11.2 OMAP3530 Interface
There are no external buffers required for the SD/MC operation. The OMAP3530
provides all of the required interfaces for the SD/MMC interface.
The main features of the MMC/SD/SDIO host controller are:
o Full compliance with MMC command/response sets as defined in the Multimedia
Card System Specification, v4.0
o Full compliance with SD command/response sets as defined in the SD Memory
Card Specifications, v1.10d
o Full compliance with SDIO command/response sets and interrupt/read-wait mode
as defined in the SDIO Card Specification, Part E1, v1.10
o Compliance with sets as defined in the SD Card Specification, Part A2, SD Host
Controller Standard Specification, v1.00
o Full compliance with MMC bus testing procedure as defined in the Multimedia
Card System Specification, v4.0
o Full compliance with CE-ATA command/response sets as defined in the CE-ATA
Standard Specification
o Full compliance with ATA for MMCA specification
o Flexible architecture allowing support for new command structure
o Support:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards
o Built-in 1024-byte buffer for read or write
o 32-bit-wide access bus to maximize bus throughput
o Single interrupt line for multiple interrupt source events
o Two slave DMA channels (1 for TX, 1 for RX)
o Programmable clock generation
o Support SDIO Read Wait and Suspend/Resume functions
o Support Stop at block gap
o Support command completion signal (CCS) and command completion signal
disable (CCSD) management as specified in the CE-ATA Standard Specification
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Revision C4
U3B
TWL4030
VMMC1
10K
U2A
OMAP35xx
MMC1_DAT3
MMC1_CMD
MMC1_CLK
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT4
MMC1_DAT5
MMC1_DAT6
MMC1_DAT7
GPIO_23
C2
+
C3
10UF
0.1uF
10V
R12
P12
VIO_1V8
R11
CD1
0.1uF
10V
R5
R36
R15
R16
R17
R18
C93
10K
10K
10K
10K
10K
10K
C2
10K
VMMC1.OUT
P28
M27
N28
R10
33
N27
N26
N25
P27
P26
R27
R25
AG9
OMAP35xx_ES2.0
P2
MHC-W21-601
1
2
3
4
5
6
7
8
9
10
11
12
13
16
17
18
19
20
21
22
23
24
25
26
27
28
14
15
#1_MMC+/MMCM/RSMMC/MMC/SD
#2_MMC+/MMCM/RSMMC/MMC/SD
#3_MMC+/MMCM/RSMMC/MMC/SD
#4_MMC+/MMCM/RSMMC/MMC/SD
#5_MMC+/MMCM/RSMMC/MMC/SD
#6_MMC+/MMCM/RSMMC/MMC/SD
#7_MMC+/MMCM/RSMMC/MMC/SD
#8_MMC+/MMCM/SD
#9_MMC+/MMCM/SD
#10_MMC+/MMCM
#11_MMC+/MMCM
#12_MMC+/MMCM
#13_MMC+/MMCM
#1_miniSD
#2_miniSD
#3_miniSD
#4_miniSD
#5_miniSD
#6_miniSD
#7_miniSD
#8_miniSD
#9_miniSD
#10_miniSD
#11_miniSD
GND1
GND2
SD_WP
CD
SD/MMC Connector 6 in 1
MMC+, MMCMobile, SD,
MMC, miniSD, RS-MMC
Figure 38. SD/MMC Interface
The known limitations are as follows:
o No built-in hardware support for error correction codes (ECC). See the
Multimedia Card System Specification, v4.0, and the SD Memory Card
Specifications, v1.10d, for details about ECC.
o The maximum block size defined in the SD Memory Card Specifications, v1.10d
that the host driver can read and write to the buffer in the host controller is 2048
bytes. MMC supports a maximum block size of 1024 bytes. Up to 512 byte
transfers, the buffer in MMC is considered as a double buffering with ping-pong
management; half of the buffer can be written while the other part is read. For 512
to 1024 byte transfers, the entire buffer is dedicated to the transfer (read only or
write only).
Table 11 provides a description of the signals on the MMC card.
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Table 11.
Signal Name
Revision C4
SD/MMC OMAP Signals
Description
MMC1_CLK
MMC1_CMD
MMC1_DAT(0..7)
SD/MMC Clock output.
SD/MMC Command pin
SD/MMC Data pins
MMC_WP
Write Protect detect
I/O
Pin
O
I/O
I/O
N28
M27
N27,N26,N25,P28,P27,
P26,R27,R25
AG9
I
8.11.3 Card Detect
When a card is inserted into the SD/MMC connector, the Card Detect pin is grounded.
This is detected on pin P12 of the TPS65950. An interrupt, if enabled, is sent to the
OMAP3530 via the interrupt pin. The SW can be written such that the system comes out
of sleep or a reduced frequency mode when the card is detected.
8.11.4 Write Protect
If an SD card is inserted into the SD/MMC connector and the write protect pin is active,
the Write Detect pin is grounded. This is detected GPIO_29 of the OMAP3530. The SW
can then determine if the card is write protected and act accordingly.
8.11.5 8 Bit Mode
The BeagleBoard also supports the new 8-bit cards. The upper 4 bits are supplied by the
VDD_SIM power rail and as such the 8-bit mode is only supported in 1.8V modes. This
requires that both the VMMC1 and VDD_SIM rails must be set to 1.8V when using 8 bit
cards.
8.11.6 Booting From SD/MMC Cards
The ROM code supports booting from MMC and SD cards with some limitations:
o Support for MMC/SD cards compliant with the Multimedia Card System
Specification v4.2 from the MMCA Technical Committee and the Secure Digital
I/O Card Specification v2.0 from the SD Association. Including high-capacity
(size >2GB) cards: HC-SD and HC MMC.
o 3-V power supply, 3-V I/O voltage on port 1
o Initial 1-bit MMC mode, 4-bit SD mode.
o Clock frequency:
– Identification mode: 400 kHz
– Data transfer mode: 20 MHz
o Only one card connected to the bus
o FAT12/16/32 support, with or without master boot sector (MBR).
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The high-speed MMC/SD/SDIO host controllers handle the physical layer while the
ROM code handles the simplified logical protocol layer (read-only protocol). A limited
range of commands is implemented in the ROM code. The MMC/SD specification
defines two operating voltages for standard or high-speed cards. The ROM code only
supports standard operating voltage range (3-V) (both modes supported). The ROM code
reads out a booting file from the card file system and boots from it.
8.12
Audio Interface
The BeagleBoard supports stereo in and out through the TPS65950 which provides the
audio CODEC.
Figure 39 is the Audio circuitry design on the BeagleBoard.
U5A
HSOL
HSOR
OMAP3530
B4
B5
U3B
OMAP3
P21
McBSP2_FSX N21
McBSP2_CLKX R21
McBSP2_DR M21
McBSP2_DX
T21
McBSP_CLKS
PHONOJACK STEREO-R
TPS65950
C53
INTER_HSOL R44
47uF,CER
33 CONN_HSOL
1
3
HSOR
C54
INTER_HSOR R46
47uF,CER
33 CONN_HSOR
2
HSOL
47pF 47pFD8
L3
K6
K4
K3
D13
C56
I2S.CLK
I2S.SYNC
I2S.DIN
I2S.DOUT
AUDIO_OUT
P5
D9
C57
DIO_V5.5MLA0603
DIO_V5.5MLA0603
CLK256FS
AUXL
AUXR
F1
G1
AUXL
AUXR
C64
0.1uF,CER
10V
C65
0.1uF,CER
10V
1
3
CONN_AUXL
CONN_AUXR
C66
C67
47pF
47pF
D10
AUDIO_IN
P6
2
D11
PHONOJACK STEREO-R
DIO_V5.5MLA0603 DIO_V5.5MLA0603
Figure 39. Audio Circuitry
8.12.1 OMAP3530 Audio Interface
There are five McBSP modules called McBSP1 through McBSP5 on the OMAP3530.
McBSP2 provides a full-duplex, direct serial interface between CODEC inside the
TPS65950. It supports the I2S format to the TPS65950. In Table 12 are the signals used
on the OMAP3530 to interface to the CODEC.
Table 12.
Signal Name
mcbsp2_dr
mcbsp2_dx
mcbsp2_clkx
mcbsp2_fsx
Mcbsp_clks
OMAP3530 Audio Signals
Description
Received serial data
Transmitted serial data
Combined serial clock
Combined frame synchronization
External clock input. Used to synchronize with
the TPS65950
I/O
Pin
I
I/O
I/O
I/O
I
R21
M21
N21
P21
T21
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8.12.2 TPS65950 Audio Interface
The TPS65950 acts as a master or a slave for the I2S interface. If the TPS65950 is the
master, it must provide the frame synchronization (I2S_SYNC) and bit clock (I2S_CLK)
to the OMAP3530. If it is the slave, the TPS65950 receives frame synchronization and
bit clock. The TPS65950 supports the I2S left-justified and right-justified data formats,
but doesn’t support the TDM slave mode.
In Table 13 are all the signals used to interface to the OMAP3530.
Table 13.
Signal Name
I2S.CLK
I2S.SYNC
I2S.DIN
I2S. DOUT
CLK256FS
OMAP3530 Audio Signals
Description
Clock signal (audio port)
Synchronization signal (audio port)
Data receive (audio port)
Data transmit (audio port)
Synchronization frame sync to the OMAP3530
I/O
Pin
I/O
IO
I
O
O
L3
K6
K4
K3
D13
8.12.3 Audio Output Jack
A single 3.5mm jack is provided on BeagleBoard to support external stereo audio output
devices such as headphones and powered speakers.
8.12.4 Audio Input Jack
A single 3.5mm jack is supplied to support external audio inputs including stereo or
mono.
8.13
DVI-D Interface
The LCD interface on the OMAP3530 is accessible from the DVI-D interface connector
on the board. Figure 40 is the DVI-D interface design.
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3.3V
L4
FERRITE, MMZ1608R301A
C119
DVI_PVDD
L5
FERRITE, MMZ1608R301A
10V
TVDD
VIO_1V8
R64
I2C3_SCL
I2C3_SDA
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R83
R84
R85
R86
R87
R88
R89
R90
R91
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
DVI_DATA0
DVI_DATA1
DVI_DATA2
DVI_DATA3
DVI_DATA4
DVI_DATA5
DVI_DATA6
DVI_DATA7
DVI_DATA8
DVI_DATA9
DVI_DATA10
DVI_DATA11
DVI_DATA12
DVI_DATA13
DVI_DATA14
DVI_DATA15
DVI_DATA16
DVI_DATA17
DVI_DATA18
DVI_DATA19
DVI_DATA20
DVI_DATA21
DVI_DATA22
DVI_DATA23
DVI_CLK+
E27
D27
D26
R92
R93
R94
10
10
10
DVI_DEN
DVI_VSYNC
DVI_HSYNC
3.3V
AF14
AG14
R98
R99
R101
R102
R103
R104
R105
R109
3
10K
1K
63
62
61
60
59
58
55
54
53
52
51
50
47
46
45
44
43
42
41
40
39
38
37
36
57
56
2
5
4
3
ISEL
10
13
BSEL 15
DVI_DSEL14
10K
10K
1K,0603
1K,0603
1K,0603
DC_5V
0.1uF
RT1
DK3
DK2
DK1
6
7
8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
IDCK+
IDCKDE
VSYNC
HSYNC
VREF
RXEF010
100Ma
1
33
12
29
23
18
TXD1TXD1+
27
28
EDGE
TXD0TXD0+
TXC+
TXC-
R82
10K TXD0TXD0+
3.3V
DVI_+5v18
17
19
9
7
8
11
10
12
TXC+
TXC-
22
21
6
4
5
VIO_1V8
DAT2DAT2+
DAT2_S
SCL
SDA
DAT1DAT1+
DAT1_S
+5V
DDC/CEC GND
HPLG
DAT0DAT0+
DAT0_S
CLK_S
CLK+
CLK-
CEC
NC
13
14
HDMI_Conn
R95 R96 R97
TFADJ
DKEN
RSVD2
NC
MSEN
19
35
34
49
TFADJ
510
1K
DKEN
4.7K
R100
410_NC
4.7K
MSEN
11
C125
C126
0.1uF 10V
3
1
2
TXD1TXD1+
9
24
25
VIO_1V8
10K
TXD2TXD2+
30
31
3.3V
BSEL
DSEL
U4B
SN74LVC2G07DCKR
4
TXD2TXD2+
15
16
PD
ISEL
DK3
DK2
DK1
P10
DVDD
DVDD
DVDD
TVDD
TVDD
PVDD
AG22
AH22
AG23
AH23
AG24
AH24
E26
F28
F27
G26
AD28
AD27
AB28
AB27
AA28
AA27
G25
H27
H26
H25
E28
J26
AC27
AC28
D28
J25
0.1uF
PGND
TP
GPIO_170
0.1uF
17
65
DSS_ACBIAS
DSS_VSY NC
DSS_HSY NC
0.1uF
t
TGND
TGND
TGND
DGND
DGND
DGND
U3A
DSS_D0
DSS_D1
DSS_D2
DSS_D3
DSS_D4
DSS_D5
DSS_D6
DSS_D7
DSS_D8
DSS_D9
DSS_D10
DSS_D11
DSS_D12
DSS_D13
DSS_D14
DSS_D15
DSS_D16
DSS_D17
DSS_D18
DSS_D19
DSS_D20
DSS_D21
DSS_D22
DSS_D23
DSS_PCLK
U8
TFP410
26
32
20
16
48
64
OMAP3
OMAP3
10K,0603
0.1uF
10K,0603
DVI_VREF
R65
0.1uF
C120
10V
C121
10V
C122
10V
C123
10V
C124
10V
DVI_DVDD
L6
FERRITE, MMZ1608R301A
Adjusted for .9V
Revision C4
10V
C1
D2
D1
C2
U11
VCCA VCCB
A1
B1
A2
B2
OE
GND
B2
A2
A1
B1
0.1uF
DDC_I2C3_SCL
DDC_I2C3_SDA
TXS0102 (YZP)
Figure 40. DVI-D Interface
8.13.1 OMAP3530 LCD Interface
The main driver for the DVI-D interface originates at the OMAP3530 via the DSS pins.
The OMAP3530 provides 24 bits of data to the DVI-D framer chip, TFP410. There are
three other signals used to control the DVI-D that originate at the OMAP3530. These are
I2C3_SCL, I2C3_SDA, and GPIO_170. All of the signals used are described in Table
14.
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Table 14.
Signal Name
dss_pclk
dss_hsync
dss_vsync
dss_acbias
dss_data0
dss_data1
dss_data2
dss_data3
dss_data4
dss_data5
dss_data6
dss_data7
dss_data8
dss_data9
dss_data10
dss_data11
dss_data12
dss_data13
dss_data14
dss_data15
dss_data16
dss_data17
dss_data18
dss_data19
dss_data20
dss_data21
dss_data22
dss_data23
GPIO_170
I2C3_SCL
I2C3_SDA
Revision C4
OMAP3530 LCD Signals
Description
Type
Ball
LCD Pixel Clock
LCD Horizontal Synchronization
LCD Vertical Synchronization
Pixel data enable (TFT) output
LCD Pixel Data bit 0
LCD Pixel Data bit 1
LCD Pixel Data bit 2
LCD Pixel Data bit 3
LCD Pixel Data bit 4
LCD Pixel Data bit 5
LCD Pixel Data bit 6
LCD Pixel Data bit 7
LCD Pixel Data bit 8
LCD Pixel Data bit 9
LCD Pixel Data bit 10
LCD Pixel Data bit 11
LCD Pixel Data bit 12
LCD Pixel Data bit 13
LCD Pixel Data bit 14
LCD Pixel Data bit 15
LCD Pixel Data bit 16
LCD Pixel Data bit 17
LCD Pixel Data bit 18
LCD Pixel Data bit 19
LCD Pixel Data bit 20
LCD Pixel Data bit 21
LCD Pixel Data bit 22
LCD Pixel Data bit 23
Powers down the TFP410 when Lo. TFP410 is active
when Hi.
I2C3 clock line. Used to communicate with the monitor
to determine setting information.
I2C3 data line. Used to communicate with the monitor
to determine setting information.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D28
D26
D27
E27
AG22
AH22
AG23
AH23
AG24
AH24
E26
F28
F27
G26
AD28
AD27
AB28
AB2
AA28
AA27
G25
H27
H26
H25
E28
J26
AC27
AC28
J25
I/O
AF14
I/O
AG14
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
10ohm series resistors are provide in the signal path to minimize reflections in the high
frequency signals from the OMAP3530 to the TFP410. These resistors are in the form of
resistor packs on the BeagleBoard. The maximum clock frequency of these signals is
65MHz.
8.13.2 OMAP3530 LCD Power
In order for the DSS outputs to operate correctly out of the OMAP3530, two voltage rails
must be active, VIO_1V8 and VDD_PLL2. Both of these rails are controlled by the
TPS65950 and must be set to 1.8V. By default, VDD_PLL2 is not turned and must be
activated by SW. Otherwise some of the bits will not have power supplied to them.
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Revision C4
8.13.3 TFP410 Framer
The TFP410 provides a universal interface to allow a glue-less connection to provide the
DVI-D digital interface to drive external LCD panels. The adjustable 1.1-V to 1.8-V
digital interface provides a low-EMI, high-speed bus that connects seamlessly with the
1.8V and 24-bit interface output by the OMAP3530. The DVI interface on the
BeagleBoard supports flat panel display resolutions up to XGA at 65 MHz in 24-bit true
color pixel format.
Table 15 is a description of all of the interface and control pins on the TFP410 and how
they are used on BeagleBoard.
Table 15.
Signal Name
TFP410 Interface Signals
Type
Ball
DATA[23:12]
DATA[11:0]
The upper 12 bits of the 24-bit pixel bus.
The bottom 12 bits of the 24-bit pixel bus.
I
I
IDCK+
IDCK-
Single ended clock input.
Tied to ground to support the single ended mode.
Data enable. During active video (DE = high), the transmitter
encodes pixel data, DATA[23:0]. During the blanking interval
(DE = low), the transmitter encodes HSYNC and VSYNC.
Horizontal sync input
Vertical sync input
These three inputs are the de-skew inputs DK[3:1], used to
adjust the setup and hold times of the pixel data inputs
DATA[23:0], relative to the clock input IDCK±.
A low level indicates a powered on receiver is detected at the
differential outputs. A high level indicates a powered on
receiver is not detected.
This pin disables the I2C mode on chip. Configuration is
specified by the configuration pins (BSEL, DSEL, EDGE,
VREF) and state pins (PD, DKEN).
Selects the 24bit and single-edge clock mode.
Lo to select the single ended clock mode.
A high level selects the primary latch to occur on the rising edge
of the input clock IDCK
A HI level enables the de-skew controlled by DK[1:3]
Sets the level of the input signals from the OMAP3530.
A HI selects normal operation and a LO selects the powerdown
mode.
This pin controls the amplitude of the DVI output voltage
swing, determined by the value of the pullup resistor RTFADJ
connected to 3.3V.
I
I
36–47
50–55.5653
57
56
I
2
I
I
I
I
I
4
5
6
7
8
O
11
I
13
I
I
I
13
14
9
I
I
I
35
3
10
I
19
DE
HSYNC
VSYNC
DK3
DK2
DK1
MSEN
ISEL
BSEL
DSEL
EDGE
DKEN
VREF
PD
TGADJ
Description
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Revision C4
8.13.4 TFP410 Power
Power to the TFP410 is supplied from the 3.3V regulator in U1, the TPS2141. In order to
insure a noise free signal, there are three inductors, L4, L5, and L6 that are used to filter
the 3.3V rail into the TFP410.
8.13.5 TFP410 Control Pins
There are twelve control pins that set up the TFP410 to operate with the OMAP3530.
Most of these pins are set by HW and do not require any intervention by the OMAP3530
to set them.
8.13.5.1
ISEL
The ISEL pin is pulled LO via R99 to place the TFP410 in the control pin mode with the
I2C feature disabled. This allows the other modes for the TFP410 to be set by the other
control pins.
8.13.5.2
BSEL
The BSEL pin is pulled HI to select the 24 bit mode for the Pixel Data interface from the
OMAP3530.
8.13.5.3
DSEL
The DSEL pin is pulled low to select the single ended clock mode from the OMAP3530.
8.13.5.4
EDGE
The EDGE signal is pulled HI through R82 to select the rising edge on the IDCK+ lead
which is the pixel clock from the OMAP3530.
8.13.5.5
DKEN
The DKEN signal is pulled HI to enable the de-skew pins. The de-skew pins, DK1-DK3,
are pulled low by the internal pulldown resistors in the TFP410. This is the default mode
of operation. If desired, the resistors can be installed to pull the signals high. However, it
is not expected that any of the resistors will need to be installed. The DK1-DK3 pins
adjust the timing of the clock as it relates to the data signals.
8.13.5.6
MSEN
The MSEN signal, when low, indicates that there is a powered monitor plugged into the
DVI-D connector. This signal is not connected to the OMAP3530 and is provided as a
test point only.
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8.13.5.7
Revision C4
VREF
The VREF signal sets the voltage level of the DATA, VSYNC, HSYNC, DE, and
IDCK+ leads from the OMAP3530. As the OMAP3530 is 1.8V, the level is set to .9V
by R64 and R65.
8.13.5.8
PD
The PD signal originates from the OMAP3530 on the GPIO_170 pin. Because the PD
signal on the TFP410 is 3.3V referenced, this signal must be converted to 3.3V. This is
done by U4, SN74LVC2G07, a non-inverting open drain buffer. If the GPIO_170 pin is
HI, then the open drain signal is inactive, causing the signal to be pulled HI by R98.
When GPIO_170 is taken low, the output of U4 will also go LO, placing the TFP410 in
the power down mode. Even though U4 is running at 1.8V to match the OMAP3530, the
output will support being pulled up to 3.3V. On power up, the TFP410 is disabled by
R109, a 10K resistor. When the OMAP3530 powers on, pin J25 comes in the safe mode,
meaning it is not being driven. R109 insures that the signal is pulled LO, putting the
TFP410 in the power down mode.
8.13.5.9
TFADJ
The TFADJ signal controls the amplitude of the DVI output voltage swing, determined
by the value of R95.
8.13.5.10
RSVD2
This unused pin is terminated to ground as directed by the TFP410 data manual.
8.13.5.11
NC
This unused pin is pulled HI as directed by the TFP410 data manual.
8.13.6 DVI-D Connector
In order to minimize board size, a HDMI connector was selected for the DVI-D
connection. The BeagleBoard does not support HDMI but only the DVI-D component of
HDMI. The Cable is not supplied with the BeagleBoard but is available from numerous
cable suppliers and is required to connect a display to the BeagleBoard.
8.13.6.1
Shield Wire
Each signal has a shield wire that is used in the cable to provide signal protection for each
differential pair. This signal is tied directly to ground.
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8.13.6.2
Revision C4
DAT0+/DAT0-
The differential signal pair DAT0+/DAT0- transmits the 8-bit blue pixel data during
active video and HSYNC and VSYNC during the blanking interval.
8.13.6.3
DAT1+/DAT1-
The differential signal pair DAT1+/DAT1- transmits the 8-bit green pixel data during
active video.
8.13.6.4
DAT2+/DAT2-
The differential signal pair DAT2+/DAT2- transmits the 8-bit red pixel data during
active.
8.13.6.5
TXC+/TXC-
The differential signal pair TXC+/TXC- transmits the differential clock from the
TFP410.
8.13.6.6
DDC Channel
The Display Data Channel or DDC (sometimes referred to as EDID Enhanced Display
ID) is a digital connection between a computer display and the OMAP3530 that allows
the display specifications to be read by the OMAP3530. The standard was created by the
Video Electronics Standards Association (VESA). The current version of DDC, called
DDC2B, is based on the I²C bus. The monitor contains a read-only memory (ROM) chip
programmed by the manufacturer with information about the graphics modes that the
monitor can display. This interface in the LCD panel is powered by the +5V pin on the
connector through RT1, a resetable fuse. As the OMAP3530 is 1.8V I/O, the I2C bus is
level translated by U11, a TXS0102. It provides for a split rail to allow the signals to
interface on both sides of the circuit. Inside of TXS0102 is a pullup on each signal,
removing the need for an external resistor.
8.13.6.7
HDMI Support
The digital portion of the DVI-D interface is compatible with HDMI and is electrically
the same. A standard HDMI cable may be used to connect to the HDMI input of monitors
or televisions. Whether or not the Beagle will support those monitors is dependent on the
timings that are used on the BeagleBoard and those that are accepted by the monitor. This
may require a change in the software running on the Beagle. The audio and encryption
features of HDMI are not supported by the BeagleBoard.
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8.13.6.8
Revision C4
DVI to VGA
The analog portion of DVI which provides RGB analog signals is not supported by the
BeagleBoard. Buying a DVI to VGA adapter connector will not work on a VGA display.
You will need an active DVI-D to VGA adapter. Another option for these signals is to
find a board that connects to the J4 and J5 expansion connectors and generates the RGB
signals for the VGA display.
8.14
LCD Expansion Headers
Access is provided on the Rev C4 to allow access to the LCD signals. Table 16 shows
the signals that are on the J4 connector. You will notice that the signals are not in a
logical order or grouping. This is due to the routing on the PCB where we allowed the
routing to take president to get it to route with no addition of layers to the design.
Table 16.
J4 LCD Signals
Pin#
Signal
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC_5V
DC_5V
DVI_DATA1
DVI_DATA0
DVI_DATA3
DVI_DATA2
DVI_DATA5
DVI_DATA4
DVI_DATA12
DVI_DATA10
DVI_DATA23
DVI_DATA14
DVI_DATA19
DVI_DATA22
I2C3_SDA
DVI_DATA11
DVI_VSYNC
PWR
PWR
O
O
O
O
O
O
O
O
O
O
O
O
I/O
O
O
18
DVI_PUP
19
20
GND
GND
DC rail from the Main DC supply
DC rail from the Main DC supply
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
I2C3 Data Line
LCD Pixel Data bit
LCD Vertical Sync Signal
Control signal for the DVI controller. When Hi,
DVI is enabled. Can be used to activate
circuitry on adapter board if desired.
Ground bus
Ground bus
O
PWR
PWR
The current available on the DC_5V rail is limited to the available current that remains
from the DC supply that is connected to the DC power jack on the board. Keep in mind
that some of that power is needed by the USB Host power rail and if more power is
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Revision C4
needed for the expansion board, the main DC power supply current capability may need
to be increased. All signals are 1.8V except the DVI_PUP which is a 3.3V signal.
Table 17 shows the signals that are on connector J5.
Table 17.
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal
3.3V
VIO_1V8
DVI_DATA20
DVI_DATA21
DVI_DATA17
DVI_DATA18
DVI_DATA15
DVI_DATA16
DVI_DATA7
DVI_DATA13
DVI_DATA8
NC
DVI_DATA9
I2C3_SCL
DVI_DATA6
DVI_CLK+
DVI_DEN
DVI_HSYNC
GND
GND
J5 LCD Signals
I/O
Description
PWR
PWR
O
O
O
O
O
O
O
O
O
3.3V reference rail
1.8V buffer reference rail.
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
No connect
LCD Pixel Data bit
I2C3 Clock Line
LCD Pixel Data bit
DVI Clock
Data Enable
Horizontal Sync
Ground bus
Ground bus
I/O
O
O
O
O
PWR
PWR
The 1.8V rail is for level translation only and should not be used to power circuitry on the
board. The 3.3V rail also has limited capacity on the power as well. If the TFP410 is
disabled on the Beagle, then 80mA is freed up for use on an adapter card connected to the
LCD signals connectors. It is not required that the TFP410 be disabled when running an
adapter card, but the power should be taken into consideration when making this
decision.
It is suggested that the 5V rail be used to generate the required voltages for an adapter
card.
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8.15
Revision C4
S-Video
A single S-Video port is provided on the BeagleBoard. Figure 41 is the design of the SVideo interface.
C140
TV_VFB1
47pF
P11
P1
P2
P3
P4
MH1
MH2
MH3
TV_VFB2
47pF
1
2
3
4
R66
MH1
MH2
MH3
L7 TV_OUT1
3.3uH
C141
1.65K TV_VFB1
R67
L8
3.3uH
TV_OUT2
OMAP35xx_ES3.0
TV_OUT2
TV_OUT1
1.65K TV_VFB2
TV_VREF
W28
Y 28
Y 27
W27
W26
U12B
TV_OUT2
TV_OUT1
TV_VFB1
TV_VFB2
TV_VREF
SVideoConn
TV/S-Video Conn
C142
0.1uF
Figure 41. S-Video Interface
Table 18 is the list of the signals on the S-Video interface and their definitions.
Table 18.
Signal
tv_out1
tv_out2
tv_vref
tv_vfb1
tv_vfb2
I/O
O
O
I
O
O
S-Video Interface Signals
Description
TV analog output composite
TV analog output S-VIDEO
Reference output voltage from internal bandgap
Amplifier feedback node
Amplifier feedback node
Power to the internal DAC is supplied by the TPS65950 via the VDAC_1V8 rail. Figure
37 reflects the filtering that is used on these rails, including the input VBAT rail.
A 47pf CAP and 3.3uh inductor are across the feedback resistors to improve the quality
of the S-Video signal.
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8.16
Revision C4
RS232 Port
A single RS232 port is provided on the BeagleBoard and provides access to the TX and
RX lines of UART3 on the OMAP3530. Figure 42 shows the design of the RS232 port.
3.3V
C114
3
3
C110
TP21
TESTPT1
UART3_TX
UART3_RX
TP22
R54
10K
232OE
3
5
4
6
U9
VCCA VCCB
A1
B1
A2
B2
OE
GND
0.1uF
10V
7
8
1
2
UART3_TX_3V
UART3_RX_3V
TXS0102 (DCU)
TESTPT1
UART3 Serial Port
0.1uF232_C1- 4
10V
232_C2+5
C118
0.1uF232_C2- 6
10V
11
9
1
12
VCC
C1+
C1-
VV+
7232_V3
C116
0.1uF
10V
C2DIN
ROUT
DOUT
RIN
EN
INVALID
FORCEON
SN65C3221EPW
232_V+
C117
C2+
GND
0.1uF
10V
C111
232_C1+2
C115
FORCEOFF
13
8
10
RS232_TX1
0.1uF
10V
RS232_RX1
P9
10
8
6
4
2
9
7
5
3
1
HEADER 5X2
16
14
3.3V
VIO_1V8
15
0.1uF
10V
U10
Figure 42. RS232 Interface Design
8.16.1 OMAP3530 Interface
Two lines, UART3_Tx and UART3_Rx, are provided by the OMAP3530. The UART3
function contains a programmable baud generator and a set of fixed dividers that divide
the 48-MHz clock input down to the expected baud rate and also supports auto bauding.
8.16.2 OMAP3530 Level Translator
All of the I/O levels from the OMAP3530 are 1.8V while the transceiver used runs at
3.3V. This requires that the voltage levels be translated. This is accomplished by the
TXS0102 which is a two-bit noninverting translator that uses two separate configurable
power-supply rails. The A port tracks VCCA, 1.8V and the B port tracks VCCB, 3.3V.
This allows for low-voltage bidirectional translation between the two voltage nodes.
When the output-enable (OE) input is low, all outputs are placed in the high-impedance
state. In this design, the OE is tied high via a 10K ohm resistor to insure that it is always
on.
8.16.3 RS232 Transceiver
The RS232 transceiver used is the SN65C322 which consists of one line driver, one line
receiver, and a dual charge-pump circuit with ±15-kV IEC ESD protection pin to pin
(serial-port connection pins, including GND). These devices provide the electrical
interface between an asynchronous communication controller and the serial-port
connector. The charge pump and four small external capacitors allow operation from a
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BeagleBoard System
Reference Manual
Revision C4
single 3-V to 5.5-V supply. The SN65C3221 operates at data signaling rates up to 1
Mbit/s and a driver output slew rate of 24 V/ms to 150 V/ms. While the OMAP3530 can
easily drive a 1Mbit/S rate, your results may vary based on cabling, distance, and the
loads and drive capability on the other end of the RS232 port.
The transceiver is powered from the 3.3V rail and is active at power up. This allows the
port to be used for UART based peripheral booting over the port.
8.16.4 Connector
Access to the RS232 port is through a 10pin header, P9. Connection to the header is
through a 10 pin IDC to 9 pin D-sub cable. This header requires the use of an ATIEverex type cable. This is the only cable that will work. This cable is readily available
from a number of sources and is commonly found on many PC motherboards and is not
supplied with the BeagleBoard. Figure 43 is a picture of what the cable assembly looks
like.
Figure 43. RS232 Cable
When purchasing, make sure the ATI-Everex or pass through cable is ordered.
8.17
Indicators
There are four green indicators on the BeagleBoard:
o
o
o
o
Power
PMU_STAT
USER0
USER1
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Revision C4
Three of these are programmable under software control and the fourth one is tied to the
main power rail. Figure 44 shows the connection of all of these indicators.
U5A
TPS65950
LEDB
LEDGND
VBAT
G15
R48
T2_LED_B
VBAT
D12
VBAT
VBAT
PMU_STAT
820
D6
PMU_STAT GRN
F16
GRN
LTST-C150CKT
USER0
200.0603USR0_LED_R
USR0_LEDR34
D7
GRN
USER1
0.125W
GRN
POWER
D5
D5_RES
6
LED0_GPIO1502
U3B
OMAP3530_ES3.0
W8
GPIO_150 AA9
GPIO_149
Q1A
10k
R9
820,0603
RN1907
USR1_LED
R35
47k
OMAP3530
200.0603 USR1_LED_R
0.125W
0.125W
1
3
LED1_GPIO149
5
Q1B
10k
RN1907
47k
4
Figure 44. Indicator Design
8.17.1 Power Indicator
This indicator, D7, connects across the VBAT supply and ground. It indicates that the
entire power path is supplying the power to the board. The VBAT regulator can be driven
from either the USB Client port or an external 5VDC power supply. Indicator D7 does
not indicate which power source is being used to supply the main power to the board but
only that it is active.
8.17.2 PMU Status Indicator
This output is driven from the TPS65950 using the LED.B output. The TPS65950
provides LED driver circuitry to power two LED circuits that can provide user indicators.
The first circuit can provide up to 160 mA and the second, 50 mA. Each LED circuit is
independently controllable for basic power (on/off) control and illumination level (using
PWM). The second driver, LED.B, is used to drive an LED that is connected to the
VBAT rail through a resistor.
The PWM inside the TPS65950 can be used to alter the brightness of the LED if desired
or it can be turned on or off by the OMAP3530 using the I2C bus. The PWM is
programmable, register-controlled, duty cycle based on a nominal 4-Hz cycle which is
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Revision C4
derived from an internal 32-kHz clock. It is possible to set the LED to flash automatically
without software control if desired.
8.17.3 User Indicators
There are two user LEDs that can be driven directly from a GPIO pin on the
OMAP3530. These can be used for any purpose by the software. The output level of the
OMAP3530 is 1.8V and the current sink capability is not enough to drive an LED with
any level of brightness. A transistor pair, RN1907 is used to drive the LEDs from the
VBAT rail. A logic level of 1 will turn the LED on.
8.18
JTAG
A JTAG header is provided to allow for advanced debugging on the BeagleBoard by
using a JTAG based debugger Figure 45 shows the interconnection to the OMAP3530
processor.
VIO_1V8
VIO_1V8
R15
R16
R17
R18
R19
R20
R21
C4
2
4
8
10
12
14
P2
76385-407LF
1
2
1 3
4
3 5
5 7
8
7 9
10
9 11
12 11
13
14 13
0.1uF10V
10K
10K
100K
100K
100K
100K
100K
OMAP3530_ES3.0
U3B
JTAG_TMS
JTAG_TDI
AA18
AA20
JTAG_TDO
JTAG_RTCK
JTAG_TCK
AA19
AA12
AA13
JTAG_EMU0
AA11
JTAG_EMU1
AA17
AA10
JTAG_nTRST
JTAG_TMS
JTAG_TDI
OMAP3530
JTAG_TDO
JTAG_RTCK
JTAG_TCK
JTAG_EMU0/SDTI_CLK/SDTI_TXD0/GPIO_11
JTAG_nTRST
JTAG_EMU1/SDTI_TXD0/SDTI_TXD1/GPIO_31
R22
10K
Figure 45. JTAG Interface
8.18.1 OMAP3530 Interface
The JTAG interface connects directly to the OMAP processor. All signals are a 1.8V
level. Table 19 describes the signals on the JTAG connector.
Page 93 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Table 19.
Revision C4
JTAG Signals
Signal
Description
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_RTCK
JTAG_TCK
JTAG_nTRST
JTAG_EMU0
JTAG_EMU1
I/O
Test mode select
Test data input
Test Data Output
ARM Clock Emulation
Test Clock
Test reset
Test emulation 0
Test emulation 1
I/O
I
O
O
I
I
I/O
I/O
8.18.2 Connector
The JTAG interface uses a 14 pin connector. All JTAG emulator modules should be able
to support this interface. Contact your emulator supplier for further information or if an
adapter is needed.
8.19
Expansion Header
The expansion header is provided to allow a limited number of functions to be added to
the BeagleBoard via the addition of a daughtercard.
Figure 46 is the design of the expansion connector and the interfaces to the OMAP3530.
DC_5V
OMAP3_ES3.0
McBSP3_DX
McBSP3_CLKX
McBSP3_FSX
McBSP3_DR
McBSP1_DX
McBSP1_CLKX
McBSP1_FSX
McBSP1_DR
McBSP1_CLKR
McBSP1_FSR
I2C2_SCL
I2C2_SDA
OMAP3
To the Reset circuitry
J3
VIO_1V8
U3B
AB26
AA25
AE5
AE6
V21
W21
K26
U21
Y21
AA21
AF15
AE15
UART2_CTS
MCBSP3_CLKX
MCBSP3_FSX
MCBSP3_DR
MCBSP1_DX
MCBSP1_CLKX
MCBSP1_FSX
MCBSP1_DR
MCBSP1_CLKR
MCBSP1_FSR
I2C2_SCL
nRESET
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
U3A
MMC2_DAT7
MMC2_DAT6
MMC2_DAT5
MMC2_DAT4
MMC2_DAT3
MMC2_DAT2
MMC2_DAT1
MMC2_DAT0
MMC2_CMD
MMC2_CLKO
I2C2_SDA
nUSB_DC_EN
HEADER 14X2
AE3
AF3
AH3
AE4
AF4
AG4
AH4
AH5
AG5
AE2
OMAP3_ES3.0
MMC2_DAT7
MMC2_DAT6
MMC2_DAT5
MMC2_DAT4
MMC2_DAT3
MMC2_DAT2
MMC2_DAT1
MMC2_DAT0
MMC2_CMD
MMC2_CLK
OMAP3
To the power circuitry
Figure 46. Expansion Header
NOTE: The Expansion header itself is NOT provided on the BeagleBoard. This is user
installed option. This header is not populated on the BeagleBoard so that based on the
usage scenario the user chooses; it can be populated as needed (Top, Bottom, Top right
angle, or Bottom Right angle). The user should take care in installing this header.
Page 94 of 180
REF: BB_SRM
BeagleBoard System
Reference Manual
Revision C4
CAUTION: The voltage levels on the expansion header are 1.8V. Exposure of these
signals to a higher voltage will result in damage to the board and a voiding of the
warranty.
8.19.1 OMAP3530 Interface
The main purpose of the expansion connector is to route additional signals from the
OMAP3530 processor. Table 20 shows all of the signals that are on the expansion
header. As the OMAP3530 has a multiplexing feature, multiple signals can be connected
to certain pins to add additional options as it pertains to the signal available. Each pin can
be set individually for a different mux mode. This allows any of the listed mux modes to
be set on a pin by pin basis by writing to the pin mux register in software. Following is
the legend for Table 20.
X= there is no signal connected when this mode is selected
Z= this is the safe mode meaning neither input to output. This is the default mode on
power up.
*= this indicates that there is a signal connected when this mode is selected, but it has no
useful purpose without other pins being available. Access to these other pins is not
provided on the expansion connector.
The first column is the pin number of the expansion connector.
The second column is the pin number of the OMAP3530 processor.
The columns labeled 0-7 represent each of the pin mux modes for that pin. By setting this
value in the control register, this signal will be routed to the corresponding pin of the
expansion connector. These setting are on a pin by pin basis. Any pin can be set with the
mux register setting, and the applicable signal will be routed to the pin on the expansion
connector.
Page 95 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Table 20.
EXP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Revision C4
Expansion Connector Signals
OMAP
0
1
AE3
AB26
AF3
AA25
AH3
AE5
AE4
AB25
AF4
V21
AG4
W21
AH4
K26
AH5
U21
AG5
Y21
AE2
AA21
AE15
AF15
25
26
27
28
MMC2_DAT7
UART2_CTS
MMC2_DAT6
UART2_TX
MMC2_DAT5
McBSP3_FSX
MMC2_DAT4
UART2_RTS
MMC2_DAT3
McBSP1_DX
MMC2_DAT2
McBSP1_CLKX
MMC2_DAT1
McBSP1_FSX
MMC2_DAT0
McBSP1_DR
MMC2_CMD
McBSP1_CLKR
MMC2_CLKO
McBSP1_FSR
I2C2_SDA
I2C2_SCL
*
McBSP3_DX
*
McBSP3_CLKX
*
UART2_RX
*
McBSP3_DR
McSPI3_CS0
McSPI4_SIMO
McSPI3_CS1
X
X
McSPI4_CS0
McSPI3_SOMI
McSPI4_SOMI
McSPI3_SIMO
McSPI4_CLK
McSPI3_CLK
X
X
X
2
VIO_1V8
DC_5V
*
GPT9_PWMEVT
*
GPT11_PWMEVT
*
X
X
GPT10_PWMEVT
X
McBSP3_DX
X
McBSP3_CLKX
X
McBSP3_FSX
X
McBSP3_DR
X
X
X
*
X
X
REGEN
nRESET
GND
GND
3
4
5
6
7
*
X
*
X
*
X
*
X
X
X
X
X
X
x
X
X
X
X
X
Z
X
X
GPIO_139
GPIO_144
GPIO_138
GPIO_146
GPIO_137
GPIO_143
GPIO_136
GPIO_145
GPIO_135
GPIO_158
GPIO_134
GPIO_162
GPIO_133
GPIO_161
GPIO_132
GPIO_159
GPIO_131
GPIO_156
GPIO_130
GPIO_157
GPIO_183
GPIO_168
*
X
*
X
*
*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
8.19.2 Expansion Signals
This section provides more detail on each of the signals available on the expansion
connector. They are grouped by functions in Table 21 along with a description of each
signal and the MUX setting to activate the pin. If you use these signals in their respective
groups and that is the only function you use, all of the signals are available. Whether or
not the signals you need are all available, depends on the muxing function on a per-pin
basis. Only one signal per pin is available at any one time.
Page 96 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Table 21.
Signal
MMC2_DAT7
MMC2_DAT6
MMC2_DAT5
MMC2_DAT4
MMC2_DAT3
MMC2_DAT2
MMC2_DAT1
MMC2_DAT0
MMC2_CMD
MMC_CLKO
McBSP1_DR
McBSP1_CLKS
McBSP1_FSR
McBSP1_DX
McBSP1_CLKX
McBSP1_FSX
McBSP1_CLKR
I2C2_SDA
I2C2_SCL
McBSP3_DR
McBSP3_DX
McBSP3_CLKX
McBSP3_FSX
GPIO_130
GPIO_131
GPIO_132
GPIO_133
GPIO_134
GPIO_135
GPIO_136
GPIO_137
GPIO_138
GPIO_139
GPIO_143
GPIO_144
GPIO_145
GPIO_146
GPIO_156
GPIO_158
GPIO_159
GPIO_161
GPIO_162
GPIO_168
GPIO_183
McSPI3_CS0
McSPI3_CS1
McSPI3_SIMO
McSPI3_SOMI
McSPI3_CLK
McSPI4_SIMO
McSPI4_SOMI
McSPI4_CS0
McSPI4_CLK
UART2_CTS
UART2_RTS
Revision C4
Expansion Connector Signal Groups
Description
SD/MMC Port 2
SD/MMC data pin 7.
SD/MMC data pin 6.
SD/MMC data pin 5.
SD/MMC data pin 4.
SD/MMC data pin 3.
SD/MMC data pin 2.
SD/MMC data pin 1.
SD/MMC data pin 0.
SD/MMC command signal.
SD/MMC clock signal.
McBSP Port 1
Multi channel buffered serial port receive
-------------------------------------------------------------------------Multi channel buffered serial port transmit frame sync RCV
Multi channel buffered serial port transmit
Multi channel buffered serial port transmit clock
Multi channel buffered serial port transmit frame sync XMT
Multi channel buffered serial port receive clock
I2C Port 2
I2C data line.
I2C clock line
McBSP Port 3
Multi channel buffered serial port receive
Multi channel buffered serial port transmit
Multi channel buffered serial port receive clock
Multi channel buffered serial port frame sync transmit
General Purpose I/O Pins
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
GP Input/Output pin. Can be used as an interrupt pin.
McSPI Port 3
Multi channel SPI chip select 0
Multi channel SPI chip select 1
Multi channel SPI slave in master out
Multi channel SPI slave out master in
Multi channel SPI clock
McSPI Port 4
Multi channel SPI slave in master out
Multi channel SPI slave out master in
Multi channel SPI chip select 0
Multi channel SPI clock
UART Port 2
UART clear to send.
UART request to send
I/O
EXP
OMAP
Mux
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
3
5
7
9
11
13
15
17
19
21
AE3
AF3
AH3
AE4
AF4
AG4
AH4
AH5
AG5
AE2
1
1
1
1
1
1
1
1
1
1
I
N/A
I/O
I/O
I/O
I/O
I/O
18
N/A
22
12
14
16
20
IOD
IOD
23
24
I
I/O
I/O
I/O
10,18
4,12
6,14
8,16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
21
19
17
15
13
11
9
7
5
3
8
4
10
6
20
12
18
16
14
24
23
O
O
I/O
I/O
I/O
11
13
19
17
21
I/O
I/)
O
I/O
12
18
16
20
I/O
O
4
10
Page 97 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
UART2_RX
UART2_TX
GPT9_PWMEVT
GPT11_PWMEVT
GPT10_PWMEVT
Revision C4
UART receive
UART transmit
I
O
8
6
GPT PWM
PWM or event for GP timer 9
PWM or event for GP timer 11
PWM or event for GP timer 10
O
O
O
4
10
8
8.19.3 Power
The expansion connector provides two power rails. The first is the VIO_1.8V rail which
is supplied by the TPS65950. This rail is limited in the current it can supply from the
TPS65950 and what remains from the current consumed by the BeagleBoard and is
intended to be used to provide a rail for voltage level conversion only. It is not intended
to power a lot of circuitry on the expansion board. All signals from the BeagleBoard are
at 1.8V.
The other rail is the DC_5V. The same restriction exits on this rail as mentioned in the
USB section. The amount of available power to an expansion board depends on the
available power from the DC supply or the USB supply from the PC.
8.19.4 Reset
The nRESET signal is the main board reset signal. When the board powers up, this
signal will act as an input to reset circuitry on the expansion board. After power up, a
system reset can be generated by the expansion board by taking this signal low. This
signal is a 1.8V level signal.
8.19.5 Power Control
There is an additional open-drain signal on the connector called REGEN. The purpose of
this signal is to provide a means to control power circuitry on the expansion card to turn
on and off the voltages. This insures that the power on the expansion board is turned on at
the appropriate time. Depending on what circuitry is provided on the expansion board, an
additional delay may be needed to be added before the circuitry is activated. Refer to the
OMAP3530 and TPS65950 documentation for more information.
8.20
Additional Expansion Header
If you choose not to use the LCD headers for access to the LCD signals or for the DVI-D
interface, they can also be used for other functions on the board based on the pin mux
setting of each pin. Table 22 shows the options for J4 and Table 23 shows the options
for J5. The MUX: column indicates which MUX mode must be set for each pin to make
the respective signals accessible on the pins of the OMAP3530.
Page 98 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Revision C4
Table 22.
J4 GPIO Signals
Pin#
Signal
MUX:0
MUX:2
MUX:4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DVI_DATA1
DVI_DATA0
DVI_DATA3
DVI_DATA2
DVI_DATA5
DVI_DATA4
DVI_DATA12
DVI_DATA10
DVI_DATA23
DVI_DATA14
DVI_DATA19
DVI_DATA22
I2C3_SDA
DVI_DATA11
DVI_VSYNC
DVI_PUP
DATA1
DATA0
DATA3
DATA2
DATA5
DATA4
DATA12
DATA10
DATA23
DATA14
DATA19
DATA22
I2C3_SDA
DATA11
VSYNC
DVI_PUP
UART1_RTS
UART1_CTS
UART3_TX
UART3_RX
GPIO71
GPIO70
GPIO73
GPIO72
GPIO75
GPIO74
GPIO82
GPIO79
GPIO93
GPIO84
GPIO89
GPIO92
GPIO81
GPIO68
-
Table 23.
McSPI3_SIMO
McSPI3_CS1
-
J5 GPIO Signals
Pin#
Signal
MUX:0
MUX:2
MUX:4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DVI_DATA20
DVI_DATA21
DVI_DATA17
DVI_DATA18
DVI_DATA15
DVI_DATA16
DVI_DATA7
DVI_DATA13
DVI_DATA8
NC
DVI_DATA9
I2C3_SCL
DVI_DATA6
DVI_CLK+
DVI_DEN
DVI_HSYNC
DATA20
DATA21
DATA17
DATA18
DATA15
DATA16
DATA7
DATA13
DATA8
DATA9
I2C3_SCL
DATA6
PCLK
DEN
HSYNC
McSPI3_SOMI
McSPI3_CS0
McSPI3_CLK
UART1_RX
-
GPIO90
GPIO91
GPIO87
GPIO88
GPIO85
GPIO86
GPIO77
GPIO83
GPIO78
GPIO79
GPIO_76
GPIO66
GPIO69
GPIO67
UART1_TX
-
Page 99 of 180
REF: BB_SRM
9.0
BeagleBoard System
Reference Manual
Revision C4
Connector Pinouts and Cables
This section provides a definition of the pinouts and cables to be used with all of the
connectors and headers on the BeagleBoard.
THERE ARE NO CABLES SUPPLIED WITH THE BEAGLEBOARD.
9.1
Power Connector
Figure 47 is a picture of the BeagleBoard power connector with the pins identified. The
supply must have a 2.1mm center hot connector with a 5.5mm outside diameter.
Figure 47. Power Connector
The supply must be at least 500mA with a maximum of 2A. If the expansion connector is
used, more power will be required depending on the load of the devices connected to the
expansion connector.
WARNING: DO NOT PLUG IN ANYTHING BUT
5V TO THE DC CONNECTOR OR THE BOARD
WILL BE DAMAGED!!!!
Page 100 of 180
REF: BB_SRM
9.2
BeagleBoard System
Reference Manual
Revision C4
USB OTG
Figure 48 is a picture of the BeagleBoard USB OTG connector with the pins identified.
Figure 48. USB OTG Connector
The shorting pads to convert the OTG port to a Host mode are found in Figure 49.
Figure 49. OTG Host Shorting Pads
Page 101 of 180
REF: BB_SRM
9.3
BeagleBoard System
Reference Manual
Revision C4
S-Video
Figure 50 is the S-Video connector on the BeagleBoard.
Figure 50. S-Video Connector
Page 102 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
9.4
Revision C4
DVI-D
Figure 51 is the pinout of the DVI-D connector on BeagleBoard.
Figure 51. DVI-D Connector
Table 24 is the pin numbering of the two ends of the cable as it relates to the signals used in the
DVI-D interface itself.
Table 24.
SIGNAL
DATA 2DATA 2+
SHIELD
DDS CLOCK
DDS DATA
DATA 1DATA 1+
SHIELD
5V
GROUND (5V)
DATA 0SIGNAL
DATA 0+
DVI-D to HDMI Cable
DVI-D PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DVI-D PIN#
18
HDMI PIN#
3
1
2
15
16
6
4
5
18
17
9
DVI-D PIN#
7
Page 103 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
SHIELD
CLOCK+
CLOCK-
19
20
21
22
23
24
Revision C4
5
10
12
DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE
BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY
AND THEN POWER ON THE BEAGLEBOARD.
Figure 52 is the cable to be used to connect to an LCD monitor.
Figure 52. DVI-D Cable
Page 104 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
9.5
Revision C4
LCD
This section covers the pair of headers that provide access to the raw 1.8V DSS signals
from the OMAP3530 processor. This provides the ability to create adapters for such
things as different LCD panels, LVDS interfaces, etc.
9.5.1
Connector Pinout
The Table 25 and 26 define the pinout of the LCD connectors. All signal levels are 1.8V
with the exception of DVI_PUP signal which is 3.3V.
Table 25.
J4 LCD Signals
Pin#
Signal
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC_5V
DC_5V
DVI_DATA1
DVI_DATA0
DVI_DATA3
DVI_DATA2
DVI_DATA5
DVI_DATA4
DVI_DATA12
DVI_DATA10
DVI_DATA23
DVI_DATA14
DVI_DATA19
DVI_DATA22
I2C3_SDA
DVI_DATA11
DVI_VSYNC
PWR
PWR
O
O
O
O
O
O
O
O
O
O
O
O
I/O
O
O
18
DVI_PUP
19
20
GND
GND
DC rail from the Main DC supply
DC rail from the Main DC supply
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
I2C3 Data Line
LCD Pixel Data bit
LCD Vertical Sync Signal
Control signal for the DVI
controller. When Hi, DVI is
enabled. Can be used to activate
circuitry on adapter board if
desired.
Ground bus
Ground bus
O
PWR
PWR
Page 105 of 180
BeagleBoard System
Reference Manual
REF: BB_SRM
Table 26.
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
9.5.2
Signal
3.3V
VIO_1V8
DVI_DATA20
DVI_DATA21
DVI_DATA17
DVI_DATA18
DVI_DATA15
DVI_DATA16
DVI_DATA7
DVI_DATA13
DVI_DATA8
NC
DVI_DATA9
I2C3_SCL
DVI_DATA6
DVI_CLK+
DVI_DEN
DVI_HSYNC
GND
GND
Revision C4
J5 LCD Signals
I/O
Description
PWR
PWR
O
O
O
O
O
O
O
O
O
3.3V reference rail
1.8V buffer reference rail.
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
LCD Pixel Data bit
No connect
LCD Pixel Data bit
I2C3 Clock Line
LCD Pixel Data bit
DVI Clock
Data Enable
Horizontal Sync
Ground bus
Ground bus
I/O
O
O
O
O
PWR
PWR
Connector Suppliers
The actual connector to be used will be determined by the supplier of the board to be
plugged into the Beagle. Table 27 below list a few of the part numbers and suppliers that
can be used for the connectors on the LCD interface. All of the listed connectors are in a
vertical mount configuration
Table 27.
Supplier
Major League
“
“
“
“
SAMTEC
“
Sullins
J4 and J5 Connector Sources
Header
TSHC-510-D-06-340-G-LF
TSHC-510-D-06-340-T-LF
TSHC-510-D-06-340-GT-LF
TSHC-510-D-06-340-H-LF
TSHC-510-D-06-340-F-LF
FTS-110-01-L-D
FTS-110-03-L-D
GRPB052VWVN-RC
Socket (Thru Hole)
SSHS-510-D-04-G-LF
SSHS-510-D-04-T-LF
SSHS-510-D-04-TG-LF
SSHS-510-D-04-H-LF
SSHS-510-D-04-F-LF
Socket (SMT)
LSSHS-510-D-06-G-LF
LSSHS-510-D-06-T-LF
LSSHS-510-D-06-F-LF
FLE-110-01-G-DV
Major League http://www.mlelectronics.com/
Samtec
http://www.samtec.com
Sullins
http://www.sullinscorp.com
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9.5.3
Revision C4
Dimensions
Figure 53 provides some of the dimensions that can assist in the location of the LCD
headers. It is strongly recommended that the CAD data be used in order to determine
their location exact. Table 28 provides the values for each lettered dimension.
Figure 53. Top Mount LCD Adapter
Table 28.
Connector Dimensions
Dimension
A
B
C
D
Inches Millimeters
1.085
27.56
0.118
2.99
0.296
7.52
0.190
4.83
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9.5.4
Revision C4
Mounting Scenarios
This section provides a few possible mounting scenarios for the LCD connectors. It
should be noted that the voltage level of these signals are 1.8V. It will require that they be
buffered in order to drive other voltage levels.
9.5.4.1
Top Mounting
Figure 54 shows the board being mounted on top of the BeagleBoard.
LCD Connector
Buffer Logic
Adapter
BeagleBoard
Figure 54. Top Mount LCD Adapter
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9.5.4.2
Revision C4
Bottom Mounting
Figure 55 shows the board being mounted under the BeagleBoard.
BeagleBoard
Buffer Logic
LCD Connector
Adapter
Figure 55. Bottom Mount LCD Adapter
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9.6
BeagleBoard System
Reference Manual
Revision C4
Audio Connections
Figure 56 is the audio input jack required to connect to the BeagleBoard.
Figure 56. Audio In Plug
Figure 57 is the actual connector used on the BeagleBoard.
Figure 57. Audio In Plug
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9.7
BeagleBoard System
Reference Manual
Revision C4
Audio Out
Figure 58 is the audio out jack required to connect to the BeagleBoard.
Figure 58. Audio Out Plug
Figure 59 is the actual connector used on the BeagleBoard.
Figure 59. Audio In Plug
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9.8
Revision C4
JTAG
Figure 60 is the JTAG connector pin out showing the pin numbering.
Figure 60. JTAG Connector Pinout
Table 29 gives a definition of each of the signals on the JTAG header.
Table 29.
Pin
Signal
1
3
7
9
11
2
13
14
5
4,8,10,12,14
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_RTCK
JTAG_TCK
JTAG_nTRST
JTAG_EMU0
JTAG_EMU1
VIO
GND
JTAG Signals
Description
Test mode select
Test data input
Test Data Output
ARM Clock Emulation
Test Clock
Test reset
Test emulation 0
Test emulation 1
Voltage pin
Ground
I/O
I/O
I
O
O
I
I
I/O
I/O
PWR
PWR
All of the signals are 1.8V only. The JTAG emulator must support 1.8V signals for use
on the BeagleBoard.
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If a 20 pin connector is provided on the JTAG emulator, then a 20 pin to 14 pin adapter
must be used. You may also use emulators that are either equipped with a 14 pin
connector or are universal in nature.
Figure 61 shows an example of a 14 pin to 20 pin adapter.
Figure 61. JTAG 14 to 20 Pin Adapter
Figure 62 shows how the JTAG cable is to be routed when connected to the
BeagleBoard.
C4
Figure 62. JTAG Connector Pinout
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9.9
BeagleBoard System
Reference Manual
Revision C4
RS232
Figure 63 is the RS232 header on the BeagleBoard with the pin numbers identified.
Figure 63. RS232 Header
Figure 64 is the cable that is required in order to access the RS232 header. This cable can
be purchased from various sources and is referred to as the ATI/Everex type cable.
Figure 64. RS232 Flat Cable
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9.10
BeagleBoard System
Reference Manual
Revision C4
Expansion
We are changing the configuration of the expansion header on all Beagle boards. This
will standardize on the configuration for compatibility with expansion cards. The socket
will be mounted on the BACKSIDE of the board.
Figure 65 is a drawing and picture of the socket that is specified.
Figure 65. Expansion Sockets
The selected supplier for this socket is Major League Electronics
http://www.mlelectronics.com/ and the part number is LSWSS-114-D-02-T-LF. Other
suppliers may be available as well and can be used as long as it is compatible with this
socket. This socket is mounted on the BACK of the BeagleBoard.
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9.11
Revision C4
Battery Installation
9.11.1 Battery
The board was designed to use the VL-1220/VCN battery from Panasonic-BSG. This is a
Vanadium Pentoxide Lithium Rechargeable Battery with a 7mAH capacity. Figure 66 is
a picture of the battery.
Figure 66. Optional Battery
9.11.2 Battery Installation
THE FOLLOWING STRUCTIONS ASSUME THE USER HAS PREVIOUS
EXPERIENCE WITH BATTERIES. BATTERY INSTALLATION IS THE SOLE
RESPONSABILTY OF THE USER. INSTALLATION OF THE BATTERY BY THE
USER IS AT THEIR OWN RISK. FAILURE TO FOLLOW THE INSTRUCTIONS
CAN RESULT IN DAMAGE TO THE BOARD. THIS DAMAGE IS NOT COVERED
UNDER THE WARRANTY.
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Figure 67 shows the location of the battery on the Beagle Board.
C4
Figure 67. Optional Battery Location
Following are the steps required to install the battery.
1)
2)
3)
4)
Remove all cables from the board.
Remove R66 from the board as shown on Figure 67.
Using Figure 66, locate the positive (+) lead of the battery.
Insert the (+) lead into the hole that is marked (+) on Figure 67.
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10.0 BeagleBoard Accessories
Throughout this manual various items are mentioned as not being provided with the
standard BeagleBoard package or as options to extend the features of the BeagleBoard.
The concept behind BeagleBoard is that different features and functions can be added to
BeagleBoard by bringing your own peripherals. This has several key advantages:
o User can choose which peripherals to add.
o User can choose the brand of peripherals based on driver availability and ability
to acquire the particular peripheral
o User can add these peripherals at a lower cost than if they were integrated into the
BeagleBoard.
This section covers these accessories and add-ons and provides information on where
they may be obtained. Obviously things can change very quickly as it relates to devices
that may be available. Please check BeagleBoard.org for an up to date listing of these
peripherals.
Inclusion of any products in this section does not guarantee that they will
operate with all SW releases. It is up to the user to find the appropriate
drivers for each of these products. Information provided here is intended to
expose the capabilities of what can be done with the BeagleBoard and how it
can be expanded.
All pricing information provided is subject to change an din most cases is likely to be
lower depending on the products purchased and from where they are purchased.
Covered in this section are the following accessories:
o
o
o
o
o
o
o
o
o
o
o
DC Power Supplies
Serial Ribbon cable
USB Hubs
USB Thumb Drives
DVI-D Cables
DVI-D Monitors
SD/MMC Cards
USB to Ethernet
USB to WiFi
USB Bluetooth
Expansion Cards
NO CABLES OR POWER SUPPLIES ARE PROVIDED WITH THE BEAGLEBOARD.
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10.1
Revision C4
DC Power Supply
Tabletop or wall plug supplies can be used to power BeagleBoard. Table 30 provides the
specifications for the BeagleBoard DC supply. Supplies that provide additional current
than what is specified can be used if additional current is needed for add on accessories.
The amount specified is equal to that supplied by a USB port.
Table 30.
DC Power Supply Specifications
Specification
Voltage
Current
Connector
Requirement
5.0
500mA (minimum)
2.1mm x 5.5mm Center hot
Unit
V
mA
It is recommended that a supply higher than 500mA be used if higher current peripherals
are expected to be used or if expansion boards are added.
Table 31 lists some power supplies that will work with the BeagleBoard.
Table 31.
Part #
EPS050100-P6P
DPS050200UPS-P5P-SZ
DC Power Supplies
Manufacturer
CUI
CUI
Supplier
Digi-Key
Digi-Key
Price
$7
$16
Figure 68 is a picture of the type of power supply that will be used on the BeagleBoard.
Figure 68. DC Power Supply
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10.2
Revision C4
Serial Ribbon Cable
Figure 69 is an example of the serial ribbon cable for the BeagleBoard. Other serial
cables that will work on the board may have a different appearance.
Figure 69. RS232 Cable
If you like, you can al71 67.
Figure 70. RS232 Cable Wiring
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Table 32 shows the pinout of the ribbon cable connector.
Table 32.
Cable Pinout
Ribbon Cable
1
2
3
4
5
6
7
8
9
10
10.3
DB9
1
2
3
4
5
6
7
8
9
10
USB Hubs
There are no known or anticipated issues with USB hubs. However, it should be noted
that a self powered hub is highly recommended. Table 34 is a list of Hubs that have been
tested on the BeagleBoard.
Table 33.
Supplier
IOGEAR
D-Link
Vakoss
10.4
USB Hubs Tested
Part Number
GUH274
DUB-H4 2.0
TC-204-NS
DVI Cables
In order to connect the DVI-D interface to a LCD monitor, a HDMI to DVI-D cable is
required. Figure 71 is a picture of a HDMI to DVI-D cable.
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Figure 71. HDMI to DVI-D Cable
10.5
DVI-D Monitors
There are many monitors that can be used with the BeagleBoard. With the integrated EDID
feature, timing data is collected from the monitor to enable the SW to adjust its timings. Table 35
shows a short list of the monitors that have been tested to date on the BeagleBoard at the
1024x768 resolution. Please check on BeagleBoard.org for an up to date listing of the DVI-D
monitors as well as information on the availability of drivers.
Table 34.
Manufacturer
Dell
Insignia
Dell
DVI-D Monitors Tested
Part Number
2407WFPb
NS-LCD15
1708FP
Status
Tested
Tested
Tested
DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE
BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY
AND THEN POWER ON THE BEAGLEBOARD.
The digital portion of the DVI-D interface is compatible with HDMI and is electrically
the same. A standard HDMI cable may be used to connect to the HDMI input of
monitors. Whether or not the Beagle will support those monitors is dependent on the
timings that are used on the Beagle and those that are accepted by the monitor. This may
require a change in the software running on the Beagle. The audio and encryption
features of HDMI are not supported by the Beagle.
The analog portion of DVI which provides RGB analog type signals is not supported by
the Beagle. Buying a DVI to VGA adapter connector will not work on a VGA display.
You will need an active DVI-D to VGA adapter.
10.6
SD/MMC Cards
Table 36 is a list of SD/MMC cards that have been tested on BeagleBoard. Please check
BeagleBoard.org for an up to date listing of the SD/MMC cards that have been tested as well as
information on the availability of drivers if required.
Table 35.
Manufacturer
Patriot
Microcenter
SD/MMC Cards Tested
Type
SD
SD
Part Number
1GB
1GB/2GB
Status
Tested
Tested
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10.7
Revision C4
USB to Ethernet
There are several USB to Ethernet adapters on the market and Figure 72 shows a few of
these devices. These devices can easily add Ethernet connectivity to BeagleBoard by
using the USB OTG port in the host. This will require a special cable to convert the
miniAB connector to a Type A or a hub can also be used. These are provided as examples
only. Check BeagleBoard.org for information on devices that have drivers available for
them.
Figure 72. USB to Ethernet Adapters
Table 37 provides examples of USB to Ethernet Adapters that might be used with the
BeagleBoard. This list has not been verified. Inclusion of these items in the table does not
guarantee that they will work, but is provided as examples only. Please check
BeagleBoard.org for an up to date listing of the USB to Ethernet devices as well as information
on the availability of drivers.
Table 36.
USB to Ethernet Adapters
Product
Manufacturer
Status
ASOHOUSB
Airlink
Not Tested
TU-ET100C 10/100Mbps
TRENDnet
Not Tested
SABRENT
NB-USB20
Not Tested
Zonet
ZUN2210
Not Tested
StarTech
USB2105S
Not Tested
MOSCHIP is the silicon provider for USB to Ethernet devices. The product that has been
tested uses the 7830 from MOSCHIP and has a vendor ID of 9710 and a product ID of
7830. The devices above that are based upon the MOSCHIP device are highlighted in
red.
10.8
USB to WiFi
There are several USB to WiFi adapters on the market and Figure 73 shows a few of
these devices. These devices can easily add WiFi connectivity to BeagleBoard by using
the USB OTG port in the host mode. This will require a special cable to convert the
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Revision C4
miniAB connector to a Type A or a hub can also be used. These are provided as examples
only. Check BeagleBoard.org for information on devices that have drivers available for
them.
Figure 73. USB to WiFi
Table 38 provides a list of USB to WiFi adapters that could be used with the
BeagleBoard. Inclusion of these items in the table does not guarantee that they will work,
but is provided as examples only. Please check BeagleBoard.org for an up to date listing
of the USB to WiFi devices as well as information on the availability of drivers.
Table 37.
Product
4410-00-00AF
HWUG1
TEW-429Uf
USB to WiFi Adapters
Manufacturer
Zoom
Hawkins
Trendnet
Status
Not Tested
Not Tested
Not Tested
It should be noted that the availability of Linux drivers for various WiFi devices is
limited. Before purchasing a particular device, please verify the availability of drivers for
that device.
10.9
USB to Bluetooth
There are several USB to Bluetooth adapters on the market and Figure 74 shows a few of
these devices. These devices can easily add Bluetooth connectivity to BeagleBoard by
using the USB OTG port in the host mode. This will require a special cable to convert the
miniAB connector to a Type A or a hub can also be used. These are provided as
examples only. Check BeagleBoard.org for information on devices that have drivers
available for them and their test status.
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Figure 74. USB to Bluetooth
Table 39 provides a list of USB to Bluetooth adapters that could be used with the
BeagleBoard. Inclusion of these items in the table does not guarantee that they will work,
but is provided as examples only. Please check BeagleBoard.org for an up to date listing
of the USB to Bluetooth devices as well as information on the availability of drivers.
Table 38.
USB to Bluetooth Adapters
Product
TBW-105UB
ABT-200
F8T012-1
Manufacturer
Trendnet
Airlink
Belkin
10.10 Expansion Card Design
This section covers the requirements for expansion cards that are designed to mount onto
the Beagle Board..
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11.0 Mechanical Information
11.1
BeagleBoard Dimensions
This section provides information on the mechanical aspect of the BeagleBoard. Figure
75 is the dimensions of the BeagleBoard.
C4
Figure 75. BeagleBoard Dimension Drawing
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11.2
BeagleBoard System
Reference Manual
Revision C4
BeagleBoard Expansion Card Design Information
This section provides information on what is required from a mechanical and electrical
aspect to create expansion cards for the BeagleBoard that are designed to connect to the
Expansion header on the BeagleBoard. Users are free to create their own cards for private
or commercial use, but in order to be supported by the Software they must conform to
these standards if such support is desired.
11.2.1 Mounting Method
The standard method to provide a daughtercard for the BeagleBoard is for it to be
mounted UNDER the Beagle Board as described in Figure 76.
Figure 76. BeagleBoard Bottom Stacked Daughter Card
At the next letter revision of the board, all BeagleBoards produced will have the
connectors pre mounted onto the bottom of the BeagleBoard.
11.2.2 Expansion EEPROM
All expansion cards designed for use with the BeagleBoard are required to have a
EEPROM located on the board. This is to allow for the identification of the card by the
Software in order to set the pin muxing on the expansion connector to be compatible with
the expansion card.
The schematic for the EEPROM is in Figure 77 below.
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1
2
3
4
A0 VCC
A1
WP
A2 SCL
VSS SDA
AT24C01
8
7
6
5
BB_WP
BB_I2C_SCL
BB_I2C_SDA
4.7K,5%,0402
1
2 R21
A0
A1
A2
4.7K,5%,0402
1
2 R20
VIO_1V8
U8
4.7K,5%,0402
1
2
R19
VIO_1V8
TP7
C28
TP
0.1uf ,CER,0402
Figure 77. BeagleBoard Expansion Board EEPROM Schematic
The EEPROM must be write protected. It is suggested that a testpoint be used to allow
for the WP to be disabled during test to allow the required data to be written to the
EEPROM. The EEPROM is to be connected to I2C2 as found on the main expansion
connector.
The EEPROM that is designated is the AT24C01 or ATC24C01B. The AT24C01 is
designated as “Not Recommended for New Design” but can still be used. The
AT24C01B is the replacement part and is available in several different packages, all of
which can be used.
o
o
o
o
o
o
TSSOP 8
PDIP 8
UDFN 8
SOIC 8
SOT23 5
dBGA2 8
The contents of the EEPROM are not specified in this document.
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12.0 Board Verification
This section provides a step by step process to be followed to verify that the hardware is
working. This is the same basic process the board is taken through in production testing.
For an up to date listing of common questions and their answers, please refer to
http://elinux.org/BeagleBoardFAQ
12.1
Equipment
To run these tests you will need the following components:
o
o
o
o
o
o
o
o
o
o
o
o
BeagleBoard
5V DC supply with a 2.1mm I.D. and 5.5mm O.D. connector
SD Card
PC
USB miniA to A cable
USB HUB
DVI-D Monitor
DVI-D to HDMI cable
Speakers
3.5mm stereo cable with connectors on both ends
DB9 Null-Modem Cable
DB9 to IDC-10 cable ATI/Everex configuration
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12.2
BeagleBoard System
Reference Manual
Revision C4
Out of the Box
Each BeagleBoard comes pre-loaded with the XLoader and UBoot in Flash. When
powered up, it will do the following:
1. Plug in either a USB cable to the board and then to a PC or plug in a 5V power
supply.
2. Power LED (D5) will turn on.
3. On the terminal window the following will be printed:
Texas Instruments X-Loader 1.4.2 (Feb 19 2009 - 12:01:24)
Loading u-boot.bin from nand
U-Boot 2009.01-dirty (Feb 19 2009 - 12:22:31)
I2C: ready
OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz
OMAP3 Beagle board + LPDDR/NAND
DRAM: 256 MB
NAND: 256 MiB
*** Warning - bad CRC or NAND, using default environment
MUSB: using high speed
In: serial usbtty
Out: serial usbtty
Err: serial usbtty
The warning message is not an indication of an error condition and is normal. The
UBoot is configured to look for a script file on the SD card for booting instructions. If
not found, it will then look for the environment variables. As these are not loaded at
the factory, you will see the warning message.
4. At this point the following LEDS will turn on:
o USR0
o USR1
o PMU
5. Then the following will be sent to the terminal window and a countdown will
commence. To stop the countdown, hit any key on the terminal
Board revision C
Serial #486000030000000004013f8a17019010
Hit any key to stop autoboot: 10
The revision of the board should be identified as a Rev C. The Serial# is NOT the
board serial number, but a unique ID for the processor.
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6. The BeagleBoard.org logo will be sent out of the DVI port and the color bars will
appear on the S-Video Port.
7. If you do not stop the booting process by hitting a key, the following will be
printed to the terminal.
No MMC card found
Booting from nand ...
NAND read: device 0 offset 0x280000, size 0x400000
4194304 bytes read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!
OMAP3 beagleboard.org #
12.3
SD Card Configuration
In order to boot from the SD card, it must be formatted and the files loaded. The
following steps explain that process.
1. Format the MMC/SD Card for FAT32 File System using the HP USB Disk
Storage Format Tool 2.0.6: http://selfdestruct.net/misc/usbboot/SP27213.exe
2. Insert the Card writer/reader into the Windows machine.
3. Insert MMC/SD card into the card reader/writer
4. Open the HP USB Disk Storage Format Tool.
5. Select “FAT as File System”. Click on “Start”.
6. After formatting is done Click “OK”
7. Copy the following files on to MMC in the exact order listed. COPY THE MLO
FIRST! Make sure you name the file as indicated in the BOLD type. These files
can be found at
http://code.google.com/p/beagleboard/wiki/BeagleboardRevCValidation
MLO as MLO
u-boot as u-boot.bin
u-boot for flash as u-boot-f.bin
ramdisk image as ramdisk.gz
Kernel (uImage) as uImage.bin
reset.scr as boot.scr
x-loader image as x-load.bin.ift
Regular script file as normal.scr
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12.4
BeagleBoard System
Reference Manual
Revision C4
Setup
This step sets up the board for the tests to follow.
1. Make sure Beagle power is in OFF state by removing the 5V supply and the USB
host connection.
2. Connect the IDC UART cable the BeagleBoard and using a Null-Modem serial
cable connect it to a SERIAL port on a Window/Linux/Mac machine
3. Have terminal program, such as TeraTerm, HyperTerminal, or Minicom, running
on the host machine.
4. Configure the terminal program for (BAUD RATE - 115200, DATA - 8 bit,
PARITY- none, STOP - 1bit, FLOW CONTROL - none)
5. Insert the MMC/SD card (that is prepared as described above) into MMC/SD slot
on Beagle Board.
6. Connect a LCD Monitor to DVI/HDMI port on the Beagle Board.
7. Connect an externally powered speaker to audio out jack on Beagle Board.
8. Connect a Line-in cable from PC or any player to Audio In jack on Beagle Board.
9. Connect a TV (NTSC-M) to S-video port.
10. Power ON LCD, TV and audio speakers.
12.5
Factory Boot Verification
The BeagleBoard comes pre-Flashed with the Xloader and UBoot in Flash. This step
verifies that the board will boot properly from NAND. If the board has been flashed and
the default code removed or overwritten, then you should proceed to the next step.
1. Connect the USB cable to the Host PC,
2. The power LED should come on.
3. On the terminal window the following should be printed out by the BeagleBoard:
Texas Instruments X-Loader 1.4.2 (Feb 19 2009 - 12:01:24)
Loading u-boot.bin from nand
U-Boot 2009.01-dirty (Feb 19 2009 - 12:22:31)
I2C: ready
OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz
OMAP3 Beagle board + LPDDR/NAND
DRAM: 256 MB
NAND: 256 MiB
*** Warning - bad CRC or NAND, using default environment
MUSB: using high speed
In: serial usbtty
Out: serial usbtty
Err: serial usbtty
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Revision C4
Board revision C
Serial #486000030000000004013f8a17019010
Hit any key to stop autoboot: 10
No MMC card found
Booting from nand ...
NAND read: device 0 offset 0x280000, size 0x400000
4194304 bytes read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
4. The USER LEDS and the PMU LED should be on.
5. The S-Video output should display color bars.
6. The DVI-D monitor should display a solid orange screen.
12.6
Board SD Boot
This test will force the BeagleBoard to boot from the SD card instead of the onboard
Flash.
1. Press and hold the USER button while pressing and releasing the RESET button.
2. The following should be printed to the terminal window:
40V
Texas Instruments X-Loader 1.4.2 (Feb 19 2009 - 12:01:24)
Reading boot sector
Loading u-boot.bin from mmc
U-Boot 2009.01-dirty (Feb 19 2009 - 12:23:21)
I2C: ready
OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz
OMAP3 Beagle board + LPDDR/NAND
DRAM: 256 MB
NAND: 256 MiB
Using default environment
MUSB: using high speed
In: serial usbtty
Out: serial usbtty
Err: serial usbtty
Board revision C
Serial #486000030000000004013f8a17019010
Hit any key to stop autoboot: 10
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3. The USER LEDS and the PMU LED should be on.
Hitting any key on the terminal before the countdown reaches 10, will stop the booting
process. If no key is hit, it will continue and flash the SW into the NAND. Go to the next
section for a description of this.
12.7
Factory Boot Reinstall
This section tells you how to restore the information in the Flash to the factory default.
This is the same test that is run in production when the board is new. The erase process is
automatically run before the Flashing process starts.
Prior to getting to this section, follow the process and section 12.6 and do not hit any key
on the terminal.
1. As long as no key is pressed on the terminal, the following will be displayed:
reading boot.scr
679 bytes read
Running bootscript from mmc ...
## Executing script at 80200000
reading x-load.bin.ift
20392 bytes read
2. The x-load.bin.ift contains the XLoader file that will be flashed into the NAND in
the following steps. The following will be displayed:
***** Replacing x-load *****
Usage:
nand - NAND sub-system
HW ECC selected
NAND erase: device 0 offset 0x0, size 0x80000
Erasing at 0x0 -- 25% complete.
Erasing at 0x20000 -- 50% complete.
Erasing at 0x40000 -- 75% complete.
Erasing at 0x60000 -- 100% complete.
OK
NAND write: device 0 offset 0x0, size 0x20000
131072 bytes written: OK
NAND write: device 0 offset 0x20000, size 0x20000
131072 bytes written: OK
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NAND write: device 0 offset 0x40000, size 0x20000
131072 bytes written: OK
NAND write: device 0 offset 0x60000, size 0x20000
131072 bytes written: OK
3. The u-boot-f.bin contains the UBoot file that will be flashed into the NAND in the
following steps. The following will be displayed:
reading u-boot-f.bin
275928 bytes read
***** Replacing u-boot *****
Usage:
nand - NAND sub-system
SW ECC selected
NAND erase: device 0 offset 0x80000, size 0x160000
Erasing at 0x80000 -- 9% complete.
Erasing at 0xa0000 -- 18% complete.
Erasing at 0xc0000 -- 27% complete.
Erasing at 0xe0000 -- 36% complete.
Erasing at 0x100000 -- 45% complete.
Erasing at 0x120000 -- 54% complete.
Erasing at 0x140000 -- 63% complete.
Erasing at 0x160000 -- 72% complete.
Erasing at 0x180000 -- 81% complete.
Erasing at 0x1a0000 -- 90% complete.
Erasing at 0x1c0000 -- 100% complete.
OK
NAND write: device 0 offset 0x80000, size 0x160000
1441792 bytes written: OK
4. After the XLoader and UBot are flashed, the environment variables are erased to
insure proper booting of the Kernel image that I son the SD card. . The following
will be displayed:
***** Erasing environment settings *****
Usage:
nand - NAND sub-system
NAND erase: device 0 offset 0x160000, size 0x20000
Erasing at 0x160000 -- 100% complete.
OK
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5. At this point you can remove power to stop the Kernel from booting, or just let it
continue the Kernel boot process. For information on the Kernel booting process,
proceed to the next section.
12.8
Booting the Kernel
This section describes how to boot the kernel from the SD card. In order to complete this
section, you must have completed section 12.7 and do not hit any keys or remove power
after the NAND has been flashed.
1. After the NAND has been flashed, the normal.scr script is read form the SD card
and the first step after that is to load in the uImage.bin file into the SDRAM.
Beagle will print the following to the terminal:
***** Executing normal.scr *****
## Executing script at 80200000
reading uImage.bin
2578044 bytes read
***** Kernel: /dev/mmcblk0p1/uImage.bin *****
2. Then the root filesystem is read into SDRAM. The BeagleBoard will output the
following:
reading ramdisk.gz
7999649 bytes read
***** RootFS: /dev/mmcblk0p1/ramdisk.gz *****
1856680 bytes read
3. At this point, the booting process will start. The following will be printed to the
terminal:
## Booting kernel from Legacy Image at 80200000 ...
Image Name: Linux-2.6.28-omap1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2577980 Bytes = 2.5 MB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing
Linux.........................................................................................................................................................
............ done, booting the kernel.
Linux version 2.6.28-omap1 ([email protected]) (gcc version 4.2.1 (CodeSourcery Sourcery G++ Lite
2007q3-51)) #2 Thu Feb 19 12:45:34 IST 2009
CPU: ARMv7 Processor [411fc083] revision 3 (ARMv7), cr=10c5387f
CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
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Machine: OMAP3 Beagle Board
Memory policy: ECC disabled, Data cache writeback
OMAP3430 ES3.0
SRAM: Mapped pa 0x40200000 to va 0xd7000000 size: 0x100000
Reserving 15728640 bytes SDRAM for VRAM
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
Kernel command line: console=ttyS2,115200n8 console=tty0 root=/dev/ram0 rw ramdisk_size=32768
initrd=0x81600000,32M
Clocking rate (Crystal/DPLL/ARM core): 26.0/332/500 MHz
GPMC revision 5.0
IRQ: Found an INTC at 0xd8200000 (revision 4.0) with 96 interrupts
Total of 96 interrupts on 1 active controller
OMAP34xx GPIO hardware version 2.5
PID hash table entries: 1024 (order: 10, 4096 bytes)
OMAP clockevent source: GPTIMER12 at 32768 Hz
Console: colour dummy device 80x30
console [tty0] enabled
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 128MB 128MB = 256MB total
Memory: 206080KB available (4776K code, 425K data, 168K init)
Calibrating delay loop... 473.71 BogoMIPS (lpj=1851392)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
net_namespace: 532 bytes
regulator: core version 0.5
NET: Registered protocol family 16
Found NAND on CS0
Registering NAND on CS0
OMAP DMA hardware revision 4.0
USB: No board-specific platform config found
OMAP DSS rev 2.0
OMAP DISPC rev 3.0
OMAP VENC rev 2
OMAP DSI rev 1.0
i2c_omap i2c_omap.1: bus 1 rev3.12 at 2600 kHz
twl4030: PIH (irq 7) chaining IRQs 368..375
twl4030: power (irq 373) chaining IRQs 376..383
twl4030: gpio (irq 368) chaining IRQs 384..401
i2c_omap i2c_omap.3: bus 3 rev3.12 at 400 kHz
SCSI subsystem initialized
twl4030_usb twl4030_usb: Initialized TWL4030 USB module
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
musb_hdrc: version 6.0, musb-dma, otg (peripheral+host), debug=0
musb_hdrc: USB OTG mode controller at d80ab000 using DMA, IRQ 92
regulator: VMMC1: 1850 <--> 3150 mV normal standby
regulator: VDAC: 1800 mV normal standby
regulator: VUSB1V5: 1500 mV normal standby
regulator: VUSB1V8: 1800 mV normal standby
regulator: VUSB3V1: 3100 mV normal standby
regulator: VSIM: 1800 <--> 3000 mV normal standby
Bluetooth: Core ver 2.13
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
cfg80211: Using static regulatory domain info
cfg80211: Regulatory domain: US
(start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
(2402000 KHz - 2472000 KHz @ 40000 KHz), (600 mBi, 2700 mBm)
(5170000 KHz - 5190000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5190000 KHz - 5210000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5210000 KHz - 5230000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5230000 KHz - 5330000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5735000 KHz - 5835000 KHz @ 40000 KHz), (600 mBi, 3000 mBm)
cfg80211: Calling CRDA for country: US
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NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP reno registered
NET: Registered protocol family 1
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 32768K
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
JFFS2 version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
msgmni has been set to 467
alg: No test for stdrng (krng)
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver4 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0x4806a000 (irq = 72) is a ST16654
serial8250.0: ttyS1 at MMIO 0x4806c000 (irq = 73) is a ST16654
serial8250.0: ttyS2 at MMIO 0x49020000 (irq = 74) is a ST16654
console [ttyS2] enabled
brd: module loaded
loop: module loaded
usbcore: registered new interface driver asix
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver rndis_host
usbcore: registered new interface driver zd1211rw
usbcore: registered new interface driver rndis_wlan
usbcore: registered new interface driver zd1201
usbcore: registered new interface driver usb8xxx
usbcore: registered new interface driver rtl8187
usbcore: registered new interface driver rt2500usb
usbcore: registered new interface driver rt73usb
usbcore: registered new interface driver p54usb
i2c /dev entries driver
input: triton2-pwrbutton as /class/input/input0
triton2 power button driver initialized
Driver 'sd' needs updating - please use bus_type methods
Driver 'sr' needs updating - please use bus_type methods
omap2-nand driver initializing
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xba (Micron NAND 256MiB 1,8V 16-bit)
cmdlinepart partition parsing not available
Creating 5 MTD partitions on "omap2-nand":
0x00000000-0x00080000 : "X-Loader"
0x00080000-0x00260000 : "U-Boot"
0x00260000-0x00280000 : "U-Boot Env"
0x00280000-0x00680000 : "Kernel"
0x00680000-0x10000000 : "File System"
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-omap ehci-omap.0: OMAP-EHCI Host Controller
ehci-omap ehci-omap.0: new USB bus registered, assigned bus number 1
ehci-omap ehci-omap.0: irq 77, io mem 0x48064800
ehci-omap ehci-omap.0: USB 2.0 started, EHCI 1.00
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 3 ports detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
g_ether gadget: using random self ethernet address
g_ether gadget: using random host ethernet address
usb0: MAC 22:46:4b:c2:b0:fb
usb0: HOST MAC a2:b4:44:63:f6:ae
g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
g_ether gadget: g_ether ready
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musb_hdrc musb_hdrc: MUSB HDRC host driver
musb_hdrc musb_hdrc: new USB bus registered, assigned bus number 2
usb usb2: configuration #1 chosen from 1 choice
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
mice: PS/2 mouse device common for all mice
input: gpio-keys as /class/input/input1
twl4030_rtc twl4030_rtc: rtc core: registered twl4030_rtc as rtc0
twl4030_rtc twl4030_rtc: Power up reset detected.
twl4030_rtc twl4030_rtc: Enabling TWL4030-RTC.
OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
Bluetooth: HCI USB driver ver 2.10
usbcore: registered new interface driver hci_usb
Bluetooth: Broadcom Blutonium firmware driver ver 1.2
usbcore: registered new interface driver bcm203x
Bluetooth: Digianswer Bluetooth USB driver ver 0.10
usbcore: registered new interface driver bpa10x
Bluetooth: Generic Bluetooth SDIO driver ver 0.1
mmci-omap-hs mmci-omap-hs.0: Failed to get debounce clock
Registered led device: beagleboard::usr0
Registered led device: beagleboard::usr1
leds-gpio: probe of leds-gpio failed with error -22
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Advanced Linux Sound Architecture Driver Version 1.0.18rc3.
usbcore: registered new interface driver snd-usb-audio
ASoC version 0.13.2
OMAP3 Beagle SoC init
TWL4030 Audio Codec init
asoc: twl4030 <-> omap-mcbsp-dai-(link_id) mapping ok
ALSA device list:
#0: omap3beagle (twl4030)
oprofile: using arm/armv7
TCP cubic registered
NET: Registered protocol family 17
NET: Registered protocol family 15
Bluetooth: L2CAP ver 2.11
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO (Voice Link) ver 0.6
Bluetooth: SCO socket layer initialized
Bluetooth: RFCOMM socket layer initialized
Bluetooth: RFCOMM TTY layer initialized
Bluetooth: RFCOMM ver 1.10
Bluetooth: BNEP (Ethernet Emulation) ver 1.3
Bluetooth: BNEP filters: protocol multicast
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
ieee80211: 802.11 data/management/control stack, git-1.1.13
ieee80211: Copyright (C) 2004-2005 Intel Corporation <[email protected]>
ThumbEE CPU extension supported.
Power Management for TI OMAP3.
SmartReflex driver initialized
Disabling unused clock "sr2_fck"
Disabling unused clock "sr1_fck"
Disabling unused clock "mcbsp_fck"
Disabling unused clock "mcbsp_fck"
Disabling unused clock "mcbsp_fck"
Disabling unused clock "mcbsp_ick"
Disabling unused clock "mcbsp_ick"
Disabling unused clock "mcbsp_ick"
Disabling unused clock "gpt2_ick"
Disabling unused clock "gpt3_ick"
Disabling unused clock "gpt4_ick"
Disabling unused clock "gpt5_ick"
Disabling unused clock "gpt6_ick"
Disabling unused clock "gpt7_ick"
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Disabling unused clock "gpt8_ick"
Disabling unused clock "gpt9_ick"
Disabling unused clock "wdt3_ick"
Disabling unused clock "wdt3_fck"
Disabling unused clock "gpio2_dbck"
Disabling unused clock "gpio3_dbck"
Disabling unused clock "gpio4_dbck"
Disabling unused clock "gpio5_dbck"
Disabling unused clock "gpio6_dbck"
Disabling unused clock "gpt9_fck"
Disabling unused clock "gpt8_fck"
Disabling unused clock "gpt7_fck"
Disabling unused clock "gpt6_fck"
Disabling unused clock "gpt5_fck"
Disabling unused clock "gpt4_fck"
Disabling unused clock "gpt3_fck"
Disabling unused clock "gpt2_fck"
Disabling unused clock "gpt1_ick"
Disabling unused clock "wdt1_ick"
Disabling unused clock "wdt2_ick"
Disabling unused clock "wdt2_fck"
Disabling unused clock "gpio1_dbck"
Disabling unused clock "gpt1_fck"
Disabling unused clock "cam_ick"
Disabling unused clock "cam_mclk"
Disabling unused clock "des1_ick"
Disabling unused clock "sha11_ick"
Disabling unused clock "rng_ick"
Disabling unused clock "aes1_ick"
Disabling unused clock "ssi_ick"
Disabling unused clock "mailboxes_ick"
Disabling unused clock "mcbsp_ick"
Disabling unused clock "mcbsp_ick"
Disabling unused clock "gpt10_ick"
Disabling unused clock "gpt11_ick"
Disabling unused clock "i2c_ick"
Disabling unused clock "mcspi_ick"
Disabling unused clock "mcspi_ick"
Disabling unused clock "mcspi_ick"
Disabling unused clock "mcspi_ick"
Disabling unused clock "hdq_ick"
Disabling unused clock "mspro_ick"
Disabling unused clock "des2_ick"
Disabling unused clock "sha12_ick"
Disabling unused clock "aes2_ick"
Disabling unused clock "icr_ick"
Disabling unused clock "pka_ick"
Disabling unused clock "ssi_ssr_fck"
Disabling unused clock "hdq_fck"
Disabling unused clock "mcspi_fck"
Disabling unused clock "mcspi_fck"
Disabling unused clock "mcspi_fck"
Disabling unused clock "mcspi_fck"
Disabling unused clock "mcbsp_fck"
Disabling unused clock "mcbsp_fck"
Disabling unused clock "i2c_fck"
Disabling unused clock "mspro_fck"
Disabling unused clock "gpt11_fck"
Disabling unused clock "gpt10_fck"
Disabling unused clock "dpll4_m6x2_ck"
Disabling unused clock "dpll3_m3x2_ck"
Disabling unused clock "sys_clkout1"
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 1
Console: switching to colour frame buffer device 80x30
clock: clksel_round_rate_div: dpll4_m4_ck target_rate 48000000
clock: new_div = 9, new_rate = 48000000
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omap-dss DISPC error: dispc irq error status 4024
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4022
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4022
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: dispc irq error status 4022
omap-dss DISPC error: dispc irq error status 4000
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
omap-dss DISPC error: Excessive DISPC errors
Turning off lcd and digit
usb 2-1: new high speed USB device using musb_hdrc and address 2
twl4030_rtc twl4030_rtc: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
RAMDISK: Compressed image found at block 0
VFS: Mounted root (ext2 filesystem).
Freeing init memory: 168K
mmc0: new high speed SD card at address b368
mmcblk0: mmc0:b368 SD 970 MiB
mmcblk0: p1
usb 2-1: device v4146 pba01 is not supported
usb 2-1: configuration #1 chosen from 1 choice
scsi0 : SCSI emulation for USB Mass Storage devices
udevd version 124 started
uncorrectable error : <3>end_request: I/O error, dev mtdblock0, sector 0
uncorrectable error : <3>end_request: I/O error, dev mtdblock0, sector 8
uncorrectable error : <3>end_request: I/O error, dev mtdblock0, sector 16
uncorrectable error : <3>end_request: I/O error, dev mtdblock0, sector 24
uncorrectable error : <3>end_request: I/O error, dev mtdblock0, sector 0
scsi 0:0:0:0: Direct-Access Pretec 256MB Tiny
1.30 PQ: 0 ANSI: 2
sd 0:0:0:0: [sda] 512000 512-byte hardware sectors: (262 MB/250 MiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Assuming drive cache: write through
sd 0:0:0:0: [sda] 512000 512-byte hardware sectors: (262 MB/250 MiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Assuming drive cache: write through
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
sd 0:0:0:0: Attached scsi generic sg0 type 0
.-------.
|
|
.-.
| | |-----.-----.-----.| | .----..-----.-----.
|
| | __ | ---'| '--.| .-'| | |
| | | | | |--- || --'| | | ' | | | |
'---'---'--'--'--. |-----''----''--' '-----'-'-'-'
-' |
'---'
The Angstrom Distribution beagleboard ttyS2
Angstrom 2008.1-test-20090127 beagleboard ttyS2
beagleboard login:
4. Type root and hit <enter>. You now are in the Linux kernel.
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12.9
BeagleBoard System
Reference Manual
Revision C4
UBoot Tests
There are a series of tests that are run while in UBoot. This requires that the Beagle is not
in the Kernel mode, but the UBoot mode. The UBoot mode is entered by hitting a key
prior to the UBoot timeout reaching 10.
The following sections describe each test and how it is to be run.
12.9.1 EDID Test
This test will display the EDID (Enhanced Display ID) from the DVI-D monitor by using
the I2C interface on the DVI-D connector. The DVI-D connector must be connected to a
DVI-D compatible monitor in order to run this test..
1. Type the following commands:
OMAP3 beagleboard.org # ibus 2
OMAP3 beagleboard.org# imd 0x50 0 100
2. Something similar to the following will be displayed:
0000: 00 ff ff ff ff ff ff 00 10 ac 24 40 5a 39 41 41 [email protected]
0010: 1f 11 01 03 80 22 1b 78 ee ae a5 a6 54 4c 99 26 .....".x....TL.&
0020: 14 50 54 a5 4b 00 71 4f 81 80 01 01 01 01 01 01 .PT.K.qO........
0030: 01 01 01 01 01 01 30 2a 00 98 51 00 2a 40 30 70 ......0*..Q.*@0p
0040: 13 00 52 0e 11 00 00 1e 00 00 00 ff 00 50 4d 30 ..R..........PM0
0050: 36 31 37 38 32 41 41 39 5a 0a 00 00 00 fc 00 44 61782AA9Z......D
0060: 45 4c 4c 20 31 37 30 38 46 50 0a 20 00 00 00 fd ELL 1708FP. ....
0070: 00 38 4c 1e 51 0e 00 0a 20 20 20 20 20 20 00 36 .8L.Q...
.6
Note the words "DELL 1708FP" which is the ID of the monitor in this example. It will be
different based on the display manufacturer of your display. For more detailed
information on the full EDID format, refer to: http://en.wikipedia.org/wiki/EDID
12.9.2 LED Test
This test checks out the PWM and USER0/1 LEDs on the Beagle.
1. Type the following commands followed by the <ENTER> key and verify that the
correct results are seen on LEDs USR0 and USR1.
OMAP3 beagleboard.org # mw 0x49056090 0x00600000 [USR0 & USR1 OFF]
OMAP3 beagleboard.org # mw 0x49056094 0x00400000 [USR0 ON]
OMAP3 beagleboard.org # mw 0x49056094 0x00200000 [USR1 ON]
2.
Type the following commands and verify that the correct results are seen on PMU
LED.
OMAP3 beagleboard.org # ibus 0
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OMAP3 beagleboard.org # imm 0x4A 0xEE <ENTER>
000000ee: 22 ? 00
<ENTER>
[PMU LED OFF]
<CTRL-C> <CTRL-C>
OMAP3 beagleboard.org # imm 0x4A 0xEE
000000ee: 22 ? 22 <ENTER>
[PMU LED ON]
<CTRL-C> <CTRL-C>
12.9.3 DVI-D Test
This test checks the DVI-D interface for proper operation. It sends various colors to the
DVI-D monitor.
1. Type the following commands followed by the <ENTER> key and very the
correct results are seen.
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
mw 0x49058090 0x00000400 [DISPLAY TURNS OFF]
mw 0x49058094 0x00000400 [DISPLAY TURNS ON]
mw 0x80500000 07e007e0 7ffff [DISPLAY TURNS GREEN]
mw 0x80500000 001f001f 7ffff [DISPLAY TURNS BLUE]
mw 0x80500000 00000000 7ffff [DISPLAY TURNS BLACK]
mw 0x80500000 ffffffff 7ffff
[DISPLAY TURNS WHITEN]
mw 0x80500000 f800f800 7ffff [DISPLAY TURNS RED
12.10 Kernel Based Tests
The following tests require that the Kernel is loaded and that you have logged into the
Kernel. [See section 12.8]
12.10.1 DVI-D Test
This test plays a short video clip to the DVI-D monitor.
1. Type the following command:
[email protected]:~# mplayer /sample_video.avi
2. It will display a 320x240 video on the DVI screen. The video has been
downloaded from https://garage.maemo.org/download.php/54/269/2380/bug.avi
12.10.2 S-Video Test
1. Type the following command:
[email protected]:/mmc# svideo
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2. Type the following command to start the video:
[[email protected]:/mmc# mplayer /sample_video.avi
3. It will display a 320x240 video on the DVI screen. The video has been
downloaded from https://garage.maemo.org/download.php/54/269/2380/bug.avi
12.10.3 Audio Test
The audio test is divided into two test, one for audio in and one for audio out. Audio is
recorded into the audio in port and then played out the audio out port.
12.10.3.1
Audio In
1. Make Sure your player is running and Audio Line in is connected to board.
2. Make sure that you are in the MMC directory. If you are, proceed to step 4. If not,
then type the following command:
[email protected]:~# mkdir /mmc
[email protected]:~# mount -t vfat /dev/mmcblk0p1 /mmc
3. Change the directory by typing:
[email protected]:/mmc# cd /mmc
4. Type the following command:
[email protected]:/mmc# arecord -t wav -c 2 -r 44100 -f S16_LE -v /mmc/k
5. The following output is expected on the terminal window:
Recording WAVE '/mmc/k' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
Plug PCM: Hardware PCM card 0 'omap3beagle' device 0 subdevice 0
Its setup is:
stream
: CAPTURE
access
: RW_INTERLEAVED
format
: S16_LE
subformat : STD
channels : 2
rate
: 44100
exact rate : 44100 (44100/1)
msbits
: 16
buffer_size : 22052
period_size : 5513
period_time : 125011
tstamp_mode : NONE
period_step : 1
avail_min : 5513
period_event : 0
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start_threshold : 1
stop_threshold : 22052
silence_threshold: 0
silence_size : 0
boundary : 1445199872
6. When you want to stop the recording process just press <CONTROL+C>.
12.10.3.2
Audio Out
NOTE: It is expected that you have previously recorded an audio file to be played and
that you are still in the MMC directory.
1. Type the following command:
[email protected]:/mmc# aplay -t wav -c 2 -r 44100 -f S16_LE -v k
2. The recorded audio should be heard on the Speakers,
3. The following output is expected on terminal window:
Playing WAVE '/mmc/k' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
Plug PCM: Hardware PCM card 0 'omap3beagle' device 0 subdevice 0
Its setup is:
stream
: PLAYBACK
access
: RW_INTERLEAVED
format
: S16_LE
subformat : STD
channels : 2
rate
: 44100
exact rate : 44100 (44100/1)
msbits
: 16
buffer_size : 22052
period_size : 5513
period_time : 125011
tstamp_mode : NONE
period_step : 1
avail_min : 5513
period_event : 0
start_threshold : 22052
stop_threshold : 22052
silence_threshold: 0
silence_size : 0
boundary : 1445199872
7. To stop the audio playback just press <CONTROL+C>. If you choose, you can the let
the recorded audio play out. It will stop when it reaches the end of the recorded file.
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12.10.3.3
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Keyboard Test
This test runs on the OTG port in the Host mode. It requires that a Powered USB hub be
used, and that the Hub and device (Keyboard or mouse) be connected when the Linux OS
is booted. This section is broken down into two sections, one for the mouse and the other
for the keyboard.
NOTE: This test is run after the OS is booted with the Hub and Keyboard plugged
in.
1. Make sure that you are in the MMC directory. If you are, proceed to step 3. If not,
then type the following command:
[email protected]:~]# mkdir /mmc
[email protected]:~]# mount -t vfat /dev/mmcblk0p1 /mnt/mmc/cd /mnt/mmc/
2. Change the directory by typing:
[email protected]:~# cd /mmc
3. Type the following command:
[email protected]:/mmc]# evtest /dev/input/event1
4. Press a Key on USB Keyboard and look for a printout in the terminal window.
Example if "a" is pressed the following output is seen on Console:
Event: time 1657.754638, type 1 (Key), code 30 (A), value 1
Event: time 1657.754638, -------------- Report Sync -----------Event: time 1657.964599, type 1 (Key), code 30 (A), value 0
Event: time 1657.964599, -------------- Report Sync ------------
5. Press <CONTROL+C> to stop the test.
12.10.3.4
Mouse Test
NOTE: This test is run after the Kernel booted with the Hub and mouse plugged in.
1. Make sure that you are in the MMC directory. If you are, proceed to step 3. If not,
then type the following command:
[email protected]:~# mount -t vfat /dev/mmcblk0p1 /mmc/
2. Change the directory by typing:
[email protected]:~# cd /mnt/mmc/
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3. Type the following command:
[email protected]:/mmc# evtest /dev/input/event0
4. Press mouse button and look for a printout in the terminal window.
Example if Left button is pressed and released the following lines should get
displayed on console
Event: time 1871.724792, -------------- Report Sync -----------Event: time 1873.804687, type 1 (Key), code 272 (LeftBtn), value 1
Event: time 1873.804687, -------------- Report Sync -----------Event: time 1873.964660, type 1 (Key), code 272 (LeftBtn), value 0
Event: time 1873.964660, -------------- Report Sync -----------5. Moving the Mouse also results in Console messages
Event: time 1959.120635, -------------- Report Sync -----------Event: time 1959.130676, type 2 (Relative), code 0 (X), value -21
Event: time 1959.130676, -------------- Report Sync -----------Event: time 1959.140625, type 2 (Relative), code 0 (X), value -16
6. Press <CONTROL+C> to stop the test
12.10.3.5
USB EHCI Test
The following test will copy a file from the SD card to the USB EHCI port and back. The
file name can be changed to anything on the SD card. You must have a USB
ThumbDrive installed in the EHCI port at power up.
Start in the root directory and make sure the MMC directory is already mounted.
1. Type the following commands to set up the test:
[email protected]:~# mkdir /usb1
[email protected]:~# mount /dev/sda1 /usb1
2. Type the following commands to copy from the SD card to the USB Drive:
[email protected]:~# cp /mmc/u-boot.bin /usb1/test.bin
3. Type the following command to make sure the file was copied to the USB drive:
[email protected]:~# ls –al /usb1
The file should be listed in the directory.
4. Type the following command to copy the file from the USB drive to the SD card.
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[email protected]:~# cp /usb1/test.bin /mmc1/test.bin
5. Type the following command to copy to make sure the file was copied to the SD
card.
[email protected]:~# ls –al /mmc
The file should be listed in the directory. Larger files can be used to create a longer test if
desired.
13.0 Troubleshooting
This section will provide assistance in troubleshooting the BeagleBoard in the event there
are questions raised as to what the sate of the BeagleBoard is. This may be due to a HW
failure or the SW not initializing things properly during development. Also provided is a
section of know issues. Be sure and check with BeagleBoard.org for any updates.
For an up to date listing of common questions and their answers, please refer to
http://elinux.org/BeagleBoardFAQ
13.1
Access Points
This section covers the various access points where various signals and voltages can be
measured.
13.1.1 Voltage Points
Figure 81 shows the test points for the various voltages on BeagleBoard.
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Figure 78. BeagleBoard Voltage Access Points
Some of these voltages may not be present depending on the state of the TWL4030 as set
by the OMAP3530. Others may be at different voltage levels depending on the same
factor.
Table 40 provides the ranges of the voltages and the definition of the conditions as
applicable.
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Table 39.
Voltage
Min
VIO_1V8
VDD_SIM
VBUS_5V0
VOCORE_1V3
VBAT
VDAC_1V8
VDD_PLL1
VDD_PLL2
VDD2
3.3V
VMMC1 (3V)
VMMC1(1.8V)
1.78
1.78
4.9
1.15
4.1
1.78
1.78
1.78
1.15
3.28
2.9
1.78
Nom Max
1.8
1.8
5.0
1.2
4.2
1.8
1.8
1.8
1.2
3.3
3.0
1.8
1.81
1.81
5.2
1.4
4.3
1.81
1.81
1.81
1.25
3.32
3.1
1.81
Revision C4
Voltages
Conditions
From the host PC. May be lower or higher.
Can be set via SW. Voltage levels may vary.
3.0V at power up. Can be set to via SW.
13.1.2 Signal Access Points
Figure 82 shows the access points for various signals on BeagleBoard.
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Figure 79. BeagleBoard Signal Access Points
13.2
Troubleshooting Guide
Table 41 provides a list of possible failure modes and conditions and suggestions on how
to diagnose them and ultimate determine whether the HW is operational or not.
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Table 40.
Symptoms
Troubleshooting
Possible Problem
Verify that the Power LED is
on.
JTAG does not connect.
JTAG interface needs to be
reset
Incorrect serial cable
configuration.
UBoot does not start,
and no activity on the
RS232 monitor.
USB Host Connection
Issues via OTG.
13.3
Revision C4
Action
If off and running over USB,
the PC may have shut down
the voltage due to excessive
current as related to what it is
capable of providing. Remove
the USB cable and re insert.
If running on a DC supply
make sure that voltage is being
supplied.
Reset the BeagleBoard.
Verify orientation of the
RS232 flat cable
Check for the right null
modem cable.
If a 40V is displayed over the Make sure the SD/MMC card
serial cable, processor is
is installed all they way into
booting. Issue could be the
the connector.
SD/MMC card.
Make sure the card is
formatted correctly and that
the MLO file is the first file
written to the SD card.
Cheap USB Cable. OTG
Measure the voltage at the card
cables are typically not
to determine the voltage drop
designed for higher current.
across the cable. If it the level
The expect 100mA max.
is below 4.35V, the USB
power is not guaranteed to
work,
Serial Port Issues
We have had several serial port issues in the field caused by different issues. This section
attempts to provide a step by step process to identify what the issue is.
The main thing to keep in mind is that the PC and the BeagleBoard connectors are wired
the same. In order for them to talk, they must have a null modem cable to connect them.
The following sections provide steps to help identify the issue.
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For additional help on debugging serial issues, refer to the FAQ at
http://elinux.org/BeagleBoardFAQ#Serial_connection_.231
13.3.1 First Step
1. Review the wiring of your IDC10 to DB9M serial adapter. Only the TX, RX and
GND signals are used.
2. Make sure that the cable is plugged in correctly. The red stripe should be at the
bottom next to pin1 of P9. Some cables may have the flat cable extending away
from the BeagleBoard and others may be extending toward the middle of the
BeagleBoard. Figure 83 shows the proper orientation of the IDC serial cable.
Figure 80. BeagleBoard Serial Cable Orientation
3. You must have a Null Modem cable to connect to a PC. This results in the TX and
RX leads being swapped, connecting the TX of the BeagleBoard to RX of the PC
and RX of the BeagleBoard to TX of the PC. This cable also must be a female to
female cable as the connectors on the BeagleBoard and PC are male. Figure 84
shows the DB9 male connector and Figure 85 shows the Null Modem Cable.
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Figure 81. DB9 Male Connector
Figure 82. DB9 Null Modem Cable
4. If you have an ohmmeter, you can measure to see if the pins are swapped between
pins 2 and 3 from each end of the cable.
13.3.2 Second Step
A simple test to verify that the cables you are using are correct to create a loopback on
the cable. This checks the IDC cable and the null modem cable for connections.
1. Connect a wire across the TX and RX leads (Pins 2 and Pins 3) of the cable that
plugs into the BeagleBoard (IDC Cable). Figure 86 shows how this is done.
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Figure 83. Serial Cable Loopback
2. On your terminal start typing.
3. If the correct characters are echoed back, then the cables are in the proper
configuration. Note that this checks the electrical connection only. If the terminal
program is set wrong, then serial port will still not work.
13.3.3 Third Step
1. Make sure your terminal settings are correct.
o
o
o
o
o
BAUD RATE: 115200
DATA: 8 bit
PARITY: none
STOP: 1bit
FLOW CONTROL: none (Critical)
Make sure that the Flow Control is set to none.
13.3.4 Fourth Step
If everything checks out OK on the previous steps, then the issue may be on the
BeagleBoard. Follow the steps below to determine that state of the BeagleBoard.
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2.
3.
4.
5.
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Apply power to the board.
LED D5 should come on indicating that power is on.
LEDs USR0 and USR1 will come on once the board runs UBOOT.
By this time data should be printed to the terminal window.
Below are a couple of scenarios we have seen:
o BeagleBoard sends data but cannot receive data
o No data is sent at all
o No data is sent, but it can be received.
If any of these issues are present, then there is a chance that the serial driver has failed.
This is an issue with the level shifter, U9, on the board that we have seen fail after 48
hours of operation. The vast majority of boards with this issue are being screened out at
the manufacturing stages, but some of the early shipment of boards could still exhibit this
issue.
If this is the case, complete the RMA process at http://beagleboard.org/support/rma
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14.0 Known Issues
This section provides information on any know issues with the BeagleBoard HW and the
overall status. Table 42 provides a list of the know issues on the BeagleBoard. The Rev
C2 and C3 are provided for reference purposes.
Table 41.
Affected
Revision
Issue
C2 and
C3
Random
USB Host
Disconnect
s
C4
None
Known Issues
Description
There is a small number of boards that are
shown to have random disconnects when
transferring large amounts of data via the
EHCI USB Host port. This requires that the
board be power cycled to restore the USB
port. The issue is related to noise in a
specific frequency range locking up the USB
PHY. Some boards are noisier than others
based on the current draw of the various
components on the 1.8V rail.
Workaround
Some boards can be
fixed by placing a
22uf capacitor in
parallel with C97.
This fix does not
work for all boards.
Others have had
success by adding
the 22uF capacitor to
the expansion
header.
None
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15.0 PCB Component Locations
Figures 85 and Figure 86 contain the bottom and top side component locations of the
BeagleBoard.
Figure 84. BeagleBoard Top Side Components
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Figure 85. BeagleBoard Bottom Side Components
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16.0 Schematics
The following pages contain the PDF schematics for the BeagleBoard. This manual will
be periodically updated, but for the latest documentations be sure and check
BeagleBoard.org for the latest schematics.
OrCAD source files are provided for BeagleBoard on BeagleBoard.org at the following
link.
http://beagleboard.org/hardware/design
These design materials are *NOT SUPPORTED* and DO NOT constitute a reference
design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.
THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT
PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN
WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE
DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER
EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE
DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR
OR CORRECTION.
We mean it, these design materials may be totally unsuitable for any purposes.
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17.0 Bills of Material
The Bill of Material for the Beagle Board is provided at BeagleBoard.org at the following
location:
http://beagleboard.org/hardware/design
These design materials are *NOT SUPPORTED* and DO NOT constitute a reference
design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.
THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT
PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN
WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE
DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER
EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE
DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR
OR CORRECTION.
We mean it; these design materials may be totally unsuitable for any purposes.
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18.0 PCB Information
The following pages contain the PDF PCB layers for the BeagleBoard. Gerber files and
Allegro source files are available on BeagleBoard.org at the following address.
http://beagleboard.org/hardware/design
These design materials are *NOT SUPPORTED* and DO NOT constitute a reference
design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.
THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT
PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN
WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE
DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER
EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE
DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR
OR CORRECTION.
We mean it; these design materials may be totally unsuitable for any purposes.
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Top Silkscreen
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Layer 1
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Layer 2
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Layer 3
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Layer 4
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Layer 5
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Layer 6
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