Seco Q7-A29 User Manual

Q7-A29
Qseven® Rel. 2.0 Compliant Module with the
AMD Embedded G-series family SOCs
REVISION HISTORY
Revision
1.0
Date
Note
Rif
18th February 2016
First official release
SB
All rights reserved. All information contained in this manual is proprietary and confidential material of SECO S.r.l.
Unauthorised use, duplication, modification or disclosure of the information to a third-party by any means without prior consent of SECO S.r.l. is prohibited.
Every effort has been made to ensure the accuracy of this manual. However, SECO S.r.l. accepts no responsibility for any inaccuracies, errors or omissions herein.
SECO S.r.l. reserves the right to change precise specifications without prior notice to supply the best product possible.
Some of the information found in the BIOS SETUP Chapter has been extracted from the following copyrighted Insyde Software Corp. documents:
InsydeH2O Setup Utility - User Reference Guide
The above mentioned documents are copyright © 2008 Insyde Software Corp. All rights reserved.
For further information on this module or other SECO products, but also to get the required assistance for any and possible issues, please contact us using the
dedicated web form available at http://www.seco.com (registration required).
Our team is ready to assist you.
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INDEX
Chapter 1.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
INTRODUCTION .......................................................................................................................................................................... 5
Warranty ........................................................................................................................................................................................................................................ 6
Information and assistance ............................................................................................................................................................................................................. 7
RMA number request ..................................................................................................................................................................................................................... 7
Safety ............................................................................................................................................................................................................................................ 8
Electrostatic Discharges ................................................................................................................................................................................................................. 8
RoHS compliance .......................................................................................................................................................................................................................... 8
Terminology and definitions ............................................................................................................................................................................................................ 9
Reference specifications .............................................................................................................................................................................................................. 11
Chapter 2.
OVERVIEW ............................................................................................................................................................................... 13
2.1
2.2
2.3
Introduction .................................................................................................................................................................................................................................. 14
Technical Specifications ............................................................................................................................................................................................................... 15
Electrical Specifications ................................................................................................................................................................................................................ 16
2.3.1
Power Rails meanings .......................................................................................................................................................................................................... 16
2.3.2
Power Consumption ............................................................................................................................................................................................................ 16
2.4
Mechanical Specifications ............................................................................................................................................................................................................ 17
2.5
Block Diagram ............................................................................................................................................................................................................................. 18
Chapter 3.
3.1
3.2
CONNECTORS ......................................................................................................................................................................... 19
Introduction .................................................................................................................................................................................................................................. 20
Connectors description ................................................................................................................................................................................................................ 21
3.2.1
VGA Connector ................................................................................................................................................................................................................... 21
3.2.2
FAN Connector .................................................................................................................................................................................................................... 22
3.2.3
Qseven® Connector ............................................................................................................................................................................................................. 23
3.2.4
BOOT Strap Signals ............................................................................................................................................................................................................. 43
Chapter 4.
BIOS SETUP ............................................................................................................................................................................. 44
4.1
4.2
Introduction .................................................................................................................................................................................................................................. 45
Main setup menu ......................................................................................................................................................................................................................... 46
4.2.1
System Time / System Date ................................................................................................................................................................................................. 46
4.3
Advanced menu .......................................................................................................................................................................................................................... 47
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4.3.1
Boot configuration submenu ................................................................................................................................................................................................. 47
4.3.2
Peripheral configuration submenu ......................................................................................................................................................................................... 48
4.3.3
SATA configuration submenu ............................................................................................................................................................................................... 48
4.3.4
Video configuration submenu ............................................................................................................................................................................................... 49
4.3.5
Chipset configuration submenu ............................................................................................................................................................................................ 49
4.3.6
ACPI Table/features submenu .............................................................................................................................................................................................. 51
4.3.7
CPU related setting submenu ............................................................................................................................................................................................... 51
4.3.8
Memory configurations submenu .......................................................................................................................................................................................... 52
4.3.9
SDIO Configuration submenu ............................................................................................................................................................................................... 52
4.4
Security menu.............................................................................................................................................................................................................................. 53
4.5
Power menu ................................................................................................................................................................................................................................ 54
4.5.1
Advanced CPU control submenu ......................................................................................................................................................................................... 55
4.5.2
Thermal Zone configuration submenu ................................................................................................................................................................................... 55
4.5.3
Clocks And Voltages Optimizations submenu ....................................................................................................................................................................... 56
4.5.4
Watchdog Configuration submenu ....................................................................................................................................................................................... 56
4.6
Boot menu .................................................................................................................................................................................................................................. 57
4.6.1
Legacy submenu ................................................................................................................................................................................................................. 58
4.7
Exit menu .................................................................................................................................................................................................................................... 59
Chapter 5.
5.1
5.2
Appendices .............................................................................................................................................................................. 60
Thermal Design ............................................................................................................................................................................................................................ 61
Accessories ................................................................................................................................................................................................................................. 64
5.2.1
VGA Adapter module M908 ................................................................................................................................................................................................. 64
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Chapter 1.
Warranty
Information and assistance
RMA number request
Safety
Electrostatic Discharges
RoHS compliance
Terminology and definitions
Reference specifications
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1.1 Warranty
This product is subject to the Italian Law Decree 24/2002, acting European Directive 1999/44/CE on matters of sale and warranties to consumers.
The warranty on this product lasts 1 year.
Under the warranty period, the Supplier guarantees the buyer assistance and service for repairing, replacing or credit of the item, at the Supplier’s own discretion.
Shipping costs that apply to non-conforming items or items that need replacement are to be paid by the customer.
Items cannot be returned unless previously authorised by the supplier.
The authorisation is released after completing the specific form available on the web-site http://www.seco.com/en/prerma (RMA Online). The RMA authorisation
number must be put both on the packaging and on the documents shipped with the items, which must include all the accessories in their original packaging, with
no signs of damage to, or tampering with, any returned item.
The error analysis form identifying the fault type must be completed by the customer and must accompany the returned item.
If any of the above mentioned requirements for RMA is not satisfied, the item will be shipped back and the customer will have to pay any and all shipping costs.
Following a technical analysis, the supplier will verify if all the requirements for which a warranty service applies are met. If the warranty cannot be applied, the
Supplier will calculate the minimum cost of this initial analysis on the item and the repair costs. Costs for replaced components will be calculated separately.
Warning!
All changes or modifications to the equipment not explicitly approved by SECO S.r.l. could impair it and could void the warranty.
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1.2 Information and assistance
What do I have to do if the product is faulty?
SECO S.r.l. offers the following services:
SECO website: visit http://www.seco.com to receive the latest information on the product. In most cases it is possible to find useful information to solve the
problem.
SECO Sales Representative: the Sales Rep can help determine the exact cause of the problem and search the best solution.
SECO Help-Desk: contact SECO Technical Assistance. A technician is at disposal to understand the exact origin of the problem and suggest the correct
solution.
E-mail: [email protected]
Fax (+39) 0575 340434
Repair centre: it is possible to send the faulty product to the SECO Repair Centre. In this case, follow this procedure:
o Returned items must be accompanied by a RMA Number. Items sent without the RMA number will be not accepted.
o Returned items must be shipped in an appropriate package. SECO is not responsible for damages caused by accidental drop, improper usage, or
customer neglect.
Note: Please have the following information before asking for technical assistance:
-
Name and serial number of the product;
-
Description of Customer’s peripheral connections;
-
Description of Customer’s software (operating system, version, application software, etc.);
-
A complete description of the problem;
-
The exact words of every kind of error message encountered.
1.3 RMA number request
To request a RMA number, please visit SECO’s web-site. On the home page, please select “RMA Online” and follow the procedure described.
A RMA Number will be released within 1 working day (only for on-line RMA requests).
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1.4 Safety
The Q7-A29 module uses only extremely-low voltages.
While handling the board, please use extreme caution to avoid any kind of risk or damages to electronic components.
Always switch the power off, and unplug the power supply unit, before handling the board and/or connecting cables or other boards.
Avoid using metallic components - like paper clips, screws and similar - near the board when connected to a power supply, to avoid
short circuits due to unwanted contacts with other board components.
If the board has become wet, never connect it to any external power supply unit or battery.
Check carefully that all cables are correctly connected and that they are not damaged.
1.5 Electrostatic Discharges
The Q7-A29 module, like any other electronic product, is an electrostatic sensitive device: high voltages caused by static electricity could damage some or all the
devices and/or components on-board.
Whenever handling a Q7-A29 module, ground yourself through an anti-static wrist strap. Placement of the board on an anti-static
surface is also highly recommended.
1.6 RoHS compliance
The Q7-A29 module is designed using RoHS compliant components and is manufactured on a lead-free production line. It is therefore fully RoHS compliant.
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1.7 Terminology and definitions
ACPI
AHCI
API
BIOS
CEC
CRT
DDC
DDR
DDR3
DP
DVI
eDP
EHCI
FFC/FPC
GBE
Gbps
GND
GPI/O
HD Audio
HDMI
I2C Bus
JTAG
LPC Bus
LVDS
MAC
Advanced Configuration and Power Interface, an open industrial standard for the board’s devices configuration and power management
Advanced Host Controller Interface, a standard which defines the operation modes of SATA interface
Application Program Interface, a set of commands and functions that can be used by programmers for writing software for specific Operating
Systems
Basic Input / Output System, the Firmware Interface that initializes the board before the OS starts loading
Consumer Electronics Control, an HDMI feature which allows controlling more devices connected together by using only one remote control
Cathode Ray Tube. Initially used to indicate a type of monitor, this acronym has been used over time to indicate the analog video interface used
to drive them.
Display Data Channel, a kind of I2C interface for digital communication between displays and graphics processing units (GPU)
Double Data Rate, a typology of memory devices which transfer data both on the rising and on the falling edge of the clock
DDR, 3rd generation
Display Port, a type of digital video display interface
Digital Visual interface, a type of digital video display interface
embedded Display Port, a type of digital video display interface specifically developed for the internal connections between boards and displays
Enhanced Host Controller interface, a high-speed controller for USB ports, able to support USB2.0 standard
Flexible Flat Cable / Flat Panel Cable
Gigabit Ethernet
Gigabits per second
Ground
General purpose Input/Output
High Definition Audio, most recent standard for hardware codecs developed by Intel® in 2004 for higher audio quality
High Definition Multimedia Interface, a digital audio and video interface
Inter-Integrated Circuit Bus, a simple serial bus consisting only of data and clock line, with multi-master capability
Joint Test Action Group, common name of IEEE1149.1 standard for testing printed circuit boards and integrated circuits through the Debug port
Low Pin Count Bus, a low speed interface based on a very restricted number of signals, deemed to management of legacy peripherals
Low Voltage Differential Signalling, a standard for transferring data at very high speed using inexpensive twisted pair copper cables, usually used
for video applications
Medium Access Controller, the hardware implementing the Data Link Layer of ISO/OSI-7 model for communication systems
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Mbps
N.A.
N.C.
OpenCL
OpenGL
OS
PCI-e
PSU
PWM
PWR
PXE
SATA
SD
SDHC
SDIO
SM Bus
SPI
TBM
TMDS
TTL
UEFI
UHCI
USB
V_REF
VGA
xHCI
Megabits per second
Not Applicable
Not Connected
Open Computing Language, a software library based on C99 programming language, conceived explicitly to realise parallel computing using
Graphics Processing Units (GPU)
Open Graphics Library, an Open Source API dedicated to 2D and 3D graphics
Operating System
Peripheral Component Interface Express
Power Supply Unit
Pulse Width Modulation
Power
Preboot Execution Environment, a way to perform the boot from the network ignoring local data storage devices and/or the installed OS
Serial Advance Technology Attachment, a differential half duplex serial interface for Hard Disks
Secure Digital, a memory card type
Secure Digital Host Controller
Secure Digital Input/Output, an evolution of the SD standard that allows the use of the same SD interface to drive different Input/Output devices,
like cameras, GPS, Tuners and so on
System Management Bus, a subset of the I2C bus dedicated to communication with devices for system management, like a smart battery and
other power supply-related devices
Serial Peripheral Interface, a 4-Wire synchronous full-duplex serial interface which is composed of a master and one or more slaves, individually
enabled through a Chip Select line
To be measured
Transition-Minimized Differential Signaling, a method for transmitting high speed serial data, normally used on DVI and HDMI interfaces
Transistor-transistor Logic
Unified Extensible Firmware Interface, a specification defining the interface between the OS and the board’s firmware. It is meant to replace the
original BIOS interface
Unified Host Controller Interface, Host Controller for USB 1.0 and 1.1 ports
Universal Serial Bus
Voltage reference Pin
Video Graphics Array, an analog computer display standard, commonly referred to also as CRT
eXtensible Host Controller Interface, Host controller for USB 3.0 ports, which can also manage USB 2.0 and USB1.1 ports
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1.8 Reference specifications
Here below it is a list of applicable industry specifications and reference documents.
Reference
Link
ACPI
http://www.acpi.info
AHCI
http://www.intel.com/content/www/us/en/io/serial-ata/ahci.html
DDC
http://www.vesa.org
DP, eDP
http://www.vesa.org
EHCI
http://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-specification.html
Gigabit Ethernet
http://standards.ieee.org/about/get/802/802.3.html
HD Audio
http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/high-definition-audio-specification.pdf
HDMI
http://www.hdmi.org/index.aspx
I2C
http://www.nxp.com/documents/other/UM10204_v5.pdf
LPC Bus
http://www.intel.com/design/chipsets/industry/lpc.htm
LVDS
http://www.ti.com/ww/en/analog/interface/lvds.shtml
http://www.ti.com/lit/ml/snla187/snla187.pdf
OpenCL
http://www.khronos.org/opencl
OpenGL
http://www.opengl.org
PCI Express
http://www.pcisig.com/specifications/pciexpress
®
Qseven specifications
http://www.sget.org/uploads/media/Qseven-Spec_2.0_SGET.pdf
SATA
https://www.sata-io.org
SD Card Association
https://www.sdcard.org/home
SM Bus
http://www.smbus.org/specs
TMDS
http://www.siliconimage.com/technologies/tmds
USB 2.0 and USB OTG
http://www.usb.org/developers/docs/usb_20_070113.zip
USB 3.0
http://www.usb.org/developers/docs/usb_30_spec_070113.zip
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xHCI
http://www.intel.com/content/www/us/en/io/universal-serial-bus/extensible-host-controler-interface-usb-xhci.html?wapkw=xhci
AMD GX SOC
http://www.amd.com/US/PRODUCTS/EMBEDDED/PROCESSORS/Pages/g-series.aspx
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Chapter 2.
Introduction
Technical Specifications
Electrical Specifications
Mechanical Specifications
Block Diagram
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2.1 Introduction
Q7-A29 is a CPU module, in Qseven® format, based on the AMD Embedded G-Series System on Chip (SOC), a family of Dual/Quad Core x86 CPU with
integrated discrete-class GPU and I/O controller on a single Chip.
This single chip solution includes the memory controller, which gives support for up to 8GB of DDR3 Single Channel ECC Memory soldered onboard.
Graphic section is embedded in the SOC; which offers an embedded AMD HD Radeon GPU, able to support dual independent displays using native LVDS /
embedded Display Port, CRT or HDMI/ Display Port interfaces. Any combinations of these video interfaces are supported. GPUs embedded in the SOC also
support DirectX® 11.1, OpenGL® rel.4.2 and OpenCL rel. 1.2.
The board can offer one optional SATA Flash Drive, directly accessible like any standard Hard Disk (SATA Flash Drive is alternative to second SATA Channel on
Qseven® connector).
This high level of integration allows an extremely reduced consumption of spaces, that is essential for boards with sizes so reduced as for Qseven® boards, which
offers all functionalities of standard PC boards in just 70x70mm.
Interface to the board comes through the single card edge connector, as defined by Qseven® specifications Rel. 2.0: on this connector, signals are available for
Gigabit Ethernet, SD interface, up to 2 x SATA Channels, one USB 3.0 Host port, six USB 2.0 Host ports, optional 24-bit Single/Dual Channel LVDS, HDMI or
Display Port interface, up to 4 x PCI-Express x 1 lanes, HD Audio interface, I2C, SPI and SM Bus, and other features, like optional UART and SPI interfaces.
Interfacing to the board comes through a single card edge connector, as defined by Qseven® specifications Rel.2.0, where are carried out all interfaces previously
described (except CRT interface, which has a dedicated connector). For external interfacing to standard devices, a carrier board with a 230-pin MXM connector is
needed. This board will implement all the routing of the interface signals to external standard connectors, as well as integration of other peripherals/devices not
already included in Q7-A29 CPU module.
Some module’s configurations are also available in industrial temperature range.
Please refer to following chapter for a complete list of all peripherals integrated and characteristics.
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2.2 Technical Specifications
SOC
AMD GX-415GA, Quad Core @ 1.5GHz, 2MB L2 Cache, TDP 15W
AMD GX-217GA, Dual Core @ 1.65GHz, 1MB L2 Cache, TDP 15W
AMD GX-210HA, Dual Core @ 1.0GHz, 1MB L2 Cache, TDP 9W
AMD GX-210JA, Dual Core @ 1.0GHz, 1MB L2 Cache, TDP 6W
AMD GX-411GA, Quad Core @1.1GHz, 2MB L2 Cache, TDP 15W, industrial
grade temperature
AMD GX-209HA, Dual Core @ 1.0GHz, 1MB L2 Cache, TDP 9W, industrial
grade temperature
Memory
up to 8GB DDR3 1600MHz Single-Channel with ECC soldered onboard (*)
(1333MHz memory with GX-210HA;1066MHz memory with GX-411GA,
GX-210JA and GX-209HA)
* Please notice that total amount of 8GB would be usable only with 64-bit OS. Total
amount of memory available with a 32-bit OS depends on the OS itself (it will be less
than 4GB, however).
Graphics
Embedded AMD HD RADEON GPUs
HD8330E @500MHz (GX-415GA), HD8280E @450MHz (GX-217GA)
HD8210E @300MHz (GX-210HA, GX-411GA)
HD8180 @225MHz (GX-210JA, GX-209HA)
Dual independent display support
Supports DirectX® 11.1, OpenGL rel. 4.2 and OpenCL rel. 1.2
Video Interfaces
HDMI or Display Port interface
Embedded Display Port or 18/24 bit single/dual channel LVDS interface
Additional VGA interface (optional external adapter is required)
Video Resolutions
HDMI:
Up to 1920x1200 @ 60Hz
Display Port, eDP:
Up to 2560x1600 @ 60Hz
CRT:
Up to 2048x1536 @ 60Hz
Optional LVDS interface:
Up to 1920x1200 @ 60 Hz
USB
1 x USB3.0 Host port
6 x USB2.0 Host port
Mass Storage
Up to 2 x external S-ATA channels
SD interface
Optional SATA Flash Drive soldered onboard
Networking
Gigabit Ethernet interface
Audio
HD Audio interface
PCI Express
Up to 4 x PCI-e x1 groupable lanes
3 x PCI-e x1 lanes with GX-210JA
Serial Ports
1 x Optional Serial port (TTL interface)
Other Interfaces
I2C / LPC / SM Bus
Thermal / FAN management
Optional UART and SPI
Power Management Signals
Power supply voltage: +5VDC ± 5%
Operating temperature:
0°C ÷ +60°C (commercial version) ***
-40°C ÷ +85°C (industrial version)
Dimensions: 70 x70 mm (2.76” x 2.76”)
Supported Operative Systems
Microsoft® Windows 7 32/64 bit / Microsoft® Windows 8 32/64 bit
Microsoft® Windows 8.1 32/64 bit / Microsoft® WES7 32/64 bit
Linux 32/64 bit
*** Temperatures indicated are the minimum and maximum temperature that
the heatspreader / heatsink can reach in any of its parts. This means that it is
customer’s responsibility to use any passive cooling solution along with an
application-dependent cooling system, capable to ensure that the
heatspreader / heatsink temperature remains in the range above indicated.
Please also check paragraph 5.1.
2.3 Electrical Specifications
According to Qseven® specifications, Q7-A29 board needs to be supplied only with an external +5VDC power supply.
5 Volts standby voltage needs to be supplied for working in ATX mode.
For Real Time Clock working and CMOS memory data retention, it is also needed a backup battery voltage. All these voltages are supplied directly through card
edge fingers (see connector’s pinout).
All remaining voltages needed for board’s working are generated internally from +5V_S power rail.
2.3.1 Power Rails meanings
In all the tables contained in this manual, Power rails are named with the following meaning:
_S: Switched voltages, i.e. power rails that are active only when the board is in ACPI’s S0 (Working) state. Examples: +3.3V_S, +5V_S.
_A: Always-on voltages, i.e. power rails that are active both in ACPI’s S0 (Working), S3 (Standby) and S5 (Soft Off) state. Examples: +5V_A, +3.3V_A.
_U: unswitched ACPI S3 voltages, i.e. power rails that are active both in ACPI’s S0 (Working) and S3 (Standby) state. Examples: +1.5V_U
2.3.2 Power Consumption
TBM
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2.4 Mechanical Specifications
According to Qseven® specifications, board dimensions are: 70 x 70 mm (2.76” x 2.76”).
Printed circuit of the board is made of twelve layers, some of them are ground planes, for
disturbance rejection.
The MXM connector accommodates various connector heights for different carrier board
applications needs. Qseven® specification suggests two connector heights, 7.8mm and
7.5mm, but it is also possible to use different connector heights, also remaining compliant to
the standard.
When using different connector heights, please consider that, according to Qseven ®
specifications, components placed on bottom side of Q7-A29 will have a maximum height of
2.2mm ± 0.1. This value must be kept in mind when choosing the MXM connector’s height,
if it is necessary to place components on the carrier board in the zone below the Qseven®
module.
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2.5 Block Diagram
DDR3L System
Memory
Power management
Watchdog
External FAN interface
STMicroelectronics
STM32F100R4
microcontroller
FACTORY
ALTERNATIVES
Embedded SATA
Drive
SATA #1
SATA #0
SPI
Internal FAN
connector
I2C
SD interface
DDR3L ECC
Memory
DDR3L System
Memory
AMD
G-Series
SOC
LPC Bus
HD Audio
USB 3.0 port
DDI1
DDI0
USB 2.0 ports
HDMI or DP
VGA connector
GFX PCI-e
GPP PCI-e
USB #6
eDP
eDP-to-LVDS
bridge
LVDS
FACTORY
ALTERNATIVES
FACTORY
ALTERNATIVES
SM bus
Intel® Ethernet
Controller I210-IT
USB to UART
bridge
Gigabit Ethernet
PCI-e interface
UART
SPI
Power section
FACTORY
OPTION
+5V_S, +5V_A
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Chapter 3.
Introduction
Connectors description
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3.1 Introduction
According to Qseven® specifications, all interfaces to the board are available through a single card edge connector. In addition, a CRT FFC/FPC connector card
slot is present on the left side of the board to take advantage of the native CRT interface of AMD G-Series SOCs. Moreover, an additional FAN connector has been
placed on the right side of the board, in order to allow an easier connection of active heatsinks to the module.
TOP SIDE
VGA
connector
BOTTOM SIDE
Ext. FAN
Connector
Card edge golden
finger, pin 228
Card edge golden
finger, pin 2
Card edge golden
finger, pin 1
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Card edge golden
finger, pin 229
20
3.2 Connectors description
3.2.1 VGA Connector
VGA Connector - CN1
Pin
Signal
Pin
Signal
1
CRT_RED
7
CRT_HSYNC
2
GND
8
CRT_VSYNC
3
CRT_GREEN
9
+5V_S
4
GND
10
CRT_DDC_CLK
5
CRT_BLUE
11
CRT_DDC_DATA
6
GND
12
GND
Qseven® specifications Rel. 2.0 define an area, on the PCB, that can be
used to place optional I/O connectors of any kind.
For this reason, on Q7-A29 board, there is an additional connector,
which carries out VGA interface coming out from AMD HD Radeon
GPUs embedded in the SOCs.
Considering that these GPUs are able to manage up to two independent displays, it is
possible this way to have many possible combinations of display, using this VGA connector,
LVDS/eDP interface and HDMI / DP interfaces available on Qseven® golden card edge
connector (type of interfaces available depends on the module’s configuration purchased).
VGA connector is an FFC/FPC connector, top contacts, type HIROSE FH12A-12S-0.5SH(55),
with pinout shown in the table on the left. This connector mates with 0.5mm pitch 12-poles
FFC cables.
Here following the VGA signals’ description:
CRT_RED: Embedded AMD HD RADEON GPU’s internal DAC’s Red Signal video output. A 150Ω pull-down resistor is placed on the line.
CRT_GREEN: Embedded AMD HD RADEON GPU’s internal DAC’s Green Signal video output. A 150Ω pull-down resistor is placed on the line.
CRT_BLUE: Embedded AMD HD RADEON GPU’s internal DAC’s Blue Signal video output. A 150Ω pull-down resistor is placed on the line.
CRT_HSYNC: Embedded AMD HD RADEON GPU’s internal DAC’s Horizontal Synchronization output signal. A 1kΩ pull-up resistor is placed on the line.
CRT_VSYNC: Embedded AMD HD RADEON GPU’s internal DAC’s Vertical Synchronization output signal..
CRT_DDC_CLK: Embedded AMD HD RADEON GPU’s internal DAC’s DDC Clock line for VGA displays detection. Output signal, electrical level +3.3V_S, 4k53Ω
pull-up resistor.
CRT_DDC_DATA: Embedded AMD HD RADEON GPU’s internal DAC’s DDC Clock line for VGA displays detection. Bidirectional signal, electrical level +3.3V_S,
4k53Ω pull-up resistor.
Please be aware that for the connection to external VGA displays, adapter circuitry is needed; it will provide for ESD protection, voltage level shifting for DDC,
filtering for reduction of noise and EMI, and so on.
Optionally, SECO can provide a dedicated VGA adapter, able to carry out the signals coming out from connector CN1 to a standard DB-15 HD VGA connector.
The adapter is also provided with necessary FFC cable, length 20cm. Please check chapter 5.2.1 for further details.
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21
3.2.2 FAN Connector
FAN Connector - CN2
Depending on the usage model of Q7-A29, for critical applications/environments on the module itself it is available a 3-pin
dedicated connector for an external +5VDC FAN.
Pin
Signal
1
GND
FAN Connector is a 3-pin single line SMT connector, type MOLEX 53261-0371 or equivalent, with pinout shown in
the table on the left.
2
FAN_POWER
Mating connector: MOLEX 51021-0300 receptacle with MOLEX 50079-8000 female crimp terminals.
3
FAN_TACHO_IN
Please be aware that the use of an external fan depends strongly on customer’s application/installation.
Please refer to chapter 5.1 for considerations about thermal dissipation.
FAN_POWER: +5V_S derived power rail for FAN, managed by the embedded microcontroller via PWM signal.
FAN_TACHO_IN: tachometric input from the fan to the embedded microcontroller, +3.3V_S electrical level signal with 10kΩ pull-up resistor.
Q7-A29
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22
3.2.3 Qseven® Connector
According to Qseven® specifications, all interface signals are reported on the card edge connector, which is a 230-pin Card Edge that can be inserted into
standard 230 pin MXM connectors, as described in Qseven® specifications.
Not all signals contemplated in Qseven® standard are implemented on MXM connector, due to the functionalities really implemented on Q7-A29 CPU module.
Therefore, please refer to the following table for a list of effective signals reported on MXM connector.
For accurate signals description, please consult the following paragraphs.
NOTE: Even pins are available on top side of CPU board; odd pins are available on bottom side of CPU board. Please refer to board photos.
Qseven® Golden Card Edge Connector - CN4
BOTTOM SIDE
SIGNAL GROUP
Type
Pin name
PWR
GBE
TOP SIDE
Pin nr.
Pin nr.
Pin name
Type
GND
1
I/O
GBE_MDI3-
GBE
I/O
GBE
O
GBE
SIGNAL GROUP
2
GND
PWR
3
4
GBE_MDI2-
I/O
GBE
GBE_MDI3+
5
6
GBE_MDI2+
I/O
GBE
GBE_LINK100#
7
8
GBE_LINK1000#
O
GBE
I/O
GBE_MDI1-
9
10
GBE_MDI0-
I/O
GBE
GBE
I/O
GBE_MDI1+
11
12
GBE_MDI0+
I/O
GBE
GBE
O
GBE_LINK#
13
14
GBE_ACT#
O
GBE
N.A.
N.C.
15
16
SUS_S5#
O
PWR_MGMT
PWR_MGMT
I
WAKE#
17
18
SUS_S3#
O
PWR_MGMT
PWR_MGMT
O
SUS_STAT#
19
20
PWRBTN#
I
PWR_MGMT
PWR_MGMT
I
SLP_BTN#
21
22
LID_BTN#
I
PWR_MGMT
PWR
GND
23
24
GND
PWR
PWR
GND
25
26
PWGIN
I
PWR_MGMT
PWR_MGMT
I
BATLOW#
27
28
RSTBTN#
I
PWR_MGMT
SATA
O
SATA0_TX+
29
30
SATA1_TX+
O
SATA
SATA
O
SATA0_TX-
31
32
SATA1_TX-
O
SATA
SATA
O
SATA_ACT#
33
34
GND
PWR
SATA
I
SATA0_RX+
35
36
SATA1_RX+
O
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23
SATA
I
SATA0_RX-
37
38
SATA1_RX-
O
SATA
PWR
GND
39
40
GND
PWR
N.A.
N.C.
41
42
SDIO_CLK
O
SDIO
SDIO
I
SDIO_CD#
43
44
SDIO_LED
O
SDIO
SDIO
I/O
SDIO_CMD
45
46
SDIO_WP
I
SDIO
SDIO
O
SDIO_PWR#
47
48
SDIO_DAT1
I/O
SDIO
SDIO
I/O
SDIO_DAT0
49
50
SDIO_DAT3
I/O
SDIO
SDIO
I/O
SDIO_DAT2
51
52
N.C.
N.A.
N.A.
N.C.
53
54
N.C.
N.A.
N.A.
N.C.
55
56
USB_DRIVE_VBUS
O
PWR
GND
57
58
GND
PWR
AUDIO
O
HDA_SYNC
59
60
SMB_CLK
I/O
MISC
AUDIO
O
HDA_RST#
61
62
SMB_DAT
I/O
MISC
AUDIO
O
HDA_BCLK
63
64
SMB_ALERT#
I/O
MISC
AUDIO
I
HDA_SDI
65
66
GP0_I2C_CLK
I/O
MISC
AUDIO
O
HDA_SDO
67
68
GP0_I2C_DAT
I/O
MISC
MISC
I
THRM#
69
70
WDTRIG#
I
MISC
N.A.
N.C.
71
72
WDOUT
O
MISC
PWR
GND
73
74
GND
PWR
USB
I/O
USB_SSTX0-
75
76
USB_SSRX0-
I/O
USB
USB
I/O
USB_SSTX0+
77
78
USB_SSRX0+
I/O
USB
USB
I
USB_6_7_OC#
79
80
USB_4_5_OC#
I
USB
USB
I/O
USB_P5-
81
82
USB_P4-
I/O
USB
USB
I/O
USB_P5+
83
84
USB_P4+
I/O
USB
USB
I
USB_2_3_OC#
85
86
USB_0_1_OC#
I
USB
USB
I/O
USB_P3-
87
88
USB_P2-
I/O
USB
USB
I/O
USB_P3+
89
90
USB_P2+
I/O
USB
USB
N.A.
N.C.
91
92
N.C.
N.A.
USB
I/O
USB_P1-
93
94
USB_P0-
I/O
USB
USB
I/O
USB_P1+
95
96
USB_P0+
I/O
USB
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24
PWR
GND
97
98
GND
PWR
LVDS/eDP
O
LVDS_A0+/eDP0_TX0+
99
100
LVDS_B0+
O
LVDS
LVDS/eDP
O
LVDS_A0-/eDP0_TX0-
101
102
LVDS_B0-
O
LVDS
LVDS/eDP
O
LVDS_A1+/eDP0_TX1+
103
104
LVDS_B1+
O
LVDS
LVDS/eDP
O
LVDS_A1-/eDP0_TX1-
105
106
LVDS_B1-
O
LVDS
LVDS/eDP
O
LVDS_A2+/eDP0_TX2+
107
108
LVDS_B2+
O
LVDS
LVDS/eDP
O
LVDS_A2-/eDP0_TX2-
109
110
LVDS_B2-
O
LVDS
LVDS/eDP
O
LVDS_PPEN
111
112
LVDS_BLEN
O
LVDS/eDP
LVDS/eDP
O
LVDS_A3+/eDP0_TX3+
113
114
LVDS_B3+
O
LVDS
LVDS/eDP
O
LVDS_A3-/eDP0_TX3-
115
116
LVDS_B3-
O
LVDS
PWR
GND
117
118
GND
PWR
LVDS/eDP
O
LVDS_A_CLK+/eDP0_AUX+
119
120
LVDS_B_CLK+
O
LVDS
LVDS/eDP
O
LVDS_A_CLK-/eDP0_AUX-
121
122
LVDS_B_CLK-
O
LVDS
LVDS/eDP
O
LVDS_BLT_CTRL
123
124
HDMI_CEC
I/O
HDMI
LVDS
O
LVDS_DID_DAT
125
126
eDP0_HPD#
I
eDP
LVDS
O
LVDS_DID_CLK
127
128
N.C.
N.A.
N.A.
N.C.
129
130
N.C.
N.A.
HDMI/DP
O
TMDS_CLK+/DP_LANE3+
131
132
N.C.
N.A.
HDMI/DP
O
TMDS_CLK-/DP_LANE3-
133
134
N.C.
N.A.
PWR
GND
135
136
GND
PWR
HDMI/DP
O
TMDS_TX1+/DP_LANE1+
137
138
DP_AUX+
I/O
DP
HDMI/DP
O
TMDS_TX1-/DP_LANE1-
139
140
DP_AUX-
I/O
DP
PWR
GND
141
142
GND
PWR
HDMI/DP
O
TMDS_TX0+/DP_LANE2+
143
144
N.C.
N.A.
HDMI/DP
O
TMDS_TX0-/DP_LANE2-
145
146
N.C.
N.A.
PWR
GND
147
148
GND
PWR
HDMI/DP
O
TMDS_TX2+/DP_LANE0+
149
150
HDMI_CTRL_DAT
I/O
HDMI
HDMI/DP
O
TMDS_TX2-/DP_LANE0-
151
152
HDMI_CTRL_CLK
I/O
HDMI
HDMI/DP
I
DP_HDMI_HPD#
153
154
DP_HPD#
I
DP
PCI-E
O
PCIE_CLK_REF+
155
156
PCIE_WAKE#
I
PCI-E
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25
PCI-E
O
PCIE_CLK_REF-
157
158
PCIE_RST#
O
PCI-E
PWR
GND
159
160
GND
PWR
PCI-E
O
PCIE3_TX+
161
162
PCIE3_RX+
I
PCI-E
PCI-E
O
PCIE3_TX-
163
164
PCIE3_RX-
I
PCI-E
PWR
GND
165
166
GND
PCI-E
O
PCIE2_TX+
167
168
PCIE2_RX+
PCI-E
O
PCIE2_TX-
169
170
UART
O
UART0_TX
171
172
PCI-E
O
PCIE1_TX+
173
PCI-E
O
PCIE1_TX-
UART
I
PCI-E
PCI-E
PWR
I
PCI-E
PCIE2_RX-
I
PCI-E
UART0_RTS#
O
UART
174
PCIE1_RX+
I
PCI-E
175
176
PCIE1_RX-
I
PCI-E
UART0_RX
177
178
UART0_CTS#
I
UART
O
PCIE0_TX+
179
180
PCIE0_RX+
I
PCI-E
O
PCIE0_TX-
181
182
PCIE0_RX-
I
PCI-E
PWR
GND
183
184
GND
PWR
LPC
I/O
LPC_AD0
185
186
LPC_AD1
I/O
LPC
LPC
I/O
LPC_AD2
187
188
LPC_AD3
I/O
LPC
LPC
O
LPC_CLK
189
190
LPC_FRAME#
O
LPC
LPC
I/O
SERIRQ
191
192
LPC_LDRQ#
I
LPC
PWR
VCC_RTC
193
194
SPKR
O
MISC
FAN_TACHOIN
195
196
FAN_PWMOUT
O
MISC
MISC
I
PWR
GND
197
198
GND
PWR
SPI
O
SPI_MOSI
199
200
SPI_CS0#
O
SPI
I
SPI_MISO
201
202
N.C.
N.A.
SPI
O
SPI_CLK
203
204
MFG_NC4
N.A.
PWR
+5V_A
205
206
+5V_A
PWR
MFG
N.A.
MFG_NC0
207
208
MFG_NC2
N.A.
MFG
MFG
N.A.
MFG_NC1
209
210
MFG_NC3
N.A.
MFG
PWR
+5V_S
211
212
+5V_S
PWR
PWR
+5V_S
213
214
+5V_S
PWR
PWR
+5V_S
215
216
+5V_S
PWR
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
SPI
MFG
26
PWR
+5V_S
217
218
+5V_S
PWR
PWR
+5V_S
219
220
+5V_S
PWR
PWR
+5V_S
221
222
+5V_S
PWR
PWR
+5V_S
223
224
+5V_S
PWR
PWR
+5V_S
225
226
+5V_S
PWR
PWR
+5V_S
227
228
+5V_S
PWR
PWR
+5V_S
229
230
+5V_S
PWR
3.2.3.1 PCI Express interface signals
Q7-A29 can offer externally up to four PCI Express lanes Gen 2 (5Gbps), which are managed by AMD G-series SOC.
Here following the signals involved in PCI express management:
PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair.
PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair.
PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair.
PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair.
PCIE2_TX+/PCIE2_TX-: PCI Express lane #2, Transmitting Output Differential pair.
PCIE2_RX+/PCIE2_RX-: PCI Express lane #2, Receiving Input Differential pair.
PCIE3_TX+/PCIE3_TX-: PCI Express lane #3, Transmitting Output Differential pair. This lane is not externally available with GX-210JA SOC.
PCIE3_RX+/PCIE3_RX-: PCI Express lane #3, Receiving Input Differential pair. This lane is not externally available with GX-210JA SOC.
PCIE_CLK_REF+/ PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair. Please consider that only one reference clock is supplied, while there are three
different PCI express lanes. When more than one PCI Express lane is used on the carrier board, then a zero-delay buffer must be used to replicate the reference
clock to all the devices.
PCIE_WAKE#: Qseven® Module’s Wake Input, it must be externally driven by devices requiring waking up the system. Since it is an Active-Low Input to the
module, this signal is pulled-up with a 100kΩ resistor to +3.3V_A power rail. On the carrier board, connect it directly to the PCI-e/miniPCI-e connector’s WAKE#
signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier Board.
PCIE_RST#: Reset Signal that is sent from Qseven® Module to any PCI-e device available on the carrier board. It is a 3.3V active-low signal; it can be used directly
to drive externally a single RESET Signal. In case it is necessary to supply Reset signal to multiple devices, then a buffer on the carrier board could be necessary.
PCI-e lanes can be managed as 4 PCI-e x1 ports, 1 PCI-e x2 + 2 PCI-e x1, 2 PCI-e x 2 or 1 PCI-e x4 ports. PCI-e x4 grouping is not possible using GX-210JA
SOC.
Q7-A29
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27
3.2.3.2 UART interface signals
According to newest Qseven® Rel. 2.0 specifications, Q7-A29 can offer one UART interface, which is derived from AMD G-series SOC’s USB port #6 by using an
USB-to-Serial bridge (Cypress CY7C65215). The UART interface is derived by device’s serial port #0.
Here following the signals related to UART interface:
UART0_TX: UART Interface, Serial data Transmit (output) line, 3.3V_S electrical level.
UART0_RX: UART Interface, Serial data Receive (input) line, 3.3V_S electrical level.
UART0_RTS#: UART Interface, Handshake signal, Request to Send (output) line, 3.3V_S electrical level.
UART0_CTS#: UART Interface, Handshake signal, Clear to Send (Input) line, 3.3V_S electrical level.
Please consider that interface is at TTL electrical level; therefore, please evaluate well the typical scenario of application. If it is not explicitly necessary to interface
directly at TTL level, for connection to standard serial ports commonly available (like those offered by common PCs, for example) it is mandatory to include an RS232 transceiver on the carrier board.
The schematic here on the right shows an
example of implementation of RS-232
transceiver on the Carrier board.
+3.3V_S
1
C4
CC-100nF/25V
UART0_TX
UART0_RTS#
UART0_RX
UART0_CTS#
3
11
10
12
9
4
C5
CC-100nF/25V
5
U1
C1+
C1T1IN
T2IN
R1OUT
R2OUT
C2+
C2SP3232ECY
VCC
GND
T1OUT
T2OUT
R1IN
R2IN
V+
V-
P1
10
16
15
C1
CC-100nF/25V
14
7
13
8
RS232_TX
RS232_RTS#
RS232_RX
RS232_CTS#
5
9
4
8
RS232_CTS#
7
RS232_RTS#
3
2
6
1
2
11
C2
CC-100nF/25V
6
DB9 CONNECTOR
C3
CC-100nF/25V
All schematics (henceforth also referred to as material) contained in this manual are provided by SECO S.r.l. for the sole purpose of supporting the
customers’ internal development activities.
The schematics are provided “AS IS”. SECO makes no representation regarding the suitability of this material for any purpose or activity and disclaims all
warranties and conditions with regard to said material, including but not limited to, all expressed or implied warranties and conditions of merchantability,
suitability for a specific purpose, title and non-infringement of any third party intellectual property rights.
The customer acknowledges and agrees to the conditions set forth that these schematics are provided only as an example and that he will conduct an
independent analysis and exercise judgment in the use of any and all material. SECO declines all and any liability for use of this or any other material in
the customers’ product design.
Q7-A29
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28
3.2.3.3 Gigabit Ethernet signals
The Gigabit Ethernet interface is realised, on Q7-A29 module, using an Intel® I210 Gigabit Ethernet controller, which is interfaced to AMD G-series SOC through
CN1
GFX PCI-express lane #0. Since G-series SOC GX-210JA doesn’t have GFX PCI-express lanes, in that case the
D2
R1
R-249
GBE_LINK1000#
G
Y
Gigabit Ethernet controller is interfaced to GPP PCI-Express lane #3, which will not be externally available anymore. GBE_LINK100#
D1
R2
R-249
Here following the signals involved in PCI express management:
GBE_MDI0+/GBE_MDI0-: Media Dependent Interface (MDI) I/O differential pair #0.
2
GBE_CTREF
9
GBE_MDI0+
1
GBE_MDI0-
GBE_MDI1+/GBE_MDI1-: Media Dependent Interface (MDI) I/O differential pair #1.
GBE_MDI2+/GBE_MDI2-: Media Dependent Interface (MDI) I/O differential pair #2, only used for 1Gbps Ethernet
mode (not for 10/100Mbps modes).
GBE_MDI3+/GBE_MDI3-: Media Dependent Interface (MDI) I/O differential pair #3, only used for 1Gbps Ethernet
mode (not for 10/100Mbps modes).
GBE_ACT#: Ethernet controller activity indicator, Active Low Output signal, electrical level +3.3V_A.
GBE_LINK#: Ethernet controller link indicator, Active Low Output signal, electrical level +3.3V_A.
GBE_LINK100#: Ethernet controller 100Mbps link indicator, Active Low Output signal, electrical level +3.3V_A.
75
10
0.1uF
2
7
GBE_MDI1+
3
75
8
GBE_MDI1-
0.1uF
6
5
GBE_MDI2+
4
75
6
GBE_MDI2-
0.1uF
5
3
GBE_MDI3+
7
75
4
GBE_MDI3-
0.1uF
8
1
GBE_ACT#
GBE_LINK#
R3
R-249
D4
R4
R-249
D3
G
Y
1000pF
2kV
SHIELD GND
LPJG16314A4NL
GBE_LINK1000#: Ethernet controller 1Gbps link indicator, Active Low Output signal, electrical level +3.3V_A.
These signals can be connected, on the Carrier board, directly to an RJ-45 connector, in order to complete the
Ethernet interface.
Please notice that if just a FastEthernet (i.e. 10/100 Mbps) is needed, then only MDI0 and MDI1 differential lanes are necessary.
Unused differential pairs and signals can be left unconnected. Please look to the schematic on the left as an example of implementation of Gigabit Ethernet
connector. In this example, it is also present GBE_CTREF signal connected on pin #2 of the RJ-45 connector. Intel® I210 Gigabit Ethernet controller, however,
doesn’t need the analog powered centre tap, therefore the signal GBE_CTREF is not available on Qseven® golden card edge connector
Q7-A29
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29
3.2.3.4 S-ATA signals
AMD G-series SOC offers two S-ATA interfaces. One of them is always carried out on the golden card edge connector. The other interface is optional; it is
available only in case the module purchased doesn’t have an embedded SATA Flash Drive onboard.
The interfaces are SATA III, with support of 1.5Gbps, 3.0 Gbps and 6.0 Gbps data rates (the GX-210JA SOC supports only SATA II, therefore with that device the
maximum data rate supported is 3.0 Gbps)
Here following the signals related to SATA interface:
SATA0_TX+/SATA0_TX-: Serial ATA Channel #0 Transmit differential pair
SATA0_RX+/SATA0_RX-: Serial ATA Channel #0 Receive differential pair
SATA1_TX+/SATA1_TX-: Serial ATA Channel #1 Transmit differential pair (optional, factory alternative to embedded SSD).
SATA1_RX+/SATA1_RX-: Serial ATA Channel #1 Receive differential pair (optional, factory alternative to embedded SSD).
SATA_ACT#: Serial ATA Activity Led. Active low output signal at +3.3V_S voltage.
10nF AC series decoupling capacitors are placed on each line of SATA differential pairs.
On the carrier board, these signals can be carried out directly to the SATA connector.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
30
3.2.3.5 USB interface signals
AMD G-Series SOC is able to manage up to 10 USB ports, which are managed by three EHCI/OHCI controllers (for USB 2.0 and USB 1.1 functionalities) and one
xHCI controller (which manages two ports able to work in USB 3.0 / USB 2.0 and USB 1.1 mode).
It is possible to enable / disable single OHCI, EHCI and XHCI controllers via BIOS settings (please check par. 4.3.2 for further details).
Here following the signals related to USB interfaces.
USB_P0+/USB_P0-: Universal Serial Bus Port #0 differential pair.
USB_P1+/USB_P1-: Universal Serial Bus Port #1 differential pair.
USB_P2+/USB_P2-: Universal Serial Bus Port #2 differential pair.
USB_P3+/USB_P3-: Universal Serial Bus Port #3 differential pair.
USB_P4+/USB_P4-: Universal Serial Bus Port #4 differential pair.
USB_P5+/USB_P5-: Universal Serial Bus Port #5 differential pair.
USB_SSRX0+/USB_SSRX0-: USB Super Speed Port #0 receive differential pair; it is managed by xHCI controller.
USB_SSTX0+/USB_SSTX0-: USB Super Speed Port #0 transmit differential pair; it is managed by xHCI controller.
USB_0_1_OC#: USB Over Current Detect Input. Active Low Input signal, electrical level +3.3V_A with 10kΩ pull-up resistor. This pin has to be used for
overcurrent detection of USB Port#0 and #1 of Q7-A29 module.
USB_2_3_OC#: USB Over Current Detect Input. Active Low Input signal, electrical level +3.3V_A with 10kΩ pull-up resistor. This pin has to be used for
overcurrent detection of USB Ports #2 and #3 of Q7-A29 module.
USB_4_5_OC#: USB Over Current Detect Input. Active Low Input signal, electrical level +3.3V_A with 10kΩ pull-up resistor. This pin has to be used for
overcurrent detection of USB Port #4 and/or #5 of Q7-A29 module.
USB_6_7_OC#: USB Over Current Detect Input. Active Low Input signal, electrical level +3.3V_A with 10kΩ pull-up resistor. This pin has to be used for
overcurrent detection of USB Superspeed Port of Q7-A29 module.
USB_DRIVE_VBUS: USB Power Enable pin for USB Port 1, output signal, electrical level +3.3V_A with 1kΩ pull-up resistor. This pin can be used to enable the power rail
output for USB port #1, necessary when used on a carrier board implementing the OTG functionality.
Please notice that for correct management of Overcurrent signals, power distribution switches are needed on the carrier board.
For EMI/ESD protection, common mode chokes on USB data lines, and clamping diodes on USB data and voltage lines, are also needed.
The schematics in the following page show an example of implementation on the Carrier Board. In there, all USB ports are carried out to standard USB 2.0 and
USB 3.0 Type A receptacles.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
31
1
3
4
6
+5V_A
EN2
OC2
OUT1
BLM18PG121SN1
VCC_USB4
CN9
OUT2
6
L42
BLM18PG121SN1
USB_P5-
C52
CC-47uF/10V
C53
CC-100nF
USB_P5+
1
5
L43
2
6
3
7
DLW21HN900SQ2
4
3
8
USB_2_3_OC#
4
5
+5V_A
EN2
OC2
OUT1
L45
BLM18PG121SN1
6
L46
BLM18PG121SN1
6
3
7
DLW21HN900SQ2
4
8
L48
USB_P3-
DLW21HN900SQ2
C60
CC-100nF
USB_P3+
C61
CC-100nF
USB_0_1_OC#
Jum per USB ports supplied:
placed:
JP1
Only in S0 state
JP2
In S0 and S3 states
JP3
Alw ays
U11
IN
OUT
C62
CC-10uF/10V
4
3
ILIM
FAULT
EN
GND
6
L49
BLM18PG121SN1
VCC_USB1
USB 2.0_single
5
R8
R-52K3/1
2
C63
USB_P1CC-47uF/10V
USB_P1+
2
L50
3
DLW21HN900SQ2
+5V_A D16
5
+5V_A
4
IP4221CZ6-S
C65
CC-100nF
USB_6_7_OC#
U12
IN
OUT
C64
CC-10uF/10V
4
3
ILIM
FAULT
EN
GND
6
L51
1
2
4
5
1
L52
6
C66
USB_P0CC-47uF/10V
USB_P0+
L53
R9
R-0
692121030100
5
R10
R-28K7/1
2
10
9
7
6
5
VCC_USB0
2
D15
IP4283CZ10
CN12
BLM18PG121SN1
+5V_A
5
IP4221CZ6-S
1
3
4
6
2
D14
1
3
4
6
1
TPS2552DBV
1
G4
CN11
1
8
2
JUMPER
+5V_A
G3
Q3
2N7002
3
1
JP10
2
G2
2
JUMPER
5
L47
G1
1
JP9
USB_P2+
1
G2
2
JUMPER
C58
CC-100nF
Dual_USB connector
VCC_USB2
G1
SUS_S3#
1
JP8
C54
CC-100nF
USB_P4+
2
7
DLW21HN900SQ2
USB_SSRX0USB_SSRX0+
3
DLW21HN900SQ2
8
4
L54
9
DLW21HN900SQ2
G1
TPS2552DBV
USB_SSTX0USB_SSTX0+
G2
SUS_S5#
USB_P2C59
CC-47uF/10V
R7
R-10K
R6
R-10K
USB_P4-
DLW21HN900SQ2
VCC_USB3
CN10
OUT2
L44
C57
CC-47uF/10V
7
1
9
+5V_A
EN1
OC1
U10
AP2142AMP
GND
IN
Exp.Pad
2
C56
CC-10uF/10V
8
G1
+5V_A
C55
CC-100nF
Dual_USB connector
VCC_USB5
G4
EN1
OC1
L41
1
9
4
5
2
C51
CC-47uF/10V
7
G3
USB_4_5_OC#
U9
AP2142AMP
GND
IN
Exp.Pad
3
8
5
IP4221CZ6-S
G2
C50
CC-10uF/10V
2
C49
CC-100nF
+5V_A
D13
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
32
3.2.3.6 SD interface signals
AMD G-Series SOCs embed a SD 3.0 compliant Host controller, supporting SDHC and SDXC UHS-I cards (speed transfer up to 104 MB/S with 4-bit SD cards).
The SD port is externally accessible through the golden card edge connector, and can work in 1-bit and 4-bit mode.
Signals involved with SD interface are the following:
SDIO_PWR#: SD power enable. Active Low Output signal, electrical level +3.3V_S. This signal can be used on the Carrier board to enable the power line for the
SD card.
SDIO_CD#: Card Detect Input. Active Low Signal, electrical level +3.3V_S. This signal must be externally pulled low to signal that a SD Card Device is present.
SDIO_CLK: Clock Line (output).
SDIO_CMD: Command/Response line. Bidirectional signal, electrical level +3.3V_S, used to send command from the Host to the connected card, and to send the
response from the card to the Host.
SDIO_WP: Write Protect input, electrical level +3.3V_S. It is used to communicate the status of Write Protect switch of the external SD card. Since microSD cards
don’t manage this signal, it is important that, when designing carrier boards with microSD slots, this signal must be tied to GND, otherwise the OS will always
consider the card as protected from writing.
SDIO_LED: Transfer indicator output, electrical level +3.3V_S. This signal can be used to drive an external LED to indicate when there are data transferring on the
bus.
SDIO_DAT[0÷3]: SD Card data bus. SDIO_DAT0 signal is used for all communication modes. SDIO_DAT[1÷3] signals are required for 4-bit communication mode.
3.2.3.7 Audio interface signals
Q7-A29 module supports HD audio format, thanks to native support offered by the chipset to this audio codec standard.
Here following the signals related to HD Audio interface:
HDA_SYNC: HD Audio Serial Bus Synchronization. 48kHz fixed rate output from the module to the Carrier board, electrical level +3.3V_S.
HDA_RST#: HD Audio Codec Reset. Active low signal, output from the module to the Carrier board, electrical level +3.3V_S.
HDA_BCLK: HD Audio Serial Bit Clock signal. 24MHz serial data clock, output from the module to the Carrier board, electrical level +3.3V_S.
HDA_SDO: HD Audio Serial Data Out signal. Output from the module to the Carrier board, electrical level +3.3V_S.
HDA_SDI: HD Audio Serial Data In signal. Input to the module from the Carrier board, electrical level +3.3V_S.
All these signals have to be connected, on the Carrier Board, to an HD Audio Codec. Please refer to the chosen Codec’s Reference Design Guide for correct
implementation of audio section on the carrier board.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
33
3.2.3.8 LVDS Flat Panel signals
The AMD G-Series SOCs offer two multi-purpose Digital Display Interfaces, which allow the implementation of HDMI/DVI, Display Port (DP) or embedded Display
Port (eDP).
The LVDS interface, which is frequently used in many application fields, is not directly supported by the SOC.
For this reason, considering that LVDS interface can be multiplexed on the same pin with the eDP interface, on Q7-A29 module can be implemented an eDP to
LVDS bridge (NXP PTN3460), which allow the implementation of a Dual Channel LVDS, with a maximum supported resolution of 1920x1200 @ 60Hx (dual channel
mode). Such an interface is derived from AMD G-Series SOCs’ Digital Display Interface #0.
Please remember that LVDS interface is not native for G-Series SOC’s, it is derived from an optional eDP-to-LVDS bridge. Depending on the
factory option purchased, on the same pins will be available LVDS or eDP interface.
When placing an order of Q7-A29 module, please take care of specifying if LVDS interface or eDP is needed.
Here following the signals related to LVDS management:
LVDS_A0+/LVDS_A0-: LVDS Primary Channel #0 differential data pair #0.
LVDS_A1+/LVDS_A1-: LVDS Primary Channel #0 differential data pair #1.
LVDS_A2+/LVDS_A2-: LVDS Primary Channel #0 differential data pair #2.
LVDS_A3+/LVDS_A3-: LVDS Primary Channel #0 differential data pair #3.
LVDS_A_CLK+/LVDS_A_CLK-: LVDS Primary Channel #0 differential clock.
LVDS_B0+/LVDS_B0-: LVDS Secondary Channel #0 differential data pair #0.
LVDS_B1+/LVDS_B1-: LVDS Secondary Channel #0 differential data pair #1.
LVDS_B2+/LVDS_B2-: LVDS Secondary Channel #0 differential data pair #2.
LVDS_B3+/LVDS_B3-: LVDS Secondary Channel #0 differential data pair #3.
LVDS_B_CLK+/LVDS_B_CLK-: LVDS Secondary Channel differential Clock
LVDS_PPEN: +3.3V_S electrical level Output, Panel Power Enable signal. It can be used to turn On/Off the connected LVDS display.
LVDS_BLEN: +3.3V_S electrical level Output, Panel Backlight Enable signal. It can be used to turn On/Off the backlight’s lamps of connected LVDS display.
LVDS_BLT_CTRL: this signal can be used to adjust the panel backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations.
LVDS_DID_DAT: DisplayID DDC Data line for LVDS flat Panel detection. Bidirectional signal, electrical level +3.3V_S with a 4k53Ω pull-up resistor.
LVDS_DID_CLK: DisplayID DDC Clock line for LVDS flat Panel detection. Bidirectional signal, electrical level +3.3V_S with a 4k53Ω pull-up resistor.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
34
3.2.3.9 Embedded Display Port (eDP) signals
As described in the previous paragraph, the AMD G-Series SOCs offer two multi-purpose Digital Display Interfaces, which allow the implementation of HDMI/DVI,
Display Port (DP) or embedded Display Port (eDP).
When the board is not configured with the eDP-to-LVDS bridge, the on the golden edge card connector is available an eDP interface (derived from AMD G-Series
SOCs Digital Display Interface #0), which allows supporting displays with a resolution up to 2560 x 1600 @ 60Hz.
Here following the signals related to eDP management:
eDP0_TX0+/eDP0_TX0-: eDP channel differential data pair #0.
eDP0_TX1+/eDP0_TX1-: eDP channel differential data pair #1.
eDP0_TX2+/eDP0_TX2-: eDP channel differential data pair #2.
eDP0_TX3+/eDP0_TX3-: eDP channel differential data pair #3.
eDP0_AUX+/eDP0_AUX-: eDP channel differential auxiliary channel.
eDP0_HPD#: eDP channel Hot Plug Detect. Active Low Signal, +3.3V_S electrical level input with 100kΩ pull-up resistor.
LVDS_PPEN: +3.3V_S electrical level output, Panel Power Enable signal. It can be used to turn On/Off the connected display.
LVDS_BLEN: +3.3V_S electrical level output, Panel Backlight Enable signal. It can be used to turn On/Off the backlight’s lamps of connected display.
LVDS_BLT_CTRL: this signal can be used to adjust the panel backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
35
3.2.3.10 HDMI interface signals
As told in the previous paragraph, the AMD G-Series SOCs offer two Digital Display Interfaces, configurable to work in HDMI/DVI/DP/eDP modes.
Please be aware that the board is factory configured to have HDMI or Display Port interface.
If the board purchased is in HDMI configuration, then voltage level shifters on the carrier board are not necessary (they can also interfere with
regular working of the board). When placing an order of Q7-A29 modules, please take care of specifying if they must have HDMI interface or DP.
Digital Display Interface #1, in particular, is used to implemented HDMI or Display Port interface.
Signals involved in HDMI management are the following:
TMDS_CLK+/TMDS_CLK-: TMDS differential Clock.
TMDS_TX0+/TMDS_TX0-: TMDS differential pair #0.
TMDS_TX1+/TMDS_TX1-: TMDS differential pair #1.
TMDS_TX2+/TMDS_TX2-: TMDS differential pair #2.
HDMI_CTRL_DAT: DDC Data line for HDMI panel. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor. Also used as a strap signal for the Q7A29 module (please check par. 3.2.4 for further details).
HDMI_CTRL_CLK: DDC Clock line for HDMI panel. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor.
HDMI_CEC: HDMI Consumer Electronics Control (CEC) Line. Bidirectional signal, electrical level +3.3V_A with a 27kΩ pull-up resistor. According to Qseven®
specifications, the signal is, in reality, a General Purpose 1_wire bus interface, that can be used for implementation of HDMI_CEC. Real usage of this signal
depends on Q7-A29 dedicated API libraries.
DP_HDMI_HPD#: Hot Plug Detect Input signal. +3.3V_S electrical level signal, active low with 100kΩ pull-up resistor. Please consider that HDMI specification
assume that the Hot Plug signal is active high, and at +5V_S level. An inverting voltage level shifter is therefore needed on the Carrier board to ensure the working
of HDMI port.
Please be aware that it is not necessary to implement voltage level shifter for TMDS differential pairs on the Carrier board, but such level shifters are still necessary
on Control data/Clock signals, as well as for Hot Plug Detect signal.
Voltage clamping diodes are also highly recommended on all signal lines for ESD suppression.
Please refer to the following schematics as an example of implementation of HDMI connection + voltage level shifters on the carrier board.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
36
1
2
4
5
+3.3V_A
1PS79SB40
Q1
2N7002
10
9
7
6
1
2
4
5
D3
IP4283CZ10-TBA
10
9
7
6
3
8
3
CN1
8
D1
D2
IP4283CZ10-TBA
TYPE A
R2
R-27K
TMDS_TX2+
TMDS_TX2TMDS_TX1+
HDMI_CEC
TMDS_TX1TMDS_TX0+
+5V_HDMI
+3.3V_S
TMDS_TX0TMDS_CLK+
Q2
2N7002
R3
R-2K2
L1
HDMI_CTRL_CLK
TMDS_CLKBLM18PG121SN1
HDMI_DDC_CLK_L
HDMI_DDC_DATA_L
+5V_HDMI
5
+3.3V_S
Q3
2N7002
C1
CC-100nF
R4
R-2K2
+5V_HDMI
D5
1
3
4
6
2
+3.3V_S
L2
BLM18PG121SN1
+5V_HDMI
+5V_S
DP_HDMI_HPD#
4
2
SL04 L3
BLM18PG121SN1
C2
CC-1uF
20
21
22
23
WHDM-19D5L1BF3U4W
U1
SN74LVC1G14DBVR
3
D7
GND
R5
R-1K
5
IP4221CZ6-S
HDMI_CTRL_DAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
R6
R-20K
C3
CC-100nF
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
37
3.2.3.11 DP interface signals
As told in the previous paragraph, the AMD G-Series SOCs offer two Digital Display Interfaces, configurable to work in HDMI/DVI/DP/eDP modes.
Digital Display Interface #1, in particular, is used to implemented HDMI or Display Port interface.
If the board purchased is in DP configuration, then this interface works as a multimode Display Port: this means that it is possible to use it directly for the
connection of Display Port compatible monitors or converted to HDMI/DVI or LVDS interfaces on the carrier board or on the external connector (by using an
adapter).
In this configuration, the following signals will be available on Qseven® golden card edge connector:
DP_LANE3+/DP_LANE3-: Display Port differential pair #3.
DP_LANE2+/DP_LANE2-: Display Port differential pair #2.
DP_LANE1+/DP_LANE1-: Display Port differential pair #1.
DP_LANE0+/DP_LANE0-: Display Port differential pair #0.
DP_AUX+/DP_AUX-: Display Port auxiliary channel differential pair.
DP_HPD#. DisplayPort Hot Plug Detect Input signal. +3.3V_S electrical level signal, active low with 100kΩ pull-up resistor. Please consider that DisplayPort
specification assume that the Hot Plug signal is an active high signal, therefore an inverter is needed on the Carrier board to ensure the working of DP port.
This signal was present on Qseven specifications until rev. 1.2, while it has been deleted with Qseven specifications rev. 2.0, since the Hot Plug signal for Display
Port had been merged with the HPD signal for HDMI. Qseven® specification Errata Sheet for version 2.0, published by SGET consortium, reintroduced this signal
for compatibility with Qseven® modules Rel 1.20 compliant. On Q7-A29 module, this signal is electrically tied to DP_HDMI_HPD#.
Please refer to the following schematics as an example of implementation of DisplayPort connection on the carrier board, which will allow the use of external
adapters for the conversion to HDMI/DVI.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
38
G1
G2
CN1
DP_LANE0+
+3.3V_S
DP_LANE0DP_LANE1+
DP_LANE1DP_LANE2+
R1
DP_LANE2R-100K DP_LANE3+
DP_LANE3-
5
+3.3V_S
U1
SN74LVC1G14DBVR
CC-100nF
C2
CC-100nF
C3 CC-100nF
C4
CC-100nF
C5 CC-100nF
C6
CC-100nF
C7 CC-100nF
C8
CC-100nF
CC-100nF
C10 CC-100nF
2 DP_AUX-
4
3
DP_HPD#
C9
DP_AUX+
C1
R2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R3
R-100K
R-100K
G3
G4
WDPE-20F5L1BU
+3.3V_S
F1
nanoSMDC075F
L1
BLM18PG121SN1
C11
CC-100nF
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
C12
CC-100nF
39
3.2.3.12 LPC interface signals
According to Qseven® specifications rel. 2.0, on the golden card edge connector there are 8 pins that are used for implementation of Low Pin Count (LPC) Bus
interface.
Warning: Although the Qseven® specification states that pins 185-192 can be used for the implementation of the LPC bus or as 8 GPIOs, this
option is intended only for the manufacturers of the modules who are free to choose the option they deem more appropriate.
On the Q7-A29 module, the aforementioned pins have been dedicated to the LPC bus; use of these pins for different implementations other than
LPC (i.e. as GPIOs) is therefore not possible.
The following signals are available:
LPC_AD[0÷3]: LPC address, command and data bus, bidirectional signal, +3.3V_A electrical level.
LPC_CLK: LPC Clock Output line, +3.3V_A electrical level. Since only a clock line is available, if more LPC devices are available on the carrier board, then it is
necessary to provide for a zero-delay clock buffer to connect all clock lines to the single clock output of Qseven® module.
LPC_LDRQ#: LPC DMA Request line, +3.3V_A electrical level input.
LPC_FRAME#: LPC Frame indicator, active low output line, +3.3V_A electrical level. This signal is used to signal the start of a new cycle of transmission, or the
termination of existing cycles due to abort or time-out condition.
SERIRQ: LPC Serialised IRQ request, bidirectional line, +3.3V_S electrical level. This signal is used only by peripherals requiring Interrupt support.
3.2.3.13 SPI interface signals
According to newest Qseven® Rel. 2.0 specifications, Q7-A29 can optionally offer one SPI interface, which is derived from AMD G-series SOC’s USB port #6 by
using the same USB-to-Serial bridge (Cypress CY7C65215) used for deriving the UART interface (see par. 3.2.3.2). The SPI interface is derived by device’s serial
port #1.
This interface can be used for connection of EEPROMs and Serial Flash devices, but it does not support platform firmware (BIOS).
SPI interface supports master mode, with speed up to 3MHz.
Signals involved with SPI management are the following:
SPI_MOSI: SPI Master Out Slave In, Output from Qseven® module to SPI devices embedded on the Carrier Board. Electrical level +3.3V_S with 10kΩ pull-up
resistor.
SPI_MISO: SPI Master In Slave Out, Input to Qseven® module from SPI devices embedded on the Carrier Board. Electrical level +3.3V_S.
SPI_CLK: SPI Clock Output to carrier board’s SPI embedded devices. Electrical level +3.3V_S.
SPI_CS0#: SPI Chip select, active low output signal, +3.3V_S electrical level.
Q7-A29
Q7-A29 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
40
3.2.3.14 Power Management signals
According to Qseven® specifications, on the golden card edge connector there is a set of signals that are used to manage the power rails and power states.
The signals involved are:
PWGIN: Power Good Input, +5V_S tolerant active high signal. It should be driven on the carrier board to signal that power supply section is ready and stable.
When this signal is asserted, the module will begin the boot phase. The signal must be kept asserted for all the time that the module is working.
PWRBTN#: Power Button Input, active low, +3.3V_A voltage signal with 10kΩ pull-up resistor. When working in ATX mode, this signal can be connected to a
momentary push-button: a pulse to GND of this signal will switch power supply On or Off.
RSTBTN#: Reset Button Input, active low, +3.3V_A voltage signal with 10kΩ pull-up resistor. This signal can be connected to a momentary push-button: a pulse
to GND of this signal will reset the Qseven® module.
BATLOW#: Battery Low Input, active low, +3.3V_A voltage signal with 10kΩ pull-up resistor. This signal can be driven on the carrier board to signal that the system
battery is low, or that some battery-related event has occurred. Can be left unconnected if not used.
WAKE#: Wake Input, active low +3.3V_A electrical voltage signal with 10kΩ pull-up resistor. This signal can be driven low, on the carrier board, to report that a
Wake-up event has occurred, and consequently the module must turn itself on. It can be left unconnected if not used.
SUS_STAT#: Suspend status output, active low +3.3V_A electrical voltage signal. This output can be used to report to the devices on the carrier board that the
module is going to enter in one of possible ACPI low-power states.
SUS_S3#: S3 status output, active low +3.3V_A electrical voltage signal. This signal must be used, on the carrier board, to shut off the power supply to all the
devices that must become inactive during S3 (Suspend to RAM) power state.
SUS_S5#: S5 status output, active low +3.3V_A electrical voltage signal. This signal is used, on the carrier board, to shut off the power supply to all the devices
that must become inactive only during S5 (Soft Off) power state.
SLP_BTN#: Sleep button Input, active low +3.3V_A electrical level signal, with 10kΩ pull-up resistor. This signal can be driven, using a pushbutton on the carrier
board, to trigger the transition of the module from Working to Sleep status, or vice versa. It can be left unconnected if not used on the carrier board.
LID_BTN#: LID button Input, active low +3.3V_A electrical level signal, with 10kΩ pull-up resistor. This signal can be driven, using a LID Switch on the carrier board,
to trigger the transition of the module from Working to Sleep status, or vice versa. It can be left unconnected if not used on the carrier board.
3.2.3.15 Miscellaneous signals
Here following, a list of Qseven® compliant signals that complete the features of Q7-A29 module.
SMB_CLK: SM Bus control clock line for System Management. Bidirectional signal, electrical level +3.3V_A with a 2k2Ω pull-up resistor. It is managed by AMD Gseries SOC’s System Management Bus controller.
SMB_DAT: SM Bus control data line for System Management. Bidirectional signal, electrical level +3.3V_A with a 2k2Ω pull-up resistor. It is managed by AMD G-
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series SOC’s System Management Bus controller.
SMB_ALERT#: SM Bus Alert line for System Management. Bidirectional signal, electrical level +3.3V_A with a 10kΩ pull-up resistor. It is managed by AMD Gseries SOC’s General Event manager. Any device place on the SM Bus can drive this signal low to signal an event on the bus itself.
GP0_I2C_CLK: general purpose I2C Bus clock line. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor. This I2C signal is derived from AMD
G-series SOC’s General Purpose I/O pin GPIO49.
GP0_I2C_DAT: general purpose I2C Bus data line. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor. This I2C signal is derived from AMD
G-series SOC’s General Purpose I/O pin GPIO51.
WDTRIG#: Watchdog Trigger Input. It is an active low signal, +3.3V_S voltage with a 10kΩ pull-up resistor. This signal can be used to reset and restart, via
Hardware, the embedded microcontroller’s internal Watchdog Timer (which is usually managed via Software using Q7-A29 dedicated API - Application Program
Interface - libraries).
WDOUT: Watchdog event indicator Output. It is an active high signal, +3.3V_S voltage. When this signal goes high (active), it reports out to the devices on the
Carrier board that the embedded microcontroller’s internal Watchdog’s timer expired without being triggered, neither via HW nor via SW.
THRM#: Thermal Alarm Input. Active Low +3.3V_S voltage signal with 10kΩ pull-up resistor, managed by the embedded microcontroller. This input gives the
possibility, to carrier board’s hardware, to indicate to the main module an overheating situation.
FAN_TACHOIN: External FAN Tachometer Input. +3.3V_S voltage signal with 10kΩ pull-up resistor, managed by ST STM32F100R4H6 microcontroller.
FAN_PWMOUT: PWM output for FAN speed management, +3.3V_S voltage signal. It is managed by ST Microelectronics STM32F100R4H6 microcontroller.
SPKR: Speaker output, +3.3V_S voltage buffered signal, directly managed by AMD G-series SOC’s embedded 8254 Timer (counter #2).
3.2.3.16 Manufacturing signals
According to Qseven® Standard specifications, rel. 2.0, on pin designed as MFG_NCx (pins 204, 207÷210) are carried the JTAG signal necessary to program Q7A29 embedded microcontroller.
The JTAG interface available on MFG_NCx pins is reserved only for the manufacturing phase; it must not be used by the customer.
It is not possible at all to use these pins to trace the software (for debug purposes).
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3.2.4 BOOT Strap Signals
Configuration straps are signals that, during system reset, are set as inputs (independently by their behaviour during normal operations) in order to allow the proper
configuration of the processor / chipset. For this reason, on Q7-A29 are placed the pull-up or pull-down resistors that are necessary to configure the board
properly.
The customer must avoid to place, on the carrier board, pull-up or pull-down resistors on signals that are used as strap signal, since it could result in malfunctions
of Q7-A29 module.
The following signals are used as configuration straps by Q7-A29 at system reset.
LPC_FRAME#: pin 190 of golden card edge connector. This pin determines if the board must boot using the embedded SPI Flash (default) or using an external
LPC Firmware Hub. Signal at +3.3V_A voltage level with a 10kΩ pull-up resistor.
LPC_CLK: pin 189 of golden card edge connector. This pin enables or disables (default) the internal Watchdog for boot failure event. Signal at +3.3V_A voltage
level with a 2k2Ω pull-down resistor.
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Chapter 4.
Introduction
Main setup menu
Advanced menu
Security menu
Power menu
Boot menu
Exit menu
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4.1 Introduction
Basic setup of the board can be done using Insyde Software Corp. “InsydeH2O Setup Utility”, that is stored inside an onboard SPI Serial Flash.
It is possible to access to InsydeH2O Setup Utility by pressing the <ESC> key after System power up, during POST phase. On the splash screen that will appear,
select “SCU” icon.
On each menu page, on left frame are shown all the options that can be configured.
Grayed-out options are only for information and cannot be configured.
Only options written in blue can be configured. Selected options are highlighted in white.
Right frame shows the key legend.
KEY LEGEND:
←/→
Navigate between various setup screens (Main, Advanced, Security, Power, Boot...)
↑/↓
Select a setup item or a submenu
<F5> / <F6>
<F5> and <F6> keys allows to change the field value of highlighted menu item
<F1>
The <F1> key allows to display the General Help screen.
<F9>
<F9> key allows loading Setup Defaults for the board. After pressing <F9> BIOS Setup utility will request for a confirmation, before saving and
exiting. By pressing <ESC> key, this function will be aborted
<F10>
<F10> key allows save any changes made and exit Setup. After pressing <F10> key, BIOS Setup utility will request for a confirmation, before
saving and exiting. By pressing <ESC> key, this function will be aborted
<ESC>
<Esc> key allows to discard any changes made and exit the Setup. After pressing <ESC> key, BIOS Setup utility will request for a confirmation,
before discarding the changes. By pressing <Cancel> key, this function will be aborted
<ENTER>
sub- screens.
<Enter> key allows to display or change the setup option listed for a particular setup item. The <Enter> key can also allow to display the setup
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4.2 Main setup menu
When entering the Setup Utility, the first screen shown is the Main setup screen. It is always possible to return to the Main setup screen by selecting the Main tab.
In this screen, are shown details regarding BIOS version, Processor type, Bus Speed and memory configuration.
Only two options can be configured:
4.2.1 System Time / System Date
Use this option to change the system time and date. Highlight System Time or System Date using the <Arrow> keys. Enter new values directly through the
keyboard, or using + / - keys to increase / reduce displayed values. Press the <Enter> key to move between fields. The date must be entered in MM/DD/YY
format. The time is entered in HH:MM:SS format.
Note: The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.
The system date is in the format mm/dd/yyyy.
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4.3 Advanced menu
Menu Item
Options
Description
Boot Configuration
See submenu
Configures settings for Boot Phase
Peripheral Configuration
See submenu
Configures the peripherals
SATA configuration
See submenu
Select the SATA controller and hard disk drive type installed in the system
Video Configuration
See submenu
Configures the options for video section
Chipset Configuration
See submenu
Configure Chipset’s parameters
ACPI Table / Features Control
See submenu
Configures the parameters for ACPI management
CPU Related settings
See submenu
Configures CPU related parameters
Memory Configurations
See submenu
Configures Memory Controller features and memory clock
SDIO Configuration
See submenu
SDIO Configuration submenu
4.3.1 Boot configuration submenu
Menu Item
Options
Description
Numlock
On / Off
Allows to choose whether NumLock Key at system boot must be turned On or Off
USB High Speed BIOS Support
Disabled / Enabled
USB emulation at high speed for capable devices
USB BIOS Support
Disabled / Enabled / UEFI only
USB keyboard / mouse / storage support under UEFI and legacy environments
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4.3.2 Peripheral configuration submenu
Menu Item
Options
Description
OHCI 1 (USB 2/3/4/5)
Disabled / Enabled
Enabled: Enable the OHCI controller 1 (for USB 1.1 support), which manages USB ports #2 ÷ #5
Disabled: Disable the OHCI Controller 1
EHCI 1 (USB 2/3/4/5)
Disabled / Enabled
Enabled: Enable the EHCI controller 1 (for USB 2.0 support), which manages USB ports 1 ÷ 4
Disabled: Disable the EHCI Controller 1
OHCI 2 (Optional Serial Bridge)
Disabled / Enabled
Enabled: Enable the OHCI controller 2 (for USB 1.1 support), which manages the USB to UART bridge
Disabled: Disable the OHCI Controller 2
EHCI 2 (Optional Serial Bridge)
Disabled / Enabled
Enabled: Enable the EHCI controller 2 (for USB 1.1 support), which manages the USB to UART bridge
Disabled: Disable the OHCI Controller 2
OHCI 3 (USB 0/1)
Disabled / Enabled
Can be changed only when “xHCI (USB 0/1)” is disabled
Enable or disable the selected OHCI controller, which is needed for driving USB 1.1 devices connected to
USB ports #0 - #1 at Low Speed / Full Speed.
EHCI 3 (USB 0/1)
Disabled / Enabled
Can be changed only when “xHCI (USB 0/1)” is disabled
Enable or disable the selected EHCI controller, which is needed for driving USB 2.0 devices connected to
USB ports #0 - #1 at High Speed.
xHCI (USB 0/1)
Disabled / Enabled
Enable or disable the internal xHCI controller, which is needed for driving USB 3.0 devices at SuperSpeed.
It can also handle slower devices without OHCI3/EHCI3 enabling.
HD Audio
Disabled / Enabled
Enabled: Enable the HD Audio Codec
Disabled: Disable the internal HD Audio Codec
SATA
Disabled / Enabled
Enabled: Enable the SATA controller.
Disabled: Disable the SATA controller
4.3.3 SATA configuration submenu
Menu Item
Options
Description
SATA Configure As
IDE
AHCI
Set SATA Configuration type
With AHCI, is not possible to install/boot UEFI O.S., only Legacy OS can be installed (a simpler driver is
required).
Setting to IDE, the controller is managed as a PCI device, so addresses reallocation and INT line sharing is
possible.
Serial ATA Port 0 / 1
Disabled / Enabled
Shows information related to eventual devices connected to SATA ports 0 or 1
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4.3.4 Video configuration submenu
Menu Item
Options
Description
UMA Frame buffer Size
Auto / 64 MB / 128 MB / 256
MB / 384 MB / 512 MB / 1 GB
/ 2 GB
Set UMA Frame buffer Size
HDMI Audio
Disabled / Enabled
Enable or Disable Audio on HDMI
LFP
Disabled / External EDID /
640x480 / 800x480 /
800x600 / 1024x600 /
1024x768 / 1280x720 /
1280x800 / 1280x1024 /
1366x768 / 1440x900 /
1600x900 / 1680x1050 /
1920x1080
Select a software resolution (EDID settings) to be used for the internal flat panel.
Using External EDID, LVDS display resolution is taken by external EDID interface
Resolutions above 1600x900 are available only using eDP interface, please take care if the board
purchased offers LVDS or eDP.
LFP Color Mode
VESA 24 bpp
JEIDA 24 bpp
18 pp
Select the color depth of LVDS interface. For 24-bit color depth, it is possible to choose also the color
mapping on LVDS channels, i.e. if it must be VESA-compatible or JEIDA compatible.
LFP Bus Mode
Single Channel
Allows configuration of LVDS interface in Single or Dual channel mode
LFP BackLight Polarity
Not Inv. (Act. High)
Inv. (Act. Low)
Configure the LVDS BackLight Polarity
LFP Default Brightness
0 ÷ 100
Set the booting LVDS brightness percentage. Please be aware that a very low brightness level could make
the panel not visible.
LFP BackLight Frequency
0 ÷ 20000
Set the LVDS Backlight Frequency in Hertz
4.3.5 Chipset configuration submenu
Menu Item
Options
Description
PCI Express Configurations
See submenu
PCI Latency timer
32 / 64 / 96 / 128 / 160 / 192
/ 224 / 248
Set this value to allow the PCI Latency Timer to be adjusted. This option sets the latency of all PCI devices
on the PCI bus. Values are in units of PCI clocks.
Adaptive S4
Enabled / Disabled
Enable/Disable Adaptive S4 Power management
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4.3.5.1 PCI Express Configurations submenu
Menu Item
Options
Description
PSPP Policy
Disabled / Performance /
PCIe Speed Power policy: the processor can dynamically support the changing to the link
Balanced High / Balanced Low/
frequency due to changes in system configuration and power policy.
Power Saving / Auto
PCI-e lanes grouping as following:
PCI-e Topology
4 x1
1 x2 + 2 x1
2 x2
1 x4
Lane #0
Lane #1
Lane #2
Lane #3
x1
x1
x1
x1
x1
x1
x2
x2
x2
x4
APU GPP #0 Features
APU GPP #1 Features
APU GPP #2 Features
APU GPP #3 Features
See following options
These menu are to be used to set single PCI express ports features, see the following menu
items
GPP Enabled
Auto /Disabled / Enabled
Use this item to enable this GPP.
Speed Mode
Auto / Gen1 / Gen2
This menu item is available only when “GPP Enabled” is set to Enabled.
Set PCI-e ports link speed/capability
Link ASPM
Disabled / L0s / L1 / L0s & L1
This menu item is available only when “GPP Enabled” is set to Enabled.
Manages PCI Express L0s and L1 power states, for OSs able to handle Active State Power
Management (ASPM)
Internal LAN configuration
See following options
This menu must be used to set GFX PCI express port features, see the following menu items
GPP Enabled
Auto /Disabled / Enabled
Use this item to enable this GPP.
Disabled / L0s / L1 / L0s & L1
This menu item is available only when “GFX Enabled” is set to Enabled.
Manages PCI Express L0s and L1 power states, for OSs able to handle Active State Power
Management (ASPM)
Link ASPM
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4.3.6 ACPI Table/features submenu
Menu Item
Options
Description
FACP - C2 Latency Value
Enabled / Disabled
Allows definition of C2 latency value to be defined in FACP Table. Values smaller than 100 mean C2
Enabled, values larger than 100 mean C2 Disabled
FACP - C3 Latency Value
Enabled / Disabled
Allows definition of C3 latency value to be defined in FACP Table. Values smaller than 1000 mean C3
Enabled, values larger than 1000 mean C3 Disabled
FACP - RTC S4 wakeup
Enabled / Disabled
Enable or disable FACP support for S4 wakeup from RTC
HPET - HPET Support
Enabled / Disabled
High Precision Event Timer is supported in Windows Vista or above. HPET controller should not been seen
in Windows XP, no matter if enabled/disabled in SCU. If this feature is enabled, the HPET table will be
added into ACPI Tables.
_OSC Support
Enabled / Disabled
Enable or Disable ACPI Operating System Capabilities (_OSC) Method to communicate to the O. S. which
features available in the system can be controlled by the operating system
Fusion Utility
Enabled / Disabled
Enable/Disable AMD Fusion Utility Support
Acpi Time Wake Alarm Device
Enabled / Disabled
Enable/Disable Acpi Time Wake Alarm Device
4.3.7 CPU related setting submenu
Menu Item
Options
Description
CPU P-State Setting
Auto / Lowest Speed
Sets the CPU P-States behavior, if AUTOmatic or fixed at lowest speed
SVM support
Enabled / Disabled
Enable or Disable Secure Virtual Machine Mode (SVM) support, for users who require to use Virtual
Machines
SMM Code Lock
Enabled / Disabled
Enable or disable locking of the SMM (System Management Mode) code segment / registers for preventing
changes to the internal code/registers
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4.3.8 Memory configurations submenu
Menu Item
Options
Description
Memory clock setting mode
select
Auto / Limited
This item allows selecting the memory clock settings.
In Auto mode, the clock will run according to SPD data.
In limited mode, if SPD clock is higher than the limit, then memory clock will follow limit clock
Select memory clock value
800 MHz / 1066 MHz / 1333
MHz / 1600 MHz
This menu item is available only when “Memory clock setting mode select” is not set to Auto.
Specifies the memory clock limit or set a specific memory clock, according to previous setting
Memory ECC enable
Disabled / Enabled
Enable or disable the ECC Correction using the recommended AMD settings.
MCA ECC features will not work unless this feature is enabled
Please be aware that changing Memory clock settings could lead to system instability.
4.3.9 SDIO Configuration submenu
Menu Item
Options
Description
SD Mode
Disabled / ADMA / DMA / PIO
Select the data transfer method that must be used by the Host Controller driver. It can be PIO Mode, DMA
mode or Advanced DMA mode, as described in SD Host Controller Specifications
SD HC Version
SD 2.0 / SD 3.0
SD Host Controller Version
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4.4 Security menu
Menu Item
Options
Description
Install or Change the password for supervisor.
Length of password must be greater than one character.
Set Supervisor Password
Password Storage
C-MOS RAM
BIOS Flash
Power on Password
Enabled / Disabled
Power on Password
Selects the place where the password will be saved. Please be aware that selecting BIOS Flash
the password will be kept also after removing the CMOS battery.
Available only when Supervisor Password has been set.
Enabled: System will ask to input a password during P.O.S.T. phase.
Disabled: system will ask to input a password only for entering Setup utility
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4.5 Power menu
Menu Item
Options
Description
Advanced CPU Control
See submenu
These items control various CPU parameters
Thermal Zone configuration
See submenu
Thermal Zone Configuration: Active and Passive Cooling Settings.
Clock and Voltages Optimizations
See submenu
Change Clock Settings
Watchdog Configuration
See submenu
Watchdog Configuration Settings
LID_BTN# Configuration
Force Open
Force Closed
Normal Polarity
Inverted Polarity
Configure LID_BTN# Signal as always open or closed (i.e., Force Open / Force Closed), no matter the pin
level, or configures the signal polarity: “Normal Polarity” means the signal goes High when open, “Inverted
Polarity” means the signal goes Low when open
LID_BTN# Wake Configuration
No Wake
Only From S3
Wake From S3/S4/S5
This item can be changed only when “LID_BTN# Configuration” is not set to Force Open or Force Closed.
Configure LID_BTN# Wake capability. According to the pin configuration, when the LID is open it can cause
a system wake from a sleep state
ACPI S3
Enabled / Disabled
Enable or Disable ACPI S3 Sleep State
Power Fail Resume Type
Always OFF
Last State
Always ON
Determine the System Behavior after a power failure event.
In case the option is “Always ON”, the board will start every time the power supply is present.
When the option is “Always OFF”, the board will not start automatically when the power supply returns.
Finally, if this option is set to “Last State”, the board will remember the state it had when the power supply
went down: so, if the board was on, it will start again when the power returns, and will remain off if the
board was in this state when the power went down.
Wake on PME
Enabled / Disabled
Determines whether the system must wake up or not when the system power is off and it occurs a PCI
Power Management Enable wake-up event.
Auto Wake on S5
Disabled
By Every Day
By Day of Month
Auto wake up from S5 state, it can be set to happen “By Day of month” or at a “Fixed time of every day”.
Wake on S5 time
[hh:mm:ss]
This menu item is available only when “Auto Wake on S5” is not set to Disabled.
Set the time of the day when the board must wake up automatically
Day of month
1 ÷ 31
This menu item is available only when “Auto Wake on S5” is set to “By Day of Month”
Set the day when the board must wake up automatically. Valid range is from 1 to 31. Error checking will be
done against month/day/year combinations that are not supported. Use + / - to Increase / reduce
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4.5.1 Advanced CPU control submenu
Menu Item
Options
Description
Cool N’ Quiet Support
Enabled / Disabled
Enable or Disable “Cool N’ Quiet” power saving and speed throttling technology for CPU idle states.
Multi CORE support
Auto / Disabled
Enable / Disable Multi CORE Support
CPU C-States
Auto / Disabled
C-State ACPI Management
4.5.2 Thermal Zone configuration submenu
Menu Item
Options
Description
Onboard FAN
Enabled / Disabled
Enable or Disable Onboard FAN
Low Threshold (°C)
0 °C ÷ 115 °C
This submenu is available only when “Onboard FAN” is set to Enabled.
Select the lowest temperature under which the onboard FAN must be Off
High Threshold (°C)
0 °C ÷ 115 °C
This submenu is available only when “Onboard FAN” is set to Enabled.
Select the highest temperature above which the onboard FAN must work always at Full Speed
Mid Duty Cycle
0 ÷ 100
This submenu is available only when “Onboard FAN” is set to Enabled.
Use this item to set the Duty Cycle for the FAN when the APU temperature is between Low and High
threshold. Values that can be accepted are between 0 (0% OFF) and 100 (100%Full Speed)
Passive Cooling Threshold (°C)
0 °C ÷ 115 °C
Use this item to set the temperature threshold for the CPU. Above this temperature value, the CPU will start
to lower its frequency.
Critical temperature (°C)
0 °C ÷ 115 °C
Use this item to set the maximum temperature that the CPU can reach. Above this temperature value, the
system will perform a critical shutdown
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4.5.3 Clocks And Voltages Optimizations submenu
Menu Item
Options
Description
LVDS Spread Spectrum
Percentage
0 ÷ 1000
LVDS Spread Spectrum Percentage (Downspread) in 0.01% units. For example: 0 = No Spread Spectrum,
40 = -0.40 spread spectrum
HDMI Spread Spectrum
Percentage
0 ÷ 1000
HDMI Spread Spectrum Percentage (Downspread) in 0.01% units. For example: 0 = No Spread Spectrum,
40 = -0.40 spread spectrum
PCIE Spread Spectrum
Percentage
0 ÷ 1000
PCIE Spread Spectrum Percentage (Downspread) in 0.001% units. For example: 0 = No Spread
Spectrum, 375 = -0.375 spread spectrum
0.4V 0dB / 0.6V 0dB
0.8V 0dB / 1.2V 0dB
Display Port Fixed Voltage Swing 0.4V 3.5dB / 0.6V 3.5dB
0.8V 3.5dB / 0.4V 6dB
0.6V 6dB / 0.4v 5dB
Allows the selection of the voltage swing and the pre-emphasis for Display port
4.5.4 Watchdog Configuration submenu
Menu Item
Options
Description
Watchdog
Enabled / Disabled
Enable / Disable Watchdog.
Watchdog Action
System Reset
Power Button 1s
Power Button 4s (Shutdown)
This submenu is available only when “Watchdog” is set to Enabled.
Specifies the action that must be performed when Watchdog timeout occurs.
With System Reset, the module will reset itself
With “Power Button 1s”, the system will simulate the pressure for 1 sec. of Power button, which will
lead the O.S. to close all his tasks then shutdown.
With “Power Button 1s”, the system will simulate the pressure for 1 sec. of Power button, which will
lead to the immediate shutdown of the module
Delay To Start (sec.)
0 ÷ 600
This submenu is available only when “Watchdog” is set to Enabled.
This menu item specifies the seconds of delay, after system power up, before the watchdog timeout starts
counting.
Timout (sec.)
20 ÷ 600
This submenu is available only when “Watchdog” is set to Enabled.
This menu item specifies the seconds of delay before the watchdog timeout.
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4.6 Boot menu
Menu Item
Options
Description
Boot type
Dual boot Type
Legacy Boot Type
UEFI Boot Type
Allows to select if the OS must be booted using Legacy Boot Mode, UEFI Boot mode or indifferently using
both modalities (depending on the OS)
Quick Boot
Enabled / Disabled
Skip certain tests while booting. This will decrease the time needed to boot the system.
Quiet Boot
Enabled / Disabled
Disables or enables booting in Text Mode.
Display ESC String
Enabled / Disabled
Display or Hide the “ESC key” strings during the BIOS boot. Disabling this configuration, no information on
how to enter Setup Configuration Utility will be displayed.
Add Boot options
First / Last / Auto
Specifies the position in Boot Order for Shell, Network and Removable Drives
ACPI selection
Acpi1.0B / Acpi3.0 / Acpi4.0 / Using this menu item is possible to select to which specifications release the ACPI tables must be
Acpi5.0
compliant.
USB Boot
Enabled / Disabled
Disables or enables booting from USB boot devices.
EFI Device First
Enabled / Disabled
Determine if boot must happen first through EFI devices or through legacy devices. When enabled, it will
happen first from EFI devices. When disabled, it will happen first from Legacy devices.
Windows® 8 Fast Boot
Enabled / Disabled
This submenu is available only when “Boot Type” is set to UEFI Boot Type.
If enabled, the system firmware does not initialize keyboard and check for firmware menu key.
USB Hot Key Support
Enabled / Disabled
This submenu is available only when “Boot Type” is set to UEFI Boot Type and “Windows® 8 Fast Boot” is
Enabled.
Enable or disable the support for USB HotKeys while booting. This will decrease the time needed to boot
the system
Timeout
0 ÷ 300
The number of seconds that the firmware will wait before booting the original default boot selection.
Automatic Failover
Enabled / Disabled
When this item is enabled, if boot from the default device fails, then the system will attempt directly to boot
from the next device on the Boot devices list
When this item is disabled, in case of failure from booting from the first boot device, then a Warning
Message will pop up and subsequently enter into Firmware UI.
EFI
See Submenu
This submenu is available only when “Boot Type” is not set to “Legacy Boot type”.
The submenu will show a list of EFI boot devices. Use F5 and F6 key to change order for boot priority.
Legacy
See Submenu
This submenu is available only when “Boot Type” is not set to “UEFI Boot type”.
Allows setting of Legacy Boot Order
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4.6.1 Legacy submenu
Menu Item
Options
Description
Normal Boot Menu
Normal / Advance
When set to Normal, this submenu will allow configuring all possible options for Legacy boot. When set to
Advance, it will be possible to configure Boot Order only for bootable devices found in the system
Boot Type Order
Floppy Drive / Hard Disk Drive
CD/DVD-ROM Drive / USB /
Other
This voice will be selectable only when “Boot menu” is set to “Normal”.
The list shown under this item will allows selecting the boot from different devices. Use the + and - Keys to
change the boot order priority
Hard Disk Drive
List of HD Drives found
connected
This voice will be selectable only when “Boot menu” is set to “Normal”.
The list shown under this item will show different Disk drives found connected to the module, therefore
changing the boot priority for them. Use the + and - Keys to change the boot order priority
USB
List of USB Drives found
connected
This voice will be selectable only when “Boot menu” is set to “Normal”.
The list shown under this item will show different USB drives found connected to the module, therefore
changing the boot priority for them. Use the + and - Keys to change the boot order priority
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4.7 Exit menu
Menu Item
Options
Description
Exit Saving Changes
Exit system setup after saving the changes.
F10 key can be used for this operation.
Save Change Without Exit
Save all changes made, but doesn’t exit from setup utility.
Exit Discarding Changes
Exit system setup without saving any changes.
ESC key can be used for this operation.
Load Optimal Defaults
Load Optimal Default values for all the setup items.
F9 key can be used for this operation.
Load Custom Defaults
Load Custom Default values for all the setup items.
Save Custom Defaults
Save Custom Default values for all the setup items.
Discard Changes
Discard all the changes made
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Chapter 5.
Thermal Design
Accessories
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5.1 Thermal Design
A parameter that has to be kept in very high consideration is the thermal design of the system.
Highly integrated modules, like Q7-A29 module, offer to the user very good performances in minimal spaces, therefore allowing the systems’ minimisation. On the
counterpart, the miniaturising of IC’s and the rise of operative frequencies of processors lead to the generation of a big amount of heat, that must be dissipated to
prevent system hang-off or faults.
Qseven® specifications take into account the use of a heatspreader, which will act only as thermal coupling device between the Qseven® module and an external
dissipating surface/cooler. The heatspreader also needs to be thermally coupled to all the heat generating surfaces using a thermal gap pad, which will optimise the
heat exchange between the module and the heatspreader.
The heatspreader is not intended to be a cooling system by itself, but only as means for transferring heat to another surface/cooler, like heatsinks, fans, heat pipes
and so on.
Conversely, heatsinks in some situation can represent the cooling solution. Until the module is used on a development Carrier board, on free air, just for software
development and system tuning, then a finned heatsink could be sufficient for module’s cooling.
Anyhow, please remember that all depends also on the workload of the processor. Heavy computational tasks will generate much heat with all CPU versions.
Indeed, when using Q7-A29 module, it is necessary to consider carefully the heat generated by the module in the assembled final system, and the scenario of
utilisation.
Therefore, it is always necessary that the customer study and develop accurately the cooling solution for his system, by evaluating processor’s workload, utilisation
scenarios, the enclosures of the system, the air flow and so on. This is particularly needed for industrial grade modules.
SECO can provide Q7-A29 specific heatspreaders and heatsinks, but please remember that their use must be evaluated accurately inside the final system, and
that they should be used only as a part of a more comprehensive ad-hoc cooling solutions.
Ordering Code
Description
QA29-DISS-1
Q7-A29 Heat Spreader
QA29-DISS-2
Q7-A29 Heatsink
QA29-DISS-3
Q7-A29 Active Heatsink with FAN
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Standard Heatspreader dimensions
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Standard Heatsink dimensions
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5.2 Accessories
SECO can offer the following accessories in completion of Q7-A29 functionalities
5.2.1 VGA Adapter module M908
Qseven® specifications didn’t include the legacy VGA interface between the interfaces available on golden card edge connector.
Such an interface, however, it is still widely used and offered by many processors/chipsets, including AMD G-series SOCs.
As previoulsy written in paragraph 3.2.1, however, Qseven® specifications Rel. 2.0 define an area, on the PCB, that can be used to place
optional I/O connectors of any kind. For this reason, on Q7-A29 board, such an area has been used for an additional FFC/FPC connector,
which carries out VGA interface.
SECO can offer an optional VGA adapter module, ordering code M908, which can be used for the connection of standard VGA displays.
The Adapter module is equipped directly with a 20cm long FFC cable for its connection to Q7-A29 board’s connector CN1.
DB-15 HD CRT connector is VESA VGA DDC2 compliant.
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SECO Srl - Via Calamandrei 91
52100 Arezzo - ITALY
Ph: +39 0575 26979 - Fax: +39 0575 350210
www.seco.com
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