Renesas UPD789322, UPD789324, UPD78F9234MCT-5A4-A User Manual

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User’s Manual
µPD789327 Subseries
8-Bit Single-Chip Microcontrollers
µPD789322
µPD789324
µPD789326
µPD789327
µPD78F9328
Document No. U15043EJ3V1UD00 (3rd edition)
Date Published October 2005 N CP(K)
©
Printed in Japan
[MEMO]
2
User’s Manual U15043EJ3V1UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U15043EJ3V1UD
3
EEPROM and FIP are trademarks of NEC Electronics Corporation.
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• The information in this document is current as of August, 2005. The information is subject to
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
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and visual equipment, home electronic appliances, machine tools, personal electronic equipment
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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U15043EJ3V1UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
• Device availability
• Ordering information
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In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
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J05.6
User’s Manual U15043EJ3V1UD
5
INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of the
µPD789327 Subseries and to design and develop application systems and programs
using these microcontrollers.
Target products:
• µPD789327 Subseries:
Purpose
µPD789322, 789324, 789326, 789327, 78F9328
This manual is intended to give users an understanding of the functions described in
the Organization below.
Organization
The µPD789327 Subseries User’s Manual is divided into two parts: this manual and
instructions (common to the 78K/0S Series).
78K/0S Series
µPD789327 Subseries
User’s Manual
User’s Manual
Instructions
• Pin functions
• CPU function
• Internal block functions
• Instruction set
• Interrupt functions
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Use This Manual
It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To understand the functions in general:
→ Read this manual in the order of the contents. The mark
shows major revised
points.
• How to interpret the register format:
→ Where the bit number is enclosed in angle brackets (<>), the bit name is
reserved for the assembler and is defined as an sfr variable by the #pragma sfr
directive for the C compiler.
• When you know a register name and want to confirm its details:
→ Read APPENDIX B REGISTER INDEX.
• To know the 78K/0S Series instruction function in detail:
→ Read 78K/0S Series Instructions User’s Manual (U11047E).
• To know the µPD789327 Subseries electrical specification in details:
→ Read CHAPTER 18 ELECTRICAL SPECIFICATIONS.
6
User’s Manual U15043EJ3V1UD
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation:
xxx (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
Numerical representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD789327 Subseries User’s Manual
This manual
78K/0S Series Instructions User's Manual
U11047E
Documents Related to Development Software Tools (User’s Manuals)
Document Name
RA78K0S Assembler Package
CC78K0S C Compiler
SM78K Series Ver. 2.52 System Simulator
ID78K0S-NS Ver. 2.52 Integrated Debugger
Document No.
Operation
U16656E
Language
U14877E
Structured Assembly Language
U11623E
Operation
U16654E
Language
U14872E
Operation
U16768E
External Part User Open Interface Specification
U15802E
Operation
U16584E
PM plus Ver.5.10
U16569E
Document Related to Development Hardware Tools (User’s Manuals)
Document Name
Document No.
IE-78K0S-NS In-Circuit Emulator
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
IE-789468-NS-EM1 Emulation Board
To be prepared
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U15043EJ3V1UD
7
Documents Related to Flash Memory Writing
Document Name
Document No.
PG-FP3 Flash Memory Programmer User's Manual
U13502E
PG-FP4 Flash Memory Programmer User's Manual
U15260E
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
8
User’s Manual U15043EJ3V1UD
CONTENTS
CHAPTER 1 GENERAL ..........................................................................................................................14
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Features ......................................................................................................................................14
Applications................................................................................................................................14
Ordering Information .................................................................................................................15
Pin Configuration (Top View)....................................................................................................16
78K/0S Series Lineup ................................................................................................................18
Block Diagram............................................................................................................................21
Overview of Functions ..............................................................................................................22
CHAPTER 2 PIN FUNCTIONS...............................................................................................................24
2.1
2.2
2.3
List of Pin Functions .................................................................................................................24
Description of Pin Functions ....................................................................................................26
2.2.1
P00 to P03 (Port 0) ....................................................................................................................... 26
2.2.2
P10, P11 (Port 1) .......................................................................................................................... 26
2.2.3
P20 to P22 (Port 2) ....................................................................................................................... 26
2.2.4
P40 to P43 (Port 4) ....................................................................................................................... 26
2.2.5
P60, P61 (Port 6) .......................................................................................................................... 27
2.2.6
P80 to P85 (Port 8) ....................................................................................................................... 27
2.2.7
S0 to S16, S23.............................................................................................................................. 27
2.2.8
COM0 to COM3 ............................................................................................................................ 27
2.2.9
VLC0 ............................................................................................................................................... 27
2.2.10
RESET .......................................................................................................................................... 27
2.2.11
X1, X2 ........................................................................................................................................... 28
2.2.12
XT1, XT2....................................................................................................................................... 28
2.2.13
VDD ................................................................................................................................................ 28
2.2.14
VSS ................................................................................................................................................ 28
2.2.15
VPP (µPD78F9328 only) ................................................................................................................ 28
2.2.16
IC0 (mask ROM version only) ....................................................................................................... 28
Pin Input/Output Circuits and Recommended Connection of Unused Pins .......................29
CHAPTER 3 CPU ARCHITECTURE......................................................................................................31
3.1
3.2
3.3
Memory Space............................................................................................................................31
3.1.1
Internal program memory space ................................................................................................... 36
3.1.2
Internal data memory (internal high-speed RAM) space ............................................................... 37
3.1.3
Special function register (SFR) area ............................................................................................. 37
3.1.4
Data memory addressing .............................................................................................................. 38
Processor Registers ..................................................................................................................43
3.2.1
Control registers............................................................................................................................ 43
3.2.2
General-purpose registers ............................................................................................................ 46
3.2.3
Special function registers (SFRs).................................................................................................. 47
Instruction Address Addressing ..............................................................................................50
3.3.1
Relative addressing....................................................................................................................... 50
3.3.2
Immediate addressing................................................................................................................... 51
User’s Manual U15043EJ3V1UD
9
3.4
3.3.3
Table indirect addressing .............................................................................................................. 52
3.3.4
Register addressing ...................................................................................................................... 52
Operand Address Addressing ..................................................................................................53
3.4.1
Direct addressing .......................................................................................................................... 53
3.4.2
Short direct addressing ................................................................................................................. 54
3.4.3
Special function register (SFR) addressing ................................................................................... 55
3.4.4
Register addressing ...................................................................................................................... 56
3.4.5
Register indirect addressing.......................................................................................................... 57
3.4.6
Based addressing ......................................................................................................................... 58
3.4.7
Stack addressing........................................................................................................................... 58
CHAPTER 4 PORT FUNCTIONS ...........................................................................................................59
4.1
4.2
Port Functions............................................................................................................................59
Port Configuration .....................................................................................................................60
4.2.1
4.3
4.4
Port 0 ............................................................................................................................................ 61
4.2.2
Port 1 ............................................................................................................................................ 62
4.2.3
Port 2 ............................................................................................................................................ 63
4.2.4
Port 4 ............................................................................................................................................ 66
4.2.5
Port 6 ............................................................................................................................................ 67
4.2.6
Port 8 ............................................................................................................................................ 69
Registers Controlling Port Function ........................................................................................70
Port Function Operation............................................................................................................74
4.4.1
Writing to I/O port .......................................................................................................................... 74
4.4.2
Reading from I/O port.................................................................................................................... 74
4.4.3
Arithmetic operation of I/O port ..................................................................................................... 74
CHAPTER 5 CLOCK GENERATOR ......................................................................................................75
5.1
5.2
5.3
5.4
5.5
5.6
Clock Generator Functions.......................................................................................................75
Clock Generator Configuration ................................................................................................75
Registers Controlling Clock Generator ...................................................................................77
System Clock Oscillators ..........................................................................................................79
5.4.1
Main system clock oscillator.......................................................................................................... 79
5.4.2
Subsystem clock oscillator ............................................................................................................ 80
5.4.3
Example of incorrect resonator connection ................................................................................... 81
5.4.4
Divider circuit................................................................................................................................. 82
5.4.5
When no subsystem clock is used ................................................................................................ 82
Clock Generator Operation .......................................................................................................83
Changing Setting of System Clock and CPU Clock ...............................................................84
5.6.1
Time required for switching between system clock and CPU clock............................................... 84
5.6.2
Switching between system clock and CPU clock .......................................................................... 85
CHAPTER 6 8-BIT TIMERS 30 AND 40................................................................................................86
6.1
6.2
6.3
10
8-Bit Timers 30 and 40 Functions.............................................................................................86
8-Bit Timers 30 and 40 Configuration ......................................................................................87
Registers Controlling 8-Bit Timers 30 and 40 .........................................................................92
User’s Manual U15043EJ3V1UD
6.4
6.5
8-Bit Timers 30 and 40 Operation.............................................................................................97
6.4.1
Operation as 8-bit timer counter.................................................................................................... 97
6.4.2
Operation as 16-bit timer counter................................................................................................ 104
6.4.3
Operation as carrier generator .................................................................................................... 108
6.4.4
Operation as PWM output (timer 40 only) ................................................................................... 112
Notes on Using 8-Bit Timers 30 and 40 .................................................................................114
CHAPTER 7 WATCH TIMER ...............................................................................................................115
7.1
7.2
7.3
7.4
Watch Timer Functions ...........................................................................................................115
Watch Timer Configuration.....................................................................................................116
Register Controlling Watch Timer..........................................................................................117
Watch Timer Operation ...........................................................................................................118
7.4.1
Operation as watch timer ............................................................................................................ 118
7.4.2
Operation as interval timer .......................................................................................................... 118
CHAPTER 8 WATCHDOG TIMER .......................................................................................................120
8.1
8.2
8.3
8.4
Watchdog Timer Functions.....................................................................................................120
Watchdog Timer Configuration ..............................................................................................121
Registers Controlling Watchdog Timer .................................................................................122
Watchdog Timer Operation.....................................................................................................124
8.4.1
Operation as watchdog timer ...................................................................................................... 124
8.4.2
Operation as interval timer .......................................................................................................... 125
CHAPTER 9 SERIAL INTERFACE 10 ................................................................................................126
9.1
9.2
9.3
9.4
Serial Interface 10 Functions ..................................................................................................126
Serial Interface 10 Configuration ...........................................................................................127
Registers Controlling Serial Interface 10 ..............................................................................129
Serial Interface 10 Operation ..................................................................................................131
9.4.1
Operation stop mode................................................................................................................... 131
9.4.2
3-wire serial I/O mode ................................................................................................................. 132
CHAPTER 10 LCD CONTROLLER/DRIVER.......................................................................................134
10.1 LCD Controller/Driver Functions............................................................................................134
10.2 LCD Controller/Driver Configuration .....................................................................................134
10.3 Registers Controlling LCD Controller/Driver ........................................................................136
10.4 Setting LCD Controller/Driver.................................................................................................140
10.5 LCD Display Data Memory ......................................................................................................141
10.6 Common and Segment Signals ..............................................................................................142
10.7 Display Modes ..........................................................................................................................145
10.7.1
Static display example ................................................................................................................ 145
10.7.2
Four-time slot display example ................................................................................................... 148
CHAPTER 11 POWER-ON-CLEAR CIRCUITS...................................................................................151
11.1 Power-on-Clear Circuit Functions..........................................................................................151
11.2 Power-on-Clear Circuit Configuration ...................................................................................151
User’s Manual U15043EJ3V1UD
11
11.3 Register Controlling Power-on-Clear Circuit ........................................................................152
11.4 Power-on-Clear Circuit Operation ..........................................................................................152
CHAPTER 12 INTERRUPT FUNCTIONS ............................................................................................153
12.1 Interrupt Function Types.........................................................................................................153
12.2 Interrupt Sources and Configuration .....................................................................................153
12.3 Registers Controlling Interrupt Function ..............................................................................156
12.4 Interrupt Servicing Operation .................................................................................................160
12.4.1
Non-maskable interrupt request acknowledgment operation ...................................................... 160
12.4.2
Maskable interrupt request acknowledgment operation .............................................................. 162
12.4.3
Multiple interrupt servicing........................................................................................................... 163
12.4.4
Putting interrupt requests on hold ............................................................................................... 165
CHAPTER 13 STANDBY FUNCTION ..................................................................................................166
13.1 Standby Function and Configuration.....................................................................................166
13.2 Register Controlling Standby Function .................................................................................167
13.3 Standby Function Operation...................................................................................................168
13.3.1
HALT mode ................................................................................................................................. 168
13.3.2
STOP mode ................................................................................................................................ 171
CHAPTER 14 RESET FUNCTION .......................................................................................................174
CHAPTER 15 µPD78F9328...................................................................................................................178
15.1 Flash Memory Characteristics................................................................................................179
15.1.1
Programming environment .......................................................................................................... 179
15.1.2
Communication mode ................................................................................................................. 180
15.1.3
On-board pin processing ............................................................................................................. 182
15.1.4
Connection on flash memory writing adapter .............................................................................. 185
CHAPTER 16 MASK OPTIONS ...........................................................................................................186
CHAPTER 17 INSTRUCTION SET ......................................................................................................187
17.1 Operation ..................................................................................................................................187
17.1.1
Operand identifiers and description methods .............................................................................. 187
17.1.2
Description of “Operation” column............................................................................................... 188
17.1.3
Description of “Flag” column ....................................................................................................... 188
17.2 Operation List...........................................................................................................................189
17.3 Instructions Listed by Addressing Type ...............................................................................194
CHAPTER 18 ELECTRICAL SPECIFICATIONS.................................................................................197
CHAPTER 19 PACKAGE DRAWING ..................................................................................................210
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User’s Manual U15043EJ3V1UD
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS ..........................................................211
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................213
A.1
A.2
A.3
A.4
A.5
A.6
A.7
Software Package ....................................................................................................................215
Language Processing Software .............................................................................................215
Control Software ......................................................................................................................216
Flash Memory Writing Tools...................................................................................................217
Debugging Tools (Hardware)..................................................................................................217
Debugging Tools (Software)...................................................................................................218
Cautions when designing target system...............................................................................219
APPENDIX B REGISTER INDEX.........................................................................................................220
B.1
B.2
Register Index (Alphabetic Order of Register Name)...........................................................220
Register Index (Alphabetic Order of Register Symbol) .......................................................222
APPENDIX C REVISION HISTORY .....................................................................................................224
C.1
C.2
Major Revisions in This Edition..............................................................................................224
Revision History of Previous Editions...................................................................................225
User’s Manual U15043EJ3V1UD
13
CHAPTER 1 GENERAL
1.1 Features
• ROM and RAM capacities
Item
Data Memory
Program Memory
(ROM)
Internal High-Speed
Part Number
LCD Display RAM
RAM
µPD789322
Mask ROM
4 KB
µPD789324
8 KB
µPD789326
16 KB
µPD789327
24 KB
µPD78F9328
Flash memory
256 bytes
24 × 4 bits
512 bytes
32 KB
• Minimum instruction execution time can be changed from high-speed (0.4 µs: @ 5.0 MHz operation with main
system clock) to ultra-low-speed (122 µs: @ 32.768 kHz operation with subsystem clock)
• I/O ports: 21
• Serial interface (3-wire serial I/O mode): 1 channel
• Timer: 4 channels
•
8-bit timer:
2 channels
•
Watch timer:
1 channel
•
Watchdog timer: 1 channel
• LCD controller/driver
Segment signals: 24, common signals: 4
• Vectored interrupt sources: 9
• On-chip power-on clear circuit (mask option for mask ROM versions)
• Power supply voltage: VDD = 1.8 to 5.5 VNote
• Operating ambient temperature: TA = –40 to +85°C
Note For mask ROM version when the use of the POC circuit is selected or for flash memory versions, the
minimum value of the operation power supply voltage is the POC detection voltage (1.9±0.1 V).
1.2 Applications
Remote controllers, healthcare equipment, etc.
14
User’s Manual U15043EJ3V1UD
CHAPTER 1 GENERAL
1.3 Ordering Information
Part Number
µPD789322GB-×××-8ET
Package
52-pin plastic LQFP (10 × 10)
Internal ROM
Mask ROM
µPD789324GB-×××-8ET
µPD789326GB-×××-8ET
µPD789327GB-×××-8ET
µPD78F9328GB-8ET
µPD789322GB-×××-8ET-A
µPD789324GB-×××-8ET-A
µPD789326GB-×××-8ET-A
µPD789327GB-×××-8ET-A
µPD78F9328GB-8ET-A
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Flash memory
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Mask ROM
52-pin plastic LQFP (10 × 10)
Flash memory
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
User’s Manual U15043EJ3V1UD
15
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
S16
7
33
S15
P02
8
32
S14
P01
9
31
S13
P00
10
30
S12
INT/P61
11
29
S11
P11
12
28
S10
P10
27
13
14 15 16 17 18 19 20 21 22 23 24 25 26
S9
COM0
16
P80/S22
34
P03
The parenthesized values apply to µPD78F9328.
User’s Manual U15043EJ3V1UD
S8
6
S7
P85/S17
P40/KR00
S6
35
S5
P84/S18
5
S4
36
P41/KR01
S3
P83/S19
4
S2
37
P42/KR02
S1
3
S0
P43/KR03
COM3
38
P82/S20
P60/TO40
COM2
P81/S21
2
1
COM1
52 51 50 49 48 47 46 45 44 43 42 41 40
39
RESET
Caution Connect the IC0 (Internally Connected) pin directly to VSS.
Remark
S23
VLC0
P22/SI10
P20/SCK10
P21/SO10
XT1
IC0 (VPP)
VSS
XT2
VDD
X1
X2
52-pin plastic LQFP (10 × 10)
CHAPTER 1 GENERAL
COM0 to COM3:
Common output
S0 to S23:
Segment output
IC0:
Internally connected
SCK10:
Serial clock input/output
INT:
Interrupt from peripherals
SI10:
Serial data input
KR00 to KR03:
Key return
SO10:
Serial data output
P00 to P03:
Port 0
TO40:
Timer output
P10, P11:
Port 1
VDD:
Power supply
P20 to P22:
Port 2
VLC0:
Power supply for LCD
P40 to P43:
Port 4
VPP:
Programming power supply
P60, P61:
Port 6
VSS:
Ground
P80 to P85:
Port 8
X1, X2:
Crystal (main system clock)
RESET:
Reset
XT1, XT2:
Crystal (subsystem clock)
User’s Manual U15043EJ3V1UD
17
CHAPTER 1 GENERAL
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass
production
Products under
development
Y subseries supports SMB.
Small-scale package, general-purpose applications
µ PD789074 with subsystem clock added
On-chip UART and capable of low-voltage (1.8 V) operation
µ PD789046
µ PD789026
µ PD789088
µ PD789074
µ PD789062
µ PD789052
44-pin
42-/44-pin
30-pin
30-pin
20-pin
20-pin
µ PD789074 with enhanced timer function and expanded ROM and RAM
µ PD789026 with enhanced timer function
RC oscillation version of µ PD789052
µ PD789860 without EEPROMTM, POC, and LVI
Small-scale package, general-purpose applications and A/D function
µ PD789177
µ PD789167
µ PD789134A
µ PD789124A
µ PD789114A
µ PD789104A
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
µ PD789177Y
µ PD789167Y
µ PD789167 with 10-bit A/D
µ PD789104A with enhanced timer
µ PD789124A with 10-bit A/D
RC oscillation version of µPD789104A
µ PD789104A with 10-bit A/D
µ PD789026 with 8-bit A/D and multiplier added
LCD drive
µ PD789835
µ PD789830
µ PD789489
µ PD789479
µ PD789417A
µ PD789407A
µ PD789456
µ PD789446
µ PD789436
µ PD789426
µ PD789316
µ PD789306
µ PD789467
µ PD789327
144-pin
88-pin
80-pin
80-pin
80-pin
78K/0S
Series
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
52-pin
52-pin
UART + 8-bit A/D + dot LCD (total display outputs: 96)
UART + dot LCD (40 × 16)
SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
µ PD789407A with 10-bit A/D
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
µ PD789446 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)
µ PD789426 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)
RC oscillation version of µPD789306
SIO + internal voltage boosting method LCD (24 × 4)
8-bit A/D + internal voltage boosting method LCD (23 × 4)
SIO + resistance division method LCD (24 × 4)
USB
44-pin
µ PD789800
For PC keyboard. On-chip USB function
Inverter control
44-pin
µ PD789842
On-chip inverter controller and UART
On-chip bus controller
44-pin
30-pin
µ PD789852
µ PD789850A
µ PD789850A with enhanced timer and A/D converter, etc.
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
µ PD789862
µ PD789861
µ PD789860
µ PD789860 with enhanced timer function, SIO, and expanded ROM and RAM
RC oscillation version of µ PD789860
On-chip POC and key return circuit
VFD drive
52-pin
µ PD789871
On-chip VFD controller (total display outputs: 25)
Meter control
64-pin
µ PD789881
UART + resistance division method LCD (26 × 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
18
User’s Manual U15043EJ3V1UD
CHAPTER 1 GENERAL
The major differences between subseries are shown below.
Series for General-Purpose and LCD Drive
Function
Subseries
Smallscale
package,
generalpurpose
applications
8-Bit 10-Bit
ROM
Timer
A/D
Capacity 8-Bit 16-Bit Watch WDT A/D
(Bytes)
µPD789046
16 K
µPD789026
4 K to 16 K
µPD789088
16 K to 32 K 3 ch
µPD789074
2 K to 8 K
1 ch
µPD789062
4K
2 ch
1 ch
1 ch
1 ch
1 ch
−
−
Serial Interface
I/O
VDD
1 ch (UART: 1 ch)
34
1.8 V
24
−
−
14
RC-oscillation
version
−
Smallscale
package,
generalpurpose
applications +
A/D
converter
µPD789177
LCD
drive
µPD789835
24 K to 60 K 6 ch
−
µPD789830
24 K
1 ch
µPD789489
32 K to 48 K 3 ch
µPD789479
24 K to 48 K
8 ch
−
µPD789417A
12 K to 24 K
−
7 ch
7 ch
−
16 K to 24 K 3 ch
1 ch
1 ch
1ch
µPD789167
−
8 ch
8 ch
−
1 ch (UART: 1 ch)
31
1.8 V
−
4 ch
4 ch
−
µPD789114A
−
4 ch
µPD789104A
4 ch
−
3 ch
−
1 ch (UART: 1 ch)
30
2.7 V
8 ch
2 ch (UART: 1 ch)
45
1.8 V
1 ch (UART: 1 ch)
43
−
2 K to 8 K 1 ch
µPD789124A
1 ch
µPD789407A
µPD789456
1 ch
1 ch
−
6 ch
−
µPD789436
−
6 ch
µPD789426
6 ch
−
−
8 K to 16 K
−
37
Note
1.8 V
Dot LCD
supported
−
30
40
2 ch (UART: 1 ch)
23
µPD789306
µPD789467
−
RC-oscillation
version
20
−
6 ch
12 K to 16 K 2 ch
µPD789446
µPD789316
−
−
µPD789052
µPD789134A
Remarks
MIN.Value
RC-oscillation
version
−
4 K to 24 K
µPD789327
−
−
1 ch
−
1 ch
18
21
Note Flash memory version: 3.0 V
User’s Manual U15043EJ3V1UD
19
CHAPTER 1 GENERAL
Series for ASSP
Function
Subseries
8-Bit 10-Bit
ROM
Timer
A/D
Capacity 8-Bit 16-Bit Watch WDT A/D
(Bytes)
Serial Interface
I/O
VDD
Remarks
MIN.Value
USB
µPD789800
8K
−
1 ch
−
−
2 ch (USB: 1 ch)
31
4.0 V
−
Inverter
control
µPD789842
8 K to 16 K 3 ch Note 1 1 ch
1 ch
8 ch
−
1 ch (UART: 1 ch)
30
4.0 V
−
On-chip
µPD789852
24 K to 32 K 3 ch
−
1 ch
−
8 ch
3 ch (UART: 2 ch)
31
4.0 V
−
bus
µPD789850A
16 K
1 ch
4 ch
−
2 ch (UART: 1 ch)
18
µPD789861
4K
2 ch
−
−
−
14
controller
Keyless
2 ch
−
1 ch
−
−
1 ch
1.8 V
entry
RC-oscillation
version,
on-chip
EEPROM
µPD789860
On-chip
µPD789862
16 K
1 ch
2 ch
VFD
drive
µPD789871
4 K to 8 K 3 ch
−
1 ch
1 ch
−
Meter
control
µPD789881
16 K
1 ch
−
1 ch
−
2 ch
22
−
1 ch
33 2.7 V
−
1 ch (UART: 1 ch)
28 2.7 V
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
20
EEPROM
1 ch (UART: 1 ch)
User’s Manual U15043EJ3V1UD
Note 2
−
−
CHAPTER 1 GENERAL
1.6 Block Diagram
TO40/P60
8-bit
timer 30 Cascaded
16-bit
8-bit
timer
timer 40
Watch timer
78K/0S
CPU core
ROM
(flash
memory)
Port 0
P00 to P03
Port 1
P10, P11
Port 2
P20 to P22
Port 4
P40 to P43
Port 6
P60, P61
Port 8
P80 to P85
Watchdog timer
SCK10/P20
SO10/P21
SI10/P22
Serial interface 10
RAM
RAM
space for
LCD data
S0 to S23
COM0 to COM3
System control
LCD
controller/driver
VLC0
RESET
X1
X2
XT1
XT2
INT/P61
Note
Interrupt control
Power-on clear
VDD
VSS
KR00/P40 to
KR03/P43
IC0
(VPP)
Note Only when use of the POC circuit is selected by a mask option in the case of the mask ROM version
(µPD789322, 789324, 789326, and 789327).
Remarks 1. The internal ROM and RAM capacities vary depending on the product.
2. The parenthesized values apply to µPD78F9328.
User’s Manual U15043EJ3V1UD
21
CHAPTER 1 GENERAL
1.7 Overview of Functions
Part Number
µPD789322
µPD789324
µPD789326
µPD789327
µPD78F9328
Item
Internal memory
ROM
Mask ROM
4 KB
High-speed RAM
256 bytes
LCD display RAM
24 × 4 bits
Flash memory
8 KB
16 KB
24 KB
32 KB
512 bytes
Main system clock (oscillation frequency)
Ceramic/crystal oscillation (1.0 to 5.0 MHz)
Subsystem clock (oscillation frequency)
Crystal oscillation (32.768 kHz)
Minimum instruction execution time
0.4 µs/1.6 µs (@ 5.0 MHz operation with main system clock)
122 µs (@ 32.768 kHz operation with subsystem clock)
General-purpose registers
Instruction set
8 bits × 8 registers
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
I/O ports
Note 1
CMOS I/O:
Timers
21
• 8-bit timer:
2 channels
• Watch timer:
1 channel
• Watchdog timer:
1 channel
Timer outputs
1
Serial interface
3-wire serial I/O mode: 1 channel
LCD controller/driver
• Segment signal outputs:
24
• Common signal outputs:
4
Note 1
• Mode: Static mode and 1/3 bias mode
Vectored interrupt
sources
Maskable
Internal: 6, external: 2
Non-maskable
Internal: 1
Reset
• Reset by RESET input
• Internal reset by watchdog timer
Note 2
• Reset by power-on-clear circuit
Note 3
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = −40 to +85°C
Package
52-pin plastic LQFP (10 × 10)
Notes
1.
Six among these pins are used to select either port function or LCD segment output via the port function
2.
register.
For mask ROM versions (µPD789322, 789324, 789326, 789327), this is available only when the use of
POC circuit is selected by mask option.
3.
22
For mask ROM versions when the use of the POC circuit is selected or for flash memory versions, the
minimum value of the operation power supply voltage is the POC detection voltage (1.9 ±0.1 V).
User’s Manual U15043EJ3V1UD
CHAPTER 1 GENERAL
An outline of the timer is shown below.
8-Bit Timer 30
Operation
mode
Function
Interval timer
8-Bit Timer 40
Watch Timer
1 channel
Note 1
Watchdog Timer
1 channel
1 channel
1 channel
External event counter
–
–
–
–
Timer outputs
–
1 output
–
–
Square-wave outputs
–
1 output
–
–
Capture
–
–
–
–
Interrupt sources
1
1
2
2
Note 2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog
timer by selecting either the watchdog timer function or interval timer function.
User’s Manual U15043EJ3V1UD
23
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
(1)
Port pins
Pin Name
P00 to P03
I/O
Function
Input/
Port 0.
output
This is a 4-bit I/O port.
After Reset
Alternate Function
Input
−
Input
−
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be
specified in port units using pull-up resistor option register 0
(PU0).
P10, P11
Input/
Port 1.
output
This is a 2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be
specified in port units using pull-up resistor option register 0
(PU0).
P20
P21
Input/
Port 2.
output
This is a 3-bit I/O port.
Input
SO10
Input/output can be specified in 1-bit units.
P22
SCK10
SI10
On-chip pull-up resistors can be specified in 1-bit units using
pull-up resistor option register 2 (PUB2).
P40 to P43
Input/
Port 4.
output
This is a 4-bit I/O port.
Input
KR00 to KR03
Input
TO40
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be
specified in port units using pull-up resistor option register 0
(PU0), or key return mode register 00 (KRM00).
P60
P61
P80 to P85
Input/
Port 6.
output
This is a 2-bit I/O port.
Input/
Port 8.
output
This is a 6-bit I/O port.
Input
Input/output can be specified in 1-bit units.
24
INT
Input/output can be specified in 1-bit units.
User’s Manual U15043EJ3V1UD
S22 to S17
CHAPTER 2 PIN FUNCTIONS
(2)
Non-port pins
Pin Name
INT
I/O
Input
Function
External interrupt input for which the valid edge (rising edge,
After Reset
Alternate Function
Input
P61
falling edge, or both rising and falling edges) can be specified.
KR00 to KR03
Input
Key return signal detection
Input
P40 to P43
TO40
Output
8-bit timer 40 output
Input
P60
SCK10
Input/
Serial clock input/output of serial interface 10
Input
P20
output
SI10
Input
Serial data input of serial interface 10
Input
P22
SO10
Output
Serial data output of serial interface 10
Input
P21
S0 to S16
Output
LCD controller/driver segment signal outputs
Low-level
−
output
S17 to S22
Input
P85 to P80
S23
Low-level
−
output
COM0 to COM3
Output
LCD controller/driver common signal outputs
Low-level
−
output
VLC0
−
X1
Input
X2
−
XT1
Input
XT2
−
RESET
Input
LCD drive voltage
−
−
Connecting crystal/ceramic resonator for main system clock
−
−
oscillation
−
−
Connecting crystal resonator for subsystem clock oscillation
−
−
−
−
System reset input
−
Input
VDD
−
Positive power supply
−
−
VSS
−
Ground potential
−
−
IC0
−
Internally connected. Connect directly to VSS.
−
−
VPP
–
Sets flash memory programming mode. Applies high voltage
−
−
when a program is written or verified.
User’s Manual U15043EJ3V1UD
25
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode
register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
2.2.2 P10, P11 (Port 1)
These pins constitute a 2-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode
register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
2.2.3 P20 to P22 (Port 2)
These pins constitute a 3-bit I/O port. In addition, these pins enable serial interface data I/O and clock I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1)
Port mode
In this mode, P20 to P22 function as a 3-bit I/O port. Port 2 can be set in the input or output port mode in 1bit units by port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified by pull-up resistor
option register B2 (PUB2) in 1-bit units.
(2)
Control mode
In this mode, P20 to P22 function as the serial interface data I/O and clock I/O.
(a)
SI10, SO10
These are the serial data I/O pins of the serial interface.
(b)
SCK10
This is the serial clock I/O pin of the serial interface.
Caution When using P20 to P22 as serial interface pins, the I/O mode and output latch must be
set according to the functions to be used. For the details of the setting, refer to Table
9-2 Settings of Serial Interface 10 Operating Mode.
2.2.4 P40 to P43 (Port 4)
These pins constitute a 4-bit I/O port. In addition, they also function as key return signal detection.
Port 4 can be specified in the following operation mode in 1-bit units.
(1)
Port mode
In this mode, port 4 functions as a 4-bit I/O port. Port 4 can be set in the input or output port mode in 1-bit
units by port mode register 4 (PM4). When used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00) in port units.
(2)
Control mode
In this mode, the pins function as key return signal detection (KR00 to KR03).
26
User’s Manual U15043EJ3V1UD
CHAPTER 2 PIN FUNCTIONS
2.2.5 P60, P61 (Port 6)
These pins constitute a 2-bit I/O port. In addition, they also function as timer output and external interrupt input.
Port 6 can be specified in the following operation mode in 1-bit units.
(1)
Port mode
In this mode, port 6 functions as a 2-bit I/O port. Port 6 can be set in the input or output port mode in 1-bit
units by port mode register 6 (PM6).
(2)
Control mode
In this mode, the pins function as timer output and external interrupt input.
(a)
TO40
This is the timer output pin to timer 40.
(b)
INT
This is the external interrupt input pin for which valid edges (rising edge, falling edge, or both rising and
falling edges) can be specified.
2.2.6 P80 to P85 (Port 8)
These pins constitute a 6-bit I/O port. In addition, they also function as LCD controller/driver segment signal output.
Port 8 can be specified in the following operation mode in 1-bit units by port function register 8 (PF8).
(1)
Port mode
In this mode, port 8 functions as a 6-bit I/O port. Port 8 can be set in the input or output port mode in 1-bit
units by port mode register 8 (PM8).
(2)
Control mode
In this mode, the pins function as LCD controller/driver segment signal output (S17 to S22).
2.2.7 S0 to S16, S23
These pins are segment signal output pins for the LCD controller/driver.
2.2.8 COM0 to COM3
These pins are common signal output pins for the LCD controller/driver.
2.2.9 VLC0
This pin is the power supply voltage pin to drive the LCD.
2.2.10 RESET
This pin inputs an active-low system reset signal.
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CHAPTER 2 PIN FUNCTIONS
2.2.11 X1, X2
These pins are used to connect a crystal/ceramic resonator for main system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.12 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
2.2.13 VDD
This is the positive power supply pin.
2.2.14 VSS
This is the ground pin.
2.2.15 VPP (µPD78F9328 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Perform either of the following.
• Independently connect a 10 kΩ pull-down resistor to VPP.
• Use the jumper on the board to connect VPP to the dedicated flash programmer or VSS, in programming mode or
normal operation mode, respectively.
If the wiring between the VPP and VSS pins is long or external noise is superimposed on the VPP pin, the
userprogram may not run correctly.
2.2.16 IC0 (mask ROM version only)
The IC0 (Internally Connected) pin is used to set the µPD789322, 789324, 789326, and 789327 in the test mode
before shipment. In the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as
possible.
If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length, or an external
noise superimposed on the IC0 pin, the user program may not run correctly.
• Directly connect the IC0 pin to the VSS pin.
VSS IC0
Keep short
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the input/output circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name
P00 to P03
I/O Circuit Type
5-A
I/O
I/O
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P10, P11
P20/SCK10
Recommended Connection of Unused Pins
8-A
P21/SO10
P22/SI10
P40/KR00 to P43/KR03
P60/TO40
5
P61/INT
8
Input:
Independently connect to VSS via a resistor.
Output: Leave open.
P80/S22 to P85/S17
17-N
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
Output
Leave open.
−
Connect to VDD
XT1
Input
Connect to VSS.
XT2
−
S0 to S16, S23
17-D
COM0 to COM3
18-B
−
VLC0
RESET
2
Input
IC0 (mask ROM version)
−
−
VPP (µPD78F9328)
Note
.
Leave open.
−
Connect directly to VSS.
Independently connect VPP to a 10 kΩ pull-down resistor or directly
connect to VSS.
Note The current flows from VLC0 to VSS via the LCD division resistors.
Figure 2-1. I/O Circuit Type (1/2)
Type 2
Type 5
VDD
Data
P-ch
IN
IN/OUT
Output
disable
Schmitt-triggered input with hysteresis characteristics.
N-ch
VSS
Input
enable
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. I/O Circuit Type (2/2)
Type 5-A
Type 8
VDD
Pull-up
enable
VDD
P-ch
Data
VDD
P-ch
IN/OUT
Data
P-ch
IN/OUT
Output
disable
Output
disable
N-ch
VSS
N-ch
VSS
Input
enable
Type 8-A
Type 17-D
VDD
VLC0
P-ch
Pull-up
enable
P-ch
VLC1
P-ch
N-ch
VDD
Data
P-ch
SEG
data
P-ch
OUT
N-ch
IN/OUT
Output
disable
P-ch
N-ch
VLC2
N-ch
N-ch
VSS
VSS
Type 17-N
Type 18-B
VLC0
Data
P-ch
IN/OUT
Output
disable
N-ch
VDD VSS
VLC0
Input
enable
VLC1
P-ch
P-ch
N-ch
P-ch
N-ch
VLC0
P-ch
VLC1
P-ch
N-ch
P-ch
N-ch
VLC2
N-ch
SEG
data
N-ch
VSS
P-ch
N-ch
VLC2
N-ch
VSS
Remark VLC1: VLC0 × 2/3, VLC2: VLC0/3
30
OUT
COM
data
P-ch
N-ch
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The µPD789327 Subseries can access 64 KB of memory space. Figures 3-1 through 3-5 show the memory maps.
Figure 3-1. Memory Map (µPD789322)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
FA18H
FA17H
Data
memory space
Reserved
LCD display RAM
24 × 4 bits
FA00H
F9FFH
0FFFH
Reserved
1000H
0FFFH
Program area
Program
memory space
Internal ROM
4096 × 8 bits
0080H
007FH
CALLT table area
0040H
003FH
Program area
0014H
0013H
0000H
0000H
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Vector table area
31
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (µPD789324)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
FA18H
FA17H
Data
memory space
Reserved
LCD display RAM
24 × 4 bits
FA00H
F9FFH
2000H
1FFFH
1FFFH
Reserved
Program area
Program
memory space
Internal ROM
8192 × 8 bits
0080H
007FH
CALLT table area
0040H
003FH
Program area
0014H
0013H
0000H
32
0000H
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Vector table area
CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (µPD789326)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
FA18H
FA17H
Data
memory space
Reserved
LCD display RAM
24 × 4 bits
FA00H
F9FFH
4000H
3FFFH
3FFFH
Reserved
Program area
Program
memory space
Internal ROM
16384 × 8 bits
0080H
007FH
CALLT table area
0040H
003FH
Program area
0014H
0013H
0000H
0000H
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Vector table area
33
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (µPD789327)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Reserved
FA18H
FA17H
Data
memory space
LCD display RAM
24 × 4 bits
FA00H
F9FFH
5FFFH
Reserved
6000H
5FFFH
Program area
Program
memory space
Internal ROM
24576 × 8 bits
0080H
007FH
CALLT table area
0040H
003FH
Program area
0014H
0013H
0000H
0000H
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Vector table area
CHAPTER 3 CPU ARCHITECTURE
Figure 3-5. Memory Map (µPD78F9328)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Reserved
FA18H
FA17H
Data
memory space
LCD display RAM
24 × 4 bits
FA00H
F9FFH
7FFFH
Reserved
8000H
7FFFH
Program area
Program
memory space
Flash memory
32768 × 8 bits
0080H
007FH
CALLT table area
0040H
003FH
Program area
0014H
0013H
0000H
0000H
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Vector table area
35
CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The µPD789327 Subseries provide internal ROM (or flash memory) with the following capacity for each product.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
µPD789322
Capacity
4096 × 8 bits
Mask ROM
µPD789324
8192 × 8 bits
µPD789326
16384 × 8 bits
µPD789327
24576 × 8 bits
µPD78F9328
32768 × 8 bits
Flash memory
The following areas are allocated to the internal program memory space.
(1)
Vector table area
The 20-byte area of addresses 0000H to 0013H is reserved as a vector table area. This area stores program
start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an
odd address.
Table 3-2. Vector Table
Vector Table Address
Interrupt Request
Vector Table Address
Interrupt Request
0000H
RESET input
000CH
INTTM30
0004H
INTWDT
000EH
INTTM40
0006H
INTP0
0010H
INTKR00
0008H
INTCSI10
0012H
INTWTI
000AH
INTWT
(2)
CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
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CHAPTER 3 CPU ARCHITECTURE
3.1.2 Internal data memory (internal high-speed RAM) space
The µPD789327 Subseries products incorporate the following RAM.
(1)
Internal high-speed RAM
Internal high-speed RAM is incorporated in the area between FE00H and FEFFH in the µPD789322 and
789324, and in the area between FD00H and FEFFH in the µPD789326, 789327, and 78F9328.
Instructions cannot be written to this on-chip high-speed RAM as a program area for execution.
The internal high-speed RAM is also used as a stack.
(2)
LCD display RAM
LCD display RAM is allocated in the area between FA00H and FA17H. The LCD display RAM can also be
used as ordinary RAM.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H and
FFFFH (see Table 3-3).
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CHAPTER 3 CPU ARCHITECTURE
3.1.4 Data memory addressing
The µPD789327 Subseries are provided with a variety of addressing modes to make memory manipulation as
efficient as possible. At the addresses corresponding to data memory area especially, specific addressing modes that
correspond to the particular function an area, such as the special function registers are available. Figures 3-6 through
3-10 show the data memory addressing modes.
Figure 3-6. Data Memory Addressing (µPD789322)
FFFFH
Special function registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
256 × 8 bits
FE20H
FE1FH
Direct addressing
FE00H
FDFFH
Register indirect
addressing
Reserved
FA18H
FA17H
Based addressing
LCD display RAM
24 × 4 bits
FA00H
F9FFH
Reserved
1000H
0FFFH
Internal ROM
4096 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Data Memory Addressing (µPD789324)
FFFFH
Special function registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
256 × 8 bits
FE20H
FE1FH
Direct addressing
FE00H
FDFFH
Register indirect
addressing
Reserved
FA18H
FA17H
Based addressing
LCD display RAM
24 × 4 bits
FA00H
F9FFH
Reserved
2000H
1FFFH
Internal ROM
8192 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-8. Data Memory Addressing (µPD789326)
FFFFH
Special function registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
Direct addressing
FD00H
FCFFH
Register indirect
addressing
Reserved
FA18H
FA17H
Based addressing
LCD display RAM
24 × 4 bits
FA00H
F9FFH
Reserved
4000H
3FFFH
Internal ROM
16384 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-9. Data Memory Addressing (µPD789327)
FFFFH
Special function registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
Direct addressing
FD00H
FCFFH
Register indirect
addressing
Reserved
FA18H
FA17H
Based addressing
LCD display RAM
24 × 4 bits
FA00H
F9FFH
Reserved
6000H
5FFFH
Internal ROM
24576 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-10. Data Memory Addressing (µPD78F9328)
FFFFH
Special function registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
Direct addressing
FD00H
FCFFH
Register indirect
addressing
Reserved
FA18H
FA17H
Based addressing
LCD display RAM
24 × 4 bits
FA00H
F9FFH
Reserved
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The µPD789327 Subseries provide the following on-chip processor registers.
3.2.1 Control registers
The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1)
Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-11. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10
(2)
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
The program status word contents are automatically stacked upon interrupt request generation or PUSH
PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW
instructions.
RESET input sets PSW to 02H.
Figure 3-12. Program Status Word Configuration
7
PSW
IE
0
Z
0
AC
0
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0
1
CY
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CHAPTER 3 CPU ARCHITECTURE
(a)
Interrupt enable flag (IE)
This flag controls interrupt request acknowledgement operations of the CPU.
When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable
interrupt are all disabled.
When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgement enable is
controlled with an interrupt mask flag for various interrupt sources.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b)
Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c)
Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d)
Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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CHAPTER 3 CPU ARCHITECTURE
(3)
Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-13. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution
Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-14. Data to Be Saved to Stack Memory
PUSH rp
instruction
Interrupt
CALL, CALLT
instructions
SP
SP
SP _ 2
SP
SP _ 2
SP _ 3
SP _ 3
PC7 to PC0
SP _ 2
Lower
register pairs
SP _ 2
PC7 to PC0
SP _ 2
PC15 to PC8
SP _ 1
Higher
register pairs
SP _ 1
PC15 to PC8
SP _ 1
PSW
SP
SP
SP
Figure 3-15. Data to Be Restored from Stack Memory
POP rp
instruction
SP
RETI instruction
RET instruction
SP
Lower
register pairs
SP
PC7 to PC0
SP
PC7 to PC0
SP + 1
Higher
register pairs
SP + 1
PC15 to PC8
SP + 1
PC15 to PC8
SP + 2
PSW
SP + 2
SP
SP + 2
SP
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CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL)
or absolute names (R0 to R7 and RP0 to RP3).
Figure 3-16. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
8-bit processing
R7
RP3
R6
R5
RP2
R4
R3
RP1
R2
R1
RP0
R0
15
0
7
0
(b) Function names
16-bit processing
8-bit processing
H
HL
L
D
DE
E
B
BC
C
A
AX
X
15
46
0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
The special function registers are allocated in the 256-byte area of FF00H to FFFFH.
Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit
manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
The manipulatable bits can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand.
When
addressing an address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. The symbols shown in this column are
reserved for the assembler and are defined as an sfr variable by the #pragma sfr directive for the C compiler.
Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special function register in question can be read or written.
R/W:
Read/write
R:
Read only
W:
Write only
• Bit unit for manipulation
Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Registers (1/2)
Address
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit Unit for Manipulation
1 Bit
8 Bits
16 Bits
√
√
−
After
Reset
00H
FF00H
Port 0
P0
FF01H
Port 1
P1
√
√
−
FF02H
Port 2
P2
√
√
−
FF04H
Port 4
P4
√
√
−
FF06H
Port 6
P6
√
√
−
FF08H
Port 8
P8
√
√
−
FF20H
Port mode register 0
PM0
√
√
−
FF21H
Port mode register 1
PM1
√
√
−
FF22H
Port mode register 2
PM2
√
√
−
FF24H
Port mode register 4
PM4
√
√
−
FF26H
Port mode register 6
PM6
√
√
−
FF28H
Port mode register 8
PM8
√
√
−
3FH
FF32H
Pull-up resistor option register B2
PUB2
√
√
−
00H
FF42H
Watchdog timer clock selection register
TCL2
–
√
−
FF4AH
Watch timer mode control register
WTM
√
√
−
FF58H
Port function register 8
PF8
√
√
−
FF63H
8-bit compare register 30
CR30
W
−
√
−
Undefined
FF64H
8-bit timer counter 30
TM30
R
−
√
−
00H
FF65H
8-bit timer mode control register 30
TMC30
R/W
√
√
−
FF66H
8-bit compare register 40
CR40
W
−
√
−
FF67H
8-bit H width compare register 40
CRH40
−
√
−
FF68H
8-bit timer counter 40
TM40
R
−
√
−
FF69H
8-bit timer mode control register 40
TMC40
R/W
√
√
−
FF6AH
Carrier generator output control register 40
TCA40
W
−
√
−
FF72H
Serial operation mode register 10
CSIM10
R/W
√
√
−
FF74H
Transmission/reception shift register 10
SIO10
√
√
−
Undefined
FFB0H
LCD display mode register 0
LCDM0
√
√
−
00H
FFB2H
LCD clock control register 0
LCDC0
√
√
−
POCF1
√
√
−
FFDDH Power-on-clear register 1
Note This value is 04H only after a power-on-clear reset.
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FFH
Undefined
00H
Note
00H
CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Registers (2/2)
Address
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit Unit for Manipulation
After
Reset
1 Bit
8 Bits
16 Bits
√
√
−
00H
FFE0H
Interrupt request flag register 0
IF0
FFE4H
Interrupt mask flag register 0
MK0
√
√
−
FFH
FFECH External interrupt mode register 0
INTM0
√
√
−
00H
FFF0H
Suboscillation mode register
SCKM
√
√
−
FFF2H
Subclock control register
CSS
√
√
−
FFF5H
Key return mode register 00
KRM00
√
√
−
FFF7H
Pull-up resistor option register 0
PU0
√
√
−
FFF9H
Watchdog timer mode register
WDTM
√
√
−
FFFAH Oscillation stabilization time selection register
OSTS
√
√
−
04H
FFFBH Processor clock control register
PCC
√
√
−
02H
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is set
to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series
Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched.
The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
This means that information is relatively branched to a location between –128 and +127, from the start address
of the next instruction when relative addressing is used.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC is the start address of
PC
the next instruction of
a BR instruction.
+
15
8
α
7
0
6
S
jdisp8
15
0
PC
When S = 0, α indicates all bits 0.
When S = 1, α indicates all bits 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
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CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
7
Instruction code
6
0
5
1
1
ta4–0
0
15
Effective address
0
7
0
0
0
0
0
0
0
Memory (Table)
8
7
6
0
0
1
5
1 0
0
0
Low Addr.
High Addr.
Effective address + 1
8
15
7
0
PC
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
rp
0
7
A
15
X
8
7
PC
52
0
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CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated with immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
1
0
0
1
OP code
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7
0
OP code





addr16 (Lower)
addr16 (Higher)
Memory
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3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed
RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.
Ports that are frequently accessed in a program and the compare register of the timer counter are mapped in
this area, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
Description
saddr
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
1
1
0
1
0
1
OP code
1
0
0
1
0
0
0
0
90H (saddr-offset)
0
1
0
1
0
0
0
0
50H (Immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
8
15
Effective
address
1
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
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3.4.3 Special function register (SFR) addressing
[Function]
The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an
instruction word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier
Description
sfr
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
Effective
address
1
8 7
1
1
1
1
1
1
0
1
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3.4.4 Register addressing
[Function]
In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose
register to be accessed is specified by a register specification code or functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specification code
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3.4.5 Register indirect addressing
[Function]
In the register indirect addressing mode, memory is manipulated according to the contents of a register pair
specified as an operand. The register pair to be accessed is specified by the register pair specification code in
an instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
DE
8 7
D
0
E
7
Addressed memory
contents are
transferred.
7
0
Memory address
specified with
register pair DE.
0
A
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3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
−
Description
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon generation of an interrupt request.
Only the internal high-speed RAM area can be addressed using stack addressing.
[Description example]
In the case of PUSH DE
Instruction code
58
1
0
1
0
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0
1
0
CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The µPD789327 Subseries provide the ports shown in Figure 4-1, enabling various methods of control.
Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more
information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P00
P40
Port 4
Port 6
Port 0
P43
P03
P60
P61
P10
P11
P80
P20
Port 1
Port 2
P22
Port 8
P85
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Table 4-1. Port Functions
Port Name
Port 0
Pin Name
P00 to P03
Function
This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be specified using pull-up
resistor option register 0 (PU0).
Port 1
P10, P11
This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be specified using pull-up
resistor option register 0 (PU0).
Port 2
P20 to P22
This is an I/O port for which input and output can be specified in 1-bit units.
On-chip pull-up resistors can be specified using pull-up resistor option register B2
(PUB2).
Port 4
P40 to P43
This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be specified using pull-up
resistor option register 0 (PU0), or key return mode register 00 (KRM00).
Port 6
P60, P61
This is an I/O port for which input and output can be specified in 1-bit units.
Port 8
P80 to P85
This is an I/O port for which input and output can be specified in 1-bit units.
4.2 Port Configuration
The ports include the following hardware.
Table 4-2. Configuration of Port
Item
Control registers
Configuration
Port mode registers (PMm: m = 0 to 2, 4, 6, 8)
Pull-up resistor option registers (PU0, PUB2)
Port function register 8 (PF8)
Ports
Total: 21 (CMOS I/O: 21)
Pull-up resistors
Total: 13 (software control: 13)
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4.2.1 Port 0
Port 0 is a 4-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using
the port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can
be connected in 4-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 0 in the input mode.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P03
VDD
WRPU0
PU00
P-ch
Selector
Internal bus
RD
WRPORT
Output latch
(P00 to P03)
P00 to P03
WRPM
PM00 to PM03
PU0:
Pull-up resistor option register 0
PM:
Port mode register
RD:
Port 0 read signal
WR:
Port 0 write signal
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4.2.2 Port 1
Port 1 is a 2-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using
port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be
connected in 2-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 1 in the input mode.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3. Block Diagram of P10 and P11
VDD
WRPU0
PU01
P-ch
Selector
Internal bus
RD
WRPORT
Output latch
(P10, P11)
P10, P11
WRPM
PM10, PM11
62
PU0:
Pull-up resistor option register 0
PM:
Port mode register
RD:
Port 1 read signal
WR:
Port 1 write signal
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4.2.3 Port 2
Port 2 is a 3-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using
port mode register 2 (PM2). On-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option
register B2 (PUB2) regardless of whether the port is in the input or output mode.
The port is also used as a data I/O to and from the serial interface.
RESET input sets port 2 in the input mode.
Figures 4-4 to 4-6 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 9-2 Settings of Serial
Interface 10 Operating Mode.
Figure 4-4. Block Diagram of P20
VDD
WRPUB2
PUB20
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P20)
P20/SCK10
WRPM
PM20
Alternate
function
PUB2:
Pull-up resistor option register B2
PM:
Port mode register
RD:
Port 2 read signal
WR:
Port 2 write signal
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Figure 4-5. Block Diagram of P21
VDD
WRPUB2
PUB21
P-ch
Selector
Internal bus
RD
WRPORT
Output latch
(P21)
P21/SO10
WRPM
PM21
Alternate
function
64
PUB2:
Pull-up resistor option register B2
PM:
Port mode register
RD:
Port 2 read signal
WR:
Port 2 write signal
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Figure 4-6. Block Diagram of P22
VDD
WRPUB2
PUB22
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P22)
P22/SI10
WRPM
PM22
PUB2:
Pull-up resistor option register B2
PM:
Port mode register
RD:
Port 2 read signal
WR:
Port 2 write signal
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4.2.4 Port 4
Port 4 is a 4-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using
port mode register 4 (PM4). When using the P40 to P43 pins as input port pins, on-chip pull-up resistors can be
connected in 4-bit units by using pull-up resistor option register 0 (PU0).
This port is also used as a key return.
RESET input sets port 4 in the input mode.
Figure 4-7 shows block diagram of port 4.
Figure 4-7. Block Diagram of P40 to P43
VDD
WRPU0
PU04
P-ch
Selector
RD
WRKRM00
Internal bus
KRM000
WRPORT
Output latch
(P40 to P43)
P40/KR00 to
P43/KR03
WRPM
PM40 to PM43
Alternate function
KRM00: Key return mode register 00
66
PU0:
Pull-up resistor option register 0
PM:
Port mode register
RD:
Port 4 read signal
WR:
Port 4 write signal
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4.2.5 Port 6
Port 6 is a 2-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using
port mode register 6 (PM6).
This port is also used as a timer output and external interrupt input.
RESET input sets port 6 in the input mode.
Figures 4-8 and 4-9 show block diagrams of port 6.
Figure 4-8. Block Diagram of P60
Internal bus
Selector
RD
WRPORT
Output latch
(P60)
P60/TO40
WRPM
PM60
Alternate
function
PM:
Port mode register
RD:
Port 6 read signal
WR:
Port 6 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-9. Block Diagram of P61
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P61)
P61/INT
WRPM
PM61
68
PM:
Port mode register
RD:
Port 6 read signal
WR:
Port 6 write signal
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4.2.6 Port 8
Port 8 is a 6-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using
port mode register 8 (PM8).
This port is also used as a segment output, and can be switched to the port function or segment output function in
1-bit units by port function register 8 (PF8).
RESET input sets port 8 in the input mode.
Figure 4-10 shows a block diagram of port 8.
Figure 4-10. Block Diagram of P80 to P85
RD
Selector
VDD
WRPORT
VLC0
Level
shifter
Internal bus
Output latch
(P80 to P85)
P80/S22 to
P85/S17
WRPM
PM80 to PM85
WRPF
PF80 to PF85
VLC0
Level
shifter
Alternate
function
PF:
Port function register
RD:
Port 8 read signal
WR:
Port 8 write signal
Caution
When using port 8 as an output port, the high-level output voltage is VLC0, not VDD. When a high
level is output from the output port, pay attention to the current capacity.
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CHAPTER 4 PORT FUNCTIONS
4.3 Registers Controlling Port Function
The ports are controlled by the following three types of registers.
• Port mode registers (PM0 to PM2, PM4, PM6, PM8)
• Pull-up resistor option registers (PU0, PUB2)
• Port function register 8 (PF8)
(1)
Port mode registers (PM0 to PM2, PM4, PM6, PM8)
PM0 to PM2, PM4, PM6 and PM8 are used to set port input/output in 1-bit units.
The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM0, PM1, PM2, PM4, and PM6 to FFH, and PM8 to 3FH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 4-3.
Caution As P61 has an alternate function as external interrupt input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. When
the output mode is used, therefore, the interrupt mask flag (PMK0) should be preset to 1.
Figure 4-11. Format of Port Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
PM1
1
1
1
1
1
1
PM11
PM10
FF21H
FFH
R/W
PM2
1
1
1
1
1
PM22
PM21
PM20
FF22H
FFH
R/W
PM4
1
1
1
1
PM43
PM42
PM41
PM40
FF24H
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FF26H
FFH
R/W
PM8
0
0
PM85
PM84
PM83
PM82
PM81
PM80
FF28H
3FH
R/W
PMmn
Pmn pin input/output mode selection
(m = 0 to 2, 4, 6, 8 n = 0 to 5)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Cautions 1. Bits 4 to 7 of PM0, bits 2 to 7 of PM1, bits 3 to 7 of PM2, bits 4 to 7 of PM4, and bits 2 to 7 of
PM6 must be set to 1.
2. Bits 6 and 7 of PM8 must be set to 0.
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Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions
Pin Name
PM××
P××
Input
1
×
Output
0
1
Alternate Function
Name
P20
I/O
SCK10
P21
SO10
Output
0
1
P22
SI10
Input
1
×
P40 to P43
KR00 to KR03
Input
1
×
P60
TO40
Output
0
0
P61
INT
Input
1
×
Output
×
×
S22 to S17
P80 to P85
Note
Note When using P80 to P85 pins as S22 to S17, set port function register 8 (PF8) to 3FH.
Caution When port 2 is used as a serial interface pin, the I/O latch or output latch must be set according
to its function. For the setting method, see Table 9-2 Settings of Serial Interface 10 Operating
Mode.
Remark
(2)
×:
don’t care
PM××:
P××:
Port mode register
Port output latch
Pull-up resistor option register 0 (PU0)
PU0 sets whether an on-chip pull-up resistor on ports 0, 1, and 4 is used or not in port units. On the port
specified to use an on-chip pull-up resistor by PU0, the pull-up resistor can be internally used only for the bits
set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless
of the setting of PU0. This also applies to cases when the pins are used for alternate functions.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Figure 4-12. Format of Pull-up Resistor Option Register 0
Symbol
7
6
5
<4>
3
2
<1>
<0>
Address
After reset
R/W
PU0
0
0
0
PU04
0
0
PU01
PU00
FFF7H
00H
R/W
PU0m
Pm on-chip pull-up resistor selection
(m = 0, 1, 4)
0
On-chip pull-up resistor not used
1
On-chip pull-up resistor used
Caution Bits 2, 3, and 5 to 7 must be set to 0.
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CHAPTER 4 PORT FUNCTIONS
(3)
Pull-up resistor option register B2 (PUB2)
PUB2 sets whether on-chip pull-up resistors on P20 to P22 are used or not in bit units. A pin for which use of
an on-chip pull-up resistor is specified by PUB2 can be connected to the pull-up resistor regardless of
whether the pin is in the input or output mode. The same applies when the alternate function of the pin is
used.
PUB2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PUB2 to 00H.
Figure 4-13. Format of Pull-up Resistor Option Register B2
Symbol
7
6
5
4
3
<2>
<1>
<0>
Address
After reset
R/W
PUB2
0
0
0
0
0
PUB22
PUB21
PUB20
FF32H
00H
R/W
PUB2n
P2n on-chip pull-up resistor selection
(n = 0 to 2)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
Cautions 1. Bits 3 to 7 must be set to 0.
2. Clear PUB2n to 0 when using P2n in the output mode or using it as an alternate function
output pin. Otherwise, it always outputs a high level.
(4)
Port function register 8 (PF8)
PF8 sets the port function of port 8 in 1-bit units.
The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according
to the setting of PF8.
PF8 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PF8 to 00H.
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Figure 4-14. Format of Port Function Register 8
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PF8
0
0
PF85
PF84
PF83
PF82
PF81
PF80
FF58H
00H
R/W
PF8n
P8n port function (n = 0 to 5)
0
Operates as a general-purpose port
1
Operates as an LCD segment signal output
Cautions 1. Bits 6 and 7 must be set to 0.
2. When port 8 is used as a general-purpose port, observe the following restriction
(because an ESD protection circuit for LCD pins (on the high-level side of port 8) is
connected to VLC0).
• When any one of pins P80/S22 to P85/S17 is used as a general-purpose input port pin,
use the microcontroller at VDD = VLC0 or VDD < VLC0.
There is no restriction when all of pins P80/S22 to P85/S17 are used as LCD segment
pins or general-purpose output port pins.
VLC0
P8n output signal
P-ch
VLC0
If a voltage higher than VLC0 is
input to the P8n/Sm pin, the
current flows from the pin to VLC0.
As a result, the voltage of VLC0
becomes unstable.
N-ch
PM8n
VSS
Segment buffer
P8n/Sm
Sm output signal
VDD
P8n input signal
VSS
PF8n
Remark Sm:
VSS
RD
LCD segment output (m = 22 to 17)
P8n:
Bit n of Port 8 (n = 0 to 5)
PF8n:
Bit n of Port function register 8 (n = 0 to 5)
RD:
Port 8 read signal
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CHAPTER 4 PORT FUNCTIONS
4.4 Port Function Operation
The operation of a port differs depending on whether the port is set in the input or output mode, as described
below.
4.4.1 Writing to I/O port
(1)
In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Data once written to the output latch is retained until new data is written to the output latch.
(2)
In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
Data once written to the output latch is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units.
When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
4.4.2 Reading from I/O port
(1)
In output mode
The status of an output latch can be read by using a transfer instruction. The contents of the output latch are
not changed.
(2)
In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
4.4.3 Arithmetic operation of I/O port
(1)
In output mode
An arithmetic operation can be performed with the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Data once written to the output latch is retained until new data is written to the output latch.
(2)
In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units.
When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
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CHAPTER 5 CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
• Main system clock (ceramic/crystal) oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
5.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Control registers
Configuration
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillators
Main system clock oscillator
Subsystem clock oscillator
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CHAPTER 5 CLOCK GENERATOR
Figure 5-1. Block Diagram of Clock Generator
Internal bus
FRC SCC Suboscillation mode register
(SCKM)
XT1
XT2
Subsystem
clock
oscillator
fXT
Watch timer
LCD controller/driver
1/2
X1
X2
Main system fX
clock
oscillator
Clock to peripheral
hardware
Prescaler
fX
22
Standby
controller
Selector
fXT
2
STOP
CLS CSS0
MCC PCC1
Processor clock
control register
(PCC)
Subclock control
register (CSS)
Internal bus
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Wait
controller
CPU clock
(fCPU)
CHAPTER 5 CLOCK GENERATOR
5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following three registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1)
Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Symbol
<7>
6
5
4
3
2
1
0
Address
After reset
R/W
PCC
MCC
0
0
0
0
0
PCC1
0
FFFBH
02H
R/W
MCC
Control of main system clock oscillator operation
0
Operation enabled
1
Operation disabled
CSS0
PCC1
CPU clock (fCPU) selection
Note
Maximum instruction execution time: 2/fCPU
fX = 5.0 MHz or fXT = 32.768 kHz operation
0.4 µs
0
0
fX
0
1
fX/2
2
1.6 µs
1
×
fXT/2
122 µs
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 5.3 (3) Subclock
control register (CSS)).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU
clock.
Setting MCC to 1 while the main system clock is operating is invalid.
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. ×:
Don’t care
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CHAPTER 5 CLOCK GENERATOR
(2)
Suboscillation mode register (SCKM)
SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SCKM to 00H.
Figure 5-3. Format of Suboscillation Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
SCKM
0
0
0
0
0
0
FRC
SCC
FFF0H
00H
R/W
FRC
Feedback resistor selection
0
On-chip feedback resistor used
1
On-chip feedback resistor not used
SCC
Note
Control of subsystem clock oscillator operation
0
Operation enabled
1
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the
mid point of the supply voltage. Only when the subclock is not used, the power consumption in STOP
mode can be further reduced by setting FRC = 1.
Caution
(3)
Bits 2 to 7 must be set to 0.
Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSS to 00H.
Figure 5-4. Format of Subclock Control Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
CSS
0
0
CLS
CSS0
0
0
0
0
FFF2H
00H
R/W
CLS
CPU clock operation status
0
Operation based on the output of the divided main system clock
1
Operation based on the subsystem clock
CSS0
Selection of the main system or subsystem clock oscillator
0
Divided output from the main system clock oscillator
1
Output from the subsystem clock oscillator
Note Bit 5 is read only.
Caution
78
Bits 0 to 3, 6, and 7 must be set to 0.
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CHAPTER 5 CLOCK GENERATOR
5.4 System Clock Oscillators
5.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected
across the X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 5-5 shows the external circuit of the main system clock oscillator.
Figure 5-5. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
External
clock
VSS
X1
X1
X2
X2
Crystal
or
ceramic resonator
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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CHAPTER 5 CLOCK GENERATOR
5.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the
inverted signal to the XT2 pin.
Figure 5-6 shows the external circuit of the subsystem clock oscillator.
Figure 5-6. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
External
clock
VSS
XT1
32.768
kHz
XT1
XT2
XT2
Crystal resonator
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock, particular care is required because the subsystem clock
oscillator is designed as a low-amplitude circuit for reducing current consumption.
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CHAPTER 5 CLOCK GENERATOR
5.4.3 Example of incorrect resonator connection
Figure 5-7 shows examples of incorrect resonator connection.
Figure 5-7. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORTn
(n = 0 to 2, 4, 6, 8)
VSS
X1
VSS
X2
(c) Wiring near high fluctuating current
X1
X2
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
VSS
X1
X2
VSS
X1
X2
B
C
High current
A
High current
Remark
When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to the XT2 in series.
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CHAPTER 5 CLOCK GENERATOR
Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signal is fetched
(f) Parallel and near signal lines of main system clock
and subsystem clock
VSS
VSS
X1
X2
X1
XT2
XT1
X2
XT2 is wired parallel to X1.
Remark
When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to the XT2 in series.
Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between the X1 and XT2,
resulting in a malfunction.
To avoid this, do not lay the X1 and XT2 wires in parallel.
5.4.4 Divider circuit
The divider circuit divides the output of the main system clock oscillator (fX) to generate various clocks.
5.4.5 When no subsystem clock is used
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows:
XT1: Connect to VSS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
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CHAPTER 5 CLOCK GENERATOR
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock
fX
• Subsystem clock
fXT
• CPU clock
fCPU
• Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a)
The low-speed mode (1.6 µs: at 5.0 MHz operation) of the main system clock is selected when the
RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the
main system clock is stopped.
(b)
Three types of minimum instruction execution time (0.4 µs and 1.6 µs: main system clock (at 5.0 MHz
operation), 122 µs: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM,
and CSS settings.
(c)
Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback
resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem
clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d)
CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation
is used (122 µs: at 32.768 kHz operation).
(e)
With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f)
The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to the watch timer and LCD controller/driver. The
watch timer and LCD controller/driver can therefore keep running even during standby. The other
hardware stops when the main system clock stops because it runs based on the main system clock
(except for external input clock operations).
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CHAPTER 5 CLOCK GENERATOR
5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
The maximum time indicated in Table 5-2 is required until the CPU clock actually switches (i.e. switching does not
occur immediately after the PCC register is rewritten). Until this time has elapsed, therefore, it is impossible to
ascertain whether the clock before or after the switch is operating.
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
CSS0
0
PCC1
Set Value After Switching
CSS0
PCC1
CSS0
PCC1
CSS0
PCC1
0
0
0
1
1
×
0
4 clocks
2fX/fXT clocks
(306 clocks)
1
2 clocks
fX/2fXT clocks
(76 clocks)
1
×
2 clocks
2 clocks
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
3. ×: don’t care
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CHAPTER 5 CLOCK GENERATOR
5.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock switch.
Figure 5-8. Example of Switching Between System Clock and CPU Clock
VDD
RESET
Input request signal
PCC
rewrite
System clock
CPU clock
CSS
rewrite
CSS
rewrite
fX
fX
fXT
fX
Low-speed
operation
High-speed
operation
Subsystem clock
operation
High-speed
operation
Oscillation stabilization time wait
(6.55 ms at 5.0 MHz operation)
Internal reset operation
Few clocks
(For maximum
values, refer
to Table 5-2.)
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6 µs at
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) is rewritten.
<3> After a few clocks have elapsed, the CPU clock is switched to high-speed (0.4 µs at 5.0 MHz operation), and
the CPU starts the high-speed operation.
<4> A drop of the VDD voltage is detected by an interrupt request signal. Bit 4 (CSS0) of the subclock control
register (CSS) is rewritten so that the clock is switched to the subsystem clock (at this moment, the
subsystem clock must be in the oscillation stabilized status).
<5> After a few clocks have elapsed, the CPU clock is switched to the subsystem clock operation (122 µs at
32.768 kHz operation). (At this time, bit 7 (MCC) of PCC can be set to 1 to stop the main system clock.)
<6> When a recover of the VDD voltage is detected by an interrupt request signal, CSS0 is written so that the
CPU clock is switched to the main system clock. (If the main system clock is stopped, set bit 7 (MCC) of
PCC to 0 so that the main system clock starts oscillating. After the time required for the oscillation to
stabilize has elapsed, rewrite CSS0.)
<7> After a few clocks, the CPU clock is switched to high speed (0.4 µs at 5.0 MHz operation), and the CPU
returns to high-speed operation.
Caution
When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 6 8-BIT TIMERS 30 AND 40
6.1 8-Bit Timers 30 and 40 Functions
The 8-bit timer in the µPD789327 Subseries has 2 channels (timer 30 and timer 40). The operation modes listed
in the following table can be set via mode register settings.
Table 6-1. Operation Modes
Channel
Timer 30
Timer 40
Available
Available
Mode
8-bit timer counter mode
(Discrete mode)
16-bit timer counter mode
Available
(Cascade connection mode)
Carrier generator mode
Available
PWM output mode
Not available
(1) 8-bit timer counter mode (discrete mode)
The following functions can be used in this mode.
• Interval timer with 8-bit resolution
• Square-wave output with 8-bit resolution (timer 40 only)
(2) 16-bit timer counter mode (cascade connection mode)
Operation as a 16-bit timer is enabled during cascade connection mode.
The following functions can be used in this mode.
• Interval timer with 16-bit resolution
• Square-wave output with 16-bit resolution
(3) Carrier generator mode
The carrier clock generated by timer 40 is output in cycles set by timer 30.
(4) PWM output mode (timer 40 only)
Pulses are output using any duty factor set by timer 40.
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Available
CHAPTER 6 8-BIT TIMERS 30 AND 40
6.2 8-Bit Timers 30 and 40 Configuration
The 8-bit timers 30 and 40 include the following hardware.
Table 6-2. Configuration of 8-Bit Timers 30 and 40
Item
Configuration
Timer counters
8 bits × 2 (TM30, TM40)
Registers
Compare registers: 8 bits × 3 (CR30, CR40, CRH40)
Timer outputs
1 (TO40)
Control registers
8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 40 (TMC40)
Carrier generator output control register 40 (TCA40)
Port mode register 6 (PM6)
Port 6 (P6)
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88
Figure 6-1. Block Diagram of Timer 30
Internal bus
8-bit timer mode control register 30
(TMC30)
TCE30 TCL301 TCL300 TMD300
8-bit compare register 30
(CR30)
Decoder
Match
(G)
Carrier clock
(from Figure 6-2 (C)) (C)
Selector
fX/26
fX/28
Timer 40 interrupt request signal
(from Figure 6-2 (B)) (B)
Selector
User’s Manual U15043EJ3V1UD
Bit 7 of TM40
(from Figure 6-2 (A))
8-bit timer counter 30
(TM30)
To Figure 6-2 (G)
Timer 30 match signal
(in carrier generator mode)
OVF
Clear
Internal reset signal
(D)
From Figure 6-2 (D)
Count operation start signal
(for cascade connection)
Selector
Cascade connection mode
INTTM30
(E)
From Figure 6-2 (E)
Timer 40 match signal
(in cascade connection mode)
(F)
To Figure 6-2 (F)
Timer 30 match signal
(in cascade connection mode)
CHAPTER 6 8-BIT TIMERS 30 AND 40
Selector
(A)
Figure 6-2. Block Diagram of Timer 40
Internal bus
Carrier generator output
control register 40 (TCA40)
8-bit timer mode control
register 40 (TMC40)
8-bit H width compare
register 40 (CRH40)
TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
8-bit compare
register 40 (CR40)
RMC40 NRZB40 NRZ40
Decoder
From Figure 6-1 (G)
Timer counter match signal from
(G) timer 30 (in carrier generator mode)
Selector
To Figure 6-1 (C)
(C) Carrier clock
8-bit timer counter 40
(TM40)
2
fX/22
3
fX/2
OVF
Clear
Selector
Prescaler
fX/2
fX/2
TO40/P60
Carrier generator mode
PWM mode
Reset
fX/24
Cascade connection mode
To Figure 6-1 (A)
Bit 7 of TM40
(A) (in cascade connection mode)
Internal reset signal
INTTM40
(D)
To Figure 6-1 (D)
Count operation start signal to timer 30
(in cascade connection mode)
(E)
To Figure 6-1 (E)
TM40 timer counter match signal
(in cascade connection mode)
(F)
To Figure 6-1 (F)
TM30 match signal
(in cascade connection mode)
89
Note Refer to Figure 6-3 for details.
To Figure 6-1 (B)
Timer 40 interrupt request signal
(B) count clock input
signal to TM30
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15043EJ3V1UD
fX
Output
controllerNote
F/F
Match
CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-3. Block Diagram of Output Controller (Timer 40)
TOE40
RMC40
NRZ40
Selector
P60
output latch
F/F
PM60
TO40/P60
Carrier clock
Carrier generator mode
(1) 8-bit compare register 30 (CR30)
This 8-bit register is used to continually compare the value set to CR30 with the count value in 8-bit timer
counter 30 (TM30) and to generate an interrupt request (INTTM30) when a match occurs.
CR30 is set with an 8-bit memory manipulation instruction.
RESET input makes CR30 undefined.
Caution
CR30 cannot be used in PWM output mode.
(2) 8-bit compare register 40 (CR40)
This 8-bit register is used to continually compare the value set to CR40 with the count value in 8-bit timer
counter 40 (TM40) and to generate an interrupt request (INTTM40) when a match occurs. When connected
to TM30 via a cascade connection and used as a 16-bit timer, the interrupt request (INTTM40) occurs only
when matches occur simultaneously between CR30 and TM30 and between CR40 and TM40 (INTTM30
does not occur).
In carrier generator mode or PWM output mode, CR40 sets the timer output low-level width.
CR40 is set with an 8-bit memory manipulation instruction.
RESET input makes CR40 undefined.
(3) 8-bit H width compare register 40 (CRH40)
In carrier generator mode or PWM output mode, the high-level width of timer output is set by writing a value
to CRH40.
The set value of CRH40 is always compared with the TM40 count value, and when they match, an interrupt
request (INTTM40) is generated.
CRH40 is set with an 8-bit memory manipulation instruction.
RESET input makes CRH40 undefined.
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CHAPTER 6 8-BIT TIMERS 30 AND 40
(4) 8-bit timer counters 30 and 40 (TM30 and TM40)
These are 8-bit registers that are used to count the count pulse.
TM30 and TM40 are read with an 8-bit memory manipulation instruction.
RESET input sets TM30 and TM40 to 00H.
TM30 and TM40 are cleared to 00H under the following conditions.
(a) Discrete mode
(i) TM30
• After reset
• When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0
• When a match occurs between TM30 and CR30
• When the TM30 count value overflows
(ii) TM40
• After reset
• When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0
• When a match occurs between TM40 and CR40
• When the TM40 count value overflows
(b) Cascade connection mode (TM30 and TM40 are simultaneously cleared to 00H)
• After reset
• When the TCE40 flag is cleared to 0
• When matches occur simultaneously between TM30 and CR30 and between TM40 and CR40
• When the TM30 and TM40 count values overflow simultaneously
(c) Carrier generator mode/PWM output mode (TM40 only)
• After reset
• When the TCE40 flag is cleared to 0
• When a match occurs between TM40 and CR40
• When a match occurs between TM40 and CRH40
• When the TM40 count value overflows
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CHAPTER 6 8-BIT TIMERS 30 AND 40
6.3 Registers Controlling 8-Bit Timers 30 and 40
8-bit timer 30 and 40 are controlled by the following five registers.
• 8-bit timer mode control register 30 (TMC30)
• 8-bit timer mode control register 40 (TMC40)
• Carrier generator output control register 40 (TCA40)
• Port mode register 6 (PM6)
• Port 6 (P6)
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CHAPTER 6 8-BIT TIMERS 30 AND 40
(1) 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 30 (TMC30) is used to control the timer 30 count clock setting and the
operation mode setting.
TMC30 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC30 to 00H.
Figure 6-4. Format of 8-Bit Timer Mode Control Register 30
Symbol
<7>
6
5
4
3
2
1
0
Address
After reset
R/W
TMC30
TCE30
0
0
TCL301
TCL300
0
TMD300
0
FF65H
00H
R/W
Note 1
TCE30
Control of TM30 count operation
0
Clear TM30 count value and stop operation
1
Start count operation
TCL301
TCL300
Selection of timer 30 count clock
6
0
0
fX/2 (78.1 kHz)
0
1
fX/2 (19.5 kHz)
1
0
Timer 40 match signal
1
1
Carrier clock created for timer 40
TMD300
TMD401
TMD400
0
0
0
8-bit timer counter mode (discrete mode)
1
0
1
16-bit timer counter mode (cascade connection mode)
0
1
1
Carrier generator mode
0
1
0
Timer 40: PWM output mode
8
Selection of operation mode for timer 30 and timer 40
Note 2
Timer 30: 8-bit timer counter mode
Other than above
Setting prohibited
Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode,
any setting for TCE30 is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Cautions 1. In cascade connection mode, the timer 40 output signal is forcibly selected for the
count clock.
2. Be sure to clear bits 0, 2, 5, and 6 to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 6 8-BIT TIMERS 30 AND 40
(2) 8-bit timer mode control register 40 (TMC40)
8-bit timer mode control register 40 (TMC40) is used to control the timer 40 count clock setting and the
operation mode setting.
TMC40 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC40 to 00H.
Figure 6-5. Format of 8-Bit Timer Mode Control Register 40
Symbol
<7>
6
5
4
3
2
1
<0>
Address
After reset
R/W
TMC40
TCE40
0
TCL402
TCL401
TCL400
TMD401
TMD400
TOE40
FF69H
00H
R/W
Note 1
TCE40
Control of TM40 count operation
0
Clear TM40 count value and stop operation (the count value is also cleared for TM30 during cascade
connection mode)
1
Start count operation (the count operation is also started for TM30 during cascade connection mode)
TCL402
TCL401
TCL400
0
0
0
fX (5 MHz)
0
0
1
fX/2 (1.25 MHz)
0
1
0
fX/2 (2.5 MHz)
0
1
1
fX/2 (1.25 MHz)
1
0
0
fX/2 (625 kHz)
1
0
1
fX/2 (313 kHz)
Other than above
Selection of timer 40 count clock
2
2
3
4
Setting prohibited
TMD300
TMD401
TMD400
0
0
0
8-bit timer counter mode (discrete mode)
1
0
1
16-bit timer counter mode (cascade connection mode)
0
1
1
Carrier generator mode
0
1
0
Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above
Selection of operation mode for timer 30 and timer 40
Note 2
Setting prohibited
TOE40
Control of timer output
0
Output disabled (port mode)
1
Output enabled
Notes 1. Since the count operation is controlled by TCE40 in cascade connection mode, any setting for
TCE30 (bit 7 of TMC30) is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Caution Be sure to clear bit 6 to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
94
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CHAPTER 6 8-BIT TIMERS 30 AND 40
(3) Carrier generator output control register 40 (TCA40)
This register is used to set the timer output data in carrier generator mode.
TCA40 is set with an 8-bit memory manipulation instruction.
RESET input sets TCA40 to 00H.
Figure 6-6. Format of Carrier Generator Output Control Register 40
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
TCA40
0
0
0
0
0
RMC40
NRZB40
NRZ40
FF6AH
00H
R/W
RMC40
Control of remote control output
0
When NRZ40 = 1, carrier pulse is output to TO40/P60 pin
1
When NRZ40 = 1, high-level signal is output to TO40/P60 pin
NRZB40
This is the bit that stores the next data to be output to NRZ40. Data is transferred to NRZ40 at the rising edge
of the timer 30 match signal. Input the necessary value in NRZB40 in advance by program.
NRZ40
No return zero data
0
Output low-level signal (carrier clock is stopped)
1
Output carrier pulse or high-level signal
Cautions 1. Bits 3 to 7 must be set to 0.
2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8bit memory manipulation instruction to set TCA40.
3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 =
0). The data cannot be overwritten when TOE40 = 1.
4. When the carrier generator is stopped once and then started again, NRZB40 does not
hold the previous data.
Re-set data to NRZB40.
manipulation instruction must not be used.
At this time, a 1-bit memory
Be sure to use an 8-bit memory
manipulation instruction.
5. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40
flags in advance. Otherwise, the signal of the timer match circuit will become unstable
and the NRZ40 flag will be undefined.
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CHAPTER 6 8-BIT TIMERS 30 AND 40
(4) Port mode register 6 (PM6)
This register is used to set the I/O mode of port 6 in 1-bit units.
When using the P60/TO40 pin as a timer output, set the PM60 and P60 output latch to 0.
PM6 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM6 to FFH.
Figure 6-7. Format of Port Mode Register 6
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FF26H
FFH
R/W
PM6n
I/O mode of P6n pin
(n = 0, 1)
0
Output mode (output buffer is on)
1
Input mode (output buffer is off)
Caution
96
Bits 2 to 7 must be set to 1.
User’s Manual U15043EJ3V1UD
CHAPTER 6 8-BIT TIMERS 30 AND 40
6.4 8-Bit Timers 30 and 40 Operation
6.4.1 Operation as 8-bit timer counter
Timers 30 and 40 can be independently used as 8-bit timer counters.
The following modes can be used for the 8-bit timer counters.
•
Interval timer with 8-bit resolution
•
Square-wave output with 8-bit resolution (timer 40 only)
(1)
Operation as interval timer with 8-bit resolution
The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register n0 (CRn0).
To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0).
<2> Disable timer output of TOn0 (TOEn0 = 0).
<3> Set a count value in CRn0.
<4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 6-4 and 6-5).
<5> Set the count clock for timer n0 (see Tables 6-3 and 6-4).
<6> Enable the operation of TMn0 (TCEn0 = 1).
When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to
00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated.
Tables 6-3 and 6-4 show the interval time, and Figures 6-8 to 6-12 show the timing of the interval timer
operation.
Caution
Be sure to stop the timer operation before overwriting the count clock with different data.
Remark
n = 3, 4
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CHAPTER 6 8-BIT TIMERS 30 AND 40
Table 6-3. Interval Time of Timer 30 (at fX = 5.0 MHz Operation)
TCL301
TCL300
Minimum Interval Time
Maximum Interval Time
Resolution
0
2 /fX (12.8 µs)
2 /fX (3.28 ms)
0
1
2 /fX (51.2 µs)
2 /fX (13.1 ms)
2 /fX (51.2 µs)
1
0
Input cycle of timer 40 match
Input cycle of timer 40 match
8
signal × 2
Input cycle of timer 40 match
Carrier clock cycle created
8
with timer 40 × 2
Carrier clock cycle created
0
6
8
signal
1
1
Carrier clock cycle created
with timer 40
Remark
14
2 /fX (12.8 µs)
16
4
8
signal
with timer 40
fX: Main system clock oscillation frequency
Table 6-4. Interval Time of Timer 40 (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
0
0
Minimum Interval Time
Maximum Interval Time
Resolution
0
1/fX (0.2 µs)
2 /fX (51 µs)
1/fX (0.2 µs)
8
0
0
1
2 /fX (0.8 µs)
2 /fX (205 µs)
2 /fX (0.8 µs)
0
1
0
2/fX (0.4 µs)
2 /fX (102 µs)
2/fX (0.4 µs)
0
1
1
2 /fX (0.8 µs)
2 /fX (205 µs)
2 /fX (0.8 µs)
1
0
0
2 /fX (1.6 µs)
2 /fX (410 µs)
2 /fX (1.6 µs)
1
0
1
2 /fX (3.2 µs)
2 /fX (819 µs)
2 /fX (3.2 µs)
Remark
2
10
2
9
2
10
3
2
11
4
3
12
4
fX: Main system clock oscillation frequency
Figure 6-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
t
Count clock
TMn0
00H
01H
N
00H
01H
00H
N
Clear
01H
N
Clear
00H
01H
00H
Clear
N
CRn0
TCEn0
Count start
Count stop
INTTMn0
Interrupt acknowledgment
Interrupt acknowledgment
Interval time
Interval time
TOn0
Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH
2. n = 3, 4
98
User’s Manual U15043EJ3V1UD
Interrupt acknowledgment
CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H)
Count clock
00H
TMn0
00H
CRn0
TCEn0
Count start
INTTMn0
TOn0
Remark
n = 3, 4
Figure 6-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
Count clock
TMn0
00H
01H
FFH
00H
Clear
01H
FFH
00H
Clear
01H
FFH
00H
FFH
00H
Clear
FFH
CRn0
TCEn0
Count start
INTTMn0
TOn0
Remark
n = 3, 4
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CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-11. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N < M))
Count clock
TMn0
00H
N
01H
00H
N
M
00H
Clear
Clear
N
CRn0
M
N
00H
01H
Clear
M
TCEn0
Count start
INTTMn0
Interrupt acknowledgment
Interrupt acknowledgment
TOn0
CRn0 overwritten
Remark
n = 3, 4
Figure 6-12. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N > M))
Count clock
TMn0
N−1
00H
N
M
N
FFH
Clear
TCEn0
Clear
N
CRn0
M
00H
Clear
M
H
TMn0 overflows
because M < N
INTTMn0
TOn0
CRn0 overwritten
Remark
100
n = 3, 4
User’s Manual U15043EJ3V1UD
00H
M
00H
CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-13. Timing of Interval Timer Operation with 8-Bit Resolution
(When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
Timer 40
count clock
TM40
00H
N
01H
M
00H
Clear
M
00H
Clear
M
Clear
N
CR40
00H
00H
Clear
M
TCE40
Count start
INTTM40
Input clock to timer 30
(timer 40 match signal)
00H
TM30
Y−1
01H
Y
00H
Y
00H
Y
CR30
TCE30
INTTM30
Count start
TO40
TO30
Remark
n = 3, 4
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101
CHAPTER 6 8-BIT TIMERS 30 AND 40
(2)
Operation as square-wave output with 8-bit resolution (timer 40 only)
Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare
register 40 (CR40).
To operate timer 40 for square-wave output, settings must be made in the following sequence.
<1> Set P60 to output mode (PM60 = 0).
<2> Set the output latch of P60 to 0.
<3> Disable operation of timer counter 40 (TM40) (TCE40 = 0).
<4> Set a count clock for timer 40 and enable output of TO40 (TOE40 = 1).
<5> Set a count value in CR40.
<6> Enable the operation of TM40 (TCE40 = 1).
When the count value of TM40 matches the value set in CR40, the TO40 pin output will be inverted. Through
application of this mechanism, square waves of any frequency can be output. As soon as a match occurs,
TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is
generated.
The square-wave output is cleared to 0 by setting TCE40 to 0.
Table 6-5 shows the square-wave output range, and Figure 6-14 shows the timing of square-wave output.
Caution
Be sure to stop the timer operation before overwriting the count clock with different data.
Table 6-5. Square-Wave Output Range of Timer 40 (at fX = 5.0 MHz Operation)
TCL402
TCL401
TCL400
0
0
0
1/fX (0.2 µs)
2 /fX (51 µs)
1/fX (0.2 µs)
Maximum Pulse Width
8
Resolution
0
0
1
2 /fX (0.8 µs)
2 /fX (205 µs)
2 /fX (0.8 µs)
0
1
0
2/fX (0.4 µs)
2 /fX (102 µs)
2/fX (0.4 µs)
2
10
9
2
0
1
1
2 /fX (0.8 µs)
2 /fX (205 µs)
2 /fX (0.8 µs)
1
0
0
2 /fX (1.6 µs)
2 /fX (410 µs)
2 /fX (1.6 µs)
1
0
1
2 /fX (3.2 µs)
2 /fX (819 µs)
2 /fX (3.2 µs)
Remark
102
Minimum Pulse Width
2
10
3
11
4
12
fX: Main system clock oscillation frequency
User’s Manual U15043EJ3V1UD
2
3
4
CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-14. Timing of Square-Wave Output with 8-Bit Resolution
t
Count clock
TM40
00H
01H
N
00H
01H
00H
N
Clear
01H
N
Clear
00H
01H
Clear
N
CR40
TCE40
Count start
INTTM40
Interrupt acknowledgment
Interrupt acknowledgment
Interrupt acknowldgement
TO40Note
Square-wave output cycle
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark
Square-wave output cycle = 2 (N + 1) × t: N = 00H to FFH
User’s Manual U15043EJ3V1UD
103
CHAPTER 6 8-BIT TIMERS 30 AND 40
6.4.2 Operation as 16-bit timer counter
Timers 30 and 40 can be used as 16-bit timer counters via a cascade connection. In this case, 8-bit timer counter
30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and
clear.
The following modes can be used for the 16-bit timer counter.
•
Interval timer with 16-bit resolution
•
Square-wave output with 16-bit resolution
(1)
Operation as interval timer with 16-bit resolution
The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40).
To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0,
TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set the count clock for timer 40 (see Table 6-4).
<4> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 6-4 and 65).
<5> Set a count value in CR30 and CR40.
<6> Enable the operation of TM30 and TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and
TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal
(INTTM40) is generated (INTTM30 is not generated).
Table 6-6 shows interval time, and Figure 6-15 shows the timing of the interval timer operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 6-6. Interval Time with 16-Bit Resolution (at fX = 5.0 MHz Operation)
TCL402
TCL401
0
0
TCL400
Minimum Interval Time
0
1/fX (0.2 µs)
Maximum Interval Time
1/fX (0.2 µs)
18
2 /fX (0.8 µs)
17
2/fX (0.4 µs)
18
2 /fX (0.8 µs)
19
2 /fX (1.6 µs)
20
2 /fX (3.2 µs)
2 /fX (13.1 ms)
0
0
1
2 /fX (0.8 µs)
2 /fX (52.4 ms)
0
1
0
2/fX (0.4 µs)
2 /fX (26.2 ms)
0
1
1
2 /fX (0.8 µs)
2 /fX (52.4 ms)
1
0
0
2 /fX (1.6 µs)
2 /fX (105 ms)
1
0
1
2 /fX (3.2 µs)
2 /fX (210 ms)
Remark
104
2
2
3
4
Resolution
16
fX: Main system clock oscillation frequency
User’s Manual U15043EJ3V1UD
2
2
3
4
Figure 6-15. Timing of Interval Timer Operation with 16-Bit Resolution
t
TM40 count clock
TM40 count value
00H
N
7FH 80H
FFH 00H
7FH 80H
N
FFH 00H
Not cleared because TM30 does not match
CR40
N
N
N
N
00H
N
FFH 00H
7FH 80H
00H
Cleared because TM30 and TM40 match simultaneously
N
N
N
N
N
N
User’s Manual U15043EJ3V1UD
Count start
TM30 count clock
TM30
00H
CR30
X
X−1
01H
X
X
X−1
00H
X
00H
X
INTTM40
TO40
Interrupt not generated because
TM30 does not match
Interrupt acknowledgment
Interval time
Remark Interval time = (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
Interrupt acknowledgment
CHAPTER 6 8-BIT TIMERS 30 AND 40
TCE40
105
CHAPTER 6 8-BIT TIMERS 30 AND 40
(2)
Operation as square-wave output with 16-bit resolution
Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and
CR40.
To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable output of TO40 (TOE40 = 0).
<3> Set a count clock for timer 40.
<4> Set P60 to output mode (PM60 = 0) and P60 output latch to 0 and enable TO40 output (TOE40 = 1).
<5> Set count values in CR30 and CR40.
<6> Enable the operation of TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40
respectively, the TO40 pin output will be inverted. Through application of this mechanism, square waves of
any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting
continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated).
The square-wave output is cleared to 0 by setting TCE40 to 0.
Table 6-7 shows the square wave-output range, and Figure 6-16 shows timing of square-wave output.
Caution
Be sure to stop the timer operation before overwriting the count clock with different data.
Table 6-7. Square-Wave Output Range with 16-Bit Resolution (at fX = 5.0 MHz Operation)
TCL402
TCL401
0
Minimum Pulse Width
0
1/fX (0.2 µs)
Maximum Pulse Width
1/fX (0.2 µs)
18
2 /fX (0.8 µs)
17
2/fX (0.4 µs)
18
2 /fX (0.8 µs)
19
2 /fX (1.6 µs)
20
2 /fX (3.2 µs)
2 /fX (13.1 ms)
0
1
2 /fX (0.8 µs)
2 /fX (52.4 ms)
0
1
0
2/fX (0.4 µs)
2 /fX (26.2 ms)
2
0
1
1
2 /fX (0.8 µs)
2 /fX (52.4 ms)
1
0
0
2 /fX (1.6 µs)
2 /fX (105 ms)
1
0
1
2 /fX (3.2 µs)
2 /fX (210 ms)
2
3
4
Resolution
16
0
Remark
106
0
TCL400
fX: Main system clock oscillation frequency
User’s Manual U15043EJ3V1UD
2
2
3
4
Figure 6-16. Timing of Square-Wave Output with 16-Bit Resolution
t
TM40 count clock
TM40 count clock
00H
N
7FH 80H
FFH 00H
7FH 80H
N
FFH 00H
Not cleared because TM30 does not match
CR40
N
N
N
N
00H
7FH 80H
FFH 00H
N
00H
Cleared because TM30 and TM40 match simultaneously
N
N
N
N
N
N
User’s Manual U15043EJ3V1UD
Count start
TM30 count clock
TM30
00H
CR30
X
X−1
01H
X
X
X−1
00H
X
00H
X
INTTM40
Note
Interrupt not generated because
TM30 does not match
Interrupt acknowledgment
TO40
Square-wave output cycle/2
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark
Square-wave output cycle = 2 (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
Interrupt acknowledgment
CHAPTER 6 8-BIT TIMERS 30 AND 40
TCE40
107
CHAPTER 6 8-BIT TIMERS 30 AND 40
6.4.3 Operation as carrier generator
An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30.
To operate timers 30 and 40 as carrier generators, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR30, CR40, and CRH40.
<4> Set the operation mode of timer 30 and timer 40 to carrier generator mode (see Figures 6-4 and 6-5).
<5> Set the count clock for timer 30 and timer 40.
<6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40
(TCA40)) = 0).
Input the required value to NRZB40 (bit 1 of TCA40) by program.
Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40.
<7> Set P60 to output mode (PM60 = 0) and the P60 output latch to 0 and enable TO40 output by setting TOE40
to 1.
<8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1).
<9> Save the NRZB40 value to a general-purpose register.
<10> When INTTM30 rises, the NRZB40 value is transferred to NRZ40. After that, rewrite TCA40 using an 8-bit
memory manipulation instruction. Input the value to be transferred next to NRZ40 to NRZB40, and input the
value saved in step <9> to NRZ40.
<11> Generate the desired carrier signal by repeating steps <9> and <10>.
The operation of the carrier generator is as follows.
<1> When the count the value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and the output of timer 40 is inverted, which makes the compare register switch from CR40 to
CRH40.
<2> After that, when the count the value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and the output of timer 40 is inverted again, which makes the compare register
switch from CRH40 to CR40.
<3> The carrier clock is generated by repeating <1> and <2> above.
<4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is
generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40.
<5> When NRZ40 is 1, a carrier clock is output from TO40 pin.
Cautions
1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit
memory manipulation instruction.
2. The NRZ40 flag can be rewritten only when the carrier generator output is stopped (TOE40
= 0). The data of the flag is not changed even if a write instruction is executed while TOE40
= 1.
3. When the carrier generator is stopped once and then started again, NRZB40 does not hold
the previous data. Re-set data to NRZB40. At this time, a 1-bit memory manipulation
instruction must not be used. Be sure to use an 8-bit memory manipulation instruction.
4. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in
advance. Otherwise, the signal of the timer match circuit will become unstable and the
NRZ40 flag will be undefined.
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CHAPTER 6 8-BIT TIMERS 30 AND 40
Figures 6-17 to 6-19 show the operation timing of the carrier generator.
Figure 6-17. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
TM40 count clock
TM40
count value
00H
01H
N
00H
M
N
Clear
CR40
N
CRH40
M
00H
N
00H
Clear
N
M
Clear
00H
Clear
TCE40
Count start
INTTM40
Carrier clock
TM30 count clock
TM30
00H
01H
X
00H
01H
X
00H
01H
X
00H
X
00H
01H
X
CR30
TCE30
INTTM30
NRZB40
NRZ40
0
0
1
0
1
1
0
0
1
0
Carrier clock
TO40
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CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-18. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
TM40 count clock
TM40
count value
N
M
00H
00H
M
N
CRH40
M
M
N
Clear
Clear
CR40
00H
M
00H
Clear
00H
Clear
TCE40
Count start
INTTM40
Carrier clock
TM30 count clock
TM30
01H
00H
CR30
X
00H
01H
X
00H
00H
X
01H
X
00H
01H
X
TCE30
INTTM30
NRZB40
NRZ40
0
0
1
0
1
1
0
0
1
0
Carrier clock
TO40
Remark
110
This figure shows an example of when the NRZ40 value is changed while the carrier clock is high level.
User’s Manual U15043EJ3V1UD
CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-19. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
TM40 count clock
TM40
count value
N
00H
00H
N
Clear
CR40
N
CRH40
N
N
00H
Clear
00H
N
Clear
00H
N
Clear
00H
N
Clear
TCE40
Count start
INTTM40
Carrier clock
TM30 count clock
TM30
00H
01H
X
00H
01H
X
00H
01H
X
00H
X
00H
01H
X
CR30
TCE30
INTTM30
NRZB40
NRZ40
0
0
1
0
1
1
0
0
1
0
Carrier clock
TO40
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CHAPTER 6 8-BIT TIMERS 30 AND 40
6.4.4 Operation as PWM output (timer 40 only)
In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a
high-level width using CRH40.
To operate timer 40 in PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM40 (TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR40 and CRH40.
<4> Set the operation mode of timer 40 to carrier generator mode (see Figure 6-5).
<5> Set the count clock for timer 40.
<6> Set P60 to output mode (PM60 = 0) and the P60 output latch to 0 and enable timer output of TO40 (TOE40 =
1).
<7> Enable the operation of TM40 (TCE40 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and the output of timer 40 is inverted, which makes the compare register switch from CR40 to
CRH40.
<2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again.
<3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and the output of timer 40 is inverted again, which makes the compare register
switch from CRH40 to CR40.
<4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again.
A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 6-20 and 6-21 show the operation
timing in the PWM output mode.
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CHAPTER 6 8-BIT TIMERS 30 AND 40
Figure 6-20. PWM Output Mode Timing (Basic Operation)
TM40 count clock
TM40
count value
00H
01H
N
00H
M
01H
Clear
CR40
N
CRH40
M
00H
00H
N
01H
Clear
M
01H
Clear
00H
Clear
TCE40
Count start
INTTM40
TO40Note
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Figure 6-21. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)
TM40 count clock
TM40
count value
00H
01H
N
00H
Y
Clear
CR40
N
CRH40
M
N
00H
X
Clear
00H
M
Clear
00H
X
Clear
X
Y
M
TCE40
Count start
INTTM40
TO40Note
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
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CHAPTER 6 8-BIT TIMERS 30 AND 40
6.5 Notes on Using 8-Bit Timers 30 and 40
(1)
Error on starting timer
An error of up to 1.5 clocks is included in the time between when the timer is started and a match signal is
generated. This is because the counter may be incremented by detecting a rising edge at the timing at which
the timer starts while the count clock is high level (see Figure 6-22).
Figure 6-22. Case in Which Error of 1.5 Clocks (Max.) Occurs
Delay A
Selected clock
Count
pulse
8-bit timer counter n0
(TMn0)
Clear signal
TCEn0
Delay B
Selected clock
TCEn0
Clear signal
Count pulse
TMn0 count value
00H
01H
02H
03H
Delay A
Delay B
If delay A > delay B when the timer starts while the selected
clock is high level, an error of 1.5 clocks (max.) occurs.
Remark
114
n = 3, 4
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CHAPTER 7 WATCH TIMER
7.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch and interval timers can be used at the same time.
Figure 7-1 shows a block diagram of the watch timer.
Figure 7-1. Block Diagram of Watch Timer
fXT
5-bit counter
9-bit prescaler
fW
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
INTWT
Clear
Selector
fX/2
Selector
Clear
7
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
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CHAPTER 7 WATCH TIMER
(1)
Watch timer
The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should
be used instead.
(2)
Interval timer
The interval timer is used to generate an interrupt request (INTWT) at specified intervals.
Table 7-1. Interval Time of Interval Timer
Interval
At fX = 5.0 MHz Operation
At fX = 4.19 MHz Operation
At fXT = 32.768 kHz Operation
2 × 1/fW
409.6 µs
488 µs
488 µs
2 × 1/fW
819.2 µs
977 µs
977 µs
2 × 1/fW
1.64 ms
1.95 ms
1.95 ms
2 × 1/fW
3.28 ms
3.91 ms
3.91 ms
2 × 1/fW
6.55 ms
7.81 ms
7.81 ms
9
2 × 1/fW
13.1 ms
15.6 ms
15.6 ms
Remarks 1. fW:
Watch timer clock frequency (fX/27 or fXT)
2. fX:
Main system clock oscillation frequency
4
5
6
7
8
3. fXT: Subsystem clock oscillation frequency
7.2 Watch Timer Configuration
The watch timer includes the following hardware.
Table 7-2. Configuration of Watch Timer
Item
Configuration
Counter
5 bits × 1
Prescaler
9 bits × 1
Control register
Watch timer mode control register (WTM)
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CHAPTER 7 WATCH TIMER
7.3 Register Controlling Watch Timer
The watch timer mode control register (WTM) is used to control the watch timer.
• Watch timer mode control register (WTM)
WTM selects a count clock for the watch timer and specifies whether to enable clocking of the timer. It also
specifies the prescaler interval and how the 5-bit counter is controlled.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WTM to 00H.
Figure 7-2. Format of Watch Timer Mode Control Register
Symbol
7
6
5
4
3
2
<1>
<0>
Address
After reset
R/W
WTM
WTM7
WTM6
WTM5
WTM4
0
0
WTM1
WTM0
FF4AH
00H
R/W
WTM7
Watch timer count clock (fW) selection
7
0
fX/2 (39.1 kHz)
1
fXT
WTM6
(32.768 kHz)
WTM5
WTM4
Prescaler interval selection
4
0
0
0
2 /fW
0
0
1
2 /fW
0
1
0
2 /fW
0
1
1
2 /fW
1
0
0
2 /fW
1
0
1
2 /fW
Other than above
5
6
7
8
9
Setting prohibited
WTM1
Control of 5-bit counter operation
0
Cleared after stop
1
Started
WTM0
Watch timer operation
0
Operation stopped (both prescaler and timer cleared)
1
Operation enabled
Caution
Bits 2 and 3 must be set to 0.
Remarks 1. fW:
Watch timer clock frequency (fX/27 or fXT)
2. fX:
Main system clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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CHAPTER 7 WATCH TIMER
7.4 Watch Timer Operation
7.4.1 Operation as watch timer
The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer which generates
0.5-second intervals.
The watch timer is used to generate an interrupt request at specified intervals.
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer
starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.
When the interval timer also operates at the same time, only the watch timer can be started from 0 seconds by
setting WTM1 to 0. However, an error of up to 29 × 1/fW seconds may occur for the first overflow of the watch timer
(INTWT) after a 0-second start because the 9-bit prescaler is not cleared in this case.
7.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count
value.
The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 7-3. Interval Time of Interval Timer
Interval
At fX = 5.0 MHz Operation
At fX = 4.19 MHz Operation
At fXT = 32.768 kHz Operation
2 × 1/fW
409.6 µs
488 µs
488 µs
2 × 1/fW
819.2 µs
977 µs
977 µs
2 × 1/fW
1.64 ms
1.95 ms
1.95 ms
2 × 1/fW
3.28 ms
3.91 ms
3.91 ms
2 × 1/fW
6.55 ms
7.81 ms
7.81 ms
9
2 × 1/fW
13.1 ms
15.6 ms
15.6 ms
Remarks 1. fW:
Watch timer clock frequency (fX/27 or fXT)
2. fX:
Main system clock oscillation frequency
4
5
6
7
8
3. fXT: Subsystem clock oscillation frequency
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CHAPTER 7 WATCH TIMER
Figure 7-3. Watch Timer/Interval Timer Operation Timing
5-bit counter
0H
Overflow
Start
Overflow
Count clock
fW/29
Watch timer
interrupt
INTWT
Watch timer interrupt time (0.5 s)
Watch timer interrupt time (0.5 s)
Interval timer
interrupt
INTWTI
Interval
timer (T)
T
Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch
timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first
interrupt request after this setting will not be exactly the same as the watch timer interrupt time
(0.5 s). This is because the 5-bit counter starts counting one cycle after the output of the 9-bit
prescaler. The INTWT signal will be generated at the set time from its second generation.
Remarks 1. fW: Watch timer clock frequency
2. The parenthesized values apply to operation at fW = 32.768 kHz.
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CHAPTER 8 WATCHDOG TIMER
8.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1)
Watchdog timer
The watchdog timer is used to detect inadvertent program loop. When the inadvertent program loop is
detected, a non-maskable interrupt or the RESET signal can be generated.
Table 8-1. Inadvertent Program Loop Detection Time of Watchdog Timer
Inadvertent Program Loop Detection Time
2 × 1/fX
410 µs
2 × 1/fX
1.64 ms
2 × 1/fX
6.55 ms
2 × 1/fX
26.2 ms
11
13
15
17
Remark
(2)
At fX = 5.0 MHz Operation
fX: Main system clock oscillation frequency
Interval timer
The interval timer generates an interrupt at any preset intervals.
Table 8-2. Interval Time of Watchdog Timer
Interval Time
410 µs
2 × 1/fX
1.64 ms
2 × 1/fX
6.55 ms
2 × 1/fX
26.2 ms
13
15
17
Remark
120
At fX = 5.0 MHz Operation
2 × 1/fX
11
fX: Main system clock oscillation frequency
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CHAPTER 8 WATCHDOG TIMER
8.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 8-3. Configuration of Watchdog Timer
Item
Configuration
Control registers
Watchdog timer clock selection register (TCL2)
Watchdog timer mode register (WDTM)
Figure 8-1. Block Diagram of Watchdog Timer
Internal bus
fX
24
WDTMK
Prescaler
fX
26
fX
28
fX
210
Selector
WDTIF
7-bit counter
Controller
INTWDT
Maskable
interrupt request
RESET
INTWDT
Non-maskable
interrupt request
Clear
2
TCL22 TCL21
RUN WDTM4 WDTM3
Watchdog timer clock selection
register (TCL2)
Watchdog timer mode register
(WDTM)
Internal bus
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CHAPTER 8 WATCHDOG TIMER
8.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
• Watchdog timer clock selection register (TCL2)
• Watchdog timer mode register (WDTM)
(1)
Watchdog timer clock selection register (TCL2)
TCL2 sets the watchdog timer count clock.
This register is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Figure 8-2. Format of Watchdog Timer Clock Selection Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
TCL2
0
0
0
0
0
TCL22
TCL21
0
FF42H
00H
R/W
TCL22
TCL21
Watchdog timer count clock selection
Inadvertent program loop detection or interval
time
4
2 /fX (410 µs)
6
2 /fX (1.64 ms)
8
2 /fX (6.55 ms)
10
2 /fX (26.2 ms)
0
0
fX/2 (313 kHz)
0
1
fX/2 (78.1 kHz)
1
0
fX/2 (19.5 kHz)
1
1
fX/2 (4.88 kHz)
Caution
11
13
15
17
Bits 0, 3 to 7 must be set to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 8 WATCHDOG TIMER
(2)
Watchdog timer mode register (WDTM)
WDTM sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 8-3. Format of Watchdog Timer Mode Register
Symbol
<7>
6
5
4
3
2
1
0
Address
After reset
R/W
WDTM
RUN
0
0
WDTM4
WDTM3
0
0
0
FFF9H
00H
R/W
Note 1
RUN
Selection of operation of watchdog timer
0
Stops counting
1
Clears counter and starts counting
Note 2
WDTM4
WDTM3
Selection of operation mode of watchdog timer
0
0
Operation stopped
0
1
Interval timer mode (when overflow occurs, a maskable interrupt occur)
1
0
Watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs)
1
1
Watchdog timer mode 2 (when overflow occurs, reset operation starts)
Note 3
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the watchdog timer clock selection register (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that the WDTIF (bit 0 of
interrupt request flag register 0 (IF0)) is set to 0. While WDTIF is 1, a non-maskable
interrupt is generated upon write completion if watchdog timer mode 1 or 2 is selected.
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CHAPTER 8 WATCHDOG TIMER
8.4 Watchdog Timer Operation
8.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode
register (WDTM) is set to 1.
The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 1
and 2 (TCL21 and TCL22) of the watchdog timer clock selection register (TCL2). By setting bit 7 (RUN) of WDTM to 1,
the watchdog timer is started. Set RUN to 1 within the set inadvertent program loop detection time interval after the
watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN
is not set to 1, and the inadvertent program loop detection time is exceeded, the system is reset or a non-maskable
interrupt is generated by the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Cautions 1. The actual inadvertent program loop detection time may be up to 0.8% shorter than the set
time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.
In this case, therefore, the watchdog timer stops operation even though the main system
clock is oscillating.
Table 8-4. Inadvertent Program Loop Detection Time of Watchdog Timer
TCL22
TCL21
0
0
2 × 1/fX
410 µs
1
2 × 1/fX
1.64 ms
0
2 × 1/fX
6.55 ms
1
2 × 1/fX
26.2 ms
0
1
1
Remark
124
Inadvertent Program Loop Detection Time
11
13
15
17
At fX = 5.0 MHz Operation
fX: Main system clock oscillation frequency
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CHAPTER 8 WATCHDOG TIMER
8.4.2 Operation as interval timer
When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time
intervals specified by a preset count value.
Select a count clock (or interval time) by setting bits 1 and 2 (TCL21 and TCL22) of the watchdog timer clock
selection register (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM)
is set to 1.
In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 8-5. Interval Time of Watchdog Timer
TCL22
Interval Time
At fX = 5.0 MHz Operation
0
2 × 1/fX
410 µs
0
1
2 × 1/fX
1.64 ms
1
0
2 × 1/fX
6.55 ms
1
2 × 1/fX
26.2 ms
0
1
Remark
TCL21
11
13
15
17
fX: Main system clock oscillation frequency
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CHAPTER 9 SERIAL INTERFACE 10
9.1 Serial Interface 10 Functions
Serial interface 10 has the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1)
Operation stop mode
This mode is used when serial transfer is not carried out. It enables a reduction in power consumption.
(2)
3-wire serial I/O mode (MSB/LSB-first switchable)
In this mode, 8-bit data transfer is carried out-first with three lines, one for the serial clock (SCK10) and two
for serial data (SI10 and SO10).
The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer
processing time.
It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus
allowing connection to devices with either start bit.
The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/O such as the 75XL
Series, 78K Series, and 17K Series, which have internal conventional clocked serial interfaces.
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CHAPTER 9 SERIAL INTERFACE 10
9.2 Serial Interface 10 Configuration
Serial interface 10 includes the following hardware.
Table 9-1. Configuration of Serial Interface 10
Item
Register
Control register
Configuration
Transmit/receive shift register 10 (SIO10)
Serial operation mode register 10 (CSIM10)
Port mode register 2 (PM2)
Port 2 (P2)
(1)
Transmit/receive shift register 10 (SIO10)
SIO10 is an 8-bit register used for parallel-to-serial conversion and to perform serial data
transmission/reception in synchronization with serial clocks.
This register is set with an 8-bit memory manipulation instruction.
RESET input makes SIO10 undefined.
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128
Figure 9-1. Block Diagram of Serial Interface 10
Internal bus
Serial operation mode
register 10 (CSIM10)
CSIE10 TPS101 TPS100 DIR10 CSCK10
Transmit/receive shift
register 10 (SIO10)
SI10/P22
PM21
output latch
(P21)
Serial clock counter
Interrupt request
generator
output latch
(P20)
PM20
F/F
Selector
Clock controller
Selector
SCK10/P20
fX/22
fX/23
TPS101 TPS100
INTCSI10
CHAPTER 9 SERIAL INTERFACE 10
User’s Manual U15043EJ3V1UD
SO10/P21
CHAPTER 9 SERIAL INTERFACE 10
9.3 Registers Controlling Serial Interface 10
Serial interface 10 is controlled by the following three registers.
• Serial operation mode register 10 (CSIM10)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1)
Serial operation mode register 10 (CSIM10)
CSIM10 is used to control serial interface 10 and set the serial clock and start bit.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Figure 9-2. Format of Serial Operation Mode Register 10
Symbol
<7>
CSIM10 CSIE10
6
5
4
3
2
1
0
Address
After reset
R/W
0
TPS101
TPS100
0
DIR10
CSCK10
0
FF72H
00H
R/W
CSIE10
Operation control in 3-wire serial I/O mode
0
Operation stopped
1
Operation enabled
TPS101
TPS100
Count clock selection when internal clock is selected
2
0
0
fX/2 (1.25 MHz)
0
1
fX/2 (625 kHz)
Other than above
3
Setting prohibited
DIR10
Start bit specification
0
MSB
1
LSB
CSCK10
SIO10 clock selection
0
Input clock to SCK10 pin from external
1
Internal clock selected by TPS100, TPS101
Cautions 1. Bits 0, 3, and 6 must be set to 0.
2. Switch operation mode after stopping the serial transmit/receive operation.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 9 SERIAL INTERFACE 10
(2) Port mode register 2 (PM2)
This register is used to set the I/O mode of port 2 in 1-bit units.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 9-3. Format of Port Mode Register 2
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM2
1
1
1
1
1
PM22
PM21
PM20
FF22H
FFH
R/W
PM2n
I/O mode of P2n pin
(n = 0 to 2)
0
Output mode (output buffer is on)
1
Input mode (output buffer is off)
Caution
Bits 3 to 7 must be set to 1.
Table 9-2. Settings of Serial Interface 10 Operating Mode
(1)
Operation stop mode
CSIM10
PM22
CSIE10
DIR10
CSCK10
0
×
×
×
Note 1
P22
×
Note 1
PM21
×
Note 1
P21
×
Note 1
PM20
×
Note 1
P20
×
Note 1
Other than above
(2)
1
Shift
P22/SI10
P21/SO10
P20/SCK10
Clock
Pin Function
Pin Function
Pin Function
P22
P21
P20
—
—
Setting prohibited
3-wire serial I/O mode
CSIM10
CSIE10
Start
Bit
DIR10
PM22
P22
PM21
P21
PM20
P20
CSCK10
0
0
Note 2
1
×
Note 2
0
1
1
×
Start
Shift
P22/SI10
P21/SO10
P20/SCK10
Bit
Clock
Pin Function
Pin Function
Pin Function
SO10
SCK10 input
MSB
External
SI10
Note 2
clock
1
0
1
Internal
(CMOS output)
SCK10 output
clock
1
1
0
1
×
LSB
External
SCK10 input
clock
1
0
1
Internal
clock
Other than above
Setting prohibited
Notes 1. Can be used as port function.
2. If used only for transmission, can be used as P22 (CMOS I/O).
Remark
130
×: don’t care
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SCK10 output
CHAPTER 9 SERIAL INTERFACE 10
9.4 Serial Interface 10 Operation
Serial interface 10 provides the following two types of modes.
• Operation stop mode
• 3-wire serial I/O mode
9.4.1 Operation stop mode
In the operation stop mode, serial transfer is not executed, therefore enabling a reduction in the power
consumption.
The P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports.
(1)
Register setting
Operation stop mode is set by serial operation mode register 10 (CSIM10).
(a)
Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Symbol
<7>
CSIM10 CSIE10
6
5
4
3
2
1
0
Address
After reset
R/W
0
TPS101
TPS100
0
DIR10
CSCK10
0
FF72H
00H
R/W
CSIE10
Operation control in 3-wire serial I/O mode
0
Operation stopped
1
Operation enabled
Caution
Bits 0, 3, and 6 must be set to 0.
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CHAPTER 9 SERIAL INTERFACE 10
9.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/O and display controllers, etc., which incorporate
a conventional clocked serial interface, such as the 75XL Series, 78K Series, 17K Series.
Communication is performed using three lines: a serial clock line (SCK10), serial output line (SO10), and serial
input line (SI10).
(1)
Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 10 (CSIM10).
(a)
Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Symbol
<7>
CSIM10 CSIE10
6
5
4
3
2
1
0
Address
After reset
R/W
0
TPS101
TPS100
0
DIR10
CSCK10
0
FF72H
00H
R/W
CSIE10
Operation control in 3-wire serial I/O mode
0
Operation stopped
1
Operation enabled
TPS101
TPS100
Count clock selection when internal clock is selected
2
0
0
fX/2 (1.25 MHz)
0
1
fX/2 (625 kHz)
Other than above
3
Setting prohibited
DIR10
Start bit specification
0
MSB
1
LSB
CSCK10
SIO10 clock selection
0
Input clock to SCK10 pin from external
1
Internal clock selected by TPS100, TPS101
Cautions 1. Bits 0, 3, and 6 must be set to 0.
2. Switch operation mode after stopping the serial transmit/receive operation.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 9 SERIAL INTERFACE 10
(2)
Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
Data is
transmitted/received bit by bit in synchronization with the serial clock.
Transmit shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the serial
clock (SCK10). Transmit data is then held in the SO10 latch and output from the SO10 pin. Also, receive
data input to the SI10 pin is latched in the input bits of SIO10 on the rise of SCK10.
At the end of an 8-bit transfer, the operation of SIO10 stops automatically, and the interrupt request signal
(INTCSI10) is generated.
Figure 9-4. 3-Wire Serial I/O Mode Timing
SCK10
1
2
3
4
5
6
7
8
SI10
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO10
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
INTCSI10
Transfer starts at the falling edge of SCK10
Cautions
End of transfer
1. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0), the
data cannot be transmitted or received.
2. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0) and
then serial operation is enabled (CSIE10 = 1), the data cannot be transmitted or
received.
3. Once data has been written to SIO10 with the external serial clock selected (CSCK10 =
0), overwriting the data does not update the contents of SIO10.
4. When CSIM10 is operated during data transmission/reception, data cannot be
transmitted or received normally.
5. When SIO10 is operated during data transmission/reception, the data cannot be
transmitted or received normally.
(3)
Transfer start
Serial transfer is started by setting transfer data to the transmit shift register 10 (SIO10) when the following
two conditions are satisfied.
• Bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) = 1
• Internal serial clock is stopped or SCK10 is a high level after 8-bit serial transfer.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI10).
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CHAPTER 10 LCD CONTROLLER/DRIVER
10.1 LCD Controller/Driver Functions
The functions of the LCD controller/driver of the µPD789327 Subseries are as follows.
(1)
Automatic output of segment and common signals based on automatic display data memory read
(2)
Two different display modes:
• Static
• 1/4 duty (1/3 bias)
(3)
Four different frame frequencies, selectable in each display mode
(4)
Up to 24 segment signal outputs (S0 to S23) and four common signal outputs (COM0 to COM3)
(5)
Operation with a subsystem clock
Table 10-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 10-1. Maximum Number of Pixels
Bias Mode
Number of Time Slices
Common Signals
Maximum Number of Pixels
Used
−
Static
24 (24 segments × 1 common)
Note 1
COM0 (COM1 to
COM3)
1/3
4
96 (24 segments × 4 commons)
Note 2
COM0 to COM3
Notes 1. 3-digit LCD panel, each digit having an 8-segment
configuration.
2. 12-digit LCD panel, each digit having a 2-segment
configuration.
10.2 LCD Controller/Driver Configuration
The LCD controller/driver consists of the following hardware.
Table 10-2. Configuration of LCD Controller/Driver
Item
Display outputs
Control registers
Configuration
Segment signals:
24
Common signals:
4
LCD display mode register 0 (LCDM0)
LCD clock control register 0 (LCDC0)
Port function register 8 (PF8)
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Figure 10-1. Block Diagram of LCD Controller/Driver
Internal bus
LCD clock control
register 0 (LCDC0)
LCD display mode
register 0 (LCDM0)
LCDON0 VAON0 LCDM02
LCDC03 LCDC02 LCDC01 LCDC00
FA00H
76543210
FA11H
76543210
FA16H
76543210
FA17H
76543210
3210
Selector
3210
Selector
3210
Selector
3210
Selector
Port function
register 8 (PF8)
2
2
Display data memory
PF85 PF84 PF83 PF82 PF81 PF80
Selector
fLCD
fLCD
26
Prescaler
fLCD
27
fLCD
28
fLCD
29
LCD
clock LCDCL
selector
Timing
controller
LCDON0
LCDON0
Gate voltage
amplifier
LCD drive voltage controller
VSS
1 VLC0
3
LCDON0
Level shifter
Level shifter
Level shifter
Level shifter
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Common driver
PF85
RLCD
RLCD
LCDON0
PF80
RLCD
2 VLC0
3
VLC0
COM0 COM1 COM2 COM3
S0
S17/P85
S22/P80
S23
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15043EJ3V1UD
fX/25
fX/26
fX/27
fXT
135
CHAPTER 10 LCD CONTROLLER/DRIVER
10.3 Registers Controlling LCD Controller/Driver
• LCD display mode register 0 (LCDM0)
• LCD clock control register 0 (LCDC0)
• Port function register 8 (PF8)
(1)
LCD display mode register 0 (LCDM0)
LCDM0 specifies whether to enable display operation. It also specifies the operation mode and display mode.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDM0 to 00H.
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CHAPTER 10 LCD CONTROLLER/DRIVER
Figure 10-2. Format of LCD Display Mode Register 0
Symbol
<7>
LCDM0 LCDON0
<6>
5
4
3
2
1
0
Address
After reset
R/W
VAON0
0
0
0
LCDM02
0
0
FFB0H
00H
R/W
LCDON0
LCD display enable/disable
0
Display off (all segment outputs are unselected for signal output)
1
Display on
VAON0
LCD controller/driver operation mode
0
No gate voltage amplification (for VLC0 = 2.7 to 5.5 V display)
1
Gate voltage amplification enabled (for VLC0 = 1.8 to 5.5 V display)
LCDM02
Display mode selection
0
Four-time slot, 1/3 bias mode
1
Static mode
Note 1
Note 2
Notes 1. When LCD display is not performed, the power consumption can be lowered by clearing VAON0 to
0.
2. To set the STOP mode while the main system clock is selected as the LCD source clock, select
the static mode (LCDM02 = 1).
Cautions 1. Bits 0,1, 3 to 5 must be set to 0.
2. When operating VAON0, follow the procedure described below.
A. To stop gate voltage amplification after switching display status from on to off:
1) Set to display off status by setting LCDON0 = 0.
2) Stop gate voltage amplification by setting VAON0= 0.
B. To stop gate voltage amplification during display on status:
Setting prohibited. Be sure to stop gate voltage amplification after setting display
off.
C. To set display on from gate voltage amplification stop status:
1) Start gate voltage amplification by setting VAON0 = 1, then wait for about 500 ms.
2) Set display on by setting LCDON0 = 1.
D. To start voltage amplification during display on status:
Setting prohibited. Be sure to setting display off, and follow the procedure in C.
3. When the main system clock is selected as the LCD source clock, If the STOP mode is
selected, an abnormal display may occur. Before selecting the STOP mode, disable
display and select the static mode (LCDON0 = 0 and LCDM02 = 1). If the subsystem
clock is selected as the LCD source clock, a normal operation is performed in the STOP
mode.
4. The LCD may momentarily light for 1 cycle immediately after the display has been
turned on/off because the waveform has not become stabilized.
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CHAPTER 10 LCD CONTROLLER/DRIVER
(2)
LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined by the LCD clock
and the number of time divisions.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDC0 to 00H.
Figure 10-3. Format of LCD Clock Control Register 0
Symbol
7
6
5
4
3
2
1
<0>
Address
After reset
R/W
LCDC0
0
0
0
0
LCDC03
LCDC02
LCDC01
LCDC00
FFB2H
00H
R/W
LCDC03
LCDC02
0
0
fXT (32.768 kHz)
0
1
fX/2 (156.3 kHz)
1
0
fX/2 (78.1 kHz)
1
1
fX/2 (39.1 kHz)
LCDC01
LCDC00
LCD source clock (fLCD) selection
Note
5
6
7
LCD clock (LCDCL) selection
0
0
fLCD/2
6
0
1
fLCD/2
7
1
0
fLCD/2
8
1
1
fLCD/2
9
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Be sure to turn off the display (LCDON = 0) and stop the voltage amplifier (VAON0 = 0)
before changing the LCDC0 settings.
For example, Table 10-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied to the LCD
source clock (fLCD).
Table 10-3. Frame Frequencies (Hz)
LCD Clock (LCDCL)
9
fXT/2
8
fXT/2
7
fXT/2
6
(64 Hz)
(128 Hz)
(256 Hz)
(512 Hz)
Static
64
128
256
512
4
16
32
64
128
Time Division
138
fXT/2
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CHAPTER 10 LCD CONTROLLER/DRIVER
(3)
Port function register 8 (PF8)
PF8 specifies whether S17/P85 to S22/P80 are used as LCD segment signal outputs or general-purpose
ports in 1-bit units.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PF8 to 00H.
Figure 10-4. Format of Port Function Register 8
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PF8
0
0
PF85
PF84
PF83
PF82
PF81
PF80
FF58H
00H
R/W
PF8n
Port function of P8n (n = 0 to 5)
0
Operates as a general-purpose port
1
Operates as an LCD segment signal output
Cautions 1. Bits 6 and 7 must be set to 0.
2. When port 8 is used as a general-purpose port, observe the following restriction
(because an ESD protection circuit for LCD pins (on the high-level side of port 8) is
connected to VLC0).
• When any one of pins P80/S22 to P85/S17 is used as a general-purpose input port pin,
use the microcontroller at VDD = VLC0 or VDD < VLC0.
There is no restriction when all of pins P80/S22 to P85/S17 are used as LCD segment
pins or general-purpose output port pins.
VLC0
P8n output signal
P-ch
VLC0
If a voltage higher than VLC0 is
input to the P8n/Sm pin, the
current flows from the pin to VLC0.
As a result, the voltage of VLC0
becomes unstable.
N-ch
PM8n
VSS
Segment buffer
P8n/Sm
Sm output signal
VDD
P8n input signal
VSS
PF8n
VSS
RD
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CHAPTER 10 LCD CONTROLLER/DRIVER
Remark Sm:
P8n:
LCD segment output (m = 22 to 17)
Bit n of Port 8 (n = 0 to 5)
PF8n:
Bit n of Port function register 8 (n = 0 to 5)
RD:
Port 8 read signal
10.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
<To enable gate voltage amplification>
<1> Set the frame frequency using LCD clock control register 0 (LCDC0).
<2> Set VAON0 (bit 6 of LCDM0) (VAON0 = 1).
Wait for 500 ms or more after setting VAON0.
<3> Start output corresponding to each display data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 =1).
<When gate voltage is not amplified>
<1> Set the frame frequency using LCD clock control register 0 (LCDC0).
<2> Start output corresponding to each display data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 =1).
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CHAPTER 10 LCD CONTROLLER/DRIVER
10.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses FA00H to FA17H. Data in the LCD display data memory
can be displayed on the LCD panel using the LCD controller/driver.
Figure 10-5 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
That part of the display data memory which is not used for display can be used as ordinary RAM.
Figure 10-5. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
Address
b7
b6
b5
b4
b3
b2
b1
b0
FA17H
S23
FA16H
S22
FA15H
S21
S20
FA02H
S2
FA01H
S1
FA00H
S0
COM3
COM2
COM1
COM0
Caution No memory has been installed as the higher 4 bits of the LCD display data memory. Be sure to
set 0 to them.
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CHAPTER 10 LCD CONTROLLER/DRIVER
10.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). It turns off when the potential
difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it. To avoid this
problem, this LCD panel is driven with AC voltage.
(1)
Common signals
Each common signal is selected sequentially according to a specified number of time slots at the timing listed
in Table 10-4.
Table 10-4. COM Signals
COM Signal
COM0
COM1
COM2
COM3
Number of Time Slots
Static display mode
Four-time slot mode
(2)
Segment signals
The segment signals correspond to 24 bytes of LCD display data memory (FA00H to FA17H). Bits 0, 1, 2,
and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If the
contents of each bit are 1, it is converted to the select voltage, and if 0, it is converted to the deselect voltage.
The conversion results are output to the segment pins (S0 to S23).
Check, with the information given above, what combination of the front-surface electrodes (corresponding to
the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display
patterns in the LCD display data memory, and write the bit data that corresponds to the desired display
pattern on a one-to-one basis.
LCD display data memory bits 1 to 3 are not used for LCD display in the static display. So these bits can be
used for purposes other than display.
LCD display data memory bits 4 to 7 are fixed to 0.
(3)
Output waveforms of common and segment signals
The voltages listed in Table 10-5 are output as common and segment signals.
When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained.
The other combinations of the signals correspond to the display off-voltage.
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CHAPTER 10 LCD CONTROLLER/DRIVER
Table 10-5. LCD Drive Voltage
(a) Static display mode
Segment Signal
Select Signal Level
Deselect Signal Level
VSS0/VLC0
VLC0/VSS0
Common Signal
VLC0/VSS0
–VLCD/+VLCD
0 V/0 V
(b) 1/3 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
VSS0/VLC0
VLC1/VLC2
Common Signal
Select signal level
VLC0/VSS0
–VLCD/+VLCD
Deselect signal level
VLC2/VLC1
–
1
3
VLCD/+
–
1
3
VLCD
–
1
3
1
3
VLCD/+
VLCD/+
1
3
1
3
VLCD
VLCD
Figure 10-6 shows the common signal waveforms, and Figure 10-7 shows the voltages and phases of the common
and segment signals.
Figure 10-6. Common Signal Waveforms
(a) Static display mode
VLC0
COM0
VLCD
(Static display)
VSS
TF = T
T: One LCD clock period
TF: Frame frequency
(b) 1/3 bias method
VLC0
COMn
VLC1
VLC2
VSS
(Four-time slot mode)
VLCD
TF = 4 × T
T: One LCD clock period
TF: Frame frequency
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CHAPTER 10 LCD CONTROLLER/DRIVER
Figure 10-7. Voltages and Phases of Common and Segment Signals
(a) Static display mode
Select
Deselect
VLC0
VLCD
Common signal
VSS
VLC0
VLCD
Segment signal
VSS
T
T
T: One LCD clock period
(b) 1/3 bias method
Select
Deselect
VLC0
VLC1
VLC2
Common signal
VLCD
VSS
VLC0
VLC1
VLC2
Segment signal
VSS
T
T
T: One LCD clock period
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VLCD
CHAPTER 10 LCD CONTROLLER/DRIVER
10.7 Display Modes
10.7.1 Static display example
Figure 10-9 shows how the three-digit LCD panel having the display pattern shown in Figure 10-8 is connected to
the segment signals (S0 to S23) and the common signal (COM0) of the µPD789327 Subseries chip. This example
displays data "12.3" in the LCD panel. The contents of the display data memory (addresses FA00H to FA17H)
correspond to this display.
The following description focuses on numeral "2." (
) displayed in the second digit. To display "2." in the LCD
panel, it is necessary to apply the select or deselect voltage to the S8 to S15 pins according to Table 10-6 at the
timing of the common signal COM0; see Figure 10-8 for the relationship between the segment signals and LCD
segments.
Table 10-6. Select and Deselect Voltages (COM0)
Segment
S8
S9
S10
S11
S12
S13
S14
S15
Select
Deselect
Select
Select
Deselect
Select
Select
Select
Common
COM0
According to Table 10-6, it is determined that the bit-0 pattern of the display data memory locations (FA08H to
FA0FH) must be 10110111.
Figure 10-10 shows the LCD drive waveforms of S11 and S12, and COM0. When the select voltage is applied to
S11 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding
LCD segment.
COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected
together to increase the driving capacity.
Figure 10-8. Static LCD Display Pattern and Electrode Connections
S8n+3
S8n+4
S8n+2
S8n+5
S8n+6
COM0
S8n+1
S8n
S8n+7
Remark
n = 0 to 2
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CHAPTER 10 LCD CONTROLLER/DRIVER
Figure 10-9. Example of Connecting Static LCD Panel
Timing Strobe
COM 3
COM 2
COM 1
3
4
5
6
Data Memory Address
7
8
9
A
B
C
D
E
F
FA10H
1
2
3
4
5
6
7
Bit 1
Bit 0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
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LCD panel
2
0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0
1
× × × × × × × × × × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × × × × × × × × × ×
Bit 3
Bit 2
COM 0
FA00H
146
Can be connected
together
CHAPTER 10 LCD CONTROLLER/DRIVER
Figure 10-10. Static LCD Drive Waveform Examples
TF
VLC0
COM0
VSS
VLC0
S11
VSS
VLC0
S12
VSS
+VLCD
COM0 to S11
0
–VLCD
+VLCD
COM0 to S12
0
–VLCD
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CHAPTER 10 LCD CONTROLLER/DRIVER
10.7.2 Four-time slot display example
Figure 10-12 shows how the 12-digit LCD panel having the display pattern shown in Figure 10-11 is connected to
the segment signals (S0 to S23) and the common signals (COM0 to COM3) of the µPD789327 Subseries chip. This
example displays data “123456.789012” in the LCD panel. The contents of the display data memory (addresses
FA00H to FA17H) correspond to this display.
The following description focuses on numeral “6.” (
) displayed in the seventh digit. To display “6.” in the LCD
panel, it is necessary to apply the select or deselect voltage to the S12 and S13 pins according to Table 10-7 at the
timing of the common signals COM0 to COM3; see Figure 10-11 for the relationship between the segment signals and
LCD segments.
Table 10-7. Select and Deselect Voltages (COM0 to COM3)
Segment
S12
S13
COM0
Select
Select
COM1
Deselect
Select
COM2
Select
Select
COM3
Select
Select
Common
According to Table 10-7, it is determined that the display data memory location (FA0CH) that corresponds to S12
must contain 1101.
Figure 10-13 shows examples of LCD drive waveforms between the S12 signal and each common signal. When
the select voltage is applied to S12 at the timing of COM0, an alternate rectangle waveform, +VLCD/–VLCD, is
generated to turn on the corresponding LCD segment.
Figure 10-11. Four-Time Slot LCD Display Pattern and Electrode Connections
S2n
;;
;;;;;;
;
COM0
COM2
S2n+1
Remark
148
COM1
n = 0 to 11
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CHAPTER 10 LCD CONTROLLER/DRIVER
Figure 10-12. Example of Connecting Four-Time Slot LCD Panel
Timing strobe
COM 3
COM 2
COM 1
2
3
4
5
6
7
Data memory address
8
9
A
B
C
D
E
F
FA10H
1
2
3
4
5
6
7
Bit 1
Bit 2
Bit 0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
LCD panel
1
0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1
0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1
FA00H
0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0
Bit 3
COM 0
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
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CHAPTER 10 LCD CONTROLLER/DRIVER
Figure 10-13. Four-Time Slot LCD Drive Waveform Examples
TF
VLC0
VLC1
COM0
VLC2
VSS
VLC0
VLC1
COM1
VLC2
VSS
VLC0
VLC1
COM2
VLC2
VSS
VLC0
VLC1
COM3
VLC2
VSS
VLC0
VLC1
S12
VLC2
VSS
+VLCD
+1/3VLCD
COM0-S12
0
−1/3VLCD
−VLCD
+VLCD
+1/3VLCD
0
COM1-S12
−1/3VLCD
−VLCD
Remark The waveforms of COM2-S12 and COM3-S12 are not shown in the above chart.
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS
µPD789327 Subseries provides a power-on-clear (POC) circuit.
In the flash memory version (µPD78F9328), the POC circuit is always operating. However, it can only be used
when selected by a mask option in mask ROM versions (µPD789322, 789324, 789326, and 789327) (see CHAPTER
16 MASK OPTIONS).
11.1 Power-on-Clear Circuit Functions
The power-on-clear circuits include the following function.
(1)
Power-on-clear (POC) circuit
• Compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal
reset signal if VDD < VPOC.
• This circuit can operate even in STOP mode.
11.2 Power-on-Clear Circuit Configuration
Figure 11-1 shows the block diagram of the power-on-clear circuits.
Figure 11-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Detection
voltage
source (VPOC)
POCOF1
Power-on-clear
register 1 (POCF1)
Internal bus
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS
11.3 Register Controlling Power-on-Clear Circuit
The power-on-clear circuits are controlled by the following register.
• Power-on-clear register 1 (POCF1)
(1)
Power-on-clear register 1 (POCF1)
POCF1 controls POC circuit operation.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
Figure 11-2. Format of Power-on-Clear Register 1
Symbol
POCF1
7
0
6
5
0
0
4
3
0
0
POCOF1
<2>
POCOF1
1
0
0
0
Address
FFDDH
After reset
Note
00H
R/W
R/W
POC output detection flag
0
Non-generation of reset signal by POC or in cleared state due to a write operation to POCF1
1
Generation of reset signal by POC
Note This value is 04H only after a power-on-clear reset.
11.4 Power-on-Clear Circuit Operation
The POC circuit compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an
internal reset signal if VDD < VPOC.
When a reset is generated via the power-on-clear circuit in bit 2 (POCOF1) on the power-on-clear register
(POCF1) is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e.
after program execution has started from address 0000H), a power failure can be detected by detecting POCOF1.
Caution Use of the POC circuit can be selected by a mask option in the case of the mask ROM version.
With the µPD78F9328, use of the POC circuit cannot be selected (always operating).
Figure 11-3. Timing of Internal Reset Signal Generation of POC Circuit
Power supply voltage (VDD)
Detection voltage (VPOC)
1.8 V
Time
Internal reset
signal
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CHAPTER 12 INTERRUPT FUNCTIONS
12.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1)
Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
(2)
Maskable interrupt
This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Table 12-1.
A standby release signal is generated.
2 external and 6 internal interrupt sources are incorporated as maskable interrupts.
12.2 Interrupt Sources and Configuration
A total of 9 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table
12-1).
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CHAPTER 12 INTERRUPT FUNCTIONS
Table 12-1. Interrupt Source List
Note 1
Interrupt Type
Priority
Interrupt Source
Name
Non-maskable
−
INTWDT
Trigger
Watchdog timer overflow (with
Internal/
Vector Table
Basic
External
Address
Configuration
Note 2
Type
Internal
0004H
(A)
watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow (with
(B)
interval timer mode selected)
1
INTP0
2
INTCSI10
Pin input edge detection
External
0006H
(C)
End of serial interface 10 3-wire
Internal
0008H
(B)
SIO transfer reception
3
INTWT
4
INTTM30
Watch timer interrupt
000AH
Generation of 8-bit timer 30
000CH
matching signal
5
INTTM40
Generation of 8-bit timer 40
000EH
matching signal
6
INTKR00
7
INTWTI
Key return signal detection
External
0010H
(C)
Watch timer interval timer
Internal
0012H
(B)
interrupt
Notes 1. Priority is the priority order when more than one maskable interrupt request is generated at the same
time. 0 is the highest priority and 7 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 12-1.
Remark
There are two interrupt sources for the watchdog timer (INTWDT):
non-maskable and maskable
interrupts (internal). Either one (but not both) should be selected for actual use.
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CHAPTER 12 INTERRUPT FUNCTIONS
Figure 12-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt request
IE
Vector table
address generator
IF
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, KRM00
Interrupt
request
Edge
detector
MK
IE
IF
Vector table
address generator
Standby
release signal
INTP0:
External interrupt mode register 0
KRM00:
Key return mode register 00
IF:
Interrupt request flag
IE:
Interrupt enable flag
MK:
Interrupt mask flag
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CHAPTER 12 INTERRUPT FUNCTIONS
12.3 Registers Controlling Interrupt Function
The following five types of registers are used to control the interrupt functions.
• Interrupt request flag register 0 (IF0)
• Interrupt mask flag register 0 (MK0)
• External interrupt mode register 0 (INTM0)
• Program status word (PSW)
• Key return mode register 00 (KRM00)
Table 12-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt
requests.
Table 12-2. Flags Corresponding to Interrupt Request Signal Name
Interrupt Request Signal Name
Interrupt Request Flag
Interrupt Mask Flag
INTWDT
WDTIF
WDTMK
INTP0
PIF0
PMK0
INTCSI10
CSIIF10
CSIMK10
INTWT
WTIF
WTMK
INTTM30
TMIF30
TMMK30
INTTM40
TMIF40
TMMK40
INTKR00
KRIF00
KRMK00
INTWTI
WTIIF
WTIMK
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CHAPTER 12 INTERRUPT FUNCTIONS
(1)
Interrupt request flag register 0 (IF0)
An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an
instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal
is input, or when an instruction is executed.
IF0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF0 to 00H.
Figure 12-2. Format of Interrupt Request Flag Register 0
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address
After reset
R/W
IF0
WTIIF
KRIF00
TMIF40
TMIF30
WTIF
CSIIF10
PIF0
WDTIF
FFE0H
00H
R/W
××IF×
Interrupt request flag
0
No interrupt request signal generated
1
An interrupt request signal is generated and an interrupt request made
Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an
interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer
mode 1 or 2.
2. Because P61 functions alternately as an external interrupt input, when the output level
changes after the output mode of the port function is specified, the interrupt request
flag will be inadvertently set.
Therefore, be sure to preset the interrupt mask flag
(PMK0) to 1 before using the port in output mode.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared
and then the interrupt routine is started.
(2) Interrupt mask flag register 0 (MK0)
Interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 to FFH.
Figure 12-3. Format of Interrupt Mask Flag Register 0
Symbol
<7>
MK0
WTIMK
<6>
<5>
<4>
KRMK00 TMMK40 TMMK30
××MK
<3>
<2>
<1>
<0>
Address
After reset
R/W
WTMK
CSIMK10
PMK0
WDTMK
FFE4H
FFH
R/W
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to
read the WDTMK flag results in an undefined value being detected.
2. Because P61 functions alternately as an external interrupt input, when the output level
changes after the output mode of the port function is specified, the interrupt request
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CHAPTER 12 INTERRUPT FUNCTIONS
flag will be inadvertently set.
Therefore, be sure to preset the interrupt mask flag
(PMK0) to 1 before using the port in output mode.
(3)
External interrupt mode register 0 (INTM0)
INTM0 is used to specify the valid edge for INTP0.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 12-4. Format of External Interrupt Mode Register 0
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
INTM0
0
0
0
0
ES01
ES00
0
0
FFECH
00H
R/W
ES01
ES00
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both rising and falling edges
INTP0 valid edge selection
Cautions 1. Bits 0, 1, and 4 to 7 must be set to 0.
2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts.
To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the
interrupt mask flag (PMK0).
(4)
Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and
dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved
into a stack, and the IE flag is reset to 0.
RESET input sets PSW to 02H.
Figure 12-5. Configuration of Program Status Word
Symbol
7
6
5
4
3
2
1
0
After reset
PSW
IE
Z
0
AC
0
0
1
CY
02H
Used when normal instruction is executed
IE
158
Interrupt acknowledgement enabled/disabled
0
Disabled
1
Enabled
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CHAPTER 12 INTERRUPT FUNCTIONS
(5)
Key return mode register 00 (KRM00)
This register is used to specify whether the key return signal (falling edge of port 4) is to be detected.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears KRM00 to 00H.
Figure 12-6. Format of Key Return Mode Register 00
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
KRM00
0
0
0
0
0
0
0
KRM00
FFF5H
00H
R/W
KRM00
Key return signal detection control
0
No detection
1
Detection (detecting falling edge of port 4)
Cautions 1. Bits 1 to 7 must be set to 0.
2. Before setting KRM00, always set bit 6 of MK0 (KRMK00 = 1) to disable interrupts. After
setting KRM00, clear KRMK00 after clearing bit 6 of IF1 (KRIF00 = 0) to enable interrupts.
3. On-chip pull-up resistors are automatically connected in input mode to the pins
specified for key return signal detection (P40 to P43). Although these resistors are
disconnected when the mode changes to output, key return signal detection continues
unchanged.
4. The key return signal can be detected while all of P40 to P43 are high level. The key
return signal cannot be detected while even one of P40 to P43 is low, even if any other
key return pin goes low.
Figure 12-7. Block Diagram of Falling Edge Detector
Key return mode register 00 (KRM00)
Note
P41/KR01
P42/KR02
Selector
P40/KR00
Falling edge detector
INTKR00
P43/KR03
KRMK00
Standby release
signal
Note Selector that selects the pin used for falling edge input
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CHAPTER 12 INTERRUPT FUNCTIONS
12.4 Interrupt Servicing Operation
12.4.1 Non-maskable interrupt request acknowledgment operation
The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 12-8 shows the flow from non-maskable interrupt request generation to acknowledgement, Figure 12-9
shows the timing of non-maskable interrupt acknowledgement, and Figure 12-10 shows the acknowledgement
operation when a number of non-maskable interrupts are generated.
Caution During non-maskable interrupt service program execution, do not input another non-maskable
interrupt request; if it is input, the service program will be interrupted and the new nonmaskable interrupt request will be acknowledged.
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Figure 12-8. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment
Start
WDTM4 = 1
(watchdog timer mode
is selected)
No
Interval timer
Yes
No
WDT
overflows
Yes
WDTM3 = 0
No
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing starts
WDTM: Watchdog timer mode register
WDT:
Watchdog timer
Figure 12-9. Timing of Non-Maskable Interrupt Request Acknowledgment
CPU processing
Instruction
Instruction
Saving PSW and PC, and
jump to interrupt servicing
Interrupt servicing program
WDTIF
Figure 12-10. Non-Maskable Interrupt Request Acknowledgment
Main routine
First interrupt servicing
NMI request
(first)
NMI request
(second)
Second interrupt servicing
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CHAPTER 12 INTERRUPT FUNCTIONS
12.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 12-3.
Refer to Figures 12-12 and 12-13 for the timing of interrupt request acknowledgement.
Table 12-3. Time from Generation of Maskable Interrupt Request to Servicing
Note
Minimum Time
Maximum Time
9 clocks
19 clocks
Note The wait time is maximum when an interrupt request is generated immediately before
BT or BF instruction.
Remark
1 clock:
1
fCPU
(fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the one assigned the highest priority by the priority specification flag.
A pending interrupt is acknowledged when the status where it can be acknowledged is set.
Figure 12-11 shows the algorithm of interrupt request acknowledgement.
When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE
flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and
execution branches.
To return from interrupt servicing, use the RETI instruction.
Figure 12-11. Interrupt Request Acknowledgment Program Algorithm
Start
No
xxIF = 1?
Yes (Interrupt request generated)
No
xxMK = 0?
Yes
Interrupt request pending
No
IE = 1?
Yes
Interrupt request pending
Vectored interrupt
servicing
xxIF: Interrupt request flag
xxMK: Interrupt mask flag
IE:
162
Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)
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CHAPTER 12 INTERRUPT FUNCTIONS
Figure 12-12. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
8 clocks
Clock
Saving PSW and PC, and
jump to interrupt servicing
MOV A, r
CPU
Interrupt servicing program
Interrupt
If the interrupt request has generated an interrupt request flag (xxIF) by the time the instruction clocks under
execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the
completion of the instruction under execution. Figure 12-12 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
Figure 12-13. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
8 clocks
Clock
CPU
NOP
MOV A, r
Saving PSW and PC, and
jump to interrupt servicing
Interrupt servicing
program
Interrupt
If the interrupt request flag (xxIF) is generated in the final clock of the instruction, interrupt request acknowledgment
processing will begin after execution of the next instruction is complete.
Figure 12-13 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
instruction). In this case, the interrupt request will be serviced after execution of MOV A, r, which follows NOP, is
complete.
Caution
When interrupt request flag register 0 (IF0), or interrupt mask flag register 0 (MK0) is being
accessed, interrupt requests will be held pending.
12.4.3 Multiple interrupt servicing
Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced,
can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in the
order according to the priority assigned to each interrupt request in advance (refer to Table 12-1).
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CHAPTER 12 INTERRUPT FUNCTIONS
Figure 12-14. Example of Multiple Interrupts
Example 1. Acknowledging multiple interrupts
INTxx servicing
Main servicing
EI
IE = 0
EI
INTyy servicing
IE = 0
INTyy
INTxx
RETI
RETI
The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are
performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is
enabled.
Example 2. Multiple interrupts are not performed because interrupts are disabled
INTxx servicing
Main servicing
EI
IE = 0
INTyy servicing
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupt requests are disabled (the EI instruction has not been issued) in the interrupt INTxx servicing,
the interrupt request INTyy is not acknowledged and multiple interrupts are not performed. INTyy is held pending and
is acknowledged after INTxx servicing is completed.
IE = 0: Interrupt requests disabled
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12.4.4 Putting interrupt requests on hold
If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type
of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such
instructions (interrupt request pending instructions) are as follows.
• Instructions that manipulate interrupt request flag register 0 (IF0)
• Instructions that manipulate interrupt mask flag register 0 (MK0)
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CHAPTER 13 STANDBY FUNCTION
13.1 Standby Function and Configuration
The standby function is to reduce the power consumption of the system and can be effected in the following two
modes:
(1)
HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the operating current as
much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2)
STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in
this mode.
The data memory can be retained at the low voltage (VDD = 1.8 V). Therefore, this mode is useful for
retaining the contents of the data memory at an extremely low operating current.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are
all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
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13.2 Register Controlling Standby Function
The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with
the oscillation stabilization time selection register (OSTS).
OSTS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. Note that the time required for oscillation to stabilize after RESET input varies
depending on the device (refer to Table 13-1), not depending on OSTS.
Figure 13-1. Format of Oscillation Stabilization Time Selection Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
FFFAH
04H
R/W
OSTS2
OSTS1
OSTS0
0
0
0
2 /fX (819 µs)
0
1
0
2 /fX (6.55 ms)
1
0
0
2 /fX (26.2 ms)
Other than above
12
15
17
Setting prohibited
Caution The wait time after the STOP mode is released does not include the time from STOP mode
release to clock oscillation start (“a” in the figure below), regardless of whether STOP
mode is released by RESET input or by interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 13-1. Oscillation Stabilization Time After RESET Input
Part Number
Oscillation Stabilization Time After RESET Input
µPD789322, 789324, 789326, 789327
2 /fX or 2 /fX (selectable using mask option)
µPD78F9328
2 /fX
15
17
15
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CHAPTER 13 STANDBY FUNCTION
13.3 Standby Function Operation
13.3.1 HALT mode
(1)
HALT mode
The HALT mode is set by executing the HALT instruction.
The operation status in the HALT mode is shown in the following table.
Table 13-2. Operation Statuses in HALT Mode
Item
HALT Mode Operation Status During Main
HALT Mode Operation Status During Subsystem
System Clock Operation
Clock Operation
Subsystem Clock
Subsystem Clock
Main System Clock
Main System Clock
Operating
Stopped
Operating
Stopped
Main system clock
Can be oscillated
Oscillation stopped
CPU
Operation stopped
Ports (output latches)
Status before HALT mode setting retained
8-bit timer 30, 40
Operable
Operation stopped
Watch timer
Operable
Operable
Watchdog timer
Operable
Power-on-clear circuit
Operable
Key return circuit
Operable
Serial interface 10
Operable
LCD controller/driver
Operable
External interrupts
Operable
Note 1
Operable
Operation stopped
Note 3
Note 4
Operable
Note 5
Operable
Notes 1, 5
Operable
Note 5
Note 3
Notes 1. Operation is enabled when the main system clock is selected
2. Operation is enabled when the subsystem clock is selected
3. Operation is enabled only for a maskable interrupt that is not masked
4. Operation is enabled only when an external clock is selected
5. The HALT instruction can be set after display instruction execution
168
Note 2
Operable
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Operable
Notes 2, 5
CHAPTER 13 STANDBY FUNCTION
(2)
Releasing HALT mode
The HALT mode can be released by the following three types of sources:
(a)
Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled
to be acknowledged, vectored interrupt processing is performed.
If the interrupt is disabled, the
instruction at the next address is executed.
Figure 13-2. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Standby
release signal
Operation
mode
HALT mode
Wait
Operation mode
Oscillation
Clock
Remarks 1. The broken line indicates the case where the interrupt request that has released the standby mode
is acknowledged.
2. The wait time is as follows:
• When vectored interrupt processing is performed:
• When vectored interrupt processing is not performed:
(b)
9 to 10 clocks
1 to 2 clocks
Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored
interrupt processing is performed.
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CHAPTER 13 STANDBY FUNCTION
(c)
Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
Figure 13-3. Releasing HALT Mode by RESET Input
HALT
instruction
WaitNote
RESET
signal
Operation
mode
Clock
HALT mode
Reset
period
Oscillation
stabilization
wait status
Oscillation
Oscillation
stops
Oscillation
Operation
mode
Note 215/fX: 6.55 ms (@ fX = 5.0 MHz operation)
Remark
fX: Main system clock oscillation frequency
Table 13-3. Operation After Releasing HALT Mode
MK××
IE
0
0
Executes next address instruction
0
1
Executes interrupt servicing
1
×
Retains HALT mode
Non-maskable interrupt request
−
×
Executes interrupt servicing
RESET input
-−-
−
Reset processing
Releasing Source
Maskable interrupt request
Operation
×: don’t care
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CHAPTER 13 STANDBY FUNCTION
13.3.2 STOP mode
(1)
Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then an
operation mode is set.
The operation status in the STOP mode is shown in the following table.
Table 13-4. Operation Statuses in STOP Mode
Item
STOP Mode Operation Status During Main System Clock Operation
Subsystem Clock Operating
Main system clock
Oscillation stopped
CPU
Operation stopped
Ports (output latches)
Status before STOP mode setting retained
8-bit timer 30, 40
Operation stopped
Watch timer
Operable
Watchdog timer
Operation stopped
Power-on-clear circuit
Operable
Key return circuit
Operable
Serial interface 10
Operable
LCD controller/driver
Operable
External interrupts
Operable
Note 1
Subsystem Clock Stopped
Operation stopped
Note 2
Note 3
Note 1
Operation stopped
Note 4
Note 2
Notes 1. Operation is enabled when the subsystem clock is selected.
2. Operation is enabled only for a maskable interrupt that is not masked.
3. Operation is enabled only when an external clock is selected.
4. Before selecting the STOP mode, disable display and select the static mode (refer to 10.3 (1) LCD
display mode register 0 (LCDM0) ).
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CHAPTER 13 STANDBY FUNCTION
(2)
Releasing STOP mode
The STOP mode can be released by the following two types of sources:
(a)
Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is
enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation
stabilization time has elapsed. If the interrupt is disabled, the instruction at the next address is executed.
Figure 13-4. Releasing STOP Mode by Interrupt
Wait
(set time by OSTS)
STOP
instruction
Standby
release signal
Clock
Remark
Operation
mode
STOP mode
Oscillation stabilization
wait status
Oscillation
Oscillation
stops
Oscillation
The broken line indicates the case where the interrupt request that has released the standby mode is
acknowledged.
172
Operation
mode
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CHAPTER 13 STANDBY FUNCTION
(b)
Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 13-5. Releasing STOP Mode by RESET Input
STOP
instruction
WaitNote
RESET
signal
Operation
mode
Clock
Oscillation
stabilization
wait status
Reset
period
STOP mode
Oscillation
stops
Oscillation
Operation
mode
Oscillation
Note 215/fX: 6.55 ms (@ fX = 5.0 MHz operation)
Remark
fX: Main system clock oscillation frequency
Table 13-5. Operation After Releasing STOP Mode
Releasing Source
Maskable interrupt request
RESET input
MK××
IE
0
0
Executes next address instruction
0
1
Executes interrupt servicing
1
×
Retains STOP mode
−
-−-
Reset processing
Operation
×: don’t care
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CHAPTER 14 RESET FUNCTION
The following three operations are available to generate reset signals.
(1) External reset signal input via RESET pin
(2) Internal reset by detection of watchdog timer inadvertent program loop time
(3) Internal reset using power-on-clear circuit (POCNote)
The external and internal reset signals are functionally equivalent. When RESET is input, program execution
begins from the addresses written at addresses 0000H and 0001H.
If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each
item of the hardware to enter the states listed in Table 14-1. While a reset is being applied, or while the oscillation
frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state.
If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution is
started after the oscillation stabilization time has elapsed. A reset sequence caused by a watchdog timer overflow is
terminated automatically and program execution is started after the oscillation stabilization time has elapsed.
Reset by power-on-clear (POCNote) is cleared if the supply voltage rises beyond a specific level, and the program
execution is started after the oscillation stabilization time has elapsed.
Note Enabled in mask ROM versions (µPD789322, 789324, 789326, and 789327) only when POC circuit usage
is selected by a mask option.
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
3. The oscillation stabilization time after RESET input or the release of STOP mode by POC can
be selected from 215/fX or 217/fX by mask option (refer to CHAPTER 16 MASK OPTIONS). In
15
the case of the µPD78F9328, only 2 /fX can be set because the mask option is not available.
Figure 14-1. Block Diagram of Reset Function
VDD
Power-on-clear circuit
RESET
Count clock
Watchdog timer
Stop
174
Reset signal
Reset controller
User’s Manual U15043EJ3V1UD
Overflow
Interrupt function
CHAPTER 14 RESET FUNCTION
Figure 14-2. Reset Timing by RESET Input
X1
During normal
operation
Oscillation
stabilization
time wait
Reset period
(oscillation stops)
Normal operation
(reset processing)
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Figure 14-3. Reset Timing by Overflow in Watchdog Timer
X1
Oscillation
stabilization
time wait
Reset period
(oscillation
continues)
During normal
operation
Normal operation
(reset processing)
Overflow in
watchdog timer
Internal
reset signal
Hi-Z
Port pin
Figure 14-4. Reset Timing by RESET Input in STOP Mode
X1
STOP instruction execution
During normal
Stop status
operation
(oscillation stops)
Reset period
(oscillation stops)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
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CHAPTER 14 RESET FUNCTION
Figure 14-5. Reset Timing by Power-on Clear
(a)
At power application
X1
Reset period
(oscillation stops)
VDD
Oscillation stabilization
time wait
Normal operation
(reset processing)
Power-on-clear voltage (VPOC)
Internal reset
signal
Hi-Z
Port pin
(b)
In STOP mode
X1
STOP instruction execution
Stop status
(oscillation stops)
During normal operation
Reset period
(oscillation stops)
Oscillation stabilization
time wait
Normal operation
(reset processing)
VDD
Power-on-clear voltage (VPOC)
Internal reset
signal
Hi-Z
Port pin
(c)
In normal operation mode (including HALT mode)
X1
Reset period
(oscillation stops)
During normal operation
Oscillation stabilization
time wait
Normal operation
(reset processing)
VDD
Power-on-clear voltage (VPOC)
Internal reset
signal
Hi-Z
Port pin
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CHAPTER 14 RESET FUNCTION
Table 14-1. Hardware Status After Reset
Hardware
Note 1
Program counter (PC)
Status After Reset
Contents of reset
vector table (0000H,
0001H) set
Stack pointer (SP)
Undefined
Program status word (PSW)
02H
RAM
Data memory
Undefined
General-purpose registers
Undefined
Note 2
Note 2
Ports (P0 to P2, P4, P6, P8) (output latches)
00H
Port mode registers (PM0 to PM2, PM4, PM6)
FFH
Port mode register 8 (PM8)
3FH
Port function register 8 (PF8)
00H
Pull-up resistor option registers (PU0, PUB2)
00H
Processor clock control register (PCC)
02H
Suboscillation mode register (SCKM)
00H
Subclock control register (CSS)
00H
Oscillation stabilization time selection register (OSTS)
04H
8-bit timer 30, 40
Timer counters (TM30, TM40)
00H
Compare registers (CR30, CR40, CRH40)
Undefined
Mode control registers (TMC30, TMC40)
00H
Carrier generator output control register (TCA40)
00H
Watch timer
Mode control register (WTM)
00H
Watchdog timer
Mode register (WDTM)
00H
Clock selection register (TCL2)
00H
Serial operation mode register 10 (CSIM10)
00H
Transmit/receive shift register 10 (SIO10)
Undefined
Display mode register 0 (LCDM0)
00H
Clock control register 0 (LCDC0)
00H
Power-on-clear circuit
Power-on-clear register 1 (POCF1)
00H
Interrupts
Request flag register 0 (IF0)
00H
Mask flag register 0 (MK0)
FFH
External interrupt mode register 0 (INTM0)
00H
Key return mode register 00 (KRM00)
00H
Serial interface 10
LCD controller/driver
Note 3
Notes 1. While a reset signal is being input, and during the oscillation stabilization time wait, only the contents of
the PC will be undefined; the remainder of the hardware will be the same state as after reset.
2. In standby mode, RAM enters the hold state after reset.
3. The value is 04H only after a power-on-clear reset.
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CHAPTER 15 µPD78F9328
The µPD78F9328 is available as the flash memory version of the µPD789327 Subseries.
The µPD78F9328 is a version with the internal ROM of the µPD789322, 789324, 789326, 789327 replaced with
flash memory. The differences between the µPD78F9328 and the mask ROM versions are shown in Table 15-1.
Table 15-1. Differences Between µPD78F9328 and Mask ROM Versions
Part Number
Flash Memory
Mask ROM Version
Version
µPD78F9328
Item
Internal
ROM
memory
32 KB
µPD789322
4 KB
µPD789324
8 KB
µPD789326
16 KB
µPD789327
24 KB
(flash memory)
High-speed RAM
512 bytes
256 bytes
512 bytes
LCD display RAM 24 × 4 bits
IC0 pin
Not provided
Provided
VPP pin
Provided
Not provided
Power-on clear (POC)
Always operates
Use is selected by mask option
circuit
Oscillation stabilization wait
15
Fixed to 2 /fX
15
17
2 /fX or 2 /fX selected by mask option
time after STOP mode is
released by RESET or POC
Electrical specifications
Caution
Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS
There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
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CHAPTER 15 µPD78F9328
15.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the
target system (on-board). A flash memory writing adapter (program adapter), which is a target board used exclusively
for programming, is also provided.
Remark
FL-PR3, FL-PR4, and the program adapter are the products made by Naito Densei Machida Mfg. Co.,
Ltd. (TEL +81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities low-quantity, varied model production
• Easy data adjustment when starting mass production
15.1.1 Programming environment
The following shows the environment required for µPD78F9328 flash memory programming.
When Flashpro III/Flashpro IV is used as a dedicated flash programmer, a host machine is required to control the
dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS232C/USB (Rev.1.1).
For details, refer the manuals for Flashpro III/Flashpro IV.
Remark
USB is supported by Flashpro IV only.
Figure 15-1. Environment for Writing Program to Flash Memory
VPP
VDD
RS-232C
VSS
USB
RESET
Dedicated flash programmer 3-wire serial I/O
µ PD78F9328
Host machine
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CHAPTER 15 µPD78F9328
15.1.2 Communication mode
Use the communication mode shown in Table 15-2 to perform communication between the dedicated flash
programmer and µPD78F9328.
Table 15-2. Communication Mode List
Note 1
Communication
Mode
TYPE Setting
COMM PORT
CPU Clock
SIO clock
In Flashpro
3-wire serial
I/O
SIO ch-0
(3-wired, sync)
100 Hz to 1.25
Note2
MHz
Pins used
1, 2, 4, 5
Number of
VPP pulses
Multiple rate
On Target Board
Note 2
1 to 5 MHz
1.0
SCK10/P20 0
Notes 2, 3
MHz
SO10/P21
SI10/P22
Notes 1.
Selection items for TYPE settings on the dedicated flash programmer (Flashpro III/Flashpro IV).
2.
The possible setting range differs depending on the voltage.
3.
For Flashpro III, only 2 MHz or 4 MHz can be selected.
For details, refer to CHAPTER 18
ELECTRICAL SPECIFICATIONS.
Caution
Be sure to select a communication mode depending on the number of VPP pulses shown in Table
15-2.
Figure 15-2. Communication Mode Selection Format
10 V
VPP
VDD
1
2
n
VSS
VPP pulses
VDD
RESET
VSS
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CHAPTER 15 µPD78F9328
Figure 15-3. Example of Connection with Dedicated Flash Programmer
µ PD78F9328
Dedicated flash programmer
VPP1
VPP
VDD
VDD
RESET
RESET
SCK
SCK10
SO
SI10
SI
SO10
CLKNote
X1
GND
VSS
Note Connect this pin when the system clock is supplied by dedicated flash programmer. If an oscillator is
already connected to the X1 pin, do not connect to the CLK pin.
Caution
The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. Before using the power supply connected to the VDD pin, supply
voltage before starting programming.
If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the
µPD78F9328. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 15-3. Pin Connection List
Signal Name
VPP1
I/O
Output
Pin Function
Write voltage
−
VPP2
VDD
I/O
−
×
Note1
VDD
Ground
VSS
CLK
Output
Clock output
X1
RESET
Output
Reset signal
RESET
SI
Input
Reception signal
SO10
SO
Output
Transmit signal
SI10
SCK
Output
Transfer clock
SCK10
−
HS
3-Wire Serial I/O
VPP
VDD voltage generation/voltage monitoring
−
GND
Pin Name
−
−
Note2
×
Notes 1. Flashpro III only
2. VDD voltage must be supplied before programming is started.
Remark
: Pin must be connected.
: If the signal is supplied on the target board, pin need not be connected.
×: Pin need not be connected.
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CHAPTER 15 µPD78F9328
15.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between normal operation mode and flash memory programming mode
may be required in some cases.
<VPP pin>
In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0
V (TYP.) is supplied to the VPP pin, so perform the following.
(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.
(2) Use the jumper on the board to switch the VPP pin input to either the writer or directly to GND.
A VPP pin connection example is shown below.
Figure 15-4. VPP Pin Connection Example
µ PD78F9328
Connection pin of dedicated flash programmer
VPP
Pull-down resistor (RVPP)
<Serial interface pin>
The following shows the pins used by the serial interface.
Serial Interface
3-wire serial I/O
Pins Used
SCK10, SO10, SI10
When connecting the dedicated flash programmer a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other devices may occur. Care must therefore be taken with
such connections.
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CHAPTER 15 µPD78F9328
(1)
Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device
or set the other device to the output high impedance status.
Figure 15-5. Signal Conflict (Input Pin of Serial Interface)
µ PD78F9328
Signal conflict
Connection pin of
dedicated flash
programmer
Input pin
Other device
Output pin
In the flash memory programming mode, the signal output by another
device and the signal sent by the dedicated flash programmer conflict,
therefore, isolate the signal of the other device.
(2)
Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that
is connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
input signals to the other device are ignored.
Figure 15-6. Abnormal Operation of Other Device
µ PD78F9328
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the µ PD78F9328 affects another device in the flash
memory programming mode, isolate the signals of the other device.
µ PD78F9328
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signals of the
other device.
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CHAPTER 15 µPD78F9328
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal
generator.
If the reset signal is input from the user system in the flash memory programming mode, a normal programming
operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash
programmer.
Figure 15-7. Signal Conflict (RESET Pin)
µ PD78F9328
Signal Conflict
Connection pin of
dedicated flash
programmer
RESET
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the flash memory programming
mode, so isolate the signal of the reset signal generator.
<Port pins>
When the µPD78F9328 enters the flash memory programming mode, all the pins other than those that
communicate in flash memory programming are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS via a resistor.
<Oscillator>
When using the on-board clock, connect X1 and X2 as required in the normal operation mode.
When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main oscillator
on-board, and leave the X2 pin open.
<Power supply>
When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND
of the flash programmer, respectively.
When using the on-board power supply, connect it as required in the normal operation mode. Because the flash
programmer monitors the voltage, however, VDD of the flash programmer must be connected.
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CHAPTER 15 µPD78F9328
15.1.4 Connection on flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 15-8. Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode
VDD (2.7 to 5.5 V)
GND
1
52 51 50 49 48 47 46 45 44 43 42 41 40
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
27
13
14 15 16 17 18 19 20 21 21 23 24 25 26
GND
VDD
VDD2 (LVDD)
SI/RxD SO/TxD SCK
CLK
/RESET
VPP
RESERVE/HS
WRITER INTERFACE
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CHAPTER 16 MASK OPTIONS
The mask ROM versions (µPD789322, 789324, 789326, and 789327) have the following mask option.
• Oscillation stabilization wait time
The oscillation stabilization wait time after the release of STOP mode by RESET or POC can be selected.
<1> 215/fX
<2> 217/fX
Caution The oscillation stabilization wait time for the flash memory version (µPD78F9328) is fixed to 215/fX.
• Power-on-clear (POC) circuit
Use/non use of the POC circuit can be selected.
<1> POC circuit used
<2> POC circuit not used
Caution
186
The POC circuit of the flash memory version (µPD78F9328) is always used (always operating).
User’s Manual U15043EJ3V1UD
CHAPTER 17 INSTRUCTION SET
This chapter lists the instruction set of the µPD789327 Subseries. For the details of the operation and machine
language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E).
17.1 Operation
17.1.1 Operand identifiers and description methods
Operands are described in “Operands” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #:
Immediate data specification
• $:
Relative address specification
• !:
Absolute address specification
• [ ]:
Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in
parenthesis in the table below, R0, R1, R2, etc.) can be used for description.
Table 17-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
rp
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr
Special-function register symbol
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
addr5
0040H to 007FH Immediate data or labels (even addresses only)
word
16-bit immediate data or label
byte
8-bit immediate data or label
bit
3-bit immediate data or label
Remark
See Table 3-3 Special Function Registers for symbols of special function registers.
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CHAPTER 17 INSTRUCTION SET
17.1.2 Description of “Operation” column
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
AX register pair; 16-bit accumulator
BC:
BC register pair
DE:
DE register pair
HL:
HL register pair
PC:
Program counter
SP:
Stack pointer
PSW:
Program status word
CY:
Carry flag
AC:
Auxiliary carry flag
Z:
Zero flag
IE:
Interrupt request enable flag
NMIS:
Flag indicating non-maskable interrupt servicing in progress
( ):
Memory contents indicated by address or register contents in parenthesis
XH, XL:
∧:
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
∨:
Logical sum (OR)
V:
Exclusive logical sum (exclusive OR)
:
Inverted data
addr16:
16-bit immediate data or label
jdisp8:
Signed 8-bit data (displacement value)
17.1.3 Description of “Flag” column
(Blank):
Unchanged
0:
Cleared to 0
1:
Set to 1
x:
Set/cleared according to the result
R:
Previously saved value is restored
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CHAPTER 17 INSTRUCTION SET
17.2 Operation List
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
MOV
r, #byte
3
6
r ← byte
saddr, #byte
3
6
(saddr) ← byte
3
6
sfr ← byte
A, r
Note 1
2
4
A←r
r, A
Note 1
2
4
r←A
A, saddr
2
4
A ← (saddr)
saddr, A
2
4
(saddr) ← A
A, sfr
2
4
A ← sfr
sfr, A
2
4
sfr ← A
A, !addr16
3
8
A ← (addr16)
!addr16, A
3
8
(addr16) ← A
PSW, #byte
3
6
PSW ← byte
A, PSW
2
4
A ← PSW
PSW, A
2
4
PSW ← A
A, [DE]
1
6
A ← (DE)
[DE], A
1
6
(DE) ← A
A, [HL]
1
6
A ← (HL)
[HL], A
1
6
(HL) ← A
A, [HL+byte]
2
6
A ← (HL + byte)
[HL+byte], A
2
6
(HL + byte) ← A
A, X
1
4
A↔X
2
6
A↔r
A, saddr
2
6
A ↔ (saddr)
A, sfr
2
6
A ↔ sfr
A, [DE]
1
8
A ↔ (DE)
A, [HL]
1
8
A ↔ (HL)
A, [HL+byte]
2
8
A ↔ (HL + byte)
sfr, #byte
XCH
A, r
Note 2
x
x
x
x
x
x
Notes 1. Except r = A.
2. Except r = A, X.
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 17 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
MOVW
rp, #word
3
6
rp ← word
AX, saddrp
2
6
AX ← (saddrp)
2
8
(saddrp) ← AX
AX, rp
Note
1
4
AX ← rp
rp, AX
Note
1
4
rp ← AX
XCHW
AX, rp
Note
1
8
AX ↔ rp
ADD
A, #byte
2
4
A, CY ← A + byte
x
x
x
saddr, #byte
3
6
(saddr), CY ← (saddr) + byte
x
x
x
A, r
2
4
A, CY ← A + r
x
x
x
A, saddr
2
4
A, CY ← A + (saddr)
x
x
x
A, !addr16
3
8
A, CY ← A + (addr16)
x
x
x
A, [HL]
1
6
A, CY ← A + (HL)
x
x
x
A, [HL+byte]
2
6
A, CY ← A + (HL + byte)
x
x
x
A, #byte
2
4
A, CY ← A + byte + CY
x
x
x
saddr, #byte
3
6
(saddr), CY ← (saddr) + byte + CY
x
x
x
A, r
2
4
A, CY ← A + r + CY
x
x
x
A, saddr
2
4
A, CY ← A + (saddr) + CY
x
x
x
A, !addr16
3
8
A, CY ← A + (addr16) + CY
x
x
x
A, [HL]
1
6
A, CY ← A + (HL) + CY
x
x
x
A, [HL+byte]
2
6
A, CY ← A + (HL + byte) + CY
x
x
x
A, #byte
2
4
A, CY ← A − byte
x
x
x
saddr, #byte
3
6
(saddr), CY ← (saddr) − byte
x
x
x
A, r
2
4
A, CY ← A − r
x
x
x
A, saddr
2
4
A, CY ← A − (saddr)
x
x
x
A, !addr16
3
8
A, CY ← A − (addr16)
x
x
x
A, [HL]
1
6
A, CY ← A − (HL)
x
x
x
A, [HL+byte]
2
6
A, CY ← A − (HL + byte)
x
x
x
saddrp, AX
ADDC
SUB
Note Only when rp = BC, DE, or HL.
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 17 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
SUBC
AND
OR
XOR
Remark
A, #byte
2
4
A, CY ← A − byte − CY
x
x
x
saddr, #byte
3
6
(saddr), CY ← (saddr) − byte − CY
x
x
x
A, r
2
4
A, CY ← A − r − CY
x
x
x
A, saddr
2
4
A, CY ← A − (saddr) − CY
x
x
x
A, !addr16
3
8
A, CY ← A − (addr16) − CY
x
x
x
A, [HL]
1
6
A, CY ← A − (HL) − CY
x
x
x
A, [HL+byte]
2
6
A, CY ← A − (HL + byte) − CY
x
x
x
A, #byte
2
4
A ← A ∧ byte
x
saddr, #byte
3
6
(saddr) ← (saddr) ∧ byte
x
A, r
2
4
A←A∧r
x
A, saddr
2
4
A ← A ∧ (saddr)
x
A, !addr16
3
8
A ← A ∧ (addr16)
x
A, [HL]
1
6
A ← A ∧ (HL)
x
A, [HL+byte]
2
6
A ← A ∧ (HL + byte)
x
A, #byte
2
4
A ← A ∨ byte
x
saddr, #byte
3
6
(saddr) ← (saddr) ∨ byte
x
A, r
2
4
A←A∨r
x
A, saddr
2
4
A ← A ∨ (saddr)
x
A, !addr16
3
8
A ← A ∨ (addr16)
x
A, [HL]
1
6
A ← A ∨ (HL)
x
A, [HL+byte]
2
6
A ← A ∨ (HL + byte)
x
A, #byte
2
4
A ← A V byte
x
saddr, #byte
3
6
(saddr) ← (saddr) V byte
x
A, r
2
4
A←AVr
x
A, saddr
2
4
A ← A V (saddr)
x
A, !addr16
3
8
A ← A V (addr16)
x
A, [HL]
1
6
A ← A V (HL)
x
A, [HL+byte]
2
6
A ← A V (HL + byte)
x
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 17 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
A, #byte
2
4
A − byte
x
x
x
saddr, #byte
3
6
(saddr) − byte
x
x
x
A, r
2
4
A−r
x
x
x
A, saddr
2
4
A − (saddr)
x
x
x
A, !addr16
3
8
A − (addr16)
x
x
x
A, [HL]
1
6
A − (HL)
x
x
x
A, [HL+byte]
2
6
A − (HL + byte)
x
x
x
ADDW
AX, #word
3
6
AX, CY ← AX + word
x
x
x
SUBW
AX, #word
3
6
AX, CY ← AX − word
x
x
x
CMPW
AX, #word
3
6
AX − word
x
x
x
INC
r
2
4
r←r+1
x
x
saddr
2
4
(saddr) ← (saddr) + 1
x
x
r
2
4
r←r−1
x
x
saddr
2
4
(saddr) ← (saddr) − 1
x
x
INCW
rp
1
4
rp ← rp + 1
DECW
rp
1
4
rp ← rp − 1
ROR
A, 1
1
2
(CY, A7 ← A0, Am−1 ← Am) × 1
x
ROL
A, 1
1
2
(CY, A0 ← A7, Am+1 ← Am) × 1
x
RORC
A, 1
1
2
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
x
ROLC
A, 1
1
2
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
x
SET1
saddr.bit
3
6
(saddr.bit) ← 1
sfr.bit
3
6
sfr.bit ← 1
A.bit
2
4
A.bit ← 1
PSW.bit
3
6
PSW.bit ← 1
[HL].bit
2
10
(HL).bit ← 1
saddr.bit
3
6
(saddr.bit) ← 0
sfr.bit
3
6
sfr.bit ← 0
A.bit
2
4
A.bit ← 0
PSW.bit
3
6
PSW.bit ← 0
[HL].bit
2
10
(HL).bit ← 0
SET1
CY
1
2
CY ← 1
1
CLR1
CY
1
2
CY ← 0
0
NOT1
CY
1
2
CY ← CY
x
CMP
DEC
CLR1
Remark
x
x
x
x
x
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
192
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CHAPTER 17 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
CALL
!addr16
3
6
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
[addr5]
1
8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
6
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
1
8
PCH ← (SP + 1), PCL ← (SP),
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PSW
1
2
(SP − 1) ← PSW, SP ← SP − 1
rp
1
4
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW
1
4
PSW ← (SP), SP ← SP + 1
rp
1
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP, AX
2
8
SP ← AX
AX, SP
2
6
AX ← SP
!addr16
3
6
PC ← addr16
$addr16
2
6
PC ← PC + 2 + jdisp8
AX
1
6
PCH ← A, PCL ← X
BC
$saddr16
2
6
PC ← PC + 2 + jdisp8 if CY = 1
BNC
$saddr16
2
6
PC ← PC + 2 + jdisp8 if CY = 0
BZ
$saddr16
2
6
PC ← PC + 2 + jdisp8 if Z = 1
BNZ
$saddr16
2
6
PC ← PC + 2 + jdisp8 if Z = 0
BT
saddr.bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
8
PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if PSW.bit = 1
saddr.bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
8
PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B, $addr16
2
6
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
3
8
(saddr) ← (saddr) − 1, then
PUSH
POP
MOVW
BR
BF
DBNZ
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
1
2
No Operation
EI
3
6
IE ← 1 (Enable interrupt)
DI
3
6
IE ← 0 (Disable interrupt)
HALT
1
2
Set HALT mode
STOP
1
2
Set STOP mode
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 17 INSTRUCTION SET
17.3 Instructions Listed by Addressing Type
(1)
8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
#byte
A
r
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL+byte]
r
1
None
6
1st Operand
A
$addr1
ADD
MOV
Note
MOV
MOV
ADDC
XCHNote
XCH
XCH
SUB
ADD
ADD
SUBC
ADDC
AND
MOV
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
ADD
RORC
ADDC
ADDC
ADDC
ADDC
ROLC
SUB
SUB
SUB
SUB
SUB
OR
SUBC
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
MOV
MOV
INC
DEC
B, C
sfr
saddr
DBNZ
MOV
MOV
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
[HL+byte]
MOV
Note Except r = A.
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CHAPTER 17 INSTRUCTION SET
(2)
16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rp
Note
saddrp
SP
None
1st Operand
AX
ADDW
MOVW
SUBW
XCHW
MOVW
MOVW
CMPW
rp
MOVW
MOVW
Note
INCW
DECW
PUSH
POP
saddrp
MOVW
SP
MOVW
Note Only when rp = BC, DE, or HL.
(3)
Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
$addr16
None
1st Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
BT
SET1
BF
CLR1
BT
SET1
BF
CLR1
BT
SET1
BF
CLR1
BT
SET1
BF
CLR1
SET1
CLR1
CY
SET1
CLR1
NOT1
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CHAPTER 17 INSTRUCTION SET
(4)
Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
AX
!addr16
[addr5]
$addr16
1st Operand
Basic Instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound Instructions
(5)
DBNZ
Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Supply voltage
Conditions
VDD
VLC0
VPP
Input voltage
Note 1
µPD78F9328 only
VO1
Unit
−0.3 to +6.5
V
−0.3 to +6.5
V
−0.3 to +10.5
Note 2
−0.3 to VDD + 0.3
VI
Output voltage
Ratings
Note 2
−0.3 to VDD + 0.3
P00 to P03, P10, P11, P20 to P22,
V
V
V
P40 to P43, P60, P61
VO2
Note 2
−0.3 to VLC0 + 0.3
COM0 to COM3, S0 to S16,
V
P80/S22 to P85/S17, S23
Output current, high
IOH
Output current, low
IOL
Operating ambient temperature
Storage temperature
TA
Tstg
Pin P60/TO40
−30
mA
Per pin (except P60/TO40)
−10
mA
Total for all pins (except P60/TO40)
−30
mA
Per pin
30
mA
Total for all pins
80
mA
During normal operation
−40 to +85
°C
During flash memory programming
10 to 40
°C
Mask ROM version
−65 to +150
°C
Flash memory version
−40 to +125
°C
Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (a in the figure below).
• When supply voltage falls
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the range of
VDD (b in the figure below).
VDD
1.8 V
0V
a
b
VPP
1.8 V
0V
2. 6.5 V or less
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Main System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
Recommended Circuit
X2
X1
resonator
C2
Crystal
X2
External
clock
X1
Conditions
Oscillation frequency
Note 1
(fX)
MIN.
1.0
Oscillation
After VDD has reached the
Note 2
stabilization time
oscillation voltage range MIN.
C1
X1
resonator
C2
Parameter
Oscillation
Note 1
frequency
1.0
4.5 ≤ VDD ≤ 5.5 V
Oscillation
Note 2
stabilization time
1.8 ≤ VDD ≤ 5.5 V
C1
X2
TYP.
MAX.
Unit
5.0
MHz
4
ms
5.0
MHz
10
ms
30
ms
X1 input frequency
Note 1
(fX)
1.0
5.0
MHz
X1 input high-/low-
85
500
ns
level width (tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator to stabilize
oscillation within the oscillation wait time.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
Recommended Oscillation Circuit Constants
Ceramic oscillator (TA = −40 to +85°C) (mask ROM version)
Manufacturer
Part Number
Frequency
(MHz)
Murata Mfg.
(standard
Note
CSBLA1M00J58-B0
CSBFB1M00J58-R1
Recommended Circuit
Oscillation Voltage
Constant (pF)
Range (VDD)
C1
C2
MIN.
MAX.
1.0
100
100
1.9
5.5
2.0
−
−
Remark
Rd = 1.5 kΩ
Note
product)
CSTCC2M00G56-R0
With internal
capacitor
CSTLS2M00G56-B0
4.0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
4.194
CSTCR4M19G53-R0
CSTLS4M19G53-B0
1.8
5.5
1.9
5.5
1.8
5.5
1.9
5.5
1.8
5.5
4.915
CSTCR4M91G53-R0
CSTLS4M91G53-B0
CSTCR5M00G53-R0
5.0
CSTLS5M00G53-B0
Murata Mfg.
(low-voltage
CSTLS4M00G53093-B0
4.0
CSTLS4M19G53093-B0
4.194
CSTCR4M91G53093-R0
4.915
−
−
With internal
capacitor
drive type)
CSTLS4M91G53093-B0
CSTCR5M00G53093-R0
5.0
CSTLS5M00G53093-B0
TDK
FCR4.0MC5
4.0
FCR5.0MC5
−
−
2.2
5.5
With internal
capacitor
5.0
Note When using the CSBLA1M00J58-B0 or CSBFB1M00J58-R1 (1.0 MHz) of Murata Mfg. as the ceramic
oscillator, a limiting resistor (Rd = 1.5 kΩ) is necessary (refer to the figure below). The limiting resistor is not
necessary when other recommended oscillators are used.
X1
X2
CSBLA1M00J58-B0
CSBFB1M00J58-R1
C1
Caution
Rd
C2
The oscillator constant is a reference value based on evaluation under a specific environment by
the resonator manufacturer.
If optimization of oscillator characteristics is necessary in the actual application, apply to the
resonator manufacturer for evaluation on the implementation circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µPD78932x so that the internal operating conditions are within the specifications of the DC and
AC characteristics.
User’s Manual U15043EJ3V1UD
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
Ceramic oscillator (TA = −40 to +85°C) (flash memory version)
Manufacturer
Part Number
Frequency
(MHz)
Murata Mfg.
(standard
product)
Note
Recommended Circuit
Oscillation Voltage
Constant (pF)
Range (VDD)
C1
C2
MIN.
MAX.
CSBLA1M00J58-B0
1.0
100
100
2.1
5.5
CSTCC2M00G56-R0
2.0
−
−
1.8
5.5
Rd = 3.3 kΩ
With internal
capacitor
4.0
CSTCR4M00G53-R0
Remark
CSTLS4M00G53-B0
4.194
CSTCR4M19G53-R0
CSTLS4M19G53-B0
4.915
CSTCR4M91G53-R0
CSTLS4M91G53-B0
CSTCR5M00G53-R0
5.0
CSTLS5M00G53-B0
TDK
FCR4.0MC5
Kyocera
4.0
FCR5.0MC5
5.0
PBRC4.00HR
4.0
PBRC4.19HR
4.19
PBRC4.91HR
4.91
PBRC5.00HR
5.0
−
−
2.2
5.5
With internal
capacitor
−
−
1.8
5.5
With internal
capacitor
Note When using the CSBLA1M00J58-B0 of Murata Mfg. as the ceramic oscillator, a limiting resistor (Rd = 3.3
kΩ) is necessary (refer to the figure below). The limiting resistor is not necessary when other recommended
oscillators are used.
X1
X2
CSBLA1M00J58-B0
C1
Caution
Rd
C2
The oscillator constant is a reference value based on evaluation under a specific environment by
the resonator manufacturer.
If optimization of oscillator characteristics is necessary in the actual application, apply to the
resonator manufacturer for evaluation on the implementation circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µPD78F9328 so that the internal operating conditions are within the specifications of the DC and
AC characteristics.
200
User’s Manual U15043EJ3V1UD
CHAPTER 18 ELECTRICAL SPECIFICATIONS
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
Recommended Circuit
XT1
resonator
C3
External
XT2
R
XT1
C4
XT2
clock
Parameter
Conditions
Oscillation frequency
Note 1
(fXT)
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
10
s
4.5 ≤ VDD ≤ 5.5 V
Oscillation
Note 2
stabilization time
1.8 ≤ VDD ≤ 5.5 V
XT1 input frequency
Note 1
(fXT)
32
35
kHz
XT1 input high-/low-
14.3
15.6
µs
level width (tXTH, tXTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a
resonator to stabilize oscillation during the oscillation wait time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
User’s Manual U15043EJ3V1UD
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Output current, low
Output current, high
Symbol
IOL
IOH
Conditions
MAX.
Unit
Per pin
10
mA
Total for all pins
80
mA
Per pin (except P60/TO40)
−1
mA
−24
mA
−15
mA
P60/TO40
VDD = 3.0 V, VOH = 2.0 V
MIN.
−7
Total for all pins (except P60/TO40)
Input voltage, high
VIH1
VIH2
Input voltage, low
−15
P00 to P03, P10, P11,
2.7 ≤ VDD ≤ 5.5 V
0.7VDD
VDD
V
P60, P80 to P85
1.8 ≤ VDD ≤ 5.5 V
0.9VDD
VDD
V
RESET, P20 to P22, P40 to
2.7 ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
P43, P61
1.8 ≤ VDD ≤ 5.5 V
0.9VDD
VDD
V
VIH3
X1, X2
VDD − 0.1
VDD
V
VIH4
XT1, XT2
VDD − 0.1
VDD
V
VIL1
P00 to P03, P10, P11,
2.7 ≤ VDD ≤ 5.5 V
0
0.3VDD
V
P60, P80 to P85
1.8 ≤ VDD ≤ 5.5 V
0
0.1VDD
V
RESET, P20 to P22, P40
2.7 ≤ VDD ≤ 5.5 V
0
0.2VDD
V
to P43, P61
1.8 ≤ VDD ≤ 5.5 V
0
0.1VDD
V
VIL2
Output voltage, high
TYP.
VIL3
X1, X2
0
0.1
V
VIL4
XT1, XT2
0
0.1
V
VOH11
P00 to P03, P10, P11,
1.8 ≤ VDD ≤ 5.5 V,
P20 to P22, P40 to P43,
IOH = −100 µA
P61
1.8 ≤ VDD ≤ 5.5 V,
VOH12
VDD − 0.5
V
VDD − 0.7
V
VDD − 0.5
V
VDD − 0.7
V
VLC0 − 0.5
V
VLC0 − 0.7
V
IOH = −500 µA
VOH21
1.8 ≤ VDD ≤ 5.5 V,
P60/TO40
IOH = −400 µA
1.8 ≤ VDD ≤ 5.5 V,
VOH22
IOH = −2 mA
VOH31
P80/S22 to P85/S17
1.8 ≤ VDD ≤ 5.5 V,
IOH = −100 µA
1.8 ≤ VDD ≤ 5.5 V,
VOH32
IOH = −500 µA
Output voltage, low
VOL11
VOL12
P00 to P03, P10, P11,
1.8 ≤ VDD ≤ 5.5 V,
P20 to P22, P40 to P43,
IOL = 400 µA
P60, P61
1.8 ≤ VDD ≤ 5.5 V,
0.5
V
0.7
V
0.5
V
0.7
V
IOL = 2 mA
VOL21
P80/S22 to P85/S17
1.8 ≤ VLC0 ≤ 5.5 V,
IOL = 400 µA
VOL22
1.8 ≤ VLC0 ≤ 5.5 V,
IOL = 2 mA
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
202
User’s Manual U15043EJ3V1UD
CHAPTER 18 ELECTRICAL SPECIFICATIONS
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Input leakage current,
ILIH1
Conditions
VIN = VDD
MIN.
TYP.
MAX.
Unit
3
µA
X1, X2, XT1, XT2
20
µA
P00 to P03, P10,
−3
µA
−20
µA
100
200
kΩ
5.0
15.0
mA
VDD = 3.3 V
2.0
5.0
mA
VDD = 5.5 V
1.2
3.6
mA
VDD = 3.3 V
0.5
1.5
mA
VDD = 5.5 V
25
70
µA
VDD = 3.3 V
10
35
µA
VDD = 5.5 V
2
20
µA
VDD = 3.3 V
1
10
µA
1.5
3.0
mA
VDD = 3.3 V
0.6
1.2
mA
VDD = 5.5 V
0.8
2.0
mA
VDD = 3.3 V
0.4
0.8
mA
VDD = 5.5 V
25
50
µA
VDD = 3.3 V
7
25
µA
VDD = 5.5 V
2
20
µA
VDD = 3.3 V
1
10
µA
VDD = 5.5 V
0.1
10
µA
VDD = 3.3 V
0.05
5
µA
P00 to P03, P10,
high
P11, P20 to P22, P40
to P43, P60, P61,
RESET, P80 to P85
ILIH2
Input leakage current,
ILIL1
VIN = 0 V
low
P11, P20 to P22, P40
to P43, P60, P61,
RESET, P80 to P85
X1, X2, XT1, XT2
ILIL2
Software pull-up
R1
VIN = 0 V
P00 to P03, P10,
resistors
50
P11, P20 to P22, P40
to P43
Note 1
Supply current
(µPD78F9328)
IDD1
5.0 MHz crystal oscillation
operating mode
IDD2
5.0 MHz crystal oscillation
HALT mode
IDD3
IDD4
32.768 kHz crystal
Note 4
oscillation HALT mode
32.768 kHz crystal oscillation
stopped STOP mode
Supply current
Note 1
IDD1
(Mask ROM product)
5.0 MHz crystal oscillation
operating mode
IDD2
5.0 MHz crystal oscillation
HALT mode
IDD3
IDD4
32.768 kHz crystal
Note 4
oscillation HALT mode
32.768 kHz crystal oscillation
stopped STOP mode
Note 2
VDD = 5.5 V
Note 3
Note 2
VDD = 5.5 V
Note 3
(POC circuit used)
IDD5
32.768 kHz crystal oscillation
stopped STOP mode
(POC circuit not used)
Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors and from VLC0
to VSS) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
3. Low-speed mode operation (when PCC is set to 02H)
4. When the main system clock operation is stopped.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
User’s Manual U15043EJ3V1UD
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Cycle time
TCY
(Min. instruction execution time)
Interrupt input
tINTH,
high-/low-level width
tINTL
Key return pin
tKRIL
Conditions
MIN.
TYP.
MAX.
Unit
2.7 ≤ VDD ≤ 5.5 V
0.4
8.0
µs
1.8 ≤ VDD ≤ 5.5 V
1.6
8.0
µs
INT
10
µs
KR00 to KR03
10
µs
10
µs
low-level width
RESET low-level width
tRSL
TCY vs. VDD (Main System Clock)
60
20
Cycle time TCY [ µ s]
10
Guaranteed
operation
range
2.0
1.0
0.5
0.4
0.1
1
2
3
4
5
Supply voltage VDD (V)
204
User’s Manual U15043EJ3V1UD
6
CHAPTER 18 ELECTRICAL SPECIFICATIONS
(2)
Serial Interface 10 (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (internal clock output)
Parameter
SCK10 cycle time
SCK10 high/low-level width
Symbol
tKCY1
tKH1,
tKL1
SI10 setup time (to SCK10↑)
SI10 hold time (from SCK10↑)
Delay time from SCK10↓ to
tSIK1
tKSI1
tKSO1
Conditions
MIN.
TYP.
MAX.
Unit
VDD = 2.7 to 5.5 V
800
ns
VDD = 1.8 to 5.5 V
3200
ns
VDD = 2.7 to 5.5 V
tKCY1/2-50
ns
VDD = 1.8 to 5.5 V
tKCY1/2-150
ns
VDD = 2.7 to 5.5 V
150
ns
VDD = 1.8 to 5.5 V
500
ns
VDD = 2.7 to 5.5 V
400
ns
VDD = 1.8 to 5.5 V
800
ns
R = 1 kΩ,
VDD = 2.7 to 5.5 V
0
250
ns
VDD = 1.8 to 5.5 V
250
1000
ns
MAX.
Unit
Note
C = 100 pF
SO10 output
Note R and C are the load resistance and load capacitance of the SO10 output line.
(a) 3-wire serial I/O mode (external clock input)
Parameter
SCK10 cycle time
SCK10 high/low-level width
Symbol
tKCY2
tKH2,
tKL2
SI10 setup time (to SCK10↑)
SI10 hold time (from SCK10↑)
Delay time from SCK10↓ to
SO10 output
tSIK2
tKSI2
tKSO2
Conditions
MIN.
TYP.
VDD = 2.7 to 5.5 V
800
ns
VDD = 1.8 to 5.5 V
3200
ns
VDD = 2.7 to 5.5 V
400
ns
VDD = 1.8 to 5.5 V
1600
ns
VDD = 2.7 to 5.5 V
100
ns
VDD = 1.8 to 5.5 V
150
ns
VDD = 2.7 to 5.5 V
400
ns
VDD = 1.8 to 5.5 V
600
ns
R = 1 kΩ,
VDD = 2.7 to 5.5 V
0
300
ns
VDD = 1.8 to 5.5 V
250
1000
ns
Note
C = 100 pF
Note R and C are the load resistance and load capacitance of the SO10 output line.
User’s Manual U15043EJ3V1UD
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CHAPTER 18 ELECTRICAL SPECIFICATIONS
AC Timing Measurement Points (Excluding X1, XT1 Input)
0.8VDD
0.8VDD
Point of measurement
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VIH3 (MIN.)
X1 input
VIL3 (MAX.)
1/fXT
tXTL
tXTH
VIH4 (MIN.)
XT1 input
VIL4 (MAX.)
Interrupt Input Timing
tINTL
tINTH
INT
Key Return Input Timing
tKRIL
KR00 to KR03
RESET Input Timing
tRSL
RESET
206
User’s Manual U15043EJ3V1UD
CHAPTER 18 ELECTRICAL SPECIFICATIONS
Serial Transfer Timing
3-wire serial I/O mode:
tKCYn
tKLn
tKHn
SCK10
tSIKn
SI10
tKSIn
Input data
tKSOn
SO10
Output data
Remark n = 1, 2
User’s Manual U15043EJ3V1UD
207
CHAPTER 18 ELECTRICAL SPECIFICATIONS
LCD Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V, VLC0 = 1.8 to 5.5 V)
Parameter
LCD drive voltage
Symbol
VLCD
Conditions
MIN.
VAON0
Note 1
=1
VAON0
Note 1
=0
MAX.
Unit
1.8
VLC0
V
2.7
VLC0
V
200
kΩ
LCD division resistor
RLCD
LCD output voltage
VODC
IO = ±5 µA
1/3 bias
0
±0.2
V
VODS
IO = ±1 µA
1/3 bias
0
±0.2
V
differential
Note 2
Note 2
100
(common)
LCD output voltage
differential
50
TYP.
(segment)
Notes 1. Bit 6 of LCD display mode register 0 (LCDM0).
2. The voltage differential is the difference between the output voltage and the ideal value of the segment
and common signal outputs.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Data retention supply voltage
VDDDR
Low voltage detection (POC)
Conditions
MIN.
TYP.
1.8
Note 1
1.9
MAX.
Unit
5.5
V
2.0
V
100
ms
VPOC
Response time: 2 ms
1.8
Supply voltage rise time
tPth
VDD : 0 V → 1.8 V
0.01
Release signal set time
tSREL
STOP released by RESET
10
Oscillation stabilization wait
tWAIT
Canceled by RESET pin or POC
Note 3
s
Canceled by interrupt request
Note 4
s
voltage
time
µs
Note 2
Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the
time until operation stabilizes after the shift from the operation stopped state to the operating state.
2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid
unstable operation at the start of oscillation. Program operation does not start until both the oscillation
stabilization time and the time until oscillation starts have elapsed.
3. µPD78F9328 is fixed to 215/fX. In mask ROM versions, 215/fX or 217/fX is selected by a mask option (refer
to CHAPTER 16 MASK OPTIONS).
4. Selection of 212/fX, 215/fX, and 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS) (refer to 13.2 Register Controlling Standby Function).
Remark fX: Main system clock oscillation frequency
208
User’s Manual U15043EJ3V1UD
CHAPTER 18 ELECTRICAL SPECIFICATIONS
Data Retention Timing
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
tSREL
VDDDR
STOP instruction execution
RESET
tWAIT
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
tSREL
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
Writing and Erasing Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter
Write operation frequency
Symbol
fX
Conditions
MIN.
TYP.
MAX.
Unit
VDD = 2.7 to 5.5 V
1.0
5
MHz
VDD = 1.8 to 5.5 V
1.0
1.25
MHz
Note
IDDW
When VPP supply voltage = VPP1
(at 5.0 MHz operation)
7
mA
Note
Write current (VDD pin)
Write current (VPP pin)
IPPW
When VPP supply voltage = VPP1
13
mA
Note
IDDE
When VPP supply voltage = VPP1
(at 5.0 MHz operation)
7
mA
Erase current (VPP pin)
Note
IPPE
When VPP supply voltage = VPP1
100
mA
Unit erase time
ter
1
s
Total erase time
tera
Erase current (VDD pin)
Number of overwrites
VPP supply voltage
0.5
1
Erase and write is considered as 1
cycle
VPP0
VPP1
Normal operation
0
Flash memory programming
9.7
10.0
20
s
20
Times
0.2VDD
V
10.3
V
Note Excludes current flowing through ports (including on-chip pull-up resistors)
User’s Manual U15043EJ3V1UD
209
CHAPTER 19 PACKAGE DRAWING
52-PIN PLASTIC LQFP (10x10)
A
B
detail of lead end
27
26
39
40
S
P
C
T
D
R
52
1
L
14
13
U
Q
F
J
G
I
H
M
K
M
N
S
S
ITEM
A
MILLIMETERS
12.0±0.2
B
10.0±0.2
C
10.0±0.2
D
12.0±0.2
F
1.1
G
1.1
H
I
0.32±0.06
0.13
J
0.65 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.05
N
0.10
P
1.4
Q
0.1±0.05
R
3° +4°
−3°
S
1.5±0.1
T
U
0.25
0.6±0.15
S52GB-65-8ET-2
210
User’s Manual U15043EJ3V1UD
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS
The µPD789322, 789324, 789326, 789327, and 78F9328 should be soldered and mounted under the following
recommended conditions.
For soldering methods and conditions other than those recommended below, please contact an NEC Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 20-1. Surface Mounting Type Soldering Conditions (1/2)
µPD789322GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
higher), Count: Twice or less
IR35-00-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
higher), Count: Twice or less
VP15-00-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count:
Once, Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)
Caution
Do not use different soldering methods together (except for partial heating).
—
µPD789324GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
µPD789326GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
µPD789327GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
Note
higher), Count: Twice or less, Exposure limit: 3 days (after that, prebake at
125°C for 10 hours)
IR35-103-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
Note
higher), Count: Twice or less, Exposure limit: 3 days (after that, prebake at
125°C for 10 hours)
VP15-103-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count:
Once, Preheating temperature: 120°C max. (package surface temperature),
Note
Exposure limit: 3 days (after that, prebake at 125°C for 10 hours)
WS60-103-1
Partial heating
Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)
—
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
User’s Manual U15043EJ3V1UD
211
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS
Table 20-1. Surface Mounting Type Soldering Conditions (2/2)
µPD78F9328GB-8ET: 52-pin plastic LQFP (10 × 10)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
Note
higher), Count: Twice or less, Exposure limit: 7 days (after that, prebake at
125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
Note
higher), Count: Twice or less, Exposure limit: 7 days (after that, prebake at
125°C for 10 hours)
VP15-107-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count:
Once, Preheating temperature: 120°C max. (package surface temperature),
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating
Pin temperature: 350°C max. Time: 3 seconds max. (per pin row)
—
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
µPD789322GB-×××-8ET-A:
µPD789324GB-×××-8ET-A:
µPD789326GB-×××-8ET-A:
µPD789327GB-×××-8ET-A:
µPD78F9328GB-8ET-A:
Soldering Method
52-pin plastic LQFP (10 × 10)
52-pin plastic LQFP (10 × 10)
52-pin plastic LQFP (10 × 10)
52-pin plastic LQFP (10 × 10)
52-pin plastic LQFP (10 × 10)
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or
Note
higher), Count: Three times or less, Exposure limit: 7 days (after that,
prebake at 125°C for 20 to 72 hours)
Wave soldering
For details, contact an NEC Electronics sales representative.
−
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
IR60-207-3
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
212
Caution
Do not use different soldering methods together (except for partial heating).
Remark
Products that have the part numbers suffixed by "-A" are lead-free products.
User’s Manual U15043EJ3V1UD
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD789327 Subseries.
Figure A-1 shows development tools.
• Support of PC98-NX series
Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX
series. When using the PC98-NX Series, refer to the explanation of IBM PC/AT compatibles.
• Windows™
Unless specified otherwise, "Windows" indicates the following operating systems.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NT™ Ver.4.0
• Windows XP
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Software package
• Software package
Language processing software
Software for debugging
• Assembler package
• C compiler package
• Device file
• C library source fileNote 1
• Integrated debugger
• System simulator
Control software
• Project manager
(Windows version only)Note 2
Host machine
(PC or EWS)
Interface adapter
Power supply unit
Flash memory writing tools
In-circuit emulator
Flash programmer
Emulation board
Flash memory
writing adapter
Flash memory
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. The C library source file is not included in the software package.
2. The project manager is included in the assembler package. The project manager is used only for
Windows.
214
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S Software package
Various software tools for 78K/0S Series development are integrated into one package.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files
Part number: µS××××SP78K0S
Remark
×××× in the part number differs depending on the operating system to be used.
µS××××SP78K0S
××××
AB17
BB17
Host Machine
PC-9800 series, IBM PC/AT
compatibles
OS
Japanese Windows
Supply Medium
CD-ROM
English Windows
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object codes that can be executed
Assembler package
by microcontroller.
In addition, automatic functions to generate symbol tables and optimize branch instructions
are also provided.
Used in combination with a device file (DF789328) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed
C compiler package
by microcontroller.
Used in combination with an assembler package (RA78K0S) and device file (DF789328)
(both sold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789328
Note1
Device file
File containing the information specific to the device.
Used in combination with the RA78K0S, CC78K0S, and SM78K0S (sold separately).
Part number: µS××××DF789328
CC78K0S-L
Note2
C library source file
Source file of functions for generating object library included in C compiler package.
Necessary for changing object library included in C compiler package according to
customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
Part number: µS××××CC78K0S-L
Notes 1. DF789328 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
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APPENDIX A DEVELOPMENT TOOLS
Remark
×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
BB13
Host Machine
PC-9800 series, IBM PC/AT
compatibles
OS
Japanese Windows
Supply Medium
3.5” 2HD FD
English Windows
AB17
Japanese Windows
BB17
English Windows
3P17
HP9000 series 700™
HP-UX™ (Rel.10.10)
3K17
SPARCstation™
SunOS™ (Rel.4.1.4),
CD-ROM
Solaris™ (Rel.2.5.1)
µS××××DF789328
µS××××CC78K0S-L
××××
AB13
BB13
Host Machine
PC-9800 series, IBM PC/AT
compatibles
OS
Japanese Windows
Supply Medium
3.5” 2HD FD
English Windows
3P16
HP9000 series 700
HP-UX (Rel.10.10)
DAT
3K13
SPARCstation
SunOS (Rel.4.1.4),
3.5” 2HD FD
Solaris (Rel.2.5.1)
3K15
1/4” CGMT
A.3 Control Software
Project manager
Control software designed so that the user program can be efficiently developed in the
Windows environment. A series of jobs for user program development including starting the
editor, building, and starting the debugger, can be executed on the project manager.
<Caution>
The project manager is included in the assembler package (RA78K0S). It cannot be used in
an environment other than Windows.
216
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APPENDIX A DEVELOPMENT TOOLS
A.4 Flash Memory Writing Tools
Flashpro III
Dedicated flash programmer for microcontrollers incorporating flash memory
(Part No. FL-PR3, PG-FP3)
Flashpro IV
(Part No. FL-PR4, PG-FP4)
Flash programmer
FA-52GB-8ET
Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV.
Flash memory writing adapter
FA-52GB-8ET: for 52-pin plastic LQFP (GB-8ET type)
Remark
The FL-PR3, The FL-PR4, and FA-52GB-8ET are products made by Naito Densei Machida Mfg. Co.,
Ltd. (TEL +81-45-475-4191).
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator for debugging hardware and software of application system using 78K/0S
In-circuit emulator
Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter,
emulation probe, and interface adapter for connecting the host machine.
IE-78K0S-NS-A
A coverage function has been added to the IE-78K0S-NS function and the debug function has
In-circuit emulator
been further enhanced, enhancing the tracer and timer functions.
IE-70000-MC-PS-B
Adapter for supplying power from AC 100 to 240 V outlet.
AC adapter
IE-70000-98-IF-C
Adapter necessary when using PC-9800 series PC (except notebook type) as host machine
Interface adapter
(C bus supported)
IE-70000-CD-IF-A
PC card and interface cable necessary when using notebook PC as host machine (PCMCIA
PC card interface
socket supported)
IE-70000-PC-IF-C
Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus
Interface adapter
supported)
IE-70000-PCI-IF-A
Adapter necessary when using personal computer incorporating PCI bus as host machine
Interface adapter
IE-789468-NS-EM1
Board for emulating peripheral hardware specific to device. Used in combination with in-circuit
Emulation board
emulator.
NP-H52GB-TQ
Probe for connecting in-circuit emulator and target system.
Emulation probe
Used in combination with TGB-052SBP.
TGB-052SBP
Conversion adapter to connect NP-H52GB-TQ and target system board on which 52-pin plastic
Conversion
LQFP (GB-8ET type) can be mounted
adapter
Remarks 1. The NP-H52GB-TQ is a product made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-4754191).
2. The TGB-052SBP is a product made by TOKYO ELETECH CORPORATION.
For further information, contact:
Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
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APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
A debugger supporting in-circuit emulators for the 78K/0S Series: IE-78K0S-NS and IE-
Integrated debugger
78K0S-NS-A. The ID78K0S-NS is Windows-based software.
This program enhances the debugging functions for C language. Therefore, it can display
the trace results corresponding to the source program by using the window integration
function that links the source program, disassembled display, and memory display with the
trace results.
Use this program in combination with a device file (DF789328) (sold separately).
Part number: µS××××ID78K0S-NS
SM78K0S
A system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
System simulator
C-source-level or assembler level debugging is possible while simulating the operation of the
target system on the host machine. Using the SM78K0S enables logical and performance
verification of an application independently of the hardware development. This enhances
development efficiency and improves software quality.
Use this program in combination with a device file (DF789328) (sold separately).
Part number: µS××××SM78K0S
DF789328
Note
File containing information specific to the device.
Device file
Use this file in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (sold
separately).
Part number: µS××××DF789328
Note DF789328 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark
×××× in the part number differs depending on the operating system to be used and the supply medium.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
BB13
218
Host Machine
PC-9800 series, IBM PC/AT
compatibles
OS
Japanese Windows
Supply Medium
3.5” 2HD FD
English Windows
AB17
Japanese Windows
BB17
English Windows
User’s Manual U15043EJ3V1UD
CD-ROM
APPENDIX A DEVELOPMENT TOOLS
A.7 Cautions when designing target system
The following shows the conditions when connecting the emulation probe to the conversion adapter. Design the
system considering shapes and other conditions of the components to be mounted on the target system and be sure
to follow the configuration below.
Figure A-2. Condition Diagram of Connection to Target System
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789468-NS-EM1
When CN1 is connected: 370 mm
CN1
CN2
Emulation probe
NP-H52GB-TQ
Conversion adapter: TGB-052SBP
Connect to CN1 if
µ PD789327 Subseries is used.
Emulation probe
NP-H52GB-TQ
Emulation board
IE-789468-NS-EM1
10 mm
43 mm
45 mm
11 mm
23 mm
Conversion adapter: TGB-052SBP
14.45 mm
14.45 mm
No.1 pin
45 mm
53 mm
Target system
User’s Manual U15043EJ3V1UD
219
APPENDIX B REGISTER INDEX
B.1 Register Index (Alphabetic Order of Register Name)
[C]
Carrier generator output control register 40 (TCA40) .............................................................................................95
[E]
8-bit compare register 30 (CR30) ...........................................................................................................................90
8-bit compare register 40 (CR40) ...........................................................................................................................90
8-bit H width compare register 40 (CRH40)............................................................................................................90
8-bit timer counter 30 (TM30) .................................................................................................................................91
8-bit timer counter 40 (TM40) .................................................................................................................................91
8-bit timer mode control register 30 (TMC30) .........................................................................................................93
8-bit timer mode control register 40 (TMC40) .........................................................................................................94
External interrupt mode register 0 (INTM0) ..........................................................................................................158
[I]
Interrupt mask flag register 0 (MK0) .....................................................................................................................157
Interrupt request flag register 0 (IF0) ....................................................................................................................157
[K]
Key return mode register 00 (KRM00)..................................................................................................................159
[L]
LCD clock control register 0 (LCDC0) ..................................................................................................................138
LCD display mode register 0 (LCDM0).................................................................................................................136
[O]
Oscillation stabilization time selection register (OSTS) ........................................................................................167
[P]
Port 0 (P0) ..............................................................................................................................................................61
Port 1 (P1) ..............................................................................................................................................................62
Port 2 (P2) ..............................................................................................................................................................63
Port 4 (P4) ..............................................................................................................................................................66
Port 6 (P6) ..............................................................................................................................................................67
Port 8 (P8) ..............................................................................................................................................................69
Port function register 8 (PF8) ......................................................................................................................... 72, 139
Port mode register 0 (PM0) ....................................................................................................................................70
Port mode register 1 (PM1) ....................................................................................................................................70
Port mode register 2 (PM2) ............................................................................................................................ 70, 130
Port mode register 4 (PM4) ....................................................................................................................................70
Port mode register 6 (PM6) .............................................................................................................................. 70, 96
Port mode register 8 (PM8) ....................................................................................................................................70
Power-on-clear register 1 (POCF1) ......................................................................................................................152
220
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APPENDIX B REGISTER INDEX
Processor clock control register (PCC) .................................................................................................................. 77
Pull-up resistor option register 0 (PU0) .................................................................................................................. 71
Pull-up resistor option register B2 (PUB2).............................................................................................................. 72
[S]
Serial operation mode register 10 (CSIM10) ........................................................................................................ 129
Subclock control register (CSS) ............................................................................................................................. 78
Suboscillation mode register (SCKM)..................................................................................................................... 78
[T]
Transmit/receive shift register 10 (SIO10)............................................................................................................ 127
[W]
Watchdog timer clock selection register (TCL2) ................................................................................................... 122
Watchdog timer mode register (WDTM)............................................................................................................... 123
Watch timer mode control register (WTM)............................................................................................................ 117
User’s Manual U15043EJ3V1UD
221
APPENDIX B REGISTER INDEX
B.2 Register Index (Alphabetic Order of Register Symbol)
[C]
CR30:
8-bit compare register 30.......................................................................................................................90
CR40:
8-bit compare register 40.......................................................................................................................90
CRH40:
8-bit H width compare register 40 ..........................................................................................................90
CSIM10: Serial operation mode register 10........................................................................................................129
CSS:
Subclock control register .......................................................................................................................78
[I]
IF0:
Interrupt request flag register 0............................................................................................................157
INTM0:
External interrupt mode register 0 .......................................................................................................158
[K]
KRM00:
Key return mode register 00 ................................................................................................................159
[L]
LCDC0:
LCD clock control register 0.................................................................................................................138
LCDM0:
LCD display mode register 0 ...............................................................................................................136
[M]
MK0:
Interrupt mask flag register 0 ...............................................................................................................157
[O]
OSTS:
Oscillation stabilization time selection register.....................................................................................167
[P]
P0:
Port 0.....................................................................................................................................................61
P1:
Port 1.....................................................................................................................................................62
P2:
Port 2.....................................................................................................................................................63
P4:
Port 4.....................................................................................................................................................66
P6:
Port 6.....................................................................................................................................................67
P8:
Port 8.....................................................................................................................................................69
PCC:
Processor clock control register.............................................................................................................77
PF8:
Port function register 8................................................................................................................... 72, 139
PM0:
Port mode register 0 ..............................................................................................................................70
PM1:
Port mode register 1 ..............................................................................................................................70
PM2:
Port mode register 2 ...................................................................................................................... 70, 130
PM4:
Port mode register 4 ..............................................................................................................................70
PM6:
Port mode register 6 ........................................................................................................................ 70, 96
PM8:
Port mode register 8 ..............................................................................................................................70
POCF1:
Power-on-clear register 1 ....................................................................................................................152
PU0:
Pull-up resistor option register 0 ............................................................................................................71
PUB2:
Pull-up resistor option register B2..........................................................................................................72
[S]
SCKM:
Suboscillation mode register..................................................................................................................78
SIO10:
Transmit/receive shift register 10.........................................................................................................127
222
User’s Manual U15043EJ3V1UD
APPENDIX B REGISTER INDEX
[T]
TCA40:
Carrier generator output control register 40........................................................................................... 95
TCL2:
Watchdog timer clock selection register .............................................................................................. 122
TM30:
8-bit timer counter 30............................................................................................................................. 91
TM40:
8-bit timer counter 40............................................................................................................................. 91
TMC30:
8-bit timer mode control register 30 ....................................................................................................... 93
TMC40:
8-bit timer mode control register 40 ....................................................................................................... 94
[W]
WDTM:
Watchdog timer mode register ............................................................................................................ 123
WTM:
Watch timer mode control register....................................................................................................... 117
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223
APPENDIX C REVISION HISTORY
C.1 Major Revisions in This Edition
Page
Description
U15043EJ2V0UD00 → U15043EJ3V0UD00
p.18
Change of 1.5 78K/0S Series Lineup
p.28
Modification of description in 2.2.15 VPP (µPD78F9328 only)
p.73
Addition of Caution 2 in Figure 4-14 Format of Port Function Register 8
Change of figures
p.88
Figure 6-1 Block Diagram of Timer 30
p.89
Figure 6-2 Block Diagram of Timer 40
p.90
Figure 6-3 Block Diagram of Output Controller (Timer 40)
p.90
Addition of description in 6.2 (2) 8-bit compare register 40 (CR40) and (3) 8-bit H width compare
register 40 (CRH40)
p.108
Addition of description in 6.4.3 Operation as carrier generator
p.114
Change of 6.5 Notes on Using 8-Bit Timers 30 and 40
p.119
Partial Change of caution in Figure 7-3 Watch Timer/Interval Timer Operation Timing
p.128
Change of Figure 9-1 Block Diagram of Serial Interface 10
p.130
Addition of 9.3 (2) Port mode register 2 (PM2)
p.134
Change of Table 10-1 Maximum Number of Pixels
p.137
Change of Note 2 in Figure 10-2 Format of LCD Display Mode Register 0
p.138
Change of Table 10-3 Frame Frequencies (Hz)
p.139
Addition of Caution 2 in Figure 10-4 Format of Port Function Register 8
p.142
Change of Table 10-4 COM Signals
p.143
Addition of (a) Static display mode in Table 10-5 LCD Drive Voltage
p.143
Addition of (a) Static display mode in Figure 10-6 Common Signal Waveforms
p.144
Addition of (a) Static display mode in Figure 10-7 Voltages and Phases of Common and Segment
Signals
p.145
Addition of 10.7.1 Static display example
p.171
Addition of Note 4 in Table 13-4 Operation Statuses in STOP Mode
p.200, 203
Addition of the recommended oscillation circuit constants of the flash memory version, and change of
the values of the supply current in CHAPTER 18 ELECTRICAL SPECIFICATIONS
p.224
Addition of C.1 Major Revisions in This Edition
U15043EJ3V0UD00 → U15043EJ3V1UD00
p. 15
Modification of 1.3 Ordering Information
p. 212
Addition of Table 20-1. Surface Mounting Type Soldering Conditions (2/2)
224
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APPENDIX C REVISION HISTORY
C.2 Revision History of Previous Editions
The revision history of this edition is listed in the table below. “Chapter” indicates the chapter of the previous
edition where the revision was made.
(1/2)
Edition
2nd
Revisions
Chapter
Use of POC circuit of mask ROM product can be selected by mask option.
Throughout
Deletion of description “input mode only” from condition of connecting on-chip pull-
CHAPTER 2 PIN
up resistor of port 2
FUNCTIONS
Change of processing of VPP pin
Change of processing of VLC0 pin when it is not used
Change of Table 3-3 Special Function Register List
CHAPTER 3 CPU
ARCHITECTURE
Deletion of description “input mode only” from condition of connecting on-chip pull-
CHAPTER 4 PORT
up resistor of port 2
FUNCTIONS
Change of block diagram of P20, P21, P22, and P80 to P85
Modification of description on PM8 in Figure 4-11 Format of Port Mode Register
Addition of Caution in Figure 4-13 Format of Pull-up Resistor Option Register
B2
Addition of note on feedback resistor
Modification of description on switching CPU clock
CHAPTER 5 CLOCK
GENERATOR
Modification of Figure 6-6 Format of Carrier Generator Output Control
CHAPTER 6 8-BIT TIMERS
Register 40
30 AND 40
Correction of value in Table 6-3 Interval Time of Timer 30 (at fX = 5.0 MHz
Operation)
Addition of Caution to 6.4.3 Operation as carrier generator
Modification of Figure 10-1 Block Diagram of LCD Controller/Driver
Modification of Figure 10-2 Format of LCD Display Mode Register 0
CHAPTER 10 LCD
CONTROLLER/DRIVER
Modification of Caution in Figure 10-3 Format of LCD Clock Control Register
Revision of description in 10.4 Setting LCD Controller/Driver
Correction of description in Table 12-2 Flags Corresponding to Interrupt
CHAPTER 12 INTERRUPT
Request Signal Name
FUNCTIONS
Modification of bit 2 in Figure 12-2 Format of Interrupt Request Flag Register 0
to CSIIF10 and addition of Caution
Modification of bit 2 in Figure 12-3 Format of Interrupt Mask Flag Register 0 to
CSIMK10
Modification of description in 12.3 (3) External interrupt mode register 0 (INTM0)
so that 1-bit memory manipulation instruction can be used
Addition of explanation to Figure 12-6 Format of Key Return Mode Register 00
Modification of description on OSTS in 13.2 Register Controlling Standby
CHAPTER 13 STANDBY
Function so that 1-bit memory manipulation instruction can be used
FUNCTION
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APPENDIX C REVISION HISTORY
(2/2)
Edition
2nd
Revisions
Addition of Figure 14-5 Reset Timing by Power-on Clear
Modification of value of port mode register 8 (PM8) in Table 14-1 Hardware
Chapter
CHAPTER 14 RESET
FUNCTION
Status After Reset
Addition of description on power-on clear circuit and oscillation stabilization wait
time to Table 15-1 Differences Between µPD78F9328 and Mask ROM Versions
CHAPTER 15 µPD78F9328
Total revision of description on flash memory programming as 15.1 Flash
Memory Characteristics
Addition of electrical specifications
CHAPTER 18
ELECTRICAL
SPECIFICATIONS
Addition of package drawing
CHAPTER 19 PACKAGE
DRAWING
Addition of recommended soldering conditions
CHAPTER 20
RECOMMENDED
SOLDERING CONDITIONS
Total revision of description of development tools
APPENDIX A
Deletion of embedded software
DEVELOPMENT TOOLS
Addition of revision history
APPENDIX C REVISION
HISTORY
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