Cypress | CY14B101L | CY14B101L 1 Mbit (128K x 8) nvSRAM

CY14B101L
1 Mbit (128K x 8) nvSRAM
Functional Description
■
25 ns, 35 ns, and 45 ns Access Times
■
Pin compatible with STK14CA8
■
Hands off Automatic STORE on Power Down with only a small
Capacitor
■
STORE to QuantumTrap Nonvolatile Elements is initiated by
software, hardware, or AutoStore on Power Down
■
RECALL to SRAM initiated by Software or Power Up
■
Unlimited READ, WRITE, and RECALL Cycles
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
■
200,000 STORE Cycles to QuantumTrap
■
20 year Data Retention at 55°C
■
Single 3V +20%, –10% Operation
■
Commercial and Industrial Temperature
■
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
■
RoHS Compliance
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Features
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Logic Block Diagram
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DQ 1
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DQ 2
N
DQ 3
DQ 4
DQ 5
DQ 6
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
HSB
A15 - A 0
COLUMN IO
INPUT BUFFERS
R
DQ 0
ROW DECODER
A5
A6
A7
A8
A9
A 12
A 13
A 14
A 15
A 16
en
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QuantumTrap
1024 x 1024
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10 A 11
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06400 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 19, 2009
[+] Feedback
CY14B101L
Contents
DC Electrical Characteristics ............................................ 8
Data Retention and Endurance ......................................... 8
Capacitance ........................................................................ 9
Thermal Resistance ............................................................ 9
AC Test Conditions ............................................................ 9
SRAM Read Cycle ...................................................... 10
SRAM Write Cycle....................................................... 11
AutoStore or Power Up RECALL .................................... 12
Software Controlled STORE/RECALL Cycle .................. 13
Switching Waveforms ...................................................... 14
Part Numbering Nomenclature ........................................ 15
Ordering Information ........................................................ 15
These parts are not recommended for new designs. ... 15
Package Diagrams ............................................................ 17
Sales, Solutions, and Legal Information ........................ 20
Worldwide Sales and Design Support......................... 20
Products ...................................................................... 20
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Functional Description ....................................................... 1
Logic Block Diagram .......................................................... 1
Contents .............................................................................. 2
Pinouts ................................................................................ 3
Device Operation ................................................................ 4
SRAM Read ......................................................................... 4
SRAM Write ......................................................................... 4
AutoStore Operation .......................................................... 4
Hardware STORE (HSB) Operation ................................... 4
Hardware RECALL (Power Up) .......................................... 5
Software STORE ................................................................. 5
Software RECALL ............................................................... 5
Data Protection ................................................................... 5
Noise Considerations ......................................................... 5
Low Average Active Power ................................................ 5
Preventing Store ................................................................. 6
Best Practices ..................................................................... 6
Maximum Ratings ............................................................... 8
Operating Range ................................................................. 8
ig
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Features ............................................................................... 1
Document Number: 001-06400 Rev. *K
Page 2 of 20
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CY14B101L
Pinouts
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
A16
A14
A12
A7
A6
A5
NC
A4
NC
NC
NC
VSS
NC
NC
DQ0
I/O Type
A0–A16
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
34
33
32
31
30
29
28
27
26
25
NC
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Description
Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
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Input
DQ0-DQ7
19
20
21
22
23
24
VCC
A15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
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Alt
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Table 1. Pin Definitions
Pin Name
Top View
(not to scale)
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A3
A2
A1
A0
DQ1
DQ2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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ns
VCAP
VCC
A15
HSB
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
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32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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VCAP
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground
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VSS
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WE
Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
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NC
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VCC
No Connect
No Connect. This pin is not connected to the die.
Document Number: 001-06400 Rev. *K
Page 3 of 20
[+] Feedback
CY14B101L
Device Operation
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to 5V by a charge pump internal to the chip.
A pull up is placed on WE to hold it inactive during power up.
The CY14B101L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE
operations.
Figure 2. AutoStore Mode
V CC
0.1UF
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V CAP
10k Ohm
V CC
V CAP
WE
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The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–16 determines the 131,072 data bytes accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAA (READ cycle 1). If the READ is
initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the tAA access time without
the need for transitions on any control input pins, and remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
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SRAM Read
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SRAM Write
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A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle.
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The data on the common IO pins DQ0–7 are written into the
memory if it has valid tSD, before the end of a WE controlled
WRITE or before the end of an CE controlled WRITE. Keep OE
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers tHZWE after WE goes LOW.
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AutoStore Operation
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The CY14B101L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101L continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, tDELAY
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
If HSB is not used, it is left unconnected.
Document Number: 001-06400 Rev. *K
Page 4 of 20
[+] Feedback
CY14B101L
Hardware RECALL (Power Up)
Data Protection
During power up or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH.
Software STORE
If the CY14B101L is in a WRITE mode (both CE and WE are low)
at power up after a RECALL or after a STORE, the WRITE is
inhibited until a negative transition on CE or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
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Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Noise Considerations
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The CY14B101L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
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Low Average Active Power
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CMOS technology provides the CY14B101L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B101L depends on the
following items:
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To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x8FC0, Initiate STORE cycle
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Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
■
The duty cycle of chip enable
■
The overall cycle rate for accesses
■
The ratio of READs to WRITEs
■
CMOS versus TTL input levels
■
The operating temperature
Software RECALL
■
The VCC level
■
IO loading
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The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Figure 3. Current Versus Cycle Time
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Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x4C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Document Number: 001-06400 Rev. *K
Page 5 of 20
[+] Feedback
CY14B101L
Preventing Store
Best Practices
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
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If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
■
If AutoStore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger VCAP value
to make sure there is extra store charge should discuss their
VCAP size selection with Cypress to understand any impact on
the Vcap voltage level at the end of a tRECALL period.
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The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on must always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
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Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of
CE controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
■
Document Number: 001-06400 Rev. *K
Page 6 of 20
[+] Feedback
CY14B101L
.
Table 2. Hardware Mode Selection
WE
X
OE
X
A15 – A0
Mode
IO
Power
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active[3]
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data Active ICC2[1, 2, 3]
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
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Active[1, 2, 3]
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CE
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Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06400 Rev. *K
Page 7 of 20
[+] Feedback
CY14B101L
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface Mount Lead Soldering
Temperature (3 Seconds) .......................................... +260°C
DC output Current (1 output at a time, 1s duration) .... 15 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High Z State ....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage...........................................–0.5V to Vcc + 0.5V
Range
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
0°C to +70°C
2.7V to 3.6V
-40°C to +85°C
2.7V to 3.6V
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Description
Test Conditions
Min
tRC = 25 ns
Commercial
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Industrial
Values obtained without output loads.
IOUT = 0 mA.
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Average VCC Current
VCC
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Industrial
Over the operating range (VCC = 2.7V to 3.6V) [4, 5]
ICC1
Ambient Temperature
Commercial
DC Electrical Characteristics
Parameter
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Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Max
Unit
65
55
50
mA
mA
70
60
55
mA
mA
mA
Average VCC Current
during STORE
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
6
mA
ICC3
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
without output loads.
Typical
10
mA
ICC4
Average VCAP Current All Inputs Do Not Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
3
mA
ISB
VCC Standby Current
3
mA
IIX
-1
+1
μA
IOZ
Input Leakage Current VCC = Max, VSS < VIN < VCC
Off State Output
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
Leakage Current
-1
+1
μA
VIH
Input HIGH Voltage
2.0
VCC + 0.5
V
VSS – 0.5
0.8
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ICC2
VIL
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CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
VOH
Output HIGH Voltage
IOUT = –2 mA
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and Vss, 6V rated.
Input LOW Voltage
V
2.4
17
V
0.4
V
120
uF
Data Retention and Endurance
Min
Unit
DATAR
Parameter
Data Retention at 55°C
Description
20
Years
NVC
Nonvolatile STORE Operations
200
K
Notes
4. The HSB pin has IOUT = –10 μA for VOH of 2.4 V. This parameter is characterized but not tested.
5. VIH changes by 100 mV when VCC > 3.5V.
Document Number: 001-06400 Rev. *K
Page 8 of 20
[+] Feedback
CY14B101L
Capacitance
In the following table, the capacitance parameters are listed.[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
7
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[6]
ΘJC
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
32-SOIC
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
Thermal Resistance
(Junction to Case)
32.9
°C/W
13.6
16.35
°C/W
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R1 577Ω For Tri-state Specs
3.0V
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3.0V
Unit
33.64
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Figure 4. AC Test Loads
R1 577Ω
48-SSOP
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ΘJA
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Parameter
Output
Output
5 pF
R2
789Ω
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R2
789Ω
30 pF
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AC Test Conditions
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Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times (10% to 90%) ...................... <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
6. These parameters are guaranteed by design and are not tested.
Document Number: 001-06400 Rev. *K
Page 9 of 20
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CY14B101L
AC Switching Characteristics
SRAM Read Cycle
25 ns
Description
Min
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
35 ns
Max
Min
25
45 ns
Max
35
15
3
3
3
3
10
3
3
13
15
0
0
35
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ew
25
15
0
es
10
45
20
13
0
0
45
ig
ns
25
12
Max
45
35
0
Min
35
25
D
Parameter
Cypress
Alt
Parameter
tACE
tELQV
tAVAV, tELEH
tRC [7]
tAA [8]
tAVQV
tDOE
tGLQV
tAXQX
tOHA [8]
tLZCE [9]
tELQX
tHZCE [9]
tEHQZ
tGLQX
tLZOE [9]
tHZOE [9]
tGHQZ
tPU [6]
tELICCH
tEHICCL
tPD [6]
Switching Waveforms
fo
W5&
rN
Figure 5. SRAM Read Cycle 1: Address Controlled [7, 8, 10]
de
W $$
d
$''5(66
en
W2+$
'$7$9$/,'
m
'4'$7$287
om
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [7, 10]
ec
R
$''5(66
W$&(
W+=&(
N
2(
W3'
W/=&(
ot
&(
W5&
W+=2(
W'2(
W/=2(
'4'$7$287
'$7$9$/,'
W 38
,&&
$&7,9(
67$1'%<
Notes
7. WE and HSB must be HIGH during SRAM READ cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
10. HSB must remain high during READ and WRITE cycles.
Document Number: 001-06400 Rev. *K
Page 10 of 20
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CY14B101L
SRAM Write Cycle
25 ns
Description
Min
Max
Min
25
20
20
10
0
20
0
0
Min
Max
45
30
30
15
0
30
0
0
13
3
3
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
Switching Waveforms
Max
35
25
25
12
0
25
0
0
10
3
45 ns
ig
ns
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
35 ns
es
Parameter
Cypress
Alt
Parameter
tAVAV
tWC
tPWE
tWLWH, tWLEH
tELWH, tELEH
tSCE
tDVWH, tDVEH
tSD
tHD
tWHDX, tEHDX
tAVWH, tAVEH
tAW
tAVWL, tAVEL
tSA
tHA
tWHAX, tEHAX
tWLQZ
tHZWE [9,11]
tWHQX
tLZWE [9]
ew
Figure 7. SRAM Write Cycle 1: WE Controlled [11, 12]
CE
tAW
de
d
tSA
en
WE
om
m
DATA IN
tPWE
tSD
tHD
DATA VALID
tHZWE
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
tHA
fo
tSCE
rN
tWC
ADDRESS
ec
Figure 8. SRAM Write Cycle 2: CE and OE Controlled [11, 12]
R
tWC
ot
N
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Notes
11. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
12. CE or WE must be greater than VIH during address transitions.
Document Number: 001-06400 Rev. *K
Page 11 of 20
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CY14B101L
AutoStore or Power Up RECALL
Parameter
Alt
tHRECALL [13]
tSTORE [14, 15]
VSWITCH
tVCCRISE
CY14B101L
Min
Max
20
12.5
2.65
150
Description
tRESTORE
tHLHZ
Power up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
Unit
ms
ms
V
μs
Figure 9. AutoStore/Power Up RECALL
STORE occurs only
if a SRAM write
has happened
es
VCC
ig
ns
Switching Waveforms
rN
ew
D
VSWITCH
No STORE occurs
without atleast one
SRAM write
fo
tVCCRISE
AutoStore
tSTORE
tHRECALL
tHRECALL
om
Read & Write Inhibited
m
POWER-UP RECALL
en
de
d
tSTORE
N
ot
R
ec
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below VSWITCH
Notes
13. tHRECALL starts from the time VCC rises above VSWITCH.
14. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
15. Industrial Grade devices requires 15 ms max.
Document Number: 001-06400 Rev. *K
Page 12 of 20
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CY14B101L
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [16, 17]
Parameter
Alt
25 ns
Description
Min
35 ns
Max
Min
Max
45 ns
Min
Max
Unit
tAVAV
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tSA
tAVEL
Address Setup Time
0
0
0
ns
tCW
tELEH
Clock Pulse Width
20
25
30
ns
tHA
tGHAX, tELAX
Address Hold Time
1
1
1
ns
RECALL Duration
tRECALL
120
ig
ns
tRC[17]
120
μs
es
Switching Waveforms
120
tRC
ew
tRC
tSA
ADDRESS # 6
rN
ADDRESS # 1
ADDRESS
D
Figure 10. CE Controlled Software STORE/RECALL Cycle [17]
tSCE
fo
CE
d
tHA
de
OE
en
DATA VALID
HIGH IMPEDANCE
om
m
DATA VALID
DQ (DATA)
t STORE / t RECALL
ec
Figure 11. OE Controlled Software STORE/RECALL Cycle [17]
tRC
CE
R
ADDRESS # 6
ot
ADDRESS # 1
N
ADDRESS
tRC
tSA
tSCE
OE
tHA
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Notes
16. The software sequence is clocked on the falling edge of CE controlled READs or OE controlled READs.
17. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-06400 Rev. *K
Page 13 of 20
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CY14B101L
Hardware STORE Cycle
Parameter
tPHSB
tDELAY
[18]
Alt
CY14B101L
Description
Min
tHLHX
Hardware STORE Pulse Width
15
tHLQZ , tBLQZ
Time Allowed to Complete SRAM Cycle
1
tss[19, 20]
Soft Sequence Processing Time
Max
Unit
ns
70
μs
70
us
Switching Waveforms
ig
ns
Figure 12. Hardware STORE Cycle
en
de
d
fo
rN
ew
D
es
3+6%
m
Figure 13. Soft Sequence Processing[19, 20]
om
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
W6$
ec
$GGUHVV
$GGUHVV
W66
$GGUHVV
W&:
N
ot
9&&
6RIW6HTXHQFH
&RPPDQG
R
&(
$GGUHVV
W&:
W66
Notes
18. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.
19. This is the amount of time to take action on a soft sequence command. Vcc power must remain high to effectively register command.
20. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Document Number: 001-06400 Rev. *K
Page 14 of 20
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CY14B101L
Part Numbering Nomenclature
CY 14 B 101 L - SZ 25 X C T
Option
T - Tape and Reel
Blank - Std.
Temperature
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
D
Data Bus
L - x8
es
Package
SZ - 32 SOIC
SP - 48 SSOP
ig
ns
Speed
25 - 25 ns
35 - 35 ns
45 - 45 ns
fo
rN
ew
Voltage
B - 3.0V
Density
101 - 1 Mb
de
d
NVSRAM
14 - AutoStore + Software Store + Hardware Store
en
Cypress
m
Ordering Information
ec
CY14B101L-SZ25XCT
Package Diagram
51-85127
Package Type
32-pin SOIC
CY14B101L-SZ25XC
51-85127
32-pin SOIC
CY14B101LL-SP25XCT
51-85061
48-pin SSOP
51-85061
48-pin SSOP
CY14B101L-SZ25XIT
51-85127
32-pin SOIC
CY14B101L-SZ25XI
51-85127
32-pin SOIC
CY14B101L-SP25XIT
51-85061
48-pin SSOP
CY14B101L-SP25XI
51-85061
48-pin SSOP
R
25
Ordering Code
ot
Speed
(ns)
om
These parts are not recommended for new designs.
N
CY14B101LL-SP25XC
Document Number: 001-06400 Rev. *K
Operating
Range
Commercial
Industrial
Page 15 of 20
[+] Feedback
CY14B101L
Ordering Information
These parts are not recommended for new designs.
32-pin SOIC
CY14B101L-SZ35XC
51-85127
32-pin SOIC
CY14B101L-SP35XCT
51-85061
48-pin SSOP
CY14B101L-SP35XC
51-85061
48-pin SSOP
CY14B101L-SZ35XIT
51-85127
32-pin SOIC
51-85127
32-pin SOIC
CY14B101L-SP35XIT
51-85061
48-pin SSOP
CY14B101L-SP35XI
51-85061
48-pin SSOP
CY14B101L-SZ45XCT
51-85127
32-pin SOIC
CY14B101L-SZ45XC
51-85127
32-pin SOIC
CY14B101L-SP45XCT
51-85061
48-pin SSOP
CY14B101L-SP45XC
51-85061
48-pin SSOP
CY14B101L-SZ45XIT
51-85127
32-pin SOIC
CY14B101L-SZ45XI
51-85127
CY14B101L-SP45XIT
51-85061
CY14B101L-SP45XI
51-85061
Industrial
Commercial
D
CY14B101L-SZ35XI
Commercial
ig
ns
51-85127
es
CY14B101L-SZ35XCT
Operating
Range
Package Type
ew
45
Package Diagram
rN
35
Ordering Code
Industrial
32-pin SOIC
48-pin SSOP
fo
Speed
(ns)
48-pin SSOP
N
ot
R
ec
om
m
en
de
d
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
Document Number: 001-06400 Rev. *K
Page 16 of 20
[+] Feedback
CY14B101L
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
16
1
ig
ns
REFERENCE JEDEC MO-119
es
0.405[10.287]
0.419[10.642]
D
32
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
ew
17
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.292[7.416]
0.299[7.594]
SEATING PLANE
fo
0.090[2.286]
0.100[2.540]
rN
0.810[20.574]
0.822[20.878]
0.026[0.660]
0.032[0.812]
d
0.004[0.101]
0.050[1.270]
TYP.
de
0.004[0.101]
0.0100[0.254]
*A
0.006[0.152]
0.012[0.304]
51-85127-*A
N
ot
R
ec
om
m
en
0.014[0.355]
0.020[0.508]
51-85058
0.021[0.533]
0.041[1.041]
Document Number: 001-06400 Rev. *K
Page 17 of 20
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CY14B101L
Package Diagrams (continued)
51-85061-*C
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
Figure 15. 48-Pin Shrunk Small Outline Package (51-85061)
Document Number: 001-06400 Rev. *K
Page 18 of 20
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CY14B101L
Document History Page
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 001-06400
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
425138
TUP
See ECN
New data sheet
437321
TUP
See ECN
Show data sheet on External Web
*B
471966
TUP
See ECN
Changed ICC3 from 5 mA to 10 mA
Changed ISB from 2 mA to 3 mA
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 40 μs to 50 μs
Changed Endurance from 1 million Cycles to 500K Cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
*C
503272
PCI
See ECN
Changed from Advance to Preliminary
Changed the term “Unlimited” to “Infinite”
Changed Endurance from 500K Cycles to 200K Cycles
Added temperature specification to Data Retention - 20 years at 55°C
Removed Icc1 values from the DC table for 25 ns and 35 ns industrial
grade
Changed Icc2 value from 3 mA to 6 mA in the DC table
Added a footnote on VIH
Changed VSWITCH(min) from 2.55V to 2.45V
Added footnote 17 related to using the software command
Updated Part Nomenclature Table and Ordering Information Table
*D
597002
TUP
See ECN
Removed VSWITCH(min) specification from the AutoStore/Power Up RECALL table
Changed tGLAX specification from 20 ns to 1 ns
Added tDELAY(max) specification of 70 μs in the hardware STORE cycle
table
Removed tHLBL specification
Changed tSS specification from 70 μs (min) to 70 μs (max)
Changed VCAP(max) from 57 μF to 120 μF
*E
688776
VKN
*F
1349963
*G
2427986
*H
2546756
m
en
de
d
fo
rN
ew
D
es
ig
ns
**
*A
Added footnote related to HSB
Changed tGLAX to tGHAX
UHA/SFV
See ECN
Changed from Preliminary to Final
Updated Ordering Information table
GVCH
See ECN
Move to external web
GVCH/AESA
08/01/2008
N
ot
R
ec
om
See ECN
Document Number: 001-06400 Rev. *K
Aligned part number nomenclature
Corrected typo in ordering information
Changed pin definition of NC pin
Updated data sheet template
Page 19 of 20
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CY14B101L
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 001-06400
Rev.
ECN No.
Orig. of
Change
Submission
Date
*I
2625139
GVCH/PYRS
01/30/09
*J
2695908
GVCH/AESA
04/20/2009
Removed part numbers CY14B101L-SP25XC and
CY14B101L-SP25XCT.
Added part numbers CY14B101LL-SP25XC and
CY14B101LL-SP25XCT.
*K
2814390
GVCH
11/25/2009
Added Note in the Ordering information section mentioning that these
parts are not recommended for new designs.
Added “Not recommended for new designs” watermark in the PDF..
Description of Change
en
Worldwide Sales and Design Support
de
Sales, Solutions, and Legal Information
d
fo
rN
ew
D
es
ig
ns
Updated “features”
Added data retention at 55oC
Updated WE pin description
Added best practices
Added ICC1 spec for 25ns and 35ns access speed for industrial temperate
Updated VIH from Vcc+0.3 to Vcc+0.5
Removed footnote 4 and 5
Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter tAS to tSA
Changed tRECALL from 50us to 120us (Including tss of 70us)
Renamed tGLAX to tHA
Updated figure 11 and 12
Renamed tHLHX to tPHSB
Updated Figure 13
m
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06400 Rev. *K
Revised November 19, 2009
Page 20 of 20
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