070205_CGC_7900_Parallel_Input_Output_DMA_Mar82.pdf

070205_CGC_7900_Parallel_Input_Output_DMA_Mar82.pdf
PARALLELINPUTjOUTPUT
DIRECT MEMORY ACCESS
CGC 7900 SERIES
COLOR GRAPHIC COMPUTERS
CHROMATICS
CGC 7999
Parallel Input/Output
Direct Memory Access
User1s Manual
March 25, 1982
DOCUMENT NUMBER 070205
PUBLICATION DATE 1/82
COPYRIGHT © 1982
. CHROMATI~S, INC.
/
TABLE OF CONTENTS
PREFACE
i-I
SECTION ONE - PIO/DMA GENERAL HARDWARE
PIO GENERAL DESCRIPTION
.DMA GENERAL DESCRIPTION
1-1
1-2
1-3
SECTION TWO - PIO/DMA HARDWARE OPTIONS
MEMORY ADDRESS SELECTION
INTERRUPT LEVEL SELECTION
VECTOR ADDRESS SELECTION
BUS GRANT SELECTION
2-1
2-2
2-3
2-4
2-5
SECTION THREE - HARDWARE EXPANSION
INTERRUPT EXPANSION
BUS MAST~R EXPNASION
3-1
3-2
3-3
SECTION FOUR - PIO THEORY OF OPERATION
PROGRAMMABLE PORT CONTROL REGISTERS
POLLING THEORY OF OPERATION
PIO POLLING TO WRITE
PIO POLLING TO READ
PIO WRITE OPERATIONS USING INTERRUPTS
PIO READ OPERATIONS USING INTERRUPTS
4-1
4-2
4-3
4-4
4-5
SECTION FIVE - PIO HARDWARE DESCRIPTION
HAR-DWARE THEORY OF OPERATION
PIO OPTIONING
PIO INPUT/OUTPUT OPTION
PIO CONNECTOR DEFINITION
4-6
4-7
5-1
5-2
5-3
5-4
5-5
SECTION
DMA
DMA
DMA
DMA
DMA
SIX - DMA THEORY OF OPERATION
TRANSFER MODES
THEORY OF OPERATION
REGISTER INITIALIZATION
BUS CYCLES
REGISTER DEFINITION
6-4
SECTION
DMA
DMA
DMA
DMA
SEVEN - DMA HARDWARE DESCRIPl'ION
SIGNAL DEFINITION
CONNECTOR PIN ASSIGNMENTS
JUMPER OPTIONS
CONFIGURATIONS
7-1
7-2
7-3
7-4
7-5
DMA Sample User Program
6-1
6-2
6-3
6-5
6-6
Appendix A
PREFACE - The purpose of tbis document is to define the CGC
Memory Access Circuit
board (PIO/DMA). It describes the overall attributes of the
board as well as goes into detail about the operation and
design of the board.
7900'S Parallel Input/Output, Direct
1-1 -PIO/DMA GENERAL HARDWARE - The CGC 7900 PIO/DMA consists
of one standard size digital circuit board, which will
occupy one card slot in the 7999 mother board.
The circuit
board has five connectors along its card edge, two for the
PIO interface, two for the DMA interface and one for
Interrupt and Bus Grant Level Prioritizing.
The PIO/DMA circuit board consists of four separate 16 bit
parallel interfaces. Two are programmable ports which the
processor has full control 'over and the other two are DMA
ports which once activated perform all transfers independent
of the CPU.
1-2 PIO GENERAL DESCRIPTION - The programmable port can be
operated by way of polling or by way of interrupts.
Polled
operation requires the CPU to write or read data to or from
the port and then test the PIO status register to determine
the readiness of .the port. The second mode of operation is
interrupt driven I/O. When the interface has a data word or
byte for the CPU or is ready to transfer another word or'
byte out the port it notifies the CPU via an interrupt
forcing the CPU to stop what it is doing and service the
parallel port.
The Parallel Port consists of two 16 bit data registers one
for input and the other for output. Each of these two ports
can be subdivided into two 8 bit ports each with its own
status, interrupt, and control circuitry.
The main features of the Parallel Port are:
1) Two 16 bit ports; one for input, one for output,
each with its own control signals.
2) Word or byte transfers.
3) CPU interaction by polling or interrupts.
4) All receivers and drivers are differential according to
RS-422 and RS-423 standards.
5) Transfer rates of up to l50K words or bytes per second.
1-3 DMA GENERAL DESCRIPTION
The
DMA
interface
is
compatible with three DEC DMA interfaces, the DRVll-B,
DRll-W and DRll-B, each being used with a different type of
DEC computer. Below are listed the main features of the DMA
interface.
1) Two 16 bit ports one for input and one for output.
2) Data transfers up to s00K per second.
3) Separate 49 pin connector for input and output.
4) Transfer of up to 64K words at once without processor
intervention.
5) Capable of Burst or Single Cycle Operation.
2-1 PIO/DMA HARDWARE OPTIONS - The purpose of this section
is to describe certain hardware options that are applicable
to both PIO and DMA portions of the board.
There are
additional options which apply strictly to either the PIO or
DMA hardware which will be· discussed in the appropriate
sections of this manual.
2-2 MEMORY ADDRESS SELECTION - By use of a switch located at·
UF3 on the board the starting base address of all the
registers on the board can ·be relocated in memory between
FF8400 to and FF84F0. See Table I for switch setting ve~sus
memory address information.
THIS SPACE LEFT BLANK INTENTIONALLY
1<-------->0
1
2
SW/UF3
3
4
Switch
Position
Base
Address
FF8400
FF8410
FF8420
FF8430
FF8440
FF8460
FF8470
FF8480
FF8490
FF84A0
FF84BI
FF84C0
FF84DI
FF84EI
FF84FI
1
2-
3
4
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
I
1
1
1
1
1
1
1
1
I1
1
0
1
0
0
1
1
Base Address Switch Postions
Table 1.
1
1
1
1
1
1
1
1
2-3 INTERRUPr LEVEL SELECTION
If any of the interrupt
capability on the board is to be used the two interrupt
level jumpers must be installed. These jumpers select the
interrupt level at which all the interrupts on the board
will operate.
The interrupt levels that are available for use are levels
1, 2, 3 and 6. Levels 4 and 5 are reserved for the CPU
board and level 7 is reserved for the power ~p interrupt.
Jumpers J2 arid J3 are the interrupt level Jumpers.
The
level of interrupt desired must be reflected on both of
these jumpers and must be the same. Example: if J2 has a
jumper in position two J3 must also have its jumper in
position two. Each header must have only one jumper.
In
order to complete interrupt acknowledge decoding there must
also be a jumper installed on header Jl at position IN~.
Refer to Section 5.~ HARDWARE EXPANSION if more than one
board is to be installed at the same interrupt level.
2-4 VECTOR ADDRESS SELECTION
The
interrupt
vector
addresses of all the interrupts occurring on the board are
switch selectable. Vector addresses between l~~ and 13F are
reserved for the interrupts on the CPU card.
There is a
possibility of eight interrupts occurring on the PIO/DMA
board including the spare. Thus, the base address of the
interrupt vectors must move at even intervals of eight.
The
switch used to select the vector addresses is located at·
position UC1l. See Table 2 for vector address selection.
2-5 BUS GRANT SELECTION - The level of bus master control
granted to each PIO/DMA board is selectable by means of
jumpers located at J4 and J5.
In a single board system
there must be one jumper installed in both J4 and J5 headers
and they must agree with each other. Example: If bus master
level three is desired, J4 must have a jumper at three and
J5 must have a jumper at three in the 2 thru 5 positions.
Refer to Section 5.9 HARDWARE EXPANSION if more than one
board is to share the same Bus Master level.
0.<-------->1
1
2
SW/Cll
3
4
Base
Vector
Adress
299H
229H
249H
269H
289H
2MH
2C08
2E0H
399H
3208
349H
36gB
3898
3A98
3C9H
3E9H
Switch
Position
1
2
3
4
9
1
9
9
1
1
9
9
9
9
"
"
""
1
1
1
1
1
1
1
9
1
o
o
1
1
9
1
o
1
o
1
o
1
o
o
1
1
o
o
1
1
9
"
1
1
1
1
1
1
9
"
1
1
1
1
9
9
9
9
""
1
Base Interrupt Vector Switch Positions
Table 2.
3-1 HARDWARE EXPANSION - The purpose of this section is to
describe methods in which more than one PIO/DMA board can be
used in one system. The types of expansion referred to are
Interrupt Expansion and Bus Master Expansion.
The first step to be taken when expanding either
an
interrupt level or a bus grant level is that of installing
the Priority Cable between the two boards at position P3.
This cable is a 26 pin card edge to card edge cable
available from Chromatics (PiN 100428).
3-2 INTERRUPr EXPANSION - When selecting interrupt levels if
it is desirable to have two boards share the same interrupt
level the hardware priority cable must be installed between
the two boards, see above. The interrupt priority jumpers
must also be positioned properly on the two boards.
The
board which is to have the highest priority within the level
must have a jumpers at positions IN 0 and OUT 1.
The next
board in the chain must have jumpers at positions IN 1 and
OUT 2 and so on down the line. The maximum number of boards
to share the same interrupt level is 10.
3-3 BUS MASTER EXPANSION
Bus
Master
Expansion
is
accomplished in much the same
manner
that
Interrupt
Expansion is.
The board which is to have the highest
priority within the bus grant level must have a jumper at
position IN2 and position OUTl on J5. The next board in the
chain will have jumpers at position IN 5+1 and position OUT2
and so on. This sequence will continue up until the last
board in the chain. All boards in the same level must have
the jumper at J4 in the same position indicating a shared
level. Thus, any board in the chain can request the bus
causing the CPU to grant it. The first board in the chain
will receive the bus grant signal from the processor and if
it does not want the bus at the present time it will
propagate the signal out to the next board and so on down
the chain.
NOTE: It must be assured that there are no
conflicts in the switch settings
for either the memory or vector
addresses.
4-1 PIO THEORY OF OPERATION - This section of the manual
will describe functionally how the PIO portion the PIO/DMA
board operates.
4-2 PROGRAMMABLE PORT CONTROL REGISTERS
The programmable
parallel port consists of one 16 bit control register and
two 16 bit data registers. The addresses of these registers
are as follows:
FF84xa
FF84X1
FF84X2
FF84X3
low data byte read or write address
high data byte read or write address
Parallel Port Status byte (See Below)
Parallel Port Interrupt mask (See Below)
Figure 1 is a definition of the Parallel Port Control
Register. Following the figure is the definition of each
bit.
THIS SPACE LEFT BLANK INTENTIONALLY
Register name
Memory location
PROGRAMMABLE PORT CONTROL REGISTER (PPCR)
FF84X2
(Base word address)
FF84X2
Status Byte
bits 8 - 15
FF84X3
Interrupt mask
bits 0 - 7
Bit position
111111111111111 I 1
115114!13112!111101 91 81716151 4! 31 21 1101
11111111111111111
Bit Name
1111111111111111
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Interrupt Enable 1 (lEI
!
1 1 1 1 1 1 1 1 1 1 1 1 1
-----------------------1 1 1 1 1 1 1 1 1 1 1 1 1 1 1----- Interrupt Enable 2 (IE2
1 1 1 1 1 1 1 1 1 1 1 1 1 1
-----------------------1 ! 1 1 1 1 1 1 I 1 1 1 1 --------- Interrupt Enable 3 (IE3
1 I 1 1 1 1 I 1 1 I 1 1 1
-----------------------1 1 1 1 1 1 1 1 1 1 1 1 ------------ Interrupt Enable 4 (lE4
1 1 I 1 1 1 1 1 1 1 I 1
-----------------------1 1 1 1 1 1 1 1 1 1 1 --------------- Interrupt Enable 5 (lES
1 1 1 1 1 1 1 1 1 1 1
-----------------------1 1 1 1 1 1 1· 1 1 1 ------------------ Interrupt Enable 6 (IE6
1 1 1 1 1 1 1 1 1 1
-----------------------1 1 1 1 1 1 1 1 1 --------------------- Interrupt Enable 7 (IE7
1 I 1 1 1 1 1 1 1
-----------------------1 1 1 1 1 1 1 1 ------------------------ SPARE
1 1 1 1 1 1 1 1
-----------------------1 1 1 I 1 1 1 --------------------------- Input Data Rdy Lo (lOR
1 1 1 1 1 1 I
-----------------------1 1 1 I 1 1 ------------------------------ Input D3ta Rdy Hi (lOR
1 I I 1 1 1
-----------------------1 1 I I 1 --------------------------------- Input Data Rdy
(IDR
-----------------------1 I 1 1 1
1 1 1 1 ------------------------------------ Output Data Rdy Lo (ODR
1
1
1
1
1
1
1
1
1
1
1
1
1
------------------------
1 --------------------------------------- Output Data Rdy Hi (ODR
1
----------------------------------------------------------------- Output Data Rdy
(ODR
1
------------------~------------------------------------------------- Output Enable Hi
(OEL
------------------------
------------------------------------------------ Output Enable Lo
Programmable Control Register Definition
Figure 1.
(OEB
The interrupt enables bits located in the low byte of the
control word are used to enable anyone of seven interrupt~···
and are defined as follows:
lEI - Enables interrupts to occur when the present DMA
transfer is complete. This indicates to the CPU that the
interface must now be re-programmed in order to perform
another transfer. (0=Interrupt Enabled, l=Interrupt Masked)
IE2 - Enables interrupts on the low byte of the
data word. This interrupt indicates to the CPU
data can now be sent out to this byte of
(0=Interrupt Enabled, l=Interrupt Masked)
out going
that more·
the port.
IE3 - Enables interrupts on the high byte of the
data word. This interrupt indicates to the CPU
data can now be sent out to this byte of
(0=Interrupt Enabled, l=Interrupt Masked)
out going
that more
the port.
IE4 - Enables interrupts on the entire sixteen bit output
word. This interrupt indicates to the CPU that the entire
word is now ready to transmit more data.
(0=Interrupt
Enabled, l=Interrupt Masked)
IES - Enables interrupts on the low byte of incoming data
word. Indicates to the CPU that a byte has been received ·on
input data bits B-7 and is ready to be read.
(0=Interrupt
Enabled, l=Interrupt Masked)
IE6 - Enables interrupts on the high byte of the incoming
data word. Indicates to the CPU that a byte has been
received on input data bits 8-15 and is ready to be read.
(0=Interrupt Enabled, l=Interrupt Masked)
IE7
Enables interrupts on the incoming
data
word,
indicates to the CPU that data has been received on input
data bits 0-15 and is now ready to be read.
(0=Interrupt
Enabled, l=Interrupt Masked) The high byte of the input data
buffers. (Active=l)
IDRLO - Status bit indicating to the CPU that there is data
present at the low byte of the input data buffers. (Active=l)
IDR - Status bit indicates to the CPU that there is data
present at the input word to the data buffers. (Active = 1)
ODRHI - Status bit indicates to the CPU that the data on the
high byte of the output data buffers has been transferred
and more data can now be written out to it.(Active=l)
ODRLO - Status bit indicates to the CPU that the data on
low byte of the output data buffers has been transferred
more data can now be written out to it. (Active=l)
ODR - Status bit indicates to the CPU that the entire
the
and
output
word has been transferred and more data can
out to it. (Active=l)
now
be
written
OELO - This is a read write control bit which when set to
011, which are
one enables the output data drivers 00
otherwise tri- state.
OEHI - This is a read write control bit which when set to
one enables the output data drivers 012- 015, .which are
otherwise tri- state.
NOTE: OELO and OEHI must be set to one's for output port
to work at all.
4-3 POLLING THEORY OF OPERATION - This portion of the manual
will describe how to use the programmable parallel port in
polling mode. There are two polling sequences- the CPU can
go thru in relation to the programmable port, the first is
polling waiting to write and the second is waiting to read.
4-4 PIO POLLING TO WRITE - When the CPU is ready to write
out either a word or a byte, the appropriate status bit can
be tested. If the bit is found to be in the active state it
indicates to the CPU that the previous data has been
transferred and more data can now be sent.
This operation
can continue as long as there is more data to be transmitt~d
or until the device on the other end of the interface stops
reading the data being transmitted.
4-5 PIO POLLING TO READ - When the CPU is expecting input
data from the parallel port it may initiate a polling
sequence on the appropriate byte or word status bit. If the
status bit is found to be active the CPU may read the byte
or word, store it and continue to poll for as long as is
required.
All control signals to the interface are manipulated
hardware which is triggered from the CPU reads or writes.
by
4-6 PIO WRITE OPERATIONS USING INTERRUPTS - There are three
types of interrupts which can trigger the CPU to transfer
data out of the parallel output port.
The first is the
write word interrupt. This interrupt occurs when the PIO
output hardware has transferred both the high and the low
bytes out to the user device and can now accept another word
for transmission. The second type of write interrupt which
can occur is the write high byte interrupt.
This interrupt
occurs when the PIO output hardware has completed the
transmission of the data on the high byte of the parallel
output latch and can now accept more data to be transmitted
out on that byte. The final type of write interrupt which
can occur is the write low byte interrupt.
This interrupt
occurs when the parallel output hardware has completed the
transmission of the data on the low byte of the parallel
output port and can now accept more data to be transmitted
on that byte. For any of these interrupts
interrupt mask bit must be set to a zero
status word. (See above).
the appropriate
in the control
4-7 PIO READ OPERATIONS USING INTERRUPTS
Three types of
interrupts exist from which the 7900 CPU can receive an
interrupt from the parallel port.
The first type is the
Read Word Interrupt. This interrupt occurs when all 16 bits
of input data have been presented to the parallel port input
buffers and is ready to be read by the CPU. The second type
of read interrupt which can occur is the read high byte
interrupt.
This interrupt occurs when data
has
been
presented to the high input data buffer of the parallel port
and is ready to be read by the CPu. The final type of read
interrupt which can' occur is the read low byte interrupt.
This interrupt occurs when data has been presented to the
high byte of the parallel port input buffers and is ready to
be read by the CPU.
5-1 PIO HARDWARE DESCRIPTION - Once the CPU has determined
that the output port desired is available for transfer a
write operation is performed to the appropriate location in
memory. On the trailing low to high transition of the write
operation the output date is latched into the output buffers
and the appropriate OUTPUT DATA READY signals are set active
as follows:
ODRLO - Output Data Ready Low Byte
ODRSI - Output Data Ready High Byte
ODR - Output Data Ready Word
These signals will remain active until the appropriate
Output. Data Acknowledgements are received at the interf ace
as follows:
ODAKLO - Output Data Acknowledge Low Byte
OOAKBI - Output Data Acknowledge High Byte
ODAK - Output Data Acknowledge Word
CPO WRITE
ODRLO
ODRHI or
ODR
ODAKLO
ODKARI
ODAK
Sets \\1JUTE Inter:rupt and STA'IUS Bit
PIO Write Timing
Figure 2.
Once the appropriate data acknowledgements go
again status bits will be set to indicate to the
another transfer can now be performed.
inactive,
CPU that
5-2 HARDWARE THEORY OF OPERATION - If a user device has data
to be input to the CPU it must first set up the data at the
appropriate data inputs. It must then bring the appropriate
positive input data ready signal positive with the respect
to the minus input as follows:
IDRLO - Input Data Ready Low Byte
IORHI - Input Data Ready High Byte
IDR - Input Data Ready Word
These signals as well as the data inputs must remain active
until the data has been read by the cpu. On the low to high
trailing edge of the CPU read of the input data port the
appropriate input data acknowledges signals will be set
active as follows:
IOAKLO - Input Data Acknowledge Low Byte
IOAKHI - Input Data Acknowledge High Byte
IOAK - Input Oata Acknowledge Word
Signal timing should be as follows:
i~~~
Sets :REM> Intern:JP.t: and
or
IDR
STA'ltlS
Bit"'l
I
CPU READ
IDAKLO
IDAKBI
IDAR
PIO Read Timing
Figure 3.
5-3 PIO OPTIONING - There are three configurations which the
PIO receivers can be operated under.
One is as straight
differential receivers
with
no
bias
or
terminating
resistors. The second is differential receivers with a
shunt terminating. resistor across the positve to minus
inputs. The third configuration is that of a single ended
receiver with terminating resistors at the minus input
holding it at a threshold of approximately 3.9 volts and a
single resistor terminator to ground on the positive input.
T~ implement each of the three
configurations see Table 3
for resistor pack values and locations.
Configuration
B
A
R4
RS
R6
R7
Ra
R9
R19
Rll
Rl6
R17
RIa
R19
R20
R21
R23
R24
C
T
S
S
S
S
S
PIO
P
P
T
T
P
P
T
T
P
1/4 w 339 ohm
1/4 w 479 ohm
1/4 W 330 ohm
1/4 W 330 ohm
1/4 W 479 ohm
1/4 W 330 ohm
*
*
*
*
*
*
Options
Table 3.
Te~minator
Configuration A is straight Differential with no resistors.
Configuration B is
straight
Differential
·with
shunt
resistors.
Configuration C is single ended receivers with 2.2 volt bias
at the minus input and a terminator to ground on the PLO
input.
Resistor S is an a pin 220 ohm series resistor pack
Resistor P is an a p1n 229 ohm common end resistor pack
Resistor T is an 10 pin· 470 ohm/330 ohm terminating resistor
pack.
*
NOTE:
When configuration B is selected a 1/4 Watt 220 ohm resistor
must be installed between the signal ends of Rla and R19,
and R23 and R24.
Below are three schematic representations of each
available configurations that can exist on the input
PIO card.
+l
~
Volts
470 Ohn
330 Ohn
PIa Terminator Configurations
Figure 4.
of
to
the
the
5-4 PIO INPUT/OUTPUT OPTIONING - On the P4 connector of the
PIO port there are the 16 data outputs, three output control
lines, three input control lines, three connections for
ground, and three connections for +5 volts.
These signals
are all that is needed for the parallel port to operate in
the mode that is described in the theory of operation of the
parallel port.
There are certain conditions with some
interfaces that a static input is needed for some sort of
status of a device.
To accomplish this static
input
operation two mechanisms have been included in the design of
the output parallel port.
The first is the ability to
tri-state the upper 4 bits of the sixteen output data bits
and the second is the four pin header located at J6 on the
circuit board. The upper four bits are made tri-state by
the clearing of bit 6 in the PIO. control register, this
operation is described further in section 6.0 PIO Theory of
Operation. Once these bits are tri-state the four jumpers
located at J6 can be installed and thus the four most
significant ouptuts bits on the P4 connector have been
turned into static inputs that can be tested by the CPU.
5-5 PIO CONNECTOR DEFINITION - The PIO/DMA circuit has two
50 Pin card edge connectors which are designed to be used
strictly for programmed parallel transfers to and from tne
CPU. The two connectors are designated P4 and P5, P4 being
the data output connector and PS being the data input
connector. Below are lists of all the pins available at the
connectors, the associated signal name for each pin and a
brief description of each is given.
PlO/DMA P4 Connector Designation
------------------------------------------------------------Signal
Name
Pin
Number
Signal
Name
Pin
Number
-~-----------------------------------------------------------
1
2
3
4
5
6
7
8
9
1a
11
12
13
14
15
16
17
18
19
2a
21
22
23
24
25
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
a
a
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
la
11
11
12
26
27
28
29
3a
31
32
33
34
35
36
37
38
39
4a
41
42
43
44
45
46
47
48
49
50
* DATA OUT
DATA OUT
* DATA OUT
DATA OUT
* DATA OUT
DATA OUT
* DATA OUT
GND
+5 Volts
GND
+5 Volts
GND
+5 Volts
ODRHl
* ODRHl
ODRLO
* ODRLO
ODR
* ODR
ODAKHl
* ODAKHI
ODAKLO
* ODAKLO
ODAK
* ODAK
PlO/DMA P4 Connector Designation
Table 4.
*SlGNAL COMPLEMENT
12
13
13
14
14
15
15
PIO/DMA P5 Connector Designation
------~---------------------------~------------------- --------
Signal
Name
Pin
Number
Pin
Number
Signal
Name
-------------------------------------------------------------1
2
3
4
5
6
7
8
9
19
11
12
13
14
15
16
17
18
19
29
21
22
23
24
25
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
* DATA
DATA
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
~
~
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
19
19
11
11
12
26
27
28
29
3ft)
31
32
33
34
35
36
37
38
39
49
41
42
43
44
45
46
47
48
49
59
* DATA IN 12
DATA IN 13
* DATA IN 13
DATA IN 14
* DATA IN 14
DATA IN 15
* DATA IN 15
GND
+5 Volts
GND
+5 Volts
GND
+5 Volts
IDRHI
* IDRHI
IDRLO
* IDRLO
IDR
* IDR
IDAKHI
* IDAKHI
IDAKLO
* IDAKLO
IDAK
* IDAK
PIO/DMA P5 Connector Designation
Table 5.
*SIGNAL COMPLEMENT
6-1 DMA THEORY OF OPERATION - The purpose of this section is
to describe how general purpose Direct Memory Transfers are
accomplished to and from the CGC 790g.
The DMA portion of the PIO/DMA card has been designed to be
compatible with DEC's DRlI-W, DRVIl-B and DRlIB DMA parallel
interfaces. The details concerning the DMA hardware are in
Section 7 nDMA Hardware Description·. This section deals
with the overall operation of the interface.
6-2 DMA TRANSFER MODES - There are two modes in which data
can be transferred to or from the DMA interface.
These are
Burst Mode transfers and Single Cycle Mode transfers.
In
both modes of operation the interface is armed by the CPU,
all subsequent transfers up until the end of the specified
transfer
size
are
then
done
without
further
CPU
intervention.
The difference
lies
in
how
the
bus
arbitration is handled between the CPU and the DMA board.
In Burst Mode once the interface is armed the logic on the
DMA board will acquire the system bus and not relinquish it
until the entire transfer is complete. In Single Cycle Mode
the DMA logic will share the system bus with the processor
using every other memory cycle while the CPU uses the ones
in between. Inside the Burst Mode and Single Cycle Mode
there are two types of data transfers that can be performed,
they are:
1 Write Words (7900 to DEC)
2 Read Words (DEC to 7900)
NOTE: The DRll-W, DRVll-B and DRlI-B interfaces also
support read-modify write mode and byte transfers,
these two modes are not supported on the CGC DMA
board.
How each of these modes are selected and their effects on
the system will be discussed in the 'control register
definition.
6-3 DMA THEORY OF OPERATION
There are two types of
transfers that can be performed to or from a DEC machine,
one is a program controlled transfer and the other is a DMA
type of transfer. The program controlled transfer is very
similar to that of the PIO transfer in that all transfers
are performed under control of the CPU.
However, the
protocol as to when data is valid and not valid
is
completely up to the user. Data is transferred via the data
buffer registers using the STATUS and FUNCTION lines to
determine data availability. The purpose of this section of
the manual is to describe in detail how a DMA transfer
operation is performed from the CGC 7900 to a receiving
device.
6-4 DMA REGISTER INITIALIZATION - Before a DMA transfer
initiated by the CGC 7900 the following registers must
set up:
is
be
1) Word Count Register
2) Control Register
3) Bus Address Register
4) Extended Address Register
The final write to the Extended Address Register is the
data.
trigger to the interface to begin
transferring
Depending on whether the transfer is from CGC 7900 to DEC or
from DEC to CGC 7909 the DMA logic will perform one of two
sequences descibed in the following section.
6-5 DMA BUS CYCLES
7909· Bus Request Cycle
The DMA control circuitry will drive low the selected Bus
Request Line on the CPU control bus and wait for the
corresponding Bus Grant Signal from the CPU.
Once the CPU·
has granted the bus and completed its present bus cycle the
DMA control logic will remove its Bus Request and drive low
the Bus Grant Acknowledge Signal (BGACK). The activation of
this signal causes the CPU buffers -to go tri-state and thus
removes the CPU from the system bus.
The BGACK signal
causes the CPU card to remove its Bus Grant. The CPU is now
completely off the bus and the DMA circuitry has full access
to the entire system.
7909 DMA Logic Data Fetch Cycle
When the DMA control logic has been granted the bus by the
CPU it immediately enables its output buffers, containing
the address and all control bus information for the desired
data. After a period of approximately 79 nanoseconds the
DMA control logic asserts Address Strobe, Upper and/or Lower
Data Strobe and then waits for the Data Transfer Acknowledge
signal back from the selected memory (DTACK).
When the
DTACK signal is received the DMA logic will wait 209 nanoseconds and then latch the data into data output buffers.
It will also remove Address Strobe, Upper and/or Lower Data
Strobe, remove its address buffers from the bus, increment
its word count register and bus address registers and
release its hold of the bus by de-asserting BGACK.
The CPU
will then begin normal execution exactly where it left off
before the bus was relinquished to the DMA control logic.
7900 Cycle Request to the DRll-W, DRVll-B or DRll-B
Once the data has been loaded into the output data buffers
and is ready for transfer to the DEC interface the DMA
control logic will assert CYCLE REQUEST.
This will cause
the DEC interface to initiate a bus cycle.
This will be
indicated to the 7900 DMA control logic by the assertion of
the BUSY signal by the DEC interface. The 7900 DMA control
logic will then remove its cycle request and wait for the
BUSY signal to be de-asserted. The 7900 DMA control logic
will then check to see if the transfer is complete.
If not
it will continue the transfer by once again requesting the
system bus.- If the transfer is complete the DMA logic can
interrupt the CPU or can be polled by the CPU by testing the
appropriate bit in the DMA Status Register.
If the transfer is to be from the DEC interface to the 7900
the 7900 Cycle Request is performed first, thus acquiring
the data to be written into the 7900 memory.
The 7900 DMA
control logic will then perform a Bus Request Cycle as
described above. Once the system bus has been acquired the
following sequence will be performed:
7908 Data Write Operation
Once the system bus has been acquired the DMA control logic
will enable its address- buffers, data buffers, function code
buffers
and
write
signal
buffer.
Approximatly
70nanoseconds later Address Strobe Upper and/or
Lower
Data
Strobes will be asserted. When the selected memory responds
with DTACK the DMA logic will wait 200 nanoseconds and then
de-assert address strobe, the data strobes as well as remove
all of its other buffers from the data bus. It will finally
relinquish the bus by de-asserting BGACK.
See timing figures five and six for signal relationships.
JAI W.. lte
,
I
V
DHA Sta .. t 'u1 ••
\
IRQ(.)
\ ~_~I
.C(x)
,
--/.1·
~----~~~---------~~----­
CPU AS.DTACI
IGACI
DKA Driv ....
----------------~\
.uff .... off
DKA AS. Data Strobe.
DTACI
Cycle Request
Busy
'
...
",,-_
< Buffers
/
on
)~_ __
""..«• ----4100tput
\..
D:lta latched Here
----~----------------=-\~--J/
,
----------------~_~--~r-\~--------\...~------------~--------~--------~I
•
CGC to DEC Host Timing
Figure 5.
XAR Write
OMA Start Pulse
'-1r------------------------\J~--------------------~--~
Cycle Request
~
~------------------...
,~~~~~~------------------------------Busy
,,._......, ere Input Data Latched Here
,
IRQ(.)
le(x)
'--_-..I
/
'
_-4
'--1,,..1___ r'
•
,
'\
..1
CPU ASePtACI,
I
\
BGACK
< Buffers
DHA Dl'tve ... - - - - - - - luf f .... of f - - - - -....
~.rJ·
DNA AS. Data Stro' ••
BTACK
DEC Host to
Timing
eee
,Figure 6 ..
,
on
)
/
I
(
6-6 DMA REGISTER DEFINITION - There are six registers which
are used strictly by the DMA portion of the DMA/PIO circuit
board. This section of the manual describes how those
registers are used.
OUTBUF - This is a 16 bit output data latch which can be
written to by the CPU directly or through the DMA hardware.
The CPU can write to this buffer only when the DMA is not
active, once the interface is armed and until the transfer
is complete all transfers to the OUTBUF are under control of
the DMA hardware.
INBUF - This is a 16 bit input latch used to receive data
from the DEC or other host device. This buffer can be read
either directly by the CPU, or via the DMA hardware.
Once
the interface is armed and until the trans'fer is complete
all control of the INBUF is via the DMA hardware.
Bus Address Register(BAR) - This register contains the least
significant 16 address bits
of
the
address
to
be
transferred. This is a write only register.
Control Register(CTRLREG) - The Control Register is an 8 bit
read/write register which is used to control all of the
details of the type of transfer to be done.
The Control
Register along with the Extended Address Register combine to'
make up one 16 bit register, the. control register being the
least 'significant 8 bits. (See Below)
Extended Address Register(XAR) - This is an 8 bit write only
register containing the most significant 7 bits of address
information. This along with the Control Register make up a
16 bit register, the XAR being the most significant 8 bits
with the MSB not being used. The loading of this register
triggers the transfer. (See Below)
Word Count Register - This is a write only register which
loaded with the two's complement of the word count to
tr ansfer red.
The addresses for all registers pertaining
portion of the PIO/DMA card are as follows:
to
the
is
be
DMA
FF84X4 Address Bits 17-23 of the DMA address (See Below)
FF84X5 Read Write Control bits pertaing to DMA transfers
(See Below)
FF84X6 Bits 8 - 15 of the word count
FF84X7 Bits 0 - 7 of the word count
FF84X8 address bits 1 - 16 of the starting DMA address
FF84XA Read/Write DMA High data word
FF84XD DMA Status byte (See Below)
X Selected by address switch, see Hardware Optioning
Register name
Memory location
Control/Extended Addresss
$FF84X4
Bit position
-------------------------------------------------
I I I I I I I I I I I I I I I 1 I
1151141131121111191 91 81 71 61 51 41 31 21 11 91
I 1 I I 1 I I I I I I I I I I I 1
Bit Name
------------------------------------------------I
Status A
1
1
I
I
I
I
J
---------------------
------ Status B
----------------------------- Status C
--------------------------------
C1
I
--------------------I --------------- C9
I
-------------------------------------- Single Cycle
--------------------- Attention
------------------------ Super/User
--------------------------- XADD-17
------------------------------ XADD-18
--------------------------------- XADD-19
------------------------------------
XADD~2S
-----------------~--------------------- XADD-21
------------------------------------------ XADD-22
--------------------------------------------- XADD-23
------~----------------------------------------- Spare
Extended Address/Control Regsiter Definition
Figure 7.
XADDl7 THRU XADD23 - Used to hold the most significant 7
bits of the CGC address to or from which the transfer is to
be perf ormed.
Status A, Band C
User defined status bits, used for
program controlled transfers to indicate data ready and data
received.
ca
and CI - These two output control signals are used by the
DEC machine to indicate the type of bus cycle to be
performed, they are defined as follows:
ca CI Bus Cycle
---------------------------------a
Word Transfer from PDP
a
a
Not Used
I
S
I
I
I
to CGC
Word Transfer from CGC to PDP
Not Used
Bus Cycle Definitions
Table 6.
Single Cycle - This signal indicates to the DEC machine the
bus master mode under which the transfer. is to take place.
When this bit is high the transfer is done one cycle at a
time, thus sharing the bus with the cpu. When this bit is
low the transfer is done all at once and the system bus isnot relinquished until the transfer is complete.
Attention - Used to notify the PDP-II that some sort
exception has occurred and that the present transfer must
aborted.
of
be
Super/User - Used to define the type of memory area in which
the CGC transfer is to take place. When it is high it will
be a supervisor data area transfer and when it is low it
will be a user data area transfer.
DMA Status Register - The DMA status register contains five
signals from the interface which are used in determining the
state of the interface. These bits are not part of the
control register due to the fact that the CGC has no control
over them, they are read only. Below is the definition of
the . . Status Register with a description of each bit following.
DMA Status Register
Register name
$FF84XD
Memory location
(Byte)
Bit position
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I 71 61 51 41 31 21 11 01
Bit Name
---------------------~---
I
I
I
I
I
I
I
I
I
I
1
1
I
1
I
1
1
------ FUNCTION CODE 1
---------------------
I I --------- FUNCTION CODE 2
I I
--------------------I ------------ FUNCTION CODE 3
I
----------------------------------- INIT V2 (DRVIl-B)
--------------~-----I -~---------------- READY
I
----------------------------------------- DMA Ready
J
---~----~--~-~---------~ SPARE
-----~~----~--------------- SPARE
DMA Status Register Definition
Figure 8.
FUNCTION CODES 1, 2 and 3 - These are status bits which can
be used to convey to the 7900 some sort of interface
information. The function of these bits are user defined.
If FUNCTION CODE 2 is set high by the user device it will
cause an interrupt to occur in the 7900.
If the DMA
interrupt enable bit is cleared in the interrupt mask
register. This is a level and must be cleared by the user
after some sort of acknowledg.ement has occurred.
INIT V2 - Used for interprocessor communication
reflect the state of FUNCTION CODE 2.
READY - Indicates to the CGC that the user
to begin a transfer. (Acive = 1)
device
it
is
DMA Ready - This bit when active indicates that the
hardware has completed the most recent transfer and is
ready to be initialized for another transfer.
will
ready
DMA
now
7-1 DMA HARDWARD DESCRIPTION
As was mentioned earlier
there are two 40 pin right angle connectors located on the
card edge of the PIO/DMA card which are used strictly for
transfers to a DEC computer.
All
signals
on
these
connectors are compatible with DEe·s DRII-W, DRII-B and
DRVII-B DMA interfaces, with a few minor differences which
will be discussed here. Connections are made to the DEC.
computer system via a pair of 40 pin flat ribbon cables.
If
connection is to be made into a DRVIl-B these cables will
connect directly onto the DRVII-B circuit board on the DEC
Q-Bus. If connection is to be made into a DRII-B these
cables will connect directly into the CGC 7900 to DRlI-B
adapter board supplied by Chromatics (PIN 100428).
See
Cable
Diagrams
A
and
B
for
these
two
cable
inter-connections. If connection is to be made to the
DRIl-W the cables will be plugged directly into the DRlI-W
on the UNIBUS.
THIS SPACE LEFT BLANK INTENTIONALLY
7-2 DMA SIGNAL DEFINITION - All signals described in this
section of the manual are also described in the Associated
DEC User Manuals for the DRVll-B, DRIlW, and the DRIl-B DMA
interf aces.
99 OUT - 15 OUT
16 TTL output
interface.
lines
99 IN - 15 IN
16 TTL input
interface.
STATUS A,B, C
Three TTL output lines to the DEC
interface. The function of these
lines are defined by the user.
FUNCT 1,2,3
Three TTL input lines from the DEC
interface. The function of these
lines are defined by the user. *
INIT
One TTL input
DEC interf ace.
INIT V2 (DRVll-B)
One TTL input line from the DEC
interface.
Used by DEC machines
for inter-processor.
User def ined'
for CGC 7999 applications.
lines
to
the
DEC
from
the
DEC
Status line from the
AS9 One TTL output line to the DEC
interface. This line is normally
for word transfers.
During byte
transfers
this
line
controls
address bit 09 in the DEC machine.
BUSY
One TTL' input line from the DEC
interface. BUSY is low when the
DRVll-B or the DRIl-B control logic
is requesting control of the LSI-II
bus or when a DMA cycle is in
progress. A low to high transition
indicates the end of the cycle.
Busy is high when the DRIl-W is
requesting the bus or performing a
data transfer.
A high
to
low
transition indicates the end of the
cycle.
READY
One TTL input line from the DEC
interface.
When the READY
line
goes low DRA transfers
may
be
initiated by the CGC 7999.
C9,Cl
C9, CI Two TTL output lines to the
DEC interface. These lines control
the type of bus cycle that the DMA
hardware logic will execute.
SINGLE CYCLE
One TTL output line to the DEC
interface.
This line is
pulled
high on the DEC interface. When it
goes low it indicates a burst mode
transfer to the DEC machine.
WC",INC ENB
One TTL output line to
interface. This line is
high to enable incrementing
Address
Counter.
Low
incrementing.
the DEC
normally
the Bus
inhibits
BA INC ENB
One TTL output line to
interface. This line is
high to enable incrementing
address counter inside the
logic. A.low on this line
incrementing.
the DEC
normally
the bus
DEC DMA
inhibits
CYCLE REQUEST
One TTL output line to the DEC
interface.
A
low
to
high
transition of this line initiates a
DMArequest.
ATTN
One TTL output line to the DEC
interface.
This line is
driven
high to terminate DMA transfers, to
set the READY bit and request an
.interrupt if the interrupt enable
bit is set.
* Whenever the DEC computer drives the F2 line high at the
CGC interface it will cause the interrupt bit to be set and
the present transfer if there is one to be terminated.
This
is level activated not edge.
7-3 DMA CONNECTOR PIN ASSIGNMENTS
P6
Conne ct or Pin
B
D
F
J
K
L
N
R
T &V
DD
FF
JJ
LL
NN
RR
TT
VV
CC
EE
aa
KK
MM
PP
SS
UU
Signal
P7
Conne ct or Pin
CYCLE-REQUEST
INIT V2
READY
WC INC ENB
SINGLE CYCLE
STATUS A
INIT
STATUS B
STATUS C
08 IN
09 IN
10 IN
11 IN
12 IN
13 IN
14 IN
15 IN
07 IN
96 IN
05 IN
04 IN
03 IN
92 IN
91 IN
00 IN
B
D
F
J
K &L
N
R
T
V
DD
FF
JJ
LL
NN
RR
TT
VV
CC
EE
HH
KK
MM
PP
5S
UU
CGC 7900 DMA Connector Pin Outs
Table 7.
Signal
BUSY
ATTN
A00
BA INC ENB
FNCT 3
C0
FNCT 2
Cl
FNCT 1
08 OUT
09 OUT
10 OUT
11 OUT
12 OUT
13 OUT
14 OUT
15 OUT
07 OUT
06 OUT
05 OUT
04 OUT
03 OUT
02 OUT
01 OUT
09 OUT
A
uu
Q:nlector
on I'-1l\IPI
tcard.
w
cable Q:nlector
-
All Dins are lettered in
.
.
al~tical order A thru Z and
M thru V'o'l.
Skiroing (;,I,O,Q,GG,II,OO and
00.
P6 or P7 Pin Definition
Figure 9.
7-4 DMA JUMPER OPTIONS - There are two jumper headers that
are related strictly to the DMA portion of the circuit,
these are J8 and J9. These two jumpers are available in
order to select the polarity of CYCLE REQUEST and BUSY at
the user interface connections.
The
following
is
a
description of each possibility and the exact position of
each jumper for each.
Refer to Figure 14 for jumper
relative positions.
OPTION 1 - The first jumper configuration is the one which
is to be used for the DRIl-W interface.
With both jpmpers
in their A positions a high CYCLE REQUEST and a high BUSY
signal is selected meaning that the active state of these
signals at the user interface will be between 2.2 volts and
5 volts.
CYCLE~
\
/
-----I
_ _--..II
BUSY
\.
OPTION 1 Waveforms
Figure 19.
OPTION 2 - The second jumper configuration is for DRVIl-B
applications. With jumper J9 in its B position and jumper
J8 in its A position a high CYCLE REQUEST and A low BUSY
signal is selected.
CYCLE
REX2UES'!'
BUSY
/
\
\
OPTION 2 Waveforms
Figure 11.
/
OPTION 3 - The third jumper configuration is for DRll-B
applications. With jumper J8 in its position A and jumper
J9 in its position B, a low CYCLE REQUEST and a high BUSY
signal is selected.
\
_oo_~____________~/
I
\~_____
OPTION 3 Waveforms
Figure 12.
OPTION 4 - The fourth and final possibility is
jumpers in position B. In this configuration a
REQUEST and a low BUSY signal is selected.
BUSY
with both
low CYCLE
\",,--------,1
\'------1/
OPTION 4 Waveforms
Figure 13.
NOTE: The BUSY signal in all of the above configurations
must be in its inactive state in order for CYCLE
REQUEST to ever go active.
The above
waveforms
illustrate that requirement.
/
(PIO out)
(PIO In)
-1'4-
I,.
(0ttA)
-PS-
I"
(0ttA)
0
J8
-P3-
G
Ie;
IS
0:
3
0:
(E:.':~tl,.)
It
• UCU I
.D<em,""
PI
JS
7-5 DMA CONFIGURATIONS
CGC 7999 to DRII-B Hardware Configuration - The DRII-B is a
Direct memory access I/O device which is designed to be
used with DEC UNIBUS. This interface consists of a small
card cage which is mounted inside the
DEC
computer
framework. Inside the card cage is all the logic necessary
to perform a DMA transfer to the DEC UNIBUS. To complete a
connection from the CGC 7999 DMA board to a DEC computer
having a DRII-B two operations must be performed.
First
the DRII-B to CGC 7999 adapter board must be inserted into
the DRII-B card cage at location C and D-4.
The second
step is to connect up the two 40 ribbon cables as follows:
P6 of CGC DMA Board to Jl of the Adapter Board
P7 of CGC DMA Board to J2 of the Adapter Board
J
a;c 7900
tf12V'PIO
DRlI-B
(l'\..ranat:ics DRlI-B
h2?ter BOard
DRII-B System Configuration
Figure 15.
i
CGC 7900 to DRll-W Configuration
is a
CGC 7900 to DRll-W Hardware Configuration -It Theis DRll-W
a
general
single board replacement for the DRIl-B. to and from the
purpose DMA devi~e used to transmit data DRII-W
connect up
DEC UNIBUS. To complete a hook up to a
the two 40 pin ribbon cables as follows:
P6 CGC 7900 DMA Board to Jl of the DRIl-W
P7 CGC 7900 DMA Board to J2 of the DRIl-W
J
CT!tC 7900
IJ·m.,I!?IO
L
I
t
1
-
O:?J.l-t~
DR11 B System Conf1gurat10n
Figure 16.
.!
;
;:;
~~
,CJl
-,
Lf
Olranatics M68000 Assembler -
Version 1.1 -
Copyright (C) 1982
Pass 11
Pass 12
000000
000000
000000
000000
000000
000000
000000
000000
. 000000
000000
000000
000000
000000
000000
000000
000000
.000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
0001
0002
0003
0004
0005
0006
0087
0008
0009
0010
00ll
0012
0013
0014
0015
0016
0017
0018
0019
0020
002l
0022
0023
0024
0025
0026
00z]
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
*
*
*
*
*
*
*
AJ;pendix A
*
*
*
132
*******************************************************************
*******************************************************************
****
****
****
****
****
Module Nane : llnaDr
****
****
Function
: a4A I/O driver
****
****
****
****
****
****
Discrip:ion - The turPOse of this modlue is to
****
****
provide an easy interface for the system programmer ****
****
to the a;c 7900' s rMA interface board. All entr anee ****
****
and exit reqisters are defined below, this infor- .
****
****
along with the Users Manual should provide all the
****
****
information needed to make use of the rMA portion
****
****
o£ the tMA/PIO circuit board.
****
****
When this module is invoked it .is assumed that
****
****
the ~cified data areas have been carefully
****
****
selected by the system programmer.
****
****
All Ad:1resses are based at £f8400 if the user
****
****
has reconfigured the adress switches the addresses
****
****
must be changed accordingly, this also };artains
****
****
to the Vector address s e l e c t i o n . ****
****
****
****
****
*******************************************************************
*******************************************************************
*******************************************************************
""""""
""""""
""""""
""""""
""""""
""""""
"""""0
"0"""0
00""00
"00900
"00000
"09000
"0"000
900"90
"090"0
"9""00
"990"0
"90090
"""900
"09900
9039
""49
~E
*
*
"942 *
"043 *
""41
""44
"045
"046
"047
"048
9"49
""50
*
PHI
PLO
PSTAT
DW)K
ARB!
Jlt1ACIm,
0"51 WCREG
""52 wa,o
"053 ARm
"054 ARLO
"055 IlWl1d'
Hardware Register Address Designations
EXlU
EXlU
EXlU
EXlU
EXlU
EXlU
B.:lU
B.:lU
EXlU
B.:lU
a:u
""56
EOJ
""57 IJt1ASTAT EXlU
I:MAU)
""58
$FF84"0
$FF8401
$FF84"2
$FF8403
$FF8404
$FF8405
$FF8496
$FF8497
$FF8498
$FF8499
$FF840A
$FF849B
$FF8400
High Data Byte Parellel Port
Lao1 Data Byte Parelle Port
Status Byte for the Parellel Port
Interrupt Mask for PIOIMA board
The High Se'len Bits of Address for IMA xf!
Caltrol. Register for IMA Transfer
High Byte Word Count Register IMA Transfe:
Lao1 Byte Word Count Register IMA Transfer
High Byte (A9-Al6) AcXiress Register IMA
Lao1 Byte (Al-AS) AcXiress Register IMA
Read I:MA Data Word, Write IMA High Byte
Wri te IMA Data LaoI Byte
IMA Status Byte
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
0059
0e60
0e61
0062
0063
006 4
0e65
0e66
0067
006 8
0e6 9
0670
*
*
*
~GE
Mask Bits in
MRIEI
Kmm
EXJU
EJJO
EXJU
EXJU
$3
KiRLO
EtU
$1
ltfiRfI
EXJJ
$2
$0
MRll'ID
MRW)
JD!AIXfi EJJO
$6
$4
$5
The
Interrupt Mask Register
Mask
Mask
Mask
Mask
Mask
Mask
Mask
InterrU{X
Interrupt
Interrupt
Interrupt
InterrU{X
Interrupt
interrupt
Bit
Bit
Bit
Bit
Bit
Bit
Bit
for Read Word
for Read Low Byte
for Read High Byte
Write Word
Write Low Byte
Write High Byte
for tMA done
BBBBBB
BBBBBB
BBBBBB
BBBBBB
BBBBBB
BBBBBB
BBBBBB
BB"B""
B"B"""
B"""""
B"""""
B1J71
B1J72 *
B1J73 *
B1J74 *
B1J75
B1J76 IDRLO
B1J77 IDRBI
B1J78 IDR
"~9
CDRLO
B"8" omBI
""81 a:R
PAGE
Status Register Bit Definition Parel1el Port
me
$B
$1
me
$2
$3
EXJU
$4
BJU
$5
EXJU
EtU
Input Data Ready Low byte
Input Data Ready High byte
Input Data Ready Word
Ready to Write La1 Byte
Ready to Write High Byte
Ready to Write Word
11J11J11J11J11J11J
11J11J11J11J11J11J
11JI1JI1JI1JI1JB
I1JBBBBB
I1JBBI1JBB
I1JI1JBBBB
BBBBBB
99BBBB
BBBBBB
BBBBBB
BBBBBB
BBBBBB
BBBBBB
I1JB82
BN3E
9BS3 *
11J984 *
I1JBBS *
9BS6
9BS7 Vlbytin mo
Interrupt Vector Locations
$29C
9BSS~mo
$2BS
BBS9 V'wordin BJU
999B Vlbytwr BJO
9991 Vhbytwr mo
$294
$21S
$214
$21B
$21C
B992 V'wordir QJ
9B93 Vdmacbn BJU
B994
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Low Byte Read
High Byte Read
Word Read
LQ1 Byte Write
high Byte Write
Write Word
tMA cbne
000i"~0
0e95
0096
0097
0098
0099
0101
0IF000
0IF000
0IF000
*
0IF000
*
0IF000
Iln *
0lF000
1102 *
01F000
1183 *
0lF000
0104 *
01F000
1105 *
01F000
'- 0186 *
01F000
1lB7 *
01F000
1108 *
01F000
1109 *
01F000
0111 *
01F000
0lll *
0lF000
1112 *
0lF000
Bll3 *
0lF000
1114 *
0lF000 0839000000FF
840D
illS IJIA
01F008 48E7F000
0116
0117
01F00C 23C30000021C
0118
01F012 E788
01F014 008000000020
1119
0lF0lA 13C000FF8405
0120
01F020
0121 *
0lF020 4441
Bl22
1123
01F022 33Cl00FF8406
01F028
0124 *
0IF028 ~8A
1125
0lF02A 33C200FF8408
0126
0lF030 4842
0127
0lF032 13C200FF8404
0128
0lF038 4CDF000F
0129
rIIlF03C
0130 *
0IF03C 4E75
0131
0IF03E
0132 *
0lF03E
1133 *
rIIlF03E
0134 *
0IF03E
0135 *
01F03E
0136
0IF03E
1137 *
0IF03E
1138 *
01F83E
0139 *
01FB3E
0140 *
01FB3E
0141
0lFB3E
1142
0lFB3E
0143
0lFB3E
0144
Error Count : 0000
mGE
CRG.L
$lF000
This S\broutine actually enables the har&are
Enter with:
DI •
D1 =D2 =D3 =-
I for a IMA read, 1 for a IMA write
NlJnber of words to be transferred
Byte address to start transfer (buffer pointer)
Vecta:: Address Location
Exit with:
<Registers lI'lchanged>
B'.CS'l'
II ,r:MAS'l'AT
MOVEM.L
KNE.L
ISL.L
CR.L
MJVE. B
~3,-(SP)
D3,Vdmad:>n
1$3,DB
1$2S ,DB
DB ,IMAC'l'RL
~.W
Dl
MJVE.W D1,wam
ISR.L 11,D2
M:>VE. W D2,ARm
StlJR
D2
Reset the interrupt
save the registers
Set up the vector address
Get the read/write bit in position
Or in the Single Cycle bit
Write to control register
Get the 2's cnnplanent of the word count
Set up the word COtmt register
KNE.B D2,ARHI
Set up low 16 bits of address
Get the upper seven in lower eight
Write cut hi seven bits of the address
MJYEM.L (SP)+,D0-03
Restore the registers
RrS
A
write to the High address register initiates the transfer
END
IMA
CGC
to DRVII-B Configuration
79~~
The DRVIl-B is a general purpose DMA device used to
transfer data to and from the DEC Q-BUS. This is the bus
which is used in LSI-II computer systems. The DRVll-B is a
single board which plugs directly into the Q-BUS.
To
complete a hook up to the DRVII-B the two 4~ pin ribbon
cables must be installed as follows:
P·6 of the CGC
. P7 of the CGC
O:-C 7900
Il'aIPIO
I
I
79~~
79~~
DMA board to JI of the DRVII-B
DMA board to J2 of the DRVlI-B
I
D~ll-B
J
;?
8en
-S
;--f
........I
tI'
§l
DRVII-B System Configuration
Figure 17.
I
lJ
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