Clearpoint_QRAM-22B_User_Information_Manual.pdf

Clearpoint_QRAM-22B_User_Information_Manual.pdf
CLEARPOINT INC.
Q-RAM22B
USER INFORMATION
MANUAL
1OS South Street
Hopkinton, MA 01748
(S1 7) 435-5395
Telex: 298281
TABLE OF CONTENTS
CHAPTER 1 - GENERAL DESCRIPTION AND SPECIFICATIONS
1.1
1.2
1.3
1.4
Introduction •••••••••••••••••••••••••••••••••••••• l-l
General Description ••••••••••••••••••••••••••••••• 1-2
Backplane Pin Utilization ••••••••••••••••••••••••• 1-4
Specifications •••••••••••••••••••••••••••••••••••• 1-6
r
CHAPTER 2 - HARDWARE INSPECTION, INSTALLATION, AND CHECKOUT
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Introduction •••••••••••••••••••••••••••••••••••••• 2-l
Configuring the Q-RAM 22(B) Program Plugs ••••••••• 2-l
Addressing Options •••••••••••••••••••••••••••••••• 2-l
Board Size Configuration Plugs •••••••••••••••••••• 2-3
CSR Option Plug Configurations •••••••••••••••••••• 2-3
Battery Backup Option Plugs ••••••••••••••••••••••• 2-4
Installation Procedure •••••••••••••••••••••••••••• 2-S
CHAPTER 3 - CSR DESCRIPTION
3.1
3.2
Introduction •••••••••••••••••••••••••••••••••••••• 3-l
CSR Bit Assignment •••••••••••••••••••••••••••••••• 3-l
FIGURES
Figure 1
Figure 2
Program Plug Description ••••••••••••••••••••• 1-2
Q-RAM 22(B) •••••••••••••••••••••••••••••••••• 1-3
i
TABLES
Table
Table
Table
Table
Table
Table
Table
Table
1
2
3
4
5
6
7
8
Q-RAM 22(B} Products •••••••••••••••••••••••••• l-l
Backplane Power Pins •••••••••••••••••••••••••• 1-4
Backplane I/O Signal Pins ••••••••••••••••••••• 1-5
Multiple Q-RAM 22(B} Starting Addresses ••••••• 2-2
Memory Size Jumpers ••••••••••••••••••••••••••• 2-3
CSR Address Selection ••••••••••••••••••••••••• 2-4
Battery Backup Mode Options ••••••••••••••••••• 2-4
CSR Bits 5 to 11 •••••••••••••••••••••••••••••• 3-3
APPENDIXES
Appendix A
Appendix B
Appendix C
Memory Starting Address Chart •••••••••••••• A-l
Bank Selection ••••••••••••••••••••••••••••• B-l
Q-RAM 22B Block Mode DMA Memory Board •••••• C-l
ii
CHAPTER 1
GENERAL DESCRIPTION AND
1.1
SPECIFICA~IONS
INTRODUCTION
This manual supplies user information for the Q-RAM
22(B) family of memory modules. Q-RAM 22(B) modules (see
Table 1) provide high density, low cost per bit storage for
systems which utilize the Digital Equipment Corporation
(hereafter referred to as DEC*) Q-BUS.
64K MOS RAMS are
used as individual storage devices to provide up to 1 mbyte
on a single quad-height board. Features available on Q-RAM
22(B) are:
- Up to 1 MB memory capacity
- Jumper selectable 18 or 22(B) bit addressing
- Parity generation and checking on board
Complete
DEC software-hardware
compatible,'
parity control and status register on board
locatable at any of 8 assigned I/O page address
- Battery back-up support
- Single 5 volt power supply
address programmable at
any 64K
- Starting
boundary
- Parity error LED provides visual indication of
board failure
Table-l
Q-RAM Products
Description
Designation
1 MB board with parity
Q-RAM 22 (B)
1 MB boar.d no parity
Q-RAM 22(B)-1
512 KB board with parity
Q-RAM 22(B)-2
512 KB board no parity
Q-RAM 22(B)-3
*Registered trademark of Digital Equipment Corporation
1-1
1.2
GENERAL DESCRIPTION
The a-RAM 22(B) is a single quad-height memory module
which interfaces to the LSI-II a-BUS.
All timing and
control logic for the memory, refresh circuitry, parity
control, and status register are contained on board.
The MOS memory array consists of up to eight rows of
65,536 X 1 bit dynamic RAM devices with 18 devices per row.
Each row will accept 65,536 18 bit words consisting of
(two) eight bit bytes and two parity bits (one per byte).
Circuitry for refresh of the MOS memory devices is provided
on board and operates transparently to the user.
The a-RAM
22(B)
module's
starting
address is
selectable using program plugs PO to P4 (see figure 1 and
2) to any 64K boundary within the Q~BUS 22 or 18 bit
address space. Program plug P7 is used to select 18 bit or
22 bit addressing. BDAL 18, BDAL 19, BDAL 20, and BDAL 21
are ignored if 18 bit addressing is selected.
The module will not respond to BBS7 transfers to allow
the top 4K addresses to be reserved for I/O peripherals.
P8 is provided on board which allows the user to reclaim 2K
of the I/O page for system memory (see figure 2).
FIGURE 1
PROGRAM
PLUG
ON
DESCRIPTION
OUT
OFF
When holding board fingers down, program plugs positioned
to left are defined as "ON". Those positioned to right are
"OFF".
1-2
~
r-....
0---"
--
1
~~
L
1
-----ot=s
Pl8000
P11000
Pl6000
Pt500
18/22 BIT AlDESSING
P07 CD 0 18 BIT AlllESS
P070 CD 22 BIT AlllESS
BATT EAY BACKlP lPTION
PH CD 0 til BACKlP
PiO []DO
MOS MEMORY ARRAY
P090 00
PU CDO BACKlP
Pl00 []D
P090 00
....,
I
w
2K I/O PAGE lPTION
P080 CD tIAW. « I/O PAGI
P08 []D 0 2K I/O PAGE
MEMORY SIZE OPTION
P07 000
P06000
P05000
P04000
POlOOO
P02000
POl000
POOOOO
fl--
n-
PUOOO
Pl0000
P09000
P06 0
P05 0
P14000
PilOOO
P12000
P08000
IL-
r-
an
an
1MB
P06 0 an
P05 ano
5121<8
P06 ano
P05 []DO
2561<8
When any byte of data is written to Q-RAM 22(B) boards
which contain parity, a parity bit is generated which is
stored along with the byte of data in the memory array.
Whenever a byte of data is read the parity logic checks it
against the stored parity bit. If parity is bad, an error
has occurred and data is asumed to be bad.
In order to utilize the parity generation and checking
circuitry in the Q-RAM 22(B), a control and status register
is provided on board which is both hardware and software
compatible with LSI-II systems.
The control and status register is used to enable the
board to interrupt if an error has occurred, latch the
upper address bits of the location with bad data, set the
parity error flag on error, and force bad parity writing
for diagnostic purposes.
1.3
BACKPLANE PIN UTILIZATION
Table 2 contains backplane power pins required for
Q-RAM 22(B).
Table 3 designates pins used for other
signals.
Board finger designations shown in figure 2 are
equivalent to backplane pin designations.
Table-2
Backplane Power Pins Required
Voltage
~
BVl
+5 normal
M2
BA2
AT1
BTl
AC2
BC2
ground
+5 battery (if used)
+5 Battery spare
(if used)
1-4
AV1
AS1
AE1
Backplane I/O Signal Pins
Table-3
Signal
R.1.n
BDAL 16
BDAL 17
BDCOK H
BDAL 18
BDAL 19
BDAL 20
BDAL 21
BDOUT L
BRPLY L
BDlN L
BSYNC L
BWTBT L
BlAKl L
BIAKO L
BBS7 L
BDMGl L
BSMGO L
BDAL 00
BDAL 01
BDAL 02
BDAL 03
BDAL 04
BDAL 05
BDAL 06
BDAL 07
BDAL 08
BDAL 09
BDAL 10
BDAL 11
BDAL 12
BDAL 13
BDAL 14
BDAL 15
AC1
AD1
BAl
BC1
BD1
BEl
BF1
AE2
AF2
AH2
AJ2
AK2
AM2
AN2
AP2
AR2
AS2
AU2
AV2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2
1-5
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1.4
SPECIFICATIONS
CHARACTERISTICS
memory device type
read access time
write access time
memory cycle time
operating temperature
storage temperature
relative humidity
voltages required
battery backup voltage
+5V operating current
+5V standby current
+5V battery backup current
* optional spares available on backplane
1-6
SPECIFICATIONS
MOS dynamic RAM
(65,536 X 1)
200 ns type
50 ns type
450 type
0 to +65 C
-40 to +85 C
0 to 90% (non-condensing
+5V ±5% pins BUl,AA2,BA2
+5V +5% pins AVl,ASl*,AEl
2 amp type
2 amp type
.9 amp type
CHAPTER 2
HARDWARE INSPECTION, INSTALLATION,
AND CHECKOUT
2.1
INTRODUCTION
This chapter provides information for configuring the
Q-RAM 22(B) programmable plug options prior to system
installation followed
by
installation
and
checkout
procedures.
2.2
CONFIGURING THE Q-RAM 22(B) PROGRAM PLUGS
Figure 2 provides the locations of the various Q-RAM
22(B) option jumpers and Figure 1 illustrates how they are
used. The module should be inspected prior to installation
to assure that it has been properly configured. Sections
2.3 through 2.6 describe the various Q-RAM 22(B) program
plug options.
2.3
ADDRESSING OPTIONS
Q-RAM 22(B) addressing logic is capable of either 22
or 18 bit operation.
P7 is used to select the desired
addressing mode as follows:
18 Bit Address Mode
P7 - ON
22 Bit Address Mode
P7 - OFF
BDAL 18, BDAL 19, BDAL 20, and BDAL 21 are ignored if 18
bit addressing mode is selected and the board may not be
configured to respond to addresses above l28K.
The memory starting address may be programmed at any
64K boundary using jumpers PO through P4. Depending on the
size of the board, the memory will utilize up to 524,288
contiguous word addresses in the address space beginning at
2-1
the selected starting address. Q-RAM 22(B) board size
options are described in section 2-4.
To program the starting address of memory, BDAL 21
through BDAL 17 must be reflected by the following program
plug configurations:
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
BDAL
21
21
20
20
19
19
18
18
17
17
P4 ON
P4 OFF
P3 ON
P3 OFF
P2 ON
P2 OFF
PION
PI OFF
PO ON
PO OFF
I
0
I
0
1
0
1
0
1
0
Appendix A may be used to determine starting addresses
if the Q-RAM 22(B) is to placed over existing resident
memory.
Table 4 may be used as an illustration of the
above described formula.
Table 4 may also be used to
directly configure systems with multiple Q-RAM 22(B) 1 MB
boards.
Table-4
lllUl
.i.
1
2
3
4
Multiple Q-RAM 22(B) starting Addresses
fLUG
S~AB~ING ADDB~6S
A21 A2C A19 Ala All Alg A15
0
0
1
1
0
I
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P4
OFF
OFF
ON
ON
CQ~fIGllRAlIQ~S
fJ
f2
el
eQ
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
The BBS7 signal is used during the address portion of
a data transfer cycle on the Q-BUS. It indicates that the
bus master is requesting a data transfer with one of the
I/O devices in the 4K I/O page space. BBS7 is asserted
whenever an I/O ,page transfer is requested. The memory
board should ignore all transfers requested within the I/O
2-2
space. If, however, there are few peripherals on the
system and it is desired by the user to reserve only 2K of
the I/O page space,' plug P8 may be used as follow:
Normal 4K I/O Page
P8 - OFF
Reserve Only 2K I/O Page
P8 - ON
2.4
BOARD SIZE CONFIGURATION PLUGS
Plugs P5 and P6 are used to configure the board size.
Q-RAM 22(B) boards have up to eight rows of 65,536 X 1 bit
dynamic RAM devices with 18 devices per row. Each row will
accept 65,536 (64K) 18 bit words. A Q-RAM 22(B) may have
2, 4, or 8 rows of memory chips corresponding to l28K,
256K, or 5l2K words respectively. P5 and P6 must be
configured, as shown in Table 5, to match the size of the
memory array on board.
Table-5
2.5
Memory Size Jumpers
Board memory capacity
l28K words
256K words (1/2 MB)
5l2K words (1 MB)
P5
ON
ON
OFF
P6
ON
OFF
OFF
CSR OPTION PLUG CONFIGURATION
The parity control and status register (hereafter
referred to as CSR) has an I/O page address in the top 4K
of memory. 'This address may be anyone of eight specified
locations reserved by DEC for this purpose. Program plugs
P12, P13, and P14 are used to select one of the reserved
addresses. Table 6 illustrates the use of these plugs.
Note that each memory board used in a system must be
configured to a different address.
2-3
CSR Address Selection
Tab1e-6
P14
CSR Address
ON
772100
ON
772102
ON
772104
ON
772106
OFF
772110
OFF
772112
OFF
772114
OFF
772116
No CSR or Parity*
OUT
*To disable parity, remove P12, P13, and
2.6
P13
ON
ON
OFF
OFF
ON
ON
OFF
OFF
OUT
P14 plugs
P12
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OUT
BATTERY BACKUP OPTION PLUGS
The MOS memory, unlike core memory, requires the 5
volt supply to retain data. If the 5V power is removed
from the boa.rd, system memory data is lost.
The battery backup option is used if battery power is
available to maintain system memory data during power
failures. Battery backup 5V must be available on backplane
pin AVI. ASl or AEI may be used as an additional battery
backup 5V input
pin.
Table
7
shows the various
configurations of the battery backup mode select plugs P9,
PlO, and Pll.
Table-7
Battery Backup Mode Options
aatte[~ as~ku~ MQg~
No Backup
Battery Backup +5 AVI
(ASl, AEI unused)
Battery Backup +5 AVl,ASl
Battery Backup +5 AVl,AEl
2-4
.lll
ON
OFF
no..
n
ON
OFF
OUT
OUT
OFF
OFF
OFF
OFF
ON
OFF
2.7
INSTALLATION PROCEDURE
The following procedure should
Q-RAM 22(B) board is received.
be
followed
when a
1.
Visually inspect the module to make sure that
it has arrived in good condition.
2.
Set up
operation.
program
plug
options
for
required
3.
Verify that the required power connections
are available on the backplane (see Table 2).
4.
Power down the
system is powered
module.
system.
~ ~ that the
off before plugging in the
5.
Plug the module into the QBUS.
Memories
should be installed in sequential slots following
the cpu. ~ ~ that the module is not being
inserted backwards. The component side must face
in the same direction as other modules in the
system.
6.
Power up the system and run any DEC memory
diagnostic as an initial test. If available, use
the following diagnostics:
MAINDEC-ll CVMSA (22(B) bit system diagnostic)
MAINDEC-ll CZKMA (18 bit· system diagnostic)
2-5
CHAPTER 3
CSR DESCRIPTION
3.1 INTRODUCTION
When any byte is written to Q-RAM 22(B) boards with
parity option, a parity bit is generated which is stored
along with the byte of data in the memory array. Whenever
a byte of data is read, the parity logic checks it against
the stored parity bit. If parity is bad, an error has
occurred and data is assumed to be bad.
In order for software to utilize the parity generation
and checking circuitry in the Q-RAM 22(B), a control and
status register (CSR) is provided.
The CSR is assigned an address in the I/O page (see
Table 6) which may be accessed by software. When a parity
error is detected, the upper address bits of the bad memory
location (All to A21) are latched in the CSR. Control bits
are provided in the CSR to enable interrupt on error and
write of bad parity for diagnostic purposes.
3.2
CSR BIT ASSIGNMENT
The CSR is a 16 bit register located in the I/O page.
The function of the 16 bits in the CSR are as follows:
Bit 0
Parity error interrupt enable
If set to 1, the memory board will
interrupt the processor on error, by
setting bits BDAL 17 and BDAL 16 along
with the data bits BDAL 0 to BDAL 15.
This will result in an LSI-II processor
trap to location 114. BUSINIT clears
this bit.
3-1
Bit 1
Bit 2
UNUSED
Write wrong parity
If
this bit is set to 1, any word
or byte written to the array will be
stored along with an incorrect parity
bit.
This
is
for
maintenance
It enables didagnostics to
purposes.
check the boards ability to detect
parity
errors and interrupt
when
enabled. This bit is cleared by BUS
Bit 3
Bit 4
Bit 5 - 11
INIT.
UNUSED
UNUSED
Latch address bits
When a parity error is detected,
the upper address bits of the failing
location are latched. These bits are
not cleared by BUS INIT, but are
writeable, as well as readable.
When
an error is detected, address bits 11
to 21 are displayed in these bits.
Bit 12
Bit 13
Bit 14
Since there are only 7 bits and there
are 11 latched address bits, they are
multiplexed.
Bit
14 in the CSR
controls which of the latched address
bits are on display. (see Table 8).
UNUSED
UNUSED
Extended CSR read enable
(See Table 8.) This bit is used
to
multiplex the extended latched
address bits A18 to A2l into the CSR
bits 5 to 11. This bit is cleared by
BUS INIT.
Program plug P17 may be
used to disable setting of bit 14. If
plug P17 is on, CSR bit 14 is always
o.
3-2
Bit 15
Parity error flag
This bit is set if a parity error
is detected and remains set until
cleared by being written or by BUS
INIT.
Table-8
CSR Bits 5 to 11
CSB Bit
05
06
07
08
09
10
11
If CSB Bit l~-O
Latched All
Latched A12
Latched A13
Latched A14
Latched AIS
Latched A16
Latched A17
3-3
If CSB Bit
Latched
Latched
Latched
Latched
0
0
0
l~-l
A18
A19
A20
A21
APPENDIX A
MEMORY STARTING ADDRESS CHART
Statting
Resident mem'u::~
in K lrl~n:gs
Aggtea~
A21 A20 Al9 AlB Al1
OK
64K
128K (1/4 MB)
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
192K
0
0
0
1
1
2S6K (1/2 MB)
0
0
1
0
0
320K
384K (3/4 MB)
0
0
0
0
0
1
1
0
448K
S12K (1 MB)
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
S76K
640K (1 1/4 ME)
704K
768K (1 1/2 MB)
832K
896K (1 3/4 ME)
960K
0
0
1024K (2 MB)
~
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
0
If starting address is greater than 2MB, subtract 2MB
from the total. Set A21-l and use table to determine state
of lAS through A20 by finding remainder in table.
A-I
APPENDIX B
BANK SELECTION
The bank select feature designed into the Q-RAM 22(B)
products is used essentially to increase the available main
memory which is addressable in a Q-BUS* system. With
Clearpoint bank select memory, up to 32 megabytes may be
used in a
single
Q-BUS
system
with
no hardware
modifications required.
To enable the Q-RAM 22(B), bank selectability jumpers
P15, P16, P17, and PIS (see figure 2) are used. If all of
these jumpers are "out" (see figure 1), the bank select
feature is disabled. To use this feature, P16, P17, and
PIS must be installed. P15 may be installed as shown below
(see table).
Any board which has jumpers PIS, P17, and
P16
installed will respond to writes (DOUT cycles) to I/O page
CSR address 7775100 in one of the following two ways:
1.
If PIS is not installed, the board will latch
bank select bits provided by D5,D6, and D7 in
the word being written.
2.
If P16,P17, and PIS are all on (see figure 1)
and PIS is installed; the board will respond
with
BREPLY L to any write to address
177775100 and latch bank select bits from Ds,
D6, and D7 in the word being written.
Since 7775100 is a write only address the memory boards
will not respond to read (DIN cycles) using 7775100 at all.
To verify data being written into bits 5, 6, and 7 of
the bank select control status register, data written will
be displayed in bits 5 - 11 of the parity control status
register for each board.
*Q-BUS is a
Corporation.
registered trademark
B-1
of
Digital
Equipment
parity CSR
have
unique
Bank selectable boards
addresses as well. Boards which are not enabled for bank
select have registers as described in Table 6. Parity CSR
addressing
for boards configured for bank select is
described below.
Table 6
CSR Address Selection for Boards Enabled for Bank Select
CSR Address
P14
772120
ON
ON
772122
ON
772124
772126
ON
772130
OFF
772132
OFF
OFF
772134
772136
OFF
No CSR or Parity*
OUT
*Parity may not be disables for bank
P13
P12
ON
ON
OFF
ON
OFF
ON
OFF
OFF
ON
ON
ON
OFF
ON
ON
OFF
OFF
OUT
OUT
selectable boards.
All memory boards in the system must have a unique parity
CSR address. Parity must be enabled to use bank select.
The data bits written into CSR 7775100 bits 5, 6, and
7 select which page of memory will be accessible in bank
selectable address space and up to eight pages may be
available. The following table shows how jumpers P16, P17,
and PlS correspond to the selection bits written into
7775100.
B-2
Table-7
Page Selection Options
Bank Select
CSR
CSR
Eage
ait 2
ait 6
CSR
lti.t 5
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
0
0
0
1
6
1
1
1
1
0
7
1
1
1
5
B-3
~la
~12
~16
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
APPENDIX C
The Q-RAM 22B Block Mode DMA Memory Board
The Q-RAM 22B is designed to implement the block mode DMA
protocols on the Q-BUS.
Block Mode DMA reduces the
"handshaking"
necessary to transfer data and thereby
increases the transfer rate by a factor of nearly 2. From
the user's perspective there is no difference in the
operation or configuration of the Q-RAM 22B since the board
will operate transparently using whatever form of DMA is
invoked by other devices on the bus.
What is Block Mode DMA?
Under conventional direct memory access (DMA), direct data
transfers between I/O devices and memory occur one (16 bit)
word at a time or one byte at a time using DATI, DATa or
DATa (B) bus cycles. Under block mode DMA, the starting
address is followed not only by' data for that address, but
by data for up to 16 consecutive addresses. By eliminating
the assertion of the address for each data word, the
transfer rate is nearly doubled.
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The Q-RAM 22B can also be used in system configurations
with non-block mode DMA memory boards (either above or
below).
Most new Q-BUS peripheral controllers will be
supporting block mode protocols and take advantage of the
improved bus bandwidth using DATBI and DATBO type bus
cycles. For devices already designed that do not use these
block mode bus cycles, bus operation is unaffected.
For a complete technical description of these protocols,
refer to the 1983 PDP-II Micro/PDP-II Handbook published by
Digital Equipment Corporation.
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